From: Jani Nikula <jani.nikula@linux.intel.com>
To: "Ville Syrjälä" <ville.syrjala@linux.intel.com>,
"Lucas De Marchi" <lucas.demarchi@intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 2/2] drm/i915: fix placement of ICP_PP_CONTROL
Date: Mon, 04 Mar 2019 23:13:12 +0200 [thread overview]
Message-ID: <87va0ycphz.fsf@intel.com> (raw)
In-Reply-To: <20190304194807.GB16917@intel.com>
On Mon, 04 Mar 2019, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote:
> On Fri, Mar 01, 2019 at 05:14:05PM -0800, Lucas De Marchi wrote:
>> This register was placed in the middle of the PP_STATUS definition. Move
>> it down together with PP_CONTROL and fix the aligment of the bit
>> definition (as per documentation it should be 2 spaces instead of 1).
>>
>> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
>> ---
>> drivers/gpu/drm/i915/i915_reg.h | 22 +++++++++++-----------
>> 1 file changed, 11 insertions(+), 11 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>> index c9b868347481..bbbc0649a180 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -4692,17 +4692,6 @@ enum {
>> #define _PP_STATUS 0x61200
>> #define PP_STATUS(pps_idx) _MMIO_PPS(pps_idx, _PP_STATUS)
>> #define PP_ON (1 << 31)
>> -
>> -#define _PP_CONTROL_1 0xc7204
>> -#define _PP_CONTROL_2 0xc7304
>> -#define ICP_PP_CONTROL(x) _MMIO(((x) == 1) ? _PP_CONTROL_1 : \
>> - _PP_CONTROL_2)
>> -#define POWER_CYCLE_DELAY_MASK (0x1f << 4)
>> -#define POWER_CYCLE_DELAY_SHIFT 4
>> -#define VDD_OVERRIDE_FORCE (1 << 3)
>> -#define BACKLIGHT_ENABLE (1 << 2)
>> -#define PWR_DOWN_ON_RESET (1 << 1)
>> -#define PWR_STATE_TARGET (1 << 0)
>> /*
>> * Indicates that all dependencies of the panel are on:
>> *
>> @@ -4728,6 +4717,17 @@ enum {
>> #define PP_SEQUENCE_STATE_ON_S1_3 (0xb << 0)
>> #define PP_SEQUENCE_STATE_RESET (0xf << 0)
>>
>> +#define _PP_CONTROL_1 0xc7204
>> +#define _PP_CONTROL_2 0xc7304
>> +#define ICP_PP_CONTROL(x) _MMIO(((x) == 1) ? _PP_CONTROL_1 : \
>> + _PP_CONTROL_2)
>> +#define POWER_CYCLE_DELAY_MASK (0x1f << 4)
>> +#define POWER_CYCLE_DELAY_SHIFT 4
>> +#define VDD_OVERRIDE_FORCE (1 << 3)
>> +#define BACKLIGHT_ENABLE (1 << 2)
>> +#define PWR_DOWN_ON_RESET (1 << 1)
>> +#define PWR_STATE_TARGET (1 << 0)
>
> This entire register looks 100% redundant. Just nuke the whole thing?
Needed in the future?
BR,
Jani.
>
>> +
>> #define _PP_CONTROL 0x61204
>> #define PP_CONTROL(pps_idx) _MMIO_PPS(pps_idx, _PP_CONTROL)
>> #define PANEL_UNLOCK_REGS (0xabcd << 16)
>> --
>> 2.20.1
--
Jani Nikula, Intel Open Source Graphics Center
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next prev parent reply other threads:[~2019-03-04 21:11 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-03-02 1:14 [PATCH 1/2] drm/i915: Fix bit name in PP_STATUS register Lucas De Marchi
2019-03-02 1:14 ` [PATCH 2/2] drm/i915: fix placement of ICP_PP_CONTROL Lucas De Marchi
2019-03-04 19:48 ` Ville Syrjälä
2019-03-04 21:13 ` Jani Nikula [this message]
2019-03-05 13:23 ` Jani Nikula
2019-03-05 21:07 ` Lucas De Marchi
2019-03-06 13:19 ` Ville Syrjälä
2019-03-08 23:23 ` [PATCH v2] drm/i915: remove ICP_PP_CONTROL Lucas De Marchi
2020-01-02 23:44 ` [Intel-gfx] " Lucas De Marchi
2020-01-07 14:20 ` Ville Syrjälä
2019-03-02 2:08 ` ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/2] drm/i915: Fix bit name in PP_STATUS register Patchwork
2019-03-02 2:40 ` ✓ Fi.CI.BAT: success " Patchwork
2019-03-02 12:29 ` ✓ Fi.CI.IGT: " Patchwork
2019-03-04 19:43 ` [PATCH 1/2] " Ville Syrjälä
2019-03-09 0:21 ` ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915: Fix bit name in PP_STATUS register (rev2) Patchwork
2019-03-09 8:17 ` ✓ Fi.CI.IGT: " Patchwork
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