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From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: Lucas De Marchi <lucas.de.marchi@gmail.com>
Cc: Intel Graphics <intel-gfx@lists.freedesktop.org>,
	Lucas De Marchi <lucas.demarchi@intel.com>
Subject: Re: [Intel-gfx] [PATCH v2] drm/i915: remove ICP_PP_CONTROL
Date: Tue, 7 Jan 2020 16:20:45 +0200	[thread overview]
Message-ID: <20200107142045.GE1208@intel.com> (raw)
In-Reply-To: <CAKi4VAKSi1otf_R_D1mPEvCjR1+MRfhQ0NEc_-hJ298W=wdTRQ@mail.gmail.com>

On Thu, Jan 02, 2020 at 03:44:38PM -0800, Lucas De Marchi wrote:
> Today I saw this register and had a vague memory of having already
> removed it in the past.
> It seems this patch has never been reviewed/applied.
> 
> Ping

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

> 
> Lucas De Marchi
> 
> On Fri, Mar 8, 2019 at 3:23 PM Lucas De Marchi <lucas.demarchi@intel.com> wrote:
> >
> > This register was placed in the middle of the PP_STATUS definition
> > instead of together with the PP_CONTROL where it should. Since it's not
> > used and there are no current plans to use it, just remove the
> > definition.
> >
> > v2: remove the define rather than moving it.
> >
> > Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> > ---
> >  drivers/gpu/drm/i915/i915_reg.h | 11 -----------
> >  1 file changed, 11 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index c0cd7a836799..4a855befa838 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -4692,17 +4692,6 @@ enum {
> >  #define _PP_STATUS                     0x61200
> >  #define PP_STATUS(pps_idx)             _MMIO_PPS(pps_idx, _PP_STATUS)
> >  #define   PP_ON                                (1 << 31)
> > -
> > -#define _PP_CONTROL_1                  0xc7204
> > -#define _PP_CONTROL_2                  0xc7304
> > -#define ICP_PP_CONTROL(x)              _MMIO(((x) == 1) ? _PP_CONTROL_1 : \
> > -                                             _PP_CONTROL_2)
> > -#define  POWER_CYCLE_DELAY_MASK        (0x1f << 4)
> > -#define  POWER_CYCLE_DELAY_SHIFT       4
> > -#define  VDD_OVERRIDE_FORCE            (1 << 3)
> > -#define  BACKLIGHT_ENABLE              (1 << 2)
> > -#define  PWR_DOWN_ON_RESET             (1 << 1)
> > -#define  PWR_STATE_TARGET              (1 << 0)
> >  /*
> >   * Indicates that all dependencies of the panel are on:
> >   *
> > --
> > 2.20.1
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 
> 
> 
> -- 
> Lucas De Marchi

-- 
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

  reply	other threads:[~2020-01-07 14:20 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-03-02  1:14 [PATCH 1/2] drm/i915: Fix bit name in PP_STATUS register Lucas De Marchi
2019-03-02  1:14 ` [PATCH 2/2] drm/i915: fix placement of ICP_PP_CONTROL Lucas De Marchi
2019-03-04 19:48   ` Ville Syrjälä
2019-03-04 21:13     ` Jani Nikula
2019-03-05 13:23       ` Jani Nikula
2019-03-05 21:07         ` Lucas De Marchi
2019-03-06 13:19           ` Ville Syrjälä
2019-03-08 23:23             ` [PATCH v2] drm/i915: remove ICP_PP_CONTROL Lucas De Marchi
2020-01-02 23:44               ` [Intel-gfx] " Lucas De Marchi
2020-01-07 14:20                 ` Ville Syrjälä [this message]
2019-03-02  2:08 ` ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/2] drm/i915: Fix bit name in PP_STATUS register Patchwork
2019-03-02  2:40 ` ✓ Fi.CI.BAT: success " Patchwork
2019-03-02 12:29 ` ✓ Fi.CI.IGT: " Patchwork
2019-03-04 19:43 ` [PATCH 1/2] " Ville Syrjälä
2019-03-09  0:21 ` ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915: Fix bit name in PP_STATUS register (rev2) Patchwork
2019-03-09  8:17 ` ✓ Fi.CI.IGT: " Patchwork

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