* [PATCH] drm/i915/icl: Fix DSS_CTL register names
@ 2018-11-01 21:06 Anusha Srivatsa
2018-11-01 21:26 ` ✗ Fi.CI.CHECKPATCH: warning for " Patchwork
` (2 more replies)
0 siblings, 3 replies; 9+ messages in thread
From: Anusha Srivatsa @ 2018-11-01 21:06 UTC (permalink / raw)
To: intel-gfx; +Cc: Jani Nikula
This patch fixes the naming of the registers:
s/PIPE_DSS_CTL/ICL_PIPE_DSS_CTL
And also fix the hex values to lower case, to match
rest of the definitions.
Manasi noticed this with the patch that was merged.
Fixes - 8b1b558d690aa (drm/i915/icl: Add DSS_CTL Registers)
Suggested-by: Manasi Navare <manasi.d.navare@intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 22 +++++++++++-----------
1 file changed, 11 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index aef1a30ff9f6..c0e6e14fe9fa 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -10050,7 +10050,7 @@ enum skl_power_gate {
#define OVERLAP_PIXELS(pixels) ((pixels) << 16)
#define LEFT_DL_BUF_TARGET_DEPTH_MASK (0xfff << 0)
#define LEFT_DL_BUF_TARGET_DEPTH(pixels) ((pixels) << 0)
-#define MAX_DL_BUFFER_TARGET_DEPTH 0x5A0
+#define MAX_DL_BUFFER_TARGET_DEPTH 0x5a0
#define DSS_CTL2 _MMIO(0x67404)
#define LEFT_BRANCH_VDSC_ENABLE (1 << 31)
@@ -10058,20 +10058,20 @@ enum skl_power_gate {
#define RIGHT_DL_BUF_TARGET_DEPTH_MASK (0xfff << 0)
#define RIGHT_DL_BUF_TARGET_DEPTH(pixels) ((pixels) << 0)
-#define _PIPE_DSS_CTL1_PB 0x78200
-#define _PIPE_DSS_CTL1_PC 0x78400
-#define PIPE_DSS_CTL1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
- _PIPE_DSS_CTL1_PB, \
- _PIPE_DSS_CTL1_PC)
+#define _ICL_PIPE_DSS_CTL1_PB 0x78200
+#define _ICL_PIPE_DSS_CTL1_PC 0x78400
+#define ICL_PIPE_DSS_CTL1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
+ _ICL_PIPE_DSS_CTL1_PB, \
+ _ICL_PIPE_DSS_CTL1_PC)
#define BIG_JOINER_ENABLE (1 << 29)
#define MASTER_BIG_JOINER_ENABLE (1 << 28)
#define VGA_CENTERING_ENABLE (1 << 27)
-#define _PIPE_DSS_CTL2_PB 0x78204
-#define _PIPE_DSS_CTL2_PC 0x78404
-#define PIPE_DSS_CTL2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
- _PIPE_DSS_CTL2_PB, \
- _PIPE_DSS_CTL2_PC)
+#define _ICL_PIPE_DSS_CTL2_PB 0x78204
+#define _ICL_PIPE_DSS_CTL2_PC 0x78404
+#define ICL_PIPE_DSS_CTL2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
+ _ICL_PIPE_DSS_CTL2_PB, \
+ _ICL_PIPE_DSS_CTL2_PC)
#define BXT_P_DSI_REGULATOR_CFG _MMIO(0x160020)
#define STAP_SELECT (1 << 0)
--
2.17.1
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^ permalink raw reply related [flat|nested] 9+ messages in thread
* ✗ Fi.CI.CHECKPATCH: warning for drm/i915/icl: Fix DSS_CTL register names
2018-11-01 21:06 [PATCH] drm/i915/icl: Fix DSS_CTL register names Anusha Srivatsa
@ 2018-11-01 21:26 ` Patchwork
2018-11-01 21:28 ` [PATCH] " Manasi Navare
2018-11-01 21:50 ` ✓ Fi.CI.BAT: success for " Patchwork
2 siblings, 0 replies; 9+ messages in thread
From: Patchwork @ 2018-11-01 21:26 UTC (permalink / raw)
To: Anusha Srivatsa; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/icl: Fix DSS_CTL register names
URL : https://patchwork.freedesktop.org/series/51901/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
4ffedc790c0f drm/i915/icl: Fix DSS_CTL register names
-:15: ERROR:GIT_COMMIT_ID: Please use git commit description style 'commit <12+ chars of sha1> ("<title line>")' - ie: 'commit 8b1b558d690a ("drm/i915/icl: Add DSS_CTL Registers")'
#15:
Fixes - 8b1b558d690aa (drm/i915/icl: Add DSS_CTL Registers)
total: 1 errors, 0 warnings, 0 checks, 38 lines checked
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH] drm/i915/icl: Fix DSS_CTL register names
2018-11-01 21:06 [PATCH] drm/i915/icl: Fix DSS_CTL register names Anusha Srivatsa
2018-11-01 21:26 ` ✗ Fi.CI.CHECKPATCH: warning for " Patchwork
@ 2018-11-01 21:28 ` Manasi Navare
2018-11-02 7:33 ` Jani Nikula
2018-11-01 21:50 ` ✓ Fi.CI.BAT: success for " Patchwork
2 siblings, 1 reply; 9+ messages in thread
From: Manasi Navare @ 2018-11-01 21:28 UTC (permalink / raw)
To: Anusha Srivatsa; +Cc: Jani Nikula, intel-gfx
On Thu, Nov 01, 2018 at 02:06:43PM -0700, Anusha Srivatsa wrote:
> This patch fixes the naming of the registers:
>
> s/PIPE_DSS_CTL/ICL_PIPE_DSS_CTL
>
> And also fix the hex values to lower case, to match
> rest of the definitions.
>
> Manasi noticed this with the patch that was merged.
>
> Fixes - 8b1b558d690aa (drm/i915/icl: Add DSS_CTL Registers)
This is not the way Fixes tag is used, not sure if the scripts will pick this.
The right way is:
Fixes: commit SHA 1st 12 letters ("commit title")
Eg:
Fixes: 57692c94dcbe ("drm/v3d: Introduce a new DRM driver for Broadcom V3D V3.x+")
Manasi
> Suggested-by: Manasi Navare <manasi.d.navare@intel.com>
> Cc: Jani Nikula <jani.nikula@intel.com>
> Cc: Manasi Navare <manasi.d.navare@intel.com>
> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 22 +++++++++++-----------
> 1 file changed, 11 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index aef1a30ff9f6..c0e6e14fe9fa 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -10050,7 +10050,7 @@ enum skl_power_gate {
> #define OVERLAP_PIXELS(pixels) ((pixels) << 16)
> #define LEFT_DL_BUF_TARGET_DEPTH_MASK (0xfff << 0)
> #define LEFT_DL_BUF_TARGET_DEPTH(pixels) ((pixels) << 0)
> -#define MAX_DL_BUFFER_TARGET_DEPTH 0x5A0
> +#define MAX_DL_BUFFER_TARGET_DEPTH 0x5a0
>
> #define DSS_CTL2 _MMIO(0x67404)
> #define LEFT_BRANCH_VDSC_ENABLE (1 << 31)
> @@ -10058,20 +10058,20 @@ enum skl_power_gate {
> #define RIGHT_DL_BUF_TARGET_DEPTH_MASK (0xfff << 0)
> #define RIGHT_DL_BUF_TARGET_DEPTH(pixels) ((pixels) << 0)
>
> -#define _PIPE_DSS_CTL1_PB 0x78200
> -#define _PIPE_DSS_CTL1_PC 0x78400
> -#define PIPE_DSS_CTL1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> - _PIPE_DSS_CTL1_PB, \
> - _PIPE_DSS_CTL1_PC)
> +#define _ICL_PIPE_DSS_CTL1_PB 0x78200
> +#define _ICL_PIPE_DSS_CTL1_PC 0x78400
> +#define ICL_PIPE_DSS_CTL1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> + _ICL_PIPE_DSS_CTL1_PB, \
> + _ICL_PIPE_DSS_CTL1_PC)
> #define BIG_JOINER_ENABLE (1 << 29)
> #define MASTER_BIG_JOINER_ENABLE (1 << 28)
> #define VGA_CENTERING_ENABLE (1 << 27)
>
> -#define _PIPE_DSS_CTL2_PB 0x78204
> -#define _PIPE_DSS_CTL2_PC 0x78404
> -#define PIPE_DSS_CTL2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> - _PIPE_DSS_CTL2_PB, \
> - _PIPE_DSS_CTL2_PC)
> +#define _ICL_PIPE_DSS_CTL2_PB 0x78204
> +#define _ICL_PIPE_DSS_CTL2_PC 0x78404
> +#define ICL_PIPE_DSS_CTL2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> + _ICL_PIPE_DSS_CTL2_PB, \
> + _ICL_PIPE_DSS_CTL2_PC)
>
> #define BXT_P_DSI_REGULATOR_CFG _MMIO(0x160020)
> #define STAP_SELECT (1 << 0)
> --
> 2.17.1
>
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 9+ messages in thread
* ✓ Fi.CI.BAT: success for drm/i915/icl: Fix DSS_CTL register names
2018-11-01 21:06 [PATCH] drm/i915/icl: Fix DSS_CTL register names Anusha Srivatsa
2018-11-01 21:26 ` ✗ Fi.CI.CHECKPATCH: warning for " Patchwork
2018-11-01 21:28 ` [PATCH] " Manasi Navare
@ 2018-11-01 21:50 ` Patchwork
2 siblings, 0 replies; 9+ messages in thread
From: Patchwork @ 2018-11-01 21:50 UTC (permalink / raw)
To: Anusha Srivatsa; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/icl: Fix DSS_CTL register names
URL : https://patchwork.freedesktop.org/series/51901/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5070 -> Patchwork_10699 =
== Summary - SUCCESS ==
No regressions found.
External URL: https://patchwork.freedesktop.org/api/1.0/series/51901/revisions/1/mbox/
== Known issues ==
Here are the changes found in Patchwork_10699 that come from known issues:
=== IGT changes ===
==== Issues hit ====
igt@drv_selftest@live_contexts:
fi-icl-u: NOTRUN -> INCOMPLETE (fdo#108315)
igt@gem_exec_suspend@basic-s3:
fi-kbl-soraka: NOTRUN -> INCOMPLETE (fdo#107859, fdo#107556, fdo#107774)
igt@gem_exec_suspend@basic-s4-devices:
fi-blb-e6850: PASS -> INCOMPLETE (fdo#107718)
igt@kms_flip@basic-flip-vs-modeset:
fi-skl-6700hq: PASS -> DMESG-WARN (fdo#105998)
igt@kms_frontbuffer_tracking@basic:
fi-hsw-peppy: PASS -> DMESG-WARN (fdo#102614)
igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a:
fi-byt-clapper: PASS -> FAIL (fdo#107362)
igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
fi-byt-clapper: PASS -> FAIL (fdo#107362, fdo#103191)
==== Possible fixes ====
igt@drv_selftest@live_evict:
fi-bsw-kefka: DMESG-WARN (fdo#107709) -> PASS
igt@drv_selftest@live_hangcheck:
fi-kbl-7560u: INCOMPLETE (fdo#108044) -> PASS
igt@gem_mmap_gtt@basic-small-bo:
fi-glk-dsi: INCOMPLETE (k.org#198133, fdo#103359) -> PASS
igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c:
fi-icl-u: INCOMPLETE (fdo#107713) -> PASS
fdo#102614 https://bugs.freedesktop.org/show_bug.cgi?id=102614
fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191
fdo#103359 https://bugs.freedesktop.org/show_bug.cgi?id=103359
fdo#105998 https://bugs.freedesktop.org/show_bug.cgi?id=105998
fdo#107362 https://bugs.freedesktop.org/show_bug.cgi?id=107362
fdo#107556 https://bugs.freedesktop.org/show_bug.cgi?id=107556
fdo#107709 https://bugs.freedesktop.org/show_bug.cgi?id=107709
fdo#107713 https://bugs.freedesktop.org/show_bug.cgi?id=107713
fdo#107718 https://bugs.freedesktop.org/show_bug.cgi?id=107718
fdo#107774 https://bugs.freedesktop.org/show_bug.cgi?id=107774
fdo#107859 https://bugs.freedesktop.org/show_bug.cgi?id=107859
fdo#108044 https://bugs.freedesktop.org/show_bug.cgi?id=108044
fdo#108315 https://bugs.freedesktop.org/show_bug.cgi?id=108315
k.org#198133 https://bugzilla.kernel.org/show_bug.cgi?id=198133
== Participating hosts (45 -> 41) ==
Additional (1): fi-kbl-soraka
Missing (5): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-apl-guc
== Build changes ==
* Linux: CI_DRM_5070 -> Patchwork_10699
CI_DRM_5070: db4461d736dcee952c0cdededcbcbed7de3ddb69 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_4704: ace031dcb1e8bf2b32b4b0d54a55eb30e8f41d6f @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_10699: 4ffedc790c0f7295350255770cd0cf361ae076e6 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
4ffedc790c0f drm/i915/icl: Fix DSS_CTL register names
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10699/issues.html
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH] drm/i915/icl: Fix DSS_CTL register names
2018-11-01 21:28 ` [PATCH] " Manasi Navare
@ 2018-11-02 7:33 ` Jani Nikula
0 siblings, 0 replies; 9+ messages in thread
From: Jani Nikula @ 2018-11-02 7:33 UTC (permalink / raw)
To: Manasi Navare, Anusha Srivatsa; +Cc: intel-gfx
On Thu, 01 Nov 2018, Manasi Navare <manasi.d.navare@intel.com> wrote:
> On Thu, Nov 01, 2018 at 02:06:43PM -0700, Anusha Srivatsa wrote:
>> This patch fixes the naming of the registers:
>>
>> s/PIPE_DSS_CTL/ICL_PIPE_DSS_CTL
>>
>> And also fix the hex values to lower case, to match
>> rest of the definitions.
>>
>> Manasi noticed this with the patch that was merged.
>>
>> Fixes - 8b1b558d690aa (drm/i915/icl: Add DSS_CTL Registers)
>
> This is not the way Fixes tag is used, not sure if the scripts will pick this.
> The right way is:
>
> Fixes: commit SHA 1st 12 letters ("commit title")
> Eg:
> Fixes: 57692c94dcbe ("drm/v3d: Introduce a new DRM driver for Broadcom V3D V3.x+")
The 'dim fixes' command will give you everything and check for need for
cc: stable etc.
BR,
Jani.
>
> Manasi
>
>> Suggested-by: Manasi Navare <manasi.d.navare@intel.com>
>> Cc: Jani Nikula <jani.nikula@intel.com>
>> Cc: Manasi Navare <manasi.d.navare@intel.com>
>> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
>> ---
>> drivers/gpu/drm/i915/i915_reg.h | 22 +++++++++++-----------
>> 1 file changed, 11 insertions(+), 11 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>> index aef1a30ff9f6..c0e6e14fe9fa 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -10050,7 +10050,7 @@ enum skl_power_gate {
>> #define OVERLAP_PIXELS(pixels) ((pixels) << 16)
>> #define LEFT_DL_BUF_TARGET_DEPTH_MASK (0xfff << 0)
>> #define LEFT_DL_BUF_TARGET_DEPTH(pixels) ((pixels) << 0)
>> -#define MAX_DL_BUFFER_TARGET_DEPTH 0x5A0
>> +#define MAX_DL_BUFFER_TARGET_DEPTH 0x5a0
>>
>> #define DSS_CTL2 _MMIO(0x67404)
>> #define LEFT_BRANCH_VDSC_ENABLE (1 << 31)
>> @@ -10058,20 +10058,20 @@ enum skl_power_gate {
>> #define RIGHT_DL_BUF_TARGET_DEPTH_MASK (0xfff << 0)
>> #define RIGHT_DL_BUF_TARGET_DEPTH(pixels) ((pixels) << 0)
>>
>> -#define _PIPE_DSS_CTL1_PB 0x78200
>> -#define _PIPE_DSS_CTL1_PC 0x78400
>> -#define PIPE_DSS_CTL1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
>> - _PIPE_DSS_CTL1_PB, \
>> - _PIPE_DSS_CTL1_PC)
>> +#define _ICL_PIPE_DSS_CTL1_PB 0x78200
>> +#define _ICL_PIPE_DSS_CTL1_PC 0x78400
>> +#define ICL_PIPE_DSS_CTL1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
>> + _ICL_PIPE_DSS_CTL1_PB, \
>> + _ICL_PIPE_DSS_CTL1_PC)
>> #define BIG_JOINER_ENABLE (1 << 29)
>> #define MASTER_BIG_JOINER_ENABLE (1 << 28)
>> #define VGA_CENTERING_ENABLE (1 << 27)
>>
>> -#define _PIPE_DSS_CTL2_PB 0x78204
>> -#define _PIPE_DSS_CTL2_PC 0x78404
>> -#define PIPE_DSS_CTL2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
>> - _PIPE_DSS_CTL2_PB, \
>> - _PIPE_DSS_CTL2_PC)
>> +#define _ICL_PIPE_DSS_CTL2_PB 0x78204
>> +#define _ICL_PIPE_DSS_CTL2_PC 0x78404
>> +#define ICL_PIPE_DSS_CTL2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
>> + _ICL_PIPE_DSS_CTL2_PB, \
>> + _ICL_PIPE_DSS_CTL2_PC)
>>
>> #define BXT_P_DSI_REGULATOR_CFG _MMIO(0x160020)
>> #define STAP_SELECT (1 << 0)
>> --
>> 2.17.1
>>
--
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH] drm/i915/icl: Fix DSS_CTL register names
2018-11-02 5:08 ` Manasi Navare
@ 2018-11-02 7:14 ` Jani Nikula
0 siblings, 0 replies; 9+ messages in thread
From: Jani Nikula @ 2018-11-02 7:14 UTC (permalink / raw)
To: Manasi Navare, Anusha Srivatsa; +Cc: intel-gfx
On Thu, 01 Nov 2018, Manasi Navare <manasi.d.navare@intel.com> wrote:
> Pushed to the dinq, thanks for the patch.
Thanks, sorry for the trouble.
BR,
Jani.
>
> Manasi
>
> On Thu, Nov 01, 2018 at 02:55:18PM -0700, Manasi Navare wrote:
>> On Thu, Nov 01, 2018 at 02:42:16PM -0700, Anusha Srivatsa wrote:
>> > This patch fixes the naming of the registers:
>> >
>> > s/PIPE_DSS_CTL/ICL_PIPE_DSS_CTL
>> >
>> > And also fix the hex values to lower case, to match
>> > rest of the definitions.
>> >
>> > Manasi noticed this with the patch that was merged.
>> >
>> > v2: fix "Fixes" tag.
>> >
>> > Fixes: 8b1b558d690a ("drm/i915/icl: Add DSS_CTL Registers")
>> > Suggested-by: Manasi Navare <manasi.d.navare@intel.com>
>> > Cc: Jani Nikula <jani.nikula@intel.com>
>> > Cc: Manasi Navare <manasi.d.navare@intel.com>
>> > Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
>>
>> Looks good.
>>
>> Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
>>
>> Manasi
>>
>> > ---
>> > drivers/gpu/drm/i915/i915_reg.h | 22 +++++++++++-----------
>> > 1 file changed, 11 insertions(+), 11 deletions(-)
>> >
>> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>> > index aef1a30ff9f6..c0e6e14fe9fa 100644
>> > --- a/drivers/gpu/drm/i915/i915_reg.h
>> > +++ b/drivers/gpu/drm/i915/i915_reg.h
>> > @@ -10050,7 +10050,7 @@ enum skl_power_gate {
>> > #define OVERLAP_PIXELS(pixels) ((pixels) << 16)
>> > #define LEFT_DL_BUF_TARGET_DEPTH_MASK (0xfff << 0)
>> > #define LEFT_DL_BUF_TARGET_DEPTH(pixels) ((pixels) << 0)
>> > -#define MAX_DL_BUFFER_TARGET_DEPTH 0x5A0
>> > +#define MAX_DL_BUFFER_TARGET_DEPTH 0x5a0
>> >
>> > #define DSS_CTL2 _MMIO(0x67404)
>> > #define LEFT_BRANCH_VDSC_ENABLE (1 << 31)
>> > @@ -10058,20 +10058,20 @@ enum skl_power_gate {
>> > #define RIGHT_DL_BUF_TARGET_DEPTH_MASK (0xfff << 0)
>> > #define RIGHT_DL_BUF_TARGET_DEPTH(pixels) ((pixels) << 0)
>> >
>> > -#define _PIPE_DSS_CTL1_PB 0x78200
>> > -#define _PIPE_DSS_CTL1_PC 0x78400
>> > -#define PIPE_DSS_CTL1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
>> > - _PIPE_DSS_CTL1_PB, \
>> > - _PIPE_DSS_CTL1_PC)
>> > +#define _ICL_PIPE_DSS_CTL1_PB 0x78200
>> > +#define _ICL_PIPE_DSS_CTL1_PC 0x78400
>> > +#define ICL_PIPE_DSS_CTL1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
>> > + _ICL_PIPE_DSS_CTL1_PB, \
>> > + _ICL_PIPE_DSS_CTL1_PC)
>> > #define BIG_JOINER_ENABLE (1 << 29)
>> > #define MASTER_BIG_JOINER_ENABLE (1 << 28)
>> > #define VGA_CENTERING_ENABLE (1 << 27)
>> >
>> > -#define _PIPE_DSS_CTL2_PB 0x78204
>> > -#define _PIPE_DSS_CTL2_PC 0x78404
>> > -#define PIPE_DSS_CTL2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
>> > - _PIPE_DSS_CTL2_PB, \
>> > - _PIPE_DSS_CTL2_PC)
>> > +#define _ICL_PIPE_DSS_CTL2_PB 0x78204
>> > +#define _ICL_PIPE_DSS_CTL2_PC 0x78404
>> > +#define ICL_PIPE_DSS_CTL2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
>> > + _ICL_PIPE_DSS_CTL2_PB, \
>> > + _ICL_PIPE_DSS_CTL2_PC)
>> >
>> > #define BXT_P_DSI_REGULATOR_CFG _MMIO(0x160020)
>> > #define STAP_SELECT (1 << 0)
>> > --
>> > 2.17.1
>> >
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH] drm/i915/icl: Fix DSS_CTL register names
2018-11-01 21:55 ` Manasi Navare
@ 2018-11-02 5:08 ` Manasi Navare
2018-11-02 7:14 ` Jani Nikula
0 siblings, 1 reply; 9+ messages in thread
From: Manasi Navare @ 2018-11-02 5:08 UTC (permalink / raw)
To: Anusha Srivatsa; +Cc: Jani Nikula, intel-gfx
Pushed to the dinq, thanks for the patch.
Manasi
On Thu, Nov 01, 2018 at 02:55:18PM -0700, Manasi Navare wrote:
> On Thu, Nov 01, 2018 at 02:42:16PM -0700, Anusha Srivatsa wrote:
> > This patch fixes the naming of the registers:
> >
> > s/PIPE_DSS_CTL/ICL_PIPE_DSS_CTL
> >
> > And also fix the hex values to lower case, to match
> > rest of the definitions.
> >
> > Manasi noticed this with the patch that was merged.
> >
> > v2: fix "Fixes" tag.
> >
> > Fixes: 8b1b558d690a ("drm/i915/icl: Add DSS_CTL Registers")
> > Suggested-by: Manasi Navare <manasi.d.navare@intel.com>
> > Cc: Jani Nikula <jani.nikula@intel.com>
> > Cc: Manasi Navare <manasi.d.navare@intel.com>
> > Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
>
> Looks good.
>
> Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
>
> Manasi
>
> > ---
> > drivers/gpu/drm/i915/i915_reg.h | 22 +++++++++++-----------
> > 1 file changed, 11 insertions(+), 11 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index aef1a30ff9f6..c0e6e14fe9fa 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -10050,7 +10050,7 @@ enum skl_power_gate {
> > #define OVERLAP_PIXELS(pixels) ((pixels) << 16)
> > #define LEFT_DL_BUF_TARGET_DEPTH_MASK (0xfff << 0)
> > #define LEFT_DL_BUF_TARGET_DEPTH(pixels) ((pixels) << 0)
> > -#define MAX_DL_BUFFER_TARGET_DEPTH 0x5A0
> > +#define MAX_DL_BUFFER_TARGET_DEPTH 0x5a0
> >
> > #define DSS_CTL2 _MMIO(0x67404)
> > #define LEFT_BRANCH_VDSC_ENABLE (1 << 31)
> > @@ -10058,20 +10058,20 @@ enum skl_power_gate {
> > #define RIGHT_DL_BUF_TARGET_DEPTH_MASK (0xfff << 0)
> > #define RIGHT_DL_BUF_TARGET_DEPTH(pixels) ((pixels) << 0)
> >
> > -#define _PIPE_DSS_CTL1_PB 0x78200
> > -#define _PIPE_DSS_CTL1_PC 0x78400
> > -#define PIPE_DSS_CTL1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> > - _PIPE_DSS_CTL1_PB, \
> > - _PIPE_DSS_CTL1_PC)
> > +#define _ICL_PIPE_DSS_CTL1_PB 0x78200
> > +#define _ICL_PIPE_DSS_CTL1_PC 0x78400
> > +#define ICL_PIPE_DSS_CTL1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> > + _ICL_PIPE_DSS_CTL1_PB, \
> > + _ICL_PIPE_DSS_CTL1_PC)
> > #define BIG_JOINER_ENABLE (1 << 29)
> > #define MASTER_BIG_JOINER_ENABLE (1 << 28)
> > #define VGA_CENTERING_ENABLE (1 << 27)
> >
> > -#define _PIPE_DSS_CTL2_PB 0x78204
> > -#define _PIPE_DSS_CTL2_PC 0x78404
> > -#define PIPE_DSS_CTL2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> > - _PIPE_DSS_CTL2_PB, \
> > - _PIPE_DSS_CTL2_PC)
> > +#define _ICL_PIPE_DSS_CTL2_PB 0x78204
> > +#define _ICL_PIPE_DSS_CTL2_PC 0x78404
> > +#define ICL_PIPE_DSS_CTL2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> > + _ICL_PIPE_DSS_CTL2_PB, \
> > + _ICL_PIPE_DSS_CTL2_PC)
> >
> > #define BXT_P_DSI_REGULATOR_CFG _MMIO(0x160020)
> > #define STAP_SELECT (1 << 0)
> > --
> > 2.17.1
> >
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH] drm/i915/icl: Fix DSS_CTL register names
2018-11-01 21:42 [PATCH] " Anusha Srivatsa
@ 2018-11-01 21:55 ` Manasi Navare
2018-11-02 5:08 ` Manasi Navare
0 siblings, 1 reply; 9+ messages in thread
From: Manasi Navare @ 2018-11-01 21:55 UTC (permalink / raw)
To: Anusha Srivatsa; +Cc: Jani Nikula, intel-gfx
On Thu, Nov 01, 2018 at 02:42:16PM -0700, Anusha Srivatsa wrote:
> This patch fixes the naming of the registers:
>
> s/PIPE_DSS_CTL/ICL_PIPE_DSS_CTL
>
> And also fix the hex values to lower case, to match
> rest of the definitions.
>
> Manasi noticed this with the patch that was merged.
>
> v2: fix "Fixes" tag.
>
> Fixes: 8b1b558d690a ("drm/i915/icl: Add DSS_CTL Registers")
> Suggested-by: Manasi Navare <manasi.d.navare@intel.com>
> Cc: Jani Nikula <jani.nikula@intel.com>
> Cc: Manasi Navare <manasi.d.navare@intel.com>
> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Looks good.
Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
Manasi
> ---
> drivers/gpu/drm/i915/i915_reg.h | 22 +++++++++++-----------
> 1 file changed, 11 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index aef1a30ff9f6..c0e6e14fe9fa 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -10050,7 +10050,7 @@ enum skl_power_gate {
> #define OVERLAP_PIXELS(pixels) ((pixels) << 16)
> #define LEFT_DL_BUF_TARGET_DEPTH_MASK (0xfff << 0)
> #define LEFT_DL_BUF_TARGET_DEPTH(pixels) ((pixels) << 0)
> -#define MAX_DL_BUFFER_TARGET_DEPTH 0x5A0
> +#define MAX_DL_BUFFER_TARGET_DEPTH 0x5a0
>
> #define DSS_CTL2 _MMIO(0x67404)
> #define LEFT_BRANCH_VDSC_ENABLE (1 << 31)
> @@ -10058,20 +10058,20 @@ enum skl_power_gate {
> #define RIGHT_DL_BUF_TARGET_DEPTH_MASK (0xfff << 0)
> #define RIGHT_DL_BUF_TARGET_DEPTH(pixels) ((pixels) << 0)
>
> -#define _PIPE_DSS_CTL1_PB 0x78200
> -#define _PIPE_DSS_CTL1_PC 0x78400
> -#define PIPE_DSS_CTL1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> - _PIPE_DSS_CTL1_PB, \
> - _PIPE_DSS_CTL1_PC)
> +#define _ICL_PIPE_DSS_CTL1_PB 0x78200
> +#define _ICL_PIPE_DSS_CTL1_PC 0x78400
> +#define ICL_PIPE_DSS_CTL1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> + _ICL_PIPE_DSS_CTL1_PB, \
> + _ICL_PIPE_DSS_CTL1_PC)
> #define BIG_JOINER_ENABLE (1 << 29)
> #define MASTER_BIG_JOINER_ENABLE (1 << 28)
> #define VGA_CENTERING_ENABLE (1 << 27)
>
> -#define _PIPE_DSS_CTL2_PB 0x78204
> -#define _PIPE_DSS_CTL2_PC 0x78404
> -#define PIPE_DSS_CTL2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> - _PIPE_DSS_CTL2_PB, \
> - _PIPE_DSS_CTL2_PC)
> +#define _ICL_PIPE_DSS_CTL2_PB 0x78204
> +#define _ICL_PIPE_DSS_CTL2_PC 0x78404
> +#define ICL_PIPE_DSS_CTL2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> + _ICL_PIPE_DSS_CTL2_PB, \
> + _ICL_PIPE_DSS_CTL2_PC)
>
> #define BXT_P_DSI_REGULATOR_CFG _MMIO(0x160020)
> #define STAP_SELECT (1 << 0)
> --
> 2.17.1
>
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH] drm/i915/icl: Fix DSS_CTL register names
@ 2018-11-01 21:42 Anusha Srivatsa
2018-11-01 21:55 ` Manasi Navare
0 siblings, 1 reply; 9+ messages in thread
From: Anusha Srivatsa @ 2018-11-01 21:42 UTC (permalink / raw)
To: intel-gfx; +Cc: Jani Nikula
This patch fixes the naming of the registers:
s/PIPE_DSS_CTL/ICL_PIPE_DSS_CTL
And also fix the hex values to lower case, to match
rest of the definitions.
Manasi noticed this with the patch that was merged.
v2: fix "Fixes" tag.
Fixes: 8b1b558d690a ("drm/i915/icl: Add DSS_CTL Registers")
Suggested-by: Manasi Navare <manasi.d.navare@intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 22 +++++++++++-----------
1 file changed, 11 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index aef1a30ff9f6..c0e6e14fe9fa 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -10050,7 +10050,7 @@ enum skl_power_gate {
#define OVERLAP_PIXELS(pixels) ((pixels) << 16)
#define LEFT_DL_BUF_TARGET_DEPTH_MASK (0xfff << 0)
#define LEFT_DL_BUF_TARGET_DEPTH(pixels) ((pixels) << 0)
-#define MAX_DL_BUFFER_TARGET_DEPTH 0x5A0
+#define MAX_DL_BUFFER_TARGET_DEPTH 0x5a0
#define DSS_CTL2 _MMIO(0x67404)
#define LEFT_BRANCH_VDSC_ENABLE (1 << 31)
@@ -10058,20 +10058,20 @@ enum skl_power_gate {
#define RIGHT_DL_BUF_TARGET_DEPTH_MASK (0xfff << 0)
#define RIGHT_DL_BUF_TARGET_DEPTH(pixels) ((pixels) << 0)
-#define _PIPE_DSS_CTL1_PB 0x78200
-#define _PIPE_DSS_CTL1_PC 0x78400
-#define PIPE_DSS_CTL1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
- _PIPE_DSS_CTL1_PB, \
- _PIPE_DSS_CTL1_PC)
+#define _ICL_PIPE_DSS_CTL1_PB 0x78200
+#define _ICL_PIPE_DSS_CTL1_PC 0x78400
+#define ICL_PIPE_DSS_CTL1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
+ _ICL_PIPE_DSS_CTL1_PB, \
+ _ICL_PIPE_DSS_CTL1_PC)
#define BIG_JOINER_ENABLE (1 << 29)
#define MASTER_BIG_JOINER_ENABLE (1 << 28)
#define VGA_CENTERING_ENABLE (1 << 27)
-#define _PIPE_DSS_CTL2_PB 0x78204
-#define _PIPE_DSS_CTL2_PC 0x78404
-#define PIPE_DSS_CTL2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
- _PIPE_DSS_CTL2_PB, \
- _PIPE_DSS_CTL2_PC)
+#define _ICL_PIPE_DSS_CTL2_PB 0x78204
+#define _ICL_PIPE_DSS_CTL2_PC 0x78404
+#define ICL_PIPE_DSS_CTL2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
+ _ICL_PIPE_DSS_CTL2_PB, \
+ _ICL_PIPE_DSS_CTL2_PC)
#define BXT_P_DSI_REGULATOR_CFG _MMIO(0x160020)
#define STAP_SELECT (1 << 0)
--
2.17.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 9+ messages in thread
end of thread, other threads:[~2018-11-02 7:32 UTC | newest]
Thread overview: 9+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2018-11-01 21:06 [PATCH] drm/i915/icl: Fix DSS_CTL register names Anusha Srivatsa
2018-11-01 21:26 ` ✗ Fi.CI.CHECKPATCH: warning for " Patchwork
2018-11-01 21:28 ` [PATCH] " Manasi Navare
2018-11-02 7:33 ` Jani Nikula
2018-11-01 21:50 ` ✓ Fi.CI.BAT: success for " Patchwork
2018-11-01 21:42 [PATCH] " Anusha Srivatsa
2018-11-01 21:55 ` Manasi Navare
2018-11-02 5:08 ` Manasi Navare
2018-11-02 7:14 ` Jani Nikula
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