[v1] Basic Radix Tree cleanups

[v1] Basic Radix Tree cleanups

[Balbir Singh]

This patch cleans up some bits of the radix tree implementation
no functionality changes were introduced. Most of them were based
on review comments. I've lightly tested the patches and checked
for correctness of code generation for the .long instruction change
bits. Please review

[PATCH 1/2] Fix .long's in mm/tlb-radix.c to more meaningful

[Balbir Singh]

The .longs with the shifts are harder to read, use more
meaningful names for the opcodes. PPC_TLBIE_5 is introduced
for the 5 opcode variation of the instruction due to an existing
op-code for the 2 opcode variant

Signed-off-by: Balbir Singh <bsingharora@gmail.com>
---
 arch/powerpc/include/asm/ppc-opcode.h | 14 ++++++++++++++
 arch/powerpc/mm/tlb-radix.c           | 13 +++++--------
 2 files changed, 19 insertions(+), 8 deletions(-)

diff --git a/arch/powerpc/include/asm/ppc-opcode.h b/arch/powerpc/include/asm/ppc-opcode.h
index 1d035c1..c0e9ea4 100644
--- a/arch/powerpc/include/asm/ppc-opcode.h
+++ b/arch/powerpc/include/asm/ppc-opcode.h
@@ -184,6 +184,7 @@
 #define PPC_INST_STSWX			0x7c00052a
 #define PPC_INST_STXVD2X		0x7c000798
 #define PPC_INST_TLBIE			0x7c000264
+#define PPC_INST_TLBIEL			0x7c000224
 #define PPC_INST_TLBILX			0x7c000024
 #define PPC_INST_WAIT			0x7c00007c
 #define PPC_INST_TLBIVAX		0x7c000624
@@ -257,6 +258,9 @@
 #define ___PPC_RB(b)	(((b) & 0x1f) << 11)
 #define ___PPC_RS(s)	(((s) & 0x1f) << 21)
 #define ___PPC_RT(t)	___PPC_RS(t)
+#define ___PPC_R(r)	(((r) & 0x1) << 16)
+#define ___PPC_PRS(prs)	(((prs) & 0x1) << 17)
+#define ___PPC_RIC(ric)	(((ric) & 0x3) << 18)
 #define __PPC_RA(a)	___PPC_RA(__REG_##a)
 #define __PPC_RA0(a)	___PPC_RA(__REGA0_##a)
 #define __PPC_RB(b)	___PPC_RB(__REG_##b)
@@ -321,6 +325,16 @@
 					__PPC_WC(w))
 #define PPC_TLBIE(lp,a) 	stringify_in_c(.long PPC_INST_TLBIE | \
 					       ___PPC_RB(a) | ___PPC_RS(lp))
+#define	PPC_TLBIE_5(rb,rs,ric,prs,r) \
+				stringify_in_c(.long PPC_INST_TLBIE | \
+					___PPC_RB(rb) | ___PPC_RS(rs) | \
+					___PPC_RIC(ric) | ___PPC_PRS(prs) | \
+					___PPC_R(r))
+#define	PPC_TLBIEL(rb,rs,ric,prs,r) \
+				stringify_in_c(.long PPC_INST_TLBIEL | \
+					___PPC_RB(rb) | ___PPC_RS(rs) | \
+					___PPC_RIC(ric) | ___PPC_PRS(prs) | \
+					___PPC_R(r))
 #define PPC_TLBSRX_DOT(a,b)	stringify_in_c(.long PPC_INST_TLBSRX_DOT | \
 					__PPC_RA0(a) | __PPC_RB(b))
 #define PPC_TLBIVAX(a,b)	stringify_in_c(.long PPC_INST_TLBIVAX | \
diff --git a/arch/powerpc/mm/tlb-radix.c b/arch/powerpc/mm/tlb-radix.c
index 0fdaf93..e6b7487 100644
--- a/arch/powerpc/mm/tlb-radix.c
+++ b/arch/powerpc/mm/tlb-radix.c
@@ -12,6 +12,7 @@
 #include <linux/mm.h>
 #include <linux/hugetlb.h>
 #include <linux/memblock.h>
+#include <asm/ppc-opcode.h>
 
 #include <asm/tlb.h>
 #include <asm/tlbflush.h>
@@ -30,8 +31,7 @@ static inline void __tlbiel_pid(unsigned long pid, int set)
 	ric = 2;  /* invalidate all the caches */
 
 	asm volatile("ptesync": : :"memory");
-	asm volatile(".long 0x7c000224 | (%0 << 11) | (%1 << 16) |"
-		     "(%2 << 17) | (%3 << 18) | (%4 << 21)"
+	asm volatile(PPC_TLBIEL(%0, %4, %3, %2, %1)
 		     : : "r"(rb), "i"(r), "i"(prs), "i"(ric), "r"(rs) : "memory");
 	asm volatile("ptesync": : :"memory");
 }
@@ -60,8 +60,7 @@ static inline void _tlbie_pid(unsigned long pid)
 	ric = 2;  /* invalidate all the caches */
 
 	asm volatile("ptesync": : :"memory");
-	asm volatile(".long 0x7c000264 | (%0 << 11) | (%1 << 16) |"
-		     "(%2 << 17) | (%3 << 18) | (%4 << 21)"
+	asm volatile(PPC_TLBIE_5(%0, %4, %3, %2, %1)
 		     : : "r"(rb), "i"(r), "i"(prs), "i"(ric), "r"(rs) : "memory");
 	asm volatile("eieio; tlbsync; ptesync": : :"memory");
 }
@@ -79,8 +78,7 @@ static inline void _tlbiel_va(unsigned long va, unsigned long pid,
 	ric = 0;  /* no cluster flush yet */
 
 	asm volatile("ptesync": : :"memory");
-	asm volatile(".long 0x7c000224 | (%0 << 11) | (%1 << 16) |"
-		     "(%2 << 17) | (%3 << 18) | (%4 << 21)"
+	asm volatile(PPC_TLBIEL(%0, %4, %3, %2, %1)
 		     : : "r"(rb), "i"(r), "i"(prs), "i"(ric), "r"(rs) : "memory");
 	asm volatile("ptesync": : :"memory");
 }
@@ -98,8 +96,7 @@ static inline void _tlbie_va(unsigned long va, unsigned long pid,
 	ric = 0;  /* no cluster flush yet */
 
 	asm volatile("ptesync": : :"memory");
-	asm volatile(".long 0x7c000264 | (%0 << 11) | (%1 << 16) |"
-		     "(%2 << 17) | (%3 << 18) | (%4 << 21)"
+	asm volatile(PPC_TLBIE_5(%0, %4, %3, %2, %1)
 		     : : "r"(rb), "i"(r), "i"(prs), "i"(ric), "r"(rs) : "memory");
 	asm volatile("eieio; tlbsync; ptesync": : :"memory");
 }
-- 
2.5.5

[PATCH 2/2] Deduplicate the actual base page size code

[Balbir Singh]

Deduplicate to one function to compute the actual page size.
Some additional warnings added for AP size as well.

Signed-off-by: Balbir Singh <bsingharora@gmail.com>
---
 arch/powerpc/mm/hugetlbpage-radix.c | 31 ++++++++++++++++---------------
 1 file changed, 16 insertions(+), 15 deletions(-)

diff --git a/arch/powerpc/mm/hugetlbpage-radix.c b/arch/powerpc/mm/hugetlbpage-radix.c
index 1e11559..9108645 100644
--- a/arch/powerpc/mm/hugetlbpage-radix.c
+++ b/arch/powerpc/mm/hugetlbpage-radix.c
@@ -6,7 +6,8 @@
 #include <asm/machdep.h>
 #include <asm/mman.h>
 
-void radix__flush_hugetlb_page(struct vm_area_struct *vma, unsigned long vmaddr)
+static inline unsigned long get_base_page_size(struct vm_area_struct *vma,
+					       unsigned long vmaddr)
 {
 	unsigned long ap, shift;
 	struct hstate *hstate = hstate_file(vma->vm_file);
@@ -18,25 +19,25 @@ void radix__flush_hugetlb_page(struct vm_area_struct *vma, unsigned long vmaddr)
 		ap = mmu_get_ap(MMU_PAGE_1G);
 	else {
 		WARN(1, "Wrong huge page shift\n");
-		return ;
+		return 0;
 	}
-	radix___flush_tlb_page(vma->vm_mm, vmaddr, ap, 0);
+#ifdef CONFIG_DEBUG_VM
+	/* Double check this assumption */
+	WARN_ON(ap != 0 && ap != 0x5);
+#endif
+	return ap;
 }
 
-void radix__local_flush_hugetlb_page(struct vm_area_struct *vma, unsigned long vmaddr)
+void radix__flush_hugetlb_page(struct vm_area_struct *vma, unsigned long vmaddr)
 {
-	unsigned long ap, shift;
-	struct hstate *hstate = hstate_file(vma->vm_file);
+	unsigned long ap = get_base_page_size(vma, vmaddr);
+	radix___flush_tlb_page(vma->vm_mm, vmaddr, ap, 0);
+}
 
-	shift = huge_page_shift(hstate);
-	if (shift == mmu_psize_defs[MMU_PAGE_2M].shift)
-		ap = mmu_get_ap(MMU_PAGE_2M);
-	else if (shift == mmu_psize_defs[MMU_PAGE_1G].shift)
-		ap = mmu_get_ap(MMU_PAGE_1G);
-	else {
-		WARN(1, "Wrong huge page shift\n");
-		return ;
-	}
+void radix__local_flush_hugetlb_page(struct vm_area_struct *vma,
+				     unsigned long vmaddr)
+{
+	unsigned long ap = get_base_page_size(vma, vmaddr);
 	radix___local_flush_tlb_page(vma->vm_mm, vmaddr, ap, 0);
 }
 
-- 
2.5.5

Re: [PATCH 2/2] Deduplicate the actual base page size code

[Aneesh Kumar K.V]

Balbir Singh <bsingharora@gmail.com> writes:

> Deduplicate to one function to compute the actual page size.
> Some additional warnings added for AP size as well.


This is getting chaned in a cleanup series I am testing before posting. 
The change from ap to psize need more update in commit message. 

commit 701e0d3dc33c93a97b825f403d58f6be99b89203
Author: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
Date:   Tue May 10 11:33:15 2016 +0530

    powerpc/mm/radix/hugetlb: Add helper for finding page size from hstate
    
    Use the helper instead of open coding the same at multiple place
    
    Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>

diff --git a/arch/powerpc/include/asm/book3s/64/hugetlb-radix.h b/arch/powerpc/include/asm/book3s/64/hugetlb-radix.h
index 60f47649306f..c45189aa7476 100644
--- a/arch/powerpc/include/asm/book3s/64/hugetlb-radix.h
+++ b/arch/powerpc/include/asm/book3s/64/hugetlb-radix.h
@@ -11,4 +11,19 @@ extern unsigned long
 radix__hugetlb_get_unmapped_area(struct file *file, unsigned long addr,
 				unsigned long len, unsigned long pgoff,
 				unsigned long flags);
+
+static inline int hstate_get_psize(struct hstate *hstate)
+{
+	unsigned long shift;
+
+	shift = huge_page_shift(hstate);
+	if (shift == mmu_psize_defs[MMU_PAGE_2M].shift)
+		return MMU_PAGE_2M;
+	else if (shift == mmu_psize_defs[MMU_PAGE_1G].shift)
+		return MMU_PAGE_1G;
+	else {
+		WARN(1, "Wrong huge page shift\n");
+		return mmu_virtual_psize;
+	}
+}
 #endif
diff --git a/arch/powerpc/include/asm/book3s/64/tlbflush-radix.h b/arch/powerpc/include/asm/book3s/64/tlbflush-radix.h
index 07b2e0031dad..68839e6adcf1 100644
--- a/arch/powerpc/include/asm/book3s/64/tlbflush-radix.h
+++ b/arch/powerpc/include/asm/book3s/64/tlbflush-radix.h
@@ -21,13 +21,13 @@ extern void radix__flush_tlb_kernel_range(unsigned long start, unsigned long end
 extern void radix__local_flush_tlb_mm(struct mm_struct *mm);
 extern void radix__local_flush_tlb_page(struct vm_area_struct *vma, unsigned long vmaddr);
 extern void radix__local_flush_tlb_page_psize(struct mm_struct *mm, unsigned long vmaddr,
-					      unsigned long ap);
+					      int psize);
 extern void radix__tlb_flush(struct mmu_gather *tlb);
 #ifdef CONFIG_SMP
 extern void radix__flush_tlb_mm(struct mm_struct *mm);
 extern void radix__flush_tlb_page(struct vm_area_struct *vma, unsigned long vmaddr);
 extern void radix__flush_tlb_page_psize(struct mm_struct *mm, unsigned long vmaddr,
-					unsigned long ap);
+					int psize);
 #else
 #define radix__flush_tlb_mm(mm)		radix__local_flush_tlb_mm(mm)
 #define radix__flush_tlb_page(vma,addr)	radix__local_flush_tlb_page(vma,addr)
diff --git a/arch/powerpc/mm/hugetlbpage-radix.c b/arch/powerpc/mm/hugetlbpage-radix.c
index 0dfa1816f0c6..1eca0deaf89b 100644
--- a/arch/powerpc/mm/hugetlbpage-radix.c
+++ b/arch/powerpc/mm/hugetlbpage-radix.c
@@ -5,39 +5,24 @@
 #include <asm/cacheflush.h>
 #include <asm/machdep.h>
 #include <asm/mman.h>
+#include <asm/tlb.h>
 
 void radix__flush_hugetlb_page(struct vm_area_struct *vma, unsigned long vmaddr)
 {
-	unsigned long ap, shift;
+	int psize;
 	struct hstate *hstate = hstate_file(vma->vm_file);
 
-	shift = huge_page_shift(hstate);
-	if (shift == mmu_psize_defs[MMU_PAGE_2M].shift)
-		ap = mmu_get_ap(MMU_PAGE_2M);
-	else if (shift == mmu_psize_defs[MMU_PAGE_1G].shift)
-		ap = mmu_get_ap(MMU_PAGE_1G);
-	else {
-		WARN(1, "Wrong huge page shift\n");
-		return ;
-	}
-	radix__flush_tlb_page_psize(vma->vm_mm, vmaddr, ap);
+	psize = hstate_get_psize(hstate);
+	radix__flush_tlb_page_psize(vma->vm_mm, vmaddr, psize);
 }
 
 void radix__local_flush_hugetlb_page(struct vm_area_struct *vma, unsigned long vmaddr)
 {
-	unsigned long ap, shift;
+	int psize;
 	struct hstate *hstate = hstate_file(vma->vm_file);
 
-	shift = huge_page_shift(hstate);
-	if (shift == mmu_psize_defs[MMU_PAGE_2M].shift)
-		ap = mmu_get_ap(MMU_PAGE_2M);
-	else if (shift == mmu_psize_defs[MMU_PAGE_1G].shift)
-		ap = mmu_get_ap(MMU_PAGE_1G);
-	else {
-		WARN(1, "Wrong huge page shift\n");
-		return ;
-	}
-	radix__local_flush_tlb_page_psize(vma->vm_mm, vmaddr, ap);
+	psize = hstate_get_psize(hstate);
+	radix__local_flush_tlb_page_psize(vma->vm_mm, vmaddr, psize);
 }
 
 /*
diff --git a/arch/powerpc/mm/tlb-radix.c b/arch/powerpc/mm/tlb-radix.c
index b1dc4675925d..7bc3d1402c63 100644
--- a/arch/powerpc/mm/tlb-radix.c
+++ b/arch/powerpc/mm/tlb-radix.c
@@ -128,9 +128,10 @@ void radix__local_flush_tlb_mm(struct mm_struct *mm)
 EXPORT_SYMBOL(radix__local_flush_tlb_mm);
 
 void radix__local_flush_tlb_page_psize(struct mm_struct *mm, unsigned long vmaddr,
-				       unsigned long ap)
+				       int psize)
 {
 	unsigned int pid;
+	unsigned long ap = mmu_get_ap(psize);
 
 	preempt_disable();
 	pid = mm ? mm->context.id : 0;
@@ -147,7 +148,7 @@ void radix__local_flush_tlb_page(struct vm_area_struct *vma, unsigned long vmadd
 		return __local_flush_hugetlb_page(vma, vmaddr);
 #endif
 	radix__local_flush_tlb_page_psize(vma ? vma->vm_mm : NULL, vmaddr,
-					  mmu_get_ap(mmu_virtual_psize));
+					  mmu_virtual_psize);
 }
 EXPORT_SYMBOL(radix__local_flush_tlb_page);
 
@@ -177,9 +178,10 @@ no_context:
 EXPORT_SYMBOL(radix__flush_tlb_mm);
 
 void radix__flush_tlb_page_psize(struct mm_struct *mm, unsigned long vmaddr,
-				 unsigned long ap)
+				 int psize)
 {
 	unsigned int pid;
+	unsigned long ap = mmu_get_ap(psize);
 
 	preempt_disable();
 	pid = mm ? mm->context.id : 0;
@@ -206,7 +208,7 @@ void radix__flush_tlb_page(struct vm_area_struct *vma, unsigned long vmaddr)
 		return flush_hugetlb_page(vma, vmaddr);
 #endif
 	radix__flush_tlb_page_psize(vma ? vma->vm_mm : NULL, vmaddr,
-				    mmu_get_ap(mmu_virtual_psize));
+				    mmu_virtual_psize);
 }
 EXPORT_SYMBOL(radix__flush_tlb_page);
 

Re: [PATCH 1/2] Fix .long's in mm/tlb-radix.c to more meaningful

[Aneesh Kumar K.V]

Balbir Singh <bsingharora@gmail.com> writes:

> The .longs with the shifts are harder to read, use more
> meaningful names for the opcodes. PPC_TLBIE_5 is introduced
> for the 5 opcode variation of the instruction due to an existing
> op-code for the 2 opcode variant
>
> Signed-off-by: Balbir Singh <bsingharora@gmail.com>

Reviewed-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>

> ---
>  arch/powerpc/include/asm/ppc-opcode.h | 14 ++++++++++++++
>  arch/powerpc/mm/tlb-radix.c           | 13 +++++--------
>  2 files changed, 19 insertions(+), 8 deletions(-)
>
> diff --git a/arch/powerpc/include/asm/ppc-opcode.h b/arch/powerpc/include/asm/ppc-opcode.h
> index 1d035c1..c0e9ea4 100644
> --- a/arch/powerpc/include/asm/ppc-opcode.h
> +++ b/arch/powerpc/include/asm/ppc-opcode.h
> @@ -184,6 +184,7 @@
>  #define PPC_INST_STSWX			0x7c00052a
>  #define PPC_INST_STXVD2X		0x7c000798
>  #define PPC_INST_TLBIE			0x7c000264
> +#define PPC_INST_TLBIEL			0x7c000224
>  #define PPC_INST_TLBILX			0x7c000024
>  #define PPC_INST_WAIT			0x7c00007c
>  #define PPC_INST_TLBIVAX		0x7c000624
> @@ -257,6 +258,9 @@
>  #define ___PPC_RB(b)	(((b) & 0x1f) << 11)
>  #define ___PPC_RS(s)	(((s) & 0x1f) << 21)
>  #define ___PPC_RT(t)	___PPC_RS(t)
> +#define ___PPC_R(r)	(((r) & 0x1) << 16)
> +#define ___PPC_PRS(prs)	(((prs) & 0x1) << 17)
> +#define ___PPC_RIC(ric)	(((ric) & 0x3) << 18)
>  #define __PPC_RA(a)	___PPC_RA(__REG_##a)
>  #define __PPC_RA0(a)	___PPC_RA(__REGA0_##a)
>  #define __PPC_RB(b)	___PPC_RB(__REG_##b)
> @@ -321,6 +325,16 @@
>  					__PPC_WC(w))
>  #define PPC_TLBIE(lp,a) 	stringify_in_c(.long PPC_INST_TLBIE | \
>  					       ___PPC_RB(a) | ___PPC_RS(lp))
> +#define	PPC_TLBIE_5(rb,rs,ric,prs,r) \
> +				stringify_in_c(.long PPC_INST_TLBIE | \
> +					___PPC_RB(rb) | ___PPC_RS(rs) | \
> +					___PPC_RIC(ric) | ___PPC_PRS(prs) | \
> +					___PPC_R(r))
> +#define	PPC_TLBIEL(rb,rs,ric,prs,r) \
> +				stringify_in_c(.long PPC_INST_TLBIEL | \
> +					___PPC_RB(rb) | ___PPC_RS(rs) | \
> +					___PPC_RIC(ric) | ___PPC_PRS(prs) | \
> +					___PPC_R(r))
>  #define PPC_TLBSRX_DOT(a,b)	stringify_in_c(.long PPC_INST_TLBSRX_DOT | \
>  					__PPC_RA0(a) | __PPC_RB(b))
>  #define PPC_TLBIVAX(a,b)	stringify_in_c(.long PPC_INST_TLBIVAX | \
> diff --git a/arch/powerpc/mm/tlb-radix.c b/arch/powerpc/mm/tlb-radix.c
> index 0fdaf93..e6b7487 100644
> --- a/arch/powerpc/mm/tlb-radix.c
> +++ b/arch/powerpc/mm/tlb-radix.c
> @@ -12,6 +12,7 @@
>  #include <linux/mm.h>
>  #include <linux/hugetlb.h>
>  #include <linux/memblock.h>
> +#include <asm/ppc-opcode.h>
>
>  #include <asm/tlb.h>
>  #include <asm/tlbflush.h>
> @@ -30,8 +31,7 @@ static inline void __tlbiel_pid(unsigned long pid, int set)
>  	ric = 2;  /* invalidate all the caches */
>
>  	asm volatile("ptesync": : :"memory");
> -	asm volatile(".long 0x7c000224 | (%0 << 11) | (%1 << 16) |"
> -		     "(%2 << 17) | (%3 << 18) | (%4 << 21)"
> +	asm volatile(PPC_TLBIEL(%0, %4, %3, %2, %1)
>  		     : : "r"(rb), "i"(r), "i"(prs), "i"(ric), "r"(rs) : "memory");
>  	asm volatile("ptesync": : :"memory");
>  }
> @@ -60,8 +60,7 @@ static inline void _tlbie_pid(unsigned long pid)
>  	ric = 2;  /* invalidate all the caches */
>
>  	asm volatile("ptesync": : :"memory");
> -	asm volatile(".long 0x7c000264 | (%0 << 11) | (%1 << 16) |"
> -		     "(%2 << 17) | (%3 << 18) | (%4 << 21)"
> +	asm volatile(PPC_TLBIE_5(%0, %4, %3, %2, %1)
>  		     : : "r"(rb), "i"(r), "i"(prs), "i"(ric), "r"(rs) : "memory");
>  	asm volatile("eieio; tlbsync; ptesync": : :"memory");
>  }
> @@ -79,8 +78,7 @@ static inline void _tlbiel_va(unsigned long va, unsigned long pid,
>  	ric = 0;  /* no cluster flush yet */
>
>  	asm volatile("ptesync": : :"memory");
> -	asm volatile(".long 0x7c000224 | (%0 << 11) | (%1 << 16) |"
> -		     "(%2 << 17) | (%3 << 18) | (%4 << 21)"
> +	asm volatile(PPC_TLBIEL(%0, %4, %3, %2, %1)
>  		     : : "r"(rb), "i"(r), "i"(prs), "i"(ric), "r"(rs) : "memory");
>  	asm volatile("ptesync": : :"memory");
>  }
> @@ -98,8 +96,7 @@ static inline void _tlbie_va(unsigned long va, unsigned long pid,
>  	ric = 0;  /* no cluster flush yet */
>
>  	asm volatile("ptesync": : :"memory");
> -	asm volatile(".long 0x7c000264 | (%0 << 11) | (%1 << 16) |"
> -		     "(%2 << 17) | (%3 << 18) | (%4 << 21)"
> +	asm volatile(PPC_TLBIE_5(%0, %4, %3, %2, %1)
>  		     : : "r"(rb), "i"(r), "i"(prs), "i"(ric), "r"(rs) : "memory");
>  	asm volatile("eieio; tlbsync; ptesync": : :"memory");
>  }
> -- 
> 2.5.5

Re: [PATCH 2/2] Deduplicate the actual base page size code

[Balbir Singh]

On 11/05/16 04:09, Aneesh Kumar K.V wrote:
> Balbir Singh <bsingharora@gmail.com> writes:
> 
>> Deduplicate to one function to compute the actual page size.
>> Some additional warnings added for AP size as well.
> 
> 
> This is getting chaned in a cleanup series I am testing before posting. 
> The change from ap to psize need more update in commit message. 
> 
> commit 701e0d3dc33c93a97b825f403d58f6be99b89203
> Author: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
> Date:   Tue May 10 11:33:15 2016 +0530
> 
>     powerpc/mm/radix/hugetlb: Add helper for finding page size from hstate
>     
>     Use the helper instead of open coding the same at multiple place
>     
>     Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>

This version makes more sense. While we are at it, mind replacing psize with base_psize and asserting
that base_psize is always 0 or 5.

Balbir Singh.

Re: [PATCH 2/2] Deduplicate the actual base page size code

[Aneesh Kumar K.V]

Balbir Singh <bsingharora@gmail.com> writes:

> On 11/05/16 04:09, Aneesh Kumar K.V wrote:
>> Balbir Singh <bsingharora@gmail.com> writes:
>> 
>>> Deduplicate to one function to compute the actual page size.
>>> Some additional warnings added for AP size as well.
>> 
>> 
>> This is getting chaned in a cleanup series I am testing before posting. 
>> The change from ap to psize need more update in commit message. 
>> 
>> commit 701e0d3dc33c93a97b825f403d58f6be99b89203
>> Author: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
>> Date:   Tue May 10 11:33:15 2016 +0530
>> 
>>     powerpc/mm/radix/hugetlb: Add helper for finding page size from hstate
>>     
>>     Use the helper instead of open coding the same at multiple place
>>     
>>     Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
>
> This version makes more sense. While we are at it, mind replacing psize with base_psize and asserting
> that base_psize is always 0 or 5.
>

With radix config there is no base/actual page size. The new function is
returning MMU_PAGE_* values and not the AP encoding.

-aneesh