* [PATCH v7 0/4] Enable second DBuf slice for ICL and TGL
@ 2019-11-29 13:37 ` Stanislav Lisovskiy
0 siblings, 0 replies; 26+ messages in thread
From: Stanislav Lisovskiy @ 2019-11-29 13:37 UTC (permalink / raw)
To: intel-gfx
Those patch series, do some initial preparation DBuf manipulating code
cleanups, i.e remove redundant structures/code, switch to mask
based DBuf manupulation, get into use DBuf assignment according to
BSpec rules.
Stanislav Lisovskiy (4):
drm/i915: Remove skl_ddl_allocation struct
drm/i915: Move dbuf slice update to proper place
drm/i915: Manipulate DBuf slices properly
drm/i915: Correctly map DBUF slices to pipes
drivers/gpu/drm/i915/display/intel_display.c | 53 ++--
.../drm/i915/display/intel_display_power.c | 100 +++---
.../drm/i915/display/intel_display_power.h | 5 +
.../drm/i915/display/intel_display_types.h | 3 +
drivers/gpu/drm/i915/i915_drv.h | 7 +-
drivers/gpu/drm/i915/i915_pci.c | 6 +-
drivers/gpu/drm/i915/intel_device_info.h | 1 +
drivers/gpu/drm/i915/intel_pm.c | 289 ++++++++++++++----
drivers/gpu/drm/i915/intel_pm.h | 6 +-
9 files changed, 333 insertions(+), 137 deletions(-)
--
2.17.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 26+ messages in thread
* [Intel-gfx] [PATCH v7 0/4] Enable second DBuf slice for ICL and TGL
@ 2019-11-29 13:37 ` Stanislav Lisovskiy
0 siblings, 0 replies; 26+ messages in thread
From: Stanislav Lisovskiy @ 2019-11-29 13:37 UTC (permalink / raw)
To: intel-gfx
Those patch series, do some initial preparation DBuf manipulating code
cleanups, i.e remove redundant structures/code, switch to mask
based DBuf manupulation, get into use DBuf assignment according to
BSpec rules.
Stanislav Lisovskiy (4):
drm/i915: Remove skl_ddl_allocation struct
drm/i915: Move dbuf slice update to proper place
drm/i915: Manipulate DBuf slices properly
drm/i915: Correctly map DBUF slices to pipes
drivers/gpu/drm/i915/display/intel_display.c | 53 ++--
.../drm/i915/display/intel_display_power.c | 100 +++---
.../drm/i915/display/intel_display_power.h | 5 +
.../drm/i915/display/intel_display_types.h | 3 +
drivers/gpu/drm/i915/i915_drv.h | 7 +-
drivers/gpu/drm/i915/i915_pci.c | 6 +-
drivers/gpu/drm/i915/intel_device_info.h | 1 +
drivers/gpu/drm/i915/intel_pm.c | 289 ++++++++++++++----
drivers/gpu/drm/i915/intel_pm.h | 6 +-
9 files changed, 333 insertions(+), 137 deletions(-)
--
2.17.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 26+ messages in thread
* [PATCH v7 1/4] drm/i915: Remove skl_ddl_allocation struct
@ 2019-11-29 13:37 ` Stanislav Lisovskiy
0 siblings, 0 replies; 26+ messages in thread
From: Stanislav Lisovskiy @ 2019-11-29 13:37 UTC (permalink / raw)
To: intel-gfx
Current consensus that it is redundant as
we already have skl_ddb_values struct out there,
also this struct contains only single member
which makes it unnecessary.
v2: As dirty_pipes soon going to be nuked away
from skl_ddb_values, evacuating enabled_slices
to safer in dev_priv.
Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 16 ++++-----
.../drm/i915/display/intel_display_power.c | 8 ++---
.../drm/i915/display/intel_display_types.h | 3 ++
drivers/gpu/drm/i915/i915_drv.h | 7 ++--
drivers/gpu/drm/i915/intel_pm.c | 34 ++++++++-----------
drivers/gpu/drm/i915/intel_pm.h | 6 ++--
6 files changed, 34 insertions(+), 40 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 53dc310a5f6d..dda43e3dcdbf 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -13393,14 +13393,13 @@ static void verify_wm_state(struct intel_crtc *crtc,
struct skl_hw_state {
struct skl_ddb_entry ddb_y[I915_MAX_PLANES];
struct skl_ddb_entry ddb_uv[I915_MAX_PLANES];
- struct skl_ddb_allocation ddb;
struct skl_pipe_wm wm;
} *hw;
- struct skl_ddb_allocation *sw_ddb;
struct skl_pipe_wm *sw_wm;
struct skl_ddb_entry *hw_ddb_entry, *sw_ddb_entry;
const enum pipe pipe = crtc->pipe;
int plane, level, max_level = ilk_wm_max_level(dev_priv);
+ u8 hw_enabled_slices;
if (INTEL_GEN(dev_priv) < 9 || !new_crtc_state->hw.active)
return;
@@ -13414,14 +13413,13 @@ static void verify_wm_state(struct intel_crtc *crtc,
skl_pipe_ddb_get_hw_state(crtc, hw->ddb_y, hw->ddb_uv);
- skl_ddb_get_hw_state(dev_priv, &hw->ddb);
- sw_ddb = &dev_priv->wm.skl_hw.ddb;
+ hw_enabled_slices = intel_enabled_dbuf_slices_num(dev_priv);
if (INTEL_GEN(dev_priv) >= 11 &&
- hw->ddb.enabled_slices != sw_ddb->enabled_slices)
+ hw_enabled_slices != dev_priv->enabled_slices)
DRM_ERROR("mismatch in DBUF Slices (expected %u, got %u)\n",
- sw_ddb->enabled_slices,
- hw->ddb.enabled_slices);
+ dev_priv->enabled_slices,
+ hw_enabled_slices);
/* planes */
for_each_universal_plane(dev_priv, pipe, plane) {
@@ -14647,8 +14645,8 @@ static void skl_commit_modeset_enables(struct intel_atomic_state *state)
unsigned int updated = 0;
bool progress;
int i;
- u8 hw_enabled_slices = dev_priv->wm.skl_hw.ddb.enabled_slices;
- u8 required_slices = state->wm_results.ddb.enabled_slices;
+ u8 hw_enabled_slices = dev_priv->enabled_slices;
+ u8 required_slices = state->enabled_slices;
struct skl_ddb_entry entries[I915_MAX_PIPES] = {};
for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index ce1b64f4dd44..4c3ede73e863 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -4264,7 +4264,7 @@ static u8 intel_dbuf_max_slices(struct drm_i915_private *dev_priv)
void icl_dbuf_slices_update(struct drm_i915_private *dev_priv,
u8 req_slices)
{
- const u8 hw_enabled_slices = dev_priv->wm.skl_hw.ddb.enabled_slices;
+ const u8 hw_enabled_slices = dev_priv->enabled_slices;
bool ret;
if (req_slices > intel_dbuf_max_slices(dev_priv)) {
@@ -4281,7 +4281,7 @@ void icl_dbuf_slices_update(struct drm_i915_private *dev_priv,
ret = intel_dbuf_slice_set(dev_priv, DBUF_CTL_S2, false);
if (ret)
- dev_priv->wm.skl_hw.ddb.enabled_slices = req_slices;
+ dev_priv->enabled_slices = req_slices;
}
static void icl_dbuf_enable(struct drm_i915_private *dev_priv)
@@ -4300,7 +4300,7 @@ static void icl_dbuf_enable(struct drm_i915_private *dev_priv)
* FIXME: for now pretend that we only have 1 slice, see
* intel_enabled_dbuf_slices_num().
*/
- dev_priv->wm.skl_hw.ddb.enabled_slices = 1;
+ dev_priv->enabled_slices = 1;
}
static void icl_dbuf_disable(struct drm_i915_private *dev_priv)
@@ -4319,7 +4319,7 @@ static void icl_dbuf_disable(struct drm_i915_private *dev_priv)
* FIXME: for now pretend that the first slice is always
* enabled, see intel_enabled_dbuf_slices_num().
*/
- dev_priv->wm.skl_hw.ddb.enabled_slices = 1;
+ dev_priv->enabled_slices = 1;
}
static void icl_mbus_init(struct drm_i915_private *dev_priv)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 83ea04149b77..5eaeaf487a01 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -517,6 +517,9 @@ struct intel_atomic_state {
/* Gen9+ only */
struct skl_ddb_values wm_results;
+ /* Number of enabled DBuf slices */
+ u8 enabled_slices;
+
struct i915_sw_fence commit_ready;
struct llist_node freed;
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index fdae5a919bc8..195629a37a61 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -798,13 +798,8 @@ static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1,
return false;
}
-struct skl_ddb_allocation {
- u8 enabled_slices; /* GEN11 has configurable 2 slices */
-};
-
struct skl_ddb_values {
unsigned dirty_pipes;
- struct skl_ddb_allocation ddb;
};
struct skl_wm_level {
@@ -1215,6 +1210,8 @@ struct drm_i915_private {
bool distrust_bios_wm;
} wm;
+ u8 enabled_slices; /* GEN11 has configurable 2 slices */
+
struct dram_info {
bool valid;
bool is_16gb_dimm;
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 5aad9d49a528..a93b4385de4b 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3599,7 +3599,7 @@ bool ilk_disable_lp_wm(struct drm_device *dev)
return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL);
}
-static u8 intel_enabled_dbuf_slices_num(struct drm_i915_private *dev_priv)
+u8 intel_enabled_dbuf_slices_num(struct drm_i915_private *dev_priv)
{
u8 enabled_slices;
@@ -3822,9 +3822,10 @@ bool intel_can_enable_sagv(struct intel_atomic_state *state)
static u16 intel_get_ddb_size(struct drm_i915_private *dev_priv,
const struct intel_crtc_state *crtc_state,
const u64 total_data_rate,
- const int num_active,
- struct skl_ddb_allocation *ddb)
+ const int num_active)
{
+ struct drm_atomic_state *state = crtc_state->uapi.state;
+ struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
const struct drm_display_mode *adjusted_mode;
u64 total_data_bw;
u16 ddb_size = INTEL_INFO(dev_priv)->ddb_size;
@@ -3846,9 +3847,9 @@ static u16 intel_get_ddb_size(struct drm_i915_private *dev_priv,
* - should validate we stay within the hw bandwidth limits
*/
if (0 && (num_active > 1 || total_data_bw >= GBps(12))) {
- ddb->enabled_slices = 2;
+ intel_state->enabled_slices = 2;
} else {
- ddb->enabled_slices = 1;
+ intel_state->enabled_slices = 1;
ddb_size /= 2;
}
@@ -3859,7 +3860,6 @@ static void
skl_ddb_get_pipe_allocation_limits(struct drm_i915_private *dev_priv,
const struct intel_crtc_state *crtc_state,
const u64 total_data_rate,
- struct skl_ddb_allocation *ddb,
struct skl_ddb_entry *alloc, /* out */
int *num_active /* out */)
{
@@ -3885,7 +3885,7 @@ skl_ddb_get_pipe_allocation_limits(struct drm_i915_private *dev_priv,
*num_active = hweight8(dev_priv->active_pipes);
ddb_size = intel_get_ddb_size(dev_priv, crtc_state, total_data_rate,
- *num_active, ddb);
+ *num_active);
/*
* If the state doesn't change the active CRTC's or there is no
@@ -4046,10 +4046,9 @@ void skl_pipe_ddb_get_hw_state(struct intel_crtc *crtc,
intel_display_power_put(dev_priv, power_domain, wakeref);
}
-void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
- struct skl_ddb_allocation *ddb /* out */)
+void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv)
{
- ddb->enabled_slices = intel_enabled_dbuf_slices_num(dev_priv);
+ dev_priv->enabled_slices = intel_enabled_dbuf_slices_num(dev_priv);
}
/*
@@ -4226,8 +4225,7 @@ icl_get_total_relative_data_rate(struct intel_crtc_state *crtc_state,
}
static int
-skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state,
- struct skl_ddb_allocation *ddb /* out */)
+skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state)
{
struct drm_atomic_state *state = crtc_state->uapi.state;
struct drm_crtc *crtc = crtc_state->uapi.crtc;
@@ -4269,7 +4267,7 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state,
skl_ddb_get_pipe_allocation_limits(dev_priv, crtc_state, total_data_rate,
- ddb, alloc, &num_active);
+ alloc, &num_active);
alloc_size = skl_ddb_entry_size(alloc);
if (alloc_size == 0)
return 0;
@@ -5183,18 +5181,17 @@ skl_ddb_add_affected_planes(const struct intel_crtc_state *old_crtc_state,
static int
skl_compute_ddb(struct intel_atomic_state *state)
{
- const struct drm_i915_private *dev_priv = to_i915(state->base.dev);
- struct skl_ddb_allocation *ddb = &state->wm_results.ddb;
+ struct drm_i915_private *dev_priv = to_i915(state->base.dev);
struct intel_crtc_state *old_crtc_state;
struct intel_crtc_state *new_crtc_state;
struct intel_crtc *crtc;
int ret, i;
- memcpy(ddb, &dev_priv->wm.skl_hw.ddb, sizeof(*ddb));
+ state->enabled_slices = dev_priv->enabled_slices;
for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
new_crtc_state, i) {
- ret = skl_allocate_pipe_ddb(new_crtc_state, ddb);
+ ret = skl_allocate_pipe_ddb(new_crtc_state);
if (ret)
return ret;
@@ -5666,11 +5663,10 @@ void skl_pipe_wm_get_hw_state(struct intel_crtc *crtc,
void skl_wm_get_hw_state(struct drm_i915_private *dev_priv)
{
struct skl_ddb_values *hw = &dev_priv->wm.skl_hw;
- struct skl_ddb_allocation *ddb = &dev_priv->wm.skl_hw.ddb;
struct intel_crtc *crtc;
struct intel_crtc_state *crtc_state;
- skl_ddb_get_hw_state(dev_priv, ddb);
+ skl_ddb_get_hw_state(dev_priv);
for_each_intel_crtc(&dev_priv->drm, crtc) {
crtc_state = to_intel_crtc_state(crtc->base.state);
diff --git a/drivers/gpu/drm/i915/intel_pm.h b/drivers/gpu/drm/i915/intel_pm.h
index b579c724b915..4aafae4c8e0d 100644
--- a/drivers/gpu/drm/i915/intel_pm.h
+++ b/drivers/gpu/drm/i915/intel_pm.h
@@ -17,8 +17,8 @@ struct intel_atomic_state;
struct intel_crtc;
struct intel_crtc_state;
struct intel_plane;
-struct skl_ddb_allocation;
struct skl_ddb_entry;
+struct skl_ddb_values;
struct skl_pipe_wm;
struct skl_wm_level;
@@ -33,11 +33,11 @@ void g4x_wm_get_hw_state(struct drm_i915_private *dev_priv);
void vlv_wm_get_hw_state(struct drm_i915_private *dev_priv);
void ilk_wm_get_hw_state(struct drm_i915_private *dev_priv);
void skl_wm_get_hw_state(struct drm_i915_private *dev_priv);
+u8 intel_enabled_dbuf_slices_num(struct drm_i915_private *dev_priv);
void skl_pipe_ddb_get_hw_state(struct intel_crtc *crtc,
struct skl_ddb_entry *ddb_y,
struct skl_ddb_entry *ddb_uv);
-void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
- struct skl_ddb_allocation *ddb /* out */);
+void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv);
void skl_pipe_wm_get_hw_state(struct intel_crtc *crtc,
struct skl_pipe_wm *out);
void g4x_wm_sanitize(struct drm_i915_private *dev_priv);
--
2.17.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [Intel-gfx] [PATCH v7 1/4] drm/i915: Remove skl_ddl_allocation struct
@ 2019-11-29 13:37 ` Stanislav Lisovskiy
0 siblings, 0 replies; 26+ messages in thread
From: Stanislav Lisovskiy @ 2019-11-29 13:37 UTC (permalink / raw)
To: intel-gfx
Current consensus that it is redundant as
we already have skl_ddb_values struct out there,
also this struct contains only single member
which makes it unnecessary.
v2: As dirty_pipes soon going to be nuked away
from skl_ddb_values, evacuating enabled_slices
to safer in dev_priv.
Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 16 ++++-----
.../drm/i915/display/intel_display_power.c | 8 ++---
.../drm/i915/display/intel_display_types.h | 3 ++
drivers/gpu/drm/i915/i915_drv.h | 7 ++--
drivers/gpu/drm/i915/intel_pm.c | 34 ++++++++-----------
drivers/gpu/drm/i915/intel_pm.h | 6 ++--
6 files changed, 34 insertions(+), 40 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 53dc310a5f6d..dda43e3dcdbf 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -13393,14 +13393,13 @@ static void verify_wm_state(struct intel_crtc *crtc,
struct skl_hw_state {
struct skl_ddb_entry ddb_y[I915_MAX_PLANES];
struct skl_ddb_entry ddb_uv[I915_MAX_PLANES];
- struct skl_ddb_allocation ddb;
struct skl_pipe_wm wm;
} *hw;
- struct skl_ddb_allocation *sw_ddb;
struct skl_pipe_wm *sw_wm;
struct skl_ddb_entry *hw_ddb_entry, *sw_ddb_entry;
const enum pipe pipe = crtc->pipe;
int plane, level, max_level = ilk_wm_max_level(dev_priv);
+ u8 hw_enabled_slices;
if (INTEL_GEN(dev_priv) < 9 || !new_crtc_state->hw.active)
return;
@@ -13414,14 +13413,13 @@ static void verify_wm_state(struct intel_crtc *crtc,
skl_pipe_ddb_get_hw_state(crtc, hw->ddb_y, hw->ddb_uv);
- skl_ddb_get_hw_state(dev_priv, &hw->ddb);
- sw_ddb = &dev_priv->wm.skl_hw.ddb;
+ hw_enabled_slices = intel_enabled_dbuf_slices_num(dev_priv);
if (INTEL_GEN(dev_priv) >= 11 &&
- hw->ddb.enabled_slices != sw_ddb->enabled_slices)
+ hw_enabled_slices != dev_priv->enabled_slices)
DRM_ERROR("mismatch in DBUF Slices (expected %u, got %u)\n",
- sw_ddb->enabled_slices,
- hw->ddb.enabled_slices);
+ dev_priv->enabled_slices,
+ hw_enabled_slices);
/* planes */
for_each_universal_plane(dev_priv, pipe, plane) {
@@ -14647,8 +14645,8 @@ static void skl_commit_modeset_enables(struct intel_atomic_state *state)
unsigned int updated = 0;
bool progress;
int i;
- u8 hw_enabled_slices = dev_priv->wm.skl_hw.ddb.enabled_slices;
- u8 required_slices = state->wm_results.ddb.enabled_slices;
+ u8 hw_enabled_slices = dev_priv->enabled_slices;
+ u8 required_slices = state->enabled_slices;
struct skl_ddb_entry entries[I915_MAX_PIPES] = {};
for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index ce1b64f4dd44..4c3ede73e863 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -4264,7 +4264,7 @@ static u8 intel_dbuf_max_slices(struct drm_i915_private *dev_priv)
void icl_dbuf_slices_update(struct drm_i915_private *dev_priv,
u8 req_slices)
{
- const u8 hw_enabled_slices = dev_priv->wm.skl_hw.ddb.enabled_slices;
+ const u8 hw_enabled_slices = dev_priv->enabled_slices;
bool ret;
if (req_slices > intel_dbuf_max_slices(dev_priv)) {
@@ -4281,7 +4281,7 @@ void icl_dbuf_slices_update(struct drm_i915_private *dev_priv,
ret = intel_dbuf_slice_set(dev_priv, DBUF_CTL_S2, false);
if (ret)
- dev_priv->wm.skl_hw.ddb.enabled_slices = req_slices;
+ dev_priv->enabled_slices = req_slices;
}
static void icl_dbuf_enable(struct drm_i915_private *dev_priv)
@@ -4300,7 +4300,7 @@ static void icl_dbuf_enable(struct drm_i915_private *dev_priv)
* FIXME: for now pretend that we only have 1 slice, see
* intel_enabled_dbuf_slices_num().
*/
- dev_priv->wm.skl_hw.ddb.enabled_slices = 1;
+ dev_priv->enabled_slices = 1;
}
static void icl_dbuf_disable(struct drm_i915_private *dev_priv)
@@ -4319,7 +4319,7 @@ static void icl_dbuf_disable(struct drm_i915_private *dev_priv)
* FIXME: for now pretend that the first slice is always
* enabled, see intel_enabled_dbuf_slices_num().
*/
- dev_priv->wm.skl_hw.ddb.enabled_slices = 1;
+ dev_priv->enabled_slices = 1;
}
static void icl_mbus_init(struct drm_i915_private *dev_priv)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 83ea04149b77..5eaeaf487a01 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -517,6 +517,9 @@ struct intel_atomic_state {
/* Gen9+ only */
struct skl_ddb_values wm_results;
+ /* Number of enabled DBuf slices */
+ u8 enabled_slices;
+
struct i915_sw_fence commit_ready;
struct llist_node freed;
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index fdae5a919bc8..195629a37a61 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -798,13 +798,8 @@ static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1,
return false;
}
-struct skl_ddb_allocation {
- u8 enabled_slices; /* GEN11 has configurable 2 slices */
-};
-
struct skl_ddb_values {
unsigned dirty_pipes;
- struct skl_ddb_allocation ddb;
};
struct skl_wm_level {
@@ -1215,6 +1210,8 @@ struct drm_i915_private {
bool distrust_bios_wm;
} wm;
+ u8 enabled_slices; /* GEN11 has configurable 2 slices */
+
struct dram_info {
bool valid;
bool is_16gb_dimm;
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 5aad9d49a528..a93b4385de4b 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3599,7 +3599,7 @@ bool ilk_disable_lp_wm(struct drm_device *dev)
return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL);
}
-static u8 intel_enabled_dbuf_slices_num(struct drm_i915_private *dev_priv)
+u8 intel_enabled_dbuf_slices_num(struct drm_i915_private *dev_priv)
{
u8 enabled_slices;
@@ -3822,9 +3822,10 @@ bool intel_can_enable_sagv(struct intel_atomic_state *state)
static u16 intel_get_ddb_size(struct drm_i915_private *dev_priv,
const struct intel_crtc_state *crtc_state,
const u64 total_data_rate,
- const int num_active,
- struct skl_ddb_allocation *ddb)
+ const int num_active)
{
+ struct drm_atomic_state *state = crtc_state->uapi.state;
+ struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
const struct drm_display_mode *adjusted_mode;
u64 total_data_bw;
u16 ddb_size = INTEL_INFO(dev_priv)->ddb_size;
@@ -3846,9 +3847,9 @@ static u16 intel_get_ddb_size(struct drm_i915_private *dev_priv,
* - should validate we stay within the hw bandwidth limits
*/
if (0 && (num_active > 1 || total_data_bw >= GBps(12))) {
- ddb->enabled_slices = 2;
+ intel_state->enabled_slices = 2;
} else {
- ddb->enabled_slices = 1;
+ intel_state->enabled_slices = 1;
ddb_size /= 2;
}
@@ -3859,7 +3860,6 @@ static void
skl_ddb_get_pipe_allocation_limits(struct drm_i915_private *dev_priv,
const struct intel_crtc_state *crtc_state,
const u64 total_data_rate,
- struct skl_ddb_allocation *ddb,
struct skl_ddb_entry *alloc, /* out */
int *num_active /* out */)
{
@@ -3885,7 +3885,7 @@ skl_ddb_get_pipe_allocation_limits(struct drm_i915_private *dev_priv,
*num_active = hweight8(dev_priv->active_pipes);
ddb_size = intel_get_ddb_size(dev_priv, crtc_state, total_data_rate,
- *num_active, ddb);
+ *num_active);
/*
* If the state doesn't change the active CRTC's or there is no
@@ -4046,10 +4046,9 @@ void skl_pipe_ddb_get_hw_state(struct intel_crtc *crtc,
intel_display_power_put(dev_priv, power_domain, wakeref);
}
-void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
- struct skl_ddb_allocation *ddb /* out */)
+void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv)
{
- ddb->enabled_slices = intel_enabled_dbuf_slices_num(dev_priv);
+ dev_priv->enabled_slices = intel_enabled_dbuf_slices_num(dev_priv);
}
/*
@@ -4226,8 +4225,7 @@ icl_get_total_relative_data_rate(struct intel_crtc_state *crtc_state,
}
static int
-skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state,
- struct skl_ddb_allocation *ddb /* out */)
+skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state)
{
struct drm_atomic_state *state = crtc_state->uapi.state;
struct drm_crtc *crtc = crtc_state->uapi.crtc;
@@ -4269,7 +4267,7 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state,
skl_ddb_get_pipe_allocation_limits(dev_priv, crtc_state, total_data_rate,
- ddb, alloc, &num_active);
+ alloc, &num_active);
alloc_size = skl_ddb_entry_size(alloc);
if (alloc_size == 0)
return 0;
@@ -5183,18 +5181,17 @@ skl_ddb_add_affected_planes(const struct intel_crtc_state *old_crtc_state,
static int
skl_compute_ddb(struct intel_atomic_state *state)
{
- const struct drm_i915_private *dev_priv = to_i915(state->base.dev);
- struct skl_ddb_allocation *ddb = &state->wm_results.ddb;
+ struct drm_i915_private *dev_priv = to_i915(state->base.dev);
struct intel_crtc_state *old_crtc_state;
struct intel_crtc_state *new_crtc_state;
struct intel_crtc *crtc;
int ret, i;
- memcpy(ddb, &dev_priv->wm.skl_hw.ddb, sizeof(*ddb));
+ state->enabled_slices = dev_priv->enabled_slices;
for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
new_crtc_state, i) {
- ret = skl_allocate_pipe_ddb(new_crtc_state, ddb);
+ ret = skl_allocate_pipe_ddb(new_crtc_state);
if (ret)
return ret;
@@ -5666,11 +5663,10 @@ void skl_pipe_wm_get_hw_state(struct intel_crtc *crtc,
void skl_wm_get_hw_state(struct drm_i915_private *dev_priv)
{
struct skl_ddb_values *hw = &dev_priv->wm.skl_hw;
- struct skl_ddb_allocation *ddb = &dev_priv->wm.skl_hw.ddb;
struct intel_crtc *crtc;
struct intel_crtc_state *crtc_state;
- skl_ddb_get_hw_state(dev_priv, ddb);
+ skl_ddb_get_hw_state(dev_priv);
for_each_intel_crtc(&dev_priv->drm, crtc) {
crtc_state = to_intel_crtc_state(crtc->base.state);
diff --git a/drivers/gpu/drm/i915/intel_pm.h b/drivers/gpu/drm/i915/intel_pm.h
index b579c724b915..4aafae4c8e0d 100644
--- a/drivers/gpu/drm/i915/intel_pm.h
+++ b/drivers/gpu/drm/i915/intel_pm.h
@@ -17,8 +17,8 @@ struct intel_atomic_state;
struct intel_crtc;
struct intel_crtc_state;
struct intel_plane;
-struct skl_ddb_allocation;
struct skl_ddb_entry;
+struct skl_ddb_values;
struct skl_pipe_wm;
struct skl_wm_level;
@@ -33,11 +33,11 @@ void g4x_wm_get_hw_state(struct drm_i915_private *dev_priv);
void vlv_wm_get_hw_state(struct drm_i915_private *dev_priv);
void ilk_wm_get_hw_state(struct drm_i915_private *dev_priv);
void skl_wm_get_hw_state(struct drm_i915_private *dev_priv);
+u8 intel_enabled_dbuf_slices_num(struct drm_i915_private *dev_priv);
void skl_pipe_ddb_get_hw_state(struct intel_crtc *crtc,
struct skl_ddb_entry *ddb_y,
struct skl_ddb_entry *ddb_uv);
-void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
- struct skl_ddb_allocation *ddb /* out */);
+void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv);
void skl_pipe_wm_get_hw_state(struct intel_crtc *crtc,
struct skl_pipe_wm *out);
void g4x_wm_sanitize(struct drm_i915_private *dev_priv);
--
2.17.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PATCH v7 2/4] drm/i915: Move dbuf slice update to proper place
@ 2019-11-29 13:37 ` Stanislav Lisovskiy
0 siblings, 0 replies; 26+ messages in thread
From: Stanislav Lisovskiy @ 2019-11-29 13:37 UTC (permalink / raw)
To: intel-gfx
Current DBuf slices update wasn't done in proper
plane, especially its "post" part, which should
disable those only once vblank had passed and
all other changes are committed.
v2: Fix to use dev_priv and intel_atomic_state
instead of skl_ddb_values
(to be nuked in Villes patch)
Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 38 ++++++++++++++------
1 file changed, 28 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index dda43e3dcdbf..db0830745f25 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -14637,6 +14637,28 @@ static void intel_update_trans_port_sync_crtcs(struct intel_crtc *crtc,
state);
}
+static void icl_dbuf_slice_pre_update(struct intel_atomic_state *state)
+{
+ struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+ u8 hw_enabled_slices = dev_priv->enabled_slices;
+ u8 required_slices = state->enabled_slices;
+
+ /* If 2nd DBuf slice required, enable it here */
+ if (INTEL_GEN(dev_priv) >= 11 && required_slices > hw_enabled_slices)
+ icl_dbuf_slices_update(dev_priv, required_slices);
+}
+
+static void icl_dbuf_slice_post_update(struct intel_atomic_state *state)
+{
+ struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+ u8 hw_enabled_slices = dev_priv->enabled_slices;
+ u8 required_slices = state->enabled_slices;
+
+ /* If 2nd DBuf slice is no more required disable it */
+ if (INTEL_GEN(dev_priv) >= 11 && required_slices < hw_enabled_slices)
+ icl_dbuf_slices_update(dev_priv, required_slices);
+}
+
static void skl_commit_modeset_enables(struct intel_atomic_state *state)
{
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
@@ -14645,8 +14667,6 @@ static void skl_commit_modeset_enables(struct intel_atomic_state *state)
unsigned int updated = 0;
bool progress;
int i;
- u8 hw_enabled_slices = dev_priv->enabled_slices;
- u8 required_slices = state->enabled_slices;
struct skl_ddb_entry entries[I915_MAX_PIPES] = {};
for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i)
@@ -14654,10 +14674,6 @@ static void skl_commit_modeset_enables(struct intel_atomic_state *state)
if (new_crtc_state->hw.active)
entries[i] = old_crtc_state->wm.skl.ddb;
- /* If 2nd DBuf slice required, enable it here */
- if (INTEL_GEN(dev_priv) >= 11 && required_slices > hw_enabled_slices)
- icl_dbuf_slices_update(dev_priv, required_slices);
-
/*
* Whenever the number of active pipes changes, we need to make sure we
* update the pipes in the right order so that their ddb allocations
@@ -14714,10 +14730,6 @@ static void skl_commit_modeset_enables(struct intel_atomic_state *state)
progress = true;
}
} while (progress);
-
- /* If 2nd DBuf slice is no more required disable it */
- if (INTEL_GEN(dev_priv) >= 11 && required_slices < hw_enabled_slices)
- icl_dbuf_slices_update(dev_priv, required_slices);
}
static void intel_atomic_helper_free_state(struct drm_i915_private *dev_priv)
@@ -14847,6 +14859,9 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
if (state->modeset)
intel_encoders_update_prepare(state);
+ /* Enable all new slices, we might need */
+ icl_dbuf_slice_pre_update(state);
+
/* Now enable the clocks, plane, pipe, and connectors that we set up. */
dev_priv->display.commit_modeset_enables(state);
@@ -14906,6 +14921,9 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
if (state->modeset && intel_can_enable_sagv(state))
intel_enable_sagv(dev_priv);
+ /* Disable all slices, we don't need */
+ icl_dbuf_slice_post_update(state);
+
drm_atomic_helper_commit_hw_done(&state->base);
if (state->modeset) {
--
2.17.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [Intel-gfx] [PATCH v7 2/4] drm/i915: Move dbuf slice update to proper place
@ 2019-11-29 13:37 ` Stanislav Lisovskiy
0 siblings, 0 replies; 26+ messages in thread
From: Stanislav Lisovskiy @ 2019-11-29 13:37 UTC (permalink / raw)
To: intel-gfx
Current DBuf slices update wasn't done in proper
plane, especially its "post" part, which should
disable those only once vblank had passed and
all other changes are committed.
v2: Fix to use dev_priv and intel_atomic_state
instead of skl_ddb_values
(to be nuked in Villes patch)
Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 38 ++++++++++++++------
1 file changed, 28 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index dda43e3dcdbf..db0830745f25 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -14637,6 +14637,28 @@ static void intel_update_trans_port_sync_crtcs(struct intel_crtc *crtc,
state);
}
+static void icl_dbuf_slice_pre_update(struct intel_atomic_state *state)
+{
+ struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+ u8 hw_enabled_slices = dev_priv->enabled_slices;
+ u8 required_slices = state->enabled_slices;
+
+ /* If 2nd DBuf slice required, enable it here */
+ if (INTEL_GEN(dev_priv) >= 11 && required_slices > hw_enabled_slices)
+ icl_dbuf_slices_update(dev_priv, required_slices);
+}
+
+static void icl_dbuf_slice_post_update(struct intel_atomic_state *state)
+{
+ struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+ u8 hw_enabled_slices = dev_priv->enabled_slices;
+ u8 required_slices = state->enabled_slices;
+
+ /* If 2nd DBuf slice is no more required disable it */
+ if (INTEL_GEN(dev_priv) >= 11 && required_slices < hw_enabled_slices)
+ icl_dbuf_slices_update(dev_priv, required_slices);
+}
+
static void skl_commit_modeset_enables(struct intel_atomic_state *state)
{
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
@@ -14645,8 +14667,6 @@ static void skl_commit_modeset_enables(struct intel_atomic_state *state)
unsigned int updated = 0;
bool progress;
int i;
- u8 hw_enabled_slices = dev_priv->enabled_slices;
- u8 required_slices = state->enabled_slices;
struct skl_ddb_entry entries[I915_MAX_PIPES] = {};
for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i)
@@ -14654,10 +14674,6 @@ static void skl_commit_modeset_enables(struct intel_atomic_state *state)
if (new_crtc_state->hw.active)
entries[i] = old_crtc_state->wm.skl.ddb;
- /* If 2nd DBuf slice required, enable it here */
- if (INTEL_GEN(dev_priv) >= 11 && required_slices > hw_enabled_slices)
- icl_dbuf_slices_update(dev_priv, required_slices);
-
/*
* Whenever the number of active pipes changes, we need to make sure we
* update the pipes in the right order so that their ddb allocations
@@ -14714,10 +14730,6 @@ static void skl_commit_modeset_enables(struct intel_atomic_state *state)
progress = true;
}
} while (progress);
-
- /* If 2nd DBuf slice is no more required disable it */
- if (INTEL_GEN(dev_priv) >= 11 && required_slices < hw_enabled_slices)
- icl_dbuf_slices_update(dev_priv, required_slices);
}
static void intel_atomic_helper_free_state(struct drm_i915_private *dev_priv)
@@ -14847,6 +14859,9 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
if (state->modeset)
intel_encoders_update_prepare(state);
+ /* Enable all new slices, we might need */
+ icl_dbuf_slice_pre_update(state);
+
/* Now enable the clocks, plane, pipe, and connectors that we set up. */
dev_priv->display.commit_modeset_enables(state);
@@ -14906,6 +14921,9 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
if (state->modeset && intel_can_enable_sagv(state))
intel_enable_sagv(dev_priv);
+ /* Disable all slices, we don't need */
+ icl_dbuf_slice_post_update(state);
+
drm_atomic_helper_commit_hw_done(&state->base);
if (state->modeset) {
--
2.17.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PATCH v7 3/4] drm/i915: Manipulate DBuf slices properly
@ 2019-11-29 13:37 ` Stanislav Lisovskiy
0 siblings, 0 replies; 26+ messages in thread
From: Stanislav Lisovskiy @ 2019-11-29 13:37 UTC (permalink / raw)
To: intel-gfx
Start manipulating DBuf slices as a mask,
but not as a total number, as current approach
doesn't give us full control on all combinations
of slices, which we might need(like enabling S2
only can't enabled by setting enabled_slices=1).
Removed wrong code from intel_get_ddb_size as
it doesn't match to BSpec. For now still just
use DBuf slice until proper algorithm is implemented.
Other minor code refactoring to get prepared
for major DBuf assignment changes landed:
- As now enabled slices contain a mask
we still need some value which should
reflect how much DBuf slices are supported
by the platform, now device info contains
num_supported_dbuf_slices.
- Removed unneeded assertion as we are now
manipulating slices in a more proper way.
v2: Start using enabled_slices in dev_priv
Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 11 +-
.../drm/i915/display/intel_display_power.c | 100 ++++++++----------
.../drm/i915/display/intel_display_power.h | 5 +
drivers/gpu/drm/i915/i915_pci.c | 6 +-
drivers/gpu/drm/i915/intel_device_info.h | 1 +
drivers/gpu/drm/i915/intel_pm.c | 45 +++-----
drivers/gpu/drm/i915/intel_pm.h | 2 +-
7 files changed, 74 insertions(+), 96 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index db0830745f25..c73bdcefd242 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -13413,11 +13413,11 @@ static void verify_wm_state(struct intel_crtc *crtc,
skl_pipe_ddb_get_hw_state(crtc, hw->ddb_y, hw->ddb_uv);
- hw_enabled_slices = intel_enabled_dbuf_slices_num(dev_priv);
+ hw_enabled_slices = intel_enabled_dbuf_slices_mask(dev_priv);
if (INTEL_GEN(dev_priv) >= 11 &&
hw_enabled_slices != dev_priv->enabled_slices)
- DRM_ERROR("mismatch in DBUF Slices (expected %u, got %u)\n",
+ DRM_ERROR("mismatch in DBUF Slices (expected %x, got %x)\n",
dev_priv->enabled_slices,
hw_enabled_slices);
@@ -14642,10 +14642,11 @@ static void icl_dbuf_slice_pre_update(struct intel_atomic_state *state)
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
u8 hw_enabled_slices = dev_priv->enabled_slices;
u8 required_slices = state->enabled_slices;
+ u8 slices_union = hw_enabled_slices | required_slices;
/* If 2nd DBuf slice required, enable it here */
- if (INTEL_GEN(dev_priv) >= 11 && required_slices > hw_enabled_slices)
- icl_dbuf_slices_update(dev_priv, required_slices);
+ if (INTEL_GEN(dev_priv) >= 11 && required_slices != hw_enabled_slices)
+ icl_dbuf_slices_update(dev_priv, slices_union);
}
static void icl_dbuf_slice_post_update(struct intel_atomic_state *state)
@@ -14655,7 +14656,7 @@ static void icl_dbuf_slice_post_update(struct intel_atomic_state *state)
u8 required_slices = state->enabled_slices;
/* If 2nd DBuf slice is no more required disable it */
- if (INTEL_GEN(dev_priv) >= 11 && required_slices < hw_enabled_slices)
+ if (INTEL_GEN(dev_priv) >= 11 && required_slices != hw_enabled_slices)
icl_dbuf_slices_update(dev_priv, required_slices);
}
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index 4c3ede73e863..ef288892c8ce 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -1031,15 +1031,6 @@ static bool gen9_dc_off_power_well_enabled(struct drm_i915_private *dev_priv,
(I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5_DC6_MASK) == 0);
}
-static void gen9_assert_dbuf_enabled(struct drm_i915_private *dev_priv)
-{
- u32 tmp = I915_READ(DBUF_CTL);
-
- WARN((tmp & (DBUF_POWER_STATE | DBUF_POWER_REQUEST)) !=
- (DBUF_POWER_STATE | DBUF_POWER_REQUEST),
- "Unexpected DBuf power power state (0x%08x)\n", tmp);
-}
-
static void gen9_disable_dc_states(struct drm_i915_private *dev_priv)
{
struct intel_cdclk_state cdclk_state = {};
@@ -1055,8 +1046,6 @@ static void gen9_disable_dc_states(struct drm_i915_private *dev_priv)
/* Can't read out voltage_level so can't use intel_cdclk_changed() */
WARN_ON(intel_cdclk_needs_modeset(&dev_priv->cdclk.hw, &cdclk_state));
- gen9_assert_dbuf_enabled(dev_priv);
-
if (IS_GEN9_LP(dev_priv))
bxt_verify_ddi_phy_power_wells(dev_priv);
@@ -4254,72 +4243,71 @@ static void gen9_dbuf_disable(struct drm_i915_private *dev_priv)
intel_dbuf_slice_set(dev_priv, DBUF_CTL, false);
}
-static u8 intel_dbuf_max_slices(struct drm_i915_private *dev_priv)
+int intel_dbuf_max_slices(struct drm_i915_private *dev_priv)
{
- if (INTEL_GEN(dev_priv) < 11)
- return 1;
- return 2;
+ return INTEL_INFO(dev_priv)->num_supported_dbuf_slices;
+}
+
+void icl_program_dbuf_slices(struct drm_i915_private *dev_priv)
+{
+ const u8 hw_enabled_slices = dev_priv->enabled_slices;
+
+ icl_dbuf_slices_update(dev_priv, hw_enabled_slices);
}
void icl_dbuf_slices_update(struct drm_i915_private *dev_priv,
u8 req_slices)
{
- const u8 hw_enabled_slices = dev_priv->enabled_slices;
- bool ret;
+ int i;
+ int max_slices = intel_dbuf_max_slices(dev_priv);
- if (req_slices > intel_dbuf_max_slices(dev_priv)) {
+ if (hweight8(req_slices) > intel_dbuf_max_slices(dev_priv)) {
DRM_ERROR("Invalid number of dbuf slices requested\n");
return;
}
- if (req_slices == hw_enabled_slices || req_slices == 0)
- return;
+ DRM_DEBUG_KMS("Updating dbuf slices to %x\n", req_slices);
- if (req_slices > hw_enabled_slices)
- ret = intel_dbuf_slice_set(dev_priv, DBUF_CTL_S2, true);
- else
- ret = intel_dbuf_slice_set(dev_priv, DBUF_CTL_S2, false);
+ for (i = 0; i < max_slices; i++) {
+ int slice_bit = BIT(i);
+ bool slice_set = (slice_bit & req_slices) != 0;
+
+ switch (slice_bit) {
+ case DBUF_S1_BIT:
+ intel_dbuf_slice_set(dev_priv,
+ DBUF_CTL_S1,
+ slice_set);
+ break;
+ case DBUF_S2_BIT:
+ intel_dbuf_slice_set(dev_priv,
+ DBUF_CTL_S2,
+ slice_set);
+ break;
+ default:
+ MISSING_CASE(slice_bit);
+ }
+ }
- if (ret)
- dev_priv->enabled_slices = req_slices;
+ dev_priv->enabled_slices = req_slices;
}
static void icl_dbuf_enable(struct drm_i915_private *dev_priv)
{
- I915_WRITE(DBUF_CTL_S1, I915_READ(DBUF_CTL_S1) | DBUF_POWER_REQUEST);
- I915_WRITE(DBUF_CTL_S2, I915_READ(DBUF_CTL_S2) | DBUF_POWER_REQUEST);
- POSTING_READ(DBUF_CTL_S2);
-
- udelay(10);
-
- if (!(I915_READ(DBUF_CTL_S1) & DBUF_POWER_STATE) ||
- !(I915_READ(DBUF_CTL_S2) & DBUF_POWER_STATE))
- DRM_ERROR("DBuf power enable timeout\n");
- else
- /*
- * FIXME: for now pretend that we only have 1 slice, see
- * intel_enabled_dbuf_slices_num().
- */
- dev_priv->enabled_slices = 1;
+ /*
+ * Just power up 1 slice, we will
+ * figure out later which slices we have and what we need.
+ */
+ dev_priv->enabled_slices = DBUF_S1_BIT;
+ icl_program_dbuf_slices(dev_priv);
}
static void icl_dbuf_disable(struct drm_i915_private *dev_priv)
{
- I915_WRITE(DBUF_CTL_S1, I915_READ(DBUF_CTL_S1) & ~DBUF_POWER_REQUEST);
- I915_WRITE(DBUF_CTL_S2, I915_READ(DBUF_CTL_S2) & ~DBUF_POWER_REQUEST);
- POSTING_READ(DBUF_CTL_S2);
-
- udelay(10);
-
- if ((I915_READ(DBUF_CTL_S1) & DBUF_POWER_STATE) ||
- (I915_READ(DBUF_CTL_S2) & DBUF_POWER_STATE))
- DRM_ERROR("DBuf power disable timeout!\n");
- else
- /*
- * FIXME: for now pretend that the first slice is always
- * enabled, see intel_enabled_dbuf_slices_num().
- */
- dev_priv->enabled_slices = 1;
+ /*
+ * Disable all slices
+ */
+ dev_priv->enabled_slices = 0;
+ icl_program_dbuf_slices(dev_priv);
}
static void icl_mbus_init(struct drm_i915_private *dev_priv)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h b/drivers/gpu/drm/i915/display/intel_display_power.h
index 1da04f3e0fb3..0d9f87607eac 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.h
+++ b/drivers/gpu/drm/i915/display/intel_display_power.h
@@ -311,8 +311,13 @@ intel_display_power_put_async(struct drm_i915_private *i915,
for ((wf) = intel_display_power_get((i915), (domain)); (wf); \
intel_display_power_put_async((i915), (domain), (wf)), (wf) = 0)
+#define DBUF_S1_BIT BIT(0)
+#define DBUF_S2_BIT BIT(1)
+
void icl_dbuf_slices_update(struct drm_i915_private *dev_priv,
u8 req_slices);
+void icl_program_dbuf_slices(struct drm_i915_private *dev_priv);
+int intel_dbuf_max_slices(struct drm_i915_private *dev_priv);
void chv_phy_powergate_lanes(struct intel_encoder *encoder,
bool override, unsigned int mask);
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index da3e9b5752ac..a050222240e4 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -614,7 +614,8 @@ static const struct intel_device_info intel_cherryview_info = {
.has_gt_uc = 1, \
.display.has_hdcp = 1, \
.display.has_ipc = 1, \
- .ddb_size = 896
+ .ddb_size = 896, \
+ .num_supported_dbuf_slices = 1
#define SKL_PLATFORM \
GEN9_FEATURES, \
@@ -649,6 +650,7 @@ static const struct intel_device_info intel_skylake_gt4_info = {
#define GEN9_LP_FEATURES \
GEN(9), \
.is_lp = 1, \
+ .num_supported_dbuf_slices = 1, \
.display.has_hotplug = 1, \
.engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \
.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), \
@@ -737,6 +739,7 @@ static const struct intel_device_info intel_coffeelake_gt3_info = {
GEN9_FEATURES, \
GEN(10), \
.ddb_size = 1024, \
+ .num_supported_dbuf_slices = 1, \
.display.has_dsc = 1, \
.has_coherent_ggtt = false, \
GLK_COLORS
@@ -773,6 +776,7 @@ static const struct intel_device_info intel_cannonlake_info = {
}, \
GEN(11), \
.ddb_size = 2048, \
+ .num_supported_dbuf_slices = 2, \
.has_logical_ring_elsq = 1, \
.color = { .degamma_lut_size = 33, .gamma_lut_size = 262145 }
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index 4bdf8a6cfb47..4a9f54a900be 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -180,6 +180,7 @@ struct intel_device_info {
} display;
u16 ddb_size; /* in blocks */
+ u8 num_supported_dbuf_slices; /* number of DBuf slices */
/* Register offsets for the various display pipes and transcoders */
int pipe_offsets[I915_MAX_TRANSCODERS];
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index a93b4385de4b..8b2a1495454c 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3599,24 +3599,20 @@ bool ilk_disable_lp_wm(struct drm_device *dev)
return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL);
}
-u8 intel_enabled_dbuf_slices_num(struct drm_i915_private *dev_priv)
+u8 intel_enabled_dbuf_slices_mask(struct drm_i915_private *dev_priv)
{
- u8 enabled_slices;
-
- /* Slice 1 will always be enabled */
- enabled_slices = 1;
+ u8 enabled_slices = 0;
/* Gen prior to GEN11 have only one DBuf slice */
if (INTEL_GEN(dev_priv) < 11)
- return enabled_slices;
+ return DBUF_S1_BIT;
- /*
- * FIXME: for now we'll only ever use 1 slice; pretend that we have
- * only that 1 slice enabled until we have a proper way for on-demand
- * toggling of the second slice.
- */
- if (0 && I915_READ(DBUF_CTL_S2) & DBUF_POWER_STATE)
- enabled_slices++;
+ /* Check if second DBuf slice is enabled */
+ if (I915_READ(DBUF_CTL_S1) & DBUF_POWER_STATE)
+ enabled_slices |= DBUF_S1_BIT;
+
+ if (I915_READ(DBUF_CTL_S2) & DBUF_POWER_STATE)
+ enabled_slices |= DBUF_S2_BIT;
return enabled_slices;
}
@@ -3826,8 +3822,6 @@ static u16 intel_get_ddb_size(struct drm_i915_private *dev_priv,
{
struct drm_atomic_state *state = crtc_state->uapi.state;
struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
- const struct drm_display_mode *adjusted_mode;
- u64 total_data_bw;
u16 ddb_size = INTEL_INFO(dev_priv)->ddb_size;
WARN_ON(ddb_size == 0);
@@ -3835,23 +3829,8 @@ static u16 intel_get_ddb_size(struct drm_i915_private *dev_priv,
if (INTEL_GEN(dev_priv) < 11)
return ddb_size - 4; /* 4 blocks for bypass path allocation */
- adjusted_mode = &crtc_state->hw.adjusted_mode;
- total_data_bw = total_data_rate * drm_mode_vrefresh(adjusted_mode);
-
- /*
- * 12GB/s is maximum BW supported by single DBuf slice.
- *
- * FIXME dbuf slice code is broken:
- * - must wait for planes to stop using the slice before powering it off
- * - plane straddling both slices is illegal in multi-pipe scenarios
- * - should validate we stay within the hw bandwidth limits
- */
- if (0 && (num_active > 1 || total_data_bw >= GBps(12))) {
- intel_state->enabled_slices = 2;
- } else {
- intel_state->enabled_slices = 1;
- ddb_size /= 2;
- }
+ intel_state->enabled_slices = DBUF_S1_BIT;
+ ddb_size /= 2;
return ddb_size;
}
@@ -4048,7 +4027,7 @@ void skl_pipe_ddb_get_hw_state(struct intel_crtc *crtc,
void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv)
{
- dev_priv->enabled_slices = intel_enabled_dbuf_slices_num(dev_priv);
+ dev_priv->enabled_slices = intel_enabled_dbuf_slices_mask(dev_priv);
}
/*
diff --git a/drivers/gpu/drm/i915/intel_pm.h b/drivers/gpu/drm/i915/intel_pm.h
index 4aafae4c8e0d..39cc42d1f84e 100644
--- a/drivers/gpu/drm/i915/intel_pm.h
+++ b/drivers/gpu/drm/i915/intel_pm.h
@@ -33,7 +33,7 @@ void g4x_wm_get_hw_state(struct drm_i915_private *dev_priv);
void vlv_wm_get_hw_state(struct drm_i915_private *dev_priv);
void ilk_wm_get_hw_state(struct drm_i915_private *dev_priv);
void skl_wm_get_hw_state(struct drm_i915_private *dev_priv);
-u8 intel_enabled_dbuf_slices_num(struct drm_i915_private *dev_priv);
+u8 intel_enabled_dbuf_slices_mask(struct drm_i915_private *dev_priv);
void skl_pipe_ddb_get_hw_state(struct intel_crtc *crtc,
struct skl_ddb_entry *ddb_y,
struct skl_ddb_entry *ddb_uv);
--
2.17.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [Intel-gfx] [PATCH v7 3/4] drm/i915: Manipulate DBuf slices properly
@ 2019-11-29 13:37 ` Stanislav Lisovskiy
0 siblings, 0 replies; 26+ messages in thread
From: Stanislav Lisovskiy @ 2019-11-29 13:37 UTC (permalink / raw)
To: intel-gfx
Start manipulating DBuf slices as a mask,
but not as a total number, as current approach
doesn't give us full control on all combinations
of slices, which we might need(like enabling S2
only can't enabled by setting enabled_slices=1).
Removed wrong code from intel_get_ddb_size as
it doesn't match to BSpec. For now still just
use DBuf slice until proper algorithm is implemented.
Other minor code refactoring to get prepared
for major DBuf assignment changes landed:
- As now enabled slices contain a mask
we still need some value which should
reflect how much DBuf slices are supported
by the platform, now device info contains
num_supported_dbuf_slices.
- Removed unneeded assertion as we are now
manipulating slices in a more proper way.
v2: Start using enabled_slices in dev_priv
Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 11 +-
.../drm/i915/display/intel_display_power.c | 100 ++++++++----------
.../drm/i915/display/intel_display_power.h | 5 +
drivers/gpu/drm/i915/i915_pci.c | 6 +-
drivers/gpu/drm/i915/intel_device_info.h | 1 +
drivers/gpu/drm/i915/intel_pm.c | 45 +++-----
drivers/gpu/drm/i915/intel_pm.h | 2 +-
7 files changed, 74 insertions(+), 96 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index db0830745f25..c73bdcefd242 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -13413,11 +13413,11 @@ static void verify_wm_state(struct intel_crtc *crtc,
skl_pipe_ddb_get_hw_state(crtc, hw->ddb_y, hw->ddb_uv);
- hw_enabled_slices = intel_enabled_dbuf_slices_num(dev_priv);
+ hw_enabled_slices = intel_enabled_dbuf_slices_mask(dev_priv);
if (INTEL_GEN(dev_priv) >= 11 &&
hw_enabled_slices != dev_priv->enabled_slices)
- DRM_ERROR("mismatch in DBUF Slices (expected %u, got %u)\n",
+ DRM_ERROR("mismatch in DBUF Slices (expected %x, got %x)\n",
dev_priv->enabled_slices,
hw_enabled_slices);
@@ -14642,10 +14642,11 @@ static void icl_dbuf_slice_pre_update(struct intel_atomic_state *state)
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
u8 hw_enabled_slices = dev_priv->enabled_slices;
u8 required_slices = state->enabled_slices;
+ u8 slices_union = hw_enabled_slices | required_slices;
/* If 2nd DBuf slice required, enable it here */
- if (INTEL_GEN(dev_priv) >= 11 && required_slices > hw_enabled_slices)
- icl_dbuf_slices_update(dev_priv, required_slices);
+ if (INTEL_GEN(dev_priv) >= 11 && required_slices != hw_enabled_slices)
+ icl_dbuf_slices_update(dev_priv, slices_union);
}
static void icl_dbuf_slice_post_update(struct intel_atomic_state *state)
@@ -14655,7 +14656,7 @@ static void icl_dbuf_slice_post_update(struct intel_atomic_state *state)
u8 required_slices = state->enabled_slices;
/* If 2nd DBuf slice is no more required disable it */
- if (INTEL_GEN(dev_priv) >= 11 && required_slices < hw_enabled_slices)
+ if (INTEL_GEN(dev_priv) >= 11 && required_slices != hw_enabled_slices)
icl_dbuf_slices_update(dev_priv, required_slices);
}
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index 4c3ede73e863..ef288892c8ce 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -1031,15 +1031,6 @@ static bool gen9_dc_off_power_well_enabled(struct drm_i915_private *dev_priv,
(I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5_DC6_MASK) == 0);
}
-static void gen9_assert_dbuf_enabled(struct drm_i915_private *dev_priv)
-{
- u32 tmp = I915_READ(DBUF_CTL);
-
- WARN((tmp & (DBUF_POWER_STATE | DBUF_POWER_REQUEST)) !=
- (DBUF_POWER_STATE | DBUF_POWER_REQUEST),
- "Unexpected DBuf power power state (0x%08x)\n", tmp);
-}
-
static void gen9_disable_dc_states(struct drm_i915_private *dev_priv)
{
struct intel_cdclk_state cdclk_state = {};
@@ -1055,8 +1046,6 @@ static void gen9_disable_dc_states(struct drm_i915_private *dev_priv)
/* Can't read out voltage_level so can't use intel_cdclk_changed() */
WARN_ON(intel_cdclk_needs_modeset(&dev_priv->cdclk.hw, &cdclk_state));
- gen9_assert_dbuf_enabled(dev_priv);
-
if (IS_GEN9_LP(dev_priv))
bxt_verify_ddi_phy_power_wells(dev_priv);
@@ -4254,72 +4243,71 @@ static void gen9_dbuf_disable(struct drm_i915_private *dev_priv)
intel_dbuf_slice_set(dev_priv, DBUF_CTL, false);
}
-static u8 intel_dbuf_max_slices(struct drm_i915_private *dev_priv)
+int intel_dbuf_max_slices(struct drm_i915_private *dev_priv)
{
- if (INTEL_GEN(dev_priv) < 11)
- return 1;
- return 2;
+ return INTEL_INFO(dev_priv)->num_supported_dbuf_slices;
+}
+
+void icl_program_dbuf_slices(struct drm_i915_private *dev_priv)
+{
+ const u8 hw_enabled_slices = dev_priv->enabled_slices;
+
+ icl_dbuf_slices_update(dev_priv, hw_enabled_slices);
}
void icl_dbuf_slices_update(struct drm_i915_private *dev_priv,
u8 req_slices)
{
- const u8 hw_enabled_slices = dev_priv->enabled_slices;
- bool ret;
+ int i;
+ int max_slices = intel_dbuf_max_slices(dev_priv);
- if (req_slices > intel_dbuf_max_slices(dev_priv)) {
+ if (hweight8(req_slices) > intel_dbuf_max_slices(dev_priv)) {
DRM_ERROR("Invalid number of dbuf slices requested\n");
return;
}
- if (req_slices == hw_enabled_slices || req_slices == 0)
- return;
+ DRM_DEBUG_KMS("Updating dbuf slices to %x\n", req_slices);
- if (req_slices > hw_enabled_slices)
- ret = intel_dbuf_slice_set(dev_priv, DBUF_CTL_S2, true);
- else
- ret = intel_dbuf_slice_set(dev_priv, DBUF_CTL_S2, false);
+ for (i = 0; i < max_slices; i++) {
+ int slice_bit = BIT(i);
+ bool slice_set = (slice_bit & req_slices) != 0;
+
+ switch (slice_bit) {
+ case DBUF_S1_BIT:
+ intel_dbuf_slice_set(dev_priv,
+ DBUF_CTL_S1,
+ slice_set);
+ break;
+ case DBUF_S2_BIT:
+ intel_dbuf_slice_set(dev_priv,
+ DBUF_CTL_S2,
+ slice_set);
+ break;
+ default:
+ MISSING_CASE(slice_bit);
+ }
+ }
- if (ret)
- dev_priv->enabled_slices = req_slices;
+ dev_priv->enabled_slices = req_slices;
}
static void icl_dbuf_enable(struct drm_i915_private *dev_priv)
{
- I915_WRITE(DBUF_CTL_S1, I915_READ(DBUF_CTL_S1) | DBUF_POWER_REQUEST);
- I915_WRITE(DBUF_CTL_S2, I915_READ(DBUF_CTL_S2) | DBUF_POWER_REQUEST);
- POSTING_READ(DBUF_CTL_S2);
-
- udelay(10);
-
- if (!(I915_READ(DBUF_CTL_S1) & DBUF_POWER_STATE) ||
- !(I915_READ(DBUF_CTL_S2) & DBUF_POWER_STATE))
- DRM_ERROR("DBuf power enable timeout\n");
- else
- /*
- * FIXME: for now pretend that we only have 1 slice, see
- * intel_enabled_dbuf_slices_num().
- */
- dev_priv->enabled_slices = 1;
+ /*
+ * Just power up 1 slice, we will
+ * figure out later which slices we have and what we need.
+ */
+ dev_priv->enabled_slices = DBUF_S1_BIT;
+ icl_program_dbuf_slices(dev_priv);
}
static void icl_dbuf_disable(struct drm_i915_private *dev_priv)
{
- I915_WRITE(DBUF_CTL_S1, I915_READ(DBUF_CTL_S1) & ~DBUF_POWER_REQUEST);
- I915_WRITE(DBUF_CTL_S2, I915_READ(DBUF_CTL_S2) & ~DBUF_POWER_REQUEST);
- POSTING_READ(DBUF_CTL_S2);
-
- udelay(10);
-
- if ((I915_READ(DBUF_CTL_S1) & DBUF_POWER_STATE) ||
- (I915_READ(DBUF_CTL_S2) & DBUF_POWER_STATE))
- DRM_ERROR("DBuf power disable timeout!\n");
- else
- /*
- * FIXME: for now pretend that the first slice is always
- * enabled, see intel_enabled_dbuf_slices_num().
- */
- dev_priv->enabled_slices = 1;
+ /*
+ * Disable all slices
+ */
+ dev_priv->enabled_slices = 0;
+ icl_program_dbuf_slices(dev_priv);
}
static void icl_mbus_init(struct drm_i915_private *dev_priv)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h b/drivers/gpu/drm/i915/display/intel_display_power.h
index 1da04f3e0fb3..0d9f87607eac 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.h
+++ b/drivers/gpu/drm/i915/display/intel_display_power.h
@@ -311,8 +311,13 @@ intel_display_power_put_async(struct drm_i915_private *i915,
for ((wf) = intel_display_power_get((i915), (domain)); (wf); \
intel_display_power_put_async((i915), (domain), (wf)), (wf) = 0)
+#define DBUF_S1_BIT BIT(0)
+#define DBUF_S2_BIT BIT(1)
+
void icl_dbuf_slices_update(struct drm_i915_private *dev_priv,
u8 req_slices);
+void icl_program_dbuf_slices(struct drm_i915_private *dev_priv);
+int intel_dbuf_max_slices(struct drm_i915_private *dev_priv);
void chv_phy_powergate_lanes(struct intel_encoder *encoder,
bool override, unsigned int mask);
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index da3e9b5752ac..a050222240e4 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -614,7 +614,8 @@ static const struct intel_device_info intel_cherryview_info = {
.has_gt_uc = 1, \
.display.has_hdcp = 1, \
.display.has_ipc = 1, \
- .ddb_size = 896
+ .ddb_size = 896, \
+ .num_supported_dbuf_slices = 1
#define SKL_PLATFORM \
GEN9_FEATURES, \
@@ -649,6 +650,7 @@ static const struct intel_device_info intel_skylake_gt4_info = {
#define GEN9_LP_FEATURES \
GEN(9), \
.is_lp = 1, \
+ .num_supported_dbuf_slices = 1, \
.display.has_hotplug = 1, \
.engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \
.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), \
@@ -737,6 +739,7 @@ static const struct intel_device_info intel_coffeelake_gt3_info = {
GEN9_FEATURES, \
GEN(10), \
.ddb_size = 1024, \
+ .num_supported_dbuf_slices = 1, \
.display.has_dsc = 1, \
.has_coherent_ggtt = false, \
GLK_COLORS
@@ -773,6 +776,7 @@ static const struct intel_device_info intel_cannonlake_info = {
}, \
GEN(11), \
.ddb_size = 2048, \
+ .num_supported_dbuf_slices = 2, \
.has_logical_ring_elsq = 1, \
.color = { .degamma_lut_size = 33, .gamma_lut_size = 262145 }
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index 4bdf8a6cfb47..4a9f54a900be 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -180,6 +180,7 @@ struct intel_device_info {
} display;
u16 ddb_size; /* in blocks */
+ u8 num_supported_dbuf_slices; /* number of DBuf slices */
/* Register offsets for the various display pipes and transcoders */
int pipe_offsets[I915_MAX_TRANSCODERS];
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index a93b4385de4b..8b2a1495454c 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3599,24 +3599,20 @@ bool ilk_disable_lp_wm(struct drm_device *dev)
return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL);
}
-u8 intel_enabled_dbuf_slices_num(struct drm_i915_private *dev_priv)
+u8 intel_enabled_dbuf_slices_mask(struct drm_i915_private *dev_priv)
{
- u8 enabled_slices;
-
- /* Slice 1 will always be enabled */
- enabled_slices = 1;
+ u8 enabled_slices = 0;
/* Gen prior to GEN11 have only one DBuf slice */
if (INTEL_GEN(dev_priv) < 11)
- return enabled_slices;
+ return DBUF_S1_BIT;
- /*
- * FIXME: for now we'll only ever use 1 slice; pretend that we have
- * only that 1 slice enabled until we have a proper way for on-demand
- * toggling of the second slice.
- */
- if (0 && I915_READ(DBUF_CTL_S2) & DBUF_POWER_STATE)
- enabled_slices++;
+ /* Check if second DBuf slice is enabled */
+ if (I915_READ(DBUF_CTL_S1) & DBUF_POWER_STATE)
+ enabled_slices |= DBUF_S1_BIT;
+
+ if (I915_READ(DBUF_CTL_S2) & DBUF_POWER_STATE)
+ enabled_slices |= DBUF_S2_BIT;
return enabled_slices;
}
@@ -3826,8 +3822,6 @@ static u16 intel_get_ddb_size(struct drm_i915_private *dev_priv,
{
struct drm_atomic_state *state = crtc_state->uapi.state;
struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
- const struct drm_display_mode *adjusted_mode;
- u64 total_data_bw;
u16 ddb_size = INTEL_INFO(dev_priv)->ddb_size;
WARN_ON(ddb_size == 0);
@@ -3835,23 +3829,8 @@ static u16 intel_get_ddb_size(struct drm_i915_private *dev_priv,
if (INTEL_GEN(dev_priv) < 11)
return ddb_size - 4; /* 4 blocks for bypass path allocation */
- adjusted_mode = &crtc_state->hw.adjusted_mode;
- total_data_bw = total_data_rate * drm_mode_vrefresh(adjusted_mode);
-
- /*
- * 12GB/s is maximum BW supported by single DBuf slice.
- *
- * FIXME dbuf slice code is broken:
- * - must wait for planes to stop using the slice before powering it off
- * - plane straddling both slices is illegal in multi-pipe scenarios
- * - should validate we stay within the hw bandwidth limits
- */
- if (0 && (num_active > 1 || total_data_bw >= GBps(12))) {
- intel_state->enabled_slices = 2;
- } else {
- intel_state->enabled_slices = 1;
- ddb_size /= 2;
- }
+ intel_state->enabled_slices = DBUF_S1_BIT;
+ ddb_size /= 2;
return ddb_size;
}
@@ -4048,7 +4027,7 @@ void skl_pipe_ddb_get_hw_state(struct intel_crtc *crtc,
void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv)
{
- dev_priv->enabled_slices = intel_enabled_dbuf_slices_num(dev_priv);
+ dev_priv->enabled_slices = intel_enabled_dbuf_slices_mask(dev_priv);
}
/*
diff --git a/drivers/gpu/drm/i915/intel_pm.h b/drivers/gpu/drm/i915/intel_pm.h
index 4aafae4c8e0d..39cc42d1f84e 100644
--- a/drivers/gpu/drm/i915/intel_pm.h
+++ b/drivers/gpu/drm/i915/intel_pm.h
@@ -33,7 +33,7 @@ void g4x_wm_get_hw_state(struct drm_i915_private *dev_priv);
void vlv_wm_get_hw_state(struct drm_i915_private *dev_priv);
void ilk_wm_get_hw_state(struct drm_i915_private *dev_priv);
void skl_wm_get_hw_state(struct drm_i915_private *dev_priv);
-u8 intel_enabled_dbuf_slices_num(struct drm_i915_private *dev_priv);
+u8 intel_enabled_dbuf_slices_mask(struct drm_i915_private *dev_priv);
void skl_pipe_ddb_get_hw_state(struct intel_crtc *crtc,
struct skl_ddb_entry *ddb_y,
struct skl_ddb_entry *ddb_uv);
--
2.17.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PATCH v7 4/4] drm/i915: Correctly map DBUF slices to pipes
@ 2019-11-29 13:37 ` Stanislav Lisovskiy
0 siblings, 0 replies; 26+ messages in thread
From: Stanislav Lisovskiy @ 2019-11-29 13:37 UTC (permalink / raw)
To: intel-gfx
Added proper DBuf slice mapping to correspondent
pipes, depending on pipe configuration as stated
in BSpec.
v2:
- Remove unneeded braces
- Stop using macro for DBuf assignments as
it seems to reduce readability.
v3: Start using enabled slices mask in dev_priv
Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
---
drivers/gpu/drm/i915/intel_pm.c | 226 ++++++++++++++++++++++++++++++--
1 file changed, 216 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 8b2a1495454c..f36b1545d9ab 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3815,13 +3815,30 @@ bool intel_can_enable_sagv(struct intel_atomic_state *state)
return true;
}
+/*
+ * Calculate initial DBuf slice offset, based on slice size
+ * and mask(i.e if slice size is 1024 and second slice is enabled
+ * offset would be 1024)
+ */
+static u32 icl_get_first_dbuf_slice_offset(u32 dbuf_slice_mask,
+ u32 slice_size, u32 ddb_size)
+{
+ u32 offset = 0;
+
+ if (!dbuf_slice_mask)
+ return 0;
+
+ offset = (ffs(dbuf_slice_mask) - 1) * slice_size;
+
+ WARN_ON(offset >= ddb_size);
+ return offset;
+}
+
static u16 intel_get_ddb_size(struct drm_i915_private *dev_priv,
const struct intel_crtc_state *crtc_state,
const u64 total_data_rate,
const int num_active)
{
- struct drm_atomic_state *state = crtc_state->uapi.state;
- struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
u16 ddb_size = INTEL_INFO(dev_priv)->ddb_size;
WARN_ON(ddb_size == 0);
@@ -3829,12 +3846,13 @@ static u16 intel_get_ddb_size(struct drm_i915_private *dev_priv,
if (INTEL_GEN(dev_priv) < 11)
return ddb_size - 4; /* 4 blocks for bypass path allocation */
- intel_state->enabled_slices = DBUF_S1_BIT;
- ddb_size /= 2;
-
return ddb_size;
}
+u32 i915_possible_dbuf_slices(struct drm_i915_private *dev_priv,
+ int pipe, u32 active_pipes,
+ const struct intel_crtc_state *crtc_state);
+
static void
skl_ddb_get_pipe_allocation_limits(struct drm_i915_private *dev_priv,
const struct intel_crtc_state *crtc_state,
@@ -3849,7 +3867,14 @@ skl_ddb_get_pipe_allocation_limits(struct drm_i915_private *dev_priv,
u32 pipe_width = 0, total_width = 0, width_before_pipe = 0;
enum pipe for_pipe = to_intel_crtc(for_crtc)->pipe;
u16 ddb_size;
+ u32 ddb_range_size;
u32 i;
+ u32 dbuf_slice_mask;
+ u32 active_pipes;
+ u32 offset;
+ u32 slice_size;
+ u32 total_slice_mask;
+ u32 start, end;
if (WARN_ON(!state) || !crtc_state->hw.active) {
alloc->start = 0;
@@ -3858,14 +3883,19 @@ skl_ddb_get_pipe_allocation_limits(struct drm_i915_private *dev_priv,
return;
}
- if (intel_state->active_pipe_changes)
+ if (intel_state->active_pipe_changes) {
*num_active = hweight8(intel_state->active_pipes);
- else
+ active_pipes = intel_state->active_pipes;
+ } else {
*num_active = hweight8(dev_priv->active_pipes);
+ active_pipes = dev_priv->active_pipes;
+ }
ddb_size = intel_get_ddb_size(dev_priv, crtc_state, total_data_rate,
*num_active);
+ slice_size = ddb_size / INTEL_INFO(dev_priv)->num_supported_dbuf_slices;
+
/*
* If the state doesn't change the active CRTC's or there is no
* modeset request, then there's no need to recalculate;
@@ -3883,18 +3913,68 @@ skl_ddb_get_pipe_allocation_limits(struct drm_i915_private *dev_priv,
return;
}
+ /*
+ * Get allowed DBuf slices for correspondent pipe and platform.
+ */
+ dbuf_slice_mask = i915_possible_dbuf_slices(dev_priv, for_pipe,
+ active_pipes, crtc_state);
+
+ DRM_DEBUG_KMS("DBuf slice mask %x pipe %d active pipes %x\n",
+ dbuf_slice_mask,
+ for_pipe, active_pipes);
+
+ /*
+ * Figure out at which DBuf slice we start, i.e if we start at Dbuf S2
+ * and slice size is 1024, the offset would be 1024
+ */
+ offset = icl_get_first_dbuf_slice_offset(dbuf_slice_mask,
+ slice_size, ddb_size);
+
+ /*
+ * Figure out total size of allowed DBuf slices, which is basically
+ * a number of allowed slices for that pipe multiplied by slice size.
+ * Inside of this
+ * range ddb entries are still allocated in proportion to display width.
+ */
+ ddb_range_size = hweight8(dbuf_slice_mask) * slice_size;
+
/*
* Watermark/ddb requirement highly depends upon width of the
* framebuffer, So instead of allocating DDB equally among pipes
* distribute DDB based on resolution/width of the display.
*/
+ total_slice_mask = dbuf_slice_mask;
for_each_new_intel_crtc_in_state(intel_state, crtc, crtc_state, i) {
const struct drm_display_mode *adjusted_mode =
&crtc_state->hw.adjusted_mode;
enum pipe pipe = crtc->pipe;
int hdisplay, vdisplay;
+ u32 pipe_dbuf_slice_mask =
+ i915_possible_dbuf_slices(dev_priv,
+ pipe,
+ active_pipes,
+ crtc_state);
+
+ if (!crtc_state->hw.active)
+ continue;
+
+ /*
+ * According to BSpec pipe can share one dbuf slice with another
+ * pipes or pipe can use multiple dbufs, in both cases we
+ * account for other pipes only if they have exactly same mask.
+ * However we need to account how many slices we should enable
+ * in total.
+ */
+ total_slice_mask |= pipe_dbuf_slice_mask;
- if (!crtc_state->hw.enable)
+ /*
+ * Do not account pipes using other slice sets
+ * luckily as of current BSpec slice sets do not partially
+ * intersect(pipes share either same one slice or same slice set
+ * i.e no partial intersection), so it is enough to check for
+ * equality for now.
+ */
+ if (dbuf_slice_mask != pipe_dbuf_slice_mask)
continue;
drm_mode_get_hv_timing(adjusted_mode, &hdisplay, &vdisplay);
@@ -3906,8 +3986,19 @@ skl_ddb_get_pipe_allocation_limits(struct drm_i915_private *dev_priv,
pipe_width = hdisplay;
}
- alloc->start = ddb_size * width_before_pipe / total_width;
- alloc->end = ddb_size * (width_before_pipe + pipe_width) / total_width;
+ intel_state->enabled_slices = total_slice_mask;
+
+ start = ddb_range_size * width_before_pipe / total_width;
+ end = ddb_range_size * (width_before_pipe + pipe_width) / total_width;
+
+ alloc->start = offset + start;
+ alloc->end = offset + end;
+
+ DRM_DEBUG_KMS("Pipe %d ddb %d-%d\n", for_pipe,
+ alloc->start, alloc->end);
+ DRM_DEBUG_KMS("Enabled ddb slices mask %x num supported %d\n",
+ intel_state->enabled_slices,
+ INTEL_INFO(dev_priv)->num_supported_dbuf_slices);
}
static int skl_compute_wm_params(const struct intel_crtc_state *crtc_state,
@@ -4077,6 +4168,121 @@ skl_plane_downscale_amount(const struct intel_crtc_state *crtc_state,
return mul_fixed16(downscale_w, downscale_h);
}
+struct dbuf_slice_conf_entry {
+ u32 active_pipes;
+ u32 dbuf_mask[I915_MAX_PIPES];
+};
+
+/*
+ * Table taken from Bspec 12716
+ * Pipes do have some preferred DBuf slice affinity,
+ * plus there are some hardcoded requirements on how
+ * those should be distributed for multipipe scenarios.
+ * For more DBuf slices algorithm can get even more messy
+ * and less readable, so decided to use a table almost
+ * as is from BSpec itself - that way it is at least easier
+ * to compare, change and check.
+ */
+static struct dbuf_slice_conf_entry icl_allowed_dbufs[] = {
+ { BIT(PIPE_A), { DBUF_S1_BIT, 0, 0, 0 } },
+ { BIT(PIPE_B), { 0, DBUF_S1_BIT, 0, 0 } },
+ { BIT(PIPE_C), { 0, 0, DBUF_S2_BIT, 0 } },
+ { BIT(PIPE_A) | BIT(PIPE_B), { DBUF_S1_BIT, DBUF_S2_BIT, 0, 0 } },
+ { BIT(PIPE_A) | BIT(PIPE_C), { DBUF_S1_BIT, 0, DBUF_S2_BIT, 0 } },
+ { BIT(PIPE_B) | BIT(PIPE_C), { 0, DBUF_S1_BIT, DBUF_S2_BIT, 0 } },
+ { BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
+ { DBUF_S1_BIT, DBUF_S1_BIT, DBUF_S2_BIT, 0 } }
+};
+
+/*
+ * Table taken from Bspec 49255
+ * Pipes do have some preferred DBuf slice affinity,
+ * plus there are some hardcoded requirements on how
+ * those should be distributed for multipipe scenarios.
+ * For more DBuf slices algorithm can get even more messy
+ * and less readable, so decided to use a table almost
+ * as is from BSpec itself - that way it is at least easier
+ * to compare, change and check.
+ */
+static struct dbuf_slice_conf_entry tgl_allowed_dbufs[] = {
+ { BIT(PIPE_A), { DBUF_S1_BIT | DBUF_S2_BIT, 0, 0, 0 } },
+ { BIT(PIPE_B), { 0, DBUF_S1_BIT | DBUF_S2_BIT, 0, 0 } },
+ { BIT(PIPE_C), { 0, 0, DBUF_S1_BIT | DBUF_S2_BIT, 0 } },
+ { BIT(PIPE_D), { 0, 0, 0, DBUF_S1_BIT | DBUF_S2_BIT } },
+ { BIT(PIPE_A) | BIT(PIPE_B), { DBUF_S2_BIT, DBUF_S1_BIT, 0, 0 } },
+ { BIT(PIPE_A) | BIT(PIPE_C), { DBUF_S1_BIT, 0, DBUF_S2_BIT, 0 } },
+ { BIT(PIPE_A) | BIT(PIPE_D), { DBUF_S1_BIT, 0, 0, DBUF_S2_BIT } },
+ { BIT(PIPE_B) | BIT(PIPE_C), { 0, DBUF_S1_BIT, DBUF_S2_BIT, 0 } },
+ { BIT(PIPE_B) | BIT(PIPE_D), { 0, DBUF_S1_BIT, 0, DBUF_S2_BIT } },
+ { BIT(PIPE_C) | BIT(PIPE_D), { 0, 0, DBUF_S2_BIT, DBUF_S2_BIT } },
+ { BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
+ { DBUF_S1_BIT, DBUF_S1_BIT, DBUF_S2_BIT, 0 } },
+ { BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_D),
+ { DBUF_S1_BIT, DBUF_S1_BIT, 0, DBUF_S2_BIT } },
+ { BIT(PIPE_A) | BIT(PIPE_C) | BIT(PIPE_D),
+ { DBUF_S1_BIT, 0, DBUF_S2_BIT, DBUF_S2_BIT } },
+ { BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),
+ { 0, DBUF_S1_BIT, DBUF_S2_BIT, DBUF_S2_BIT } },
+ { BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),
+ { DBUF_S1_BIT, DBUF_S1_BIT, DBUF_S2_BIT, DBUF_S2_BIT } },
+};
+
+static u32 i915_find_pipe_conf(int pipe,
+ u32 active_pipes,
+ const struct dbuf_slice_conf_entry *dbuf_slices,
+ int size)
+{
+ int i;
+
+ for (i = 0; i < size; i++) {
+ if (dbuf_slices[i].active_pipes == active_pipes)
+ return dbuf_slices[i].dbuf_mask[pipe];
+ }
+ return 0;
+}
+
+/*
+ * This function finds an entry with same enabled pipe configuration and
+ * returns correspondent DBuf slice mask as stated in BSpec for particular
+ * platform.
+ */
+static u32 icl_possible_dbuf_slices(int pipe,
+ u32 active_pipes,
+ const struct intel_crtc_state *crtc_state)
+{
+ return i915_find_pipe_conf(pipe, active_pipes,
+ icl_allowed_dbufs,
+ ARRAY_SIZE(icl_allowed_dbufs));
+}
+
+static u32 tgl_possible_dbuf_slices(int pipe,
+ u32 active_pipes,
+ const struct intel_crtc_state *crtc_state)
+{
+ return i915_find_pipe_conf(pipe, active_pipes,
+ tgl_allowed_dbufs,
+ ARRAY_SIZE(tgl_allowed_dbufs));
+}
+
+u32 i915_possible_dbuf_slices(struct drm_i915_private *dev_priv,
+ int pipe, u32 active_pipes,
+ const struct intel_crtc_state *crtc_state)
+{
+ if (IS_GEN(dev_priv, 11))
+ return icl_possible_dbuf_slices(pipe,
+ active_pipes,
+ crtc_state);
+ else if (IS_GEN(dev_priv, 12))
+ return tgl_possible_dbuf_slices(pipe,
+ active_pipes,
+ crtc_state);
+ /*
+ * For anything else just return one slice yet.
+ * Should be extended for other platforms.
+ */
+ return DBUF_S1_BIT;
+}
+
static u64
skl_plane_relative_data_rate(const struct intel_crtc_state *crtc_state,
const struct intel_plane_state *plane_state,
--
2.17.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [Intel-gfx] [PATCH v7 4/4] drm/i915: Correctly map DBUF slices to pipes
@ 2019-11-29 13:37 ` Stanislav Lisovskiy
0 siblings, 0 replies; 26+ messages in thread
From: Stanislav Lisovskiy @ 2019-11-29 13:37 UTC (permalink / raw)
To: intel-gfx
Added proper DBuf slice mapping to correspondent
pipes, depending on pipe configuration as stated
in BSpec.
v2:
- Remove unneeded braces
- Stop using macro for DBuf assignments as
it seems to reduce readability.
v3: Start using enabled slices mask in dev_priv
Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
---
drivers/gpu/drm/i915/intel_pm.c | 226 ++++++++++++++++++++++++++++++--
1 file changed, 216 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 8b2a1495454c..f36b1545d9ab 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3815,13 +3815,30 @@ bool intel_can_enable_sagv(struct intel_atomic_state *state)
return true;
}
+/*
+ * Calculate initial DBuf slice offset, based on slice size
+ * and mask(i.e if slice size is 1024 and second slice is enabled
+ * offset would be 1024)
+ */
+static u32 icl_get_first_dbuf_slice_offset(u32 dbuf_slice_mask,
+ u32 slice_size, u32 ddb_size)
+{
+ u32 offset = 0;
+
+ if (!dbuf_slice_mask)
+ return 0;
+
+ offset = (ffs(dbuf_slice_mask) - 1) * slice_size;
+
+ WARN_ON(offset >= ddb_size);
+ return offset;
+}
+
static u16 intel_get_ddb_size(struct drm_i915_private *dev_priv,
const struct intel_crtc_state *crtc_state,
const u64 total_data_rate,
const int num_active)
{
- struct drm_atomic_state *state = crtc_state->uapi.state;
- struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
u16 ddb_size = INTEL_INFO(dev_priv)->ddb_size;
WARN_ON(ddb_size == 0);
@@ -3829,12 +3846,13 @@ static u16 intel_get_ddb_size(struct drm_i915_private *dev_priv,
if (INTEL_GEN(dev_priv) < 11)
return ddb_size - 4; /* 4 blocks for bypass path allocation */
- intel_state->enabled_slices = DBUF_S1_BIT;
- ddb_size /= 2;
-
return ddb_size;
}
+u32 i915_possible_dbuf_slices(struct drm_i915_private *dev_priv,
+ int pipe, u32 active_pipes,
+ const struct intel_crtc_state *crtc_state);
+
static void
skl_ddb_get_pipe_allocation_limits(struct drm_i915_private *dev_priv,
const struct intel_crtc_state *crtc_state,
@@ -3849,7 +3867,14 @@ skl_ddb_get_pipe_allocation_limits(struct drm_i915_private *dev_priv,
u32 pipe_width = 0, total_width = 0, width_before_pipe = 0;
enum pipe for_pipe = to_intel_crtc(for_crtc)->pipe;
u16 ddb_size;
+ u32 ddb_range_size;
u32 i;
+ u32 dbuf_slice_mask;
+ u32 active_pipes;
+ u32 offset;
+ u32 slice_size;
+ u32 total_slice_mask;
+ u32 start, end;
if (WARN_ON(!state) || !crtc_state->hw.active) {
alloc->start = 0;
@@ -3858,14 +3883,19 @@ skl_ddb_get_pipe_allocation_limits(struct drm_i915_private *dev_priv,
return;
}
- if (intel_state->active_pipe_changes)
+ if (intel_state->active_pipe_changes) {
*num_active = hweight8(intel_state->active_pipes);
- else
+ active_pipes = intel_state->active_pipes;
+ } else {
*num_active = hweight8(dev_priv->active_pipes);
+ active_pipes = dev_priv->active_pipes;
+ }
ddb_size = intel_get_ddb_size(dev_priv, crtc_state, total_data_rate,
*num_active);
+ slice_size = ddb_size / INTEL_INFO(dev_priv)->num_supported_dbuf_slices;
+
/*
* If the state doesn't change the active CRTC's or there is no
* modeset request, then there's no need to recalculate;
@@ -3883,18 +3913,68 @@ skl_ddb_get_pipe_allocation_limits(struct drm_i915_private *dev_priv,
return;
}
+ /*
+ * Get allowed DBuf slices for correspondent pipe and platform.
+ */
+ dbuf_slice_mask = i915_possible_dbuf_slices(dev_priv, for_pipe,
+ active_pipes, crtc_state);
+
+ DRM_DEBUG_KMS("DBuf slice mask %x pipe %d active pipes %x\n",
+ dbuf_slice_mask,
+ for_pipe, active_pipes);
+
+ /*
+ * Figure out at which DBuf slice we start, i.e if we start at Dbuf S2
+ * and slice size is 1024, the offset would be 1024
+ */
+ offset = icl_get_first_dbuf_slice_offset(dbuf_slice_mask,
+ slice_size, ddb_size);
+
+ /*
+ * Figure out total size of allowed DBuf slices, which is basically
+ * a number of allowed slices for that pipe multiplied by slice size.
+ * Inside of this
+ * range ddb entries are still allocated in proportion to display width.
+ */
+ ddb_range_size = hweight8(dbuf_slice_mask) * slice_size;
+
/*
* Watermark/ddb requirement highly depends upon width of the
* framebuffer, So instead of allocating DDB equally among pipes
* distribute DDB based on resolution/width of the display.
*/
+ total_slice_mask = dbuf_slice_mask;
for_each_new_intel_crtc_in_state(intel_state, crtc, crtc_state, i) {
const struct drm_display_mode *adjusted_mode =
&crtc_state->hw.adjusted_mode;
enum pipe pipe = crtc->pipe;
int hdisplay, vdisplay;
+ u32 pipe_dbuf_slice_mask =
+ i915_possible_dbuf_slices(dev_priv,
+ pipe,
+ active_pipes,
+ crtc_state);
+
+ if (!crtc_state->hw.active)
+ continue;
+
+ /*
+ * According to BSpec pipe can share one dbuf slice with another
+ * pipes or pipe can use multiple dbufs, in both cases we
+ * account for other pipes only if they have exactly same mask.
+ * However we need to account how many slices we should enable
+ * in total.
+ */
+ total_slice_mask |= pipe_dbuf_slice_mask;
- if (!crtc_state->hw.enable)
+ /*
+ * Do not account pipes using other slice sets
+ * luckily as of current BSpec slice sets do not partially
+ * intersect(pipes share either same one slice or same slice set
+ * i.e no partial intersection), so it is enough to check for
+ * equality for now.
+ */
+ if (dbuf_slice_mask != pipe_dbuf_slice_mask)
continue;
drm_mode_get_hv_timing(adjusted_mode, &hdisplay, &vdisplay);
@@ -3906,8 +3986,19 @@ skl_ddb_get_pipe_allocation_limits(struct drm_i915_private *dev_priv,
pipe_width = hdisplay;
}
- alloc->start = ddb_size * width_before_pipe / total_width;
- alloc->end = ddb_size * (width_before_pipe + pipe_width) / total_width;
+ intel_state->enabled_slices = total_slice_mask;
+
+ start = ddb_range_size * width_before_pipe / total_width;
+ end = ddb_range_size * (width_before_pipe + pipe_width) / total_width;
+
+ alloc->start = offset + start;
+ alloc->end = offset + end;
+
+ DRM_DEBUG_KMS("Pipe %d ddb %d-%d\n", for_pipe,
+ alloc->start, alloc->end);
+ DRM_DEBUG_KMS("Enabled ddb slices mask %x num supported %d\n",
+ intel_state->enabled_slices,
+ INTEL_INFO(dev_priv)->num_supported_dbuf_slices);
}
static int skl_compute_wm_params(const struct intel_crtc_state *crtc_state,
@@ -4077,6 +4168,121 @@ skl_plane_downscale_amount(const struct intel_crtc_state *crtc_state,
return mul_fixed16(downscale_w, downscale_h);
}
+struct dbuf_slice_conf_entry {
+ u32 active_pipes;
+ u32 dbuf_mask[I915_MAX_PIPES];
+};
+
+/*
+ * Table taken from Bspec 12716
+ * Pipes do have some preferred DBuf slice affinity,
+ * plus there are some hardcoded requirements on how
+ * those should be distributed for multipipe scenarios.
+ * For more DBuf slices algorithm can get even more messy
+ * and less readable, so decided to use a table almost
+ * as is from BSpec itself - that way it is at least easier
+ * to compare, change and check.
+ */
+static struct dbuf_slice_conf_entry icl_allowed_dbufs[] = {
+ { BIT(PIPE_A), { DBUF_S1_BIT, 0, 0, 0 } },
+ { BIT(PIPE_B), { 0, DBUF_S1_BIT, 0, 0 } },
+ { BIT(PIPE_C), { 0, 0, DBUF_S2_BIT, 0 } },
+ { BIT(PIPE_A) | BIT(PIPE_B), { DBUF_S1_BIT, DBUF_S2_BIT, 0, 0 } },
+ { BIT(PIPE_A) | BIT(PIPE_C), { DBUF_S1_BIT, 0, DBUF_S2_BIT, 0 } },
+ { BIT(PIPE_B) | BIT(PIPE_C), { 0, DBUF_S1_BIT, DBUF_S2_BIT, 0 } },
+ { BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
+ { DBUF_S1_BIT, DBUF_S1_BIT, DBUF_S2_BIT, 0 } }
+};
+
+/*
+ * Table taken from Bspec 49255
+ * Pipes do have some preferred DBuf slice affinity,
+ * plus there are some hardcoded requirements on how
+ * those should be distributed for multipipe scenarios.
+ * For more DBuf slices algorithm can get even more messy
+ * and less readable, so decided to use a table almost
+ * as is from BSpec itself - that way it is at least easier
+ * to compare, change and check.
+ */
+static struct dbuf_slice_conf_entry tgl_allowed_dbufs[] = {
+ { BIT(PIPE_A), { DBUF_S1_BIT | DBUF_S2_BIT, 0, 0, 0 } },
+ { BIT(PIPE_B), { 0, DBUF_S1_BIT | DBUF_S2_BIT, 0, 0 } },
+ { BIT(PIPE_C), { 0, 0, DBUF_S1_BIT | DBUF_S2_BIT, 0 } },
+ { BIT(PIPE_D), { 0, 0, 0, DBUF_S1_BIT | DBUF_S2_BIT } },
+ { BIT(PIPE_A) | BIT(PIPE_B), { DBUF_S2_BIT, DBUF_S1_BIT, 0, 0 } },
+ { BIT(PIPE_A) | BIT(PIPE_C), { DBUF_S1_BIT, 0, DBUF_S2_BIT, 0 } },
+ { BIT(PIPE_A) | BIT(PIPE_D), { DBUF_S1_BIT, 0, 0, DBUF_S2_BIT } },
+ { BIT(PIPE_B) | BIT(PIPE_C), { 0, DBUF_S1_BIT, DBUF_S2_BIT, 0 } },
+ { BIT(PIPE_B) | BIT(PIPE_D), { 0, DBUF_S1_BIT, 0, DBUF_S2_BIT } },
+ { BIT(PIPE_C) | BIT(PIPE_D), { 0, 0, DBUF_S2_BIT, DBUF_S2_BIT } },
+ { BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
+ { DBUF_S1_BIT, DBUF_S1_BIT, DBUF_S2_BIT, 0 } },
+ { BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_D),
+ { DBUF_S1_BIT, DBUF_S1_BIT, 0, DBUF_S2_BIT } },
+ { BIT(PIPE_A) | BIT(PIPE_C) | BIT(PIPE_D),
+ { DBUF_S1_BIT, 0, DBUF_S2_BIT, DBUF_S2_BIT } },
+ { BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),
+ { 0, DBUF_S1_BIT, DBUF_S2_BIT, DBUF_S2_BIT } },
+ { BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),
+ { DBUF_S1_BIT, DBUF_S1_BIT, DBUF_S2_BIT, DBUF_S2_BIT } },
+};
+
+static u32 i915_find_pipe_conf(int pipe,
+ u32 active_pipes,
+ const struct dbuf_slice_conf_entry *dbuf_slices,
+ int size)
+{
+ int i;
+
+ for (i = 0; i < size; i++) {
+ if (dbuf_slices[i].active_pipes == active_pipes)
+ return dbuf_slices[i].dbuf_mask[pipe];
+ }
+ return 0;
+}
+
+/*
+ * This function finds an entry with same enabled pipe configuration and
+ * returns correspondent DBuf slice mask as stated in BSpec for particular
+ * platform.
+ */
+static u32 icl_possible_dbuf_slices(int pipe,
+ u32 active_pipes,
+ const struct intel_crtc_state *crtc_state)
+{
+ return i915_find_pipe_conf(pipe, active_pipes,
+ icl_allowed_dbufs,
+ ARRAY_SIZE(icl_allowed_dbufs));
+}
+
+static u32 tgl_possible_dbuf_slices(int pipe,
+ u32 active_pipes,
+ const struct intel_crtc_state *crtc_state)
+{
+ return i915_find_pipe_conf(pipe, active_pipes,
+ tgl_allowed_dbufs,
+ ARRAY_SIZE(tgl_allowed_dbufs));
+}
+
+u32 i915_possible_dbuf_slices(struct drm_i915_private *dev_priv,
+ int pipe, u32 active_pipes,
+ const struct intel_crtc_state *crtc_state)
+{
+ if (IS_GEN(dev_priv, 11))
+ return icl_possible_dbuf_slices(pipe,
+ active_pipes,
+ crtc_state);
+ else if (IS_GEN(dev_priv, 12))
+ return tgl_possible_dbuf_slices(pipe,
+ active_pipes,
+ crtc_state);
+ /*
+ * For anything else just return one slice yet.
+ * Should be extended for other platforms.
+ */
+ return DBUF_S1_BIT;
+}
+
static u64
skl_plane_relative_data_rate(const struct intel_crtc_state *crtc_state,
const struct intel_plane_state *plane_state,
--
2.17.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 26+ messages in thread
* ✓ Fi.CI.BAT: success for Enable second DBuf slice for ICL and TGL (rev3)
@ 2019-11-29 21:10 ` Patchwork
0 siblings, 0 replies; 26+ messages in thread
From: Patchwork @ 2019-11-29 21:10 UTC (permalink / raw)
To: Stanislav Lisovskiy; +Cc: intel-gfx
== Series Details ==
Series: Enable second DBuf slice for ICL and TGL (rev3)
URL : https://patchwork.freedesktop.org/series/70059/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7446 -> Patchwork_15513
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15513/index.html
Known issues
------------
Here are the changes found in Patchwork_15513 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@i915_module_load@reload-with-fault-injection:
- fi-icl-u3: [PASS][1] -> [INCOMPLETE][2] ([fdo#107713])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7446/fi-icl-u3/igt@i915_module_load@reload-with-fault-injection.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15513/fi-icl-u3/igt@i915_module_load@reload-with-fault-injection.html
* igt@i915_pm_rpm@module-reload:
- fi-skl-lmem: [PASS][3] -> [DMESG-WARN][4] ([fdo#112261])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7446/fi-skl-lmem/igt@i915_pm_rpm@module-reload.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15513/fi-skl-lmem/igt@i915_pm_rpm@module-reload.html
#### Possible fixes ####
* igt@i915_selftest@live_blt:
- fi-bsw-n3050: [DMESG-FAIL][5] ([fdo#112176]) -> [PASS][6]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7446/fi-bsw-n3050/igt@i915_selftest@live_blt.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15513/fi-bsw-n3050/igt@i915_selftest@live_blt.html
* igt@i915_selftest@live_dmabuf:
- fi-icl-y: [INCOMPLETE][7] ([fdo#107713]) -> [PASS][8]
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7446/fi-icl-y/igt@i915_selftest@live_dmabuf.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15513/fi-icl-y/igt@i915_selftest@live_dmabuf.html
* igt@kms_chamelium@dp-crc-fast:
- fi-kbl-7500u: [FAIL][9] ([fdo#109483] / [fdo#109635]) -> [PASS][10]
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7446/fi-kbl-7500u/igt@kms_chamelium@dp-crc-fast.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15513/fi-kbl-7500u/igt@kms_chamelium@dp-crc-fast.html
#### Warnings ####
* igt@kms_flip@basic-flip-vs-modeset:
- fi-kbl-x1275: [DMESG-WARN][11] ([fdo#103558] / [fdo#105602] / [fdo#105763]) -> [DMESG-WARN][12] ([fdo#103558] / [fdo#105602]) +8 similar issues
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7446/fi-kbl-x1275/igt@kms_flip@basic-flip-vs-modeset.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15513/fi-kbl-x1275/igt@kms_flip@basic-flip-vs-modeset.html
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
- fi-kbl-x1275: [DMESG-WARN][13] ([fdo#103558] / [fdo#105602]) -> [DMESG-WARN][14] ([fdo#103558] / [fdo#105602] / [fdo#105763]) +3 similar issues
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7446/fi-kbl-x1275/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15513/fi-kbl-x1275/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html
[fdo#103558]: https://bugs.freedesktop.org/show_bug.cgi?id=103558
[fdo#105602]: https://bugs.freedesktop.org/show_bug.cgi?id=105602
[fdo#105763]: https://bugs.freedesktop.org/show_bug.cgi?id=105763
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#109483]: https://bugs.freedesktop.org/show_bug.cgi?id=109483
[fdo#109635]: https://bugs.freedesktop.org/show_bug.cgi?id=109635
[fdo#112176]: https://bugs.freedesktop.org/show_bug.cgi?id=112176
[fdo#112261]: https://bugs.freedesktop.org/show_bug.cgi?id=112261
Participating hosts (50 -> 45)
------------------------------
Additional (1): fi-gdg-551
Missing (6): fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_7446 -> Patchwork_15513
CI-20190529: 20190529
CI_DRM_7446: dd4c99f05be238533a8a09f33b4c122f83d1f2be @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5318: 26ae6584ac03ad862d82f986302275a68bcccb29 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_15513: eebb0b2da903a777b34b46a0135fa3055f5fd971 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
eebb0b2da903 drm/i915: Correctly map DBUF slices to pipes
f873b7ab0960 drm/i915: Manipulate DBuf slices properly
b10c611ce1ad drm/i915: Move dbuf slice update to proper place
71bfd702d5e1 drm/i915: Remove skl_ddl_allocation struct
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15513/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 26+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for Enable second DBuf slice for ICL and TGL (rev3)
@ 2019-11-29 21:10 ` Patchwork
0 siblings, 0 replies; 26+ messages in thread
From: Patchwork @ 2019-11-29 21:10 UTC (permalink / raw)
To: Stanislav Lisovskiy; +Cc: intel-gfx
== Series Details ==
Series: Enable second DBuf slice for ICL and TGL (rev3)
URL : https://patchwork.freedesktop.org/series/70059/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7446 -> Patchwork_15513
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15513/index.html
Known issues
------------
Here are the changes found in Patchwork_15513 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@i915_module_load@reload-with-fault-injection:
- fi-icl-u3: [PASS][1] -> [INCOMPLETE][2] ([fdo#107713])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7446/fi-icl-u3/igt@i915_module_load@reload-with-fault-injection.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15513/fi-icl-u3/igt@i915_module_load@reload-with-fault-injection.html
* igt@i915_pm_rpm@module-reload:
- fi-skl-lmem: [PASS][3] -> [DMESG-WARN][4] ([fdo#112261])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7446/fi-skl-lmem/igt@i915_pm_rpm@module-reload.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15513/fi-skl-lmem/igt@i915_pm_rpm@module-reload.html
#### Possible fixes ####
* igt@i915_selftest@live_blt:
- fi-bsw-n3050: [DMESG-FAIL][5] ([fdo#112176]) -> [PASS][6]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7446/fi-bsw-n3050/igt@i915_selftest@live_blt.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15513/fi-bsw-n3050/igt@i915_selftest@live_blt.html
* igt@i915_selftest@live_dmabuf:
- fi-icl-y: [INCOMPLETE][7] ([fdo#107713]) -> [PASS][8]
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7446/fi-icl-y/igt@i915_selftest@live_dmabuf.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15513/fi-icl-y/igt@i915_selftest@live_dmabuf.html
* igt@kms_chamelium@dp-crc-fast:
- fi-kbl-7500u: [FAIL][9] ([fdo#109483] / [fdo#109635]) -> [PASS][10]
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7446/fi-kbl-7500u/igt@kms_chamelium@dp-crc-fast.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15513/fi-kbl-7500u/igt@kms_chamelium@dp-crc-fast.html
#### Warnings ####
* igt@kms_flip@basic-flip-vs-modeset:
- fi-kbl-x1275: [DMESG-WARN][11] ([fdo#103558] / [fdo#105602] / [fdo#105763]) -> [DMESG-WARN][12] ([fdo#103558] / [fdo#105602]) +8 similar issues
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7446/fi-kbl-x1275/igt@kms_flip@basic-flip-vs-modeset.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15513/fi-kbl-x1275/igt@kms_flip@basic-flip-vs-modeset.html
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
- fi-kbl-x1275: [DMESG-WARN][13] ([fdo#103558] / [fdo#105602]) -> [DMESG-WARN][14] ([fdo#103558] / [fdo#105602] / [fdo#105763]) +3 similar issues
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7446/fi-kbl-x1275/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15513/fi-kbl-x1275/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html
[fdo#103558]: https://bugs.freedesktop.org/show_bug.cgi?id=103558
[fdo#105602]: https://bugs.freedesktop.org/show_bug.cgi?id=105602
[fdo#105763]: https://bugs.freedesktop.org/show_bug.cgi?id=105763
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#109483]: https://bugs.freedesktop.org/show_bug.cgi?id=109483
[fdo#109635]: https://bugs.freedesktop.org/show_bug.cgi?id=109635
[fdo#112176]: https://bugs.freedesktop.org/show_bug.cgi?id=112176
[fdo#112261]: https://bugs.freedesktop.org/show_bug.cgi?id=112261
Participating hosts (50 -> 45)
------------------------------
Additional (1): fi-gdg-551
Missing (6): fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_7446 -> Patchwork_15513
CI-20190529: 20190529
CI_DRM_7446: dd4c99f05be238533a8a09f33b4c122f83d1f2be @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5318: 26ae6584ac03ad862d82f986302275a68bcccb29 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_15513: eebb0b2da903a777b34b46a0135fa3055f5fd971 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
eebb0b2da903 drm/i915: Correctly map DBUF slices to pipes
f873b7ab0960 drm/i915: Manipulate DBuf slices properly
b10c611ce1ad drm/i915: Move dbuf slice update to proper place
71bfd702d5e1 drm/i915: Remove skl_ddl_allocation struct
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15513/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 26+ messages in thread
* ✗ Fi.CI.IGT: failure for Enable second DBuf slice for ICL and TGL (rev3)
@ 2019-11-30 23:00 ` Patchwork
0 siblings, 0 replies; 26+ messages in thread
From: Patchwork @ 2019-11-30 23:00 UTC (permalink / raw)
To: Stanislav Lisovskiy; +Cc: intel-gfx
== Series Details ==
Series: Enable second DBuf slice for ICL and TGL (rev3)
URL : https://patchwork.freedesktop.org/series/70059/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7446_full -> Patchwork_15513_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_15513_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_15513_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_15513_full:
### IGT changes ###
#### Possible regressions ####
* igt@gem_exec_suspend@basic-s0:
- shard-tglb: [PASS][1] -> [INCOMPLETE][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7446/shard-tglb7/igt@gem_exec_suspend@basic-s0.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15513/shard-tglb5/igt@gem_exec_suspend@basic-s0.html
* igt@i915_selftest@live_active:
- shard-skl: [PASS][3] -> [DMESG-FAIL][4]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7446/shard-skl1/igt@i915_selftest@live_active.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15513/shard-skl10/igt@i915_selftest@live_active.html
* igt@kms_cursor_crc@pipe-c-cursor-suspend:
- shard-hsw: [PASS][5] -> [DMESG-WARN][6]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7446/shard-hsw6/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15513/shard-hsw6/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* {igt@gem_exec_schedule@pi-common-bsd}:
- shard-iclb: [PASS][7] -> [SKIP][8]
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7446/shard-iclb8/igt@gem_exec_schedule@pi-common-bsd.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15513/shard-iclb4/igt@gem_exec_schedule@pi-common-bsd.html
* {igt@gem_exec_schedule@pi-distinct-iova-bsd}:
- shard-iclb: NOTRUN -> [SKIP][9]
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15513/shard-iclb1/igt@gem_exec_schedule@pi-distinct-iova-bsd.html
* {igt@gem_exec_schedule@pi-userfault-bsd}:
- shard-tglb: NOTRUN -> [SKIP][10]
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15513/shard-tglb4/igt@gem_exec_schedule@pi-userfault-bsd.html
* {igt@perf_pmu@frequency-idle}:
- shard-iclb: NOTRUN -> [FAIL][11]
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15513/shard-iclb1/igt@perf_pmu@frequency-idle.html
Known issues
------------
Here are the changes found in Patchwork_15513_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_exec_parallel@fds:
- shard-tglb: [PASS][12] -> [INCOMPLETE][13] ([i915#470])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7446/shard-tglb2/igt@gem_exec_parallel@fds.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15513/shard-tglb6/igt@gem_exec_parallel@fds.html
* igt@gem_exec_schedule@reorder-wide-bsd:
- shard-iclb: [PASS][14] -> [SKIP][15] ([fdo#112146]) +3 similar issues
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7446/shard-iclb8/igt@gem_exec_schedule@reorder-wide-bsd.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15513/shard-iclb4/igt@gem_exec_schedule@reorder-wide-bsd.html
* igt@gem_ppgtt@flink-and-close-vma-leak:
- shard-glk: [PASS][16] -> [FAIL][17] ([i915#644])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7446/shard-glk8/igt@gem_ppgtt@flink-and-close-vma-leak.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15513/shard-glk1/igt@gem_ppgtt@flink-and-close-vma-leak.html
* igt@gem_userptr_blits@sync-unmap-after-close:
- shard-hsw: [PASS][18] -> [DMESG-WARN][19] ([fdo#111870]) +1 similar issue
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7446/shard-hsw5/igt@gem_userptr_blits@sync-unmap-after-close.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15513/shard-hsw1/igt@gem_userptr_blits@sync-unmap-after-close.html
* igt@kms_cursor_crc@pipe-a-cursor-suspend:
- shard-kbl: [PASS][20] -> [DMESG-WARN][21] ([i915#180]) +5 similar issues
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7446/shard-kbl3/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15513/shard-kbl3/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
* igt@kms_cursor_legacy@2x-long-cursor-vs-flip-legacy:
- shard-hsw: [PASS][22] -> [FAIL][23] ([i915#96])
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7446/shard-hsw6/igt@kms_cursor_legacy@2x-long-cursor-vs-flip-legacy.html
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15513/shard-hsw6/igt@kms_cursor_legacy@2x-long-cursor-vs-flip-legacy.html
* igt@kms_draw_crc@draw-method-rgb565-render-untiled:
- shard-skl: [PASS][24] -> [INCOMPLETE][25] ([i915#646])
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7446/shard-skl4/igt@kms_draw_crc@draw-method-rgb565-render-untiled.html
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15513/shard-skl4/igt@kms_draw_crc@draw-method-rgb565-render-untiled.html
* igt@kms_flip@flip-vs-suspend-interruptible:
- shard-apl: [PASS][26] -> [DMESG-WARN][27] ([i915#180]) +2 similar issues
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7446/shard-apl8/igt@kms_flip@flip-vs-suspend-interruptible.html
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15513/shard-apl4/igt@kms_flip@flip-vs-suspend-interruptible.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-mmap-cpu:
- shard-tglb: [PASS][28] -> [INCOMPLETE][29] ([i915#474])
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7446/shard-tglb7/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-mmap-cpu.html
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15513/shard-tglb1/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-mmap-cpu.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-indfb-plflip-blt:
- shard-tglb: [PASS][30] -> [FAIL][31] ([i915#49]) +2 similar issues
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7446/shard-tglb1/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-indfb-plflip-blt.html
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15513/shard-tglb1/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-indfb-plflip-blt.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-indfb-plflip-blt:
- shard-skl: [PASS][32] -> [INCOMPLETE][33] ([i915#123]) +2 similar issues
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7446/shard-skl7/igt@kms_frontbuffer_tracking@psr-1p-primscrn-indfb-plflip-blt.html
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15513/shard-skl6/igt@kms_frontbuffer_tracking@psr-1p-primscrn-indfb-plflip-blt.html
* igt@kms_plane@pixel-format-pipe-b-planes-source-clamping:
- shard-skl: [PASS][34] -> [INCOMPLETE][35] ([fdo#112347] / [fdo#112391])
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7446/shard-skl3/igt@kms_plane@pixel-format-pipe-b-planes-source-clamping.html
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15513/shard-skl7/igt@kms_plane@pixel-format-pipe-b-planes-source-clamping.html
* igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes:
- shard-skl: [PASS][36] -> [INCOMPLETE][37] ([i915#69]) +2 similar issues
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7446/shard-skl5/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15513/shard-skl2/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html
* igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
- shard-skl: [PASS][38] -> [FAIL][39] ([fdo#108145] / [i915#265])
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7446/shard-skl2/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15513/shard-skl9/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
* igt@kms_setmode@basic:
- shard-hsw: [PASS][40] -> [FAIL][41] ([i915#31])
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7446/shard-hsw6/igt@kms_setmode@basic.html
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15513/shard-hsw6/igt@kms_setmode@basic.html
* igt@kms_vblank@pipe-d-ts-continuation-suspend:
- shard-tglb: [PASS][42] -> [INCOMPLETE][43] ([i915#460])
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7446/shard-tglb1/igt@kms_vblank@pipe-d-ts-continuation-suspend.html
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15513/shard-tglb2/igt@kms_vblank@pipe-d-ts-continuation-suspend.html
#### Possible fixes ####
* igt@gem_ctx_isolation@vcs1-dirty-create:
- shard-iclb: [SKIP][44] ([fdo#109276] / [fdo#112080]) -> [PASS][45] +1 similar issue
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7446/shard-iclb6/igt@gem_ctx_isolation@vcs1-dirty-create.html
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15513/shard-iclb1/igt@gem_ctx_isolation@vcs1-dirty-create.html
* igt@gem_ctx_persistence@processes:
- shard-apl: [FAIL][46] -> [PASS][47]
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7446/shard-apl2/igt@gem_ctx_persistence@processes.html
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15513/shard-apl8/igt@gem_ctx_persistence@processes.html
* igt@gem_ctx_persistence@smoketest:
- shard-apl: [TIMEOUT][48] -> [PASS][49]
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7446/shard-apl3/igt@gem_ctx_persistence@smoketest.html
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15513/shard-apl3/igt@gem_ctx_persistence@smoketest.html
- shard-glk: [TIMEOUT][50] ([i915#652]) -> [PASS][51]
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7446/shard-glk1/igt@gem_ctx_persistence@smoketest.html
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15513/shard-glk9/igt@gem_ctx_persistence@smoketest.html
* igt@gem_exec_nop@basic-sequential:
- shard-tglb: [INCOMPLETE][52] ([i915#435]) -> [PASS][53]
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7446/shard-tglb6/igt@gem_exec_nop@basic-sequential.html
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15513/shard-tglb1/igt@gem_exec_nop@basic-sequential.html
* igt@gem_exec_parallel@vcs0-fds:
- shard-tglb: [INCOMPLETE][54] ([i915#470]) -> [PASS][55]
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7446/shard-tglb1/igt@gem_exec_parallel@vcs0-fds.html
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15513/shard-tglb1/igt@gem_exec_parallel@vcs0-fds.html
* igt@gem_exec_parallel@vcs1-contexts:
- shard-iclb: [SKIP][56] ([fdo#112080]) -> [PASS][57]
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7446/shard-iclb6/igt@gem_exec_parallel@vcs1-contexts.html
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15513/shard-iclb1/igt@gem_exec_parallel@vcs1-contexts.html
* igt@gem_exec_schedule@preempt-queue-bsd2:
- shard-tglb: [INCOMPLETE][58] ([fdo#111606] / [fdo#111677]) -> [PASS][59]
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7446/shard-tglb6/igt@gem_exec_schedule@preempt-queue-bsd2.html
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15513/shard-tglb1/igt@gem_exec_schedule@preempt-queue-bsd2.html
* igt@gem_persistent_relocs@forked-faulting-reloc-thrashing:
- shard-tglb: [TIMEOUT][60] ([i915#530]) -> [PASS][61]
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7446/shard-tglb5/igt@gem_persistent_relocs@forked-faulting-reloc-thrashing.html
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15513/shard-tglb5/igt@gem_persistent_relocs@forked-faulting-reloc-thrashing.html
* igt@gem_sync@basic-all:
- shard-hsw: [INCOMPLETE][62] ([i915#61]) -> [PASS][63]
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7446/shard-hsw7/igt@gem_sync@basic-all.html
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15513/shard-hsw4/igt@gem_sync@basic-all.html
* igt@gem_sync@basic-each:
- shard-tglb: [INCOMPLETE][64] ([fdo#111998] / [i915#472]) -> [PASS][65]
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7446/shard-tglb5/igt@gem_sync@basic-each.html
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15513/shard-tglb5/igt@gem_sync@basic-each.html
* igt@gem_userptr_blits@dmabuf-sync:
- shard-snb: [DMESG-WARN][66] ([fdo#111870]) -> [PASS][67] +1 similar issue
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7446/shard-snb1/igt@gem_userptr_blits@dmabuf-sync.html
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15513/shard-snb4/igt@gem_userptr_blits@dmabuf-sync.html
* igt@gem_userptr_blits@sync-unmap-after-close:
- shard-glk: [INCOMPLETE][68] ([i915#58] / [k.org#198133]) -> [PASS][69]
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7446/shard-glk6/igt@gem_userptr_blits@sync-unmap-after-close.html
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15513/shard-glk3/igt@gem_userptr_blits@sync-unmap-after-close.html
* igt@gem_workarounds@suspend-resume-fd:
- shard-kbl: [DMESG-WARN][70] ([i915#180]) -> [PASS][71] +1 similar issue
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7446/shard-kbl7/igt@gem_workarounds@suspend-resume-fd.html
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15513/shard-kbl6/igt@gem_workarounds@suspend-resume-fd.html
* igt@kms_flip@flip-vs-expired-vblank:
- shard-skl: [FAIL][72] ([i915#79]) -> [PASS][73]
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7446/shard-skl2/igt@kms_flip@flip-vs-expired-vblank.html
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15513/shard-skl9/igt@kms_flip@flip-vs-expired-vblank.html
* igt@kms_frontbuffer_tracking@fbc-suspend:
- shard-apl: [DMESG-WARN][74] ([i915#180]) -> [PASS][75] +1 similar issue
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7446/shard-apl6/igt@kms_frontbuffer_tracking@fbc-suspend.html
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15513/shard-apl6/igt@kms_frontbuffer_tracking@fbc-suspend.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-mmap-cpu:
- shard-iclb: [INCOMPLETE][76] ([i915#123] / [i915#140]) -> [PASS][77]
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7446/shard-iclb3/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-mmap-cpu.html
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15513/shard-iclb6/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-mmap-cpu.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-move:
- shard-tglb: [INCOMPLETE][78] ([i915#474]) -> [PASS][79]
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7446/shard-tglb1/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-move.html
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15513/shard-tglb5/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-move.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-mmap-wc:
- shard-tglb: [FAIL][80] ([i915#49]) -> [PASS][81]
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7446/shard-tglb4/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-mmap-wc.html
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15513/shard-tglb4/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-mmap-wc.html
* igt@kms_plane@pixel-format-pipe-a-planes:
- shard-skl: [INCOMPLETE][82] ([fdo#112347]) -> [PASS][83]
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7446/shard-skl2/igt@kms_plane@pixel-format-pipe-a-planes.html
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15513/shard-skl1/igt@kms_plane@pixel-format-pipe-a-planes.html
* igt@kms_plane@pixel-format-pipe-a-planes-source-clamping:
- shard-skl: [INCOMPLETE][84] ([i915#648]) -> [PASS][85]
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7446/shard-skl1/igt@kms_plane@pixel-format-pipe-a-planes-source-clamping.html
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15513/shard-skl6/igt@kms_plane@pixel-format-pipe-a-planes-source-clamping.html
* igt@kms_plane@pixel-format-pipe-b-planes-source-clamping:
- shard-kbl: [INCOMPLETE][86] ([fdo#103665] / [i915#435]) -> [PASS][87]
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7446/shard-kbl1/igt@kms_plane@pixel-format-pipe-b-planes-source-clamping.html
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15513/shard-kbl6/igt@kms_plane@pixel-format-pipe-b-planes-source-clamping.html
* igt@kms_plane_alpha_blend@pipe-b-coverage-7efc:
- shard-skl: [FAIL][88] ([fdo#108145] / [i915#265]) -> [PASS][89]
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7446/shard-skl8/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15513/shard-skl5/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
* igt@kms_setmode@basic:
- shard-apl: [FAIL][90] ([i915#31]) -> [PASS][91]
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7446/shard-apl1/igt@kms_setmode@basic.html
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15513/shard-apl6/igt@kms_setmode@basic.html
* igt@perf@oa-exponents:
- shard-glk: [FAIL][92] ([i915#84]) -> [PASS][93]
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7446/shard-glk1/igt@perf@oa-exponents.html
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15513/shard-glk6/igt@perf@oa-exponents.html
* igt@prime_busy@hang-bsd2:
- shard-iclb: [SKIP][94] ([fdo#109276]) -> [PASS][95] +5 similar issues
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7446/shard-iclb6/igt@prime_busy@hang-bsd2.html
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15513/shard-iclb1/igt@prime_busy@hang-bsd2.html
#### Warnings ####
* igt@kms_cursor_crc@pipe-b-cursor-suspend:
- shard-apl: [DMESG-FAIL][96] ([i915#180] / [i915#54]) -> [FAIL][97] ([i915#54])
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7446/shard-apl1/igt@kms_cursor_crc@pipe-b-cursor-suspend.html
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15513/shard-apl6/igt@kms_cursor_crc@pipe-b-cursor-suspend.html
* igt@kms_plane@pixel-format-pipe-b-planes:
- shard-skl: [INCOMPLETE][98] ([fdo#112347] / [fdo#112391]) -> [INCOMPLETE][99] ([fdo#112391])
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7446/shard-skl4/igt@kms_plane@pixel-format-pipe-b-planes.html
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15513/shard-skl10/igt@kms_plane@pixel-format-pipe-b-planes.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103665]: https://bugs.freedesktop.org/show_bug.cgi?id=103665
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
[fdo#111606]: https://bugs.freedesktop.org/show_bug.cgi?id=111606
[fdo#111677]: https://bugs.freedesktop.org/show_bug.cgi?id=111677
[fdo#111870]: https://bugs.freedesktop.org/show_bug.cgi?id=111870
[fdo#111998]: https://bugs.freedesktop.org/show_bug.cgi?id=111998
[fdo#112080]: https://bugs.freedesktop.org/show_bug.cgi?id=112080
[fdo#112146]: https://bugs.freedesktop.org/show_bug.cgi?id=112146
[fdo#112347]: https://bugs.freedesktop.org/show_bug.cgi?id=112347
[fdo#112391]: https://bugs.freedesktop.org/show_bug.cgi?id=112391
[i915#123]: https://gitlab.freedesktop.org/drm/intel/issues/123
[i915#140]: https://gitlab.freedesktop.org/drm/intel/issues/140
[i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
[i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265
[i915#31]: https://gitlab.freedesktop.org/drm/intel/issues/31
[i915#435]: https://gitlab.freedesktop.org/drm/intel/issues/435
[i915#460]: https://gitlab.freedesktop.org/drm/intel/issues/460
[i915#470]: https://gitlab.freedesktop.org/drm/intel/issues/470
[i915#472]: https://gitlab.freedesktop.org/drm/intel/issues/472
[i915#474]: https://gitlab.freedesktop.org/drm/intel/issues/474
[i915#49]: https://gitlab.freedesktop.org/drm/intel/issues/49
[i915#530]: https://gitlab.freedesktop.org/drm/intel/issues/530
[i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54
[i915#58]: https://gitlab.freedesktop.org/drm/intel/issues/58
[i915#61]: https://gitlab.freedesktop.org/drm/intel/issues/61
[i915#644]: https://gitlab.freedesktop.org/drm/intel/issues/644
[i915#646]: https://gitlab.freedesktop.org/drm/intel/issues/646
[i915#648]: https://gitlab.freedesktop.org/drm/intel/issues/648
[i915#652]: https://gitlab.freedesktop.org/drm/intel/issues/652
[i915#69]: https://gitlab.freedesktop.org/drm/intel/issues/69
[i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
[i915#84]: https://gitlab.freedesktop.org/drm/intel/issues/84
[i915#96]: https://gitlab.freedesktop.org/drm/intel/issues/96
[k.org#198133]: https://bugzilla.kernel.org/show_bug.cgi?id=198133
Participating hosts (11 -> 11)
------------------------------
No changes in participating hosts
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_7446 -> Patchwork_15513
CI-20190529: 20190529
CI_DRM_7446: dd4c99f05be238533a8a09f33b4c122f83d1f2be @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5318: 26ae6584ac03ad862d82f986302275a68bcccb29 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_15513: eebb0b2da903a777b34b46a0135fa3055f5fd971 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15513/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 26+ messages in thread
* [Intel-gfx] ✗ Fi.CI.IGT: failure for Enable second DBuf slice for ICL and TGL (rev3)
@ 2019-11-30 23:00 ` Patchwork
0 siblings, 0 replies; 26+ messages in thread
From: Patchwork @ 2019-11-30 23:00 UTC (permalink / raw)
To: Stanislav Lisovskiy; +Cc: intel-gfx
== Series Details ==
Series: Enable second DBuf slice for ICL and TGL (rev3)
URL : https://patchwork.freedesktop.org/series/70059/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7446_full -> Patchwork_15513_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_15513_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_15513_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_15513_full:
### IGT changes ###
#### Possible regressions ####
* igt@gem_exec_suspend@basic-s0:
- shard-tglb: [PASS][1] -> [INCOMPLETE][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7446/shard-tglb7/igt@gem_exec_suspend@basic-s0.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15513/shard-tglb5/igt@gem_exec_suspend@basic-s0.html
* igt@i915_selftest@live_active:
- shard-skl: [PASS][3] -> [DMESG-FAIL][4]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7446/shard-skl1/igt@i915_selftest@live_active.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15513/shard-skl10/igt@i915_selftest@live_active.html
* igt@kms_cursor_crc@pipe-c-cursor-suspend:
- shard-hsw: [PASS][5] -> [DMESG-WARN][6]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7446/shard-hsw6/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15513/shard-hsw6/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* {igt@gem_exec_schedule@pi-common-bsd}:
- shard-iclb: [PASS][7] -> [SKIP][8]
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7446/shard-iclb8/igt@gem_exec_schedule@pi-common-bsd.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15513/shard-iclb4/igt@gem_exec_schedule@pi-common-bsd.html
* {igt@gem_exec_schedule@pi-distinct-iova-bsd}:
- shard-iclb: NOTRUN -> [SKIP][9]
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15513/shard-iclb1/igt@gem_exec_schedule@pi-distinct-iova-bsd.html
* {igt@gem_exec_schedule@pi-userfault-bsd}:
- shard-tglb: NOTRUN -> [SKIP][10]
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15513/shard-tglb4/igt@gem_exec_schedule@pi-userfault-bsd.html
* {igt@perf_pmu@frequency-idle}:
- shard-iclb: NOTRUN -> [FAIL][11]
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15513/shard-iclb1/igt@perf_pmu@frequency-idle.html
Known issues
------------
Here are the changes found in Patchwork_15513_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_exec_parallel@fds:
- shard-tglb: [PASS][12] -> [INCOMPLETE][13] ([i915#470])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7446/shard-tglb2/igt@gem_exec_parallel@fds.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15513/shard-tglb6/igt@gem_exec_parallel@fds.html
* igt@gem_exec_schedule@reorder-wide-bsd:
- shard-iclb: [PASS][14] -> [SKIP][15] ([fdo#112146]) +3 similar issues
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7446/shard-iclb8/igt@gem_exec_schedule@reorder-wide-bsd.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15513/shard-iclb4/igt@gem_exec_schedule@reorder-wide-bsd.html
* igt@gem_ppgtt@flink-and-close-vma-leak:
- shard-glk: [PASS][16] -> [FAIL][17] ([i915#644])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7446/shard-glk8/igt@gem_ppgtt@flink-and-close-vma-leak.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15513/shard-glk1/igt@gem_ppgtt@flink-and-close-vma-leak.html
* igt@gem_userptr_blits@sync-unmap-after-close:
- shard-hsw: [PASS][18] -> [DMESG-WARN][19] ([fdo#111870]) +1 similar issue
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7446/shard-hsw5/igt@gem_userptr_blits@sync-unmap-after-close.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15513/shard-hsw1/igt@gem_userptr_blits@sync-unmap-after-close.html
* igt@kms_cursor_crc@pipe-a-cursor-suspend:
- shard-kbl: [PASS][20] -> [DMESG-WARN][21] ([i915#180]) +5 similar issues
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7446/shard-kbl3/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15513/shard-kbl3/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
* igt@kms_cursor_legacy@2x-long-cursor-vs-flip-legacy:
- shard-hsw: [PASS][22] -> [FAIL][23] ([i915#96])
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7446/shard-hsw6/igt@kms_cursor_legacy@2x-long-cursor-vs-flip-legacy.html
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15513/shard-hsw6/igt@kms_cursor_legacy@2x-long-cursor-vs-flip-legacy.html
* igt@kms_draw_crc@draw-method-rgb565-render-untiled:
- shard-skl: [PASS][24] -> [INCOMPLETE][25] ([i915#646])
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7446/shard-skl4/igt@kms_draw_crc@draw-method-rgb565-render-untiled.html
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15513/shard-skl4/igt@kms_draw_crc@draw-method-rgb565-render-untiled.html
* igt@kms_flip@flip-vs-suspend-interruptible:
- shard-apl: [PASS][26] -> [DMESG-WARN][27] ([i915#180]) +2 similar issues
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7446/shard-apl8/igt@kms_flip@flip-vs-suspend-interruptible.html
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15513/shard-apl4/igt@kms_flip@flip-vs-suspend-interruptible.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-mmap-cpu:
- shard-tglb: [PASS][28] -> [INCOMPLETE][29] ([i915#474])
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7446/shard-tglb7/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-mmap-cpu.html
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15513/shard-tglb1/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-mmap-cpu.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-indfb-plflip-blt:
- shard-tglb: [PASS][30] -> [FAIL][31] ([i915#49]) +2 similar issues
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7446/shard-tglb1/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-indfb-plflip-blt.html
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15513/shard-tglb1/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-indfb-plflip-blt.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-indfb-plflip-blt:
- shard-skl: [PASS][32] -> [INCOMPLETE][33] ([i915#123]) +2 similar issues
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7446/shard-skl7/igt@kms_frontbuffer_tracking@psr-1p-primscrn-indfb-plflip-blt.html
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15513/shard-skl6/igt@kms_frontbuffer_tracking@psr-1p-primscrn-indfb-plflip-blt.html
* igt@kms_plane@pixel-format-pipe-b-planes-source-clamping:
- shard-skl: [PASS][34] -> [INCOMPLETE][35] ([fdo#112347] / [fdo#112391])
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7446/shard-skl3/igt@kms_plane@pixel-format-pipe-b-planes-source-clamping.html
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15513/shard-skl7/igt@kms_plane@pixel-format-pipe-b-planes-source-clamping.html
* igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes:
- shard-skl: [PASS][36] -> [INCOMPLETE][37] ([i915#69]) +2 similar issues
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7446/shard-skl5/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15513/shard-skl2/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html
* igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
- shard-skl: [PASS][38] -> [FAIL][39] ([fdo#108145] / [i915#265])
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7446/shard-skl2/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15513/shard-skl9/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
* igt@kms_setmode@basic:
- shard-hsw: [PASS][40] -> [FAIL][41] ([i915#31])
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7446/shard-hsw6/igt@kms_setmode@basic.html
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15513/shard-hsw6/igt@kms_setmode@basic.html
* igt@kms_vblank@pipe-d-ts-continuation-suspend:
- shard-tglb: [PASS][42] -> [INCOMPLETE][43] ([i915#460])
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7446/shard-tglb1/igt@kms_vblank@pipe-d-ts-continuation-suspend.html
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15513/shard-tglb2/igt@kms_vblank@pipe-d-ts-continuation-suspend.html
#### Possible fixes ####
* igt@gem_ctx_isolation@vcs1-dirty-create:
- shard-iclb: [SKIP][44] ([fdo#109276] / [fdo#112080]) -> [PASS][45] +1 similar issue
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7446/shard-iclb6/igt@gem_ctx_isolation@vcs1-dirty-create.html
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15513/shard-iclb1/igt@gem_ctx_isolation@vcs1-dirty-create.html
* igt@gem_ctx_persistence@processes:
- shard-apl: [FAIL][46] -> [PASS][47]
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7446/shard-apl2/igt@gem_ctx_persistence@processes.html
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15513/shard-apl8/igt@gem_ctx_persistence@processes.html
* igt@gem_ctx_persistence@smoketest:
- shard-apl: [TIMEOUT][48] -> [PASS][49]
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7446/shard-apl3/igt@gem_ctx_persistence@smoketest.html
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15513/shard-apl3/igt@gem_ctx_persistence@smoketest.html
- shard-glk: [TIMEOUT][50] ([i915#652]) -> [PASS][51]
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7446/shard-glk1/igt@gem_ctx_persistence@smoketest.html
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15513/shard-glk9/igt@gem_ctx_persistence@smoketest.html
* igt@gem_exec_nop@basic-sequential:
- shard-tglb: [INCOMPLETE][52] ([i915#435]) -> [PASS][53]
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7446/shard-tglb6/igt@gem_exec_nop@basic-sequential.html
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15513/shard-tglb1/igt@gem_exec_nop@basic-sequential.html
* igt@gem_exec_parallel@vcs0-fds:
- shard-tglb: [INCOMPLETE][54] ([i915#470]) -> [PASS][55]
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7446/shard-tglb1/igt@gem_exec_parallel@vcs0-fds.html
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15513/shard-tglb1/igt@gem_exec_parallel@vcs0-fds.html
* igt@gem_exec_parallel@vcs1-contexts:
- shard-iclb: [SKIP][56] ([fdo#112080]) -> [PASS][57]
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7446/shard-iclb6/igt@gem_exec_parallel@vcs1-contexts.html
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15513/shard-iclb1/igt@gem_exec_parallel@vcs1-contexts.html
* igt@gem_exec_schedule@preempt-queue-bsd2:
- shard-tglb: [INCOMPLETE][58] ([fdo#111606] / [fdo#111677]) -> [PASS][59]
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7446/shard-tglb6/igt@gem_exec_schedule@preempt-queue-bsd2.html
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15513/shard-tglb1/igt@gem_exec_schedule@preempt-queue-bsd2.html
* igt@gem_persistent_relocs@forked-faulting-reloc-thrashing:
- shard-tglb: [TIMEOUT][60] ([i915#530]) -> [PASS][61]
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7446/shard-tglb5/igt@gem_persistent_relocs@forked-faulting-reloc-thrashing.html
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15513/shard-tglb5/igt@gem_persistent_relocs@forked-faulting-reloc-thrashing.html
* igt@gem_sync@basic-all:
- shard-hsw: [INCOMPLETE][62] ([i915#61]) -> [PASS][63]
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7446/shard-hsw7/igt@gem_sync@basic-all.html
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15513/shard-hsw4/igt@gem_sync@basic-all.html
* igt@gem_sync@basic-each:
- shard-tglb: [INCOMPLETE][64] ([fdo#111998] / [i915#472]) -> [PASS][65]
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7446/shard-tglb5/igt@gem_sync@basic-each.html
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15513/shard-tglb5/igt@gem_sync@basic-each.html
* igt@gem_userptr_blits@dmabuf-sync:
- shard-snb: [DMESG-WARN][66] ([fdo#111870]) -> [PASS][67] +1 similar issue
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7446/shard-snb1/igt@gem_userptr_blits@dmabuf-sync.html
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15513/shard-snb4/igt@gem_userptr_blits@dmabuf-sync.html
* igt@gem_userptr_blits@sync-unmap-after-close:
- shard-glk: [INCOMPLETE][68] ([i915#58] / [k.org#198133]) -> [PASS][69]
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7446/shard-glk6/igt@gem_userptr_blits@sync-unmap-after-close.html
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15513/shard-glk3/igt@gem_userptr_blits@sync-unmap-after-close.html
* igt@gem_workarounds@suspend-resume-fd:
- shard-kbl: [DMESG-WARN][70] ([i915#180]) -> [PASS][71] +1 similar issue
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7446/shard-kbl7/igt@gem_workarounds@suspend-resume-fd.html
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15513/shard-kbl6/igt@gem_workarounds@suspend-resume-fd.html
* igt@kms_flip@flip-vs-expired-vblank:
- shard-skl: [FAIL][72] ([i915#79]) -> [PASS][73]
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7446/shard-skl2/igt@kms_flip@flip-vs-expired-vblank.html
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15513/shard-skl9/igt@kms_flip@flip-vs-expired-vblank.html
* igt@kms_frontbuffer_tracking@fbc-suspend:
- shard-apl: [DMESG-WARN][74] ([i915#180]) -> [PASS][75] +1 similar issue
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7446/shard-apl6/igt@kms_frontbuffer_tracking@fbc-suspend.html
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15513/shard-apl6/igt@kms_frontbuffer_tracking@fbc-suspend.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-mmap-cpu:
- shard-iclb: [INCOMPLETE][76] ([i915#123] / [i915#140]) -> [PASS][77]
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7446/shard-iclb3/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-mmap-cpu.html
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15513/shard-iclb6/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-mmap-cpu.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-move:
- shard-tglb: [INCOMPLETE][78] ([i915#474]) -> [PASS][79]
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7446/shard-tglb1/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-move.html
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15513/shard-tglb5/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-move.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-mmap-wc:
- shard-tglb: [FAIL][80] ([i915#49]) -> [PASS][81]
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7446/shard-tglb4/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-mmap-wc.html
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15513/shard-tglb4/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-mmap-wc.html
* igt@kms_plane@pixel-format-pipe-a-planes:
- shard-skl: [INCOMPLETE][82] ([fdo#112347]) -> [PASS][83]
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7446/shard-skl2/igt@kms_plane@pixel-format-pipe-a-planes.html
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15513/shard-skl1/igt@kms_plane@pixel-format-pipe-a-planes.html
* igt@kms_plane@pixel-format-pipe-a-planes-source-clamping:
- shard-skl: [INCOMPLETE][84] ([i915#648]) -> [PASS][85]
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7446/shard-skl1/igt@kms_plane@pixel-format-pipe-a-planes-source-clamping.html
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15513/shard-skl6/igt@kms_plane@pixel-format-pipe-a-planes-source-clamping.html
* igt@kms_plane@pixel-format-pipe-b-planes-source-clamping:
- shard-kbl: [INCOMPLETE][86] ([fdo#103665] / [i915#435]) -> [PASS][87]
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7446/shard-kbl1/igt@kms_plane@pixel-format-pipe-b-planes-source-clamping.html
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15513/shard-kbl6/igt@kms_plane@pixel-format-pipe-b-planes-source-clamping.html
* igt@kms_plane_alpha_blend@pipe-b-coverage-7efc:
- shard-skl: [FAIL][88] ([fdo#108145] / [i915#265]) -> [PASS][89]
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7446/shard-skl8/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15513/shard-skl5/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
* igt@kms_setmode@basic:
- shard-apl: [FAIL][90] ([i915#31]) -> [PASS][91]
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7446/shard-apl1/igt@kms_setmode@basic.html
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15513/shard-apl6/igt@kms_setmode@basic.html
* igt@perf@oa-exponents:
- shard-glk: [FAIL][92] ([i915#84]) -> [PASS][93]
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7446/shard-glk1/igt@perf@oa-exponents.html
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15513/shard-glk6/igt@perf@oa-exponents.html
* igt@prime_busy@hang-bsd2:
- shard-iclb: [SKIP][94] ([fdo#109276]) -> [PASS][95] +5 similar issues
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7446/shard-iclb6/igt@prime_busy@hang-bsd2.html
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15513/shard-iclb1/igt@prime_busy@hang-bsd2.html
#### Warnings ####
* igt@kms_cursor_crc@pipe-b-cursor-suspend:
- shard-apl: [DMESG-FAIL][96] ([i915#180] / [i915#54]) -> [FAIL][97] ([i915#54])
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7446/shard-apl1/igt@kms_cursor_crc@pipe-b-cursor-suspend.html
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15513/shard-apl6/igt@kms_cursor_crc@pipe-b-cursor-suspend.html
* igt@kms_plane@pixel-format-pipe-b-planes:
- shard-skl: [INCOMPLETE][98] ([fdo#112347] / [fdo#112391]) -> [INCOMPLETE][99] ([fdo#112391])
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7446/shard-skl4/igt@kms_plane@pixel-format-pipe-b-planes.html
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15513/shard-skl10/igt@kms_plane@pixel-format-pipe-b-planes.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103665]: https://bugs.freedesktop.org/show_bug.cgi?id=103665
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
[fdo#111606]: https://bugs.freedesktop.org/show_bug.cgi?id=111606
[fdo#111677]: https://bugs.freedesktop.org/show_bug.cgi?id=111677
[fdo#111870]: https://bugs.freedesktop.org/show_bug.cgi?id=111870
[fdo#111998]: https://bugs.freedesktop.org/show_bug.cgi?id=111998
[fdo#112080]: https://bugs.freedesktop.org/show_bug.cgi?id=112080
[fdo#112146]: https://bugs.freedesktop.org/show_bug.cgi?id=112146
[fdo#112347]: https://bugs.freedesktop.org/show_bug.cgi?id=112347
[fdo#112391]: https://bugs.freedesktop.org/show_bug.cgi?id=112391
[i915#123]: https://gitlab.freedesktop.org/drm/intel/issues/123
[i915#140]: https://gitlab.freedesktop.org/drm/intel/issues/140
[i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
[i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265
[i915#31]: https://gitlab.freedesktop.org/drm/intel/issues/31
[i915#435]: https://gitlab.freedesktop.org/drm/intel/issues/435
[i915#460]: https://gitlab.freedesktop.org/drm/intel/issues/460
[i915#470]: https://gitlab.freedesktop.org/drm/intel/issues/470
[i915#472]: https://gitlab.freedesktop.org/drm/intel/issues/472
[i915#474]: https://gitlab.freedesktop.org/drm/intel/issues/474
[i915#49]: https://gitlab.freedesktop.org/drm/intel/issues/49
[i915#530]: https://gitlab.freedesktop.org/drm/intel/issues/530
[i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54
[i915#58]: https://gitlab.freedesktop.org/drm/intel/issues/58
[i915#61]: https://gitlab.freedesktop.org/drm/intel/issues/61
[i915#644]: https://gitlab.freedesktop.org/drm/intel/issues/644
[i915#646]: https://gitlab.freedesktop.org/drm/intel/issues/646
[i915#648]: https://gitlab.freedesktop.org/drm/intel/issues/648
[i915#652]: https://gitlab.freedesktop.org/drm/intel/issues/652
[i915#69]: https://gitlab.freedesktop.org/drm/intel/issues/69
[i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
[i915#84]: https://gitlab.freedesktop.org/drm/intel/issues/84
[i915#96]: https://gitlab.freedesktop.org/drm/intel/issues/96
[k.org#198133]: https://bugzilla.kernel.org/show_bug.cgi?id=198133
Participating hosts (11 -> 11)
------------------------------
No changes in participating hosts
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_7446 -> Patchwork_15513
CI-20190529: 20190529
CI_DRM_7446: dd4c99f05be238533a8a09f33b4c122f83d1f2be @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5318: 26ae6584ac03ad862d82f986302275a68bcccb29 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_15513: eebb0b2da903a777b34b46a0135fa3055f5fd971 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15513/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 26+ messages in thread
* ✗ Fi.CI.BAT: failure for Enable second DBuf slice for ICL and TGL (rev4)
@ 2019-12-03 0:20 ` Patchwork
0 siblings, 0 replies; 26+ messages in thread
From: Patchwork @ 2019-12-03 0:20 UTC (permalink / raw)
To: Stanislav Lisovskiy; +Cc: intel-gfx
== Series Details ==
Series: Enable second DBuf slice for ICL and TGL (rev4)
URL : https://patchwork.freedesktop.org/series/70059/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7467 -> Patchwork_15545
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_15545 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_15545, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15545/index.html
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_15545:
### IGT changes ###
#### Possible regressions ####
* igt@i915_module_load@reload-no-display:
- fi-bwr-2160: [PASS][1] -> [INCOMPLETE][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7467/fi-bwr-2160/igt@i915_module_load@reload-no-display.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15545/fi-bwr-2160/igt@i915_module_load@reload-no-display.html
Known issues
------------
Here are the changes found in Patchwork_15545 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@i915_pm_rpm@basic-pci-d3-state:
- fi-icl-dsi: [PASS][3] -> [INCOMPLETE][4] ([i915#140] / [i915#189])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7467/fi-icl-dsi/igt@i915_pm_rpm@basic-pci-d3-state.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15545/fi-icl-dsi/igt@i915_pm_rpm@basic-pci-d3-state.html
* igt@kms_chamelium@dp-edid-read:
- fi-icl-u2: [PASS][5] -> [DMESG-WARN][6] ([i915#109])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7467/fi-icl-u2/igt@kms_chamelium@dp-edid-read.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15545/fi-icl-u2/igt@kms_chamelium@dp-edid-read.html
#### Possible fixes ####
* igt@i915_pm_rpm@module-reload:
- fi-skl-6770hq: [DMESG-WARN][7] ([i915#592]) -> [PASS][8]
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7467/fi-skl-6770hq/igt@i915_pm_rpm@module-reload.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15545/fi-skl-6770hq/igt@i915_pm_rpm@module-reload.html
* igt@i915_selftest@live_blt:
- fi-ivb-3770: [DMESG-FAIL][9] ([i915#563]) -> [PASS][10]
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7467/fi-ivb-3770/igt@i915_selftest@live_blt.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15545/fi-ivb-3770/igt@i915_selftest@live_blt.html
- fi-hsw-4770: [DMESG-FAIL][11] ([i915#563]) -> [PASS][12]
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7467/fi-hsw-4770/igt@i915_selftest@live_blt.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15545/fi-hsw-4770/igt@i915_selftest@live_blt.html
* igt@i915_selftest@live_gem_contexts:
- fi-skl-lmem: [INCOMPLETE][13] ([i915#424]) -> [PASS][14]
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7467/fi-skl-lmem/igt@i915_selftest@live_gem_contexts.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15545/fi-skl-lmem/igt@i915_selftest@live_gem_contexts.html
* igt@kms_frontbuffer_tracking@basic:
- fi-icl-guc: [FAIL][15] ([i915#49]) -> [PASS][16]
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7467/fi-icl-guc/igt@kms_frontbuffer_tracking@basic.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15545/fi-icl-guc/igt@kms_frontbuffer_tracking@basic.html
#### Warnings ####
* igt@gem_exec_suspend@basic-s4-devices:
- fi-kbl-x1275: [DMESG-WARN][17] ([fdo#107139] / [i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][18] ([fdo#107139] / [i915#62] / [i915#92])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7467/fi-kbl-x1275/igt@gem_exec_suspend@basic-s4-devices.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15545/fi-kbl-x1275/igt@gem_exec_suspend@basic-s4-devices.html
* igt@i915_selftest@live_gem_contexts:
- fi-hsw-peppy: [DMESG-FAIL][19] ([fdo#111692]) -> [INCOMPLETE][20] ([i915#694])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7467/fi-hsw-peppy/igt@i915_selftest@live_gem_contexts.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15545/fi-hsw-peppy/igt@i915_selftest@live_gem_contexts.html
* igt@kms_busy@basic-flip-pipe-b:
- fi-kbl-x1275: [DMESG-WARN][21] ([i915#62] / [i915#92]) -> [DMESG-WARN][22] ([i915#62] / [i915#92] / [i915#95]) +6 similar issues
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7467/fi-kbl-x1275/igt@kms_busy@basic-flip-pipe-b.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15545/fi-kbl-x1275/igt@kms_busy@basic-flip-pipe-b.html
* igt@kms_cursor_legacy@basic-flip-after-cursor-legacy:
- fi-kbl-x1275: [DMESG-WARN][23] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][24] ([i915#62] / [i915#92]) +6 similar issues
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7467/fi-kbl-x1275/igt@kms_cursor_legacy@basic-flip-after-cursor-legacy.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15545/fi-kbl-x1275/igt@kms_cursor_legacy@basic-flip-after-cursor-legacy.html
[fdo#107139]: https://bugs.freedesktop.org/show_bug.cgi?id=107139
[fdo#111692]: https://bugs.freedesktop.org/show_bug.cgi?id=111692
[i915#109]: https://gitlab.freedesktop.org/drm/intel/issues/109
[i915#140]: https://gitlab.freedesktop.org/drm/intel/issues/140
[i915#189]: https://gitlab.freedesktop.org/drm/intel/issues/189
[i915#424]: https://gitlab.freedesktop.org/drm/intel/issues/424
[i915#49]: https://gitlab.freedesktop.org/drm/intel/issues/49
[i915#563]: https://gitlab.freedesktop.org/drm/intel/issues/563
[i915#592]: https://gitlab.freedesktop.org/drm/intel/issues/592
[i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62
[i915#694]: https://gitlab.freedesktop.org/drm/intel/issues/694
[i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92
[i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95
Participating hosts (50 -> 45)
------------------------------
Missing (5): fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_7467 -> Patchwork_15545
CI-20190529: 20190529
CI_DRM_7467: 14954f24e7251b067b2081aaa09a7da6840da0d5 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5321: 9df50aef49e0da4413609d9866b41b82b725f2a0 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_15545: b26279b92ff697b244bf5fc1b298f8bec6c29c9a @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
b26279b92ff6 drm/i915: Correctly map DBUF slices to pipes
4fda5a6b8995 drm/i915: Manipulate DBuf slices properly
398ab0e115ee drm/i915: Move dbuf slice update to proper place
fe2e52f7a301 drm/i915: Remove skl_ddl_allocation struct
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15545/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 26+ messages in thread
* [Intel-gfx] ✗ Fi.CI.BAT: failure for Enable second DBuf slice for ICL and TGL (rev4)
@ 2019-12-03 0:20 ` Patchwork
0 siblings, 0 replies; 26+ messages in thread
From: Patchwork @ 2019-12-03 0:20 UTC (permalink / raw)
To: Stanislav Lisovskiy; +Cc: intel-gfx
== Series Details ==
Series: Enable second DBuf slice for ICL and TGL (rev4)
URL : https://patchwork.freedesktop.org/series/70059/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7467 -> Patchwork_15545
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_15545 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_15545, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15545/index.html
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_15545:
### IGT changes ###
#### Possible regressions ####
* igt@i915_module_load@reload-no-display:
- fi-bwr-2160: [PASS][1] -> [INCOMPLETE][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7467/fi-bwr-2160/igt@i915_module_load@reload-no-display.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15545/fi-bwr-2160/igt@i915_module_load@reload-no-display.html
Known issues
------------
Here are the changes found in Patchwork_15545 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@i915_pm_rpm@basic-pci-d3-state:
- fi-icl-dsi: [PASS][3] -> [INCOMPLETE][4] ([i915#140] / [i915#189])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7467/fi-icl-dsi/igt@i915_pm_rpm@basic-pci-d3-state.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15545/fi-icl-dsi/igt@i915_pm_rpm@basic-pci-d3-state.html
* igt@kms_chamelium@dp-edid-read:
- fi-icl-u2: [PASS][5] -> [DMESG-WARN][6] ([i915#109])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7467/fi-icl-u2/igt@kms_chamelium@dp-edid-read.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15545/fi-icl-u2/igt@kms_chamelium@dp-edid-read.html
#### Possible fixes ####
* igt@i915_pm_rpm@module-reload:
- fi-skl-6770hq: [DMESG-WARN][7] ([i915#592]) -> [PASS][8]
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7467/fi-skl-6770hq/igt@i915_pm_rpm@module-reload.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15545/fi-skl-6770hq/igt@i915_pm_rpm@module-reload.html
* igt@i915_selftest@live_blt:
- fi-ivb-3770: [DMESG-FAIL][9] ([i915#563]) -> [PASS][10]
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7467/fi-ivb-3770/igt@i915_selftest@live_blt.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15545/fi-ivb-3770/igt@i915_selftest@live_blt.html
- fi-hsw-4770: [DMESG-FAIL][11] ([i915#563]) -> [PASS][12]
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7467/fi-hsw-4770/igt@i915_selftest@live_blt.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15545/fi-hsw-4770/igt@i915_selftest@live_blt.html
* igt@i915_selftest@live_gem_contexts:
- fi-skl-lmem: [INCOMPLETE][13] ([i915#424]) -> [PASS][14]
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7467/fi-skl-lmem/igt@i915_selftest@live_gem_contexts.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15545/fi-skl-lmem/igt@i915_selftest@live_gem_contexts.html
* igt@kms_frontbuffer_tracking@basic:
- fi-icl-guc: [FAIL][15] ([i915#49]) -> [PASS][16]
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7467/fi-icl-guc/igt@kms_frontbuffer_tracking@basic.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15545/fi-icl-guc/igt@kms_frontbuffer_tracking@basic.html
#### Warnings ####
* igt@gem_exec_suspend@basic-s4-devices:
- fi-kbl-x1275: [DMESG-WARN][17] ([fdo#107139] / [i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][18] ([fdo#107139] / [i915#62] / [i915#92])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7467/fi-kbl-x1275/igt@gem_exec_suspend@basic-s4-devices.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15545/fi-kbl-x1275/igt@gem_exec_suspend@basic-s4-devices.html
* igt@i915_selftest@live_gem_contexts:
- fi-hsw-peppy: [DMESG-FAIL][19] ([fdo#111692]) -> [INCOMPLETE][20] ([i915#694])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7467/fi-hsw-peppy/igt@i915_selftest@live_gem_contexts.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15545/fi-hsw-peppy/igt@i915_selftest@live_gem_contexts.html
* igt@kms_busy@basic-flip-pipe-b:
- fi-kbl-x1275: [DMESG-WARN][21] ([i915#62] / [i915#92]) -> [DMESG-WARN][22] ([i915#62] / [i915#92] / [i915#95]) +6 similar issues
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7467/fi-kbl-x1275/igt@kms_busy@basic-flip-pipe-b.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15545/fi-kbl-x1275/igt@kms_busy@basic-flip-pipe-b.html
* igt@kms_cursor_legacy@basic-flip-after-cursor-legacy:
- fi-kbl-x1275: [DMESG-WARN][23] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][24] ([i915#62] / [i915#92]) +6 similar issues
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7467/fi-kbl-x1275/igt@kms_cursor_legacy@basic-flip-after-cursor-legacy.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15545/fi-kbl-x1275/igt@kms_cursor_legacy@basic-flip-after-cursor-legacy.html
[fdo#107139]: https://bugs.freedesktop.org/show_bug.cgi?id=107139
[fdo#111692]: https://bugs.freedesktop.org/show_bug.cgi?id=111692
[i915#109]: https://gitlab.freedesktop.org/drm/intel/issues/109
[i915#140]: https://gitlab.freedesktop.org/drm/intel/issues/140
[i915#189]: https://gitlab.freedesktop.org/drm/intel/issues/189
[i915#424]: https://gitlab.freedesktop.org/drm/intel/issues/424
[i915#49]: https://gitlab.freedesktop.org/drm/intel/issues/49
[i915#563]: https://gitlab.freedesktop.org/drm/intel/issues/563
[i915#592]: https://gitlab.freedesktop.org/drm/intel/issues/592
[i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62
[i915#694]: https://gitlab.freedesktop.org/drm/intel/issues/694
[i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92
[i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95
Participating hosts (50 -> 45)
------------------------------
Missing (5): fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_7467 -> Patchwork_15545
CI-20190529: 20190529
CI_DRM_7467: 14954f24e7251b067b2081aaa09a7da6840da0d5 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5321: 9df50aef49e0da4413609d9866b41b82b725f2a0 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_15545: b26279b92ff697b244bf5fc1b298f8bec6c29c9a @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
b26279b92ff6 drm/i915: Correctly map DBUF slices to pipes
4fda5a6b8995 drm/i915: Manipulate DBuf slices properly
398ab0e115ee drm/i915: Move dbuf slice update to proper place
fe2e52f7a301 drm/i915: Remove skl_ddl_allocation struct
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15545/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for Enable second DBuf slice for ICL and TGL (rev4)
2019-12-03 0:20 ` [Intel-gfx] " Patchwork
(?)
@ 2019-12-03 9:22 ` Lisovskiy, Stanislav
-1 siblings, 0 replies; 26+ messages in thread
From: Lisovskiy, Stanislav @ 2019-12-03 9:22 UTC (permalink / raw)
To: intel-gfx
Module-reload failure was now discussed on sync up meeting - not related to this patch series.
Best Regards,
Lisovskiy Stanislav
Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo
________________________________________
From: Patchwork [patchwork@emeril.freedesktop.org]
Sent: Tuesday, December 03, 2019 2:20 AM
To: Lisovskiy, Stanislav
Cc: intel-gfx@lists.freedesktop.org
Subject: ✗ Fi.CI.BAT: failure for Enable second DBuf slice for ICL and TGL (rev4)
== Series Details ==
Series: Enable second DBuf slice for ICL and TGL (rev4)
URL : https://patchwork.freedesktop.org/series/70059/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7467 -> Patchwork_15545
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_15545 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_15545, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15545/index.html
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_15545:
### IGT changes ###
#### Possible regressions ####
* igt@i915_module_load@reload-no-display:
- fi-bwr-2160: [PASS][1] -> [INCOMPLETE][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7467/fi-bwr-2160/igt@i915_module_load@reload-no-display.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15545/fi-bwr-2160/igt@i915_module_load@reload-no-display.html
Known issues
------------
Here are the changes found in Patchwork_15545 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@i915_pm_rpm@basic-pci-d3-state:
- fi-icl-dsi: [PASS][3] -> [INCOMPLETE][4] ([i915#140] / [i915#189])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7467/fi-icl-dsi/igt@i915_pm_rpm@basic-pci-d3-state.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15545/fi-icl-dsi/igt@i915_pm_rpm@basic-pci-d3-state.html
* igt@kms_chamelium@dp-edid-read:
- fi-icl-u2: [PASS][5] -> [DMESG-WARN][6] ([i915#109])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7467/fi-icl-u2/igt@kms_chamelium@dp-edid-read.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15545/fi-icl-u2/igt@kms_chamelium@dp-edid-read.html
#### Possible fixes ####
* igt@i915_pm_rpm@module-reload:
- fi-skl-6770hq: [DMESG-WARN][7] ([i915#592]) -> [PASS][8]
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7467/fi-skl-6770hq/igt@i915_pm_rpm@module-reload.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15545/fi-skl-6770hq/igt@i915_pm_rpm@module-reload.html
* igt@i915_selftest@live_blt:
- fi-ivb-3770: [DMESG-FAIL][9] ([i915#563]) -> [PASS][10]
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7467/fi-ivb-3770/igt@i915_selftest@live_blt.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15545/fi-ivb-3770/igt@i915_selftest@live_blt.html
- fi-hsw-4770: [DMESG-FAIL][11] ([i915#563]) -> [PASS][12]
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7467/fi-hsw-4770/igt@i915_selftest@live_blt.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15545/fi-hsw-4770/igt@i915_selftest@live_blt.html
* igt@i915_selftest@live_gem_contexts:
- fi-skl-lmem: [INCOMPLETE][13] ([i915#424]) -> [PASS][14]
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7467/fi-skl-lmem/igt@i915_selftest@live_gem_contexts.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15545/fi-skl-lmem/igt@i915_selftest@live_gem_contexts.html
* igt@kms_frontbuffer_tracking@basic:
- fi-icl-guc: [FAIL][15] ([i915#49]) -> [PASS][16]
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7467/fi-icl-guc/igt@kms_frontbuffer_tracking@basic.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15545/fi-icl-guc/igt@kms_frontbuffer_tracking@basic.html
#### Warnings ####
* igt@gem_exec_suspend@basic-s4-devices:
- fi-kbl-x1275: [DMESG-WARN][17] ([fdo#107139] / [i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][18] ([fdo#107139] / [i915#62] / [i915#92])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7467/fi-kbl-x1275/igt@gem_exec_suspend@basic-s4-devices.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15545/fi-kbl-x1275/igt@gem_exec_suspend@basic-s4-devices.html
* igt@i915_selftest@live_gem_contexts:
- fi-hsw-peppy: [DMESG-FAIL][19] ([fdo#111692]) -> [INCOMPLETE][20] ([i915#694])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7467/fi-hsw-peppy/igt@i915_selftest@live_gem_contexts.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15545/fi-hsw-peppy/igt@i915_selftest@live_gem_contexts.html
* igt@kms_busy@basic-flip-pipe-b:
- fi-kbl-x1275: [DMESG-WARN][21] ([i915#62] / [i915#92]) -> [DMESG-WARN][22] ([i915#62] / [i915#92] / [i915#95]) +6 similar issues
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7467/fi-kbl-x1275/igt@kms_busy@basic-flip-pipe-b.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15545/fi-kbl-x1275/igt@kms_busy@basic-flip-pipe-b.html
* igt@kms_cursor_legacy@basic-flip-after-cursor-legacy:
- fi-kbl-x1275: [DMESG-WARN][23] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][24] ([i915#62] / [i915#92]) +6 similar issues
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7467/fi-kbl-x1275/igt@kms_cursor_legacy@basic-flip-after-cursor-legacy.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15545/fi-kbl-x1275/igt@kms_cursor_legacy@basic-flip-after-cursor-legacy.html
[fdo#107139]: https://bugs.freedesktop.org/show_bug.cgi?id=107139
[fdo#111692]: https://bugs.freedesktop.org/show_bug.cgi?id=111692
[i915#109]: https://gitlab.freedesktop.org/drm/intel/issues/109
[i915#140]: https://gitlab.freedesktop.org/drm/intel/issues/140
[i915#189]: https://gitlab.freedesktop.org/drm/intel/issues/189
[i915#424]: https://gitlab.freedesktop.org/drm/intel/issues/424
[i915#49]: https://gitlab.freedesktop.org/drm/intel/issues/49
[i915#563]: https://gitlab.freedesktop.org/drm/intel/issues/563
[i915#592]: https://gitlab.freedesktop.org/drm/intel/issues/592
[i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62
[i915#694]: https://gitlab.freedesktop.org/drm/intel/issues/694
[i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92
[i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95
Participating hosts (50 -> 45)
------------------------------
Missing (5): fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_7467 -> Patchwork_15545
CI-20190529: 20190529
CI_DRM_7467: 14954f24e7251b067b2081aaa09a7da6840da0d5 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5321: 9df50aef49e0da4413609d9866b41b82b725f2a0 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_15545: b26279b92ff697b244bf5fc1b298f8bec6c29c9a @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
b26279b92ff6 drm/i915: Correctly map DBUF slices to pipes
4fda5a6b8995 drm/i915: Manipulate DBuf slices properly
398ab0e115ee drm/i915: Move dbuf slice update to proper place
fe2e52f7a301 drm/i915: Remove skl_ddl_allocation struct
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15545/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 26+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for Enable second DBuf slice for ICL and TGL (rev5)
2019-11-29 13:37 ` [Intel-gfx] " Stanislav Lisovskiy
` (7 preceding siblings ...)
(?)
@ 2019-12-05 14:34 ` Patchwork
-1 siblings, 0 replies; 26+ messages in thread
From: Patchwork @ 2019-12-05 14:34 UTC (permalink / raw)
To: Lisovskiy, Stanislav; +Cc: intel-gfx
== Series Details ==
Series: Enable second DBuf slice for ICL and TGL (rev5)
URL : https://patchwork.freedesktop.org/series/70059/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7489 -> Patchwork_15602
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/index.html
Known issues
------------
Here are the changes found in Patchwork_15602 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@kms_frontbuffer_tracking@basic:
- fi-hsw-peppy: [PASS][1] -> [DMESG-WARN][2] ([i915#44])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/fi-hsw-peppy/igt@kms_frontbuffer_tracking@basic.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/fi-hsw-peppy/igt@kms_frontbuffer_tracking@basic.html
#### Possible fixes ####
* igt@gem_exec_gttfill@basic:
- {fi-tgl-guc}: [INCOMPLETE][3] ([fdo#111593]) -> [PASS][4]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/fi-tgl-guc/igt@gem_exec_gttfill@basic.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/fi-tgl-guc/igt@gem_exec_gttfill@basic.html
* igt@i915_pm_rpm@module-reload:
- fi-skl-6770hq: [DMESG-WARN][5] ([i915#592]) -> [PASS][6]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/fi-skl-6770hq/igt@i915_pm_rpm@module-reload.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/fi-skl-6770hq/igt@i915_pm_rpm@module-reload.html
* igt@i915_selftest@live_blt:
- fi-byt-n2820: [DMESG-FAIL][7] ([i915#725]) -> [PASS][8]
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/fi-byt-n2820/igt@i915_selftest@live_blt.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/fi-byt-n2820/igt@i915_selftest@live_blt.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [FAIL][9] ([fdo#111096] / [i915#323]) -> [PASS][10]
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
#### Warnings ####
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
- fi-kbl-x1275: [DMESG-WARN][11] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][12] ([i915#62] / [i915#92]) +6 similar issues
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/fi-kbl-x1275/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/fi-kbl-x1275/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html
* igt@kms_flip@basic-flip-vs-modeset:
- fi-kbl-x1275: [DMESG-WARN][13] ([i915#62] / [i915#92]) -> [DMESG-WARN][14] ([i915#62] / [i915#92] / [i915#95]) +3 similar issues
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/fi-kbl-x1275/igt@kms_flip@basic-flip-vs-modeset.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/fi-kbl-x1275/igt@kms_flip@basic-flip-vs-modeset.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096
[fdo#111593]: https://bugs.freedesktop.org/show_bug.cgi?id=111593
[i915#109]: https://gitlab.freedesktop.org/drm/intel/issues/109
[i915#323]: https://gitlab.freedesktop.org/drm/intel/issues/323
[i915#44]: https://gitlab.freedesktop.org/drm/intel/issues/44
[i915#592]: https://gitlab.freedesktop.org/drm/intel/issues/592
[i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62
[i915#710]: https://gitlab.freedesktop.org/drm/intel/issues/710
[i915#725]: https://gitlab.freedesktop.org/drm/intel/issues/725
[i915#726]: https://gitlab.freedesktop.org/drm/intel/issues/726
[i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92
[i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95
Participating hosts (53 -> 47)
------------------------------
Additional (1): fi-hsw-4770r
Missing (7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_7489 -> Patchwork_15602
CI-20190529: 20190529
CI_DRM_7489: 969b4daff0be9ed5dcefda656621bad5f9a06906 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5332: 59be90b3c76113d03a1bb095c4d4585e51058f4a @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_15602: bc63fa083ebab437445ac7b1f395ccd512e61611 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
bc63fa083eba drm/i915: Correctly map DBUF slices to pipes
607986baf168 drm/i915: Manipulate DBuf slices properly
bedac556a9da drm/i915: Move dbuf slice update to proper place
48b81e12bcf9 drm/i915: Remove skl_ddl_allocation struct
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 26+ messages in thread
* [Intel-gfx] ✗ Fi.CI.IGT: failure for Enable second DBuf slice for ICL and TGL (rev5)
2019-11-29 13:37 ` [Intel-gfx] " Stanislav Lisovskiy
` (8 preceding siblings ...)
(?)
@ 2019-12-05 18:40 ` Patchwork
2019-12-09 7:55 ` Lisovskiy, Stanislav
-1 siblings, 1 reply; 26+ messages in thread
From: Patchwork @ 2019-12-05 18:40 UTC (permalink / raw)
To: Lisovskiy, Stanislav; +Cc: intel-gfx
== Series Details ==
Series: Enable second DBuf slice for ICL and TGL (rev5)
URL : https://patchwork.freedesktop.org/series/70059/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7489_full -> Patchwork_15602_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_15602_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_15602_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_15602_full:
### IGT changes ###
#### Possible regressions ####
* igt@gem_exec_balancer@bonded-cork:
- shard-iclb: [PASS][1] -> [DMESG-WARN][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-iclb4/igt@gem_exec_balancer@bonded-cork.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-iclb4/igt@gem_exec_balancer@bonded-cork.html
* igt@gem_exec_parse_blt@allowed-all:
- shard-skl: [PASS][3] -> [DMESG-WARN][4]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-skl8/igt@gem_exec_parse_blt@allowed-all.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-skl9/igt@gem_exec_parse_blt@allowed-all.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-indfb-pgflip-blt:
- shard-skl: NOTRUN -> [DMESG-WARN][5]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-skl7/igt@kms_frontbuffer_tracking@psr-1p-primscrn-indfb-pgflip-blt.html
* igt@perf_pmu@busy-idle-bcs0:
- shard-kbl: [PASS][6] -> [DMESG-WARN][7] +2 similar issues
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-kbl1/igt@perf_pmu@busy-idle-bcs0.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-kbl4/igt@perf_pmu@busy-idle-bcs0.html
Known issues
------------
Here are the changes found in Patchwork_15602_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_busy@extended-parallel-vcs1:
- shard-iclb: [PASS][8] -> [SKIP][9] ([fdo#112080]) +6 similar issues
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-iclb1/igt@gem_busy@extended-parallel-vcs1.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-iclb3/igt@gem_busy@extended-parallel-vcs1.html
* igt@gem_ctx_isolation@bcs0-s3:
- shard-apl: [PASS][10] -> [DMESG-WARN][11] ([i915#180]) +1 similar issue
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-apl3/igt@gem_ctx_isolation@bcs0-s3.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-apl6/igt@gem_ctx_isolation@bcs0-s3.html
* igt@gem_ctx_isolation@rcs0-s3:
- shard-kbl: [PASS][12] -> [DMESG-WARN][13] ([i915#180]) +6 similar issues
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-kbl1/igt@gem_ctx_isolation@rcs0-s3.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-kbl3/igt@gem_ctx_isolation@rcs0-s3.html
* igt@gem_ctx_persistence@vcs1-queued:
- shard-iclb: [PASS][14] -> [SKIP][15] ([fdo#109276] / [fdo#112080]) +1 similar issue
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-iclb2/igt@gem_ctx_persistence@vcs1-queued.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-iclb6/igt@gem_ctx_persistence@vcs1-queued.html
* igt@gem_eio@kms:
- shard-snb: [PASS][16] -> [INCOMPLETE][17] ([i915#82])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-snb1/igt@gem_eio@kms.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-snb6/igt@gem_eio@kms.html
* igt@gem_exec_balancer@smoke:
- shard-iclb: [PASS][18] -> [SKIP][19] ([fdo#110854])
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-iclb2/igt@gem_exec_balancer@smoke.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-iclb6/igt@gem_exec_balancer@smoke.html
* igt@gem_exec_schedule@fifo-bsd1:
- shard-iclb: [PASS][20] -> [SKIP][21] ([fdo#109276]) +4 similar issues
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-iclb1/igt@gem_exec_schedule@fifo-bsd1.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-iclb3/igt@gem_exec_schedule@fifo-bsd1.html
* igt@gem_exec_schedule@preempt-hang-bsd:
- shard-iclb: [PASS][22] -> [SKIP][23] ([fdo#112146]) +1 similar issue
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-iclb6/igt@gem_exec_schedule@preempt-hang-bsd.html
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-iclb1/igt@gem_exec_schedule@preempt-hang-bsd.html
* igt@gem_exec_schedule@preempt-queue-chain-bsd2:
- shard-tglb: [PASS][24] -> [INCOMPLETE][25] ([fdo#111677])
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-tglb5/igt@gem_exec_schedule@preempt-queue-chain-bsd2.html
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-tglb6/igt@gem_exec_schedule@preempt-queue-chain-bsd2.html
* igt@gem_exec_schedule@preempt-queue-chain-render:
- shard-tglb: [PASS][26] -> [INCOMPLETE][27] ([fdo#111606] / [fdo#111677])
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-tglb1/igt@gem_exec_schedule@preempt-queue-chain-render.html
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-tglb6/igt@gem_exec_schedule@preempt-queue-chain-render.html
* igt@gem_persistent_relocs@forked-interruptible-thrashing:
- shard-kbl: [PASS][28] -> [FAIL][29] ([i915#520])
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-kbl1/igt@gem_persistent_relocs@forked-interruptible-thrashing.html
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-kbl2/igt@gem_persistent_relocs@forked-interruptible-thrashing.html
* igt@gem_persistent_relocs@forked-thrashing:
- shard-iclb: [PASS][30] -> [TIMEOUT][31] ([i915#530])
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-iclb4/igt@gem_persistent_relocs@forked-thrashing.html
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-iclb4/igt@gem_persistent_relocs@forked-thrashing.html
* igt@gem_ppgtt@flink-and-close-vma-leak:
- shard-skl: [PASS][32] -> [FAIL][33] ([i915#644])
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-skl3/igt@gem_ppgtt@flink-and-close-vma-leak.html
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-skl8/igt@gem_ppgtt@flink-and-close-vma-leak.html
* igt@gem_userptr_blits@map-fixed-invalidate-busy-gup:
- shard-snb: [PASS][34] -> [DMESG-WARN][35] ([fdo#111870])
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-snb6/igt@gem_userptr_blits@map-fixed-invalidate-busy-gup.html
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-snb2/igt@gem_userptr_blits@map-fixed-invalidate-busy-gup.html
* igt@gem_workarounds@suspend-resume-fd:
- shard-skl: [PASS][36] -> [INCOMPLETE][37] ([i915#69]) +1 similar issue
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-skl3/igt@gem_workarounds@suspend-resume-fd.html
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-skl8/igt@gem_workarounds@suspend-resume-fd.html
* igt@i915_pm_rpm@system-suspend-execbuf:
- shard-skl: [PASS][38] -> [INCOMPLETE][39] ([i915#151] / [i915#69]) +1 similar issue
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-skl9/igt@i915_pm_rpm@system-suspend-execbuf.html
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-skl2/igt@i915_pm_rpm@system-suspend-execbuf.html
* igt@i915_selftest@live_blt:
- shard-hsw: [PASS][40] -> [DMESG-FAIL][41] ([i915#683])
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-hsw4/igt@i915_selftest@live_blt.html
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-hsw6/igt@i915_selftest@live_blt.html
* igt@kms_big_fb@y-tiled-16bpp-rotate-0:
- shard-kbl: [PASS][42] -> [INCOMPLETE][43] ([fdo#103665] / [fdo#112413])
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-kbl4/igt@kms_big_fb@y-tiled-16bpp-rotate-0.html
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-kbl4/igt@kms_big_fb@y-tiled-16bpp-rotate-0.html
* igt@kms_big_fb@y-tiled-16bpp-rotate-180:
- shard-tglb: [PASS][44] -> [INCOMPLETE][45] ([i915#667])
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-tglb8/igt@kms_big_fb@y-tiled-16bpp-rotate-180.html
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-tglb7/igt@kms_big_fb@y-tiled-16bpp-rotate-180.html
* igt@kms_big_fb@y-tiled-8bpp-rotate-180:
- shard-skl: [PASS][46] -> [INCOMPLETE][47] ([fdo#112347])
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-skl1/igt@kms_big_fb@y-tiled-8bpp-rotate-180.html
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-skl8/igt@kms_big_fb@y-tiled-8bpp-rotate-180.html
* igt@kms_ccs@pipe-a-crc-primary-basic:
- shard-skl: [PASS][48] -> [INCOMPLETE][49] ([i915#667])
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-skl9/igt@kms_ccs@pipe-a-crc-primary-basic.html
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-skl6/igt@kms_ccs@pipe-a-crc-primary-basic.html
* igt@kms_cursor_crc@pipe-a-cursor-128x42-onscreen:
- shard-hsw: [PASS][50] -> [DMESG-WARN][51] ([IGT#6])
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-hsw5/igt@kms_cursor_crc@pipe-a-cursor-128x42-onscreen.html
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-hsw6/igt@kms_cursor_crc@pipe-a-cursor-128x42-onscreen.html
* igt@kms_cursor_crc@pipe-c-cursor-256x85-random:
- shard-skl: [PASS][52] -> [FAIL][53] ([i915#54]) +1 similar issue
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-skl8/igt@kms_cursor_crc@pipe-c-cursor-256x85-random.html
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-skl8/igt@kms_cursor_crc@pipe-c-cursor-256x85-random.html
* igt@kms_cursor_crc@pipe-d-cursor-suspend:
- shard-tglb: [PASS][54] -> [INCOMPLETE][55] ([i915#460]) +1 similar issue
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-tglb9/igt@kms_cursor_crc@pipe-d-cursor-suspend.html
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-tglb4/igt@kms_cursor_crc@pipe-d-cursor-suspend.html
* igt@kms_draw_crc@draw-method-rgb565-render-xtiled:
- shard-kbl: [PASS][56] -> [DMESG-WARN][57] ([i915#728]) +4 similar issues
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-kbl3/igt@kms_draw_crc@draw-method-rgb565-render-xtiled.html
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-kbl1/igt@kms_draw_crc@draw-method-rgb565-render-xtiled.html
* igt@kms_draw_crc@draw-method-xrgb2101010-render-xtiled:
- shard-skl: [PASS][58] -> [DMESG-WARN][59] ([i915#728]) +4 similar issues
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-skl3/igt@kms_draw_crc@draw-method-xrgb2101010-render-xtiled.html
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-skl7/igt@kms_draw_crc@draw-method-xrgb2101010-render-xtiled.html
* igt@kms_fbcon_fbt@fbc-suspend:
- shard-tglb: [PASS][60] -> [INCOMPLETE][61] ([i915#435] / [i915#456] / [i915#460])
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-tglb7/igt@kms_fbcon_fbt@fbc-suspend.html
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-tglb5/igt@kms_fbcon_fbt@fbc-suspend.html
* igt@kms_flip@flip-vs-suspend:
- shard-skl: [PASS][62] -> [INCOMPLETE][63] ([i915#221])
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-skl5/igt@kms_flip@flip-vs-suspend.html
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-skl5/igt@kms_flip@flip-vs-suspend.html
* igt@kms_flip@flip-vs-suspend-interruptible:
- shard-tglb: [PASS][64] -> [INCOMPLETE][65] ([i915#456] / [i915#460] / [i915#516])
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-tglb9/igt@kms_flip@flip-vs-suspend-interruptible.html
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-tglb8/igt@kms_flip@flip-vs-suspend-interruptible.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-indfb-draw-mmap-gtt:
- shard-tglb: [PASS][66] -> [INCOMPLETE][67] ([i915#474])
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-tglb7/igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-indfb-draw-mmap-gtt.html
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-tglb1/igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-indfb-draw-mmap-gtt.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-blt:
- shard-iclb: [PASS][68] -> [FAIL][69] ([i915#49]) +1 similar issue
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-iclb3/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-blt.html
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-iclb2/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-blt.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-pwrite:
- shard-tglb: [PASS][70] -> [FAIL][71] ([i915#49])
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-tglb7/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-pwrite.html
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-tglb5/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-pwrite.html
* igt@kms_frontbuffer_tracking@fbcpsr-suspend:
- shard-tglb: [PASS][72] -> [INCOMPLETE][73] ([i915#456] / [i915#460] / [i915#474])
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-tglb6/igt@kms_frontbuffer_tracking@fbcpsr-suspend.html
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-tglb2/igt@kms_frontbuffer_tracking@fbcpsr-suspend.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-mmap-cpu:
- shard-tglb: [PASS][74] -> [DMESG-WARN][75] ([i915#728]) +3 similar issues
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-tglb7/igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-mmap-cpu.html
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-tglb7/igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-mmap-cpu.html
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
- shard-tglb: [PASS][76] -> [INCOMPLETE][77] ([i915#456] / [i915#460])
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-tglb9/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b.html
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-tglb2/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b.html
* igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
- shard-skl: [PASS][78] -> [FAIL][79] ([fdo#108145] / [i915#265])
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-skl4/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-skl4/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
* igt@kms_psr@psr2_cursor_render:
- shard-iclb: [PASS][80] -> [SKIP][81] ([fdo#109441])
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-iclb2/igt@kms_psr@psr2_cursor_render.html
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-iclb6/igt@kms_psr@psr2_cursor_render.html
* igt@perf@disabled-read-error:
- shard-iclb: [PASS][82] -> [DMESG-WARN][83] ([i915#645])
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-iclb4/igt@perf@disabled-read-error.html
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-iclb2/igt@perf@disabled-read-error.html
* igt@perf_pmu@busy-check-all-rcs0:
- shard-iclb: [PASS][84] -> [DMESG-WARN][85] ([i915#728]) +6 similar issues
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-iclb4/igt@perf_pmu@busy-check-all-rcs0.html
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-iclb4/igt@perf_pmu@busy-check-all-rcs0.html
#### Possible fixes ####
* igt@gem_busy@busy-vcs1:
- shard-iclb: [SKIP][86] ([fdo#112080]) -> [PASS][87] +5 similar issues
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-iclb3/igt@gem_busy@busy-vcs1.html
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-iclb2/igt@gem_busy@busy-vcs1.html
* igt@gem_ctx_persistence@vcs1-mixed:
- shard-iclb: [SKIP][88] ([fdo#109276] / [fdo#112080]) -> [PASS][89] +1 similar issue
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-iclb6/igt@gem_ctx_persistence@vcs1-mixed.html
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-iclb1/igt@gem_ctx_persistence@vcs1-mixed.html
* igt@gem_exec_balancer@hang:
- shard-kbl: [DMESG-WARN][90] -> [PASS][91] +1 similar issue
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-kbl1/igt@gem_exec_balancer@hang.html
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-kbl3/igt@gem_exec_balancer@hang.html
* igt@gem_exec_create@forked:
- shard-tglb: [INCOMPLETE][92] ([fdo#108838] / [i915#435]) -> [PASS][93]
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-tglb4/igt@gem_exec_create@forked.html
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-tglb9/igt@gem_exec_create@forked.html
* igt@gem_exec_nop@basic-sequential:
- shard-tglb: [INCOMPLETE][94] ([i915#435]) -> [PASS][95]
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-tglb6/igt@gem_exec_nop@basic-sequential.html
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-tglb3/igt@gem_exec_nop@basic-sequential.html
* igt@gem_exec_parallel@vecs0-fds:
- shard-hsw: [FAIL][96] ([i915#676]) -> [PASS][97] +2 similar issues
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-hsw1/igt@gem_exec_parallel@vecs0-fds.html
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-hsw7/igt@gem_exec_parallel@vecs0-fds.html
* igt@gem_exec_schedule@preempt-queue-contexts-bsd2:
- shard-tglb: [INCOMPLETE][98] ([fdo#111606] / [fdo#111677]) -> [PASS][99]
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-tglb6/igt@gem_exec_schedule@preempt-queue-contexts-bsd2.html
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-tglb8/igt@gem_exec_schedule@preempt-queue-contexts-bsd2.html
* igt@gem_persistent_relocs@forked-interruptible-faulting-reloc-thrash-inactive:
- shard-hsw: [TIMEOUT][100] ([i915#530]) -> [PASS][101]
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-hsw5/igt@gem_persistent_relocs@forked-interruptible-faulting-reloc-thrash-inactive.html
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-hsw2/igt@gem_persistent_relocs@forked-interruptible-faulting-reloc-thrash-inactive.html
* igt@gem_ppgtt@flink-and-close-vma-leak:
- shard-iclb: [FAIL][102] ([i915#644]) -> [PASS][103]
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-iclb5/igt@gem_ppgtt@flink-and-close-vma-leak.html
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-iclb7/igt@gem_ppgtt@flink-and-close-vma-leak.html
* igt@gem_userptr_blits@sync-unmap:
- shard-snb: [DMESG-WARN][104] ([fdo#111870]) -> [PASS][105]
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-snb6/igt@gem_userptr_blits@sync-unmap.html
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-snb5/igt@gem_userptr_blits@sync-unmap.html
* igt@i915_pm_backlight@fade_with_suspend:
- shard-tglb: [INCOMPLETE][106] ([i915#456] / [i915#460]) -> [PASS][107]
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-tglb1/igt@i915_pm_backlight@fade_with_suspend.html
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-tglb6/igt@i915_pm_backlight@fade_with_suspend.html
* igt@i915_pm_dc@dc6-dpms:
- shard-iclb: [FAIL][108] ([i915#454]) -> [PASS][109]
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-iclb3/igt@i915_pm_dc@dc6-dpms.html
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-iclb1/igt@i915_pm_dc@dc6-dpms.html
* igt@kms_big_fb@yf-tiled-16bpp-rotate-0:
- shard-kbl: [INCOMPLETE][110] ([fdo#103665]) -> [PASS][111] +1 similar issue
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-kbl6/igt@kms_big_fb@yf-tiled-16bpp-rotate-0.html
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-kbl3/igt@kms_big_fb@yf-tiled-16bpp-rotate-0.html
* igt@kms_cursor_crc@pipe-a-cursor-suspend:
- shard-kbl: [DMESG-WARN][112] ([i915#180]) -> [PASS][113] +3 similar issues
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-kbl4/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-kbl2/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
* igt@kms_cursor_crc@pipe-b-cursor-64x21-onscreen:
- shard-kbl: [DMESG-WARN][114] ([IGT#6]) -> [PASS][115]
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-kbl3/igt@kms_cursor_crc@pipe-b-cursor-64x21-onscreen.html
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-kbl3/igt@kms_cursor_crc@pipe-b-cursor-64x21-onscreen.html
* igt@kms_cursor_crc@pipe-b-cursor-64x21-sliding:
- shard-skl: [FAIL][116] ([i915#54]) -> [PASS][117] +1 similar issue
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-skl7/igt@kms_cursor_crc@pipe-b-cursor-64x21-sliding.html
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-skl5/igt@kms_cursor_crc@pipe-b-cursor-64x21-sliding.html
* igt@kms_draw_crc@draw-method-rgb565-mmap-wc-xtiled:
- shard-skl: [FAIL][118] ([i915#52] / [i915#54]) -> [PASS][119]
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-skl9/igt@kms_draw_crc@draw-method-rgb565-mmap-wc-xtiled.html
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-skl4/igt@kms_draw_crc@draw-method-rgb565-mmap-wc-xtiled.html
* igt@kms_flip@2x-flip-vs-expired-vblank-interruptible:
- shard-glk: [FAIL][120] ([i915#79]) -> [PASS][121]
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-glk7/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible.html
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-glk9/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible:
- shard-skl: [FAIL][122] ([i915#79]) -> [PASS][123]
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-skl5/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-skl4/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
* igt@kms_flip@flip-vs-suspend-interruptible:
- shard-skl: [INCOMPLETE][124] ([i915#221]) -> [PASS][125]
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-skl7/igt@kms_flip@flip-vs-suspend-interruptible.html
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-skl7/igt@kms_flip@flip-vs-suspend-interruptible.html
* igt@kms_flip_tiling@flip-x-tiled:
- shard-tglb: [FAIL][126] ([i915#699]) -> [PASS][127]
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-tglb5/igt@kms_flip_tiling@flip-x-tiled.html
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-tglb3/igt@kms_flip_tiling@flip-x-tiled.html
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-render:
- shard-iclb: [FAIL][128] ([i915#49]) -> [PASS][129] +3 similar issues
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-iclb6/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-render.html
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-iclb6/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-render.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-blt:
- shard-tglb: [FAIL][130] ([i915#49]) -> [PASS][131] +2 similar issues
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-tglb6/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-blt.html
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-tglb8/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-blt.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-indfb-msflip-blt:
- shard-skl: [DMESG-WARN][132] ([i915#728]) -> [PASS][133] +5 similar issues
[132]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-skl1/igt@kms_frontbuffer_tracking@psr-1p-primscrn-indfb-msflip-blt.html
[133]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-skl5/igt@kms_frontbuffer_tracking@psr-1p-primscrn-indfb-msflip-blt.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-indfb-plflip-blt:
- shard-skl: [INCOMPLETE][134] ([i915#123]) -> [PASS][135]
[134]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-skl10/igt@kms_frontbuffer_tracking@psr-1p-primscrn-indfb-plflip-blt.html
[135]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-skl5/igt@kms_frontbuffer_tracking@psr-1p-primscrn-indfb-plflip-blt.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-render:
- shard-tglb: [DMESG-WARN][136] ([i915#728]) -> [PASS][137] +2 similar issues
[136]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-tglb6/igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-render.html
[137]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-tglb3/igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-render.html
* igt@kms_frontbuffer_tracking@psr-1p-rte:
- shard-iclb: [DMESG-WARN][138] ([i915#728]) -> [PASS][139] +3 similar issues
[138]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-iclb6/igt@kms_frontbuffer_tracking@psr-1p-rte.html
[139]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-iclb1/igt@kms_frontbuffer_tracking@psr-1p-rte.html
* igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes:
- shard-apl: [DMESG-WARN][140] ([i915#180]) -> [PASS][141] +1 similar issue
[140]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-apl6/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html
[141]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-apl4/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html
* igt@kms_psr@psr2_sprite_mmap_cpu:
- shard-iclb: [SKIP][142] ([fdo#109441]) -> [PASS][143]
[142]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-iclb4/igt@kms_psr@psr2_sprite_mmap_cpu.html
[143]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-iclb2/igt@kms_psr@psr2_sprite_mmap_cpu.html
* igt@kms_psr@psr2_suspend:
- shard-tglb: [DMESG-WARN][144] ([i915#402]) -> [PASS][145]
[144]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-tglb6/igt@kms_psr@psr2_suspend.html
[145]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-tglb8/igt@kms_psr@psr2_suspend.html
* igt@kms_setmode@basic:
- shard-kbl: [FAIL][146] ([i915#31]) -> [PASS][147]
[146]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-kbl2/igt@kms_setmode@basic.html
[147]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-kbl3/igt@kms_setmode@basic.html
* igt@kms_vblank@pipe-c-ts-continuation-dpms-suspend:
- shard-tglb: [INCOMPLETE][148] ([i915#460]) -> [PASS][149]
[148]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-tglb4/igt@kms_vblank@pipe-c-ts-continuation-dpms-suspend.html
[149]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-tglb4/igt@kms_vblank@pipe-c-ts-continuation-dpms-suspend.html
* igt@perf@oa-exponents:
- shard-hsw: [FAIL][150] ([i915#84]) -> [PASS][151]
[150]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-hsw4/igt@perf@oa-exponents.html
[151]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-hsw5/igt@perf@oa-exponents.html
* igt@prime_vgem@fence-wait-bsd2:
- shard-iclb: [SKIP][152] ([fdo#109276]) -> [PASS][153] +10 similar issues
[152]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-iclb3/igt@prime_vgem@fence-wait-bsd2.html
[153]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-iclb1/igt@prime_vgem@fence-wait-bsd2.html
#### Warnings ####
* igt@gem_ctx_isolation@vcs1-nonpriv:
- shard-iclb: [FAIL][154] ([IGT#28]) -> [SKIP][155] ([fdo#109276] / [fdo#112080])
[154]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-iclb2/igt@gem_ctx_isolation@vcs1-nonpriv.html
[155]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-iclb6/igt@gem_ctx_isolation@vcs1-nonpriv.html
* igt@kms_flip@flip-vs-suspend:
- shard-kbl: [INCOMPLETE][156] ([fdo#103665] / [i915#600]) -> [DMESG-WARN][157] ([i915#180])
[156]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-kbl7/igt@kms_fl
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for Enable second DBuf slice for ICL and TGL (rev5)
2019-12-05 18:40 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
@ 2019-12-09 7:55 ` Lisovskiy, Stanislav
2019-12-09 8:11 ` Vudum, Lakshminarayana
0 siblings, 1 reply; 26+ messages in thread
From: Lisovskiy, Stanislav @ 2019-12-09 7:55 UTC (permalink / raw)
To: intel-gfx; +Cc: Vudum, Lakshminarayana
Getting already a bit pissed off with need on hitting retest button as those failures
have nothing in common with DBuf changes. It's again gem-gem-gem...
Best Regards,
Lisovskiy Stanislav
Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo
________________________________________
From: Patchwork [patchwork@emeril.freedesktop.org]
Sent: Thursday, December 05, 2019 8:40 PM
To: Lisovskiy, Stanislav
Cc: intel-gfx@lists.freedesktop.org
Subject: ✗ Fi.CI.IGT: failure for Enable second DBuf slice for ICL and TGL (rev5)
== Series Details ==
Series: Enable second DBuf slice for ICL and TGL (rev5)
URL : https://patchwork.freedesktop.org/series/70059/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7489_full -> Patchwork_15602_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_15602_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_15602_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_15602_full:
### IGT changes ###
#### Possible regressions ####
* igt@gem_exec_balancer@bonded-cork:
- shard-iclb: [PASS][1] -> [DMESG-WARN][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-iclb4/igt@gem_exec_balancer@bonded-cork.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-iclb4/igt@gem_exec_balancer@bonded-cork.html
* igt@gem_exec_parse_blt@allowed-all:
- shard-skl: [PASS][3] -> [DMESG-WARN][4]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-skl8/igt@gem_exec_parse_blt@allowed-all.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-skl9/igt@gem_exec_parse_blt@allowed-all.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-indfb-pgflip-blt:
- shard-skl: NOTRUN -> [DMESG-WARN][5]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-skl7/igt@kms_frontbuffer_tracking@psr-1p-primscrn-indfb-pgflip-blt.html
* igt@perf_pmu@busy-idle-bcs0:
- shard-kbl: [PASS][6] -> [DMESG-WARN][7] +2 similar issues
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-kbl1/igt@perf_pmu@busy-idle-bcs0.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-kbl4/igt@perf_pmu@busy-idle-bcs0.html
Known issues
------------
Here are the changes found in Patchwork_15602_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_busy@extended-parallel-vcs1:
- shard-iclb: [PASS][8] -> [SKIP][9] ([fdo#112080]) +6 similar issues
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-iclb1/igt@gem_busy@extended-parallel-vcs1.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-iclb3/igt@gem_busy@extended-parallel-vcs1.html
* igt@gem_ctx_isolation@bcs0-s3:
- shard-apl: [PASS][10] -> [DMESG-WARN][11] ([i915#180]) +1 similar issue
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-apl3/igt@gem_ctx_isolation@bcs0-s3.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-apl6/igt@gem_ctx_isolation@bcs0-s3.html
* igt@gem_ctx_isolation@rcs0-s3:
- shard-kbl: [PASS][12] -> [DMESG-WARN][13] ([i915#180]) +6 similar issues
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-kbl1/igt@gem_ctx_isolation@rcs0-s3.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-kbl3/igt@gem_ctx_isolation@rcs0-s3.html
* igt@gem_ctx_persistence@vcs1-queued:
- shard-iclb: [PASS][14] -> [SKIP][15] ([fdo#109276] / [fdo#112080]) +1 similar issue
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-iclb2/igt@gem_ctx_persistence@vcs1-queued.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-iclb6/igt@gem_ctx_persistence@vcs1-queued.html
* igt@gem_eio@kms:
- shard-snb: [PASS][16] -> [INCOMPLETE][17] ([i915#82])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-snb1/igt@gem_eio@kms.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-snb6/igt@gem_eio@kms.html
* igt@gem_exec_balancer@smoke:
- shard-iclb: [PASS][18] -> [SKIP][19] ([fdo#110854])
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-iclb2/igt@gem_exec_balancer@smoke.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-iclb6/igt@gem_exec_balancer@smoke.html
* igt@gem_exec_schedule@fifo-bsd1:
- shard-iclb: [PASS][20] -> [SKIP][21] ([fdo#109276]) +4 similar issues
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-iclb1/igt@gem_exec_schedule@fifo-bsd1.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-iclb3/igt@gem_exec_schedule@fifo-bsd1.html
* igt@gem_exec_schedule@preempt-hang-bsd:
- shard-iclb: [PASS][22] -> [SKIP][23] ([fdo#112146]) +1 similar issue
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-iclb6/igt@gem_exec_schedule@preempt-hang-bsd.html
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-iclb1/igt@gem_exec_schedule@preempt-hang-bsd.html
* igt@gem_exec_schedule@preempt-queue-chain-bsd2:
- shard-tglb: [PASS][24] -> [INCOMPLETE][25] ([fdo#111677])
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-tglb5/igt@gem_exec_schedule@preempt-queue-chain-bsd2.html
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-tglb6/igt@gem_exec_schedule@preempt-queue-chain-bsd2.html
* igt@gem_exec_schedule@preempt-queue-chain-render:
- shard-tglb: [PASS][26] -> [INCOMPLETE][27] ([fdo#111606] / [fdo#111677])
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-tglb1/igt@gem_exec_schedule@preempt-queue-chain-render.html
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-tglb6/igt@gem_exec_schedule@preempt-queue-chain-render.html
* igt@gem_persistent_relocs@forked-interruptible-thrashing:
- shard-kbl: [PASS][28] -> [FAIL][29] ([i915#520])
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-kbl1/igt@gem_persistent_relocs@forked-interruptible-thrashing.html
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-kbl2/igt@gem_persistent_relocs@forked-interruptible-thrashing.html
* igt@gem_persistent_relocs@forked-thrashing:
- shard-iclb: [PASS][30] -> [TIMEOUT][31] ([i915#530])
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-iclb4/igt@gem_persistent_relocs@forked-thrashing.html
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-iclb4/igt@gem_persistent_relocs@forked-thrashing.html
* igt@gem_ppgtt@flink-and-close-vma-leak:
- shard-skl: [PASS][32] -> [FAIL][33] ([i915#644])
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-skl3/igt@gem_ppgtt@flink-and-close-vma-leak.html
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-skl8/igt@gem_ppgtt@flink-and-close-vma-leak.html
* igt@gem_userptr_blits@map-fixed-invalidate-busy-gup:
- shard-snb: [PASS][34] -> [DMESG-WARN][35] ([fdo#111870])
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-snb6/igt@gem_userptr_blits@map-fixed-invalidate-busy-gup.html
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-snb2/igt@gem_userptr_blits@map-fixed-invalidate-busy-gup.html
* igt@gem_workarounds@suspend-resume-fd:
- shard-skl: [PASS][36] -> [INCOMPLETE][37] ([i915#69]) +1 similar issue
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-skl3/igt@gem_workarounds@suspend-resume-fd.html
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-skl8/igt@gem_workarounds@suspend-resume-fd.html
* igt@i915_pm_rpm@system-suspend-execbuf:
- shard-skl: [PASS][38] -> [INCOMPLETE][39] ([i915#151] / [i915#69]) +1 similar issue
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-skl9/igt@i915_pm_rpm@system-suspend-execbuf.html
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-skl2/igt@i915_pm_rpm@system-suspend-execbuf.html
* igt@i915_selftest@live_blt:
- shard-hsw: [PASS][40] -> [DMESG-FAIL][41] ([i915#683])
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-hsw4/igt@i915_selftest@live_blt.html
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-hsw6/igt@i915_selftest@live_blt.html
* igt@kms_big_fb@y-tiled-16bpp-rotate-0:
- shard-kbl: [PASS][42] -> [INCOMPLETE][43] ([fdo#103665] / [fdo#112413])
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-kbl4/igt@kms_big_fb@y-tiled-16bpp-rotate-0.html
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-kbl4/igt@kms_big_fb@y-tiled-16bpp-rotate-0.html
* igt@kms_big_fb@y-tiled-16bpp-rotate-180:
- shard-tglb: [PASS][44] -> [INCOMPLETE][45] ([i915#667])
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-tglb8/igt@kms_big_fb@y-tiled-16bpp-rotate-180.html
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-tglb7/igt@kms_big_fb@y-tiled-16bpp-rotate-180.html
* igt@kms_big_fb@y-tiled-8bpp-rotate-180:
- shard-skl: [PASS][46] -> [INCOMPLETE][47] ([fdo#112347])
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-skl1/igt@kms_big_fb@y-tiled-8bpp-rotate-180.html
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-skl8/igt@kms_big_fb@y-tiled-8bpp-rotate-180.html
* igt@kms_ccs@pipe-a-crc-primary-basic:
- shard-skl: [PASS][48] -> [INCOMPLETE][49] ([i915#667])
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-skl9/igt@kms_ccs@pipe-a-crc-primary-basic.html
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-skl6/igt@kms_ccs@pipe-a-crc-primary-basic.html
* igt@kms_cursor_crc@pipe-a-cursor-128x42-onscreen:
- shard-hsw: [PASS][50] -> [DMESG-WARN][51] ([IGT#6])
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-hsw5/igt@kms_cursor_crc@pipe-a-cursor-128x42-onscreen.html
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-hsw6/igt@kms_cursor_crc@pipe-a-cursor-128x42-onscreen.html
* igt@kms_cursor_crc@pipe-c-cursor-256x85-random:
- shard-skl: [PASS][52] -> [FAIL][53] ([i915#54]) +1 similar issue
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-skl8/igt@kms_cursor_crc@pipe-c-cursor-256x85-random.html
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-skl8/igt@kms_cursor_crc@pipe-c-cursor-256x85-random.html
* igt@kms_cursor_crc@pipe-d-cursor-suspend:
- shard-tglb: [PASS][54] -> [INCOMPLETE][55] ([i915#460]) +1 similar issue
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-tglb9/igt@kms_cursor_crc@pipe-d-cursor-suspend.html
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-tglb4/igt@kms_cursor_crc@pipe-d-cursor-suspend.html
* igt@kms_draw_crc@draw-method-rgb565-render-xtiled:
- shard-kbl: [PASS][56] -> [DMESG-WARN][57] ([i915#728]) +4 similar issues
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-kbl3/igt@kms_draw_crc@draw-method-rgb565-render-xtiled.html
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-kbl1/igt@kms_draw_crc@draw-method-rgb565-render-xtiled.html
* igt@kms_draw_crc@draw-method-xrgb2101010-render-xtiled:
- shard-skl: [PASS][58] -> [DMESG-WARN][59] ([i915#728]) +4 similar issues
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-skl3/igt@kms_draw_crc@draw-method-xrgb2101010-render-xtiled.html
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-skl7/igt@kms_draw_crc@draw-method-xrgb2101010-render-xtiled.html
* igt@kms_fbcon_fbt@fbc-suspend:
- shard-tglb: [PASS][60] -> [INCOMPLETE][61] ([i915#435] / [i915#456] / [i915#460])
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-tglb7/igt@kms_fbcon_fbt@fbc-suspend.html
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-tglb5/igt@kms_fbcon_fbt@fbc-suspend.html
* igt@kms_flip@flip-vs-suspend:
- shard-skl: [PASS][62] -> [INCOMPLETE][63] ([i915#221])
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-skl5/igt@kms_flip@flip-vs-suspend.html
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-skl5/igt@kms_flip@flip-vs-suspend.html
* igt@kms_flip@flip-vs-suspend-interruptible:
- shard-tglb: [PASS][64] -> [INCOMPLETE][65] ([i915#456] / [i915#460] / [i915#516])
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-tglb9/igt@kms_flip@flip-vs-suspend-interruptible.html
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-tglb8/igt@kms_flip@flip-vs-suspend-interruptible.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-indfb-draw-mmap-gtt:
- shard-tglb: [PASS][66] -> [INCOMPLETE][67] ([i915#474])
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-tglb7/igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-indfb-draw-mmap-gtt.html
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-tglb1/igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-indfb-draw-mmap-gtt.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-blt:
- shard-iclb: [PASS][68] -> [FAIL][69] ([i915#49]) +1 similar issue
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-iclb3/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-blt.html
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-iclb2/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-blt.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-pwrite:
- shard-tglb: [PASS][70] -> [FAIL][71] ([i915#49])
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-tglb7/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-pwrite.html
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-tglb5/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-pwrite.html
* igt@kms_frontbuffer_tracking@fbcpsr-suspend:
- shard-tglb: [PASS][72] -> [INCOMPLETE][73] ([i915#456] / [i915#460] / [i915#474])
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-tglb6/igt@kms_frontbuffer_tracking@fbcpsr-suspend.html
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-tglb2/igt@kms_frontbuffer_tracking@fbcpsr-suspend.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-mmap-cpu:
- shard-tglb: [PASS][74] -> [DMESG-WARN][75] ([i915#728]) +3 similar issues
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-tglb7/igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-mmap-cpu.html
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-tglb7/igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-mmap-cpu.html
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
- shard-tglb: [PASS][76] -> [INCOMPLETE][77] ([i915#456] / [i915#460])
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-tglb9/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b.html
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-tglb2/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b.html
* igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
- shard-skl: [PASS][78] -> [FAIL][79] ([fdo#108145] / [i915#265])
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-skl4/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-skl4/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
* igt@kms_psr@psr2_cursor_render:
- shard-iclb: [PASS][80] -> [SKIP][81] ([fdo#109441])
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-iclb2/igt@kms_psr@psr2_cursor_render.html
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-iclb6/igt@kms_psr@psr2_cursor_render.html
* igt@perf@disabled-read-error:
- shard-iclb: [PASS][82] -> [DMESG-WARN][83] ([i915#645])
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-iclb4/igt@perf@disabled-read-error.html
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-iclb2/igt@perf@disabled-read-error.html
* igt@perf_pmu@busy-check-all-rcs0:
- shard-iclb: [PASS][84] -> [DMESG-WARN][85] ([i915#728]) +6 similar issues
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-iclb4/igt@perf_pmu@busy-check-all-rcs0.html
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-iclb4/igt@perf_pmu@busy-check-all-rcs0.html
#### Possible fixes ####
* igt@gem_busy@busy-vcs1:
- shard-iclb: [SKIP][86] ([fdo#112080]) -> [PASS][87] +5 similar issues
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-iclb3/igt@gem_busy@busy-vcs1.html
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-iclb2/igt@gem_busy@busy-vcs1.html
* igt@gem_ctx_persistence@vcs1-mixed:
- shard-iclb: [SKIP][88] ([fdo#109276] / [fdo#112080]) -> [PASS][89] +1 similar issue
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-iclb6/igt@gem_ctx_persistence@vcs1-mixed.html
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-iclb1/igt@gem_ctx_persistence@vcs1-mixed.html
* igt@gem_exec_balancer@hang:
- shard-kbl: [DMESG-WARN][90] -> [PASS][91] +1 similar issue
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-kbl1/igt@gem_exec_balancer@hang.html
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-kbl3/igt@gem_exec_balancer@hang.html
* igt@gem_exec_create@forked:
- shard-tglb: [INCOMPLETE][92] ([fdo#108838] / [i915#435]) -> [PASS][93]
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-tglb4/igt@gem_exec_create@forked.html
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-tglb9/igt@gem_exec_create@forked.html
* igt@gem_exec_nop@basic-sequential:
- shard-tglb: [INCOMPLETE][94] ([i915#435]) -> [PASS][95]
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-tglb6/igt@gem_exec_nop@basic-sequential.html
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-tglb3/igt@gem_exec_nop@basic-sequential.html
* igt@gem_exec_parallel@vecs0-fds:
- shard-hsw: [FAIL][96] ([i915#676]) -> [PASS][97] +2 similar issues
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-hsw1/igt@gem_exec_parallel@vecs0-fds.html
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-hsw7/igt@gem_exec_parallel@vecs0-fds.html
* igt@gem_exec_schedule@preempt-queue-contexts-bsd2:
- shard-tglb: [INCOMPLETE][98] ([fdo#111606] / [fdo#111677]) -> [PASS][99]
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-tglb6/igt@gem_exec_schedule@preempt-queue-contexts-bsd2.html
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-tglb8/igt@gem_exec_schedule@preempt-queue-contexts-bsd2.html
* igt@gem_persistent_relocs@forked-interruptible-faulting-reloc-thrash-inactive:
- shard-hsw: [TIMEOUT][100] ([i915#530]) -> [PASS][101]
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-hsw5/igt@gem_persistent_relocs@forked-interruptible-faulting-reloc-thrash-inactive.html
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-hsw2/igt@gem_persistent_relocs@forked-interruptible-faulting-reloc-thrash-inactive.html
* igt@gem_ppgtt@flink-and-close-vma-leak:
- shard-iclb: [FAIL][102] ([i915#644]) -> [PASS][103]
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-iclb5/igt@gem_ppgtt@flink-and-close-vma-leak.html
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-iclb7/igt@gem_ppgtt@flink-and-close-vma-leak.html
* igt@gem_userptr_blits@sync-unmap:
- shard-snb: [DMESG-WARN][104] ([fdo#111870]) -> [PASS][105]
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-snb6/igt@gem_userptr_blits@sync-unmap.html
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-snb5/igt@gem_userptr_blits@sync-unmap.html
* igt@i915_pm_backlight@fade_with_suspend:
- shard-tglb: [INCOMPLETE][106] ([i915#456] / [i915#460]) -> [PASS][107]
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-tglb1/igt@i915_pm_backlight@fade_with_suspend.html
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-tglb6/igt@i915_pm_backlight@fade_with_suspend.html
* igt@i915_pm_dc@dc6-dpms:
- shard-iclb: [FAIL][108] ([i915#454]) -> [PASS][109]
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-iclb3/igt@i915_pm_dc@dc6-dpms.html
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-iclb1/igt@i915_pm_dc@dc6-dpms.html
* igt@kms_big_fb@yf-tiled-16bpp-rotate-0:
- shard-kbl: [INCOMPLETE][110] ([fdo#103665]) -> [PASS][111] +1 similar issue
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-kbl6/igt@kms_big_fb@yf-tiled-16bpp-rotate-0.html
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-kbl3/igt@kms_big_fb@yf-tiled-16bpp-rotate-0.html
* igt@kms_cursor_crc@pipe-a-cursor-suspend:
- shard-kbl: [DMESG-WARN][112] ([i915#180]) -> [PASS][113] +3 similar issues
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-kbl4/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-kbl2/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
* igt@kms_cursor_crc@pipe-b-cursor-64x21-onscreen:
- shard-kbl: [DMESG-WARN][114] ([IGT#6]) -> [PASS][115]
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-kbl3/igt@kms_cursor_crc@pipe-b-cursor-64x21-onscreen.html
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-kbl3/igt@kms_cursor_crc@pipe-b-cursor-64x21-onscreen.html
* igt@kms_cursor_crc@pipe-b-cursor-64x21-sliding:
- shard-skl: [FAIL][116] ([i915#54]) -> [PASS][117] +1 similar issue
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-skl7/igt@kms_cursor_crc@pipe-b-cursor-64x21-sliding.html
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-skl5/igt@kms_cursor_crc@pipe-b-cursor-64x21-sliding.html
* igt@kms_draw_crc@draw-method-rgb565-mmap-wc-xtiled:
- shard-skl: [FAIL][118] ([i915#52] / [i915#54]) -> [PASS][119]
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-skl9/igt@kms_draw_crc@draw-method-rgb565-mmap-wc-xtiled.html
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-skl4/igt@kms_draw_crc@draw-method-rgb565-mmap-wc-xtiled.html
* igt@kms_flip@2x-flip-vs-expired-vblank-interruptible:
- shard-glk: [FAIL][120] ([i915#79]) -> [PASS][121]
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-glk7/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible.html
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-glk9/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible:
- shard-skl: [FAIL][122] ([i915#79]) -> [PASS][123]
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-skl5/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-skl4/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
* igt@kms_flip@flip-vs-suspend-interruptible:
- shard-skl: [INCOMPLETE][124] ([i915#221]) -> [PASS][125]
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-skl7/igt@kms_flip@flip-vs-suspend-interruptible.html
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-skl7/igt@kms_flip@flip-vs-suspend-interruptible.html
* igt@kms_flip_tiling@flip-x-tiled:
- shard-tglb: [FAIL][126] ([i915#699]) -> [PASS][127]
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-tglb5/igt@kms_flip_tiling@flip-x-tiled.html
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-tglb3/igt@kms_flip_tiling@flip-x-tiled.html
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-render:
- shard-iclb: [FAIL][128] ([i915#49]) -> [PASS][129] +3 similar issues
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-iclb6/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-render.html
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-iclb6/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-render.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-blt:
- shard-tglb: [FAIL][130] ([i915#49]) -> [PASS][131] +2 similar issues
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-tglb6/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-blt.html
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-tglb8/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-blt.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-indfb-msflip-blt:
- shard-skl: [DMESG-WARN][132] ([i915#728]) -> [PASS][133] +5 similar issues
[132]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-skl1/igt@kms_frontbuffer_tracking@psr-1p-primscrn-indfb-msflip-blt.html
[133]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-skl5/igt@kms_frontbuffer_tracking@psr-1p-primscrn-indfb-msflip-blt.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-indfb-plflip-blt:
- shard-skl: [INCOMPLETE][134] ([i915#123]) -> [PASS][135]
[134]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-skl10/igt@kms_frontbuffer_tracking@psr-1p-primscrn-indfb-plflip-blt.html
[135]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-skl5/igt@kms_frontbuffer_tracking@psr-1p-primscrn-indfb-plflip-blt.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-render:
- shard-tglb: [DMESG-WARN][136] ([i915#728]) -> [PASS][137] +2 similar issues
[136]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-tglb6/igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-render.html
[137]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-tglb3/igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-render.html
* igt@kms_frontbuffer_tracking@psr-1p-rte:
- shard-iclb: [DMESG-WARN][138] ([i915#728]) -> [PASS][139] +3 similar issues
[138]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-iclb6/igt@kms_frontbuffer_tracking@psr-1p-rte.html
[139]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-iclb1/igt@kms_frontbuffer_tracking@psr-1p-rte.html
* igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes:
- shard-apl: [DMESG-WARN][140] ([i915#180]) -> [PASS][141] +1 similar issue
[140]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-apl6/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html
[141]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-apl4/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html
* igt@kms_psr@psr2_sprite_mmap_cpu:
- shard-iclb: [SKIP][142] ([fdo#109441]) -> [PASS][143]
[142]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-iclb4/igt@kms_psr@psr2_sprite_mmap_cpu.html
[143]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-iclb2/igt@kms_psr@psr2_sprite_mmap_cpu.html
* igt@kms_psr@psr2_suspend:
- shard-tglb: [DMESG-WARN][144] ([i915#402]) -> [PASS][145]
[144]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-tglb6/igt@kms_psr@psr2_suspend.html
[145]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-tglb8/igt@kms_psr@psr2_suspend.html
* igt@kms_setmode@basic:
- shard-kbl: [FAIL][146] ([i915#31]) -> [PASS][147]
[146]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-kbl2/igt@kms_setmode@basic.html
[147]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-kbl3/igt@kms_setmode@basic.html
* igt@kms_vblank@pipe-c-ts-continuation-dpms-suspend:
- shard-tglb: [INCOMPLETE][148] ([i915#460]) -> [PASS][149]
[148]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-tglb4/igt@kms_vblank@pipe-c-ts-continuation-dpms-suspend.html
[149]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-tglb4/igt@kms_vblank@pipe-c-ts-continuation-dpms-suspend.html
* igt@perf@oa-exponents:
- shard-hsw: [FAIL][150] ([i915#84]) -> [PASS][151]
[150]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-hsw4/igt@perf@oa-exponents.html
[151]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-hsw5/igt@perf@oa-exponents.html
* igt@prime_vgem@fence-wait-bsd2:
- shard-iclb: [SKIP][152] ([fdo#109276]) -> [PASS][153] +10 similar issues
[152]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-iclb3/igt@prime_vgem@fence-wait-bsd2.html
[153]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-iclb1/igt@prime_vgem@fence-wait-bsd2.html
#### Warnings ####
* igt@gem_ctx_isolation@vcs1-nonpriv:
- shard-iclb: [FAIL][154] ([IGT#28]) -> [SKIP][155] ([fdo#109276] / [fdo#112080])
[154]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-iclb2/igt@gem_ctx_isolation@vcs1-nonpriv.html
[155]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-iclb6/igt@gem_ctx_isolation@vcs1-nonpriv.html
* igt@kms_flip@flip-vs-suspend:
- shard-kbl: [INCOMPLETE][156] ([fdo#103665] / [i915#600]) -> [DMESG-WARN][157] ([i915#180])
[156]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-kbl7/igt@kms_fl
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for Enable second DBuf slice for ICL and TGL (rev5)
2019-12-09 7:55 ` Lisovskiy, Stanislav
@ 2019-12-09 8:11 ` Vudum, Lakshminarayana
2019-12-09 8:40 ` Lisovskiy, Stanislav
0 siblings, 1 reply; 26+ messages in thread
From: Vudum, Lakshminarayana @ 2019-12-09 8:11 UTC (permalink / raw)
To: Lisovskiy, Stanislav, intel-gfx
Stan,
I don't think retest is needed if the failure is not caused by your change. Please send the patch series to me, I will address those failures.
I will soon address the below failures and re-report the results.
Lakshmi.
-----Original Message-----
From: Lisovskiy, Stanislav <stanislav.lisovskiy@intel.com>
Sent: Monday, December 9, 2019 9:55 AM
To: intel-gfx@lists.freedesktop.org
Cc: Vudum, Lakshminarayana <lakshminarayana.vudum@intel.com>
Subject: RE: ✗ Fi.CI.IGT: failure for Enable second DBuf slice for ICL and TGL (rev5)
Getting already a bit pissed off with need on hitting retest button as those failures have nothing in common with DBuf changes. It's again gem-gem-gem...
Best Regards,
Lisovskiy Stanislav
Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo
________________________________________
From: Patchwork [patchwork@emeril.freedesktop.org]
Sent: Thursday, December 05, 2019 8:40 PM
To: Lisovskiy, Stanislav
Cc: intel-gfx@lists.freedesktop.org
Subject: ✗ Fi.CI.IGT: failure for Enable second DBuf slice for ICL and TGL (rev5)
== Series Details ==
Series: Enable second DBuf slice for ICL and TGL (rev5)
URL : https://patchwork.freedesktop.org/series/70059/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7489_full -> Patchwork_15602_full ====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_15602_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_15602_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_15602_full:
### IGT changes ###
#### Possible regressions ####
* igt@gem_exec_balancer@bonded-cork:
- shard-iclb: [PASS][1] -> [DMESG-WARN][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-iclb4/igt@gem_exec_balancer@bonded-cork.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-iclb4/igt@gem_exec_balancer@bonded-cork.html
* igt@gem_exec_parse_blt@allowed-all:
- shard-skl: [PASS][3] -> [DMESG-WARN][4]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-skl8/igt@gem_exec_parse_blt@allowed-all.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-skl9/igt@gem_exec_parse_blt@allowed-all.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-indfb-pgflip-blt:
- shard-skl: NOTRUN -> [DMESG-WARN][5]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-skl7/igt@kms_frontbuffer_tracking@psr-1p-primscrn-indfb-pgflip-blt.html
* igt@perf_pmu@busy-idle-bcs0:
- shard-kbl: [PASS][6] -> [DMESG-WARN][7] +2 similar issues
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-kbl1/igt@perf_pmu@busy-idle-bcs0.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-kbl4/igt@perf_pmu@busy-idle-bcs0.html
Known issues
------------
Here are the changes found in Patchwork_15602_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_busy@extended-parallel-vcs1:
- shard-iclb: [PASS][8] -> [SKIP][9] ([fdo#112080]) +6 similar issues
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-iclb1/igt@gem_busy@extended-parallel-vcs1.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-iclb3/igt@gem_busy@extended-parallel-vcs1.html
* igt@gem_ctx_isolation@bcs0-s3:
- shard-apl: [PASS][10] -> [DMESG-WARN][11] ([i915#180]) +1 similar issue
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-apl3/igt@gem_ctx_isolation@bcs0-s3.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-apl6/igt@gem_ctx_isolation@bcs0-s3.html
* igt@gem_ctx_isolation@rcs0-s3:
- shard-kbl: [PASS][12] -> [DMESG-WARN][13] ([i915#180]) +6 similar issues
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-kbl1/igt@gem_ctx_isolation@rcs0-s3.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-kbl3/igt@gem_ctx_isolation@rcs0-s3.html
* igt@gem_ctx_persistence@vcs1-queued:
- shard-iclb: [PASS][14] -> [SKIP][15] ([fdo#109276] / [fdo#112080]) +1 similar issue
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-iclb2/igt@gem_ctx_persistence@vcs1-queued.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-iclb6/igt@gem_ctx_persistence@vcs1-queued.html
* igt@gem_eio@kms:
- shard-snb: [PASS][16] -> [INCOMPLETE][17] ([i915#82])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-snb1/igt@gem_eio@kms.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-snb6/igt@gem_eio@kms.html
* igt@gem_exec_balancer@smoke:
- shard-iclb: [PASS][18] -> [SKIP][19] ([fdo#110854])
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-iclb2/igt@gem_exec_balancer@smoke.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-iclb6/igt@gem_exec_balancer@smoke.html
* igt@gem_exec_schedule@fifo-bsd1:
- shard-iclb: [PASS][20] -> [SKIP][21] ([fdo#109276]) +4 similar issues
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-iclb1/igt@gem_exec_schedule@fifo-bsd1.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-iclb3/igt@gem_exec_schedule@fifo-bsd1.html
* igt@gem_exec_schedule@preempt-hang-bsd:
- shard-iclb: [PASS][22] -> [SKIP][23] ([fdo#112146]) +1 similar issue
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-iclb6/igt@gem_exec_schedule@preempt-hang-bsd.html
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-iclb1/igt@gem_exec_schedule@preempt-hang-bsd.html
* igt@gem_exec_schedule@preempt-queue-chain-bsd2:
- shard-tglb: [PASS][24] -> [INCOMPLETE][25] ([fdo#111677])
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-tglb5/igt@gem_exec_schedule@preempt-queue-chain-bsd2.html
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-tglb6/igt@gem_exec_schedule@preempt-queue-chain-bsd2.html
* igt@gem_exec_schedule@preempt-queue-chain-render:
- shard-tglb: [PASS][26] -> [INCOMPLETE][27] ([fdo#111606] / [fdo#111677])
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-tglb1/igt@gem_exec_schedule@preempt-queue-chain-render.html
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-tglb6/igt@gem_exec_schedule@preempt-queue-chain-render.html
* igt@gem_persistent_relocs@forked-interruptible-thrashing:
- shard-kbl: [PASS][28] -> [FAIL][29] ([i915#520])
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-kbl1/igt@gem_persistent_relocs@forked-interruptible-thrashing.html
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-kbl2/igt@gem_persistent_relocs@forked-interruptible-thrashing.html
* igt@gem_persistent_relocs@forked-thrashing:
- shard-iclb: [PASS][30] -> [TIMEOUT][31] ([i915#530])
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-iclb4/igt@gem_persistent_relocs@forked-thrashing.html
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-iclb4/igt@gem_persistent_relocs@forked-thrashing.html
* igt@gem_ppgtt@flink-and-close-vma-leak:
- shard-skl: [PASS][32] -> [FAIL][33] ([i915#644])
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-skl3/igt@gem_ppgtt@flink-and-close-vma-leak.html
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-skl8/igt@gem_ppgtt@flink-and-close-vma-leak.html
* igt@gem_userptr_blits@map-fixed-invalidate-busy-gup:
- shard-snb: [PASS][34] -> [DMESG-WARN][35] ([fdo#111870])
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-snb6/igt@gem_userptr_blits@map-fixed-invalidate-busy-gup.html
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-snb2/igt@gem_userptr_blits@map-fixed-invalidate-busy-gup.html
* igt@gem_workarounds@suspend-resume-fd:
- shard-skl: [PASS][36] -> [INCOMPLETE][37] ([i915#69]) +1 similar issue
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-skl3/igt@gem_workarounds@suspend-resume-fd.html
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-skl8/igt@gem_workarounds@suspend-resume-fd.html
* igt@i915_pm_rpm@system-suspend-execbuf:
- shard-skl: [PASS][38] -> [INCOMPLETE][39] ([i915#151] / [i915#69]) +1 similar issue
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-skl9/igt@i915_pm_rpm@system-suspend-execbuf.html
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-skl2/igt@i915_pm_rpm@system-suspend-execbuf.html
* igt@i915_selftest@live_blt:
- shard-hsw: [PASS][40] -> [DMESG-FAIL][41] ([i915#683])
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-hsw4/igt@i915_selftest@live_blt.html
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-hsw6/igt@i915_selftest@live_blt.html
* igt@kms_big_fb@y-tiled-16bpp-rotate-0:
- shard-kbl: [PASS][42] -> [INCOMPLETE][43] ([fdo#103665] / [fdo#112413])
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-kbl4/igt@kms_big_fb@y-tiled-16bpp-rotate-0.html
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-kbl4/igt@kms_big_fb@y-tiled-16bpp-rotate-0.html
* igt@kms_big_fb@y-tiled-16bpp-rotate-180:
- shard-tglb: [PASS][44] -> [INCOMPLETE][45] ([i915#667])
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-tglb8/igt@kms_big_fb@y-tiled-16bpp-rotate-180.html
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-tglb7/igt@kms_big_fb@y-tiled-16bpp-rotate-180.html
* igt@kms_big_fb@y-tiled-8bpp-rotate-180:
- shard-skl: [PASS][46] -> [INCOMPLETE][47] ([fdo#112347])
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-skl1/igt@kms_big_fb@y-tiled-8bpp-rotate-180.html
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-skl8/igt@kms_big_fb@y-tiled-8bpp-rotate-180.html
* igt@kms_ccs@pipe-a-crc-primary-basic:
- shard-skl: [PASS][48] -> [INCOMPLETE][49] ([i915#667])
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-skl9/igt@kms_ccs@pipe-a-crc-primary-basic.html
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-skl6/igt@kms_ccs@pipe-a-crc-primary-basic.html
* igt@kms_cursor_crc@pipe-a-cursor-128x42-onscreen:
- shard-hsw: [PASS][50] -> [DMESG-WARN][51] ([IGT#6])
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-hsw5/igt@kms_cursor_crc@pipe-a-cursor-128x42-onscreen.html
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-hsw6/igt@kms_cursor_crc@pipe-a-cursor-128x42-onscreen.html
* igt@kms_cursor_crc@pipe-c-cursor-256x85-random:
- shard-skl: [PASS][52] -> [FAIL][53] ([i915#54]) +1 similar issue
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-skl8/igt@kms_cursor_crc@pipe-c-cursor-256x85-random.html
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-skl8/igt@kms_cursor_crc@pipe-c-cursor-256x85-random.html
* igt@kms_cursor_crc@pipe-d-cursor-suspend:
- shard-tglb: [PASS][54] -> [INCOMPLETE][55] ([i915#460]) +1 similar issue
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-tglb9/igt@kms_cursor_crc@pipe-d-cursor-suspend.html
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-tglb4/igt@kms_cursor_crc@pipe-d-cursor-suspend.html
* igt@kms_draw_crc@draw-method-rgb565-render-xtiled:
- shard-kbl: [PASS][56] -> [DMESG-WARN][57] ([i915#728]) +4 similar issues
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-kbl3/igt@kms_draw_crc@draw-method-rgb565-render-xtiled.html
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-kbl1/igt@kms_draw_crc@draw-method-rgb565-render-xtiled.html
* igt@kms_draw_crc@draw-method-xrgb2101010-render-xtiled:
- shard-skl: [PASS][58] -> [DMESG-WARN][59] ([i915#728]) +4 similar issues
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-skl3/igt@kms_draw_crc@draw-method-xrgb2101010-render-xtiled.html
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-skl7/igt@kms_draw_crc@draw-method-xrgb2101010-render-xtiled.html
* igt@kms_fbcon_fbt@fbc-suspend:
- shard-tglb: [PASS][60] -> [INCOMPLETE][61] ([i915#435] / [i915#456] / [i915#460])
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-tglb7/igt@kms_fbcon_fbt@fbc-suspend.html
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-tglb5/igt@kms_fbcon_fbt@fbc-suspend.html
* igt@kms_flip@flip-vs-suspend:
- shard-skl: [PASS][62] -> [INCOMPLETE][63] ([i915#221])
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-skl5/igt@kms_flip@flip-vs-suspend.html
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-skl5/igt@kms_flip@flip-vs-suspend.html
* igt@kms_flip@flip-vs-suspend-interruptible:
- shard-tglb: [PASS][64] -> [INCOMPLETE][65] ([i915#456] / [i915#460] / [i915#516])
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-tglb9/igt@kms_flip@flip-vs-suspend-interruptible.html
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-tglb8/igt@kms_flip@flip-vs-suspend-interruptible.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-indfb-draw-mmap-gtt:
- shard-tglb: [PASS][66] -> [INCOMPLETE][67] ([i915#474])
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-tglb7/igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-indfb-draw-mmap-gtt.html
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-tglb1/igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-indfb-draw-mmap-gtt.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-blt:
- shard-iclb: [PASS][68] -> [FAIL][69] ([i915#49]) +1 similar issue
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-iclb3/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-blt.html
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-iclb2/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-blt.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-pwrite:
- shard-tglb: [PASS][70] -> [FAIL][71] ([i915#49])
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-tglb7/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-pwrite.html
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-tglb5/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-pwrite.html
* igt@kms_frontbuffer_tracking@fbcpsr-suspend:
- shard-tglb: [PASS][72] -> [INCOMPLETE][73] ([i915#456] / [i915#460] / [i915#474])
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-tglb6/igt@kms_frontbuffer_tracking@fbcpsr-suspend.html
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-tglb2/igt@kms_frontbuffer_tracking@fbcpsr-suspend.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-mmap-cpu:
- shard-tglb: [PASS][74] -> [DMESG-WARN][75] ([i915#728]) +3 similar issues
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-tglb7/igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-mmap-cpu.html
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-tglb7/igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-mmap-cpu.html
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
- shard-tglb: [PASS][76] -> [INCOMPLETE][77] ([i915#456] / [i915#460])
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-tglb9/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b.html
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-tglb2/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b.html
* igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
- shard-skl: [PASS][78] -> [FAIL][79] ([fdo#108145] / [i915#265])
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-skl4/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-skl4/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
* igt@kms_psr@psr2_cursor_render:
- shard-iclb: [PASS][80] -> [SKIP][81] ([fdo#109441])
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-iclb2/igt@kms_psr@psr2_cursor_render.html
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-iclb6/igt@kms_psr@psr2_cursor_render.html
* igt@perf@disabled-read-error:
- shard-iclb: [PASS][82] -> [DMESG-WARN][83] ([i915#645])
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-iclb4/igt@perf@disabled-read-error.html
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-iclb2/igt@perf@disabled-read-error.html
* igt@perf_pmu@busy-check-all-rcs0:
- shard-iclb: [PASS][84] -> [DMESG-WARN][85] ([i915#728]) +6 similar issues
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-iclb4/igt@perf_pmu@busy-check-all-rcs0.html
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-iclb4/igt@perf_pmu@busy-check-all-rcs0.html
#### Possible fixes ####
* igt@gem_busy@busy-vcs1:
- shard-iclb: [SKIP][86] ([fdo#112080]) -> [PASS][87] +5 similar issues
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-iclb3/igt@gem_busy@busy-vcs1.html
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-iclb2/igt@gem_busy@busy-vcs1.html
* igt@gem_ctx_persistence@vcs1-mixed:
- shard-iclb: [SKIP][88] ([fdo#109276] / [fdo#112080]) -> [PASS][89] +1 similar issue
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-iclb6/igt@gem_ctx_persistence@vcs1-mixed.html
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-iclb1/igt@gem_ctx_persistence@vcs1-mixed.html
* igt@gem_exec_balancer@hang:
- shard-kbl: [DMESG-WARN][90] -> [PASS][91] +1 similar issue
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-kbl1/igt@gem_exec_balancer@hang.html
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-kbl3/igt@gem_exec_balancer@hang.html
* igt@gem_exec_create@forked:
- shard-tglb: [INCOMPLETE][92] ([fdo#108838] / [i915#435]) -> [PASS][93]
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-tglb4/igt@gem_exec_create@forked.html
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-tglb9/igt@gem_exec_create@forked.html
* igt@gem_exec_nop@basic-sequential:
- shard-tglb: [INCOMPLETE][94] ([i915#435]) -> [PASS][95]
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-tglb6/igt@gem_exec_nop@basic-sequential.html
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-tglb3/igt@gem_exec_nop@basic-sequential.html
* igt@gem_exec_parallel@vecs0-fds:
- shard-hsw: [FAIL][96] ([i915#676]) -> [PASS][97] +2 similar issues
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-hsw1/igt@gem_exec_parallel@vecs0-fds.html
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-hsw7/igt@gem_exec_parallel@vecs0-fds.html
* igt@gem_exec_schedule@preempt-queue-contexts-bsd2:
- shard-tglb: [INCOMPLETE][98] ([fdo#111606] / [fdo#111677]) -> [PASS][99]
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-tglb6/igt@gem_exec_schedule@preempt-queue-contexts-bsd2.html
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-tglb8/igt@gem_exec_schedule@preempt-queue-contexts-bsd2.html
* igt@gem_persistent_relocs@forked-interruptible-faulting-reloc-thrash-inactive:
- shard-hsw: [TIMEOUT][100] ([i915#530]) -> [PASS][101]
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-hsw5/igt@gem_persistent_relocs@forked-interruptible-faulting-reloc-thrash-inactive.html
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-hsw2/igt@gem_persistent_relocs@forked-interruptible-faulting-reloc-thrash-inactive.html
* igt@gem_ppgtt@flink-and-close-vma-leak:
- shard-iclb: [FAIL][102] ([i915#644]) -> [PASS][103]
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-iclb5/igt@gem_ppgtt@flink-and-close-vma-leak.html
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-iclb7/igt@gem_ppgtt@flink-and-close-vma-leak.html
* igt@gem_userptr_blits@sync-unmap:
- shard-snb: [DMESG-WARN][104] ([fdo#111870]) -> [PASS][105]
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-snb6/igt@gem_userptr_blits@sync-unmap.html
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-snb5/igt@gem_userptr_blits@sync-unmap.html
* igt@i915_pm_backlight@fade_with_suspend:
- shard-tglb: [INCOMPLETE][106] ([i915#456] / [i915#460]) -> [PASS][107]
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-tglb1/igt@i915_pm_backlight@fade_with_suspend.html
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-tglb6/igt@i915_pm_backlight@fade_with_suspend.html
* igt@i915_pm_dc@dc6-dpms:
- shard-iclb: [FAIL][108] ([i915#454]) -> [PASS][109]
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-iclb3/igt@i915_pm_dc@dc6-dpms.html
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-iclb1/igt@i915_pm_dc@dc6-dpms.html
* igt@kms_big_fb@yf-tiled-16bpp-rotate-0:
- shard-kbl: [INCOMPLETE][110] ([fdo#103665]) -> [PASS][111] +1 similar issue
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-kbl6/igt@kms_big_fb@yf-tiled-16bpp-rotate-0.html
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-kbl3/igt@kms_big_fb@yf-tiled-16bpp-rotate-0.html
* igt@kms_cursor_crc@pipe-a-cursor-suspend:
- shard-kbl: [DMESG-WARN][112] ([i915#180]) -> [PASS][113] +3 similar issues
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-kbl4/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-kbl2/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
* igt@kms_cursor_crc@pipe-b-cursor-64x21-onscreen:
- shard-kbl: [DMESG-WARN][114] ([IGT#6]) -> [PASS][115]
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-kbl3/igt@kms_cursor_crc@pipe-b-cursor-64x21-onscreen.html
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-kbl3/igt@kms_cursor_crc@pipe-b-cursor-64x21-onscreen.html
* igt@kms_cursor_crc@pipe-b-cursor-64x21-sliding:
- shard-skl: [FAIL][116] ([i915#54]) -> [PASS][117] +1 similar issue
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-skl7/igt@kms_cursor_crc@pipe-b-cursor-64x21-sliding.html
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-skl5/igt@kms_cursor_crc@pipe-b-cursor-64x21-sliding.html
* igt@kms_draw_crc@draw-method-rgb565-mmap-wc-xtiled:
- shard-skl: [FAIL][118] ([i915#52] / [i915#54]) -> [PASS][119]
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-skl9/igt@kms_draw_crc@draw-method-rgb565-mmap-wc-xtiled.html
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-skl4/igt@kms_draw_crc@draw-method-rgb565-mmap-wc-xtiled.html
* igt@kms_flip@2x-flip-vs-expired-vblank-interruptible:
- shard-glk: [FAIL][120] ([i915#79]) -> [PASS][121]
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-glk7/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible.html
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-glk9/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible:
- shard-skl: [FAIL][122] ([i915#79]) -> [PASS][123]
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-skl5/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-skl4/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
* igt@kms_flip@flip-vs-suspend-interruptible:
- shard-skl: [INCOMPLETE][124] ([i915#221]) -> [PASS][125]
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-skl7/igt@kms_flip@flip-vs-suspend-interruptible.html
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-skl7/igt@kms_flip@flip-vs-suspend-interruptible.html
* igt@kms_flip_tiling@flip-x-tiled:
- shard-tglb: [FAIL][126] ([i915#699]) -> [PASS][127]
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-tglb5/igt@kms_flip_tiling@flip-x-tiled.html
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-tglb3/igt@kms_flip_tiling@flip-x-tiled.html
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-render:
- shard-iclb: [FAIL][128] ([i915#49]) -> [PASS][129] +3 similar issues
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-iclb6/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-render.html
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-iclb6/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-render.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-blt:
- shard-tglb: [FAIL][130] ([i915#49]) -> [PASS][131] +2 similar issues
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-tglb6/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-blt.html
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-tglb8/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-blt.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-indfb-msflip-blt:
- shard-skl: [DMESG-WARN][132] ([i915#728]) -> [PASS][133] +5 similar issues
[132]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-skl1/igt@kms_frontbuffer_tracking@psr-1p-primscrn-indfb-msflip-blt.html
[133]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-skl5/igt@kms_frontbuffer_tracking@psr-1p-primscrn-indfb-msflip-blt.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-indfb-plflip-blt:
- shard-skl: [INCOMPLETE][134] ([i915#123]) -> [PASS][135]
[134]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-skl10/igt@kms_frontbuffer_tracking@psr-1p-primscrn-indfb-plflip-blt.html
[135]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-skl5/igt@kms_frontbuffer_tracking@psr-1p-primscrn-indfb-plflip-blt.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-render:
- shard-tglb: [DMESG-WARN][136] ([i915#728]) -> [PASS][137] +2 similar issues
[136]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-tglb6/igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-render.html
[137]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-tglb3/igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-render.html
* igt@kms_frontbuffer_tracking@psr-1p-rte:
- shard-iclb: [DMESG-WARN][138] ([i915#728]) -> [PASS][139] +3 similar issues
[138]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-iclb6/igt@kms_frontbuffer_tracking@psr-1p-rte.html
[139]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-iclb1/igt@kms_frontbuffer_tracking@psr-1p-rte.html
* igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes:
- shard-apl: [DMESG-WARN][140] ([i915#180]) -> [PASS][141] +1 similar issue
[140]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-apl6/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html
[141]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-apl4/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html
* igt@kms_psr@psr2_sprite_mmap_cpu:
- shard-iclb: [SKIP][142] ([fdo#109441]) -> [PASS][143]
[142]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-iclb4/igt@kms_psr@psr2_sprite_mmap_cpu.html
[143]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-iclb2/igt@kms_psr@psr2_sprite_mmap_cpu.html
* igt@kms_psr@psr2_suspend:
- shard-tglb: [DMESG-WARN][144] ([i915#402]) -> [PASS][145]
[144]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-tglb6/igt@kms_psr@psr2_suspend.html
[145]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-tglb8/igt@kms_psr@psr2_suspend.html
* igt@kms_setmode@basic:
- shard-kbl: [FAIL][146] ([i915#31]) -> [PASS][147]
[146]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-kbl2/igt@kms_setmode@basic.html
[147]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-kbl3/igt@kms_setmode@basic.html
* igt@kms_vblank@pipe-c-ts-continuation-dpms-suspend:
- shard-tglb: [INCOMPLETE][148] ([i915#460]) -> [PASS][149]
[148]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-tglb4/igt@kms_vblank@pipe-c-ts-continuation-dpms-suspend.html
[149]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-tglb4/igt@kms_vblank@pipe-c-ts-continuation-dpms-suspend.html
* igt@perf@oa-exponents:
- shard-hsw: [FAIL][150] ([i915#84]) -> [PASS][151]
[150]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-hsw4/igt@perf@oa-exponents.html
[151]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-hsw5/igt@perf@oa-exponents.html
* igt@prime_vgem@fence-wait-bsd2:
- shard-iclb: [SKIP][152] ([fdo#109276]) -> [PASS][153] +10 similar issues
[152]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-iclb3/igt@prime_vgem@fence-wait-bsd2.html
[153]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-iclb1/igt@prime_vgem@fence-wait-bsd2.html
#### Warnings ####
* igt@gem_ctx_isolation@vcs1-nonpriv:
- shard-iclb: [FAIL][154] ([IGT#28]) -> [SKIP][155] ([fdo#109276] / [fdo#112080])
[154]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-iclb2/igt@gem_ctx_isolation@vcs1-nonpriv.html
[155]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-iclb6/igt@gem_ctx_isolation@vcs1-nonpriv.html
* igt@kms_flip@flip-vs-suspend:
- shard-kbl: [INCOMPLETE][156] ([fdo#103665] / [i915#600]) -> [DMESG-WARN][157] ([i915#180])
[156]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-kbl7/igt@kms_fl
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/index.html
---------------------------------------------------------------------
Intel Finland Oy
Registered Address: PL 281, 00181 Helsinki
Business Identity Code: 0357606 - 4
Domiciled in Helsinki
This e-mail and any attachments may contain confidential material for
the sole use of the intended recipient(s). Any review or distribution
by others is strictly prohibited. If you are not the intended
recipient, please contact the sender and delete all copies.
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for Enable second DBuf slice for ICL and TGL (rev5)
2019-12-09 8:11 ` Vudum, Lakshminarayana
@ 2019-12-09 8:40 ` Lisovskiy, Stanislav
0 siblings, 0 replies; 26+ messages in thread
From: Lisovskiy, Stanislav @ 2019-12-09 8:40 UTC (permalink / raw)
To: Vudum, Lakshminarayana, intel-gfx
Thank you very much, well the patch series is here: https://patchwork.freedesktop.org/series/70059/
The failures here were some gem related stuff:
WARNING: possible circular locking dependency detected
<4> [73.588465] 5.4.0-rc8-CI-Patchwork_15602+ #1 Tainted: G U
<4> [73.588467] ------------------------------------------------------
<4> [73.588469] gem_exec_balanc/1141 is trying to acquire lock:
<4> [73.588472] ffff88849db4bd58 (&mm->mmap_sem#2){++++}, at: __might_fault+0x39/0x90
...
some corruption which is clearly gem again:
<4> [116.956277] ------------[ cut here ]------------
<4> [116.956281] list_add corruption. prev->next should be next (ffffc90000de39e0), but was ffff88826610a440. (prev=ffff88825b83ba70).
<4> [116.956296] WARNING: CPU: 0 PID: 2312 at lib/list_debug.c:28 __list_add_valid+0x4d/0x70
<4> [116.956299] Modules linked in: vgem snd_hda_codec_hdmi snd_hda_codec_realtek snd_hda_codec_generic mei_hdcp i915 x86_pkg_temp_thermal coretemp snd_hda_intel snd_intel_dspcfg btusb btrtl crct10dif_pclmul btbcm snd_hda_codec btintel crc32_pclmul snd_hwdep snd_hda_core bluetooth ghash_clmulni_intel snd_pcm ecdh_generic e1000e ecc ptp mei_me pps_core mei prime_numbers
<4> [116.956317] CPU: 0 PID: 2312 Comm: kms_frontbuffer Tainted: G U 5.4.0-rc8-CI-Patchwork_15602+ #1
<4> [116.956319] Hardware name: /NUC7i5BNB, BIOS BNKBL357.86A.0054.2017.1025.1822 10/25/2017
<4> [116.956322] RIP: 0010:__list_add_valid+0x4d/0x70
<4> [116.956325] Code: c3 48 89 d1 48 c7 c7 d0 5a 0e 82 48 89 c2 e8 9a 10 bb ff 0f 0b 31 c0 c3 48 89 c1 4c 89 c6 48 c7 c7 20 5b 0e 82 e8 83 10 bb ff <0f> 0b 31 c0 c3 48 89 f2 4c 89 c1 48 89 fe 48 c7 c7 70 5b 0e 82 e8
<4> [116.956328] RSP: 0018:ffffc90000de39a0 EFLAGS: 00010286
<4> [116.956330] RAX: 0000000000000000 RBX: ffff88825b83ba70 RCX: 0000000000000002
<4> [116.956333] RDX: 0000000080000002 RSI: 0000000000000000 RDI: 00000000ffffffff
<4> [116.956335] RBP: ffffc90000de39e0 R08: 0000000000000000 R09: 0000000000000001
<4> [116.956337] R10: 0000000000000000 R11: ffffc90000de3840 R12: 0000000000000000
<4> [116.956339] R13: ffff88826610a408 R14: ffff88825b83ba70 R15: ffff8882561091d8
<4> [116.956341] FS: 00007fb9e4656e40(0000) GS:ffff888276a00000(0000) knlGS:0000000000000000
<4> [116.956344] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033
<4> [116.956346] CR2: 0000561cd664a9e8 CR3: 0000000263276002 CR4: 00000000003606f0
<4> [116.956348] Call Trace:
<4> [116.956436] i915_gem_object_unbind+0x17e/0x400 [i915]
<4> [116.956494] i915_gem_object_set_cache_level+0x32/0x90 [i915]
<4> [116.956546] i915_gem_object_pin_to_display_plane+0x5d/0x160 [i915]
<4> [116.956606] intel_pin_and_fence_fb_obj+0x9e/0x200 [i915]
<4> [116.956666] intel_plane_pin_fb+0x3f/0xd0 [i915]
<4> [116.956725] intel_prepare_plane_fb+0x130/0x520 [i915]
<4> [116.956732] drm_atomic_helper_prepare_planes+0x85/0x110
<4> [116.956790] intel_atomic_commit+0xc6/0x350 [i915]
<4> [116.956795] drm_atomic_helper_set_config+0x61/0x90
<4> [116.956798] drm_mode_setcrtc+0x18e/0x720
<4> [116.956806] ? drm_mode_getcrtc+0x180/0x180
<4> [116.956810] drm_ioctl_kernel+0xa7/0xf0
<4> [116.956814] drm_ioctl+0x2e1/0x390
<4> [116.956817] ? drm_mode_getcrtc+0x180/0x180
<4> [116.956824] do_vfs_ioctl+0xa0/0x6f0
<4> [116.956829] ? get_task_pid+0x150/0x150
<4> [116.956833] ksys_ioctl+0x35/0x60
<4> [116.956837] __x64_sys_ioctl+0x11/0x20
<4> [116.956840] do_syscall_64+0x4f/0x210
<4> [116.956843] entry_SYSCALL_64_after_hwframe+0x49/0xbe
<4> [116.956846] RIP: 0033:0x7fb9e36ac5d7
and DP related issue:
"<3> [1917.432109] [drm:lspcon_write_infoframe [i915]] *ERROR* DPCD read failed, address 0x5df"
All have nothing in common with changes I have here.
Best Regards,
Lisovskiy Stanislav
Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo
________________________________________
From: Vudum, Lakshminarayana
Sent: Monday, December 09, 2019 10:11 AM
To: Lisovskiy, Stanislav; intel-gfx@lists.freedesktop.org
Subject: RE: ✗ Fi.CI.IGT: failure for Enable second DBuf slice for ICL and TGL (rev5)
Stan,
I don't think retest is needed if the failure is not caused by your change. Please send the patch series to me, I will address those failures.
I will soon address the below failures and re-report the results.
Lakshmi.
-----Original Message-----
From: Lisovskiy, Stanislav <stanislav.lisovskiy@intel.com>
Sent: Monday, December 9, 2019 9:55 AM
To: intel-gfx@lists.freedesktop.org
Cc: Vudum, Lakshminarayana <lakshminarayana.vudum@intel.com>
Subject: RE: ✗ Fi.CI.IGT: failure for Enable second DBuf slice for ICL and TGL (rev5)
Getting already a bit pissed off with need on hitting retest button as those failures have nothing in common with DBuf changes. It's again gem-gem-gem...
Best Regards,
Lisovskiy Stanislav
Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo
________________________________________
From: Patchwork [patchwork@emeril.freedesktop.org]
Sent: Thursday, December 05, 2019 8:40 PM
To: Lisovskiy, Stanislav
Cc: intel-gfx@lists.freedesktop.org
Subject: ✗ Fi.CI.IGT: failure for Enable second DBuf slice for ICL and TGL (rev5)
== Series Details ==
Series: Enable second DBuf slice for ICL and TGL (rev5)
URL : https://patchwork.freedesktop.org/series/70059/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7489_full -> Patchwork_15602_full ====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_15602_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_15602_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_15602_full:
### IGT changes ###
#### Possible regressions ####
* igt@gem_exec_balancer@bonded-cork:
- shard-iclb: [PASS][1] -> [DMESG-WARN][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-iclb4/igt@gem_exec_balancer@bonded-cork.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-iclb4/igt@gem_exec_balancer@bonded-cork.html
* igt@gem_exec_parse_blt@allowed-all:
- shard-skl: [PASS][3] -> [DMESG-WARN][4]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-skl8/igt@gem_exec_parse_blt@allowed-all.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-skl9/igt@gem_exec_parse_blt@allowed-all.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-indfb-pgflip-blt:
- shard-skl: NOTRUN -> [DMESG-WARN][5]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-skl7/igt@kms_frontbuffer_tracking@psr-1p-primscrn-indfb-pgflip-blt.html
* igt@perf_pmu@busy-idle-bcs0:
- shard-kbl: [PASS][6] -> [DMESG-WARN][7] +2 similar issues
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-kbl1/igt@perf_pmu@busy-idle-bcs0.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-kbl4/igt@perf_pmu@busy-idle-bcs0.html
Known issues
------------
Here are the changes found in Patchwork_15602_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_busy@extended-parallel-vcs1:
- shard-iclb: [PASS][8] -> [SKIP][9] ([fdo#112080]) +6 similar issues
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-iclb1/igt@gem_busy@extended-parallel-vcs1.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-iclb3/igt@gem_busy@extended-parallel-vcs1.html
* igt@gem_ctx_isolation@bcs0-s3:
- shard-apl: [PASS][10] -> [DMESG-WARN][11] ([i915#180]) +1 similar issue
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-apl3/igt@gem_ctx_isolation@bcs0-s3.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-apl6/igt@gem_ctx_isolation@bcs0-s3.html
* igt@gem_ctx_isolation@rcs0-s3:
- shard-kbl: [PASS][12] -> [DMESG-WARN][13] ([i915#180]) +6 similar issues
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-kbl1/igt@gem_ctx_isolation@rcs0-s3.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-kbl3/igt@gem_ctx_isolation@rcs0-s3.html
* igt@gem_ctx_persistence@vcs1-queued:
- shard-iclb: [PASS][14] -> [SKIP][15] ([fdo#109276] / [fdo#112080]) +1 similar issue
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-iclb2/igt@gem_ctx_persistence@vcs1-queued.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-iclb6/igt@gem_ctx_persistence@vcs1-queued.html
* igt@gem_eio@kms:
- shard-snb: [PASS][16] -> [INCOMPLETE][17] ([i915#82])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-snb1/igt@gem_eio@kms.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-snb6/igt@gem_eio@kms.html
* igt@gem_exec_balancer@smoke:
- shard-iclb: [PASS][18] -> [SKIP][19] ([fdo#110854])
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-iclb2/igt@gem_exec_balancer@smoke.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-iclb6/igt@gem_exec_balancer@smoke.html
* igt@gem_exec_schedule@fifo-bsd1:
- shard-iclb: [PASS][20] -> [SKIP][21] ([fdo#109276]) +4 similar issues
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-iclb1/igt@gem_exec_schedule@fifo-bsd1.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-iclb3/igt@gem_exec_schedule@fifo-bsd1.html
* igt@gem_exec_schedule@preempt-hang-bsd:
- shard-iclb: [PASS][22] -> [SKIP][23] ([fdo#112146]) +1 similar issue
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-iclb6/igt@gem_exec_schedule@preempt-hang-bsd.html
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-iclb1/igt@gem_exec_schedule@preempt-hang-bsd.html
* igt@gem_exec_schedule@preempt-queue-chain-bsd2:
- shard-tglb: [PASS][24] -> [INCOMPLETE][25] ([fdo#111677])
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-tglb5/igt@gem_exec_schedule@preempt-queue-chain-bsd2.html
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-tglb6/igt@gem_exec_schedule@preempt-queue-chain-bsd2.html
* igt@gem_exec_schedule@preempt-queue-chain-render:
- shard-tglb: [PASS][26] -> [INCOMPLETE][27] ([fdo#111606] / [fdo#111677])
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-tglb1/igt@gem_exec_schedule@preempt-queue-chain-render.html
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-tglb6/igt@gem_exec_schedule@preempt-queue-chain-render.html
* igt@gem_persistent_relocs@forked-interruptible-thrashing:
- shard-kbl: [PASS][28] -> [FAIL][29] ([i915#520])
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-kbl1/igt@gem_persistent_relocs@forked-interruptible-thrashing.html
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-kbl2/igt@gem_persistent_relocs@forked-interruptible-thrashing.html
* igt@gem_persistent_relocs@forked-thrashing:
- shard-iclb: [PASS][30] -> [TIMEOUT][31] ([i915#530])
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-iclb4/igt@gem_persistent_relocs@forked-thrashing.html
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-iclb4/igt@gem_persistent_relocs@forked-thrashing.html
* igt@gem_ppgtt@flink-and-close-vma-leak:
- shard-skl: [PASS][32] -> [FAIL][33] ([i915#644])
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-skl3/igt@gem_ppgtt@flink-and-close-vma-leak.html
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-skl8/igt@gem_ppgtt@flink-and-close-vma-leak.html
* igt@gem_userptr_blits@map-fixed-invalidate-busy-gup:
- shard-snb: [PASS][34] -> [DMESG-WARN][35] ([fdo#111870])
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-snb6/igt@gem_userptr_blits@map-fixed-invalidate-busy-gup.html
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-snb2/igt@gem_userptr_blits@map-fixed-invalidate-busy-gup.html
* igt@gem_workarounds@suspend-resume-fd:
- shard-skl: [PASS][36] -> [INCOMPLETE][37] ([i915#69]) +1 similar issue
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-skl3/igt@gem_workarounds@suspend-resume-fd.html
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-skl8/igt@gem_workarounds@suspend-resume-fd.html
* igt@i915_pm_rpm@system-suspend-execbuf:
- shard-skl: [PASS][38] -> [INCOMPLETE][39] ([i915#151] / [i915#69]) +1 similar issue
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-skl9/igt@i915_pm_rpm@system-suspend-execbuf.html
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-skl2/igt@i915_pm_rpm@system-suspend-execbuf.html
* igt@i915_selftest@live_blt:
- shard-hsw: [PASS][40] -> [DMESG-FAIL][41] ([i915#683])
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-hsw4/igt@i915_selftest@live_blt.html
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-hsw6/igt@i915_selftest@live_blt.html
* igt@kms_big_fb@y-tiled-16bpp-rotate-0:
- shard-kbl: [PASS][42] -> [INCOMPLETE][43] ([fdo#103665] / [fdo#112413])
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-kbl4/igt@kms_big_fb@y-tiled-16bpp-rotate-0.html
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-kbl4/igt@kms_big_fb@y-tiled-16bpp-rotate-0.html
* igt@kms_big_fb@y-tiled-16bpp-rotate-180:
- shard-tglb: [PASS][44] -> [INCOMPLETE][45] ([i915#667])
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-tglb8/igt@kms_big_fb@y-tiled-16bpp-rotate-180.html
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-tglb7/igt@kms_big_fb@y-tiled-16bpp-rotate-180.html
* igt@kms_big_fb@y-tiled-8bpp-rotate-180:
- shard-skl: [PASS][46] -> [INCOMPLETE][47] ([fdo#112347])
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-skl1/igt@kms_big_fb@y-tiled-8bpp-rotate-180.html
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-skl8/igt@kms_big_fb@y-tiled-8bpp-rotate-180.html
* igt@kms_ccs@pipe-a-crc-primary-basic:
- shard-skl: [PASS][48] -> [INCOMPLETE][49] ([i915#667])
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-skl9/igt@kms_ccs@pipe-a-crc-primary-basic.html
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-skl6/igt@kms_ccs@pipe-a-crc-primary-basic.html
* igt@kms_cursor_crc@pipe-a-cursor-128x42-onscreen:
- shard-hsw: [PASS][50] -> [DMESG-WARN][51] ([IGT#6])
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-hsw5/igt@kms_cursor_crc@pipe-a-cursor-128x42-onscreen.html
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-hsw6/igt@kms_cursor_crc@pipe-a-cursor-128x42-onscreen.html
* igt@kms_cursor_crc@pipe-c-cursor-256x85-random:
- shard-skl: [PASS][52] -> [FAIL][53] ([i915#54]) +1 similar issue
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-skl8/igt@kms_cursor_crc@pipe-c-cursor-256x85-random.html
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-skl8/igt@kms_cursor_crc@pipe-c-cursor-256x85-random.html
* igt@kms_cursor_crc@pipe-d-cursor-suspend:
- shard-tglb: [PASS][54] -> [INCOMPLETE][55] ([i915#460]) +1 similar issue
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-tglb9/igt@kms_cursor_crc@pipe-d-cursor-suspend.html
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-tglb4/igt@kms_cursor_crc@pipe-d-cursor-suspend.html
* igt@kms_draw_crc@draw-method-rgb565-render-xtiled:
- shard-kbl: [PASS][56] -> [DMESG-WARN][57] ([i915#728]) +4 similar issues
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-kbl3/igt@kms_draw_crc@draw-method-rgb565-render-xtiled.html
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-kbl1/igt@kms_draw_crc@draw-method-rgb565-render-xtiled.html
* igt@kms_draw_crc@draw-method-xrgb2101010-render-xtiled:
- shard-skl: [PASS][58] -> [DMESG-WARN][59] ([i915#728]) +4 similar issues
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-skl3/igt@kms_draw_crc@draw-method-xrgb2101010-render-xtiled.html
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-skl7/igt@kms_draw_crc@draw-method-xrgb2101010-render-xtiled.html
* igt@kms_fbcon_fbt@fbc-suspend:
- shard-tglb: [PASS][60] -> [INCOMPLETE][61] ([i915#435] / [i915#456] / [i915#460])
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-tglb7/igt@kms_fbcon_fbt@fbc-suspend.html
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-tglb5/igt@kms_fbcon_fbt@fbc-suspend.html
* igt@kms_flip@flip-vs-suspend:
- shard-skl: [PASS][62] -> [INCOMPLETE][63] ([i915#221])
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-skl5/igt@kms_flip@flip-vs-suspend.html
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-skl5/igt@kms_flip@flip-vs-suspend.html
* igt@kms_flip@flip-vs-suspend-interruptible:
- shard-tglb: [PASS][64] -> [INCOMPLETE][65] ([i915#456] / [i915#460] / [i915#516])
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-tglb9/igt@kms_flip@flip-vs-suspend-interruptible.html
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-tglb8/igt@kms_flip@flip-vs-suspend-interruptible.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-indfb-draw-mmap-gtt:
- shard-tglb: [PASS][66] -> [INCOMPLETE][67] ([i915#474])
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-tglb7/igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-indfb-draw-mmap-gtt.html
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-tglb1/igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-indfb-draw-mmap-gtt.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-blt:
- shard-iclb: [PASS][68] -> [FAIL][69] ([i915#49]) +1 similar issue
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-iclb3/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-blt.html
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-iclb2/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-blt.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-pwrite:
- shard-tglb: [PASS][70] -> [FAIL][71] ([i915#49])
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-tglb7/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-pwrite.html
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-tglb5/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-pwrite.html
* igt@kms_frontbuffer_tracking@fbcpsr-suspend:
- shard-tglb: [PASS][72] -> [INCOMPLETE][73] ([i915#456] / [i915#460] / [i915#474])
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-tglb6/igt@kms_frontbuffer_tracking@fbcpsr-suspend.html
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-tglb2/igt@kms_frontbuffer_tracking@fbcpsr-suspend.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-mmap-cpu:
- shard-tglb: [PASS][74] -> [DMESG-WARN][75] ([i915#728]) +3 similar issues
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-tglb7/igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-mmap-cpu.html
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-tglb7/igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-mmap-cpu.html
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
- shard-tglb: [PASS][76] -> [INCOMPLETE][77] ([i915#456] / [i915#460])
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-tglb9/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b.html
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-tglb2/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b.html
* igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
- shard-skl: [PASS][78] -> [FAIL][79] ([fdo#108145] / [i915#265])
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-skl4/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-skl4/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
* igt@kms_psr@psr2_cursor_render:
- shard-iclb: [PASS][80] -> [SKIP][81] ([fdo#109441])
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-iclb2/igt@kms_psr@psr2_cursor_render.html
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-iclb6/igt@kms_psr@psr2_cursor_render.html
* igt@perf@disabled-read-error:
- shard-iclb: [PASS][82] -> [DMESG-WARN][83] ([i915#645])
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-iclb4/igt@perf@disabled-read-error.html
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-iclb2/igt@perf@disabled-read-error.html
* igt@perf_pmu@busy-check-all-rcs0:
- shard-iclb: [PASS][84] -> [DMESG-WARN][85] ([i915#728]) +6 similar issues
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-iclb4/igt@perf_pmu@busy-check-all-rcs0.html
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-iclb4/igt@perf_pmu@busy-check-all-rcs0.html
#### Possible fixes ####
* igt@gem_busy@busy-vcs1:
- shard-iclb: [SKIP][86] ([fdo#112080]) -> [PASS][87] +5 similar issues
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-iclb3/igt@gem_busy@busy-vcs1.html
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-iclb2/igt@gem_busy@busy-vcs1.html
* igt@gem_ctx_persistence@vcs1-mixed:
- shard-iclb: [SKIP][88] ([fdo#109276] / [fdo#112080]) -> [PASS][89] +1 similar issue
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-iclb6/igt@gem_ctx_persistence@vcs1-mixed.html
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-iclb1/igt@gem_ctx_persistence@vcs1-mixed.html
* igt@gem_exec_balancer@hang:
- shard-kbl: [DMESG-WARN][90] -> [PASS][91] +1 similar issue
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-kbl1/igt@gem_exec_balancer@hang.html
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-kbl3/igt@gem_exec_balancer@hang.html
* igt@gem_exec_create@forked:
- shard-tglb: [INCOMPLETE][92] ([fdo#108838] / [i915#435]) -> [PASS][93]
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-tglb4/igt@gem_exec_create@forked.html
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-tglb9/igt@gem_exec_create@forked.html
* igt@gem_exec_nop@basic-sequential:
- shard-tglb: [INCOMPLETE][94] ([i915#435]) -> [PASS][95]
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-tglb6/igt@gem_exec_nop@basic-sequential.html
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-tglb3/igt@gem_exec_nop@basic-sequential.html
* igt@gem_exec_parallel@vecs0-fds:
- shard-hsw: [FAIL][96] ([i915#676]) -> [PASS][97] +2 similar issues
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-hsw1/igt@gem_exec_parallel@vecs0-fds.html
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-hsw7/igt@gem_exec_parallel@vecs0-fds.html
* igt@gem_exec_schedule@preempt-queue-contexts-bsd2:
- shard-tglb: [INCOMPLETE][98] ([fdo#111606] / [fdo#111677]) -> [PASS][99]
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-tglb6/igt@gem_exec_schedule@preempt-queue-contexts-bsd2.html
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-tglb8/igt@gem_exec_schedule@preempt-queue-contexts-bsd2.html
* igt@gem_persistent_relocs@forked-interruptible-faulting-reloc-thrash-inactive:
- shard-hsw: [TIMEOUT][100] ([i915#530]) -> [PASS][101]
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-hsw5/igt@gem_persistent_relocs@forked-interruptible-faulting-reloc-thrash-inactive.html
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-hsw2/igt@gem_persistent_relocs@forked-interruptible-faulting-reloc-thrash-inactive.html
* igt@gem_ppgtt@flink-and-close-vma-leak:
- shard-iclb: [FAIL][102] ([i915#644]) -> [PASS][103]
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-iclb5/igt@gem_ppgtt@flink-and-close-vma-leak.html
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-iclb7/igt@gem_ppgtt@flink-and-close-vma-leak.html
* igt@gem_userptr_blits@sync-unmap:
- shard-snb: [DMESG-WARN][104] ([fdo#111870]) -> [PASS][105]
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-snb6/igt@gem_userptr_blits@sync-unmap.html
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-snb5/igt@gem_userptr_blits@sync-unmap.html
* igt@i915_pm_backlight@fade_with_suspend:
- shard-tglb: [INCOMPLETE][106] ([i915#456] / [i915#460]) -> [PASS][107]
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-tglb1/igt@i915_pm_backlight@fade_with_suspend.html
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-tglb6/igt@i915_pm_backlight@fade_with_suspend.html
* igt@i915_pm_dc@dc6-dpms:
- shard-iclb: [FAIL][108] ([i915#454]) -> [PASS][109]
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-iclb3/igt@i915_pm_dc@dc6-dpms.html
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-iclb1/igt@i915_pm_dc@dc6-dpms.html
* igt@kms_big_fb@yf-tiled-16bpp-rotate-0:
- shard-kbl: [INCOMPLETE][110] ([fdo#103665]) -> [PASS][111] +1 similar issue
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-kbl6/igt@kms_big_fb@yf-tiled-16bpp-rotate-0.html
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-kbl3/igt@kms_big_fb@yf-tiled-16bpp-rotate-0.html
* igt@kms_cursor_crc@pipe-a-cursor-suspend:
- shard-kbl: [DMESG-WARN][112] ([i915#180]) -> [PASS][113] +3 similar issues
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-kbl4/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-kbl2/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
* igt@kms_cursor_crc@pipe-b-cursor-64x21-onscreen:
- shard-kbl: [DMESG-WARN][114] ([IGT#6]) -> [PASS][115]
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-kbl3/igt@kms_cursor_crc@pipe-b-cursor-64x21-onscreen.html
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-kbl3/igt@kms_cursor_crc@pipe-b-cursor-64x21-onscreen.html
* igt@kms_cursor_crc@pipe-b-cursor-64x21-sliding:
- shard-skl: [FAIL][116] ([i915#54]) -> [PASS][117] +1 similar issue
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-skl7/igt@kms_cursor_crc@pipe-b-cursor-64x21-sliding.html
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-skl5/igt@kms_cursor_crc@pipe-b-cursor-64x21-sliding.html
* igt@kms_draw_crc@draw-method-rgb565-mmap-wc-xtiled:
- shard-skl: [FAIL][118] ([i915#52] / [i915#54]) -> [PASS][119]
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-skl9/igt@kms_draw_crc@draw-method-rgb565-mmap-wc-xtiled.html
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-skl4/igt@kms_draw_crc@draw-method-rgb565-mmap-wc-xtiled.html
* igt@kms_flip@2x-flip-vs-expired-vblank-interruptible:
- shard-glk: [FAIL][120] ([i915#79]) -> [PASS][121]
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-glk7/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible.html
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-glk9/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible:
- shard-skl: [FAIL][122] ([i915#79]) -> [PASS][123]
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-skl5/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-skl4/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
* igt@kms_flip@flip-vs-suspend-interruptible:
- shard-skl: [INCOMPLETE][124] ([i915#221]) -> [PASS][125]
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-skl7/igt@kms_flip@flip-vs-suspend-interruptible.html
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-skl7/igt@kms_flip@flip-vs-suspend-interruptible.html
* igt@kms_flip_tiling@flip-x-tiled:
- shard-tglb: [FAIL][126] ([i915#699]) -> [PASS][127]
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-tglb5/igt@kms_flip_tiling@flip-x-tiled.html
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-tglb3/igt@kms_flip_tiling@flip-x-tiled.html
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-render:
- shard-iclb: [FAIL][128] ([i915#49]) -> [PASS][129] +3 similar issues
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-iclb6/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-render.html
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-iclb6/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-render.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-blt:
- shard-tglb: [FAIL][130] ([i915#49]) -> [PASS][131] +2 similar issues
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-tglb6/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-blt.html
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-tglb8/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-blt.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-indfb-msflip-blt:
- shard-skl: [DMESG-WARN][132] ([i915#728]) -> [PASS][133] +5 similar issues
[132]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-skl1/igt@kms_frontbuffer_tracking@psr-1p-primscrn-indfb-msflip-blt.html
[133]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-skl5/igt@kms_frontbuffer_tracking@psr-1p-primscrn-indfb-msflip-blt.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-indfb-plflip-blt:
- shard-skl: [INCOMPLETE][134] ([i915#123]) -> [PASS][135]
[134]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-skl10/igt@kms_frontbuffer_tracking@psr-1p-primscrn-indfb-plflip-blt.html
[135]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-skl5/igt@kms_frontbuffer_tracking@psr-1p-primscrn-indfb-plflip-blt.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-render:
- shard-tglb: [DMESG-WARN][136] ([i915#728]) -> [PASS][137] +2 similar issues
[136]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-tglb6/igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-render.html
[137]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-tglb3/igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-render.html
* igt@kms_frontbuffer_tracking@psr-1p-rte:
- shard-iclb: [DMESG-WARN][138] ([i915#728]) -> [PASS][139] +3 similar issues
[138]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-iclb6/igt@kms_frontbuffer_tracking@psr-1p-rte.html
[139]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-iclb1/igt@kms_frontbuffer_tracking@psr-1p-rte.html
* igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes:
- shard-apl: [DMESG-WARN][140] ([i915#180]) -> [PASS][141] +1 similar issue
[140]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-apl6/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html
[141]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-apl4/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html
* igt@kms_psr@psr2_sprite_mmap_cpu:
- shard-iclb: [SKIP][142] ([fdo#109441]) -> [PASS][143]
[142]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-iclb4/igt@kms_psr@psr2_sprite_mmap_cpu.html
[143]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-iclb2/igt@kms_psr@psr2_sprite_mmap_cpu.html
* igt@kms_psr@psr2_suspend:
- shard-tglb: [DMESG-WARN][144] ([i915#402]) -> [PASS][145]
[144]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-tglb6/igt@kms_psr@psr2_suspend.html
[145]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-tglb8/igt@kms_psr@psr2_suspend.html
* igt@kms_setmode@basic:
- shard-kbl: [FAIL][146] ([i915#31]) -> [PASS][147]
[146]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-kbl2/igt@kms_setmode@basic.html
[147]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-kbl3/igt@kms_setmode@basic.html
* igt@kms_vblank@pipe-c-ts-continuation-dpms-suspend:
- shard-tglb: [INCOMPLETE][148] ([i915#460]) -> [PASS][149]
[148]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-tglb4/igt@kms_vblank@pipe-c-ts-continuation-dpms-suspend.html
[149]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-tglb4/igt@kms_vblank@pipe-c-ts-continuation-dpms-suspend.html
* igt@perf@oa-exponents:
- shard-hsw: [FAIL][150] ([i915#84]) -> [PASS][151]
[150]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-hsw4/igt@perf@oa-exponents.html
[151]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-hsw5/igt@perf@oa-exponents.html
* igt@prime_vgem@fence-wait-bsd2:
- shard-iclb: [SKIP][152] ([fdo#109276]) -> [PASS][153] +10 similar issues
[152]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-iclb3/igt@prime_vgem@fence-wait-bsd2.html
[153]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-iclb1/igt@prime_vgem@fence-wait-bsd2.html
#### Warnings ####
* igt@gem_ctx_isolation@vcs1-nonpriv:
- shard-iclb: [FAIL][154] ([IGT#28]) -> [SKIP][155] ([fdo#109276] / [fdo#112080])
[154]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-iclb2/igt@gem_ctx_isolation@vcs1-nonpriv.html
[155]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/shard-iclb6/igt@gem_ctx_isolation@vcs1-nonpriv.html
* igt@kms_flip@flip-vs-suspend:
- shard-kbl: [INCOMPLETE][156] ([fdo#103665] / [i915#600]) -> [DMESG-WARN][157] ([i915#180])
[156]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7489/shard-kbl7/igt@kms_fl
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15602/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [Intel-gfx] [PATCH v7 1/4] drm/i915: Remove skl_ddl_allocation struct
2019-11-29 13:37 ` [Intel-gfx] " Stanislav Lisovskiy
(?)
@ 2019-12-13 4:22 ` Matt Roper
2019-12-13 6:28 ` Jani Nikula
2019-12-13 8:27 ` Lisovskiy, Stanislav
-1 siblings, 2 replies; 26+ messages in thread
From: Matt Roper @ 2019-12-13 4:22 UTC (permalink / raw)
To: Stanislav Lisovskiy; +Cc: intel-gfx
On Fri, Nov 29, 2019 at 03:37:06PM +0200, Stanislav Lisovskiy wrote:
> Current consensus that it is redundant as
> we already have skl_ddb_values struct out there,
> also this struct contains only single member
> which makes it unnecessary.
>
> v2: As dirty_pipes soon going to be nuked away
> from skl_ddb_values, evacuating enabled_slices
> to safer in dev_priv.
>
> Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 16 ++++-----
> .../drm/i915/display/intel_display_power.c | 8 ++---
> .../drm/i915/display/intel_display_types.h | 3 ++
> drivers/gpu/drm/i915/i915_drv.h | 7 ++--
> drivers/gpu/drm/i915/intel_pm.c | 34 ++++++++-----------
> drivers/gpu/drm/i915/intel_pm.h | 6 ++--
> 6 files changed, 34 insertions(+), 40 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 53dc310a5f6d..dda43e3dcdbf 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -13393,14 +13393,13 @@ static void verify_wm_state(struct intel_crtc *crtc,
> struct skl_hw_state {
> struct skl_ddb_entry ddb_y[I915_MAX_PLANES];
> struct skl_ddb_entry ddb_uv[I915_MAX_PLANES];
> - struct skl_ddb_allocation ddb;
> struct skl_pipe_wm wm;
> } *hw;
> - struct skl_ddb_allocation *sw_ddb;
> struct skl_pipe_wm *sw_wm;
> struct skl_ddb_entry *hw_ddb_entry, *sw_ddb_entry;
> const enum pipe pipe = crtc->pipe;
> int plane, level, max_level = ilk_wm_max_level(dev_priv);
> + u8 hw_enabled_slices;
>
> if (INTEL_GEN(dev_priv) < 9 || !new_crtc_state->hw.active)
> return;
> @@ -13414,14 +13413,13 @@ static void verify_wm_state(struct intel_crtc *crtc,
>
> skl_pipe_ddb_get_hw_state(crtc, hw->ddb_y, hw->ddb_uv);
>
> - skl_ddb_get_hw_state(dev_priv, &hw->ddb);
> - sw_ddb = &dev_priv->wm.skl_hw.ddb;
> + hw_enabled_slices = intel_enabled_dbuf_slices_num(dev_priv);
>
> if (INTEL_GEN(dev_priv) >= 11 &&
> - hw->ddb.enabled_slices != sw_ddb->enabled_slices)
> + hw_enabled_slices != dev_priv->enabled_slices)
> DRM_ERROR("mismatch in DBUF Slices (expected %u, got %u)\n",
> - sw_ddb->enabled_slices,
> - hw->ddb.enabled_slices);
> + dev_priv->enabled_slices,
> + hw_enabled_slices);
>
> /* planes */
> for_each_universal_plane(dev_priv, pipe, plane) {
> @@ -14647,8 +14645,8 @@ static void skl_commit_modeset_enables(struct intel_atomic_state *state)
> unsigned int updated = 0;
> bool progress;
> int i;
> - u8 hw_enabled_slices = dev_priv->wm.skl_hw.ddb.enabled_slices;
> - u8 required_slices = state->wm_results.ddb.enabled_slices;
> + u8 hw_enabled_slices = dev_priv->enabled_slices;
> + u8 required_slices = state->enabled_slices;
> struct skl_ddb_entry entries[I915_MAX_PIPES] = {};
>
> for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i)
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
> index ce1b64f4dd44..4c3ede73e863 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> @@ -4264,7 +4264,7 @@ static u8 intel_dbuf_max_slices(struct drm_i915_private *dev_priv)
> void icl_dbuf_slices_update(struct drm_i915_private *dev_priv,
> u8 req_slices)
> {
> - const u8 hw_enabled_slices = dev_priv->wm.skl_hw.ddb.enabled_slices;
> + const u8 hw_enabled_slices = dev_priv->enabled_slices;
> bool ret;
>
> if (req_slices > intel_dbuf_max_slices(dev_priv)) {
> @@ -4281,7 +4281,7 @@ void icl_dbuf_slices_update(struct drm_i915_private *dev_priv,
> ret = intel_dbuf_slice_set(dev_priv, DBUF_CTL_S2, false);
>
> if (ret)
> - dev_priv->wm.skl_hw.ddb.enabled_slices = req_slices;
> + dev_priv->enabled_slices = req_slices;
> }
>
> static void icl_dbuf_enable(struct drm_i915_private *dev_priv)
> @@ -4300,7 +4300,7 @@ static void icl_dbuf_enable(struct drm_i915_private *dev_priv)
> * FIXME: for now pretend that we only have 1 slice, see
> * intel_enabled_dbuf_slices_num().
> */
> - dev_priv->wm.skl_hw.ddb.enabled_slices = 1;
> + dev_priv->enabled_slices = 1;
> }
>
> static void icl_dbuf_disable(struct drm_i915_private *dev_priv)
> @@ -4319,7 +4319,7 @@ static void icl_dbuf_disable(struct drm_i915_private *dev_priv)
> * FIXME: for now pretend that the first slice is always
> * enabled, see intel_enabled_dbuf_slices_num().
> */
> - dev_priv->wm.skl_hw.ddb.enabled_slices = 1;
> + dev_priv->enabled_slices = 1;
> }
>
> static void icl_mbus_init(struct drm_i915_private *dev_priv)
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 83ea04149b77..5eaeaf487a01 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -517,6 +517,9 @@ struct intel_atomic_state {
> /* Gen9+ only */
> struct skl_ddb_values wm_results;
>
> + /* Number of enabled DBuf slices */
> + u8 enabled_slices;
> +
> struct i915_sw_fence commit_ready;
>
> struct llist_node freed;
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index fdae5a919bc8..195629a37a61 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -798,13 +798,8 @@ static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1,
> return false;
> }
>
> -struct skl_ddb_allocation {
> - u8 enabled_slices; /* GEN11 has configurable 2 slices */
> -};
> -
> struct skl_ddb_values {
> unsigned dirty_pipes;
> - struct skl_ddb_allocation ddb;
> };
Seems strange to have a single entry structure (especially one that
isn't even a "DDB value" as the name implies). Do you kill dirty_pipes
somewhere later in this series? I didn't see it from a quick skim.
>
> struct skl_wm_level {
> @@ -1215,6 +1210,8 @@ struct drm_i915_private {
> bool distrust_bios_wm;
> } wm;
>
> + u8 enabled_slices; /* GEN11 has configurable 2 slices */
Intel hardware has long used the terms "slice" and "subslice" for the
way EUs are grouped on the GT side. Now that this is pulled out from
the substructs that gave it additional context, I think we need to
rename this to something like 'enabled_dbuf_slices' to avoid confusion
with the more widespread meaning of the word 'slice.' Same for
intel_atomic_state farther up.
> +
> struct dram_info {
> bool valid;
> bool is_16gb_dimm;
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 5aad9d49a528..a93b4385de4b 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3599,7 +3599,7 @@ bool ilk_disable_lp_wm(struct drm_device *dev)
> return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL);
> }
>
> -static u8 intel_enabled_dbuf_slices_num(struct drm_i915_private *dev_priv)
> +u8 intel_enabled_dbuf_slices_num(struct drm_i915_private *dev_priv)
> {
> u8 enabled_slices;
>
> @@ -3822,9 +3822,10 @@ bool intel_can_enable_sagv(struct intel_atomic_state *state)
> static u16 intel_get_ddb_size(struct drm_i915_private *dev_priv,
> const struct intel_crtc_state *crtc_state,
> const u64 total_data_rate,
> - const int num_active,
> - struct skl_ddb_allocation *ddb)
> + const int num_active)
> {
> + struct drm_atomic_state *state = crtc_state->uapi.state;
> + struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
> const struct drm_display_mode *adjusted_mode;
> u64 total_data_bw;
> u16 ddb_size = INTEL_INFO(dev_priv)->ddb_size;
> @@ -3846,9 +3847,9 @@ static u16 intel_get_ddb_size(struct drm_i915_private *dev_priv,
> * - should validate we stay within the hw bandwidth limits
> */
> if (0 && (num_active > 1 || total_data_bw >= GBps(12))) {
> - ddb->enabled_slices = 2;
> + intel_state->enabled_slices = 2;
> } else {
> - ddb->enabled_slices = 1;
> + intel_state->enabled_slices = 1;
> ddb_size /= 2;
> }
>
> @@ -3859,7 +3860,6 @@ static void
> skl_ddb_get_pipe_allocation_limits(struct drm_i915_private *dev_priv,
> const struct intel_crtc_state *crtc_state,
> const u64 total_data_rate,
> - struct skl_ddb_allocation *ddb,
> struct skl_ddb_entry *alloc, /* out */
> int *num_active /* out */)
> {
> @@ -3885,7 +3885,7 @@ skl_ddb_get_pipe_allocation_limits(struct drm_i915_private *dev_priv,
> *num_active = hweight8(dev_priv->active_pipes);
>
> ddb_size = intel_get_ddb_size(dev_priv, crtc_state, total_data_rate,
> - *num_active, ddb);
> + *num_active);
>
> /*
> * If the state doesn't change the active CRTC's or there is no
> @@ -4046,10 +4046,9 @@ void skl_pipe_ddb_get_hw_state(struct intel_crtc *crtc,
> intel_display_power_put(dev_priv, power_domain, wakeref);
> }
>
> -void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
> - struct skl_ddb_allocation *ddb /* out */)
> +void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv)
> {
> - ddb->enabled_slices = intel_enabled_dbuf_slices_num(dev_priv);
> + dev_priv->enabled_slices = intel_enabled_dbuf_slices_num(dev_priv);
> }
>
> /*
> @@ -4226,8 +4225,7 @@ icl_get_total_relative_data_rate(struct intel_crtc_state *crtc_state,
> }
>
> static int
> -skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state,
> - struct skl_ddb_allocation *ddb /* out */)
> +skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state)
> {
> struct drm_atomic_state *state = crtc_state->uapi.state;
> struct drm_crtc *crtc = crtc_state->uapi.crtc;
> @@ -4269,7 +4267,7 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state,
>
>
> skl_ddb_get_pipe_allocation_limits(dev_priv, crtc_state, total_data_rate,
> - ddb, alloc, &num_active);
> + alloc, &num_active);
> alloc_size = skl_ddb_entry_size(alloc);
> if (alloc_size == 0)
> return 0;
> @@ -5183,18 +5181,17 @@ skl_ddb_add_affected_planes(const struct intel_crtc_state *old_crtc_state,
> static int
> skl_compute_ddb(struct intel_atomic_state *state)
> {
> - const struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> - struct skl_ddb_allocation *ddb = &state->wm_results.ddb;
> + struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> struct intel_crtc_state *old_crtc_state;
> struct intel_crtc_state *new_crtc_state;
> struct intel_crtc *crtc;
> int ret, i;
>
> - memcpy(ddb, &dev_priv->wm.skl_hw.ddb, sizeof(*ddb));
> + state->enabled_slices = dev_priv->enabled_slices;
>
> for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
> new_crtc_state, i) {
> - ret = skl_allocate_pipe_ddb(new_crtc_state, ddb);
> + ret = skl_allocate_pipe_ddb(new_crtc_state);
> if (ret)
> return ret;
>
> @@ -5666,11 +5663,10 @@ void skl_pipe_wm_get_hw_state(struct intel_crtc *crtc,
> void skl_wm_get_hw_state(struct drm_i915_private *dev_priv)
> {
> struct skl_ddb_values *hw = &dev_priv->wm.skl_hw;
> - struct skl_ddb_allocation *ddb = &dev_priv->wm.skl_hw.ddb;
> struct intel_crtc *crtc;
> struct intel_crtc_state *crtc_state;
>
> - skl_ddb_get_hw_state(dev_priv, ddb);
> + skl_ddb_get_hw_state(dev_priv);
At this point you might as well replace this with a direct call to
intel_enabled_dbuf_slices_num() and drop the skl_ddb_get_hw_state()
completely.
> for_each_intel_crtc(&dev_priv->drm, crtc) {
> crtc_state = to_intel_crtc_state(crtc->base.state);
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.h b/drivers/gpu/drm/i915/intel_pm.h
> index b579c724b915..4aafae4c8e0d 100644
> --- a/drivers/gpu/drm/i915/intel_pm.h
> +++ b/drivers/gpu/drm/i915/intel_pm.h
> @@ -17,8 +17,8 @@ struct intel_atomic_state;
> struct intel_crtc;
> struct intel_crtc_state;
> struct intel_plane;
> -struct skl_ddb_allocation;
> struct skl_ddb_entry;
> +struct skl_ddb_values;
> struct skl_pipe_wm;
> struct skl_wm_level;
>
> @@ -33,11 +33,11 @@ void g4x_wm_get_hw_state(struct drm_i915_private *dev_priv);
> void vlv_wm_get_hw_state(struct drm_i915_private *dev_priv);
> void ilk_wm_get_hw_state(struct drm_i915_private *dev_priv);
> void skl_wm_get_hw_state(struct drm_i915_private *dev_priv);
> +u8 intel_enabled_dbuf_slices_num(struct drm_i915_private *dev_priv);
> void skl_pipe_ddb_get_hw_state(struct intel_crtc *crtc,
> struct skl_ddb_entry *ddb_y,
> struct skl_ddb_entry *ddb_uv);
> -void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
> - struct skl_ddb_allocation *ddb /* out */);
> +void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv);
> void skl_pipe_wm_get_hw_state(struct intel_crtc *crtc,
> struct skl_pipe_wm *out);
> void g4x_wm_sanitize(struct drm_i915_private *dev_priv);
> --
> 2.17.1
>
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [Intel-gfx] [PATCH v7 2/4] drm/i915: Move dbuf slice update to proper place
2019-11-29 13:37 ` [Intel-gfx] " Stanislav Lisovskiy
(?)
@ 2019-12-13 4:22 ` Matt Roper
-1 siblings, 0 replies; 26+ messages in thread
From: Matt Roper @ 2019-12-13 4:22 UTC (permalink / raw)
To: Stanislav Lisovskiy; +Cc: intel-gfx
On Fri, Nov 29, 2019 at 03:37:07PM +0200, Stanislav Lisovskiy wrote:
> Current DBuf slices update wasn't done in proper
> plane, especially its "post" part, which should
> disable those only once vblank had passed and
> all other changes are committed.
>
> v2: Fix to use dev_priv and intel_atomic_state
> instead of skl_ddb_values
> (to be nuked in Villes patch)
>
> Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 38 ++++++++++++++------
> 1 file changed, 28 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index dda43e3dcdbf..db0830745f25 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -14637,6 +14637,28 @@ static void intel_update_trans_port_sync_crtcs(struct intel_crtc *crtc,
> state);
> }
>
> +static void icl_dbuf_slice_pre_update(struct intel_atomic_state *state)
> +{
> + struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> + u8 hw_enabled_slices = dev_priv->enabled_slices;
> + u8 required_slices = state->enabled_slices;
> +
> + /* If 2nd DBuf slice required, enable it here */
> + if (INTEL_GEN(dev_priv) >= 11 && required_slices > hw_enabled_slices)
> + icl_dbuf_slices_update(dev_priv, required_slices);
> +}
> +
> +static void icl_dbuf_slice_post_update(struct intel_atomic_state *state)
> +{
> + struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> + u8 hw_enabled_slices = dev_priv->enabled_slices;
> + u8 required_slices = state->enabled_slices;
> +
> + /* If 2nd DBuf slice is no more required disable it */
> + if (INTEL_GEN(dev_priv) >= 11 && required_slices < hw_enabled_slices)
> + icl_dbuf_slices_update(dev_priv, required_slices);
> +}
> +
> static void skl_commit_modeset_enables(struct intel_atomic_state *state)
> {
> struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> @@ -14645,8 +14667,6 @@ static void skl_commit_modeset_enables(struct intel_atomic_state *state)
> unsigned int updated = 0;
> bool progress;
> int i;
> - u8 hw_enabled_slices = dev_priv->enabled_slices;
> - u8 required_slices = state->enabled_slices;
> struct skl_ddb_entry entries[I915_MAX_PIPES] = {};
>
> for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i)
> @@ -14654,10 +14674,6 @@ static void skl_commit_modeset_enables(struct intel_atomic_state *state)
> if (new_crtc_state->hw.active)
> entries[i] = old_crtc_state->wm.skl.ddb;
>
> - /* If 2nd DBuf slice required, enable it here */
> - if (INTEL_GEN(dev_priv) >= 11 && required_slices > hw_enabled_slices)
> - icl_dbuf_slices_update(dev_priv, required_slices);
> -
> /*
> * Whenever the number of active pipes changes, we need to make sure we
> * update the pipes in the right order so that their ddb allocations
> @@ -14714,10 +14730,6 @@ static void skl_commit_modeset_enables(struct intel_atomic_state *state)
> progress = true;
> }
> } while (progress);
> -
> - /* If 2nd DBuf slice is no more required disable it */
> - if (INTEL_GEN(dev_priv) >= 11 && required_slices < hw_enabled_slices)
> - icl_dbuf_slices_update(dev_priv, required_slices);
> }
>
> static void intel_atomic_helper_free_state(struct drm_i915_private *dev_priv)
> @@ -14847,6 +14859,9 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
> if (state->modeset)
> intel_encoders_update_prepare(state);
>
> + /* Enable all new slices, we might need */
> + icl_dbuf_slice_pre_update(state);
> +
> /* Now enable the clocks, plane, pipe, and connectors that we set up. */
> dev_priv->display.commit_modeset_enables(state);
>
> @@ -14906,6 +14921,9 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
> if (state->modeset && intel_can_enable_sagv(state))
> intel_enable_sagv(dev_priv);
>
> + /* Disable all slices, we don't need */
> + icl_dbuf_slice_post_update(state);
> +
> drm_atomic_helper_commit_hw_done(&state->base);
>
> if (state->modeset) {
> --
> 2.17.1
>
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [Intel-gfx] [PATCH v7 1/4] drm/i915: Remove skl_ddl_allocation struct
2019-12-13 4:22 ` Matt Roper
@ 2019-12-13 6:28 ` Jani Nikula
2019-12-13 8:27 ` Lisovskiy, Stanislav
1 sibling, 0 replies; 26+ messages in thread
From: Jani Nikula @ 2019-12-13 6:28 UTC (permalink / raw)
To: Matt Roper, Stanislav Lisovskiy; +Cc: intel-gfx
On Thu, 12 Dec 2019, Matt Roper <matthew.d.roper@intel.com> wrote:
> On Fri, Nov 29, 2019 at 03:37:06PM +0200, Stanislav Lisovskiy wrote:
>> struct skl_wm_level {
>> @@ -1215,6 +1210,8 @@ struct drm_i915_private {
>> bool distrust_bios_wm;
>> } wm;
>>
>> + u8 enabled_slices; /* GEN11 has configurable 2 slices */
>
> Intel hardware has long used the terms "slice" and "subslice" for the
> way EUs are grouped on the GT side. Now that this is pulled out from
> the substructs that gave it additional context, I think we need to
> rename this to something like 'enabled_dbuf_slices' to avoid confusion
> with the more widespread meaning of the word 'slice.' Same for
> intel_atomic_state farther up.
Agreed.
BR,
Jani.
--
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [Intel-gfx] [PATCH v7 1/4] drm/i915: Remove skl_ddl_allocation struct
2019-12-13 4:22 ` Matt Roper
2019-12-13 6:28 ` Jani Nikula
@ 2019-12-13 8:27 ` Lisovskiy, Stanislav
1 sibling, 0 replies; 26+ messages in thread
From: Lisovskiy, Stanislav @ 2019-12-13 8:27 UTC (permalink / raw)
To: Roper, Matthew D; +Cc: intel-gfx
On Thu, 2019-12-12 at 20:22 -0800, Matt Roper wrote:
> On Fri, Nov 29, 2019 at 03:37:06PM +0200, Stanislav Lisovskiy wrote:
> > Current consensus that it is redundant as
> > we already have skl_ddb_values struct out there,
> > also this struct contains only single member
> > which makes it unnecessary.
> >
> > v2: As dirty_pipes soon going to be nuked away
> > from skl_ddb_values, evacuating enabled_slices
> > to safer in dev_priv.
> >
> > Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_display.c | 16 ++++-----
> > .../drm/i915/display/intel_display_power.c | 8 ++---
> > .../drm/i915/display/intel_display_types.h | 3 ++
> > drivers/gpu/drm/i915/i915_drv.h | 7 ++--
> > drivers/gpu/drm/i915/intel_pm.c | 34 ++++++++-------
> > ----
> > drivers/gpu/drm/i915/intel_pm.h | 6 ++--
> > 6 files changed, 34 insertions(+), 40 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> > b/drivers/gpu/drm/i915/display/intel_display.c
> > index 53dc310a5f6d..dda43e3dcdbf 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > @@ -13393,14 +13393,13 @@ static void verify_wm_state(struct
> > intel_crtc *crtc,
> > struct skl_hw_state {
> > struct skl_ddb_entry ddb_y[I915_MAX_PLANES];
> > struct skl_ddb_entry ddb_uv[I915_MAX_PLANES];
> > - struct skl_ddb_allocation ddb;
> > struct skl_pipe_wm wm;
> > } *hw;
> > - struct skl_ddb_allocation *sw_ddb;
> > struct skl_pipe_wm *sw_wm;
> > struct skl_ddb_entry *hw_ddb_entry, *sw_ddb_entry;
> > const enum pipe pipe = crtc->pipe;
> > int plane, level, max_level = ilk_wm_max_level(dev_priv);
> > + u8 hw_enabled_slices;
> >
> > if (INTEL_GEN(dev_priv) < 9 || !new_crtc_state->hw.active)
> > return;
> > @@ -13414,14 +13413,13 @@ static void verify_wm_state(struct
> > intel_crtc *crtc,
> >
> > skl_pipe_ddb_get_hw_state(crtc, hw->ddb_y, hw->ddb_uv);
> >
> > - skl_ddb_get_hw_state(dev_priv, &hw->ddb);
> > - sw_ddb = &dev_priv->wm.skl_hw.ddb;
> > + hw_enabled_slices = intel_enabled_dbuf_slices_num(dev_priv);
> >
> > if (INTEL_GEN(dev_priv) >= 11 &&
> > - hw->ddb.enabled_slices != sw_ddb->enabled_slices)
> > + hw_enabled_slices != dev_priv->enabled_slices)
> > DRM_ERROR("mismatch in DBUF Slices (expected %u, got
> > %u)\n",
> > - sw_ddb->enabled_slices,
> > - hw->ddb.enabled_slices);
> > + dev_priv->enabled_slices,
> > + hw_enabled_slices);
> >
> > /* planes */
> > for_each_universal_plane(dev_priv, pipe, plane) {
> > @@ -14647,8 +14645,8 @@ static void
> > skl_commit_modeset_enables(struct intel_atomic_state *state)
> > unsigned int updated = 0;
> > bool progress;
> > int i;
> > - u8 hw_enabled_slices = dev_priv->wm.skl_hw.ddb.enabled_slices;
> > - u8 required_slices = state->wm_results.ddb.enabled_slices;
> > + u8 hw_enabled_slices = dev_priv->enabled_slices;
> > + u8 required_slices = state->enabled_slices;
> > struct skl_ddb_entry entries[I915_MAX_PIPES] = {};
> >
> > for_each_oldnew_intel_crtc_in_state(state, crtc,
> > old_crtc_state, new_crtc_state, i)
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
> > b/drivers/gpu/drm/i915/display/intel_display_power.c
> > index ce1b64f4dd44..4c3ede73e863 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> > @@ -4264,7 +4264,7 @@ static u8 intel_dbuf_max_slices(struct
> > drm_i915_private *dev_priv)
> > void icl_dbuf_slices_update(struct drm_i915_private *dev_priv,
> > u8 req_slices)
> > {
> > - const u8 hw_enabled_slices = dev_priv-
> > >wm.skl_hw.ddb.enabled_slices;
> > + const u8 hw_enabled_slices = dev_priv->enabled_slices;
> > bool ret;
> >
> > if (req_slices > intel_dbuf_max_slices(dev_priv)) {
> > @@ -4281,7 +4281,7 @@ void icl_dbuf_slices_update(struct
> > drm_i915_private *dev_priv,
> > ret = intel_dbuf_slice_set(dev_priv, DBUF_CTL_S2,
> > false);
> >
> > if (ret)
> > - dev_priv->wm.skl_hw.ddb.enabled_slices = req_slices;
> > + dev_priv->enabled_slices = req_slices;
> > }
> >
> > static void icl_dbuf_enable(struct drm_i915_private *dev_priv)
> > @@ -4300,7 +4300,7 @@ static void icl_dbuf_enable(struct
> > drm_i915_private *dev_priv)
> > * FIXME: for now pretend that we only have 1 slice,
> > see
> > * intel_enabled_dbuf_slices_num().
> > */
> > - dev_priv->wm.skl_hw.ddb.enabled_slices = 1;
> > + dev_priv->enabled_slices = 1;
> > }
> >
> > static void icl_dbuf_disable(struct drm_i915_private *dev_priv)
> > @@ -4319,7 +4319,7 @@ static void icl_dbuf_disable(struct
> > drm_i915_private *dev_priv)
> > * FIXME: for now pretend that the first slice is
> > always
> > * enabled, see intel_enabled_dbuf_slices_num().
> > */
> > - dev_priv->wm.skl_hw.ddb.enabled_slices = 1;
> > + dev_priv->enabled_slices = 1;
> > }
> >
> > static void icl_mbus_init(struct drm_i915_private *dev_priv)
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> > b/drivers/gpu/drm/i915/display/intel_display_types.h
> > index 83ea04149b77..5eaeaf487a01 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > @@ -517,6 +517,9 @@ struct intel_atomic_state {
> > /* Gen9+ only */
> > struct skl_ddb_values wm_results;
> >
> > + /* Number of enabled DBuf slices */
> > + u8 enabled_slices;
> > +
> > struct i915_sw_fence commit_ready;
> >
> > struct llist_node freed;
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h
> > b/drivers/gpu/drm/i915/i915_drv.h
> > index fdae5a919bc8..195629a37a61 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -798,13 +798,8 @@ static inline bool skl_ddb_entry_equal(const
> > struct skl_ddb_entry *e1,
> > return false;
> > }
> >
> > -struct skl_ddb_allocation {
> > - u8 enabled_slices; /* GEN11 has configurable 2 slices */
> > -};
> > -
> > struct skl_ddb_values {
> > unsigned dirty_pipes;
> > - struct skl_ddb_allocation ddb;
> > };
>
> Seems strange to have a single entry structure (especially one that
> isn't even a "DDB value" as the name implies). Do you kill
> dirty_pipes
> somewhere later in this series? I didn't see it from a quick skim.
Those dirty pipes are going to be nuked in Villes series, I guess then
the whole skl_ddb_values struct will be then removed completely.
I would remove it myself however Villes patches need to land, where
he gets rid of dirty_pipes usage.
>
> >
> > struct skl_wm_level {
> > @@ -1215,6 +1210,8 @@ struct drm_i915_private {
> > bool distrust_bios_wm;
> > } wm;
> >
> > + u8 enabled_slices; /* GEN11 has configurable 2 slices */
>
> Intel hardware has long used the terms "slice" and "subslice" for the
> way EUs are grouped on the GT side. Now that this is pulled out from
> the substructs that gave it additional context, I think we need to
> rename this to something like 'enabled_dbuf_slices' to avoid
> confusion
> with the more widespread meaning of the word 'slice.' Same for
> intel_atomic_state farther up.
Absolutely agree. I was just a bit confused as I have also
num_supported_dbuf_slices in dev_info, which indicates how much we
theoretically support, which is now named properly, what made
me think that I've renamed that one already..
However now probably we will have also "enabled_dbuf_slices_mask" here.
>
> > +
> > struct dram_info {
> > bool valid;
> > bool is_16gb_dimm;
> > diff --git a/drivers/gpu/drm/i915/intel_pm.c
> > b/drivers/gpu/drm/i915/intel_pm.c
> > index 5aad9d49a528..a93b4385de4b 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > @@ -3599,7 +3599,7 @@ bool ilk_disable_lp_wm(struct drm_device
> > *dev)
> > return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL);
> > }
> >
> > -static u8 intel_enabled_dbuf_slices_num(struct drm_i915_private
> > *dev_priv)
> > +u8 intel_enabled_dbuf_slices_num(struct drm_i915_private
> > *dev_priv)
> > {
> > u8 enabled_slices;
> >
> > @@ -3822,9 +3822,10 @@ bool intel_can_enable_sagv(struct
> > intel_atomic_state *state)
> > static u16 intel_get_ddb_size(struct drm_i915_private *dev_priv,
> > const struct intel_crtc_state
> > *crtc_state,
> > const u64 total_data_rate,
> > - const int num_active,
> > - struct skl_ddb_allocation *ddb)
> > + const int num_active)
> > {
> > + struct drm_atomic_state *state = crtc_state->uapi.state;
> > + struct intel_atomic_state *intel_state =
> > to_intel_atomic_state(state);
> > const struct drm_display_mode *adjusted_mode;
> > u64 total_data_bw;
> > u16 ddb_size = INTEL_INFO(dev_priv)->ddb_size;
> > @@ -3846,9 +3847,9 @@ static u16 intel_get_ddb_size(struct
> > drm_i915_private *dev_priv,
> > * - should validate we stay within the hw bandwidth limits
> > */
> > if (0 && (num_active > 1 || total_data_bw >= GBps(12))) {
> > - ddb->enabled_slices = 2;
> > + intel_state->enabled_slices = 2;
> > } else {
> > - ddb->enabled_slices = 1;
> > + intel_state->enabled_slices = 1;
> > ddb_size /= 2;
> > }
> >
> > @@ -3859,7 +3860,6 @@ static void
> > skl_ddb_get_pipe_allocation_limits(struct drm_i915_private
> > *dev_priv,
> > const struct intel_crtc_state
> > *crtc_state,
> > const u64 total_data_rate,
> > - struct skl_ddb_allocation *ddb,
> > struct skl_ddb_entry *alloc, /* out
> > */
> > int *num_active /* out */)
> > {
> > @@ -3885,7 +3885,7 @@ skl_ddb_get_pipe_allocation_limits(struct
> > drm_i915_private *dev_priv,
> > *num_active = hweight8(dev_priv->active_pipes);
> >
> > ddb_size = intel_get_ddb_size(dev_priv, crtc_state,
> > total_data_rate,
> > - *num_active, ddb);
> > + *num_active);
> >
> > /*
> > * If the state doesn't change the active CRTC's or there is no
> > @@ -4046,10 +4046,9 @@ void skl_pipe_ddb_get_hw_state(struct
> > intel_crtc *crtc,
> > intel_display_power_put(dev_priv, power_domain, wakeref);
> > }
> >
> > -void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
> > - struct skl_ddb_allocation *ddb /* out */)
> > +void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv)
> > {
> > - ddb->enabled_slices = intel_enabled_dbuf_slices_num(dev_priv);
> > + dev_priv->enabled_slices =
> > intel_enabled_dbuf_slices_num(dev_priv);
> > }
> >
> > /*
> > @@ -4226,8 +4225,7 @@ icl_get_total_relative_data_rate(struct
> > intel_crtc_state *crtc_state,
> > }
> >
> > static int
> > -skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state,
> > - struct skl_ddb_allocation *ddb /* out */)
> > +skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state)
> > {
> > struct drm_atomic_state *state = crtc_state->uapi.state;
> > struct drm_crtc *crtc = crtc_state->uapi.crtc;
> > @@ -4269,7 +4267,7 @@ skl_allocate_pipe_ddb(struct intel_crtc_state
> > *crtc_state,
> >
> >
> > skl_ddb_get_pipe_allocation_limits(dev_priv, crtc_state,
> > total_data_rate,
> > - ddb, alloc, &num_active);
> > + alloc, &num_active);
> > alloc_size = skl_ddb_entry_size(alloc);
> > if (alloc_size == 0)
> > return 0;
> > @@ -5183,18 +5181,17 @@ skl_ddb_add_affected_planes(const struct
> > intel_crtc_state *old_crtc_state,
> > static int
> > skl_compute_ddb(struct intel_atomic_state *state)
> > {
> > - const struct drm_i915_private *dev_priv = to_i915(state-
> > >base.dev);
> > - struct skl_ddb_allocation *ddb = &state->wm_results.ddb;
> > + struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> > struct intel_crtc_state *old_crtc_state;
> > struct intel_crtc_state *new_crtc_state;
> > struct intel_crtc *crtc;
> > int ret, i;
> >
> > - memcpy(ddb, &dev_priv->wm.skl_hw.ddb, sizeof(*ddb));
> > + state->enabled_slices = dev_priv->enabled_slices;
> >
> > for_each_oldnew_intel_crtc_in_state(state, crtc,
> > old_crtc_state,
> > new_crtc_state, i) {
> > - ret = skl_allocate_pipe_ddb(new_crtc_state, ddb);
> > + ret = skl_allocate_pipe_ddb(new_crtc_state);
> > if (ret)
> > return ret;
> >
> > @@ -5666,11 +5663,10 @@ void skl_pipe_wm_get_hw_state(struct
> > intel_crtc *crtc,
> > void skl_wm_get_hw_state(struct drm_i915_private *dev_priv)
> > {
> > struct skl_ddb_values *hw = &dev_priv->wm.skl_hw;
> > - struct skl_ddb_allocation *ddb = &dev_priv->wm.skl_hw.ddb;
> > struct intel_crtc *crtc;
> > struct intel_crtc_state *crtc_state;
> >
> > - skl_ddb_get_hw_state(dev_priv, ddb);
> > + skl_ddb_get_hw_state(dev_priv);
>
> At this point you might as well replace this with a direct call to
> intel_enabled_dbuf_slices_num() and drop the skl_ddb_get_hw_state()
> completely.
>
> > for_each_intel_crtc(&dev_priv->drm, crtc) {
> > crtc_state = to_intel_crtc_state(crtc->base.state);
> >
> > diff --git a/drivers/gpu/drm/i915/intel_pm.h
> > b/drivers/gpu/drm/i915/intel_pm.h
> > index b579c724b915..4aafae4c8e0d 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.h
> > +++ b/drivers/gpu/drm/i915/intel_pm.h
> > @@ -17,8 +17,8 @@ struct intel_atomic_state;
> > struct intel_crtc;
> > struct intel_crtc_state;
> > struct intel_plane;
> > -struct skl_ddb_allocation;
> > struct skl_ddb_entry;
> > +struct skl_ddb_values;
> > struct skl_pipe_wm;
> > struct skl_wm_level;
> >
> > @@ -33,11 +33,11 @@ void g4x_wm_get_hw_state(struct
> > drm_i915_private *dev_priv);
> > void vlv_wm_get_hw_state(struct drm_i915_private *dev_priv);
> > void ilk_wm_get_hw_state(struct drm_i915_private *dev_priv);
> > void skl_wm_get_hw_state(struct drm_i915_private *dev_priv);
> > +u8 intel_enabled_dbuf_slices_num(struct drm_i915_private
> > *dev_priv);
> > void skl_pipe_ddb_get_hw_state(struct intel_crtc *crtc,
> > struct skl_ddb_entry *ddb_y,
> > struct skl_ddb_entry *ddb_uv);
> > -void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
> > - struct skl_ddb_allocation *ddb /* out */);
> > +void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv);
> > void skl_pipe_wm_get_hw_state(struct intel_crtc *crtc,
> > struct skl_pipe_wm *out);
> > void g4x_wm_sanitize(struct drm_i915_private *dev_priv);
> > --
> > 2.17.1
> >
>
>
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 26+ messages in thread
end of thread, other threads:[~2019-12-13 8:27 UTC | newest]
Thread overview: 26+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-11-29 13:37 [PATCH v7 0/4] Enable second DBuf slice for ICL and TGL Stanislav Lisovskiy
2019-11-29 13:37 ` [Intel-gfx] " Stanislav Lisovskiy
2019-11-29 13:37 ` [PATCH v7 1/4] drm/i915: Remove skl_ddl_allocation struct Stanislav Lisovskiy
2019-11-29 13:37 ` [Intel-gfx] " Stanislav Lisovskiy
2019-12-13 4:22 ` Matt Roper
2019-12-13 6:28 ` Jani Nikula
2019-12-13 8:27 ` Lisovskiy, Stanislav
2019-11-29 13:37 ` [PATCH v7 2/4] drm/i915: Move dbuf slice update to proper place Stanislav Lisovskiy
2019-11-29 13:37 ` [Intel-gfx] " Stanislav Lisovskiy
2019-12-13 4:22 ` Matt Roper
2019-11-29 13:37 ` [PATCH v7 3/4] drm/i915: Manipulate DBuf slices properly Stanislav Lisovskiy
2019-11-29 13:37 ` [Intel-gfx] " Stanislav Lisovskiy
2019-11-29 13:37 ` [PATCH v7 4/4] drm/i915: Correctly map DBUF slices to pipes Stanislav Lisovskiy
2019-11-29 13:37 ` [Intel-gfx] " Stanislav Lisovskiy
2019-11-29 21:10 ` ✓ Fi.CI.BAT: success for Enable second DBuf slice for ICL and TGL (rev3) Patchwork
2019-11-29 21:10 ` [Intel-gfx] " Patchwork
2019-11-30 23:00 ` ✗ Fi.CI.IGT: failure " Patchwork
2019-11-30 23:00 ` [Intel-gfx] " Patchwork
2019-12-03 0:20 ` ✗ Fi.CI.BAT: failure for Enable second DBuf slice for ICL and TGL (rev4) Patchwork
2019-12-03 0:20 ` [Intel-gfx] " Patchwork
2019-12-03 9:22 ` Lisovskiy, Stanislav
2019-12-05 14:34 ` [Intel-gfx] ✓ Fi.CI.BAT: success for Enable second DBuf slice for ICL and TGL (rev5) Patchwork
2019-12-05 18:40 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2019-12-09 7:55 ` Lisovskiy, Stanislav
2019-12-09 8:11 ` Vudum, Lakshminarayana
2019-12-09 8:40 ` Lisovskiy, Stanislav
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.