[PATCH v9 00/15] staging: mt7621-pci: avoid custom pci config read and writes

[PATCH v9 00/15] staging: mt7621-pci: avoid custom pci config read and writes

[Sergio Paracuellos]

This patch series include an attempt to avoid the use of custom
read and writes in driver code and use PCI subsystem common ones.

In order to do this 'map_bus' callback is implemented and also
data structures for driver are included. The regs base address
ranges and data is being readed from device tree and the driver
gets clean a lot of code.

This patchet also removes all legacy PCI code using now PCI_DRIVERS_GENERIC
kernel api.

Changes in v9:
    - PATCH 1: Use 'res' as resources list and void store resources in
      the pcie data struct.
    - PATCH 1: Rewrite 'mt7621_pci_parse_request_of_pci_ranges' to use
      'devm_of_pci_get_host_bridge_resources' and use 'remap' directly
      with the returned 'iobase' address instead of 'devm_pci_remap_iospace' 
      which get into a WARN_ONCE statement because 'PCI_IOBASE' is not
      defined for mips.
    - Other patches rebased and adapted to this changes.

Changes in v8:
    - PATCH 1: don't check 'of_pci_range_to_resource' return value which is not
      being checked for the legacy code.
    - PATCH 1: call 'mt7621_pci_parse_request_of_pci_ranges' 'and setup_cm_memory_region'
      after the port initialization code.
    - PATCH 1: make use of 'pci_host_probe' to avoid code duplication in function
      'mt7621_pcie_register_host'.
    - PATCH 1: set resource limits with no limit for the end in 'ioport_resource' and
      'iomem_resource'. It seems mips needs this to work properly.
    - Other patches rebased and adapted to this changes.

Changes in v7:
    - PATCH 1: Store resources in mt7621_pci data structure.
    - PATCH 1: Change completely function mt7621_pci_parse_request_of_pci_ranges
      to parse resources from ranges manually instead of use the function
      devm_of_pci_get_host_bridge_resources. This is closer to the mips pci legacy
      code.
    - PATCH 1: Create 'mt7621_pcie_request_resources' function to request resources
      parsed from ranges property in the DT. Use pci_add_resource_offset and set them
      manually like the mips pci-legacy code do.
    - PATCH 1: don't delete function setup_cm_memory_region and call it with memory
      resource.
    - Other patches rebased and adapted to this changes.

Changes in v6:
    - Reorder patches to be each patch correct in itself.
    - PATCH 1 adds also Kconfig to do the step from legacy to generic code
    - PATCH 1 remaps io space using devm_pci_remap_iospace for io resource in
      a new function called 'mt7621_pci_parse_request_of_pci_ranges'.
    - Other patches rebased and adapted with this changes.

Changes in v5:
    - Include driver Kconfig file to add compilation depends of PCI_DRIVERS_GENERIC.
      The new added configuration option is CONFIG_PCI_MT7621.
    - Add list_splice_init(&res, &bridge->windows); in PATCH 1 to set windows
      from resources obtanined from devm_request_pci_bus_resources.
    - Move devm_of_pci_get_host_bridge_resources and devm_request_pci_bus_resources
      after the ports initialization legacy code.
    - Add pcie ports 1 and 2 RC registers to device tree. There was only being included
      port RC register for port 0.
    - Review includes and order them alphabetically.

Changes in v4:
    - Rebased onto staging-next.

Changes in v3:
    - Include new patches to delete all RALINK_BASE definition
      dependant code and be able to avoid use of pci_legacy code.
    - use devm_of_pci_get_host_bridge_resources,
      devm_request_pci_bus_resources and pci_scan_root_bus_bridge
      and pci_bus_add_devices

Changes in v2:
    - squash PATCH 1 and PATCH 2 of previous series in only PATCH 1
    - Change name for host structure.
    - Create a new port structure (platform has 3 pcie controllers)
    - Replace the use of pci_generic_config_[read|write]32 in favour
      of pci_generic_config_[read|write] and change map_bus implemen-
      tation for hopefully the right one.

Best regards,
    Sergio Paracuellos

Sergio Paracuellos (15):
  staging: mt7621-pci: use generic kernel pci subsystem read and write
  staging: mt7621-pci: remove dead code derived to not use custom reads
    and writes
  staging: mt7621-pci: add pcie_write and pcie_read helpers
  staging: mt7621-pci: use pcie_[read|write] in [write|read]_config
  staging: mt7621-pci: simplify read_config function
  staging: mt7621-pci: simplify write_config function
  staging: mt7621-pci: remove unused macros
  staging: mt7621-pci: avoid register duplication per controller using
    pcie_[read|write]
  staging: mt7621-pci: review includes putting them in alphabethic order
  staging: mt7621-pci: use pcie_[read|write] in RALINK_PCI_PCICFG_ADDR
    and RALINK_PCI_PCIMSK_ADDR
  staging: mt7621-pci: remove RALINK_PCI_BASE from remaining definitions
  staging: mt7621-pci: use BIT macro in preprocessor definitions
  staging: mt7621-pci: rename RALINK_PCI_CONFIG_DATA_VIRTUAL_REG
    definition
  staging: mt7621-pci: remove remaining pci_legacy dependant code
  staging: mt7621-dts: add pcie controller port registers

 drivers/staging/Kconfig                 |   2 +
 drivers/staging/mt7621-dts/mt7621.dtsi  |   6 +-
 drivers/staging/mt7621-pci/Kconfig      |   7 +
 drivers/staging/mt7621-pci/pci-mt7621.c | 726 ++++++++++++++++----------------
 4 files changed, 372 insertions(+), 369 deletions(-)
 create mode 100644 drivers/staging/mt7621-pci/Kconfig

-- 
2.7.4

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[PATCH v9 01/15] staging: mt7621-pci: use generic kernel pci subsystem read and write

[Sergio Paracuellos]

map_bus callback is called before every .read/.write operation.
Implement it and change custom read write operations for the
pci subsystem generics. Make the probe function to don't use
legacy stuff and request bus resources directly. Get pci register
base and ranges from device tree.
The driver is not using PCI_LEGACY code anymore and shall use the
PCI_DRIVERS_GENERIC option to correct compile it. Add also new
Kconfig file for this controller setting there its correct dependencies.

Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
---
 drivers/staging/Kconfig                 |   2 +
 drivers/staging/mt7621-pci/Kconfig      |   7 ++
 drivers/staging/mt7621-pci/pci-mt7621.c | 195 +++++++++++++++++++++++++++++---
 3 files changed, 187 insertions(+), 17 deletions(-)
 create mode 100644 drivers/staging/mt7621-pci/Kconfig

diff --git a/drivers/staging/Kconfig b/drivers/staging/Kconfig
index 2bce647..732b631 100644
--- a/drivers/staging/Kconfig
+++ b/drivers/staging/Kconfig
@@ -110,6 +110,8 @@ source "drivers/staging/vboxvideo/Kconfig"
 
 source "drivers/staging/pi433/Kconfig"
 
+source "drivers/staging/mt7621-pci/Kconfig"
+
 source "drivers/staging/mt7621-pinctrl/Kconfig"
 
 source "drivers/staging/mt7621-spi/Kconfig"
diff --git a/drivers/staging/mt7621-pci/Kconfig b/drivers/staging/mt7621-pci/Kconfig
new file mode 100644
index 0000000..d335338
--- /dev/null
+++ b/drivers/staging/mt7621-pci/Kconfig
@@ -0,0 +1,7 @@
+config PCI_MT7621
+	tristate "MediaTek MT7621 PCI Controller"
+	depends on RALINK
+	select PCI_DRIVERS_GENERIC
+	help
+	  This selects a driver for the MediaTek MT7621 PCI Controller.
+
diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c b/drivers/staging/mt7621-pci/pci-mt7621.c
index 650e49b..fb2618a 100644
--- a/drivers/staging/mt7621-pci/pci-mt7621.c
+++ b/drivers/staging/mt7621-pci/pci-mt7621.c
@@ -53,11 +53,16 @@
 #include <linux/delay.h>
 #include <linux/of.h>
 #include <linux/of_pci.h>
+#include <linux/of_platform.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
 #include <linux/platform_device.h>
 
 #include <ralink_regs.h>
 #include <mt7621.h>
 
+#include "../../pci/pci.h"
+
 /*
  * These functions and structures provide the BIOS scan and mapping of the PCI
  * devices.
@@ -178,6 +183,32 @@ static int pcie_link_status = 0;
 #define PCI_ACCESS_WRITE_2 4
 #define PCI_ACCESS_WRITE_4 5
 
+/**
+ * struct mt7621_pcie_port - PCIe port information
+ * @base: IO mapped register base
+ * @list: port list
+ * @pcie: pointer to PCIe host info
+ * @reset: pointer to port reset control
+ */
+struct mt7621_pcie_port {
+	void __iomem *base;
+	struct list_head list;
+	struct mt7621_pcie *pcie;
+	struct reset_control *reset;
+};
+
+/**
+ * struct mt7621_pcie - PCIe host information
+ * @base: IO Mapped Register Base
+ * @dev: Pointer to PCIe device
+ * @ports: pointer to PCIe port information
+ */
+struct mt7621_pcie {
+	void __iomem *base;
+	struct device *dev;
+	struct list_head ports;
+};
+
 static inline u32 mt7621_pci_get_cfgaddr(unsigned int bus, unsigned int slot,
 					 unsigned int func, unsigned int where)
 {
@@ -297,17 +328,22 @@ pci_config_write(struct pci_bus *bus, unsigned int devfn, int where, int size, u
 	}
 }
 
-struct pci_ops mt7621_pci_ops = {
-	.read		= pci_config_read,
-	.write		= pci_config_write,
-};
+static void __iomem *mt7621_pcie_map_bus(struct pci_bus *bus,
+					 unsigned int devfn, int where)
+{
+	struct mt7621_pcie *pcie = bus->sysdata;
+	u32 address = mt7621_pci_get_cfgaddr(bus->number, PCI_SLOT(devfn),
+					     PCI_FUNC(devfn), where);
+
+	writel(address, pcie->base + RALINK_PCI_CONFIG_ADDR);
+
+	return pcie->base + RALINK_PCI_CONFIG_DATA_VIRTUAL_REG + (where & 3);
+}
 
-static struct resource mt7621_res_pci_mem1;
-static struct resource mt7621_res_pci_io1;
-static struct pci_controller mt7621_controller = {
-	.pci_ops	= &mt7621_pci_ops,
-	.mem_resource	= &mt7621_res_pci_mem1,
-	.io_resource	= &mt7621_res_pci_io1,
+struct pci_ops mt7621_pci_ops = {
+	.map_bus	= mt7621_pcie_map_bus,
+	.read		= pci_generic_config_read,
+	.write		= pci_generic_config_write,
 };
 
 static void
@@ -463,9 +499,10 @@ set_phy_for_ssc(void)
 	set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x000),  4, 1, 0x00);	// rg_pe1_frc_phy_en	//Force Port 0 disable control
 }
 
-void setup_cm_memory_region(struct resource *mem_resource)
+static void setup_cm_memory_region(struct resource *mem_resource)
 {
 	resource_size_t mask;
+
 	if (mips_cps_numiocu(0)) {
 		/* FIXME: hardware doesn't accept mask values with 1s after
 		 * 0s (e.g. 0xffef), so it would be great to warn if that's
@@ -480,14 +517,130 @@ void setup_cm_memory_region(struct resource *mem_resource)
 	}
 }
 
+static int mt7621_pci_parse_request_of_pci_ranges(struct mt7621_pcie *pcie,
+						  struct list_head *res)
+{
+	struct device *dev = pcie->dev;
+	int err;
+	u32 size;
+	resource_size_t iobase;
+	struct resource_entry *win, *tmp;
+
+	err = devm_of_pci_get_host_bridge_resources(dev, 0, 0xff, res, &iobase);
+	if (err) {
+		dev_err(dev, "Getting bridge resources failed\n");
+		return err;
+	}
+
+	err = devm_request_pci_bus_resources(dev, res);
+	if (err)
+		return err;
+
+	resource_list_for_each_entry_safe(win, tmp, res) {
+		struct resource *res = win->res;
+
+		switch (resource_type(res)) {
+		case IORESOURCE_IO:
+			size = res->end - res->start + 1;
+			ioremap(iobase, size);
+			/*
+			 * This should be the way to go but PCI_IOBASE
+			 * is not defined for mips so the call to this
+			 * function ends up in a call to 'pci_remap_iospace'
+			 * which expects PCI_IOBASE to be defined to don't
+			 * get into 'else' and the WARN_ONCE statement.
+			 */
+			/* err = devm_pci_remap_iospace(dev, res, iobase);
+			if (err) {
+				dev_warn(dev, "error %d: failed to map resource %pR\n",
+					 err, res);
+				resource_list_destroy_entry(win);
+			}*/
+			break;
+		case IORESOURCE_MEM:
+			setup_cm_memory_region(res);
+			break;
+		}
+	}
+
+	return 0;
+}
+
+static int mt7621_pcie_parse_dt(struct mt7621_pcie *pcie)
+{
+	struct device *dev = pcie->dev;
+	struct device_node *node = dev->of_node;
+	struct resource regs;
+	const char *type;
+	int err;
+
+	type = of_get_property(node, "device_type", NULL);
+	if (!type || strcmp(type, "pci") != 0) {
+		dev_err(dev, "invalid \"device_type\" %s\n", type);
+		return -EINVAL;
+	}
+
+	err = of_address_to_resource(node, 0, &regs);
+	if (err) {
+		dev_err(dev, "missing \"reg\" property\n");
+		return err;
+	}
+
+	pcie->base = devm_ioremap_resource(dev, &regs);
+	if (IS_ERR(pcie->base))
+		return PTR_ERR(pcie->base);
+
+	return 0;
+}
+
+static int mt7621_pcie_register_host(struct pci_host_bridge *host,
+				     struct list_head *res)
+{
+	struct mt7621_pcie *pcie = pci_host_bridge_priv(host);
+
+	list_splice_init(res, &host->windows);
+	host->busnr = 0;
+	host->dev.parent = pcie->dev;
+	host->ops = &mt7621_pci_ops;
+	host->map_irq = pcibios_map_irq;
+	host->swizzle_irq = pci_common_swizzle;
+	host->sysdata = pcie;
+
+	return pci_host_probe(host);
+}
+
 static int mt7621_pci_probe(struct platform_device *pdev)
 {
+	struct device *dev = &pdev->dev;
+	struct mt7621_pcie *pcie;
+	struct pci_host_bridge *bridge;
+	int err;
 	unsigned long val = 0;
+	LIST_HEAD(res);
+
+	if (!dev->of_node)
+		return -ENODEV;
+
+	bridge = devm_pci_alloc_host_bridge(dev, sizeof(*pcie));
+	if (!bridge)
+		return -ENODEV;
+
+	pcie = pci_host_bridge_priv(bridge);
+	pcie->dev = dev;
+	platform_set_drvdata(pdev, pcie);
+	INIT_LIST_HEAD(&pcie->ports);
+
+	err = mt7621_pcie_parse_dt(pcie);
+	if (err) {
+		dev_err(dev, "Parsing DT failed\n");
+		return err;
+	}
 
+	/* set resources limits */
 	iomem_resource.start = 0;
-	iomem_resource.end = ~0;
+	iomem_resource.end = ~0UL; /* no limit */
 	ioport_resource.start = 0;
-	ioport_resource.end = ~0;
+	ioport_resource.end = ~0UL; /* no limit */
 
 	val = RALINK_PCIE0_RST;
 	val |= RALINK_PCIE1_RST;
@@ -665,11 +818,19 @@ pcie(2/1/0) link status	pcie2_num	pcie1_num	pcie0_num
 		write_config(0, 0, 0, 0x70c, val);
 	}
 
-	pci_load_of_ranges(&mt7621_controller, pdev->dev.of_node);
-	setup_cm_memory_region(mt7621_controller.mem_resource);
-	register_pci_controller(&mt7621_controller);
-	return 0;
+	err = mt7621_pci_parse_request_of_pci_ranges(pcie, &res);
+	if (err) {
+		dev_err(dev, "Error requesting pci resources from ranges");
+		return err;
+	}
 
+	err = mt7621_pcie_register_host(bridge, &res);
+	if (err) {
+		dev_err(dev, "Error registering host\n");
+		return err;
+	}
+
+	return 0;
 }
 
 int pcibios_plat_dev_init(struct pci_dev *dev)
-- 
2.7.4

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[PATCH v9 02/15] staging: mt7621-pci: remove dead code derived to not use custom reads and writes

[Sergio Paracuellos]

Driver is using now pci subsystem generics reads and writes and requesting
bus resources without using legacy code functions. Because of this there is
a lot of dead code that can be removed.

Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
---
 drivers/staging/mt7621-pci/pci-mt7621.c | 128 --------------------------------
 1 file changed, 128 deletions(-)

diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c b/drivers/staging/mt7621-pci/pci-mt7621.c
index fb2618a..a82fd01 100644
--- a/drivers/staging/mt7621-pci/pci-mt7621.c
+++ b/drivers/staging/mt7621-pci/pci-mt7621.c
@@ -123,15 +123,6 @@
 	*(volatile u32 *)(RALINK_PCI_BASE+(ofs)) = cpu_to_le32(data)
 #define MV_READ(ofs, data)	\
 	*(data) = le32_to_cpu(*(volatile u32 *)(RALINK_PCI_BASE+(ofs)))
-#define MV_WRITE_16(ofs, data)	\
-	*(volatile u16 *)(RALINK_PCI_BASE+(ofs)) = cpu_to_le16(data)
-#define MV_READ_16(ofs, data)	\
-	*(data) = le16_to_cpu(*(volatile u16 *)(RALINK_PCI_BASE+(ofs)))
-
-#define MV_WRITE_8(ofs, data)	\
-	*(volatile u8 *)(RALINK_PCI_BASE+(ofs)) = data
-#define MV_READ_8(ofs, data)	\
-	*(data) = *(volatile u8 *)(RALINK_PCI_BASE+(ofs))
 
 #define RALINK_PCI_MM_MAP_BASE		0x60000000
 #define RALINK_PCI_IO_MAP_BASE		0x1e160000
@@ -176,13 +167,6 @@
 #define MEMORY_BASE 0x0
 static int pcie_link_status = 0;
 
-#define PCI_ACCESS_READ_1  0
-#define PCI_ACCESS_READ_2  1
-#define PCI_ACCESS_READ_4  2
-#define PCI_ACCESS_WRITE_1 3
-#define PCI_ACCESS_WRITE_2 4
-#define PCI_ACCESS_WRITE_4 5
-
 /**
  * struct mt7621_pcie_port - PCIe port information
  * @base: IO mapped register base
@@ -216,118 +200,6 @@ static inline u32 mt7621_pci_get_cfgaddr(unsigned int bus, unsigned int slot,
 		(func << 8) | (where & 0xfc) | 0x80000000;
 }
 
-static int config_access(unsigned char access_type, struct pci_bus *bus,
-			unsigned int devfn, unsigned int where, u32 *data)
-{
-	unsigned int slot = PCI_SLOT(devfn);
-	u8 func = PCI_FUNC(devfn);
-	u32 address_reg, data_reg;
-	unsigned int address;
-
-	address_reg = RALINK_PCI_CONFIG_ADDR;
-	data_reg = RALINK_PCI_CONFIG_DATA_VIRTUAL_REG;
-
-	address = mt7621_pci_get_cfgaddr(bus->number, slot, func, where);
-
-	MV_WRITE(address_reg, address);
-
-	switch (access_type) {
-	case PCI_ACCESS_WRITE_1:
-		MV_WRITE_8(data_reg+(where&0x3), *data);
-		break;
-	case PCI_ACCESS_WRITE_2:
-		MV_WRITE_16(data_reg+(where&0x3), *data);
-		break;
-	case PCI_ACCESS_WRITE_4:
-		MV_WRITE(data_reg, *data);
-		break;
-	case PCI_ACCESS_READ_1:
-		MV_READ_8(data_reg+(where&0x3), data);
-		break;
-	case PCI_ACCESS_READ_2:
-		MV_READ_16(data_reg+(where&0x3), data);
-		break;
-	case PCI_ACCESS_READ_4:
-		MV_READ(data_reg, data);
-		break;
-	default:
-		printk("no specify access type\n");
-		break;
-	}
-	return 0;
-}
-
-static int
-read_config_byte(struct pci_bus *bus, unsigned int devfn, int where, u8 *val)
-{
-	return config_access(PCI_ACCESS_READ_1, bus, devfn, (unsigned int)where, (u32 *)val);
-}
-
-static int
-read_config_word(struct pci_bus *bus, unsigned int devfn, int where, u16 *val)
-{
-	return config_access(PCI_ACCESS_READ_2, bus, devfn, (unsigned int)where, (u32 *)val);
-}
-
-static int
-read_config_dword(struct pci_bus *bus, unsigned int devfn, int where, u32 *val)
-{
-	return config_access(PCI_ACCESS_READ_4, bus, devfn, (unsigned int)where, (u32 *)val);
-}
-
-static int
-write_config_byte(struct pci_bus *bus, unsigned int devfn, int where, u8 val)
-{
-	if (config_access(PCI_ACCESS_WRITE_1, bus, devfn, (unsigned int)where, (u32 *)&val))
-		return -1;
-
-	return PCIBIOS_SUCCESSFUL;
-}
-
-static int
-write_config_word(struct pci_bus *bus, unsigned int devfn, int where, u16 val)
-{
-	if (config_access(PCI_ACCESS_WRITE_2, bus, devfn, where, (u32 *)&val))
-		return -1;
-
-	return PCIBIOS_SUCCESSFUL;
-}
-
-static int
-write_config_dword(struct pci_bus *bus, unsigned int devfn, int where, u32 val)
-{
-	if (config_access(PCI_ACCESS_WRITE_4, bus, devfn, where, &val))
-		return -1;
-
-	return PCIBIOS_SUCCESSFUL;
-}
-
-static int
-pci_config_read(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val)
-{
-	switch (size) {
-	case 1:
-		return read_config_byte(bus, devfn, where, (u8 *) val);
-	case 2:
-		return read_config_word(bus, devfn, where, (u16 *) val);
-	default:
-		return read_config_dword(bus, devfn, where, val);
-	}
-}
-
-static int
-pci_config_write(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val)
-{
-	switch (size) {
-	case 1:
-		return write_config_byte(bus, devfn, where, (u8) val);
-	case 2:
-		return write_config_word(bus, devfn, where, (u16) val);
-	default:
-		return write_config_dword(bus, devfn, where, val);
-	}
-}
-
 static void __iomem *mt7621_pcie_map_bus(struct pci_bus *bus,
 					 unsigned int devfn, int where)
 {
-- 
2.7.4

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[PATCH v9 03/15] staging: mt7621-pci: add pcie_write and pcie_read helpers

[Sergio Paracuellos]

Introdice this functions to make easier to write/read to/from
an offset relative to base address

Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
---
 drivers/staging/mt7621-pci/pci-mt7621.c | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c b/drivers/staging/mt7621-pci/pci-mt7621.c
index a82fd01..c170cd5 100644
--- a/drivers/staging/mt7621-pci/pci-mt7621.c
+++ b/drivers/staging/mt7621-pci/pci-mt7621.c
@@ -193,6 +193,16 @@ struct mt7621_pcie {
 	struct list_head ports;
 };
 
+static inline u32 pcie_read(struct mt7621_pcie *pcie, u32 reg)
+{
+	return readl(pcie->base + reg);
+}
+
+static inline void pcie_write(struct mt7621_pcie *pcie, u32 val, u32 reg)
+{
+	writel(val, pcie->base + reg);
+}
+
 static inline u32 mt7621_pci_get_cfgaddr(unsigned int bus, unsigned int slot,
 					 unsigned int func, unsigned int where)
 {
-- 
2.7.4

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[PATCH v9 04/15] staging: mt7621-pci: use pcie_[read|write] in [write|read]_config

[Sergio Paracuellos]

Instead of custom macros use pcie_read and pcie_write functions.

Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
---
 drivers/staging/mt7621-pci/pci-mt7621.c | 67 ++++++++++++++++-----------------
 1 file changed, 32 insertions(+), 35 deletions(-)

diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c b/drivers/staging/mt7621-pci/pci-mt7621.c
index c170cd5..d5b939d 100644
--- a/drivers/staging/mt7621-pci/pci-mt7621.c
+++ b/drivers/staging/mt7621-pci/pci-mt7621.c
@@ -229,41 +229,38 @@ struct pci_ops mt7621_pci_ops = {
 };
 
 static void
-read_config(unsigned long bus, unsigned long dev, unsigned long func, unsigned long reg, unsigned long *val)
+read_config(struct mt7621_pcie *pcie,
+	    unsigned long bus, unsigned long dev,
+	    unsigned long func, unsigned long reg, unsigned long *val)
 {
-	u32 address_reg, data_reg, address;
-
-	address_reg = RALINK_PCI_CONFIG_ADDR;
-	data_reg = RALINK_PCI_CONFIG_DATA_VIRTUAL_REG;
-	address = mt7621_pci_get_cfgaddr(bus, dev, func, reg);
-	MV_WRITE(address_reg, address);
-	MV_READ(data_reg, val);
-	return;
+	u32 address = mt7621_pci_get_cfgaddr(bus, dev, func, reg);
+
+	pcie_write(pcie, address, RALINK_PCI_CONFIG_ADDR);
+	*val = pcie_read(pcie, RALINK_PCI_CONFIG_DATA_VIRTUAL_REG);
 }
 
 static void
-write_config(unsigned long bus, unsigned long dev, unsigned long func, unsigned long reg, unsigned long val)
+write_config(struct mt7621_pcie *pcie,
+	     unsigned long bus, unsigned long dev,
+	     unsigned long func, unsigned long reg, unsigned long val)
 {
-	u32 address_reg, data_reg, address;
-
-	address_reg = RALINK_PCI_CONFIG_ADDR;
-	data_reg = RALINK_PCI_CONFIG_DATA_VIRTUAL_REG;
-	address = mt7621_pci_get_cfgaddr(bus, dev, func, reg);
-	MV_WRITE(address_reg, address);
-	MV_WRITE(data_reg, val);
-	return;
+	u32 address = mt7621_pci_get_cfgaddr(bus, dev, func, reg);
+
+	pcie_write(pcie, address, RALINK_PCI_CONFIG_ADDR);
+	pcie_write(pcie, val, RALINK_PCI_CONFIG_DATA_VIRTUAL_REG);
 }
 
 int
 pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
 {
+	struct mt7621_pcie *pcie = dev->bus->sysdata;
 	u16 cmd;
 	u32 val;
 	int irq;
 
 	if (dev->bus->number == 0) {
-		write_config(0, slot, 0, PCI_BASE_ADDRESS_0, MEMORY_BASE);
-		read_config(0, slot, 0, PCI_BASE_ADDRESS_0, (unsigned long *)&val);
+		write_config(pcie, 0, slot, 0, PCI_BASE_ADDRESS_0, MEMORY_BASE);
+		read_config(pcie, 0, slot, 0, PCI_BASE_ADDRESS_0, (unsigned long *)&val);
 		printk("BAR0 at slot %d = %x\n", slot, val);
 	}
 
@@ -549,13 +546,13 @@ static int mt7621_pci_probe(struct platform_device *pdev)
 		bypass_pipe_rst();
 	set_phy_for_ssc();
 
-	read_config(0, 0, 0, 0x70c, &val);
+	read_config(pcie, 0, 0, 0, 0x70c, &val);
 	printk("Port 0 N_FTS = %x\n", (unsigned int)val);
 
-	read_config(0, 1, 0, 0x70c, &val);
+	read_config(pcie, 0, 1, 0, 0x70c, &val);
 	printk("Port 1 N_FTS = %x\n", (unsigned int)val);
 
-	read_config(0, 2, 0, 0x70c, &val);
+	read_config(pcie, 0, 2, 0, 0x70c, &val);
 	printk("Port 2 N_FTS = %x\n", (unsigned int)val);
 
 	rt_sysc_m32(0, RALINK_PCIE_RST, RALINK_RSTCTRL);
@@ -676,28 +673,28 @@ pcie(2/1/0) link status	pcie2_num	pcie1_num	pcie0_num
 
 	switch (pcie_link_status) {
 	case 7:
-		read_config(0, 2, 0, 0x4, &val);
-		write_config(0, 2, 0, 0x4, val|0x4);
-		read_config(0, 2, 0, 0x70c, &val);
+		read_config(pcie, 0, 2, 0, 0x4, &val);
+		write_config(pcie, 0, 2, 0, 0x4, val|0x4);
+		read_config(pcie, 0, 2, 0, 0x70c, &val);
 		val &= ~(0xff)<<8;
 		val |= 0x50<<8;
-		write_config(0, 2, 0, 0x70c, val);
+		write_config(pcie, 0, 2, 0, 0x70c, val);
 	case 3:
 	case 5:
 	case 6:
-		read_config(0, 1, 0, 0x4, &val);
-		write_config(0, 1, 0, 0x4, val|0x4);
-		read_config(0, 1, 0, 0x70c, &val);
+		read_config(pcie, 0, 1, 0, 0x4, &val);
+		write_config(pcie, 0, 1, 0, 0x4, val|0x4);
+		read_config(pcie, 0, 1, 0, 0x70c, &val);
 		val &= ~(0xff)<<8;
 		val |= 0x50<<8;
-		write_config(0, 1, 0, 0x70c, val);
+		write_config(pcie, 0, 1, 0, 0x70c, val);
 	default:
-		read_config(0, 0, 0, 0x4, &val);
-		write_config(0, 0, 0, 0x4, val|0x4); //bus master enable
-		read_config(0, 0, 0, 0x70c, &val);
+		read_config(pcie, 0, 0, 0, 0x4, &val);
+		write_config(pcie, 0, 0, 0, 0x4, val|0x4); //bus master enable
+		read_config(pcie, 0, 0, 0, 0x70c, &val);
 		val &= ~(0xff)<<8;
 		val |= 0x50<<8;
-		write_config(0, 0, 0, 0x70c, val);
+		write_config(pcie, 0, 0, 0, 0x70c, val);
 	}
 
 	err = mt7621_pci_parse_request_of_pci_ranges(pcie, &res);
-- 
2.7.4

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[PATCH v9 05/15] staging: mt7621-pci: simplify read_config function

[Sergio Paracuellos]

read_config function is always called with bus and func
being 0. Avoid those params and just use 0 inside the
function. Return readed value instead pass a reference
parameter.

Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
---
 drivers/staging/mt7621-pci/pci-mt7621.c | 32 +++++++++++++++-----------------
 1 file changed, 15 insertions(+), 17 deletions(-)

diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c b/drivers/staging/mt7621-pci/pci-mt7621.c
index d5b939d..c724165 100644
--- a/drivers/staging/mt7621-pci/pci-mt7621.c
+++ b/drivers/staging/mt7621-pci/pci-mt7621.c
@@ -228,15 +228,13 @@ struct pci_ops mt7621_pci_ops = {
 	.write		= pci_generic_config_write,
 };
 
-static void
-read_config(struct mt7621_pcie *pcie,
-	    unsigned long bus, unsigned long dev,
-	    unsigned long func, unsigned long reg, unsigned long *val)
+static u32
+read_config(struct mt7621_pcie *pcie, unsigned int dev, u32 reg)
 {
-	u32 address = mt7621_pci_get_cfgaddr(bus, dev, func, reg);
+	u32 address = mt7621_pci_get_cfgaddr(0, dev, 0, reg);
 
 	pcie_write(pcie, address, RALINK_PCI_CONFIG_ADDR);
-	*val = pcie_read(pcie, RALINK_PCI_CONFIG_DATA_VIRTUAL_REG);
+	return pcie_read(pcie, RALINK_PCI_CONFIG_DATA_VIRTUAL_REG);
 }
 
 static void
@@ -260,7 +258,7 @@ pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
 
 	if (dev->bus->number == 0) {
 		write_config(pcie, 0, slot, 0, PCI_BASE_ADDRESS_0, MEMORY_BASE);
-		read_config(pcie, 0, slot, 0, PCI_BASE_ADDRESS_0, (unsigned long *)&val);
+		val = read_config(pcie, slot, PCI_BASE_ADDRESS_0);
 		printk("BAR0 at slot %d = %x\n", slot, val);
 	}
 
@@ -494,7 +492,7 @@ static int mt7621_pci_probe(struct platform_device *pdev)
 	struct mt7621_pcie *pcie;
 	struct pci_host_bridge *bridge;
 	int err;
-	unsigned long val = 0;
+	u32 val = 0;
 	LIST_HEAD(res);
 
 	if (!dev->of_node)
@@ -546,13 +544,13 @@ static int mt7621_pci_probe(struct platform_device *pdev)
 		bypass_pipe_rst();
 	set_phy_for_ssc();
 
-	read_config(pcie, 0, 0, 0, 0x70c, &val);
+	val = read_config(pcie, 0, 0x70c);
 	printk("Port 0 N_FTS = %x\n", (unsigned int)val);
 
-	read_config(pcie, 0, 1, 0, 0x70c, &val);
+	val = read_config(pcie, 1, 0x70c);
 	printk("Port 1 N_FTS = %x\n", (unsigned int)val);
 
-	read_config(pcie, 0, 2, 0, 0x70c, &val);
+	val = read_config(pcie, 2, 0x70c);
 	printk("Port 2 N_FTS = %x\n", (unsigned int)val);
 
 	rt_sysc_m32(0, RALINK_PCIE_RST, RALINK_RSTCTRL);
@@ -673,25 +671,25 @@ pcie(2/1/0) link status	pcie2_num	pcie1_num	pcie0_num
 
 	switch (pcie_link_status) {
 	case 7:
-		read_config(pcie, 0, 2, 0, 0x4, &val);
+		val = read_config(pcie, 2, 0x4);
 		write_config(pcie, 0, 2, 0, 0x4, val|0x4);
-		read_config(pcie, 0, 2, 0, 0x70c, &val);
+		val = read_config(pcie, 2, 0x70c);
 		val &= ~(0xff)<<8;
 		val |= 0x50<<8;
 		write_config(pcie, 0, 2, 0, 0x70c, val);
 	case 3:
 	case 5:
 	case 6:
-		read_config(pcie, 0, 1, 0, 0x4, &val);
+		val = read_config(pcie, 1, 0x4);
 		write_config(pcie, 0, 1, 0, 0x4, val|0x4);
-		read_config(pcie, 0, 1, 0, 0x70c, &val);
+		val = read_config(pcie, 1, 0x70c);
 		val &= ~(0xff)<<8;
 		val |= 0x50<<8;
 		write_config(pcie, 0, 1, 0, 0x70c, val);
 	default:
-		read_config(pcie, 0, 0, 0, 0x4, &val);
+		val = read_config(pcie, 0, 0x4);
 		write_config(pcie, 0, 0, 0, 0x4, val|0x4); //bus master enable
-		read_config(pcie, 0, 0, 0, 0x70c, &val);
+		val = read_config(pcie, 0, 0x70c);
 		val &= ~(0xff)<<8;
 		val |= 0x50<<8;
 		write_config(pcie, 0, 0, 0, 0x70c, val);
-- 
2.7.4

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[PATCH v9 06/15] staging: mt7621-pci: simplify write_config function

[Sergio Paracuellos]

write_config function is always called with bus and func
being 0. Avoid those params and just use 0 inside the
function. Review parameter types changing for more proper
ones.

Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
---
 drivers/staging/mt7621-pci/pci-mt7621.c | 20 +++++++++-----------
 1 file changed, 9 insertions(+), 11 deletions(-)

diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c b/drivers/staging/mt7621-pci/pci-mt7621.c
index c724165..aa95457 100644
--- a/drivers/staging/mt7621-pci/pci-mt7621.c
+++ b/drivers/staging/mt7621-pci/pci-mt7621.c
@@ -238,11 +238,9 @@ read_config(struct mt7621_pcie *pcie, unsigned int dev, u32 reg)
 }
 
 static void
-write_config(struct mt7621_pcie *pcie,
-	     unsigned long bus, unsigned long dev,
-	     unsigned long func, unsigned long reg, unsigned long val)
+write_config(struct mt7621_pcie *pcie, unsigned int dev, u32 reg, u32 val)
 {
-	u32 address = mt7621_pci_get_cfgaddr(bus, dev, func, reg);
+	u32 address = mt7621_pci_get_cfgaddr(0, dev, 0, reg);
 
 	pcie_write(pcie, address, RALINK_PCI_CONFIG_ADDR);
 	pcie_write(pcie, val, RALINK_PCI_CONFIG_DATA_VIRTUAL_REG);
@@ -257,7 +255,7 @@ pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
 	int irq;
 
 	if (dev->bus->number == 0) {
-		write_config(pcie, 0, slot, 0, PCI_BASE_ADDRESS_0, MEMORY_BASE);
+		write_config(pcie, slot, PCI_BASE_ADDRESS_0, MEMORY_BASE);
 		val = read_config(pcie, slot, PCI_BASE_ADDRESS_0);
 		printk("BAR0 at slot %d = %x\n", slot, val);
 	}
@@ -672,27 +670,27 @@ pcie(2/1/0) link status	pcie2_num	pcie1_num	pcie0_num
 	switch (pcie_link_status) {
 	case 7:
 		val = read_config(pcie, 2, 0x4);
-		write_config(pcie, 0, 2, 0, 0x4, val|0x4);
+		write_config(pcie, 2, 0x4, val|0x4);
 		val = read_config(pcie, 2, 0x70c);
 		val &= ~(0xff)<<8;
 		val |= 0x50<<8;
-		write_config(pcie, 0, 2, 0, 0x70c, val);
+		write_config(pcie, 2, 0x70c, val);
 	case 3:
 	case 5:
 	case 6:
 		val = read_config(pcie, 1, 0x4);
-		write_config(pcie, 0, 1, 0, 0x4, val|0x4);
+		write_config(pcie, 1, 0x4, val|0x4);
 		val = read_config(pcie, 1, 0x70c);
 		val &= ~(0xff)<<8;
 		val |= 0x50<<8;
-		write_config(pcie, 0, 1, 0, 0x70c, val);
+		write_config(pcie, 1, 0x70c, val);
 	default:
 		val = read_config(pcie, 0, 0x4);
-		write_config(pcie, 0, 0, 0, 0x4, val|0x4); //bus master enable
+		write_config(pcie, 0, 0x4, val|0x4); //bus master enable
 		val = read_config(pcie, 0, 0x70c);
 		val &= ~(0xff)<<8;
 		val |= 0x50<<8;
-		write_config(pcie, 0, 0, 0, 0x70c, val);
+		write_config(pcie, 0, 0x70c, val);
 	}
 
 	err = mt7621_pci_parse_request_of_pci_ranges(pcie, &res);
-- 
2.7.4

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[PATCH v9 07/15] staging: mt7621-pci: remove unused macros

[Sergio Paracuellos]

There some macros that are not being used. Remove them.

Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
---
 drivers/staging/mt7621-pci/pci-mt7621.c | 24 +-----------------------
 1 file changed, 1 insertion(+), 23 deletions(-)

diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c b/drivers/staging/mt7621-pci/pci-mt7621.c
index aa95457..65c573c 100644
--- a/drivers/staging/mt7621-pci/pci-mt7621.c
+++ b/drivers/staging/mt7621-pci/pci-mt7621.c
@@ -84,7 +84,6 @@
 #define RALINK_PCI_PCIMSK_ADDR		*(volatile u32 *)(RALINK_PCI_BASE + 0x000C)
 #define RALINK_PCI_BASE	0xBE140000
 
-#define RALINK_PCIEPHY_P0P1_CTL_OFFSET	(RALINK_PCI_BASE + 0x9000)
 #define RT6855_PCIE0_OFFSET		0x2000
 #define RT6855_PCIE1_OFFSET		0x3000
 #define RT6855_PCIE2_OFFSET		0x4000
@@ -95,8 +94,6 @@
 #define RALINK_PCI0_CLASS		*(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0034)
 #define RALINK_PCI0_SUBID		*(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0038)
 #define RALINK_PCI0_STATUS		*(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0050)
-#define RALINK_PCI0_DERR		*(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0060)
-#define RALINK_PCI0_ECRC		*(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0064)
 
 #define RALINK_PCI1_BAR0SETUP_ADDR	*(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0010)
 #define RALINK_PCI1_IMBASEBAR0_ADDR	*(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0018)
@@ -104,8 +101,6 @@
 #define RALINK_PCI1_CLASS		*(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0034)
 #define RALINK_PCI1_SUBID		*(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0038)
 #define RALINK_PCI1_STATUS		*(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0050)
-#define RALINK_PCI1_DERR		*(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0060)
-#define RALINK_PCI1_ECRC		*(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0064)
 
 #define RALINK_PCI2_BAR0SETUP_ADDR	*(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0010)
 #define RALINK_PCI2_IMBASEBAR0_ADDR	*(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0018)
@@ -113,17 +108,10 @@
 #define RALINK_PCI2_CLASS		*(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0034)
 #define RALINK_PCI2_SUBID		*(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0038)
 #define RALINK_PCI2_STATUS		*(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0050)
-#define RALINK_PCI2_DERR		*(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0060)
-#define RALINK_PCI2_ECRC		*(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0064)
 
 #define RALINK_PCIEPHY_P0P1_CTL_OFFSET	(RALINK_PCI_BASE + 0x9000)
 #define RALINK_PCIEPHY_P2_CTL_OFFSET	(RALINK_PCI_BASE + 0xA000)
 
-#define MV_WRITE(ofs, data)	\
-	*(volatile u32 *)(RALINK_PCI_BASE+(ofs)) = cpu_to_le32(data)
-#define MV_READ(ofs, data)	\
-	*(data) = le32_to_cpu(*(volatile u32 *)(RALINK_PCI_BASE+(ofs)))
-
 #define RALINK_PCI_MM_MAP_BASE		0x60000000
 #define RALINK_PCI_IO_MAP_BASE		0x1e160000
 
@@ -141,28 +129,18 @@
 		else							\
 			rt_sysc_m32(0, val, RALINK_RSTCTRL);		\
 	} while (0)
+
 #define RALINK_CLKCFG1			0x30
 #define RALINK_RSTCTRL			0x34
 #define RALINK_GPIOMODE			0x60
 #define RALINK_PCIE_CLK_GEN		0x7c
 #define RALINK_PCIE_CLK_GEN1		0x80
-#define PPLL_CFG1			0x9c
-#define PPLL_DRV			0xa0
-/* SYSC_REG_SYSTEM_CONFIG1 bits */
-#define RALINK_PCI_HOST_MODE_EN		(1<<7)
-#define RALINK_PCIE_RC_MODE_EN		(1<<8)
 //RALINK_RSTCTRL bit
 #define RALINK_PCIE_RST			(1<<23)
 #define RALINK_PCI_RST			(1<<24)
 //RALINK_CLKCFG1 bit
 #define RALINK_PCI_CLK_EN		(1<<19)
 #define RALINK_PCIE_CLK_EN		(1<<21)
-//RALINK_GPIOMODE bit
-#define PCI_SLOTx2			(1<<11)
-#define PCI_SLOTx1			(2<<11)
-//MTK PCIE PLL bit
-#define PDRV_SW_SET			(1<<31)
-#define LC_CKDRVPD_			(1<<19)
 
 #define MEMORY_BASE 0x0
 static int pcie_link_status = 0;
-- 
2.7.4

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[PATCH v9 08/15] staging: mt7621-pci: avoid register duplication per controller using pcie_[read|write]

[Sergio Paracuellos]

Use pcie_[read|write] fucntions to read and write controller registers.
Define those only by offset and pass controller offset + register offset
relative to base address to functions.

Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
---
 drivers/staging/mt7621-pci/pci-mt7621.c | 70 ++++++++++++++++-----------------
 1 file changed, 34 insertions(+), 36 deletions(-)

diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c b/drivers/staging/mt7621-pci/pci-mt7621.c
index 65c573c..2533dfc 100644
--- a/drivers/staging/mt7621-pci/pci-mt7621.c
+++ b/drivers/staging/mt7621-pci/pci-mt7621.c
@@ -74,8 +74,8 @@
 
 #define RALINK_PCI_CONFIG_ADDR		0x20
 #define RALINK_PCI_CONFIG_DATA_VIRTUAL_REG	0x24
-#define RALINK_PCI_MEMBASE		*(volatile u32 *)(RALINK_PCI_BASE + 0x0028)
-#define RALINK_PCI_IOBASE		*(volatile u32 *)(RALINK_PCI_BASE + 0x002C)
+#define RALINK_PCI_MEMBASE		0x28
+#define RALINK_PCI_IOBASE		0x2C
 #define RALINK_PCIE0_RST		(1<<24)
 #define RALINK_PCIE1_RST		(1<<25)
 #define RALINK_PCIE2_RST		(1<<26)
@@ -88,26 +88,12 @@
 #define RT6855_PCIE1_OFFSET		0x3000
 #define RT6855_PCIE2_OFFSET		0x4000
 
-#define RALINK_PCI0_BAR0SETUP_ADDR	*(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0010)
-#define RALINK_PCI0_IMBASEBAR0_ADDR	*(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0018)
-#define RALINK_PCI0_ID			*(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0030)
-#define RALINK_PCI0_CLASS		*(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0034)
-#define RALINK_PCI0_SUBID		*(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0038)
-#define RALINK_PCI0_STATUS		*(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0050)
-
-#define RALINK_PCI1_BAR0SETUP_ADDR	*(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0010)
-#define RALINK_PCI1_IMBASEBAR0_ADDR	*(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0018)
-#define RALINK_PCI1_ID			*(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0030)
-#define RALINK_PCI1_CLASS		*(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0034)
-#define RALINK_PCI1_SUBID		*(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0038)
-#define RALINK_PCI1_STATUS		*(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0050)
-
-#define RALINK_PCI2_BAR0SETUP_ADDR	*(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0010)
-#define RALINK_PCI2_IMBASEBAR0_ADDR	*(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0018)
-#define RALINK_PCI2_ID			*(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0030)
-#define RALINK_PCI2_CLASS		*(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0034)
-#define RALINK_PCI2_SUBID		*(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0038)
-#define RALINK_PCI2_STATUS		*(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0050)
+#define RALINK_PCI_BAR0SETUP_ADDR	0x0010
+#define RALINK_PCI_IMBASEBAR0_ADDR	0x0018
+#define RALINK_PCI_ID			0x0030
+#define RALINK_PCI_CLASS		0x0034
+#define RALINK_PCI_SUBID		0x0038
+#define RALINK_PCI_STATUS		0x0050
 
 #define RALINK_PCIEPHY_P0P1_CTL_OFFSET	(RALINK_PCI_BASE + 0x9000)
 #define RALINK_PCIEPHY_P2_CTL_OFFSET	(RALINK_PCI_BASE + 0xA000)
@@ -543,7 +529,7 @@ static int mt7621_pci_probe(struct platform_device *pdev)
 	*(unsigned int *)(0xbe000620) |= 0x1<<19 | 0x1<<8 | 0x1<<7;		// set DATA
 	mdelay(1000);
 
-	if ((RALINK_PCI0_STATUS & 0x1) == 0) {
+	if ((pcie_read(pcie, RT6855_PCIE0_OFFSET + RALINK_PCI_STATUS) & 0x1) == 0) {
 		printk("PCIE0 no card, disable it(RST&CLK)\n");
 		ASSERT_SYSRST_PCIE(RALINK_PCIE0_RST);
 		rt_sysc_m32(RALINK_PCIE0_CLK_EN, 0, RALINK_CLKCFG1);
@@ -553,7 +539,7 @@ static int mt7621_pci_probe(struct platform_device *pdev)
 		RALINK_PCI_PCIMSK_ADDR |= (1<<20); // enable pcie1 interrupt
 	}
 
-	if ((RALINK_PCI1_STATUS & 0x1) == 0) {
+	if ((pcie_read(pcie, RT6855_PCIE1_OFFSET + RALINK_PCI_STATUS) & 0x1) == 0) {
 		printk("PCIE1 no card, disable it(RST&CLK)\n");
 		ASSERT_SYSRST_PCIE(RALINK_PCIE1_RST);
 		rt_sysc_m32(RALINK_PCIE1_CLK_EN, 0, RALINK_CLKCFG1);
@@ -563,7 +549,7 @@ static int mt7621_pci_probe(struct platform_device *pdev)
 		RALINK_PCI_PCIMSK_ADDR |= (1<<21); // enable pcie1 interrupt
 	}
 
-	if ((RALINK_PCI2_STATUS & 0x1) == 0) {
+	if ((pcie_read(pcie, RT6855_PCIE2_OFFSET + RALINK_PCI_STATUS) & 0x1) == 0) {
 		printk("PCIE2 no card, disable it(RST&CLK)\n");
 		ASSERT_SYSRST_PCIE(RALINK_PCIE2_RST);
 		rt_sysc_m32(RALINK_PCIE2_CLK_EN, 0, RALINK_CLKCFG1);
@@ -618,30 +604,42 @@ pcie(2/1/0) link status	pcie2_num	pcie1_num	pcie0_num
 	ioport_resource.end = mt7621_res_pci_io1.end;
 */
 
-	RALINK_PCI_MEMBASE = 0xffffffff; //RALINK_PCI_MM_MAP_BASE;
-	RALINK_PCI_IOBASE = RALINK_PCI_IO_MAP_BASE;
+	pcie_write(pcie, 0xffffffff, RALINK_PCI_MEMBASE);
+	pcie_write(pcie, RALINK_PCI_IO_MAP_BASE, RALINK_PCI_IOBASE);
 
 	//PCIe0
 	if ((pcie_link_status & 0x1) != 0) {
-		RALINK_PCI0_BAR0SETUP_ADDR = 0x7FFF0001;	//open 7FFF:2G; ENABLE
-		RALINK_PCI0_IMBASEBAR0_ADDR = MEMORY_BASE;
-		RALINK_PCI0_CLASS = 0x06040001;
+		/* open 7FFF:2G; ENABLE */
+		pcie_write(pcie, 0x7FFF0001,
+			   RT6855_PCIE0_OFFSET + RALINK_PCI_BAR0SETUP_ADDR);
+		pcie_write(pcie, MEMORY_BASE,
+			   RT6855_PCIE0_OFFSET + RALINK_PCI_IMBASEBAR0_ADDR);
+		pcie_write(pcie, 0x06040001,
+			   RT6855_PCIE0_OFFSET + RALINK_PCI_CLASS);
 		printk("PCIE0 enabled\n");
 	}
 
 	//PCIe1
 	if ((pcie_link_status & 0x2) != 0) {
-		RALINK_PCI1_BAR0SETUP_ADDR = 0x7FFF0001;	//open 7FFF:2G; ENABLE
-		RALINK_PCI1_IMBASEBAR0_ADDR = MEMORY_BASE;
-		RALINK_PCI1_CLASS = 0x06040001;
+		/* open 7FFF:2G; ENABLE */
+		pcie_write(pcie, 0x7FFF0001,
+			   RT6855_PCIE1_OFFSET + RALINK_PCI_BAR0SETUP_ADDR);
+		pcie_write(pcie, MEMORY_BASE,
+			   RT6855_PCIE1_OFFSET + RALINK_PCI_IMBASEBAR0_ADDR);
+		pcie_write(pcie, 0x06040001,
+			   RT6855_PCIE1_OFFSET + RALINK_PCI_CLASS);
 		printk("PCIE1 enabled\n");
 	}
 
 	//PCIe2
 	if ((pcie_link_status & 0x4) != 0) {
-		RALINK_PCI2_BAR0SETUP_ADDR = 0x7FFF0001;	//open 7FFF:2G; ENABLE
-		RALINK_PCI2_IMBASEBAR0_ADDR = MEMORY_BASE;
-		RALINK_PCI2_CLASS = 0x06040001;
+		/* open 7FFF:2G; ENABLE */
+		pcie_write(pcie, 0x7FFF0001,
+			   RT6855_PCIE2_OFFSET + RALINK_PCI_BAR0SETUP_ADDR);
+		pcie_write(pcie, MEMORY_BASE,
+			   RT6855_PCIE2_OFFSET + RALINK_PCI_IMBASEBAR0_ADDR);
+		pcie_write(pcie, 0x06040001,
+			   RT6855_PCIE2_OFFSET + RALINK_PCI_CLASS);
 		printk("PCIE2 enabled\n");
 	}
 
-- 
2.7.4

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[PATCH v9 09/15] staging: mt7621-pci: review includes putting them in alphabethic order

[Sergio Paracuellos]

There are some includes that are being used that are not really
needed to correct driver compilation. Remove them and reorder the
rest alphabetically.

Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
---
 drivers/staging/mt7621-pci/pci-mt7621.c | 22 ++++++++--------------
 1 file changed, 8 insertions(+), 14 deletions(-)

diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c b/drivers/staging/mt7621-pci/pci-mt7621.c
index 2533dfc..4dcb881 100644
--- a/drivers/staging/mt7621-pci/pci-mt7621.c
+++ b/drivers/staging/mt7621-pci/pci-mt7621.c
@@ -40,26 +40,20 @@
  **************************************************************************
  */
 
-#include <linux/types.h>
-#include <linux/pci.h>
-#include <linux/kernel.h>
-#include <linux/slab.h>
-#include <linux/version.h>
-#include <linux/pci.h>
-#include <linux/io.h>
-#include <asm/mips-cm.h>
-#include <linux/init.h>
-#include <linux/module.h>
+#include <linux/bitops.h>
+#include <linux/clk.h>
 #include <linux/delay.h>
+#include <linux/module.h>
 #include <linux/of.h>
-#include <linux/of_pci.h>
-#include <linux/of_platform.h>
 #include <linux/of_address.h>
 #include <linux/of_irq.h>
+#include <linux/of_pci.h>
+#include <linux/of_platform.h>
+#include <linux/pci.h>
 #include <linux/platform_device.h>
-
-#include <ralink_regs.h>
+#include <linux/reset.h>
 #include <mt7621.h>
+#include <ralink_regs.h>
 
 #include "../../pci/pci.h"
 
-- 
2.7.4

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[PATCH v9 10/15] staging: mt7621-pci: use pcie_[read|write] in RALINK_PCI_PCICFG_ADDR and RALINK_PCI_PCIMSK_ADDR

[Sergio Paracuellos]

RALINK_PCI_PCICFG_ADDR and RALINK_PCI_PCIMSK_ADDR are defined to be directly
referenced for read and write. Use pcie_read and pcie_write instead changing
its definition to a simple relative offset to pcie base address.

Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
---
 drivers/staging/mt7621-pci/pci-mt7621.c | 54 +++++++++++++++++++++------------
 1 file changed, 34 insertions(+), 20 deletions(-)

diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c b/drivers/staging/mt7621-pci/pci-mt7621.c
index 4dcb881..696d967 100644
--- a/drivers/staging/mt7621-pci/pci-mt7621.c
+++ b/drivers/staging/mt7621-pci/pci-mt7621.c
@@ -74,8 +74,8 @@
 #define RALINK_PCIE1_RST		(1<<25)
 #define RALINK_PCIE2_RST		(1<<26)
 
-#define RALINK_PCI_PCICFG_ADDR		*(volatile u32 *)(RALINK_PCI_BASE + 0x0000)
-#define RALINK_PCI_PCIMSK_ADDR		*(volatile u32 *)(RALINK_PCI_BASE + 0x000C)
+#define RALINK_PCI_PCICFG_ADDR		0x0000
+#define RALINK_PCI_PCIMSK_ADDR		0x000C
 #define RALINK_PCI_BASE	0xBE140000
 
 #define RT6855_PCIE0_OFFSET		0x2000
@@ -530,7 +530,9 @@ static int mt7621_pci_probe(struct platform_device *pdev)
 		pcie_link_status &= ~(1<<0);
 	} else {
 		pcie_link_status |= 1<<0;
-		RALINK_PCI_PCIMSK_ADDR |= (1<<20); // enable pcie1 interrupt
+		val = pcie_read(pcie, RALINK_PCI_PCIMSK_ADDR);
+		val |= (1<<20); // enable pcie1 interrupt
+		pcie_write(pcie, val, RALINK_PCI_PCIMSK_ADDR);
 	}
 
 	if ((pcie_read(pcie, RT6855_PCIE1_OFFSET + RALINK_PCI_STATUS) & 0x1) == 0) {
@@ -540,7 +542,9 @@ static int mt7621_pci_probe(struct platform_device *pdev)
 		pcie_link_status &= ~(1<<1);
 	} else {
 		pcie_link_status |= 1<<1;
-		RALINK_PCI_PCIMSK_ADDR |= (1<<21); // enable pcie1 interrupt
+		val = pcie_read(pcie, RALINK_PCI_PCIMSK_ADDR);
+		val |= (1<<21); // enable pcie1 interrupt
+		pcie_write(pcie, val, RALINK_PCI_PCIMSK_ADDR);
 	}
 
 	if ((pcie_read(pcie, RT6855_PCIE2_OFFSET + RALINK_PCI_STATUS) & 0x1) == 0) {
@@ -550,7 +554,9 @@ static int mt7621_pci_probe(struct platform_device *pdev)
 		pcie_link_status &= ~(1<<2);
 	} else {
 		pcie_link_status |= 1<<2;
-		RALINK_PCI_PCIMSK_ADDR |= (1<<22); // enable pcie2 interrupt
+		val = pcie_read(pcie, RALINK_PCI_PCIMSK_ADDR);
+		val |= (1<<22); // enable pcie2 interrupt
+		pcie_write(pcie, val, RALINK_PCI_PCIMSK_ADDR);
 	}
 
 	if (pcie_link_status == 0)
@@ -569,27 +575,35 @@ pcie(2/1/0) link status	pcie2_num	pcie1_num	pcie0_num
 */
 	switch (pcie_link_status) {
 	case 2:
-		RALINK_PCI_PCICFG_ADDR &= ~0x00ff0000;
-		RALINK_PCI_PCICFG_ADDR |= 0x1 << 16;	//port0
-		RALINK_PCI_PCICFG_ADDR |= 0x0 << 20;	//port1
+		val = pcie_read(pcie, RALINK_PCI_PCICFG_ADDR);
+		val &= ~0x00ff0000;
+		val |= 0x1 << 16;	// port 0
+		val |= 0x0 << 20;	// port 1
+		pcie_write(pcie, val, RALINK_PCI_PCICFG_ADDR);
 		break;
 	case 4:
-		RALINK_PCI_PCICFG_ADDR &= ~0x0fff0000;
-		RALINK_PCI_PCICFG_ADDR |= 0x1 << 16;	//port0
-		RALINK_PCI_PCICFG_ADDR |= 0x2 << 20;	//port1
-		RALINK_PCI_PCICFG_ADDR |= 0x0 << 24;	//port2
+		val = pcie_read(pcie, RALINK_PCI_PCICFG_ADDR);
+		val &= ~0x0fff0000;
+		val |= 0x1 << 16;	//port0
+		val |= 0x2 << 20;	//port1
+		val |= 0x0 << 24;	//port2
+		pcie_write(pcie, val, RALINK_PCI_PCICFG_ADDR);
 		break;
 	case 5:
-		RALINK_PCI_PCICFG_ADDR &= ~0x0fff0000;
-		RALINK_PCI_PCICFG_ADDR |= 0x0 << 16;	//port0
-		RALINK_PCI_PCICFG_ADDR |= 0x2 << 20;	//port1
-		RALINK_PCI_PCICFG_ADDR |= 0x1 << 24;	//port2
+		val = pcie_read(pcie, RALINK_PCI_PCICFG_ADDR);
+		val &= ~0x0fff0000;
+		val |= 0x0 << 16;	//port0
+		val |= 0x2 << 20;	//port1
+		val |= 0x1 << 24;	//port2
+		pcie_write(pcie, val, RALINK_PCI_PCICFG_ADDR);
 		break;
 	case 6:
-		RALINK_PCI_PCICFG_ADDR &= ~0x0fff0000;
-		RALINK_PCI_PCICFG_ADDR |= 0x2 << 16;	//port0
-		RALINK_PCI_PCICFG_ADDR |= 0x0 << 20;	//port1
-		RALINK_PCI_PCICFG_ADDR |= 0x1 << 24;	//port2
+		val = pcie_read(pcie, RALINK_PCI_PCICFG_ADDR);
+		val &= ~0x0fff0000;
+		val |= 0x2 << 16;	//port0
+		val |= 0x0 << 20;	//port1
+		val |= 0x1 << 24;	//port2
+		pcie_write(pcie, val, RALINK_PCI_PCICFG_ADDR);
 		break;
 	}
 
-- 
2.7.4

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[PATCH v9 11/15] staging: mt7621-pci: remove RALINK_PCI_BASE from remaining definitions

[Sergio Paracuellos]

RALINK_PCI_BASE has no sense and this driver has base address readed
and mapped from device tree. Remove remaining uses of it and
change code to use pcie_read and pcie_write functions in places
where this was being used.

Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
---
 drivers/staging/mt7621-pci/pci-mt7621.c | 131 ++++++++++++++++----------------
 1 file changed, 67 insertions(+), 64 deletions(-)

diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c b/drivers/staging/mt7621-pci/pci-mt7621.c
index 696d967..288f83a 100644
--- a/drivers/staging/mt7621-pci/pci-mt7621.c
+++ b/drivers/staging/mt7621-pci/pci-mt7621.c
@@ -76,7 +76,6 @@
 
 #define RALINK_PCI_PCICFG_ADDR		0x0000
 #define RALINK_PCI_PCIMSK_ADDR		0x000C
-#define RALINK_PCI_BASE	0xBE140000
 
 #define RT6855_PCIE0_OFFSET		0x2000
 #define RT6855_PCIE1_OFFSET		0x3000
@@ -89,8 +88,8 @@
 #define RALINK_PCI_SUBID		0x0038
 #define RALINK_PCI_STATUS		0x0050
 
-#define RALINK_PCIEPHY_P0P1_CTL_OFFSET	(RALINK_PCI_BASE + 0x9000)
-#define RALINK_PCIEPHY_P2_CTL_OFFSET	(RALINK_PCI_BASE + 0xA000)
+#define RALINK_PCIEPHY_P0P1_CTL_OFFSET	0x9000
+#define RALINK_PCIEPHY_P2_CTL_OFFSET	0xA000
 
 #define RALINK_PCI_MM_MAP_BASE		0x60000000
 #define RALINK_PCI_IO_MAP_BASE		0x1e160000
@@ -231,105 +230,109 @@ pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
 }
 
 void
-set_pcie_phy(u32 *addr, int start_b, int bits, int val)
+set_pcie_phy(struct mt7621_pcie *pcie, u32 offset,
+	     int start_b, int bits, int val)
 {
-	*(unsigned int *)(addr) &= ~(((1<<bits) - 1)<<start_b);
-	*(unsigned int *)(addr) |= val << start_b;
+	u32 reg = pcie_read(pcie, offset);
+
+	reg &= ~(((1 << bits) - 1) << start_b);
+	reg |= val << start_b;
+	pcie_write(pcie, reg, offset);
 }
 
 void
-bypass_pipe_rst(void)
+bypass_pipe_rst(struct mt7621_pcie *pcie)
 {
 	/* PCIe Port 0 */
-	set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x02c), 12, 1, 0x01);	// rg_pe1_pipe_rst_b
-	set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x02c),  4, 1, 0x01);	// rg_pe1_pipe_cmd_frc[4]
+	set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x02c), 12, 1, 0x01);	// rg_pe1_pipe_rst_b
+	set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x02c),  4, 1, 0x01);	// rg_pe1_pipe_cmd_frc[4]
 	/* PCIe Port 1 */
-	set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x12c), 12, 1, 0x01);	// rg_pe1_pipe_rst_b
-	set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x12c),  4, 1, 0x01);	// rg_pe1_pipe_cmd_frc[4]
+	set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x12c), 12, 1, 0x01);	// rg_pe1_pipe_rst_b
+	set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x12c),  4, 1, 0x01);	// rg_pe1_pipe_cmd_frc[4]
 	/* PCIe Port 2 */
-	set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x02c), 12, 1, 0x01);	// rg_pe1_pipe_rst_b
-	set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x02c),  4, 1, 0x01);	// rg_pe1_pipe_cmd_frc[4]
+	set_pcie_phy(pcie, (RALINK_PCIEPHY_P2_CTL_OFFSET + 0x02c), 12, 1, 0x01);	// rg_pe1_pipe_rst_b
+	set_pcie_phy(pcie, (RALINK_PCIEPHY_P2_CTL_OFFSET + 0x02c),  4, 1, 0x01);	// rg_pe1_pipe_cmd_frc[4]
 }
 
 void
-set_phy_for_ssc(void)
+set_phy_for_ssc(struct mt7621_pcie *pcie)
 {
 	unsigned long reg = rt_sysc_r32(SYSC_REG_SYSTEM_CONFIG0);
 
 	reg = (reg >> 6) & 0x7;
 	/* Set PCIe Port0 & Port1 PHY to disable SSC */
 	/* Debug Xtal Type */
-	set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x400),  8, 1, 0x01);	// rg_pe1_frc_h_xtal_type
-	set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x400),  9, 2, 0x00);	// rg_pe1_h_xtal_type
-	set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x000),  4, 1, 0x01);	// rg_pe1_frc_phy_en	//Force Port 0 enable control
-	set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x100),  4, 1, 0x01);	// rg_pe1_frc_phy_en	//Force Port 1 enable control
-	set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x000),  5, 1, 0x00);	// rg_pe1_phy_en	//Port 0 disable
-	set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x100),  5, 1, 0x00);	// rg_pe1_phy_en	//Port 1 disable
+	set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x400),  8, 1, 0x01);	// rg_pe1_frc_h_xtal_type
+	set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x400),  9, 2, 0x00);	// rg_pe1_h_xtal_type
+	set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x000),  4, 1, 0x01);	// rg_pe1_frc_phy_en	//Force Port 0 enable control
+	set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x100),  4, 1, 0x01);	// rg_pe1_frc_phy_en	//Force Port 1 enable control
+	set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x000),  5, 1, 0x00);	// rg_pe1_phy_en	//Port 0 disable
+	set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x100),  5, 1, 0x00);	// rg_pe1_phy_en	//Port 1 disable
 	if (reg <= 5 && reg >= 3) {	// 40MHz Xtal
-		set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490),  6, 2, 0x01);	// RG_PE1_H_PLL_PREDIV	//Pre-divider ratio (for host mode)
+		set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490),  6, 2, 0x01);	// RG_PE1_H_PLL_PREDIV	//Pre-divider ratio (for host mode)
 		printk("***** Xtal 40MHz *****\n");
 	} else {			// 25MHz | 20MHz Xtal
-		set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490),  6, 2, 0x00);	// RG_PE1_H_PLL_PREDIV	//Pre-divider ratio (for host mode)
+		set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490),  6, 2, 0x00);	// RG_PE1_H_PLL_PREDIV	//Pre-divider ratio (for host mode)
 		if (reg >= 6) {
 			printk("***** Xtal 25MHz *****\n");
-			set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4bc),  4, 2, 0x01);	// RG_PE1_H_PLL_FBKSEL	//Feedback clock select
-			set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x49c),  0, 31, 0x18000000);	// RG_PE1_H_LCDDS_PCW_NCPO	//DDS NCPO PCW (for host mode)
-			set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4a4),  0, 16, 0x18d);	// RG_PE1_H_LCDDS_SSC_PRD	//DDS SSC dither period control
-			set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4a8),  0, 12, 0x4a);	// RG_PE1_H_LCDDS_SSC_DELTA	//DDS SSC dither amplitude control
-			set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4a8), 16, 12, 0x4a);	// RG_PE1_H_LCDDS_SSC_DELTA1	//DDS SSC dither amplitude control for initial
+			set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4bc),  4, 2, 0x01);	// RG_PE1_H_PLL_FBKSEL	//Feedback clock select
+			set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x49c),  0, 31, 0x18000000);	// RG_PE1_H_LCDDS_PCW_NCPO	//DDS NCPO PCW (for host mode)
+			set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4a4),  0, 16, 0x18d);	// RG_PE1_H_LCDDS_SSC_PRD	//DDS SSC dither period control
+			set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4a8),  0, 12, 0x4a);	// RG_PE1_H_LCDDS_SSC_DELTA	//DDS SSC dither amplitude control
+			set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4a8), 16, 12, 0x4a);	// RG_PE1_H_LCDDS_SSC_DELTA1	//DDS SSC dither amplitude control for initial
 		} else {
 			printk("***** Xtal 20MHz *****\n");
 		}
 	}
-	set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4a0),  5, 1, 0x01);	// RG_PE1_LCDDS_CLK_PH_INV	//DDS clock inversion
-	set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 22, 2, 0x02);	// RG_PE1_H_PLL_BC
-	set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 18, 4, 0x06);	// RG_PE1_H_PLL_BP
-	set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 12, 4, 0x02);	// RG_PE1_H_PLL_IR
-	set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490),  8, 4, 0x01);	// RG_PE1_H_PLL_IC
-	set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4ac), 16, 3, 0x00);	// RG_PE1_H_PLL_BR
-	set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490),  1, 3, 0x02);	// RG_PE1_PLL_DIVEN
+	set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4a0),  5, 1, 0x01);	// RG_PE1_LCDDS_CLK_PH_INV	//DDS clock inversion
+	set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 22, 2, 0x02);	// RG_PE1_H_PLL_BC
+	set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 18, 4, 0x06);	// RG_PE1_H_PLL_BP
+	set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 12, 4, 0x02);	// RG_PE1_H_PLL_IR
+	set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490),  8, 4, 0x01);	// RG_PE1_H_PLL_IC
+	set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4ac), 16, 3, 0x00);	// RG_PE1_H_PLL_BR
+	set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490),  1, 3, 0x02);	// RG_PE1_PLL_DIVEN
 	if (reg <= 5 && reg >= 3) {	// 40MHz Xtal
-		set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x414),  6, 2, 0x01);	// rg_pe1_mstckdiv		//value of da_pe1_mstckdiv when force mode enable
-		set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x414),  5, 1, 0x01);	// rg_pe1_frc_mstckdiv	//force mode enable of da_pe1_mstckdiv
+		set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x414),  6, 2, 0x01);	// rg_pe1_mstckdiv		//value of da_pe1_mstckdiv when force mode enable
+		set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x414),  5, 1, 0x01);	// rg_pe1_frc_mstckdiv	//force mode enable of da_pe1_mstckdiv
 	}
 	/* Enable PHY and disable force mode */
-	set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x000),  5, 1, 0x01);	// rg_pe1_phy_en	//Port 0 enable
-	set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x100),  5, 1, 0x01);	// rg_pe1_phy_en	//Port 1 enable
-	set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x000),  4, 1, 0x00);	// rg_pe1_frc_phy_en	//Force Port 0 disable control
-	set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x100),  4, 1, 0x00);	// rg_pe1_frc_phy_en	//Force Port 1 disable control
+	set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x000),  5, 1, 0x01);	// rg_pe1_phy_en	//Port 0 enable
+	set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x100),  5, 1, 0x01);	// rg_pe1_phy_en	//Port 1 enable
+	set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x000),  4, 1, 0x00);	// rg_pe1_frc_phy_en	//Force Port 0 disable control
+	set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x100),  4, 1, 0x00);	// rg_pe1_frc_phy_en	//Force Port 1 disable control
 
 	/* Set PCIe Port2 PHY to disable SSC */
 	/* Debug Xtal Type */
-	set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x400),  8, 1, 0x01);	// rg_pe1_frc_h_xtal_type
-	set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x400),  9, 2, 0x00);	// rg_pe1_h_xtal_type
-	set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x000),  4, 1, 0x01);	// rg_pe1_frc_phy_en	//Force Port 0 enable control
-	set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x000),  5, 1, 0x00);	// rg_pe1_phy_en	//Port 0 disable
+	set_pcie_phy(pcie, (RALINK_PCIEPHY_P2_CTL_OFFSET + 0x400),  8, 1, 0x01);	// rg_pe1_frc_h_xtal_type
+	set_pcie_phy(pcie, (RALINK_PCIEPHY_P2_CTL_OFFSET + 0x400),  9, 2, 0x00);	// rg_pe1_h_xtal_type
+	set_pcie_phy(pcie, (RALINK_PCIEPHY_P2_CTL_OFFSET + 0x000),  4, 1, 0x01);	// rg_pe1_frc_phy_en	//Force Port 0 enable control
+	set_pcie_phy(pcie, (RALINK_PCIEPHY_P2_CTL_OFFSET + 0x000),  5, 1, 0x00);	// rg_pe1_phy_en	//Port 0 disable
 	if (reg <= 5 && reg >= 3) {	// 40MHz Xtal
-		set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490),  6, 2, 0x01);	// RG_PE1_H_PLL_PREDIV	//Pre-divider ratio (for host mode)
+		set_pcie_phy(pcie, (RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490),  6, 2, 0x01);	// RG_PE1_H_PLL_PREDIV	//Pre-divider ratio (for host mode)
 	} else {			// 25MHz | 20MHz Xtal
-		set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490),  6, 2, 0x00);	// RG_PE1_H_PLL_PREDIV	//Pre-divider ratio (for host mode)
+		set_pcie_phy(pcie, (RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490),  6, 2, 0x00);	// RG_PE1_H_PLL_PREDIV	//Pre-divider ratio (for host mode)
 		if (reg >= 6) {		// 25MHz Xtal
-			set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4bc),  4, 2, 0x01);	// RG_PE1_H_PLL_FBKSEL	//Feedback clock select
-			set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x49c),  0, 31, 0x18000000);	// RG_PE1_H_LCDDS_PCW_NCPO	//DDS NCPO PCW (for host mode)
-			set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4a4),  0, 16, 0x18d);	// RG_PE1_H_LCDDS_SSC_PRD	//DDS SSC dither period control
-			set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4a8),  0, 12, 0x4a);	// RG_PE1_H_LCDDS_SSC_DELTA	//DDS SSC dither amplitude control
-			set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4a8), 16, 12, 0x4a);	// RG_PE1_H_LCDDS_SSC_DELTA1	//DDS SSC dither amplitude control for initial
+			set_pcie_phy(pcie, (RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4bc),  4, 2, 0x01);	// RG_PE1_H_PLL_FBKSEL	//Feedback clock select
+			set_pcie_phy(pcie, (RALINK_PCIEPHY_P2_CTL_OFFSET + 0x49c),  0, 31, 0x18000000);	// RG_PE1_H_LCDDS_PCW_NCPO	//DDS NCPO PCW (for host mode)
+			set_pcie_phy(pcie, (RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4a4),  0, 16, 0x18d);	// RG_PE1_H_LCDDS_SSC_PRD	//DDS SSC dither period control
+			set_pcie_phy(pcie, (RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4a8),  0, 12, 0x4a);	// RG_PE1_H_LCDDS_SSC_DELTA	//DDS SSC dither amplitude control
+			set_pcie_phy(pcie, (RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4a8), 16, 12, 0x4a);	// RG_PE1_H_LCDDS_SSC_DELTA1	//DDS SSC dither amplitude control for initial
 		}
 	}
-	set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4a0),  5, 1, 0x01);	// RG_PE1_LCDDS_CLK_PH_INV	//DDS clock inversion
-	set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 22, 2, 0x02);	// RG_PE1_H_PLL_BC
-	set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 18, 4, 0x06);	// RG_PE1_H_PLL_BP
-	set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 12, 4, 0x02);	// RG_PE1_H_PLL_IR
-	set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490),  8, 4, 0x01);	// RG_PE1_H_PLL_IC
-	set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4ac), 16, 3, 0x00);	// RG_PE1_H_PLL_BR
-	set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490),  1, 3, 0x02);	// RG_PE1_PLL_DIVEN
+	set_pcie_phy(pcie, (RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4a0),  5, 1, 0x01);	// RG_PE1_LCDDS_CLK_PH_INV	//DDS clock inversion
+	set_pcie_phy(pcie, (RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 22, 2, 0x02);	// RG_PE1_H_PLL_BC
+	set_pcie_phy(pcie, (RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 18, 4, 0x06);	// RG_PE1_H_PLL_BP
+	set_pcie_phy(pcie, (RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 12, 4, 0x02);	// RG_PE1_H_PLL_IR
+	set_pcie_phy(pcie, (RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490),  8, 4, 0x01);	// RG_PE1_H_PLL_IC
+	set_pcie_phy(pcie, (RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4ac), 16, 3, 0x00);	// RG_PE1_H_PLL_BR
+	set_pcie_phy(pcie, (RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490),  1, 3, 0x02);	// RG_PE1_PLL_DIVEN
 	if (reg <= 5 && reg >= 3) {	// 40MHz Xtal
-		set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x414),  6, 2, 0x01);	// rg_pe1_mstckdiv		//value of da_pe1_mstckdiv when force mode enable
-		set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x414),  5, 1, 0x01);	// rg_pe1_frc_mstckdiv	//force mode enable of da_pe1_mstckdiv
+		set_pcie_phy(pcie, (RALINK_PCIEPHY_P2_CTL_OFFSET + 0x414),  6, 2, 0x01);	// rg_pe1_mstckdiv		//value of da_pe1_mstckdiv when force mode enable
+		set_pcie_phy(pcie, (RALINK_PCIEPHY_P2_CTL_OFFSET + 0x414),  5, 1, 0x01);	// rg_pe1_frc_mstckdiv	//force mode enable of da_pe1_mstckdiv
 	}
 	/* Enable PHY and disable force mode */
-	set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x000),  5, 1, 0x01);	// rg_pe1_phy_en	//Port 0 enable
-	set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x000),  4, 1, 0x00);	// rg_pe1_frc_phy_en	//Force Port 0 disable control
+	set_pcie_phy(pcie, (RALINK_PCIEPHY_P2_CTL_OFFSET + 0x000),  5, 1, 0x01);	// rg_pe1_phy_en	//Port 0 enable
+	set_pcie_phy(pcie, (RALINK_PCIEPHY_P2_CTL_OFFSET + 0x000),  4, 1, 0x00);	// rg_pe1_frc_phy_en	//Force Port 0 disable control
 }
 
 static void setup_cm_memory_region(struct resource *mem_resource)
@@ -497,8 +500,8 @@ static int mt7621_pci_probe(struct platform_device *pdev)
 	DEASSERT_SYSRST_PCIE(val);
 
 	if ((*(unsigned int *)(0xbe00000c)&0xFFFF) == 0x0101) // MT7621 E2
-		bypass_pipe_rst();
-	set_phy_for_ssc();
+		bypass_pipe_rst(pcie);
+	set_phy_for_ssc(pcie);
 
 	val = read_config(pcie, 0, 0x70c);
 	printk("Port 0 N_FTS = %x\n", (unsigned int)val);
-- 
2.7.4

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[PATCH v9 12/15] staging: mt7621-pci: use BIT macro in preprocessor definitions

[Sergio Paracuellos]

Some preprocessor definitions are using a custom implementation of
BIT macro. Just use linux kernel BIT macro instead.

Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
---
 drivers/staging/mt7621-pci/pci-mt7621.c | 20 ++++++++++----------
 1 file changed, 10 insertions(+), 10 deletions(-)

diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c b/drivers/staging/mt7621-pci/pci-mt7621.c
index 288f83a..d6f4085 100644
--- a/drivers/staging/mt7621-pci/pci-mt7621.c
+++ b/drivers/staging/mt7621-pci/pci-mt7621.c
@@ -62,17 +62,17 @@
  * devices.
  */
 
-#define RALINK_PCIE0_CLK_EN		(1<<24)
-#define RALINK_PCIE1_CLK_EN		(1<<25)
-#define RALINK_PCIE2_CLK_EN		(1<<26)
+#define RALINK_PCIE0_CLK_EN		BIT(24)
+#define RALINK_PCIE1_CLK_EN		BIT(25)
+#define RALINK_PCIE2_CLK_EN		BIT(26)
 
 #define RALINK_PCI_CONFIG_ADDR		0x20
 #define RALINK_PCI_CONFIG_DATA_VIRTUAL_REG	0x24
 #define RALINK_PCI_MEMBASE		0x28
 #define RALINK_PCI_IOBASE		0x2C
-#define RALINK_PCIE0_RST		(1<<24)
-#define RALINK_PCIE1_RST		(1<<25)
-#define RALINK_PCIE2_RST		(1<<26)
+#define RALINK_PCIE0_RST		BIT(24)
+#define RALINK_PCIE1_RST		BIT(25)
+#define RALINK_PCIE2_RST		BIT(26)
 
 #define RALINK_PCI_PCICFG_ADDR		0x0000
 #define RALINK_PCI_PCIMSK_ADDR		0x000C
@@ -115,11 +115,11 @@
 #define RALINK_PCIE_CLK_GEN		0x7c
 #define RALINK_PCIE_CLK_GEN1		0x80
 //RALINK_RSTCTRL bit
-#define RALINK_PCIE_RST			(1<<23)
-#define RALINK_PCI_RST			(1<<24)
+#define RALINK_PCIE_RST			BIT(23)
+#define RALINK_PCI_RST			BIT(24)
 //RALINK_CLKCFG1 bit
-#define RALINK_PCI_CLK_EN		(1<<19)
-#define RALINK_PCIE_CLK_EN		(1<<21)
+#define RALINK_PCI_CLK_EN		BIT(19)
+#define RALINK_PCIE_CLK_EN		BIT(21)
 
 #define MEMORY_BASE 0x0
 static int pcie_link_status = 0;
-- 
2.7.4

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[PATCH v9 13/15] staging: mt7621-pci: rename RALINK_PCI_CONFIG_DATA_VIRTUAL_REG definition

[Sergio Paracuellos]

RALINK_PCI_CONFIG_DATA_VIRTUAL_REG is a very long name. Make it a bit
shorter renaming it to RALINK_PCI_CONFIG_DATA.

Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
---
 drivers/staging/mt7621-pci/pci-mt7621.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c b/drivers/staging/mt7621-pci/pci-mt7621.c
index d6f4085..491dda7 100644
--- a/drivers/staging/mt7621-pci/pci-mt7621.c
+++ b/drivers/staging/mt7621-pci/pci-mt7621.c
@@ -67,7 +67,7 @@
 #define RALINK_PCIE2_CLK_EN		BIT(26)
 
 #define RALINK_PCI_CONFIG_ADDR		0x20
-#define RALINK_PCI_CONFIG_DATA_VIRTUAL_REG	0x24
+#define RALINK_PCI_CONFIG_DATA		0x24
 #define RALINK_PCI_MEMBASE		0x28
 #define RALINK_PCI_IOBASE		0x2C
 #define RALINK_PCIE0_RST		BIT(24)
@@ -176,7 +176,7 @@ static void __iomem *mt7621_pcie_map_bus(struct pci_bus *bus,
 
 	writel(address, pcie->base + RALINK_PCI_CONFIG_ADDR);
 
-	return pcie->base + RALINK_PCI_CONFIG_DATA_VIRTUAL_REG + (where & 3);
+	return pcie->base + RALINK_PCI_CONFIG_DATA + (where & 3);
 }
 
 struct pci_ops mt7621_pci_ops = {
@@ -191,7 +191,7 @@ read_config(struct mt7621_pcie *pcie, unsigned int dev, u32 reg)
 	u32 address = mt7621_pci_get_cfgaddr(0, dev, 0, reg);
 
 	pcie_write(pcie, address, RALINK_PCI_CONFIG_ADDR);
-	return pcie_read(pcie, RALINK_PCI_CONFIG_DATA_VIRTUAL_REG);
+	return pcie_read(pcie, RALINK_PCI_CONFIG_DATA);
 }
 
 static void
@@ -200,7 +200,7 @@ write_config(struct mt7621_pcie *pcie, unsigned int dev, u32 reg, u32 val)
 	u32 address = mt7621_pci_get_cfgaddr(0, dev, 0, reg);
 
 	pcie_write(pcie, address, RALINK_PCI_CONFIG_ADDR);
-	pcie_write(pcie, val, RALINK_PCI_CONFIG_DATA_VIRTUAL_REG);
+	pcie_write(pcie, val, RALINK_PCI_CONFIG_DATA);
 }
 
 int
-- 
2.7.4

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[PATCH v9 14/15] staging: mt7621-pci: remove remaining pci_legacy dependant code

[Sergio Paracuellos]

pcibios_* remaining code is not neccessary at all. We can use
map_irq set to of_irq_parse_and_map_pci driver 'probe' function.
Remove this code.

Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
---
 drivers/staging/mt7621-pci/pci-mt7621.c | 33 +--------------------------------
 1 file changed, 1 insertion(+), 32 deletions(-)

diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c b/drivers/staging/mt7621-pci/pci-mt7621.c
index 491dda7..e224d30 100644
--- a/drivers/staging/mt7621-pci/pci-mt7621.c
+++ b/drivers/staging/mt7621-pci/pci-mt7621.c
@@ -203,32 +203,6 @@ write_config(struct mt7621_pcie *pcie, unsigned int dev, u32 reg, u32 val)
 	pcie_write(pcie, val, RALINK_PCI_CONFIG_DATA);
 }
 
-int
-pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
-{
-	struct mt7621_pcie *pcie = dev->bus->sysdata;
-	u16 cmd;
-	u32 val;
-	int irq;
-
-	if (dev->bus->number == 0) {
-		write_config(pcie, slot, PCI_BASE_ADDRESS_0, MEMORY_BASE);
-		val = read_config(pcie, slot, PCI_BASE_ADDRESS_0);
-		printk("BAR0 at slot %d = %x\n", slot, val);
-	}
-
-	pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 0x14);  //configure cache line size 0x14
-	pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0xFF);  //configure latency timer 0x10
-	pci_read_config_word(dev, PCI_COMMAND, &cmd);
-	cmd = cmd | PCI_COMMAND_MASTER | PCI_COMMAND_IO | PCI_COMMAND_MEMORY;
-	pci_write_config_word(dev, PCI_COMMAND, cmd);
-
-	irq = of_irq_parse_and_map_pci(dev, slot, pin);
-
-	pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq);
-	return irq;
-}
-
 void
 set_pcie_phy(struct mt7621_pcie *pcie, u32 offset,
 	     int start_b, int bits, int val)
@@ -438,7 +412,7 @@ static int mt7621_pcie_register_host(struct pci_host_bridge *host,
 	host->busnr = 0;
 	host->dev.parent = pcie->dev;
 	host->ops = &mt7621_pci_ops;
-	host->map_irq = pcibios_map_irq;
+	host->map_irq = of_irq_parse_and_map_pci;
 	host->swizzle_irq = pci_common_swizzle;
 	host->sysdata = pcie;
 
@@ -695,11 +669,6 @@ pcie(2/1/0) link status	pcie2_num	pcie1_num	pcie0_num
 	return 0;
 }
 
-int pcibios_plat_dev_init(struct pci_dev *dev)
-{
-	return 0;
-}
-
 static const struct of_device_id mt7621_pci_ids[] = {
 	{ .compatible = "mediatek,mt7621-pci" },
 	{},
-- 
2.7.4

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[PATCH v9 15/15] staging: mt7621-dts: add pcie controller port registers

[Sergio Paracuellos]

The pcie node of the device tree only contains registers
for the host-bridge and pcie port 0. Add the pcie port 1
and pcie port 2 also.

Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
---
 drivers/staging/mt7621-dts/mt7621.dtsi | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/staging/mt7621-dts/mt7621.dtsi b/drivers/staging/mt7621-dts/mt7621.dtsi
index 4610403..2e837e6 100644
--- a/drivers/staging/mt7621-dts/mt7621.dtsi
+++ b/drivers/staging/mt7621-dts/mt7621.dtsi
@@ -394,8 +394,10 @@
 
 	pcie: pcie@1e140000 {
 		compatible = "mediatek,mt7621-pci";
-		reg = <0x1e140000 0x100
-			0x1e142000 0x100>;
+		reg = <0x1e140000 0x100     /* host-pci bridge registers */
+			0x1e142000 0x100    /* pcie port 0 RC control registers */
+			0x1e143000 0x100    /* pcie port 1 RC control registers */
+			0x1e144000 0x100>;  /* pcie port 2 RC control registers */
 
 		#address-cells = <3>;
 		#size-cells = <2>;
-- 
2.7.4

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Re: [PATCH v9 00/15] staging: mt7621-pci: avoid custom pci config read and writes

[NeilBrown]

[-- Attachment #1.1: Type: text/plain, Size: 42880 bytes --]

On Thu, Aug 02 2018, Sergio Paracuellos wrote:

> This patch series include an attempt to avoid the use of custom
> read and writes in driver code and use PCI subsystem common ones.
>
> In order to do this 'map_bus' callback is implemented and also
> data structures for driver are included. The regs base address
> ranges and data is being readed from device tree and the driver
> gets clean a lot of code.
>
> This patchet also removes all legacy PCI code using now PCI_DRIVERS_GENERIC
> kernel api.
>
> Changes in v9:
>     - PATCH 1: Use 'res' as resources list and void store resources in
>       the pcie data struct.
>     - PATCH 1: Rewrite 'mt7621_pci_parse_request_of_pci_ranges' to use
>       'devm_of_pci_get_host_bridge_resources' and use 'remap' directly
>       with the returned 'iobase' address instead of 'devm_pci_remap_iospace' 
>       which get into a WARN_ONCE statement because 'PCI_IOBASE' is not
>       defined for mips.
>     - Other patches rebased and adapted to this changes.

You probably expected this, but still no change.
Just for completeness boot log is below.

Thanks,
NeilBrown

Starting kernel ...

[    0.000000] Linux version 4.18.0-rc7+ (neilb@noble) (gcc version 7.2.0 (GCC)) #277 SMP Fri Aug 3 14:30:02 AEST 2018
[    0.000000] SoC Type: MediaTek MT7621 ver:1 eco:3
[    0.000000] bootconsole [early0] enabled
[    0.000000] CPU0 revision is: 0001992f (MIPS 1004Kc)
[    0.000000] MIPS: machine is GB-PC1
[    0.000000] Determined physical RAM map:
[    0.000000]  memory: 1c000000 @ 00000000 (usable)
[    0.000000]  memory: 04000000 @ 20000000 (usable)
[    0.000000] Initrd not found or empty - disabling initrd
[    0.000000] VPE topology {2,2} total 4
[    0.000000] Primary instruction cache 32kB, VIPT, 4-way, linesize 32 bytes.
[    0.000000] Primary data cache 32kB, 4-way, PIPT, no aliases, linesize 32 bytes
[    0.000000] MIPS secondary cache 256kB, 8-way, linesize 32 bytes.
[    0.000000] Zone ranges:
[    0.000000]   Normal   [mem 0x0000000000000000-0x000000001fffffff]
[    0.000000]   HighMem  [mem 0x0000000020000000-0x0000000023ffffff]
[    0.000000] Movable zone start for each node
[    0.000000] Early memory node ranges
[    0.000000]   node   0: [mem 0x0000000000000000-0x000000001bffffff]
[    0.000000]   node   0: [mem 0x0000000020000000-0x0000000023ffffff]
[    0.000000] Initmem setup node 0 [mem 0x0000000000000000-0x0000000023ffffff]
[    0.000000] random: get_random_bytes called from start_kernel+0xb4/0x4ec with crng_init=0
[    0.000000] percpu: Embedded 15 pages/cpu @(ptrval) s30480 r8192 d22768 u61440
[    0.000000] Built 1 zonelists, mobility grouping on.  Total pages: 130048
[    0.000000] Kernel command line: console=ttyS0,57600
[    0.000000] Dentry cache hash table entries: 65536 (order: 6, 262144 bytes)
[    0.000000] Inode-cache hash table entries: 32768 (order: 5, 131072 bytes)
[    0.000000] Writing ErrCtl register=000108a2
[    0.000000] Readback ErrCtl register=000108a2
[    0.000000] Memory: 504788K/524288K available (6135K kernel code, 228K rwdata, 1052K rodata, 6524K init, 241K bss, 19500K reserved, 0K cma-reserved, 65536K highmem)
[    0.000000] SLUB: HWalign=32, Order=0-3, MinObjects=0, CPUs=4, Nodes=1
[    0.000000] Hierarchical RCU implementation.
[    0.000000] NR_IRQS: 256
[    0.000000] clocksource: GIC: mask: 0xffffffffffffffff max_cycles: 0xcf914c9718, max_idle_ns: 440795231327 ns
[    0.000000] sched_clock: 32 bits at 100 Hz, resolution 10000000ns, wraps every 21474836475000000ns
[    0.010000] Calibrating delay loop... 597.60 BogoMIPS (lpj=2988032)
[    0.070000] pid_max: default: 32768 minimum: 301
[    0.080000] Mount-cache hash table entries: 1024 (order: 0, 4096 bytes)
[    0.090000] Mountpoint-cache hash table entries: 1024 (order: 0, 4096 bytes)
[    0.100000] Hierarchical SRCU implementation.
[    0.110000] smp: Bringing up secondary CPUs ...
[    0.120000] Primary instruction cache 32kB, VIPT, 4-way, linesize 32 bytes.
[    0.120000] Primary data cache 32kB, 4-way, PIPT, no aliases, linesize 32 bytes
[    0.120000] MIPS secondary cache 256kB, 8-way, linesize 32 bytes.
[    0.120000] CPU1 revision is: 0001992f (MIPS 1004Kc)
[    0.180000] Synchronize counters for CPU 1: done.
[    0.220000] Primary instruction cache 32kB, VIPT, 4-way, linesize 32 bytes.
[    0.220000] Primary data cache 32kB, 4-way, PIPT, no aliases, linesize 32 bytes
[    0.220000] MIPS secondary cache 256kB, 8-way, linesize 32 bytes.
[    0.220000] CPU2 revision is: 0001992f (MIPS 1004Kc)
[    0.280000] Synchronize counters for CPU 2: done.
[    0.320000] Primary instruction cache 32kB, VIPT, 4-way, linesize 32 bytes.
[    0.320000] Primary data cache 32kB, 4-way, PIPT, no aliases, linesize 32 bytes
[    0.320000] MIPS secondary cache 256kB, 8-way, linesize 32 bytes.
[    0.320000] CPU3 revision is: 0001992f (MIPS 1004Kc)
[    0.380000] Synchronize counters for CPU 3: done.
[    0.420000] smp: Brought up 1 node, 4 CPUs
[    0.430000] devtmpfs: initialized
[    0.480000] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns
[    0.490000] futex hash table entries: 1024 (order: 3, 32768 bytes)
[    0.500000] pinctrl core: initialized pinctrl subsystem
[    0.510000] NET: Registered protocol family 16
[    0.870000] ***** Xtal 40MHz *****
[    0.880000] Port 0 N_FTS = 1b102800
[    0.890000] Port 1 N_FTS = 1b102800
[    0.890000] Port 2 N_FTS = 1b102800
[    1.950000] PCIE0 enabled
[    1.960000] PCIE1 enabled
[    1.960000] PCIE2 enabled
[    1.970000] mt7621-pci 1e140000.pcie: host bridge /pcie@1e140000 ranges:
[    1.980000] mt7621-pci 1e140000.pcie:   MEM 0x60000000..0x6fffffff -> 0x00000000
[    2.000000] mt7621-pci 1e140000.pcie:    IO 0x1e160000..0x1e16ffff -> 0x00000000
[    2.010000] PCI coherence region base: 0x60000000, mask/settings: 0xf0000002
[    2.020000] mt7621-pci 1e140000.pcie: PCI host bridge to bus 0000:00
[    2.040000] pci_bus 0000:00: root bus resource [bus 00-ff]
[    2.050000] pci_bus 0000:00: root bus resource [mem 0x60000000-0x6fffffff] (bus address [0x00000000-0x0fffffff])
[    2.070000] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
[    2.090000] pci 0000:00:01.0: bridge configuration invalid ([bus 00-00]), reconfiguring
[    2.100000] pci 0000:00:02.0: bridge configuration invalid ([bus 00-00]), reconfiguring
[    2.120000] pci 0000:00:00.0: PCI bridge to [bus 01-ff]
[    2.140000] pci 0000:00:01.0: PCI bridge to [bus 02-ff]
[    2.150000] pci 0000:00:02.0: PCI bridge to [bus 03-ff]
[    2.160000] pci 0000:00:00.0: BAR 0: no space for [mem size 0x80000000]
[    2.170000] pci 0000:00:00.0: BAR 0: failed to assign [mem size 0x80000000]
[    2.190000] pci 0000:00:01.0: BAR 0: no space for [mem size 0x80000000]
[    2.200000] pci 0000:00:01.0: BAR 0: failed to assign [mem size 0x80000000]
[    2.210000] pci 0000:00:02.0: BAR 0: no space for [mem size 0x80000000]
[    2.230000] pci 0000:00:02.0: BAR 0: failed to assign [mem size 0x80000000]
[    2.240000] pci 0000:00:00.0: BAR 8: assigned [mem 0x60000000-0x600fffff]
[    2.250000] pci 0000:00:00.0: BAR 9: assigned [mem 0x60100000-0x601fffff pref]
[    2.270000] pci 0000:00:01.0: BAR 8: assigned [mem 0x60200000-0x602fffff]
[    2.280000] pci 0000:00:01.0: BAR 9: assigned [mem 0x60300000-0x603fffff pref]
[    2.290000] pci 0000:00:02.0: BAR 8: assigned [mem 0x60400000-0x604fffff]
[    2.310000] pci 0000:00:02.0: BAR 9: assigned [mem 0x60500000-0x605fffff pref]
[    2.320000] pci 0000:00:00.0: BAR 1: assigned [mem 0x60600000-0x6060ffff]
[    2.330000] pci 0000:00:01.0: BAR 1: assigned [mem 0x60610000-0x6061ffff]
[    2.350000] pci 0000:00:02.0: BAR 1: assigned [mem 0x60620000-0x6062ffff]
[    2.360000] pci 0000:00:00.0: BAR 7: no space for [io  size 0x1000]
[    2.370000] pci 0000:00:00.0: BAR 7: failed to assign [io  size 0x1000]
[    2.390000] pci 0000:00:01.0: BAR 7: no space for [io  size 0x1000]
[    2.400000] pci 0000:00:01.0: BAR 7: failed to assign [io  size 0x1000]
[    2.410000] pci 0000:00:02.0: BAR 7: no space for [io  size 0x1000]
[    2.420000] pci 0000:00:02.0: BAR 7: failed to assign [io  size 0x1000]
[    2.440000] pci 0000:01:00.0: BAR 5: assigned [mem 0x60000000-0x600001ff]
[    2.450000] pci 0000:01:00.0: BAR 4: no space for [io  size 0x0010]
[    2.460000] pci 0000:01:00.0: BAR 4: failed to assign [io  size 0x0010]
[    2.480000] pci 0000:01:00.0: BAR 0: no space for [io  size 0x0008]
[    2.490000] pci 0000:01:00.0: BAR 0: failed to assign [io  size 0x0008]
[    2.500000] pci 0000:01:00.0: BAR 2: no space for [io  size 0x0008]
[    2.510000] pci 0000:01:00.0: BAR 2: failed to assign [io  size 0x0008]
[    2.530000] pci 0000:01:00.0: BAR 1: no space for [io  size 0x0004]
[    2.540000] pci 0000:01:00.0: BAR 1: failed to assign [io  size 0x0004]
[    2.550000] pci 0000:01:00.0: BAR 3: no space for [io  size 0x0004]
[    2.560000] pci 0000:01:00.0: BAR 3: failed to assign [io  size 0x0004]
[    2.580000] pci 0000:00:00.0: PCI bridge to [bus 01]
[    2.590000] pci 0000:00:00.0:   bridge window [mem 0x60000000-0x600fffff]
[    2.600000] pci 0000:00:00.0:   bridge window [mem 0x60100000-0x601fffff pref]
[    2.610000] pci 0000:02:00.0: BAR 5: assigned [mem 0x60200000-0x602001ff]
[    2.630000] pci 0000:02:00.0: BAR 4: no space for [io  size 0x0010]
[    2.640000] pci 0000:02:00.0: BAR 4: failed to assign [io  size 0x0010]
[    2.650000] pci 0000:02:00.0: BAR 0: no space for [io  size 0x0008]
[    2.660000] pci 0000:02:00.0: BAR 0: failed to assign [io  size 0x0008]
[    2.680000] pci 0000:02:00.0: BAR 2: no space for [io  size 0x0008]
[    2.690000] pci 0000:02:00.0: BAR 2: failed to assign [io  size 0x0008]
[    2.700000] pci 0000:02:00.0: BAR 1: no space for [io  size 0x0004]
[    2.710000] pci 0000:02:00.0: BAR 1: failed to assign [io  size 0x0004]
[    2.730000] pci 0000:02:00.0: BAR 3: no space for [io  size 0x0004]
[    2.740000] pci 0000:02:00.0: BAR 3: failed to assign [io  size 0x0004]
[    2.750000] pci 0000:00:01.0: PCI bridge to [bus 02]
[    2.760000] pci 0000:00:01.0:   bridge window [mem 0x60200000-0x602fffff]
[    2.780000] pci 0000:00:01.0:   bridge window [mem 0x60300000-0x603fffff pref]
[    2.790000] pci 0000:03:00.0: BAR 5: assigned [mem 0x60400000-0x604001ff]
[    2.800000] pci 0000:03:00.0: BAR 4: no space for [io  size 0x0010]
[    2.820000] pci 0000:03:00.0: BAR 4: failed to assign [io  size 0x0010]
[    2.830000] pci 0000:03:00.0: BAR 0: no space for [io  size 0x0008]
[    2.840000] pci 0000:03:00.0: BAR 0: failed to assign [io  size 0x0008]
[    2.850000] pci 0000:03:00.0: BAR 2: no space for [io  size 0x0008]
[    2.870000] pci 0000:03:00.0: BAR 2: failed to assign [io  size 0x0008]
[    2.880000] pci 0000:03:00.0: BAR 1: no space for [io  size 0x0004]
[    2.890000] pci 0000:03:00.0: BAR 1: failed to assign [io  size 0x0004]
[    2.900000] pci 0000:03:00.0: BAR 3: no space for [io  size 0x0004]
[    2.920000] pci 0000:03:00.0: BAR 3: failed to assign [io  size 0x0004]
[    2.930000] pci 0000:00:02.0: PCI bridge to [bus 03]
[    2.940000] pci 0000:00:02.0:   bridge window [mem 0x60400000-0x604fffff]
[    2.950000] pci 0000:00:02.0:   bridge window [mem 0x60500000-0x605fffff pref]
[    3.030000] SCSI subsystem initialized
[    3.040000] random: fast init done
[    3.060000] clocksource: Switched to clocksource GIC
[    3.090000] NET: Registered protocol family 2
[    3.100000] tcp_listen_portaddr_hash hash table entries: 512 (order: 0, 6144 bytes)
[    3.110000] TCP established hash table entries: 4096 (order: 2, 16384 bytes)
[    3.130000] TCP bind hash table entries: 4096 (order: 3, 32768 bytes)
[    3.140000] TCP: Hash tables configured (established 4096 bind 4096)
[    3.150000] UDP hash table entries: 256 (order: 1, 8192 bytes)
[    3.170000] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)
[    3.180000] NET: Registered protocol family 1
[    8.150000] Initialise system trusted keyrings
[    8.160000] workingset: timestamp_bits=30 max_order=17 bucket_order=0
[    8.290000] squashfs: version 4.0 (2009/01/31) Phillip Lougher
[    8.310000] jffs2: version 2.2. (NAND) (SUMMARY)  © 2001-2006 Red Hat, Inc.
[    8.330000] SGI XFS with security attributes, no debug enabled
[    8.380000] Key type asymmetric registered
[    8.390000] Asymmetric key parser 'x509' registered
[    8.400000] bounce: pool size: 64 pages
[    8.410000] io scheduler noop registered
[    8.420000] io scheduler deadline registered (default)
[    8.430000] io scheduler mq-deadline registered (default)
[    8.440000] io scheduler kyber registered
[    8.460000] Serial: 8250/16550 driver, 3 ports, IRQ sharing disabled
[    8.480000] console [ttyS0] disabled
[    8.490000] 1e000c00.uartlite: ttyS0 at MMIO 0x1e000c00 (irq = 18, base_baud = 3125000) is a 16550A
[    8.500000] console [ttyS0] enabled
[    8.500000] console [ttyS0] enabled
[    8.520000] bootconsole [early0] disabled
[    8.520000] bootconsole [early0] disabled
[    8.540000] cacheinfo: Failed to find cpu0 device node
[    8.550000] cacheinfo: Unable to detect cache hierarchy for CPU 0
[    8.630000] loop: module loaded
[    8.640000] pci 0000:00:00.0: enabling device (0004 -> 0006)
[    8.650000] ahci 0000:01:00.0: enabling device (0000 -> 0002)
[    8.830000] ------------[ cut here ]------------
[    8.830000] WARNING: CPU: 1 PID: 1 at ../drivers/ata/libahci.c:227 ahci_save_initial_config+0x3c/0x3e0
[    8.850000] Modules linked in:
[    8.860000] CPU: 1 PID: 1 Comm: swapper/0 Not tainted 4.18.0-rc7+ #277
[    8.870000] Stack : 00000000 00000004 00000006 00000000 00000000 00000000 00000000 00000000
[    8.890000]         80da7a3e 0000003a 00000000 00000000 80710000 00000001 9bc73b40 1c044177
[    8.910000]         00000000 00000000 80de0000 00000007 00000000 000000f1 00000000 00000000
[    8.920000]         00000000 000000f0 80dd0000 65726568 80710000 00000000 80730000 806dc1fc
[    8.940000]         00000009 000000e3 00000005 00000000 00000001 803a0508 00000004 80da0004
[    8.950000]         ...
[    8.960000] Call Trace:
[    8.960000] [<8000bd34>] show_stack+0x8c/0x130
[    8.970000] [<805dd684>] dump_stack+0x94/0xd0
[    8.980000] [<80027c30>] __warn+0x10c/0x114
[    8.990000] [<80027ce0>] warn_slowpath_null+0x44/0x58
[    9.000000] [<803f696c>] ahci_save_initial_config+0x3c/0x3e0
[    9.010000] [<803f4bfc>] ahci_init_one+0x46c/0xa40
[    9.020000] [<80371cf0>] pci_device_probe+0x90/0x120
[    9.030000] [<803aff10>] driver_probe_device+0x314/0x46c
[    9.040000] [<803b011c>] __driver_attach+0xb4/0x138
[    9.050000] [<803ad9c0>] bus_for_each_dev+0x6c/0xb0
[    9.060000] [<803aebf8>] bus_add_driver+0x204/0x24c
[    9.070000] [<803b0a68>] driver_register+0xd0/0x118
[    9.080000] [<80001618>] do_one_initcall+0x84/0x19c
[    9.090000] [<80741ed0>] kernel_init_freeable+0x248/0x250
[    9.100000] [<805f5e1c>] kernel_init+0x14/0x110
[    9.110000] [<800066f8>] ret_from_kernel_thread+0x14/0x1c
[    9.120000] ---[ end trace 8d118b8e5f7182f4 ]---
[    9.130000] ahci 0000:01:00.0: forcing PORTS_IMPL to 0x1
[    9.290000] ------------[ cut here ]------------
[    9.290000] WARNING: CPU: 1 PID: 1 at ../drivers/ata/libahci.c:227 ahci_reset_controller+0x2c/0x128
[    9.310000] Modules linked in:
[    9.320000] CPU: 1 PID: 1 Comm: swapper/0 Tainted: G        W         4.18.0-rc7+ #277
[    9.330000] Stack : 00000000 00000004 00000006 00000000 00000000 00000000 00000000 00000000
[    9.350000]         80da7a3e 0000004a 00000000 00000000 80710000 00000001 9bc73b48 1c044177
[    9.370000]         00000000 00000000 80de0000 00000007 00000000 0000010e 00000000 00000000
[    9.380000]         00000000 0000010d 80dd0000 65726568 80710000 00000000 80730000 806dc1fc
[    9.400000]         00000009 000000e3 00000005 9a0a8000 00000001 803a0508 00000004 80da0004
[    9.420000]         ...
[    9.420000] Call Trace:
[    9.430000] [<8000bd34>] show_stack+0x8c/0x130
[    9.440000] [<805dd684>] dump_stack+0x94/0xd0
[    9.440000] [<80027c30>] __warn+0x10c/0x114
[    9.450000] [<80027ce0>] warn_slowpath_null+0x44/0x58
[    9.460000] [<803f6dac>] ahci_reset_controller+0x2c/0x128
[    9.470000] [<803f4fb4>] ahci_init_one+0x824/0xa40
[    9.480000] [<80371cf0>] pci_device_probe+0x90/0x120
[    9.490000] [<803aff10>] driver_probe_device+0x314/0x46c
[    9.500000] [<803b011c>] __driver_attach+0xb4/0x138
[    9.510000] [<803ad9c0>] bus_for_each_dev+0x6c/0xb0
[    9.520000] [<803aebf8>] bus_add_driver+0x204/0x24c
[    9.530000] [<803b0a68>] driver_register+0xd0/0x118
[    9.540000] [<80001618>] do_one_initcall+0x84/0x19c
[    9.550000] [<80741ed0>] kernel_init_freeable+0x248/0x250
[    9.560000] [<805f5e1c>] kernel_init+0x14/0x110
[    9.570000] [<800066f8>] ret_from_kernel_thread+0x14/0x1c
[    9.580000] ---[ end trace 8d118b8e5f7182f5 ]---
[    9.750000] ------------[ cut here ]------------
[    9.750000] WARNING: CPU: 1 PID: 1 at ../drivers/ata/libahci.c:227 ahci_reset_controller+0xc8/0x128
[    9.770000] Modules linked in:
[    9.780000] CPU: 1 PID: 1 Comm: swapper/0 Tainted: G        W         4.18.0-rc7+ #277
[    9.790000] Stack : 00000000 00000004 00000006 00000000 00000000 00000000 00000000 00000000
[    9.810000]         80da7a3e 0000004a 00000000 00000000 80710000 00000001 9bc73b48 1c044177
[    9.830000]         00000000 00000000 80de0000 00000007 00000000 0000012a 00000000 00000000
[    9.840000]         00000000 00000129 80dd0000 65726568 80710000 00000000 80730000 806dc1fc
[    9.860000]         00000009 000000e3 00000005 9a0a8000 00000001 803a0508 00000004 80da0004
[    9.880000]         ...
[    9.880000] Call Trace:
[    9.890000] [<8000bd34>] show_stack+0x8c/0x130
[    9.900000] [<805dd684>] dump_stack+0x94/0xd0
[    9.900000] [<80027c30>] __warn+0x10c/0x114
[    9.910000] [<80027ce0>] warn_slowpath_null+0x44/0x58
[    9.920000] [<803f6e48>] ahci_reset_controller+0xc8/0x128
[    9.930000] [<803f4fb4>] ahci_init_one+0x824/0xa40
[    9.940000] [<80371cf0>] pci_device_probe+0x90/0x120
[    9.950000] [<803aff10>] driver_probe_device+0x314/0x46c
[    9.960000] [<803b011c>] __driver_attach+0xb4/0x138
[    9.970000] [<803ad9c0>] bus_for_each_dev+0x6c/0xb0
[    9.980000] [<803aebf8>] bus_add_driver+0x204/0x24c
[    9.990000] [<803b0a68>] driver_register+0xd0/0x118
[   10.000000] [<80001618>] do_one_initcall+0x84/0x19c
[   10.010000] [<80741ed0>] kernel_init_freeable+0x248/0x250
[   10.020000] [<805f5e1c>] kernel_init+0x14/0x110
[   10.030000] [<800066f8>] ret_from_kernel_thread+0x14/0x1c
[   10.040000] ---[ end trace 8d118b8e5f7182f6 ]---
[   10.050000] ahci 0000:01:00.0: AHCI 0000.0000 1 slots 1 ports ? Gbps 0x1 impl IDE mode
[   10.070000] ahci 0000:01:00.0: flags: 
[   10.080000] scsi host0: ahci
[   10.090000] ata1: SATA max UDMA/133 abar m512@0x60000000 port 0x60000100 irq 23
[   10.100000] pci 0000:00:01.0: enabling device (0004 -> 0006)
[   10.120000] ahci 0000:02:00.0: enabling device (0000 -> 0002)
[   10.280000] ------------[ cut here ]------------
[   10.280000] WARNING: CPU: 1 PID: 1 at ../drivers/ata/libahci.c:227 ahci_save_initial_config+0x3c/0x3e0
[   10.300000] Modules linked in:
[   10.310000] CPU: 1 PID: 1 Comm: swapper/0 Tainted: G        W         4.18.0-rc7+ #277
[   10.320000] Stack : 00000000 00000004 00000006 00000000 00000000 00000000 00000000 00000000
[   10.340000]         80da7a3e 0000004a 00000000 00000000 80710000 00000001 9bc73b40 1c044177
[   10.360000]         00000000 00000000 80de0000 00000007 00000000 0000014c 00000000 00000000
[   10.370000]         00000000 0000014b 80dd0000 65726568 80710000 00000000 80730000 806dc1fc
[   10.390000]         00000009 000000e3 00000005 00000000 00000001 803a0508 00000004 80da0004
[   10.410000]         ...
[   10.410000] Call Trace:
[   10.420000] [<8000bd34>] show_stack+0x8c/0x130
[   10.430000] [<805dd684>] dump_stack+0x94/0xd0
[   10.430000] [<80027c30>] __warn+0x10c/0x114
[   10.440000] [<80027ce0>] warn_slowpath_null+0x44/0x58
[   10.450000] [<803f696c>] ahci_save_initial_config+0x3c/0x3e0
[   10.460000] [<803f4bfc>] ahci_init_one+0x46c/0xa40
[   10.470000] [<80371cf0>] pci_device_probe+0x90/0x120
[   10.480000] [<803aff10>] driver_probe_device+0x314/0x46c
[   10.490000] [<803b011c>] __driver_attach+0xb4/0x138
[   10.500000] [<803ad9c0>] bus_for_each_dev+0x6c/0xb0
[   10.510000] [<803aebf8>] bus_add_driver+0x204/0x24c
[   10.520000] [<803b0a68>] driver_register+0xd0/0x118
[   10.530000] [<80001618>] do_one_initcall+0x84/0x19c
[   10.540000] [<80741ed0>] kernel_init_freeable+0x248/0x250
[   10.550000] [<805f5e1c>] kernel_init+0x14/0x110
[   10.560000] [<800066f8>] ret_from_kernel_thread+0x14/0x1c
[   10.570000] ---[ end trace 8d118b8e5f7182f7 ]---
[   10.580000] ahci 0000:02:00.0: forcing PORTS_IMPL to 0x1
[   10.740000] ------------[ cut here ]------------
[   10.740000] WARNING: CPU: 1 PID: 1 at ../drivers/ata/libahci.c:227 ahci_reset_controller+0x2c/0x128
[   10.760000] Modules linked in:
[   10.770000] CPU: 1 PID: 1 Comm: swapper/0 Tainted: G        W         4.18.0-rc7+ #277
[   10.780000] Stack : 00000000 00000004 00000006 00000000 00000000 00000000 00000000 00000000
[   10.800000]         80da7a3e 0000004a 00000000 00000000 80710000 00000001 9bc73b48 1c044177
[   10.820000]         00000000 00000000 80de0000 00000007 00000000 00000169 00000000 00000000
[   10.830000]         00000000 00000168 80dd0000 65726568 80710000 00000000 80730000 806dc1fc
[   10.850000]         00000009 000000e3 00000005 9a0ac000 00000001 803a0508 00000004 80da0004
[   10.870000]         ...
[   10.870000] Call Trace:
[   10.880000] [<8000bd34>] show_stack+0x8c/0x130
[   10.890000] [<805dd684>] dump_stack+0x94/0xd0
[   10.890000] [<80027c30>] __warn+0x10c/0x114
[   10.900000] [<80027ce0>] warn_slowpath_null+0x44/0x58
[   10.910000] [<803f6dac>] ahci_reset_controller+0x2c/0x128
[   10.920000] [<803f4fb4>] ahci_init_one+0x824/0xa40
[   10.930000] [<80371cf0>] pci_device_probe+0x90/0x120
[   10.940000] [<803aff10>] driver_probe_device+0x314/0x46c
[   10.950000] [<803b011c>] __driver_attach+0xb4/0x138
[   10.960000] [<803ad9c0>] bus_for_each_dev+0x6c/0xb0
[   10.970000] [<803aebf8>] bus_add_driver+0x204/0x24c
[   10.980000] [<803b0a68>] driver_register+0xd0/0x118
[   10.990000] [<80001618>] do_one_initcall+0x84/0x19c
[   11.000000] [<80741ed0>] kernel_init_freeable+0x248/0x250
[   11.010000] [<805f5e1c>] kernel_init+0x14/0x110
[   11.020000] [<800066f8>] ret_from_kernel_thread+0x14/0x1c
[   11.030000] ---[ end trace 8d118b8e5f7182f8 ]---
[   11.190000] ------------[ cut here ]------------
[   11.190000] WARNING: CPU: 1 PID: 1 at ../drivers/ata/libahci.c:227 ahci_reset_controller+0xc8/0x128
[   11.210000] ata1: failed to resume link (SControl 0)
[   11.210000] Modules linked in:
[   11.220000] ata1: SATA link down (SStatus 0 SControl 0)
[   11.230000] CPU: 1 PID: 1 Comm: swapper/0 Tainted: G        W         4.18.0-rc7+ #277
[   11.250000] Stack : 00000000 00000004 00000006 00000000 00000000 00000000 00000000 00000000
[   11.270000]         80da7a3e 0000004a 00000000 00000000 80710000 00000001 9bc73b48 1c044177
[   11.290000]         00000000 00000000 80de0000 00000007 00000000 00000187 00000000 00000000
[   11.300000]         00000000 00000186 80dd0000 65726568 80710000 00000000 80730000 806dc1fc
[   11.320000]         00000009 000000e3 00000005 9a0ac000 00000001 803a0508 00000004 80da0004
[   11.340000]         ...
[   11.340000] Call Trace:
[   11.350000] [<8000bd34>] show_stack+0x8c/0x130
[   11.360000] [<805dd684>] dump_stack+0x94/0xd0
[   11.360000] [<80027c30>] __warn+0x10c/0x114
[   11.370000] [<80027ce0>] warn_slowpath_null+0x44/0x58
[   11.380000] [<803f6e48>] ahci_reset_controller+0xc8/0x128
[   11.390000] [<803f4fb4>] ahci_init_one+0x824/0xa40
[   11.400000] [<80371cf0>] pci_device_probe+0x90/0x120
[   11.410000] [<803aff10>] driver_probe_device+0x314/0x46c
[   11.420000] [<803b011c>] __driver_attach+0xb4/0x138
[   11.430000] [<803ad9c0>] bus_for_each_dev+0x6c/0xb0
[   11.440000] [<803aebf8>] bus_add_driver+0x204/0x24c
[   11.450000] [<803b0a68>] driver_register+0xd0/0x118
[   11.460000] [<80001618>] do_one_initcall+0x84/0x19c
[   11.470000] [<80741ed0>] kernel_init_freeable+0x248/0x250
[   11.480000] [<805f5e1c>] kernel_init+0x14/0x110
[   11.490000] [<800066f8>] ret_from_kernel_thread+0x14/0x1c
[   11.500000] ---[ end trace 8d118b8e5f7182f9 ]---
[   11.510000] ahci 0000:02:00.0: AHCI 0000.0000 1 slots 1 ports ? Gbps 0x1 impl IDE mode
[   11.530000] ahci 0000:02:00.0: flags: 
[   11.540000] scsi host1: ahci
[   11.550000] ata2: SATA max UDMA/133 abar m512@0x60200000 port 0x60200100 irq 24
[   11.560000] pci 0000:00:02.0: enabling device (0004 -> 0006)
[   11.570000] ahci 0000:03:00.0: enabling device (0000 -> 0002)
[   11.740000] ------------[ cut here ]------------
[   11.740000] WARNING: CPU: 1 PID: 1 at ../drivers/ata/libahci.c:227 ahci_save_initial_config+0x3c/0x3e0
[   11.760000] Modules linked in:
[   11.770000] CPU: 1 PID: 1 Comm: swapper/0 Tainted: G        W         4.18.0-rc7+ #277
[   11.780000] Stack : 00000000 00000004 00000006 00000000 00000000 00000000 00000000 00000000
[   11.800000]         80da7a3e 0000004a 00000000 00000000 80710000 00000001 9bc73b40 1c044177
[   11.820000]         00000000 00000000 80de0000 00000007 00000000 000001a9 00000000 00000000
[   11.830000]         00000000 000001a8 80dd0000 65726568 80710000 00000000 80730000 806dc1fc
[   11.850000]         00000009 000000e3 00000005 00000000 00000001 803a0508 00000004 80da0004
[   11.870000]         ...
[   11.870000] Call Trace:
[   11.880000] [<8000bd34>] show_stack+0x8c/0x130
[   11.890000] [<805dd684>] dump_stack+0x94/0xd0
[   11.890000] [<80027c30>] __warn+0x10c/0x114
[   11.900000] [<80027ce0>] warn_slowpath_null+0x44/0x58
[   11.910000] [<803f696c>] ahci_save_initial_config+0x3c/0x3e0
[   11.920000] [<803f4bfc>] ahci_init_one+0x46c/0xa40
[   11.930000] [<80371cf0>] pci_device_probe+0x90/0x120
[   11.940000] [<803aff10>] driver_probe_device+0x314/0x46c
[   11.950000] [<803b011c>] __driver_attach+0xb4/0x138
[   11.960000] [<803ad9c0>] bus_for_each_dev+0x6c/0xb0
[   11.970000] [<803aebf8>] bus_add_driver+0x204/0x24c
[   11.980000] [<803b0a68>] driver_register+0xd0/0x118
[   11.990000] [<80001618>] do_one_initcall+0x84/0x19c
[   12.000000] [<80741ed0>] kernel_init_freeable+0x248/0x250
[   12.010000] [<805f5e1c>] kernel_init+0x14/0x110
[   12.020000] [<800066f8>] ret_from_kernel_thread+0x14/0x1c
[   12.030000] ---[ end trace 8d118b8e5f7182fa ]---
[   12.040000] ahci 0000:03:00.0: forcing PORTS_IMPL to 0x1
[   12.200000] ------------[ cut here ]------------
[   12.200000] WARNING: CPU: 1 PID: 1 at ../drivers/ata/libahci.c:227 ahci_reset_controller+0x2c/0x128
[   12.220000] Modules linked in:
[   12.230000] CPU: 1 PID: 1 Comm: swapper/0 Tainted: G        W         4.18.0-rc7+ #277
[   12.240000] Stack : 00000000 00000004 00000006 00000000 00000000 00000000 00000000 00000000
[   12.260000]         80da7a3e 0000004a 00000000 00000000 80710000 00000001 9bc73b48 1c044177
[   12.280000]         00000000 00000000 80de0000 00000007 00000000 000001c6 00000000 00000000
[   12.290000]         00000000 000001c5 80dd0000 65726568 80710000 00000000 80730000 806dc1fc
[   12.310000]         00000009 000000e3 00000005 9a104000 00000001 803a0508 00000004 80da0004
[   12.330000]         ...
[   12.330000] Call Trace:
[   12.340000] [<8000bd34>] show_stack+0x8c/0x130
[   12.350000] [<805dd684>] dump_stack+0x94/0xd0
[   12.350000] [<80027c30>] __warn+0x10c/0x114
[   12.360000] [<80027ce0>] warn_slowpath_null+0x44/0x58
[   12.370000] [<803f6dac>] ahci_reset_controller+0x2c/0x128
[   12.380000] [<803f4fb4>] ahci_init_one+0x824/0xa40
[   12.390000] [<80371cf0>] pci_device_probe+0x90/0x120
[   12.400000] [<803aff10>] driver_probe_device+0x314/0x46c
[   12.410000] [<803b011c>] __driver_attach+0xb4/0x138
[   12.420000] [<803ad9c0>] bus_for_each_dev+0x6c/0xb0
[   12.430000] [<803aebf8>] bus_add_driver+0x204/0x24c
[   12.440000] [<803b0a68>] driver_register+0xd0/0x118
[   12.450000] [<80001618>] do_one_initcall+0x84/0x19c
[   12.460000] [<80741ed0>] kernel_init_freeable+0x248/0x250
[   12.470000] [<805f5e1c>] kernel_init+0x14/0x110
[   12.480000] [<800066f8>] ret_from_kernel_thread+0x14/0x1c
[   12.490000] ---[ end trace 8d118b8e5f7182fb ]---
[   12.660000] ------------[ cut here ]------------
[   12.660000] ata2: failed to resume link (SControl 0)
[   12.660000] ata2: SATA link down (SStatus 0 SControl 0)
[   12.660000] WARNING: CPU: 1 PID: 1 at ../drivers/ata/libahci.c:227 ahci_reset_controller+0xc8/0x128
[   12.700000] Modules linked in:
[   12.710000] CPU: 1 PID: 1 Comm: swapper/0 Tainted: G        W         4.18.0-rc7+ #277
[   12.720000] Stack : 00000000 00000004 00000006 00000000 00000000 00000000 00000000 00000000
[   12.740000]         80da7a3e 0000004a 00000000 00000000 80710000 00000001 9bc73b48 1c044177
[   12.760000]         00000000 00000000 80de0000 00000007 00000000 000001e4 00000000 00000000
[   12.770000]         00000000 000001e3 80dd0000 65726568 80710000 00000000 80730000 806dc1fc
[   12.790000]         00000009 000000e3 00000005 9a104000 00000001 803a0508 00000004 80da0004
[   12.810000]         ...
[   12.810000] Call Trace:
[   12.820000] [<8000bd34>] show_stack+0x8c/0x130
[   12.830000] [<805dd684>] dump_stack+0x94/0xd0
[   12.830000] [<80027c30>] __warn+0x10c/0x114
[   12.840000] [<80027ce0>] warn_slowpath_null+0x44/0x58
[   12.850000] [<803f6e48>] ahci_reset_controller+0xc8/0x128
[   12.860000] [<803f4fb4>] ahci_init_one+0x824/0xa40
[   12.870000] [<80371cf0>] pci_device_probe+0x90/0x120
[   12.880000] [<803aff10>] driver_probe_device+0x314/0x46c
[   12.890000] [<803b011c>] __driver_attach+0xb4/0x138
[   12.900000] [<803ad9c0>] bus_for_each_dev+0x6c/0xb0
[   12.910000] [<803aebf8>] bus_add_driver+0x204/0x24c
[   12.920000] [<803b0a68>] driver_register+0xd0/0x118
[   12.930000] [<80001618>] do_one_initcall+0x84/0x19c
[   12.940000] [<80741ed0>] kernel_init_freeable+0x248/0x250
[   12.950000] [<805f5e1c>] kernel_init+0x14/0x110
[   12.960000] [<800066f8>] ret_from_kernel_thread+0x14/0x1c
[   12.970000] ---[ end trace 8d118b8e5f7182fc ]---
[   12.980000] ahci 0000:03:00.0: AHCI 0000.0000 1 slots 1 ports ? Gbps 0x1 impl IDE mode
[   13.000000] ahci 0000:03:00.0: flags: 
[   13.010000] scsi host2: ahci
[   13.020000] ata3: SATA max UDMA/133 abar m512@0x60400000 port 0x60400100 irq 25
[   13.040000] libphy: Fixed MDIO Bus: probed
[   13.050000] tun: Universal TUN/TAP device driver, 1.6
[   13.060000] sdhci: Secure Digital Host Controller Interface driver
[   13.070000] sdhci: Copyright(c) Pierre Ossman
[   13.080000] spi-mt7621 1e000b00.spi: sys_freq: 225000000
[   13.100000] m25p80 spi0.0: w25q256 (32768 Kbytes)
[   13.110000] 4 fixed-partitions partitions found on MTD device spi0.0
[   13.120000] Creating 4 MTD partitions on "spi0.0":
[   13.130000] 0x000000000000-0x000000030000 : "u-boot"
[   13.150000] 0x000000030000-0x000000040000 : "u-boot-env"
[   13.160000] 0x000000040000-0x000000050000 : "factory"
[   13.180000] 0x000000050000-0x000002000000 : "firmware"
[   13.250000] libphy: mdio: probed
[   13.280000] mtk_soc_eth 1e100000.ethernet: generated random MAC address ce:c3:44:0e:5b:90
[   13.300000] mtk_soc_eth 1e100000.ethernet eth0: mediatek frame engine at 0xbe100000, irq 21
[   13.330000] NET: Registered protocol family 10
[   13.350000] Segment Routing with IPv6
[   13.360000] NET: Registered protocol family 17
[   13.370000] 8021q: 802.1Q VLAN Support v1.8
[   13.380000] Loading compiled-in X.509 certificates
[   13.400000] hctosys: unable to open rtc device (rtc0)
[   13.450000] mmc0: new high speed SD card at address 0002
[   13.480000] mmcblk0: mmc0:0002 00000 1.88 GiB 
[   14.140000] ata3: failed to resume link (SControl 0)
[   14.140000] ata3: SATA link down (SStatus 0 SControl 0)
[   14.180000] Freeing unused kernel memory: 6524K
[   14.190000] This architecture does not have kernel memory protection.
[   14.410000] usbcore: registered new interface driver usbfs
[   14.430000] usbcore: registered new interface driver hub
[   14.450000] usbcore: registered new device driver usb
[   14.560000] xhci-mtk 1e1c0000.xhci: xHCI Host Controller
[   14.570000] xhci-mtk 1e1c0000.xhci: new USB bus registered, assigned bus number 1
[   14.590000] xhci-mtk 1e1c0000.xhci: hcc params 0x01401198 hci version 0x96 quirks 0x0000000000210010
[   14.610000] xhci-mtk 1e1c0000.xhci: irq 20, io mem 0x1e1c0000
[   14.650000] hub 1-0:1.0: USB hub found
[   14.660000] hub 1-0:1.0: 2 ports detected
[   14.680000] xhci-mtk 1e1c0000.xhci: xHCI Host Controller
[   14.690000] xhci-mtk 1e1c0000.xhci: new USB bus registered, assigned bus number 2
[   14.710000] xhci-mtk 1e1c0000.xhci: Host supports USB 3.0  SuperSpeed
[   14.730000] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
[   14.760000] hub 2-0:1.0: USB hub found
[   14.770000] hub 2-0:1.0: 1 port detected
[   14.830000] usbcore: registered new interface driver usb-storage
[   15.190000] Waiting disk spinup and searching for partition GNUBEE-ROOT...
[   15.200000] usb 1-2: new high-speed USB device number 2 using xhci-mtk
[   15.420000] hub 1-2:1.0: USB hub found
[   15.430000] hub 1-2:1.0: 4 ports detected
[   15.650000] mtk_soc_eth 1e100000.ethernet eth0: port 0 link up
[   18.220000] done.
mdadm: No devices listed in conf file were found.
[   19.470000] msdc0 -> TUNE_BREAD<PASS> dcrc<0x0> DATRDDLY0/1<0x10101010><0x0> dsmpl<0x0> <- msdc_tune_bread() : L<1342> PID<kworker/3:0H><0x1c>
findfs: unable to resolve 'PARTLABEL=GNUBEE-CRYPT-ROOT'
[   19.790000] EXT4-fs (mmcblk0): INFO: recovery required on readonly filesystem
[   19.800000] EXT4-fs (mmcblk0): write access will be enabled during recovery
[   22.430000] EXT4-fs (mmcblk0): recovery complete
[   22.450000] EXT4-fs (mmcblk0): mounted filesystem with ordered data mode. Opts: (null)
[   22.480000] Partition GNUBEE-ROOT found. Starting...
[   23.910000] systemd[1]: System time before build time, advancing clock.
[   24.060000] random: systemd: uninitialized urandom read (16 bytes read)
[   24.090000] systemd[1]: systemd 232 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +SECCOMP +BLKID +ELFUTILS +KMOD +IDN)
[   24.130000] systemd[1]: Detected architecture mips.

Welcome to Debian GNU/Linux 9 (stretch)!

[   24.190000] systemd[1]: Set hostname to <gnubeaver.brown>.
[   24.320000] random: systemd: uninitialized urandom read (16 bytes read)
[   24.370000] random: systemd-gpt-aut: uninitialized urandom read (16 bytes read)
[   25.100000] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
[  OK  ] Started Dispatch Password Requests to Console Directory Watch.
[   25.160000] systemd[1]: Created slice System Slice.
[  OK  ] Created slice System Slice.
[   25.210000] systemd[1]: Listening on udev Kernel Socket.
[  OK  ] Listening on udev Kernel Socket.
[   25.270000] systemd[1]: Mounting Debug File System...
         Mounting Debug File System...
[   25.320000] systemd[1]: Created slice system-getty.slice.
[  OK  ] Created slice system-getty.slice.
[   25.370000] systemd[1]: Listening on Syslog Socket.
[  OK  ] Listening on Syslog Socket.
[   25.420000] systemd[1]: Created slice User and Session Slice.
[  OK  ] Created slice User and Session Slice.
[  OK  ] Listening on /dev/initctl Compatibility Named Pipe.
[  OK  ] Listening on Journal Socket (/dev/log).
[  OK  ] Reached target Slices.
[  OK  ] Reached target Remote File Systems.
[  OK  ] Listening on Journal Socket.
[   25.650000] random: crng init done
[   25.660000] random: 7 urandom warning(s) missed due to ratelimiting
         Starting Create list of required st…ce nodes for the current kernel...
         Starting Load Kernel Modules...
         Starting Set the console keyboard layout...
[  OK  ] Listening on fsck to fsckd communication Socket.
         Starting File System Check on Root Device...
[  OK  ] Created slice system-serial\x2dgetty.slice.
[  OK  ] Listening on udev Control Socket.
[  OK  ] Reached target Swap.
         Starting Journal Service...
[  OK  ] Started Forward Password Requests to Wall Directory Watch.
[  OK  ] Reached target Paths.
[  OK  ] Reached target Encrypted Volumes.
[  OK  ] Mounted Debug File System.
[  OK  ] Started Create list of required sta…vice nodes for the current kernel.
[  OK  ] Started Load Kernel Modules.
[  OK  ] Started File System Check on Root Device.
[  OK  ] Started File System Check Daemon to report status.
         Starting Remount Root and Kernel File Systems...
         Starting Apply Kernel Variables...
         Starting Create Static Device Nodes in /dev...
[  OK  ] Started Set the console keyboard layout.
[  OK  ] Started Apply Kernel Variables.
[  OK  ] Started Create Static Device Nodes in /dev.
[   26.920000] EXT4-fs (mmcblk0): re-mounted. Opts: errors=remount-ro
         Starting udev Kernel Device Manager...
[  OK  ] Started Remount Root and Kernel File Systems.
         Starting udev Coldplug all Devices...
         Starting Load/Save Random Seed...
[  OK  ] Reached target Local File Systems (Pre).
[  OK  ] Reached target Local File Systems.
         Starting Raise network interfaces...
         Starting Set console font and keymap...
[  OK  ] Started Journal Service.
[  OK  ] Started udev Kernel Device Manager.
[  OK  ] Started Load/Save Random Seed.
[  OK  ] Started Set console font and keymap.
         Starting Flush Journal to Persistent Storage...
[   27.900000] systemd-journald[647]: Received request to flush runtime journal from PID 1
[  OK  ] Started Flush Journal to Persistent Storage.
         Starting Create Volatile Files and Directories...
[  OK  ] Started udev Coldplug all Devices.
[  OK  ] Started Create Volatile Files and Directories.
[  OK  ] Found device /dev/ttyS0.
[  OK  ] Listening on Load/Save RF Kill Switch Status /dev/rfkill Watch.
         Starting Network Time Synchronization...
         Starting Update UTMP about System Boot/Shutdown...
[  OK  ] Started Update UTMP about System Boot/Shutdown.
[  OK  ] Started Network Time Synchronization.
[  OK  ] Reached target System Initialization.
[  OK  ] Started Daily Cleanup of Temporary Directories.
[  OK  ] Listening on D-Bus System Message Bus Socket.
[  OK  ] Reached target Sockets.
[  OK  ] Reached target Basic System.
[   29.840000] IPv6: ADDRCONF(NETDEV_UP): eth0: link is not ready
[   29.850000] IPv6: ADDRCONF(NETDEV_CHANGE): eth0: link becomes ready
[  OK  ] Started Regular background program processing daemon.
         Starting System Logging Service...
[  OK  ] Started Self Monitoring and Reporting Technology (SMART) Daemon.
[  OK  ] Started D-Bus System Message Bus.
         Starting Login Service...
         Starting LSB: Execute the kexec -e command to reboot system...
         Starting LSB: Mount debugfs on /sys/kernel/debug...
[  OK  ] Reached target System Time Synchronized.
[  OK  ] Started Daily apt download activities.
[  OK  ] Started Daily apt upgrade and clean activities.
[  OK  ] Reached target Timers.
[  OK  ] Started System Logging Service.
[  OK  ] Started LSB: Execute the kexec -e command to reboot system.
         Starting LSB: Load kernel image with kexec...
[  OK  ] Started Login Service.
[  OK  ] Started LSB: Mount debugfs on /sys/kernel/debug.
[  OK  ] Started LSB: Load kernel image with kexec.
[FAILED] Failed to start Raise network interfaces.
See 'systemctl status networking.service' for details.
[  OK  ] Reached target Network.
         Starting OpenBSD Secure Shell server...
[  OK  ] Started BIND Domain Name Server.
[  OK  ] Reached target Host and Network Name Lookups.
         Starting Permit User Sessions...
         Starting The Apache HTTP Server...
[  OK  ] Reached target Network is Online.
         Starting LSB: Advanced IEEE 802.11 management daemon...
         Starting LSB: exim Mail Transport Agent...
         Starting /etc/rc.local Compatibility...
         Starting LSB: DHCP server...
[  OK  ] Started Permit User Sessions.
[  OK  ] Started LSB: Advanced IEEE 802.11 management daemon.
[  OK  ] Started OpenBSD Secure Shell server.
[  OK  ] Started The Apache HTTP Server.
[FAILED] Failed to start LSB: DHCP server.
See 'systemctl status isc-dhcp-server.service' for details.
[  OK  ] Started LSB: exim Mail Transport Agent.
[   45.857040] rc.local[923]:  3 Aug 14:32:11 ntpdate[928]: step time server 220.233.156.30 offset 109341.916405 sec
[  OK  ] Started /etc/rc.local Compatibility.
[  OK  ] Started Serial Getty on ttyS0.
[  OK  ] Reached target Login Prompts.
[  OK  ] Reached target Multi-User System.
[  OK  ] Reached target Graphical Interface.
         Starting Update UTMP about System Runlevel Changes...
         Starting Daily apt download activities...
[  OK  ] Started Update UTMP about System Runlevel Changes.

Debian GNU/Linux 9 gnubeaver.brown ttyS0

gnubeaver login: root
Password: 
Last login: Thu Aug  2 08:04:16 AEST 2018 on ttyS0
Linux gnubeaver.brown 4.18.0-rc7+ #277 SMP Fri Aug 3 14:30:02 AEST 2018 mips

The programs included with the Debian GNU/Linux system are free software;
the exact distribution terms for each program are described in the
individual files in /usr/share/doc/*/copyright.

Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
permitted by applicable law.
                                                                                                                                      resize: unknown character, exiting.
root@gnubeaver:~# lspci
00:00.0 PCI bridge: Device 0e8d:0801 (rev 01)
00:01.0 PCI bridge: Device 0e8d:0801 (rev 01)
00:02.0 PCI bridge: Device 0e8d:0801 (rev 01)
01:00.0 IDE interface: ASMedia Technology Inc. ASM1061 SATA IDE Controller (rev 02)
02:00.0 IDE interface: ASMedia Technology Inc. ASM1061 SATA IDE Controller (rev 02)
03:00.0 IDE interface: ASMedia Technology Inc. ASM1061 SATA IDE Controller (rev 02)
root@gnubeaver:~# 
root@gnubeaver:~# cat /proc/partitions 
major minor  #blocks  name

  31        0        192 mtdblock0
  31        1         64 mtdblock1
  31        2         64 mtdblock2
  31        3      32448 mtdblock3
 179        0    1974272 mmcblk0

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Re: [PATCH v9 00/15] staging: mt7621-pci: avoid custom pci config read and writes

[Sergio Paracuellos]

On Fri, Aug 03, 2018 at 02:33:22PM +1000, NeilBrown wrote:
> On Thu, Aug 02 2018, Sergio Paracuellos wrote:
> 
> > This patch series include an attempt to avoid the use of custom
> > read and writes in driver code and use PCI subsystem common ones.
> >
> > In order to do this 'map_bus' callback is implemented and also
> > data structures for driver are included. The regs base address
> > ranges and data is being readed from device tree and the driver
> > gets clean a lot of code.
> >
> > This patchet also removes all legacy PCI code using now PCI_DRIVERS_GENERIC
> > kernel api.
> >
> > Changes in v9:
> >     - PATCH 1: Use 'res' as resources list and void store resources in
> >       the pcie data struct.
> >     - PATCH 1: Rewrite 'mt7621_pci_parse_request_of_pci_ranges' to use
> >       'devm_of_pci_get_host_bridge_resources' and use 'remap' directly
> >       with the returned 'iobase' address instead of 'devm_pci_remap_iospace' 
> >       which get into a WARN_ONCE statement because 'PCI_IOBASE' is not
> >       defined for mips.
> >     - Other patches rebased and adapted to this changes.
> 
> You probably expected this, but still no change.

As always thanks for your time, Neil.

Not really I was expecting still not working (I am loosing my faith :-)) but 
avoid the first WARN_ON and see if root resources were properly listed using
the v8 code which I think is better. Anyway, the problem is with the io resource. 
When we call the function to get the resources 'devm_of_pci_get_host_bridge_resources' 
this ends up in a 'for_each_of_pci_range' parsing every range in the device tree 
and trying to get a resource from it calling to 'of_pci_range_to_resource' function. 
This function fails for the IO resource because of the call to 'pci_address_to_pio(range->cpu_addr);'
with an address (0x1e160000) which is greater than IO_SPACE_LIMIT (0xFFFF)
setting a 'OF_BAD_ADDR' for 'start' and 'end' in the resource and 
returns EINVAL which is get by 'devm_of_pci_get_host_bridge_resources' to just
don't add the resource to the list and 'continue' with the next range (without failing). 
So the difference with previous v7 and lower PATCHes version is that the system does not hang because
probably the increase of the ioport_resource (parent) memory range end limit to
0xFFFFFFFF. Why the legacy code works? Just because it just adds the range as a valid
resource and directly remaps to kernel virtual space the 'range.cpu_addr' to avoid the problem
when accesing from the ahci driver. That simple. So it seems that in this case with an
io address upper of IO_SPACE_LIMIT we cannot do nothing but little 'hack' the code to
get the 'map_bus' callback etc from generic pci api properly working (which cleans the code a lot),
but we cannot use some of other useful and cleaner functions. I am going to send hopefully last v10
which I really expect to work applying the things I am explaining here but we should think if
this is the only way to get this properly clean and working.

> Just for completeness boot log is below.
> 
> Thanks,
> NeilBrown
> 
> Starting kernel ...
> 
> [    0.000000] Linux version 4.18.0-rc7+ (neilb@noble) (gcc version 7.2.0 (GCC)) #277 SMP Fri Aug 3 14:30:02 AEST 2018
> [    0.000000] SoC Type: MediaTek MT7621 ver:1 eco:3
> [    0.000000] bootconsole [early0] enabled
> [    0.000000] CPU0 revision is: 0001992f (MIPS 1004Kc)
> [    0.000000] MIPS: machine is GB-PC1
> [    0.000000] Determined physical RAM map:
> [    0.000000]  memory: 1c000000 @ 00000000 (usable)
> [    0.000000]  memory: 04000000 @ 20000000 (usable)
> [    0.000000] Initrd not found or empty - disabling initrd
> [    0.000000] VPE topology {2,2} total 4
> [    0.000000] Primary instruction cache 32kB, VIPT, 4-way, linesize 32 bytes.
> [    0.000000] Primary data cache 32kB, 4-way, PIPT, no aliases, linesize 32 bytes
> [    0.000000] MIPS secondary cache 256kB, 8-way, linesize 32 bytes.
> [    0.000000] Zone ranges:
> [    0.000000]   Normal   [mem 0x0000000000000000-0x000000001fffffff]
> [    0.000000]   HighMem  [mem 0x0000000020000000-0x0000000023ffffff]
> [    0.000000] Movable zone start for each node
> [    0.000000] Early memory node ranges
> [    0.000000]   node   0: [mem 0x0000000000000000-0x000000001bffffff]
> [    0.000000]   node   0: [mem 0x0000000020000000-0x0000000023ffffff]
> [    0.000000] Initmem setup node 0 [mem 0x0000000000000000-0x0000000023ffffff]
> [    0.000000] random: get_random_bytes called from start_kernel+0xb4/0x4ec with crng_init=0
> [    0.000000] percpu: Embedded 15 pages/cpu @(ptrval) s30480 r8192 d22768 u61440
> [    0.000000] Built 1 zonelists, mobility grouping on.  Total pages: 130048
> [    0.000000] Kernel command line: console=ttyS0,57600
> [    0.000000] Dentry cache hash table entries: 65536 (order: 6, 262144 bytes)
> [    0.000000] Inode-cache hash table entries: 32768 (order: 5, 131072 bytes)
> [    0.000000] Writing ErrCtl register=000108a2
> [    0.000000] Readback ErrCtl register=000108a2
> [    0.000000] Memory: 504788K/524288K available (6135K kernel code, 228K rwdata, 1052K rodata, 6524K init, 241K bss, 19500K reserved, 0K cma-reserved, 65536K highmem)
> [    0.000000] SLUB: HWalign=32, Order=0-3, MinObjects=0, CPUs=4, Nodes=1
> [    0.000000] Hierarchical RCU implementation.
> [    0.000000] NR_IRQS: 256
> [    0.000000] clocksource: GIC: mask: 0xffffffffffffffff max_cycles: 0xcf914c9718, max_idle_ns: 440795231327 ns
> [    0.000000] sched_clock: 32 bits at 100 Hz, resolution 10000000ns, wraps every 21474836475000000ns
> [    0.010000] Calibrating delay loop... 597.60 BogoMIPS (lpj=2988032)
> [    0.070000] pid_max: default: 32768 minimum: 301
> [    0.080000] Mount-cache hash table entries: 1024 (order: 0, 4096 bytes)
> [    0.090000] Mountpoint-cache hash table entries: 1024 (order: 0, 4096 bytes)
> [    0.100000] Hierarchical SRCU implementation.
> [    0.110000] smp: Bringing up secondary CPUs ...
> [    0.120000] Primary instruction cache 32kB, VIPT, 4-way, linesize 32 bytes.
> [    0.120000] Primary data cache 32kB, 4-way, PIPT, no aliases, linesize 32 bytes
> [    0.120000] MIPS secondary cache 256kB, 8-way, linesize 32 bytes.
> [    0.120000] CPU1 revision is: 0001992f (MIPS 1004Kc)
> [    0.180000] Synchronize counters for CPU 1: done.
> [    0.220000] Primary instruction cache 32kB, VIPT, 4-way, linesize 32 bytes.
> [    0.220000] Primary data cache 32kB, 4-way, PIPT, no aliases, linesize 32 bytes
> [    0.220000] MIPS secondary cache 256kB, 8-way, linesize 32 bytes.
> [    0.220000] CPU2 revision is: 0001992f (MIPS 1004Kc)
> [    0.280000] Synchronize counters for CPU 2: done.
> [    0.320000] Primary instruction cache 32kB, VIPT, 4-way, linesize 32 bytes.
> [    0.320000] Primary data cache 32kB, 4-way, PIPT, no aliases, linesize 32 bytes
> [    0.320000] MIPS secondary cache 256kB, 8-way, linesize 32 bytes.
> [    0.320000] CPU3 revision is: 0001992f (MIPS 1004Kc)
> [    0.380000] Synchronize counters for CPU 3: done.
> [    0.420000] smp: Brought up 1 node, 4 CPUs
> [    0.430000] devtmpfs: initialized
> [    0.480000] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns
> [    0.490000] futex hash table entries: 1024 (order: 3, 32768 bytes)
> [    0.500000] pinctrl core: initialized pinctrl subsystem
> [    0.510000] NET: Registered protocol family 16
> [    0.870000] ***** Xtal 40MHz *****
> [    0.880000] Port 0 N_FTS = 1b102800
> [    0.890000] Port 1 N_FTS = 1b102800
> [    0.890000] Port 2 N_FTS = 1b102800
> [    1.950000] PCIE0 enabled
> [    1.960000] PCIE1 enabled
> [    1.960000] PCIE2 enabled
> [    1.970000] mt7621-pci 1e140000.pcie: host bridge /pcie@1e140000 ranges:
> [    1.980000] mt7621-pci 1e140000.pcie:   MEM 0x60000000..0x6fffffff -> 0x00000000
> [    2.000000] mt7621-pci 1e140000.pcie:    IO 0x1e160000..0x1e16ffff -> 0x00000000
> [    2.010000] PCI coherence region base: 0x60000000, mask/settings: 0xf0000002
> [    2.020000] mt7621-pci 1e140000.pcie: PCI host bridge to bus 0000:00
> [    2.040000] pci_bus 0000:00: root bus resource [bus 00-ff]
> [    2.050000] pci_bus 0000:00: root bus resource [mem 0x60000000-0x6fffffff] (bus address [0x00000000-0x0fffffff])

See... There is no 'root bus resource [io 0xFFFFFFFF]' ... here because of my previous explanation.

> [    2.070000] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
> [    2.090000] pci 0000:00:01.0: bridge configuration invalid ([bus 00-00]), reconfiguring
> [    2.100000] pci 0000:00:02.0: bridge configuration invalid ([bus 00-00]), reconfiguring
> [    2.120000] pci 0000:00:00.0: PCI bridge to [bus 01-ff]
> [    2.140000] pci 0000:00:01.0: PCI bridge to [bus 02-ff]
> [    2.150000] pci 0000:00:02.0: PCI bridge to [bus 03-ff]
> [    2.160000] pci 0000:00:00.0: BAR 0: no space for [mem size 0x80000000]
> [    2.170000] pci 0000:00:00.0: BAR 0: failed to assign [mem size 0x80000000]
> [    2.190000] pci 0000:00:01.0: BAR 0: no space for [mem size 0x80000000]
> [    2.200000] pci 0000:00:01.0: BAR 0: failed to assign [mem size 0x80000000]
> [    2.210000] pci 0000:00:02.0: BAR 0: no space for [mem size 0x80000000]
> [    2.230000] pci 0000:00:02.0: BAR 0: failed to assign [mem size 0x80000000]
> [    2.240000] pci 0000:00:00.0: BAR 8: assigned [mem 0x60000000-0x600fffff]
> [    2.250000] pci 0000:00:00.0: BAR 9: assigned [mem 0x60100000-0x601fffff pref]
> [    2.270000] pci 0000:00:01.0: BAR 8: assigned [mem 0x60200000-0x602fffff]
> [    2.280000] pci 0000:00:01.0: BAR 9: assigned [mem 0x60300000-0x603fffff pref]
> [    2.290000] pci 0000:00:02.0: BAR 8: assigned [mem 0x60400000-0x604fffff]
> [    2.310000] pci 0000:00:02.0: BAR 9: assigned [mem 0x60500000-0x605fffff pref]
> [    2.320000] pci 0000:00:00.0: BAR 1: assigned [mem 0x60600000-0x6060ffff]
> [    2.330000] pci 0000:00:01.0: BAR 1: assigned [mem 0x60610000-0x6061ffff]
> [    2.350000] pci 0000:00:02.0: BAR 1: assigned [mem 0x60620000-0x6062ffff]
> [    2.360000] pci 0000:00:00.0: BAR 7: no space for [io  size 0x1000]
> [    2.370000] pci 0000:00:00.0: BAR 7: failed to assign [io  size 0x1000]
> [    2.390000] pci 0000:00:01.0: BAR 7: no space for [io  size 0x1000]
> [    2.400000] pci 0000:00:01.0: BAR 7: failed to assign [io  size 0x1000]
> [    2.410000] pci 0000:00:02.0: BAR 7: no space for [io  size 0x1000]
> [    2.420000] pci 0000:00:02.0: BAR 7: failed to assign [io  size 0x1000]
> [    2.440000] pci 0000:01:00.0: BAR 5: assigned [mem 0x60000000-0x600001ff]
> [    2.450000] pci 0000:01:00.0: BAR 4: no space for [io  size 0x0010]
> [    2.460000] pci 0000:01:00.0: BAR 4: failed to assign [io  size 0x0010]
> [    2.480000] pci 0000:01:00.0: BAR 0: no space for [io  size 0x0008]
> [    2.490000] pci 0000:01:00.0: BAR 0: failed to assign [io  size 0x0008]
> [    2.500000] pci 0000:01:00.0: BAR 2: no space for [io  size 0x0008]
> [    2.510000] pci 0000:01:00.0: BAR 2: failed to assign [io  size 0x0008]
> [    2.530000] pci 0000:01:00.0: BAR 1: no space for [io  size 0x0004]
> [    2.540000] pci 0000:01:00.0: BAR 1: failed to assign [io  size 0x0004]
> [    2.550000] pci 0000:01:00.0: BAR 3: no space for [io  size 0x0004]
> [    2.560000] pci 0000:01:00.0: BAR 3: failed to assign [io  size 0x0004]
> [    2.580000] pci 0000:00:00.0: PCI bridge to [bus 01]
> [    2.590000] pci 0000:00:00.0:   bridge window [mem 0x60000000-0x600fffff]
> [    2.600000] pci 0000:00:00.0:   bridge window [mem 0x60100000-0x601fffff pref]
> [    2.610000] pci 0000:02:00.0: BAR 5: assigned [mem 0x60200000-0x602001ff]
> [    2.630000] pci 0000:02:00.0: BAR 4: no space for [io  size 0x0010]
> [    2.640000] pci 0000:02:00.0: BAR 4: failed to assign [io  size 0x0010]
> [    2.650000] pci 0000:02:00.0: BAR 0: no space for [io  size 0x0008]
> [    2.660000] pci 0000:02:00.0: BAR 0: failed to assign [io  size 0x0008]
> [    2.680000] pci 0000:02:00.0: BAR 2: no space for [io  size 0x0008]
> [    2.690000] pci 0000:02:00.0: BAR 2: failed to assign [io  size 0x0008]
> [    2.700000] pci 0000:02:00.0: BAR 1: no space for [io  size 0x0004]
> [    2.710000] pci 0000:02:00.0: BAR 1: failed to assign [io  size 0x0004]
> [    2.730000] pci 0000:02:00.0: BAR 3: no space for [io  size 0x0004]
> [    2.740000] pci 0000:02:00.0: BAR 3: failed to assign [io  size 0x0004]
> [    2.750000] pci 0000:00:01.0: PCI bridge to [bus 02]
> [    2.760000] pci 0000:00:01.0:   bridge window [mem 0x60200000-0x602fffff]
> [    2.780000] pci 0000:00:01.0:   bridge window [mem 0x60300000-0x603fffff pref]
> [    2.790000] pci 0000:03:00.0: BAR 5: assigned [mem 0x60400000-0x604001ff]
> [    2.800000] pci 0000:03:00.0: BAR 4: no space for [io  size 0x0010]
> [    2.820000] pci 0000:03:00.0: BAR 4: failed to assign [io  size 0x0010]
> [    2.830000] pci 0000:03:00.0: BAR 0: no space for [io  size 0x0008]
> [    2.840000] pci 0000:03:00.0: BAR 0: failed to assign [io  size 0x0008]
> [    2.850000] pci 0000:03:00.0: BAR 2: no space for [io  size 0x0008]
> [    2.870000] pci 0000:03:00.0: BAR 2: failed to assign [io  size 0x0008]
> [    2.880000] pci 0000:03:00.0: BAR 1: no space for [io  size 0x0004]
> [    2.890000] pci 0000:03:00.0: BAR 1: failed to assign [io  size 0x0004]
> [    2.900000] pci 0000:03:00.0: BAR 3: no space for [io  size 0x0004]
> [    2.920000] pci 0000:03:00.0: BAR 3: failed to assign [io  size 0x0004]
> [    2.930000] pci 0000:00:02.0: PCI bridge to [bus 03]
> [    2.940000] pci 0000:00:02.0:   bridge window [mem 0x60400000-0x604fffff]
> [    2.950000] pci 0000:00:02.0:   bridge window [mem 0x60500000-0x605fffff pref]
> [    3.030000] SCSI subsystem initialized
> [    3.040000] random: fast init done
> [    3.060000] clocksource: Switched to clocksource GIC
> [    3.090000] NET: Registered protocol family 2
> [    3.100000] tcp_listen_portaddr_hash hash table entries: 512 (order: 0, 6144 bytes)
> [    3.110000] TCP established hash table entries: 4096 (order: 2, 16384 bytes)
> [    3.130000] TCP bind hash table entries: 4096 (order: 3, 32768 bytes)
> [    3.140000] TCP: Hash tables configured (established 4096 bind 4096)
> [    3.150000] UDP hash table entries: 256 (order: 1, 8192 bytes)
> [    3.170000] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)
> [    3.180000] NET: Registered protocol family 1
> [    8.150000] Initialise system trusted keyrings
> [    8.160000] workingset: timestamp_bits=30 max_order=17 bucket_order=0
> [    8.290000] squashfs: version 4.0 (2009/01/31) Phillip Lougher
> [    8.310000] jffs2: version 2.2. (NAND) (SUMMARY)  © 2001-2006 Red Hat, Inc.
> [    8.330000] SGI XFS with security attributes, no debug enabled
> [    8.380000] Key type asymmetric registered
> [    8.390000] Asymmetric key parser 'x509' registered
> [    8.400000] bounce: pool size: 64 pages
> [    8.410000] io scheduler noop registered
> [    8.420000] io scheduler deadline registered (default)
> [    8.430000] io scheduler mq-deadline registered (default)
> [    8.440000] io scheduler kyber registered
> [    8.460000] Serial: 8250/16550 driver, 3 ports, IRQ sharing disabled
> [    8.480000] console [ttyS0] disabled
> [    8.490000] 1e000c00.uartlite: ttyS0 at MMIO 0x1e000c00 (irq = 18, base_baud = 3125000) is a 16550A
> [    8.500000] console [ttyS0] enabled
> [    8.500000] console [ttyS0] enabled
> [    8.520000] bootconsole [early0] disabled
> [    8.520000] bootconsole [early0] disabled
> [    8.540000] cacheinfo: Failed to find cpu0 device node
> [    8.550000] cacheinfo: Unable to detect cache hierarchy for CPU 0
> [    8.630000] loop: module loaded
> [    8.640000] pci 0000:00:00.0: enabling device (0004 -> 0006)
> [    8.650000] ahci 0000:01:00.0: enabling device (0000 -> 0002)
> [    8.830000] ------------[ cut here ]------------
> [    8.830000] WARNING: CPU: 1 PID: 1 at ../drivers/ata/libahci.c:227 ahci_save_initial_config+0x3c/0x3e0
> [    8.850000] Modules linked in:
> [    8.860000] CPU: 1 PID: 1 Comm: swapper/0 Not tainted 4.18.0-rc7+ #277
> [    8.870000] Stack : 00000000 00000004 00000006 00000000 00000000 00000000 00000000 00000000
> [    8.890000]         80da7a3e 0000003a 00000000 00000000 80710000 00000001 9bc73b40 1c044177
> [    8.910000]         00000000 00000000 80de0000 00000007 00000000 000000f1 00000000 00000000
> [    8.920000]         00000000 000000f0 80dd0000 65726568 80710000 00000000 80730000 806dc1fc
> [    8.940000]         00000009 000000e3 00000005 00000000 00000001 803a0508 00000004 80da0004
> [    8.950000]         ...
> [    8.960000] Call Trace:
> [    8.960000] [<8000bd34>] show_stack+0x8c/0x130
> [    8.970000] [<805dd684>] dump_stack+0x94/0xd0
> [    8.980000] [<80027c30>] __warn+0x10c/0x114
> [    8.990000] [<80027ce0>] warn_slowpath_null+0x44/0x58
> [    9.000000] [<803f696c>] ahci_save_initial_config+0x3c/0x3e0
> [    9.010000] [<803f4bfc>] ahci_init_one+0x46c/0xa40
> [    9.020000] [<80371cf0>] pci_device_probe+0x90/0x120
> [    9.030000] [<803aff10>] driver_probe_device+0x314/0x46c
> [    9.040000] [<803b011c>] __driver_attach+0xb4/0x138
> [    9.050000] [<803ad9c0>] bus_for_each_dev+0x6c/0xb0
> [    9.060000] [<803aebf8>] bus_add_driver+0x204/0x24c
> [    9.070000] [<803b0a68>] driver_register+0xd0/0x118
> [    9.080000] [<80001618>] do_one_initcall+0x84/0x19c
> [    9.090000] [<80741ed0>] kernel_init_freeable+0x248/0x250
> [    9.100000] [<805f5e1c>] kernel_init+0x14/0x110
> [    9.110000] [<800066f8>] ret_from_kernel_thread+0x14/0x1c
> [    9.120000] ---[ end trace 8d118b8e5f7182f4 ]---
> [    9.130000] ahci 0000:01:00.0: forcing PORTS_IMPL to 0x1
> [    9.290000] ------------[ cut here ]------------
> [    9.290000] WARNING: CPU: 1 PID: 1 at ../drivers/ata/libahci.c:227 ahci_reset_controller+0x2c/0x128
> [    9.310000] Modules linked in:
> [    9.320000] CPU: 1 PID: 1 Comm: swapper/0 Tainted: G        W         4.18.0-rc7+ #277
> [    9.330000] Stack : 00000000 00000004 00000006 00000000 00000000 00000000 00000000 00000000
> [    9.350000]         80da7a3e 0000004a 00000000 00000000 80710000 00000001 9bc73b48 1c044177
> [    9.370000]         00000000 00000000 80de0000 00000007 00000000 0000010e 00000000 00000000
> [    9.380000]         00000000 0000010d 80dd0000 65726568 80710000 00000000 80730000 806dc1fc
> [    9.400000]         00000009 000000e3 00000005 9a0a8000 00000001 803a0508 00000004 80da0004
> [    9.420000]         ...
> [    9.420000] Call Trace:
> [    9.430000] [<8000bd34>] show_stack+0x8c/0x130
> [    9.440000] [<805dd684>] dump_stack+0x94/0xd0
> [    9.440000] [<80027c30>] __warn+0x10c/0x114
> [    9.450000] [<80027ce0>] warn_slowpath_null+0x44/0x58
> [    9.460000] [<803f6dac>] ahci_reset_controller+0x2c/0x128
> [    9.470000] [<803f4fb4>] ahci_init_one+0x824/0xa40
> [    9.480000] [<80371cf0>] pci_device_probe+0x90/0x120
> [    9.490000] [<803aff10>] driver_probe_device+0x314/0x46c
> [    9.500000] [<803b011c>] __driver_attach+0xb4/0x138
> [    9.510000] [<803ad9c0>] bus_for_each_dev+0x6c/0xb0
> [    9.520000] [<803aebf8>] bus_add_driver+0x204/0x24c
> [    9.530000] [<803b0a68>] driver_register+0xd0/0x118
> [    9.540000] [<80001618>] do_one_initcall+0x84/0x19c
> [    9.550000] [<80741ed0>] kernel_init_freeable+0x248/0x250
> [    9.560000] [<805f5e1c>] kernel_init+0x14/0x110
> [    9.570000] [<800066f8>] ret_from_kernel_thread+0x14/0x1c
> [    9.580000] ---[ end trace 8d118b8e5f7182f5 ]---
> [    9.750000] ------------[ cut here ]------------
> [    9.750000] WARNING: CPU: 1 PID: 1 at ../drivers/ata/libahci.c:227 ahci_reset_controller+0xc8/0x128
> [    9.770000] Modules linked in:
> [    9.780000] CPU: 1 PID: 1 Comm: swapper/0 Tainted: G        W         4.18.0-rc7+ #277
> [    9.790000] Stack : 00000000 00000004 00000006 00000000 00000000 00000000 00000000 00000000
> [    9.810000]         80da7a3e 0000004a 00000000 00000000 80710000 00000001 9bc73b48 1c044177
> [    9.830000]         00000000 00000000 80de0000 00000007 00000000 0000012a 00000000 00000000
> [    9.840000]         00000000 00000129 80dd0000 65726568 80710000 00000000 80730000 806dc1fc
> [    9.860000]         00000009 000000e3 00000005 9a0a8000 00000001 803a0508 00000004 80da0004
> [    9.880000]         ...
> [    9.880000] Call Trace:
> [    9.890000] [<8000bd34>] show_stack+0x8c/0x130
> [    9.900000] [<805dd684>] dump_stack+0x94/0xd0
> [    9.900000] [<80027c30>] __warn+0x10c/0x114
> [    9.910000] [<80027ce0>] warn_slowpath_null+0x44/0x58
> [    9.920000] [<803f6e48>] ahci_reset_controller+0xc8/0x128
> [    9.930000] [<803f4fb4>] ahci_init_one+0x824/0xa40
> [    9.940000] [<80371cf0>] pci_device_probe+0x90/0x120
> [    9.950000] [<803aff10>] driver_probe_device+0x314/0x46c
> [    9.960000] [<803b011c>] __driver_attach+0xb4/0x138
> [    9.970000] [<803ad9c0>] bus_for_each_dev+0x6c/0xb0
> [    9.980000] [<803aebf8>] bus_add_driver+0x204/0x24c
> [    9.990000] [<803b0a68>] driver_register+0xd0/0x118
> [   10.000000] [<80001618>] do_one_initcall+0x84/0x19c
> [   10.010000] [<80741ed0>] kernel_init_freeable+0x248/0x250
> [   10.020000] [<805f5e1c>] kernel_init+0x14/0x110
> [   10.030000] [<800066f8>] ret_from_kernel_thread+0x14/0x1c
> [   10.040000] ---[ end trace 8d118b8e5f7182f6 ]---
> [   10.050000] ahci 0000:01:00.0: AHCI 0000.0000 1 slots 1 ports ? Gbps 0x1 impl IDE mode
> [   10.070000] ahci 0000:01:00.0: flags: 
> [   10.080000] scsi host0: ahci
> [   10.090000] ata1: SATA max UDMA/133 abar m512@0x60000000 port 0x60000100 irq 23
> [   10.100000] pci 0000:00:01.0: enabling device (0004 -> 0006)
> [   10.120000] ahci 0000:02:00.0: enabling device (0000 -> 0002)
> [   10.280000] ------------[ cut here ]------------
> [   10.280000] WARNING: CPU: 1 PID: 1 at ../drivers/ata/libahci.c:227 ahci_save_initial_config+0x3c/0x3e0
> [   10.300000] Modules linked in:
> [   10.310000] CPU: 1 PID: 1 Comm: swapper/0 Tainted: G        W         4.18.0-rc7+ #277
> [   10.320000] Stack : 00000000 00000004 00000006 00000000 00000000 00000000 00000000 00000000
> [   10.340000]         80da7a3e 0000004a 00000000 00000000 80710000 00000001 9bc73b40 1c044177
> [   10.360000]         00000000 00000000 80de0000 00000007 00000000 0000014c 00000000 00000000
> [   10.370000]         00000000 0000014b 80dd0000 65726568 80710000 00000000 80730000 806dc1fc
> [   10.390000]         00000009 000000e3 00000005 00000000 00000001 803a0508 00000004 80da0004
> [   10.410000]         ...
> [   10.410000] Call Trace:
> [   10.420000] [<8000bd34>] show_stack+0x8c/0x130
> [   10.430000] [<805dd684>] dump_stack+0x94/0xd0
> [   10.430000] [<80027c30>] __warn+0x10c/0x114
> [   10.440000] [<80027ce0>] warn_slowpath_null+0x44/0x58
> [   10.450000] [<803f696c>] ahci_save_initial_config+0x3c/0x3e0
> [   10.460000] [<803f4bfc>] ahci_init_one+0x46c/0xa40
> [   10.470000] [<80371cf0>] pci_device_probe+0x90/0x120
> [   10.480000] [<803aff10>] driver_probe_device+0x314/0x46c
> [   10.490000] [<803b011c>] __driver_attach+0xb4/0x138
> [   10.500000] [<803ad9c0>] bus_for_each_dev+0x6c/0xb0
> [   10.510000] [<803aebf8>] bus_add_driver+0x204/0x24c
> [   10.520000] [<803b0a68>] driver_register+0xd0/0x118
> [   10.530000] [<80001618>] do_one_initcall+0x84/0x19c
> [   10.540000] [<80741ed0>] kernel_init_freeable+0x248/0x250
> [   10.550000] [<805f5e1c>] kernel_init+0x14/0x110
> [   10.560000] [<800066f8>] ret_from_kernel_thread+0x14/0x1c
> [   10.570000] ---[ end trace 8d118b8e5f7182f7 ]---
> [   10.580000] ahci 0000:02:00.0: forcing PORTS_IMPL to 0x1
> [   10.740000] ------------[ cut here ]------------
> [   10.740000] WARNING: CPU: 1 PID: 1 at ../drivers/ata/libahci.c:227 ahci_reset_controller+0x2c/0x128
> [   10.760000] Modules linked in:
> [   10.770000] CPU: 1 PID: 1 Comm: swapper/0 Tainted: G        W         4.18.0-rc7+ #277
> [   10.780000] Stack : 00000000 00000004 00000006 00000000 00000000 00000000 00000000 00000000
> [   10.800000]         80da7a3e 0000004a 00000000 00000000 80710000 00000001 9bc73b48 1c044177
> [   10.820000]         00000000 00000000 80de0000 00000007 00000000 00000169 00000000 00000000
> [   10.830000]         00000000 00000168 80dd0000 65726568 80710000 00000000 80730000 806dc1fc
> [   10.850000]         00000009 000000e3 00000005 9a0ac000 00000001 803a0508 00000004 80da0004
> [   10.870000]         ...
> [   10.870000] Call Trace:
> [   10.880000] [<8000bd34>] show_stack+0x8c/0x130
> [   10.890000] [<805dd684>] dump_stack+0x94/0xd0
> [   10.890000] [<80027c30>] __warn+0x10c/0x114
> [   10.900000] [<80027ce0>] warn_slowpath_null+0x44/0x58
> [   10.910000] [<803f6dac>] ahci_reset_controller+0x2c/0x128
> [   10.920000] [<803f4fb4>] ahci_init_one+0x824/0xa40
> [   10.930000] [<80371cf0>] pci_device_probe+0x90/0x120
> [   10.940000] [<803aff10>] driver_probe_device+0x314/0x46c
> [   10.950000] [<803b011c>] __driver_attach+0xb4/0x138
> [   10.960000] [<803ad9c0>] bus_for_each_dev+0x6c/0xb0
> [   10.970000] [<803aebf8>] bus_add_driver+0x204/0x24c
> [   10.980000] [<803b0a68>] driver_register+0xd0/0x118
> [   10.990000] [<80001618>] do_one_initcall+0x84/0x19c
> [   11.000000] [<80741ed0>] kernel_init_freeable+0x248/0x250
> [   11.010000] [<805f5e1c>] kernel_init+0x14/0x110
> [   11.020000] [<800066f8>] ret_from_kernel_thread+0x14/0x1c
> [   11.030000] ---[ end trace 8d118b8e5f7182f8 ]---
> [   11.190000] ------------[ cut here ]------------
> [   11.190000] WARNING: CPU: 1 PID: 1 at ../drivers/ata/libahci.c:227 ahci_reset_controller+0xc8/0x128
> [   11.210000] ata1: failed to resume link (SControl 0)
> [   11.210000] Modules linked in:
> [   11.220000] ata1: SATA link down (SStatus 0 SControl 0)
> [   11.230000] CPU: 1 PID: 1 Comm: swapper/0 Tainted: G        W         4.18.0-rc7+ #277
> [   11.250000] Stack : 00000000 00000004 00000006 00000000 00000000 00000000 00000000 00000000
> [   11.270000]         80da7a3e 0000004a 00000000 00000000 80710000 00000001 9bc73b48 1c044177
> [   11.290000]         00000000 00000000 80de0000 00000007 00000000 00000187 00000000 00000000
> [   11.300000]         00000000 00000186 80dd0000 65726568 80710000 00000000 80730000 806dc1fc
> [   11.320000]         00000009 000000e3 00000005 9a0ac000 00000001 803a0508 00000004 80da0004
> [   11.340000]         ...
> [   11.340000] Call Trace:
> [   11.350000] [<8000bd34>] show_stack+0x8c/0x130
> [   11.360000] [<805dd684>] dump_stack+0x94/0xd0
> [   11.360000] [<80027c30>] __warn+0x10c/0x114
> [   11.370000] [<80027ce0>] warn_slowpath_null+0x44/0x58
> [   11.380000] [<803f6e48>] ahci_reset_controller+0xc8/0x128
> [   11.390000] [<803f4fb4>] ahci_init_one+0x824/0xa40
> [   11.400000] [<80371cf0>] pci_device_probe+0x90/0x120
> [   11.410000] [<803aff10>] driver_probe_device+0x314/0x46c
> [   11.420000] [<803b011c>] __driver_attach+0xb4/0x138
> [   11.430000] [<803ad9c0>] bus_for_each_dev+0x6c/0xb0
> [   11.440000] [<803aebf8>] bus_add_driver+0x204/0x24c
> [   11.450000] [<803b0a68>] driver_register+0xd0/0x118
> [   11.460000] [<80001618>] do_one_initcall+0x84/0x19c
> [   11.470000] [<80741ed0>] kernel_init_freeable+0x248/0x250
> [   11.480000] [<805f5e1c>] kernel_init+0x14/0x110
> [   11.490000] [<800066f8>] ret_from_kernel_thread+0x14/0x1c
> [   11.500000] ---[ end trace 8d118b8e5f7182f9 ]---
> [   11.510000] ahci 0000:02:00.0: AHCI 0000.0000 1 slots 1 ports ? Gbps 0x1 impl IDE mode
> [   11.530000] ahci 0000:02:00.0: flags: 
> [   11.540000] scsi host1: ahci
> [   11.550000] ata2: SATA max UDMA/133 abar m512@0x60200000 port 0x60200100 irq 24
> [   11.560000] pci 0000:00:02.0: enabling device (0004 -> 0006)
> [   11.570000] ahci 0000:03:00.0: enabling device (0000 -> 0002)
> [   11.740000] ------------[ cut here ]------------
> [   11.740000] WARNING: CPU: 1 PID: 1 at ../drivers/ata/libahci.c:227 ahci_save_initial_config+0x3c/0x3e0
> [   11.760000] Modules linked in:
> [   11.770000] CPU: 1 PID: 1 Comm: swapper/0 Tainted: G        W         4.18.0-rc7+ #277
> [   11.780000] Stack : 00000000 00000004 00000006 00000000 00000000 00000000 00000000 00000000
> [   11.800000]         80da7a3e 0000004a 00000000 00000000 80710000 00000001 9bc73b40 1c044177
> [   11.820000]         00000000 00000000 80de0000 00000007 00000000 000001a9 00000000 00000000
> [   11.830000]         00000000 000001a8 80dd0000 65726568 80710000 00000000 80730000 806dc1fc
> [   11.850000]         00000009 000000e3 00000005 00000000 00000001 803a0508 00000004 80da0004
> [   11.870000]         ...
> [   11.870000] Call Trace:
> [   11.880000] [<8000bd34>] show_stack+0x8c/0x130
> [   11.890000] [<805dd684>] dump_stack+0x94/0xd0
> [   11.890000] [<80027c30>] __warn+0x10c/0x114
> [   11.900000] [<80027ce0>] warn_slowpath_null+0x44/0x58
> [   11.910000] [<803f696c>] ahci_save_initial_config+0x3c/0x3e0
> [   11.920000] [<803f4bfc>] ahci_init_one+0x46c/0xa40
> [   11.930000] [<80371cf0>] pci_device_probe+0x90/0x120
> [   11.940000] [<803aff10>] driver_probe_device+0x314/0x46c
> [   11.950000] [<803b011c>] __driver_attach+0xb4/0x138
> [   11.960000] [<803ad9c0>] bus_for_each_dev+0x6c/0xb0
> [   11.970000] [<803aebf8>] bus_add_driver+0x204/0x24c
> [   11.980000] [<803b0a68>] driver_register+0xd0/0x118
> [   11.990000] [<80001618>] do_one_initcall+0x84/0x19c
> [   12.000000] [<80741ed0>] kernel_init_freeable+0x248/0x250
> [   12.010000] [<805f5e1c>] kernel_init+0x14/0x110
> [   12.020000] [<800066f8>] ret_from_kernel_thread+0x14/0x1c
> [   12.030000] ---[ end trace 8d118b8e5f7182fa ]---
> [   12.040000] ahci 0000:03:00.0: forcing PORTS_IMPL to 0x1
> [   12.200000] ------------[ cut here ]------------
> [   12.200000] WARNING: CPU: 1 PID: 1 at ../drivers/ata/libahci.c:227 ahci_reset_controller+0x2c/0x128
> [   12.220000] Modules linked in:
> [   12.230000] CPU: 1 PID: 1 Comm: swapper/0 Tainted: G        W         4.18.0-rc7+ #277
> [   12.240000] Stack : 00000000 00000004 00000006 00000000 00000000 00000000 00000000 00000000
> [   12.260000]         80da7a3e 0000004a 00000000 00000000 80710000 00000001 9bc73b48 1c044177
> [   12.280000]         00000000 00000000 80de0000 00000007 00000000 000001c6 00000000 00000000
> [   12.290000]         00000000 000001c5 80dd0000 65726568 80710000 00000000 80730000 806dc1fc
> [   12.310000]         00000009 000000e3 00000005 9a104000 00000001 803a0508 00000004 80da0004
> [   12.330000]         ...
> [   12.330000] Call Trace:
> [   12.340000] [<8000bd34>] show_stack+0x8c/0x130
> [   12.350000] [<805dd684>] dump_stack+0x94/0xd0
> [   12.350000] [<80027c30>] __warn+0x10c/0x114
> [   12.360000] [<80027ce0>] warn_slowpath_null+0x44/0x58
> [   12.370000] [<803f6dac>] ahci_reset_controller+0x2c/0x128
> [   12.380000] [<803f4fb4>] ahci_init_one+0x824/0xa40
> [   12.390000] [<80371cf0>] pci_device_probe+0x90/0x120
> [   12.400000] [<803aff10>] driver_probe_device+0x314/0x46c
> [   12.410000] [<803b011c>] __driver_attach+0xb4/0x138
> [   12.420000] [<803ad9c0>] bus_for_each_dev+0x6c/0xb0
> [   12.430000] [<803aebf8>] bus_add_driver+0x204/0x24c
> [   12.440000] [<803b0a68>] driver_register+0xd0/0x118
> [   12.450000] [<80001618>] do_one_initcall+0x84/0x19c
> [   12.460000] [<80741ed0>] kernel_init_freeable+0x248/0x250
> [   12.470000] [<805f5e1c>] kernel_init+0x14/0x110
> [   12.480000] [<800066f8>] ret_from_kernel_thread+0x14/0x1c
> [   12.490000] ---[ end trace 8d118b8e5f7182fb ]---
> [   12.660000] ------------[ cut here ]------------
> [   12.660000] ata2: failed to resume link (SControl 0)
> [   12.660000] ata2: SATA link down (SStatus 0 SControl 0)
> [   12.660000] WARNING: CPU: 1 PID: 1 at ../drivers/ata/libahci.c:227 ahci_reset_controller+0xc8/0x128
> [   12.700000] Modules linked in:
> [   12.710000] CPU: 1 PID: 1 Comm: swapper/0 Tainted: G        W         4.18.0-rc7+ #277
> [   12.720000] Stack : 00000000 00000004 00000006 00000000 00000000 00000000 00000000 00000000
> [   12.740000]         80da7a3e 0000004a 00000000 00000000 80710000 00000001 9bc73b48 1c044177
> [   12.760000]         00000000 00000000 80de0000 00000007 00000000 000001e4 00000000 00000000
> [   12.770000]         00000000 000001e3 80dd0000 65726568 80710000 00000000 80730000 806dc1fc
> [   12.790000]         00000009 000000e3 00000005 9a104000 00000001 803a0508 00000004 80da0004
> [   12.810000]         ...
> [   12.810000] Call Trace:
> [   12.820000] [<8000bd34>] show_stack+0x8c/0x130
> [   12.830000] [<805dd684>] dump_stack+0x94/0xd0
> [   12.830000] [<80027c30>] __warn+0x10c/0x114
> [   12.840000] [<80027ce0>] warn_slowpath_null+0x44/0x58
> [   12.850000] [<803f6e48>] ahci_reset_controller+0xc8/0x128
> [   12.860000] [<803f4fb4>] ahci_init_one+0x824/0xa40
> [   12.870000] [<80371cf0>] pci_device_probe+0x90/0x120
> [   12.880000] [<803aff10>] driver_probe_device+0x314/0x46c
> [   12.890000] [<803b011c>] __driver_attach+0xb4/0x138
> [   12.900000] [<803ad9c0>] bus_for_each_dev+0x6c/0xb0
> [   12.910000] [<803aebf8>] bus_add_driver+0x204/0x24c
> [   12.920000] [<803b0a68>] driver_register+0xd0/0x118
> [   12.930000] [<80001618>] do_one_initcall+0x84/0x19c
> [   12.940000] [<80741ed0>] kernel_init_freeable+0x248/0x250
> [   12.950000] [<805f5e1c>] kernel_init+0x14/0x110
> [   12.960000] [<800066f8>] ret_from_kernel_thread+0x14/0x1c
> [   12.970000] ---[ end trace 8d118b8e5f7182fc ]---
> [   12.980000] ahci 0000:03:00.0: AHCI 0000.0000 1 slots 1 ports ? Gbps 0x1 impl IDE mode
> [   13.000000] ahci 0000:03:00.0: flags: 
> [   13.010000] scsi host2: ahci
> [   13.020000] ata3: SATA max UDMA/133 abar m512@0x60400000 port 0x60400100 irq 25
> [   13.040000] libphy: Fixed MDIO Bus: probed
> [   13.050000] tun: Universal TUN/TAP device driver, 1.6
> [   13.060000] sdhci: Secure Digital Host Controller Interface driver
> [   13.070000] sdhci: Copyright(c) Pierre Ossman
> [   13.080000] spi-mt7621 1e000b00.spi: sys_freq: 225000000
> [   13.100000] m25p80 spi0.0: w25q256 (32768 Kbytes)
> [   13.110000] 4 fixed-partitions partitions found on MTD device spi0.0
> [   13.120000] Creating 4 MTD partitions on "spi0.0":
> [   13.130000] 0x000000000000-0x000000030000 : "u-boot"
> [   13.150000] 0x000000030000-0x000000040000 : "u-boot-env"
> [   13.160000] 0x000000040000-0x000000050000 : "factory"
> [   13.180000] 0x000000050000-0x000002000000 : "firmware"
> [   13.250000] libphy: mdio: probed
> [   13.280000] mtk_soc_eth 1e100000.ethernet: generated random MAC address ce:c3:44:0e:5b:90
> [   13.300000] mtk_soc_eth 1e100000.ethernet eth0: mediatek frame engine at 0xbe100000, irq 21
> [   13.330000] NET: Registered protocol family 10
> [   13.350000] Segment Routing with IPv6
> [   13.360000] NET: Registered protocol family 17
> [   13.370000] 8021q: 802.1Q VLAN Support v1.8
> [   13.380000] Loading compiled-in X.509 certificates
> [   13.400000] hctosys: unable to open rtc device (rtc0)
> [   13.450000] mmc0: new high speed SD card at address 0002
> [   13.480000] mmcblk0: mmc0:0002 00000 1.88 GiB 
> [   14.140000] ata3: failed to resume link (SControl 0)
> [   14.140000] ata3: SATA link down (SStatus 0 SControl 0)
> [   14.180000] Freeing unused kernel memory: 6524K
> [   14.190000] This architecture does not have kernel memory protection.
> [   14.410000] usbcore: registered new interface driver usbfs
> [   14.430000] usbcore: registered new interface driver hub
> [   14.450000] usbcore: registered new device driver usb
> [   14.560000] xhci-mtk 1e1c0000.xhci: xHCI Host Controller
> [   14.570000] xhci-mtk 1e1c0000.xhci: new USB bus registered, assigned bus number 1
> [   14.590000] xhci-mtk 1e1c0000.xhci: hcc params 0x01401198 hci version 0x96 quirks 0x0000000000210010
> [   14.610000] xhci-mtk 1e1c0000.xhci: irq 20, io mem 0x1e1c0000
> [   14.650000] hub 1-0:1.0: USB hub found
> [   14.660000] hub 1-0:1.0: 2 ports detected
> [   14.680000] xhci-mtk 1e1c0000.xhci: xHCI Host Controller
> [   14.690000] xhci-mtk 1e1c0000.xhci: new USB bus registered, assigned bus number 2
> [   14.710000] xhci-mtk 1e1c0000.xhci: Host supports USB 3.0  SuperSpeed
> [   14.730000] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
> [   14.760000] hub 2-0:1.0: USB hub found
> [   14.770000] hub 2-0:1.0: 1 port detected
> [   14.830000] usbcore: registered new interface driver usb-storage
> [   15.190000] Waiting disk spinup and searching for partition GNUBEE-ROOT...
> [   15.200000] usb 1-2: new high-speed USB device number 2 using xhci-mtk
> [   15.420000] hub 1-2:1.0: USB hub found
> [   15.430000] hub 1-2:1.0: 4 ports detected
> [   15.650000] mtk_soc_eth 1e100000.ethernet eth0: port 0 link up
> [   18.220000] done.
> mdadm: No devices listed in conf file were found.
> [   19.470000] msdc0 -> TUNE_BREAD<PASS> dcrc<0x0> DATRDDLY0/1<0x10101010><0x0> dsmpl<0x0> <- msdc_tune_bread() : L<1342> PID<kworker/3:0H><0x1c>
> findfs: unable to resolve 'PARTLABEL=GNUBEE-CRYPT-ROOT'
> [   19.790000] EXT4-fs (mmcblk0): INFO: recovery required on readonly filesystem
> [   19.800000] EXT4-fs (mmcblk0): write access will be enabled during recovery
> [   22.430000] EXT4-fs (mmcblk0): recovery complete
> [   22.450000] EXT4-fs (mmcblk0): mounted filesystem with ordered data mode. Opts: (null)
> [   22.480000] Partition GNUBEE-ROOT found. Starting...
> [   23.910000] systemd[1]: System time before build time, advancing clock.
> [   24.060000] random: systemd: uninitialized urandom read (16 bytes read)
> [   24.090000] systemd[1]: systemd 232 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +SECCOMP +BLKID +ELFUTILS +KMOD +IDN)
> [   24.130000] systemd[1]: Detected architecture mips.
> 
> Welcome to Debian GNU/Linux 9 (stretch)!
> 
> [   24.190000] systemd[1]: Set hostname to <gnubeaver.brown>.
> [   24.320000] random: systemd: uninitialized urandom read (16 bytes read)
> [   24.370000] random: systemd-gpt-aut: uninitialized urandom read (16 bytes read)
> [   25.100000] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
> [  OK  ] Started Dispatch Password Requests to Console Directory Watch.
> [   25.160000] systemd[1]: Created slice System Slice.
> [  OK  ] Created slice System Slice.
> [   25.210000] systemd[1]: Listening on udev Kernel Socket.
> [  OK  ] Listening on udev Kernel Socket.
> [   25.270000] systemd[1]: Mounting Debug File System...
>          Mounting Debug File System...
> [   25.320000] systemd[1]: Created slice system-getty.slice.
> [  OK  ] Created slice system-getty.slice.
> [   25.370000] systemd[1]: Listening on Syslog Socket.
> [  OK  ] Listening on Syslog Socket.
> [   25.420000] systemd[1]: Created slice User and Session Slice.
> [  OK  ] Created slice User and Session Slice.
> [  OK  ] Listening on /dev/initctl Compatibility Named Pipe.
> [  OK  ] Listening on Journal Socket (/dev/log).
> [  OK  ] Reached target Slices.
> [  OK  ] Reached target Remote File Systems.
> [  OK  ] Listening on Journal Socket.
> [   25.650000] random: crng init done
> [   25.660000] random: 7 urandom warning(s) missed due to ratelimiting
>          Starting Create list of required st…ce nodes for the current kernel...
>          Starting Load Kernel Modules...
>          Starting Set the console keyboard layout...
> [  OK  ] Listening on fsck to fsckd communication Socket.
>          Starting File System Check on Root Device...
> [  OK  ] Created slice system-serial\x2dgetty.slice.
> [  OK  ] Listening on udev Control Socket.
> [  OK  ] Reached target Swap.
>          Starting Journal Service...
> [  OK  ] Started Forward Password Requests to Wall Directory Watch.
> [  OK  ] Reached target Paths.
> [  OK  ] Reached target Encrypted Volumes.
> [  OK  ] Mounted Debug File System.
> [  OK  ] Started Create list of required sta…vice nodes for the current kernel.
> [  OK  ] Started Load Kernel Modules.
> [  OK  ] Started File System Check on Root Device.
> [  OK  ] Started File System Check Daemon to report status.
>          Starting Remount Root and Kernel File Systems...
>          Starting Apply Kernel Variables...
>          Starting Create Static Device Nodes in /dev...
> [  OK  ] Started Set the console keyboard layout.
> [  OK  ] Started Apply Kernel Variables.
> [  OK  ] Started Create Static Device Nodes in /dev.
> [   26.920000] EXT4-fs (mmcblk0): re-mounted. Opts: errors=remount-ro
>          Starting udev Kernel Device Manager...
> [  OK  ] Started Remount Root and Kernel File Systems.
>          Starting udev Coldplug all Devices...
>          Starting Load/Save Random Seed...
> [  OK  ] Reached target Local File Systems (Pre).
> [  OK  ] Reached target Local File Systems.
>          Starting Raise network interfaces...
>          Starting Set console font and keymap...
> [  OK  ] Started Journal Service.
> [  OK  ] Started udev Kernel Device Manager.
> [  OK  ] Started Load/Save Random Seed.
> [  OK  ] Started Set console font and keymap.
>          Starting Flush Journal to Persistent Storage...
> [   27.900000] systemd-journald[647]: Received request to flush runtime journal from PID 1
> [  OK  ] Started Flush Journal to Persistent Storage.
>          Starting Create Volatile Files and Directories...
> [  OK  ] Started udev Coldplug all Devices.
> [  OK  ] Started Create Volatile Files and Directories.
> [  OK  ] Found device /dev/ttyS0.
> [  OK  ] Listening on Load/Save RF Kill Switch Status /dev/rfkill Watch.
>          Starting Network Time Synchronization...
>          Starting Update UTMP about System Boot/Shutdown...
> [  OK  ] Started Update UTMP about System Boot/Shutdown.
> [  OK  ] Started Network Time Synchronization.
> [  OK  ] Reached target System Initialization.
> [  OK  ] Started Daily Cleanup of Temporary Directories.
> [  OK  ] Listening on D-Bus System Message Bus Socket.
> [  OK  ] Reached target Sockets.
> [  OK  ] Reached target Basic System.
> [   29.840000] IPv6: ADDRCONF(NETDEV_UP): eth0: link is not ready
> [   29.850000] IPv6: ADDRCONF(NETDEV_CHANGE): eth0: link becomes ready
> [  OK  ] Started Regular background program processing daemon.
>          Starting System Logging Service...
> [  OK  ] Started Self Monitoring and Reporting Technology (SMART) Daemon.
> [  OK  ] Started D-Bus System Message Bus.
>          Starting Login Service...
>          Starting LSB: Execute the kexec -e command to reboot system...
>          Starting LSB: Mount debugfs on /sys/kernel/debug...
> [  OK  ] Reached target System Time Synchronized.
> [  OK  ] Started Daily apt download activities.
> [  OK  ] Started Daily apt upgrade and clean activities.
> [  OK  ] Reached target Timers.
> [  OK  ] Started System Logging Service.
> [  OK  ] Started LSB: Execute the kexec -e command to reboot system.
>          Starting LSB: Load kernel image with kexec...
> [  OK  ] Started Login Service.
> [  OK  ] Started LSB: Mount debugfs on /sys/kernel/debug.
> [  OK  ] Started LSB: Load kernel image with kexec.
> [FAILED] Failed to start Raise network interfaces.
> See 'systemctl status networking.service' for details.
> [  OK  ] Reached target Network.
>          Starting OpenBSD Secure Shell server...
> [  OK  ] Started BIND Domain Name Server.
> [  OK  ] Reached target Host and Network Name Lookups.
>          Starting Permit User Sessions...
>          Starting The Apache HTTP Server...
> [  OK  ] Reached target Network is Online.
>          Starting LSB: Advanced IEEE 802.11 management daemon...
>          Starting LSB: exim Mail Transport Agent...
>          Starting /etc/rc.local Compatibility...
>          Starting LSB: DHCP server...
> [  OK  ] Started Permit User Sessions.
> [  OK  ] Started LSB: Advanced IEEE 802.11 management daemon.
> [  OK  ] Started OpenBSD Secure Shell server.
> [  OK  ] Started The Apache HTTP Server.
> [FAILED] Failed to start LSB: DHCP server.
> See 'systemctl status isc-dhcp-server.service' for details.
> [  OK  ] Started LSB: exim Mail Transport Agent.
> [   45.857040] rc.local[923]:  3 Aug 14:32:11 ntpdate[928]: step time server 220.233.156.30 offset 109341.916405 sec
> [  OK  ] Started /etc/rc.local Compatibility.
> [  OK  ] Started Serial Getty on ttyS0.
> [  OK  ] Reached target Login Prompts.
> [  OK  ] Reached target Multi-User System.
> [  OK  ] Reached target Graphical Interface.
>          Starting Update UTMP about System Runlevel Changes...
>          Starting Daily apt download activities...
> [  OK  ] Started Update UTMP about System Runlevel Changes.
> 
> Debian GNU/Linux 9 gnubeaver.brown ttyS0
> 
> gnubeaver login: root
> Password: 
> Last login: Thu Aug  2 08:04:16 AEST 2018 on ttyS0
> Linux gnubeaver.brown 4.18.0-rc7+ #277 SMP Fri Aug 3 14:30:02 AEST 2018 mips
> 
> The programs included with the Debian GNU/Linux system are free software;
> the exact distribution terms for each program are described in the
> individual files in /usr/share/doc/*/copyright.
> 
> Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
> permitted by applicable law.
>                                                                                                                                       resize: unknown character, exiting.
> root@gnubeaver:~# lspci
> 00:00.0 PCI bridge: Device 0e8d:0801 (rev 01)
> 00:01.0 PCI bridge: Device 0e8d:0801 (rev 01)
> 00:02.0 PCI bridge: Device 0e8d:0801 (rev 01)
> 01:00.0 IDE interface: ASMedia Technology Inc. ASM1061 SATA IDE Controller (rev 02)
> 02:00.0 IDE interface: ASMedia Technology Inc. ASM1061 SATA IDE Controller (rev 02)
> 03:00.0 IDE interface: ASMedia Technology Inc. ASM1061 SATA IDE Controller (rev 02)
> root@gnubeaver:~# 
> root@gnubeaver:~# cat /proc/partitions 
> major minor  #blocks  name
> 
>   31        0        192 mtdblock0
>   31        1         64 mtdblock1
>   31        2         64 mtdblock2
>   31        3      32448 mtdblock3
>  179        0    1974272 mmcblk0