All of lore.kernel.org
 help / color / mirror / Atom feed
From: Florian Weimer <fweimer@redhat.com>
To: Andrew Waterman <andrew@sifive.com>
Cc: Palmer Dabbelt <palmer@dabbelt.com>,
	 Vineet Gupta <vineetg@rivosinc.com>,
	 stillson@rivosinc.com,  Paul Walmsley <paul.walmsley@sifive.com>,
	 anup@brainfault.org,  atishp@atishpatra.org, guoren@kernel.org,
	 Conor Dooley <conor.dooley@microchip.com>,
	greentime.hu@sifive.com,  vincent.chen@sifive.com,
	 andy.chiu@sifive.com, arnd@kernel.org,
	 linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org,
	 bjorn@kernel.org, libc-alpha@sourceware.org,
	 christoph.muellner@vrull.eu,
	 Aaron Durbin <adurbin@rivosinc.com>,
	 linux@rivosinc.com
Subject: Re: RISCV Vector unit disabled by default for new task (was Re: [PATCH v12 17/17] riscv: prctl to enable vector commands)
Date: Fri, 09 Dec 2022 14:04:23 +0100	[thread overview]
Message-ID: <87zgbwk9t4.fsf@oldenburg.str.redhat.com> (raw)
In-Reply-To: <Y5MtTLtrDnCW6Dik@bruce.bluespec.com> (Darius Rad's message of "Fri, 9 Dec 2022 07:42:52 -0500")

* Darius Rad:

> On Fri, Dec 09, 2022 at 01:32:33PM +0100, Florian Weimer via Libc-alpha wrote:
>> * Darius Rad:
>> 
>> > On Fri, Dec 09, 2022 at 11:02:57AM +0100, Florian Weimer wrote:
>> >> * Andrew Waterman:
>> >> 
>> >> > This suggests that ld.so, early-stage libc, or possibly both will need
>> >> > to make this prctl() call, perhaps by parsing the ELF headers of the
>> >> > binary and each library to determine if the V extension is used.
>> >> 
>> >> If the string functions use the V extension, it will be enabled
>> >> unconditionally.  So I don't see why it's okay for libc to trigger this
>> >> alleged UAPI change, when the kernel can't do it by default.
>> >> 
>> >
>> > Because the call to enable can fail and userspace needs to deal with that.
>> 
>> Failure is usually indicated by an AT_HWCAP or AT_HWCAP2 bit remaining
>> zero, or perhaps a special CPU register (although that is more unusual).
>
> That would indicate that the extension is not present, which is one of, but
> not the only way it can fail.

I think you should bring down the number of failure modes.  HWCAP has
the advantage that it communicates kernel/hypervisor/firmware/CPU
support in a single bit, which simplifies the programming model and
avoids hard-to-detect bugs.  It's not clear why it would be beneficial
to continue on ENOMEM failures here because the system must clearly be
in bad shape at this point, and launching a new process is very unlikely
to improve matters.  So I think the simpler programming model is the way
to go here.

> The vector extension relies on dynamically allocated memory in the kernel,
> which can fail.

But this failure can be reported as part of execve and clone.

> It also provides the opportunity for the kernel to deny access to the
> vector extension, perhaps due to administrative policy or other future
> mechanism.

HWCAP can do this, too.

Thanks,
Florian


_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

WARNING: multiple messages have this Message-ID (diff)
From: Florian Weimer <fweimer@redhat.com>
To: Andrew Waterman <andrew@sifive.com>
Cc: Palmer Dabbelt <palmer@dabbelt.com>,
	Vineet Gupta <vineetg@rivosinc.com>,
	stillson@rivosinc.com, Paul Walmsley <paul.walmsley@sifive.com>,
	anup@brainfault.org, atishp@atishpatra.org, guoren@kernel.org,
	Conor Dooley <conor.dooley@microchip.com>,
	greentime.hu@sifive.com, vincent.chen@sifive.com,
	andy.chiu@sifive.com, arnd@kernel.org,
	linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org,
	bjorn@kernel.org, libc-alpha@sourceware.org,
	christoph.muellner@vrull.eu, Aaron Durbin <adurbin@rivosinc.com>,
	linux@rivosinc.com
Subject: Re: RISCV Vector unit disabled by default for new task (was Re: [PATCH v12 17/17] riscv: prctl to enable vector commands)
Date: Fri, 09 Dec 2022 14:04:23 +0100	[thread overview]
Message-ID: <87zgbwk9t4.fsf@oldenburg.str.redhat.com> (raw)
In-Reply-To: <Y5MtTLtrDnCW6Dik@bruce.bluespec.com> (Darius Rad's message of "Fri, 9 Dec 2022 07:42:52 -0500")

* Darius Rad:

> On Fri, Dec 09, 2022 at 01:32:33PM +0100, Florian Weimer via Libc-alpha wrote:
>> * Darius Rad:
>> 
>> > On Fri, Dec 09, 2022 at 11:02:57AM +0100, Florian Weimer wrote:
>> >> * Andrew Waterman:
>> >> 
>> >> > This suggests that ld.so, early-stage libc, or possibly both will need
>> >> > to make this prctl() call, perhaps by parsing the ELF headers of the
>> >> > binary and each library to determine if the V extension is used.
>> >> 
>> >> If the string functions use the V extension, it will be enabled
>> >> unconditionally.  So I don't see why it's okay for libc to trigger this
>> >> alleged UAPI change, when the kernel can't do it by default.
>> >> 
>> >
>> > Because the call to enable can fail and userspace needs to deal with that.
>> 
>> Failure is usually indicated by an AT_HWCAP or AT_HWCAP2 bit remaining
>> zero, or perhaps a special CPU register (although that is more unusual).
>
> That would indicate that the extension is not present, which is one of, but
> not the only way it can fail.

I think you should bring down the number of failure modes.  HWCAP has
the advantage that it communicates kernel/hypervisor/firmware/CPU
support in a single bit, which simplifies the programming model and
avoids hard-to-detect bugs.  It's not clear why it would be beneficial
to continue on ENOMEM failures here because the system must clearly be
in bad shape at this point, and launching a new process is very unlikely
to improve matters.  So I think the simpler programming model is the way
to go here.

> The vector extension relies on dynamically allocated memory in the kernel,
> which can fail.

But this failure can be reported as part of execve and clone.

> It also provides the opportunity for the kernel to deny access to the
> vector extension, perhaps due to administrative policy or other future
> mechanism.

HWCAP can do this, too.

Thanks,
Florian


  reply	other threads:[~2022-12-09 13:04 UTC|newest]

Thread overview: 147+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-09-21 21:43 [PATCH v12 01/17] riscv: Rename __switch_to_aux -> fpu Chris Stillson
2022-09-21 21:43 ` Chris Stillson
2022-09-21 21:43 ` Chris Stillson
2022-09-21 21:43 ` [PATCH v12 02/17] riscv: Extending cpufeature.c to detect V-extension Chris Stillson
2022-09-21 21:43   ` Chris Stillson
2022-09-21 21:43   ` Chris Stillson
     [not found]   ` <4b6e20fb-d013-0a09-0b74-b6c46e045af3@rivosinc.com>
     [not found]     ` <CAJF2gTSPoKu_owEb6+MLhAgK5nz2FTRDkTn4qfXF4KyA-XTwvw@mail.gmail.com>
     [not found]       ` <CAJF2gTT_z96V3kjPtr9hpTq8XRn0x=91wFNPYFFdetAA2u-01Q@mail.gmail.com>
2022-11-04  9:13         ` Conor.Dooley
2022-11-04 18:04           ` Vineet Gupta
2022-09-21 21:43 ` [PATCH v12 03/17] riscv: Add new csr defines related to vector extension Chris Stillson
2022-09-21 21:43   ` Chris Stillson
2022-09-21 21:43   ` Chris Stillson
2023-01-23 11:24   ` Heiko Stübner
2023-01-23 11:24     ` Heiko Stübner
2022-09-21 21:43 ` [PATCH v12 04/17] riscv: Add vector feature to compile Chris Stillson
2022-09-21 21:43   ` Chris Stillson
2022-09-21 21:43   ` Chris Stillson
2022-11-07 17:21   ` Björn Töpel
2022-11-07 17:21     ` Björn Töpel
2022-11-08  0:04     ` Vineet Gupta
2022-11-08  0:04       ` Vineet Gupta
2022-11-08  7:56       ` Conor Dooley
2022-11-08  7:56         ` Conor Dooley
2022-11-08 17:17         ` Vineet Gupta
2022-11-08 17:17           ` Vineet Gupta
2022-11-08 17:22           ` Conor Dooley
2022-11-08 17:22             ` Conor Dooley
2022-11-13 16:16     ` Conor.Dooley
2022-11-13 16:16       ` Conor.Dooley
2022-11-15 17:38       ` Vineet Gupta
2022-11-15 17:38         ` Vineet Gupta
2022-11-15 22:17         ` Conor Dooley
2022-11-15 22:17           ` Conor Dooley
2022-12-15  0:40   ` Atish Patra
2022-12-15  0:40     ` Atish Patra
2022-09-21 21:43 ` [PATCH v12 05/17] riscv: Add has_vector/riscv_vsize to save vector features Chris Stillson
2022-09-21 21:43   ` Chris Stillson
2022-09-21 21:43   ` Chris Stillson
2022-09-22  4:23   ` Samuel Holland
2022-09-22  4:23     ` Samuel Holland
2022-09-23 16:27     ` Chris Stillson
2022-09-23 16:27       ` Chris Stillson
2022-09-24 18:01       ` Conor Dooley
2022-09-24 18:01         ` Conor Dooley
2022-11-04  4:10   ` Vineet Gupta
2022-11-04  4:10     ` Vineet Gupta
2022-11-04  4:33   ` Vineet Gupta
2022-11-04  4:33     ` Vineet Gupta
2022-09-21 21:43 ` [PATCH v12 06/17] riscv: Reset vector register Chris Stillson
2022-09-21 21:43   ` Chris Stillson
2022-09-21 21:43   ` Chris Stillson
2022-11-04  5:01   ` Vineet Gupta
2022-11-04  5:01     ` Vineet Gupta
2022-11-04  8:45     ` Guo Ren
2022-11-04  8:45       ` Guo Ren
2023-01-20 12:20   ` Heiko Stübner
2023-01-20 12:20     ` Heiko Stübner
2022-09-21 21:43 ` [PATCH v12 07/17] riscv: Add vector struct and assembler definitions Chris Stillson
2022-09-21 21:43   ` Chris Stillson
2022-09-21 21:43   ` Chris Stillson
2022-11-04  5:13   ` Vineet Gupta
2022-11-04  5:13     ` Vineet Gupta
2022-09-21 21:43 ` [PATCH v12 08/17] riscv: Add task switch support for vector Chris Stillson
2022-09-21 21:43   ` Chris Stillson
2022-09-21 21:43   ` Chris Stillson
2022-11-04 22:08   ` Vineet Gupta
2022-11-04 22:08     ` Vineet Gupta
2022-09-21 21:43 ` [PATCH v12 09/17] riscv: Add ptrace vector support Chris Stillson
2022-09-21 21:43   ` Chris Stillson
2022-09-21 21:43   ` Chris Stillson
2022-11-08  1:38   ` Vineet Gupta
2022-11-08  1:38     ` Vineet Gupta
2022-11-14 20:01     ` Arnd Bergmann
2022-11-14 20:01       ` Arnd Bergmann
2022-09-21 21:43 ` [PATCH v12 10/17] riscv: Add sigcontext save/restore for vector Chris Stillson
2022-09-21 21:43   ` Chris Stillson
2022-09-21 21:43   ` Chris Stillson
2022-11-09  1:27   ` Vineet Gupta
2022-11-09  1:27     ` Vineet Gupta
2022-09-21 21:43 ` [PATCH v12 11/17] riscv: signal: Report signal frame size to userspace via auxv Chris Stillson
2022-09-21 21:43   ` Chris Stillson
2022-09-21 21:43   ` Chris Stillson
2022-09-21 21:43 ` [PATCH v12 12/17] riscv: Add support for kernel mode vector Chris Stillson
2022-09-21 21:43   ` Chris Stillson
2022-09-21 21:43   ` Chris Stillson
2022-09-21 21:43 ` [PATCH v12 13/17] riscv: Add vector extension XOR implementation Chris Stillson
2022-09-21 21:43   ` Chris Stillson
2022-09-21 21:43   ` Chris Stillson
2022-09-21 21:43 ` [PATCH v12 14/17] riscv: Fix a kernel panic issue if $s2 is set to a specific value before entering Linux Chris Stillson
2022-09-21 21:43   ` Chris Stillson
2022-09-21 21:43   ` Chris Stillson
2022-09-21 21:43 ` [PATCH v12 15/17] riscv: Add V extension to KVM ISA allow list Chris Stillson
2022-09-21 21:43   ` Chris Stillson
2022-09-21 21:43   ` Chris Stillson
2022-09-21 21:43 ` [PATCH v12 16/17] riscv: KVM: Add vector lazy save/restore support Chris Stillson
2022-09-21 21:43   ` Chris Stillson
2022-09-21 21:43   ` Chris Stillson
2022-09-21 21:43 ` [PATCH v12 17/17] riscv: prctl to enable vector commands Chris Stillson
2022-09-21 21:43   ` Chris Stillson
2022-09-21 21:43   ` Chris Stillson
2022-12-09  5:16   ` RISCV Vector unit disabled by default for new task (was Re: [PATCH v12 17/17] riscv: prctl to enable vector commands) Vineet Gupta
2022-12-09  5:16     ` Vineet Gupta
2022-12-09  6:27     ` Palmer Dabbelt
2022-12-09  6:27       ` Palmer Dabbelt
2022-12-09  7:42       ` Andrew Waterman
2022-12-09  7:42         ` Andrew Waterman
2022-12-09 10:02         ` Florian Weimer
2022-12-09 10:02           ` Florian Weimer
2022-12-09 12:21           ` Darius Rad
2022-12-09 12:21             ` Darius Rad
2022-12-09 12:32             ` Florian Weimer
2022-12-09 12:32               ` Florian Weimer
2022-12-09 12:42               ` Darius Rad
2022-12-09 12:42                 ` Darius Rad
2022-12-09 13:04                 ` Florian Weimer [this message]
2022-12-09 13:04                   ` Florian Weimer
2022-12-09 17:21                   ` Palmer Dabbelt
2022-12-09 17:21                     ` Palmer Dabbelt
2022-12-09 19:42                     ` Vineet Gupta
2022-12-09 19:42                       ` Vineet Gupta
2022-12-09 19:58                       ` Andrew Waterman
2022-12-09 19:58                         ` Andrew Waterman
2022-12-13 16:43                       ` Darius Rad
2022-12-13 16:43                         ` Darius Rad
2022-12-14 20:07                         ` Vineet Gupta
2022-12-14 20:07                           ` Vineet Gupta
2022-12-14 23:13                           ` Samuel Holland
2022-12-14 23:13                             ` Samuel Holland
2022-12-15  2:09                           ` Darius Rad
2022-12-15  2:09                             ` Darius Rad
2022-12-15 11:48                             ` Björn Töpel
2022-12-15 11:48                               ` Björn Töpel
2022-12-15 12:28                               ` Florian Weimer
2022-12-15 12:28                                 ` Florian Weimer
2022-12-15 15:33                                 ` Richard Henderson
2022-12-15 15:33                                   ` Richard Henderson
2022-12-15 18:57                                   ` Vineet Gupta
2022-12-15 18:57                                     ` Vineet Gupta
2022-12-15 18:59                                     ` Andrew Pinski
2022-12-15 18:59                                       ` Andrew Pinski
2022-12-15 19:01                                       ` Andrew Pinski
2022-12-15 19:01                                         ` Andrew Pinski
2022-12-15 19:56                                     ` Richard Henderson
2022-12-15 19:56                                       ` Richard Henderson
2022-12-09 13:58       ` Icenowy Zheng
2022-12-09 13:58         ` Icenowy Zheng
2023-01-23 11:20 ` [PATCH v12 01/17] riscv: Rename __switch_to_aux -> fpu Heiko Stübner
2023-01-23 11:20   ` Heiko Stübner

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=87zgbwk9t4.fsf@oldenburg.str.redhat.com \
    --to=fweimer@redhat.com \
    --cc=adurbin@rivosinc.com \
    --cc=andrew@sifive.com \
    --cc=andy.chiu@sifive.com \
    --cc=anup@brainfault.org \
    --cc=arnd@kernel.org \
    --cc=atishp@atishpatra.org \
    --cc=bjorn@kernel.org \
    --cc=christoph.muellner@vrull.eu \
    --cc=conor.dooley@microchip.com \
    --cc=greentime.hu@sifive.com \
    --cc=guoren@kernel.org \
    --cc=libc-alpha@sourceware.org \
    --cc=linux-kernel@vger.kernel.org \
    --cc=linux-riscv@lists.infradead.org \
    --cc=linux@rivosinc.com \
    --cc=palmer@dabbelt.com \
    --cc=paul.walmsley@sifive.com \
    --cc=stillson@rivosinc.com \
    --cc=vincent.chen@sifive.com \
    --cc=vineetg@rivosinc.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.