* [PATCH V2] drm: Add LTTPR defines for DP 1.4a
@ 2019-08-26 15:29 Siqueira, Rodrigo
[not found] ` <20190826152925.4x7mwhzxit353yww-1ViLX0X+lBJGNQ1M2rI3KwRV3xvJKrda@public.gmane.org>
0 siblings, 1 reply; 4+ messages in thread
From: Siqueira, Rodrigo @ 2019-08-26 15:29 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: Li, Sun peng (Leo), Berthe, Abdoulaye, Wentland, Harry
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DP 1.4a specification defines Link Training Tunable PHY Repeater (LTTPR)
which is required to add support for systems with Thunderbolt or other
repeater devices.
Changes since V1:
- Adjusts registers names to be aligned with spec and the rest of the
file
- Update spec comment from 1.4 to 1.4a
Cc: Abdoulaye Berthe <Abdoulaye.Berthe-5C7GfCeVMHo@public.gmane.org>
Cc: Harry Wentland <harry.wentland-5C7GfCeVMHo@public.gmane.org>
Cc: Leo Li <sunpeng.li-5C7GfCeVMHo@public.gmane.org>
Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira-5C7GfCeVMHo@public.gmane.org>
Signed-off-by: Abdoulaye Berthe <Abdoulaye.Berthe-5C7GfCeVMHo@public.gmane.org>
---
include/drm/drm_dp_helper.h | 25 +++++++++++++++++++++++++
1 file changed, 25 insertions(+)
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index 8364502f92cf..e8beb4e7e5da 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -134,6 +134,31 @@
#define DP_SUPPORTED_LINK_RATES 0x010 /* eDP 1.4 */
# define DP_MAX_SUPPORTED_RATES 8 /* 16-bit little-endian */
+/** Link Training (LT)-tunable Physical Repeaters - DP 1.4a **/
+#define DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV 0xf0000
+#define DP_MAX_LINK_RATE_PHY_REPEATER 0xf0001
+#define DP_PHY_REPEATER_CNT 0xf0002
+#define DP_PHY_REPEATER_MODE 0xf0003
+#define DP_MAX_LANE_COUNT_PHY_REPEATER 0xf0004
+#define DP_PHY_REPEATER_EXTENDED_WAIT_TIMEOUT 0xf0005
+#define DP_TRAINING_PATTERN_SET_PHY_REPEATER1 0xf0010
+#define DP_TRAINING_LANE0_SET_PHY_REPEATER1 0xf0011
+#define DP_TRAINING_LANE1_SET_PHY_REPEATER1 0xf0012
+#define DP_TRAINING_LANE2_SET_PHY_REPEATER1 0xf0013
+#define DP_TRAINING_LANE3_SET_PHY_REPEATER1 0xf0014
+#define DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1 0xf0020
+#define DP_TRANSMITTER_CAPABILITY_PHY_REPEATER1 0xf0021
+#define DP_LANE0_1_STATUS_PHY_REPEATER1 0xf0030
+#define DP_LANE2_3_STATUS_PHY_REPEATER1 0xf0031
+#define DP_LANE_ALIGN_STATUS_UPDATED_PHY_REPEATER1 0xf0032
+#define DP_ADJUST_REQUEST_LANE0_1_PHY_REPEATER1 0xf0033
+#define DP_ADJUST_REQUEST_LANE2_3_PHY_REPEATER1 0xf0034
+#define DP_SYMBOL_ERROR_COUNT_LANE0_PHY_REPEATER1 0xf0035
+#define DP_SYMBOL_ERROR_COUNT_LANE1_PHY_REPEATER1 0xf0037
+#define DP_SYMBOL_ERROR_COUNT_LANE2_PHY_REPEATER1 0xf0039
+#define DP_SYMBOL_ERROR_COUNT_LANE3_PHY_REPEATER1 0xf003b
+#define DP_FEC_STATUS_PHY_REPEATER1 0xf0290
+
/* Multiple stream transport */
#define DP_FAUX_CAP 0x020 /* 1.2 */
# define DP_FAUX_CAP_1 (1 << 0)
--
2.23.0
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^ permalink raw reply related [flat|nested] 4+ messages in thread
* Re: [PATCH V2] drm: Add LTTPR defines for DP 1.4a
[not found] ` <20190826152925.4x7mwhzxit353yww-1ViLX0X+lBJGNQ1M2rI3KwRV3xvJKrda@public.gmane.org>
@ 2019-08-26 15:44 ` Harry Wentland
2019-08-27 8:16 ` Jani Nikula
1 sibling, 0 replies; 4+ messages in thread
From: Harry Wentland @ 2019-08-26 15:44 UTC (permalink / raw)
To: Siqueira, Rodrigo, amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Cc: Li, Sun peng (Leo), Berthe, Abdoulaye, Navare, Manasi D, Wentland, Harry
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+Cc Manasi, FYI
On 2019-08-26 11:29 a.m., Siqueira, Rodrigo wrote:
> DP 1.4a specification defines Link Training Tunable PHY Repeater (LTTPR)
> which is required to add support for systems with Thunderbolt or other
> repeater devices.
>
> Changes since V1:
> - Adjusts registers names to be aligned with spec and the rest of the
> file
> - Update spec comment from 1.4 to 1.4a
>
> Cc: Abdoulaye Berthe <Abdoulaye.Berthe-5C7GfCeVMHo@public.gmane.org>
> Cc: Harry Wentland <harry.wentland-5C7GfCeVMHo@public.gmane.org>
> Cc: Leo Li <sunpeng.li-5C7GfCeVMHo@public.gmane.org>
> Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira-5C7GfCeVMHo@public.gmane.org>
> Signed-off-by: Abdoulaye Berthe <Abdoulaye.Berthe-5C7GfCeVMHo@public.gmane.org>
Reviewed-by: Harry Wentland <harry.wentland-5C7GfCeVMHo@public.gmane.org>
Harry
> ---
> include/drm/drm_dp_helper.h | 25 +++++++++++++++++++++++++
> 1 file changed, 25 insertions(+)
>
> diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
> index 8364502f92cf..e8beb4e7e5da 100644
> --- a/include/drm/drm_dp_helper.h
> +++ b/include/drm/drm_dp_helper.h
> @@ -134,6 +134,31 @@
> #define DP_SUPPORTED_LINK_RATES 0x010 /* eDP 1.4 */
> # define DP_MAX_SUPPORTED_RATES 8 /* 16-bit little-endian */
>
> +/** Link Training (LT)-tunable Physical Repeaters - DP 1.4a **/
> +#define DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV 0xf0000
> +#define DP_MAX_LINK_RATE_PHY_REPEATER 0xf0001
> +#define DP_PHY_REPEATER_CNT 0xf0002
> +#define DP_PHY_REPEATER_MODE 0xf0003
> +#define DP_MAX_LANE_COUNT_PHY_REPEATER 0xf0004
> +#define DP_PHY_REPEATER_EXTENDED_WAIT_TIMEOUT 0xf0005
> +#define DP_TRAINING_PATTERN_SET_PHY_REPEATER1 0xf0010
> +#define DP_TRAINING_LANE0_SET_PHY_REPEATER1 0xf0011
> +#define DP_TRAINING_LANE1_SET_PHY_REPEATER1 0xf0012
> +#define DP_TRAINING_LANE2_SET_PHY_REPEATER1 0xf0013
> +#define DP_TRAINING_LANE3_SET_PHY_REPEATER1 0xf0014
> +#define DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1 0xf0020
> +#define DP_TRANSMITTER_CAPABILITY_PHY_REPEATER1 0xf0021
> +#define DP_LANE0_1_STATUS_PHY_REPEATER1 0xf0030
> +#define DP_LANE2_3_STATUS_PHY_REPEATER1 0xf0031
> +#define DP_LANE_ALIGN_STATUS_UPDATED_PHY_REPEATER1 0xf0032
> +#define DP_ADJUST_REQUEST_LANE0_1_PHY_REPEATER1 0xf0033
> +#define DP_ADJUST_REQUEST_LANE2_3_PHY_REPEATER1 0xf0034
> +#define DP_SYMBOL_ERROR_COUNT_LANE0_PHY_REPEATER1 0xf0035
> +#define DP_SYMBOL_ERROR_COUNT_LANE1_PHY_REPEATER1 0xf0037
> +#define DP_SYMBOL_ERROR_COUNT_LANE2_PHY_REPEATER1 0xf0039
> +#define DP_SYMBOL_ERROR_COUNT_LANE3_PHY_REPEATER1 0xf003b
> +#define DP_FEC_STATUS_PHY_REPEATER1 0xf0290
> +
> /* Multiple stream transport */
> #define DP_FAUX_CAP 0x020 /* 1.2 */
> # define DP_FAUX_CAP_1 (1 << 0)
>
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^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH V2] drm: Add LTTPR defines for DP 1.4a
[not found] ` <20190826152925.4x7mwhzxit353yww-1ViLX0X+lBJGNQ1M2rI3KwRV3xvJKrda@public.gmane.org>
2019-08-26 15:44 ` Harry Wentland
@ 2019-08-27 8:16 ` Jani Nikula
2019-08-28 19:58 ` Siqueira, Rodrigo
1 sibling, 1 reply; 4+ messages in thread
From: Jani Nikula @ 2019-08-27 8:16 UTC (permalink / raw)
To: Siqueira, Rodrigo, amd-gfx@lists.freedesktop.org,
dri-devel@lists.freedesktop.org
Cc: Li, Sun peng (Leo), Berthe, Abdoulaye
On Mon, 26 Aug 2019, "Siqueira, Rodrigo" <Rodrigo.Siqueira@amd.com> wrote:
> DP 1.4a specification defines Link Training Tunable PHY Repeater (LTTPR)
> which is required to add support for systems with Thunderbolt or other
> repeater devices.
>
> Changes since V1:
> - Adjusts registers names to be aligned with spec and the rest of the
> file
> - Update spec comment from 1.4 to 1.4a
>
> Cc: Abdoulaye Berthe <Abdoulaye.Berthe@amd.com>
> Cc: Harry Wentland <harry.wentland@amd.com>
> Cc: Leo Li <sunpeng.li@amd.com>
> Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
> Signed-off-by: Abdoulaye Berthe <Abdoulaye.Berthe@amd.com>
> ---
> include/drm/drm_dp_helper.h | 25 +++++++++++++++++++++++++
> 1 file changed, 25 insertions(+)
>
> diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
> index 8364502f92cf..e8beb4e7e5da 100644
> --- a/include/drm/drm_dp_helper.h
> +++ b/include/drm/drm_dp_helper.h
> @@ -134,6 +134,31 @@
> #define DP_SUPPORTED_LINK_RATES 0x010 /* eDP 1.4 */
> # define DP_MAX_SUPPORTED_RATES 8 /* 16-bit little-endian */
>
> +/** Link Training (LT)-tunable Physical Repeaters - DP 1.4a **/
This is not a kernel-doc comment, so please drop the double ** and use
regular comments.
All the DPCD register definitions are ordered according to register
offset. Why add 0xf0000 and friends between 0x10 and 0x20...?
BR,
Jani.
> +#define DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV 0xf0000
> +#define DP_MAX_LINK_RATE_PHY_REPEATER 0xf0001
> +#define DP_PHY_REPEATER_CNT 0xf0002
> +#define DP_PHY_REPEATER_MODE 0xf0003
> +#define DP_MAX_LANE_COUNT_PHY_REPEATER 0xf0004
> +#define DP_PHY_REPEATER_EXTENDED_WAIT_TIMEOUT 0xf0005
> +#define DP_TRAINING_PATTERN_SET_PHY_REPEATER1 0xf0010
> +#define DP_TRAINING_LANE0_SET_PHY_REPEATER1 0xf0011
> +#define DP_TRAINING_LANE1_SET_PHY_REPEATER1 0xf0012
> +#define DP_TRAINING_LANE2_SET_PHY_REPEATER1 0xf0013
> +#define DP_TRAINING_LANE3_SET_PHY_REPEATER1 0xf0014
> +#define DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1 0xf0020
> +#define DP_TRANSMITTER_CAPABILITY_PHY_REPEATER1 0xf0021
> +#define DP_LANE0_1_STATUS_PHY_REPEATER1 0xf0030
> +#define DP_LANE2_3_STATUS_PHY_REPEATER1 0xf0031
> +#define DP_LANE_ALIGN_STATUS_UPDATED_PHY_REPEATER1 0xf0032
> +#define DP_ADJUST_REQUEST_LANE0_1_PHY_REPEATER1 0xf0033
> +#define DP_ADJUST_REQUEST_LANE2_3_PHY_REPEATER1 0xf0034
> +#define DP_SYMBOL_ERROR_COUNT_LANE0_PHY_REPEATER1 0xf0035
> +#define DP_SYMBOL_ERROR_COUNT_LANE1_PHY_REPEATER1 0xf0037
> +#define DP_SYMBOL_ERROR_COUNT_LANE2_PHY_REPEATER1 0xf0039
> +#define DP_SYMBOL_ERROR_COUNT_LANE3_PHY_REPEATER1 0xf003b
> +#define DP_FEC_STATUS_PHY_REPEATER1 0xf0290
> +
> /* Multiple stream transport */
> #define DP_FAUX_CAP 0x020 /* 1.2 */
> # define DP_FAUX_CAP_1 (1 << 0)
--
Jani Nikula, Intel Open Source Graphics Center
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amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH V2] drm: Add LTTPR defines for DP 1.4a
2019-08-27 8:16 ` Jani Nikula
@ 2019-08-28 19:58 ` Siqueira, Rodrigo
0 siblings, 0 replies; 4+ messages in thread
From: Siqueira, Rodrigo @ 2019-08-28 19:58 UTC (permalink / raw)
To: Jani Nikula; +Cc: Li, Sun peng (Leo), Berthe, Abdoulaye, dri-devel, amd-gfx
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On 08/27, Jani Nikula wrote:
> On Mon, 26 Aug 2019, "Siqueira, Rodrigo" <Rodrigo.Siqueira@amd.com> wrote:
> > DP 1.4a specification defines Link Training Tunable PHY Repeater (LTTPR)
> > which is required to add support for systems with Thunderbolt or other
> > repeater devices.
> >
> > Changes since V1:
> > - Adjusts registers names to be aligned with spec and the rest of the
> > file
> > - Update spec comment from 1.4 to 1.4a
> >
> > Cc: Abdoulaye Berthe <Abdoulaye.Berthe@amd.com>
> > Cc: Harry Wentland <harry.wentland@amd.com>
> > Cc: Leo Li <sunpeng.li@amd.com>
> > Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
> > Signed-off-by: Abdoulaye Berthe <Abdoulaye.Berthe@amd.com>
> > ---
> > include/drm/drm_dp_helper.h | 25 +++++++++++++++++++++++++
> > 1 file changed, 25 insertions(+)
> >
> > diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
> > index 8364502f92cf..e8beb4e7e5da 100644
> > --- a/include/drm/drm_dp_helper.h
> > +++ b/include/drm/drm_dp_helper.h
> > @@ -134,6 +134,31 @@
> > #define DP_SUPPORTED_LINK_RATES 0x010 /* eDP 1.4 */
> > # define DP_MAX_SUPPORTED_RATES 8 /* 16-bit little-endian */
> >
> > +/** Link Training (LT)-tunable Physical Repeaters - DP 1.4a **/
>
> This is not a kernel-doc comment, so please drop the double ** and use
> regular comments.
>
> All the DPCD register definitions are ordered according to register
> offset. Why add 0xf0000 and friends between 0x10 and 0x20...?
Hi Jani,
Thank you for the feedback. I already sent a V3 patch based on your
comments; please let me know if you have any other suggestion.
Best Regards
> BR,
> Jani.
>
> > +#define DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV 0xf0000
> > +#define DP_MAX_LINK_RATE_PHY_REPEATER 0xf0001
> > +#define DP_PHY_REPEATER_CNT 0xf0002
> > +#define DP_PHY_REPEATER_MODE 0xf0003
> > +#define DP_MAX_LANE_COUNT_PHY_REPEATER 0xf0004
> > +#define DP_PHY_REPEATER_EXTENDED_WAIT_TIMEOUT 0xf0005
> > +#define DP_TRAINING_PATTERN_SET_PHY_REPEATER1 0xf0010
> > +#define DP_TRAINING_LANE0_SET_PHY_REPEATER1 0xf0011
> > +#define DP_TRAINING_LANE1_SET_PHY_REPEATER1 0xf0012
> > +#define DP_TRAINING_LANE2_SET_PHY_REPEATER1 0xf0013
> > +#define DP_TRAINING_LANE3_SET_PHY_REPEATER1 0xf0014
> > +#define DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1 0xf0020
> > +#define DP_TRANSMITTER_CAPABILITY_PHY_REPEATER1 0xf0021
> > +#define DP_LANE0_1_STATUS_PHY_REPEATER1 0xf0030
> > +#define DP_LANE2_3_STATUS_PHY_REPEATER1 0xf0031
> > +#define DP_LANE_ALIGN_STATUS_UPDATED_PHY_REPEATER1 0xf0032
> > +#define DP_ADJUST_REQUEST_LANE0_1_PHY_REPEATER1 0xf0033
> > +#define DP_ADJUST_REQUEST_LANE2_3_PHY_REPEATER1 0xf0034
> > +#define DP_SYMBOL_ERROR_COUNT_LANE0_PHY_REPEATER1 0xf0035
> > +#define DP_SYMBOL_ERROR_COUNT_LANE1_PHY_REPEATER1 0xf0037
> > +#define DP_SYMBOL_ERROR_COUNT_LANE2_PHY_REPEATER1 0xf0039
> > +#define DP_SYMBOL_ERROR_COUNT_LANE3_PHY_REPEATER1 0xf003b
> > +#define DP_FEC_STATUS_PHY_REPEATER1 0xf0290
> > +
> > /* Multiple stream transport */
> > #define DP_FAUX_CAP 0x020 /* 1.2 */
> > # define DP_FAUX_CAP_1 (1 << 0)
>
> --
> Jani Nikula, Intel Open Source Graphics Center
--
Rodrigo Siqueira
Software Engineer, Advanced Micro Devices (AMD)
https://siqueira.tech
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end of thread, other threads:[~2019-08-28 19:58 UTC | newest]
Thread overview: 4+ messages (download: mbox.gz / follow: Atom feed)
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2019-08-26 15:29 [PATCH V2] drm: Add LTTPR defines for DP 1.4a Siqueira, Rodrigo
[not found] ` <20190826152925.4x7mwhzxit353yww-1ViLX0X+lBJGNQ1M2rI3KwRV3xvJKrda@public.gmane.org>
2019-08-26 15:44 ` Harry Wentland
2019-08-27 8:16 ` Jani Nikula
2019-08-28 19:58 ` Siqueira, Rodrigo
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