* [PATCH v7 00/12] SVE feature for arm guests
@ 2023-05-23 7:43 Luca Fancellu
2023-05-23 7:43 ` [PATCH v7 01/12] xen/arm: enable SVE extension for Xen Luca Fancellu
` (12 more replies)
0 siblings, 13 replies; 49+ messages in thread
From: Luca Fancellu @ 2023-05-23 7:43 UTC (permalink / raw)
To: xen-devel
Cc: bertrand.marquis, wei.chen, Stefano Stabellini, Julien Grall,
Volodymyr Babchuk, Andrew Cooper, George Dunlap, Jan Beulich,
Wei Liu, Roger Pau Monné,
Nick Rosbrook, Anthony PERARD, Juergen Gross, Christian Lindig,
David Scott, Marek Marczykowski-Górecki, Henry Wang,
Community Manager
This serie is introducing the possibility for Dom0 and DomU guests to use
sve/sve2 instructions.
SVE feature introduces new instruction and registers to improve performances on
floating point operations.
The SVE feature is advertised using the ID_AA64PFR0_EL1 register, SVE field, and
when available the ID_AA64ZFR0_EL1 register provides additional information
about the implemented version and other SVE feature.
New registers added by the SVE feature are Z0-Z31, P0-P15, FFR, ZCR_ELx.
Z0-Z31 are scalable vector register whose size is implementation defined and
goes from 128 bits to maximum 2048, the term vector length will be used to refer
to this quantity.
P0-P15 are predicate registers and the size is the vector length divided by 8,
same size is the FFR (First Fault Register).
ZCR_ELx is a register that can control and restrict the maximum vector length
used by the <x> exception level and all the lower exception levels, so for
example EL3 can restrict the vector length usable by EL3,2,1,0.
The platform has a maximum implemented vector length, so for every value
written in ZCR register, if this value is above the implemented length, then the
lower value will be used. The RDVL instruction can be used to check what vector
length is the HW using after setting ZCR.
For an SVE guest, the V0-V31 registers are part of the Z0-Z31, so there is no
need to save them separately, saving Z0-Z31 will save implicitly also V0-V31.
SVE usage can be trapped using a flag in CPTR_EL2, hence in this serie the
register is added to the domain state, to be able to trap only the guests that
are not allowed to use SVE.
This serie is introducing a command line parameter to enable Dom0 to use SVE and
to set its maximum vector length that by default is 0 which means the guest is
not allowed to use SVE. Values from 128 to 2048 mean the guest can use SVE with
the selected value used as maximum allowed vector length (which could be lower
if the implemented one is lower).
For DomUs, an XL parameter with the same way of use is introduced and a dom0less
DTB binding is created.
The context switch is the most critical part because there can be big registers
to be saved, in this serie an easy approach is used and the context is
saved/restored every time for the guests that are allowed to use SVE.
Luca Fancellu (12):
xen/arm: enable SVE extension for Xen
xen/arm: add SVE vector length field to the domain
xen/arm: Expose SVE feature to the guest
xen/arm: add SVE exception class handling
arm/sve: save/restore SVE context switch
xen/common: add dom0 xen command line argument for Arm
xen: enable Dom0 to use SVE feature
xen/physinfo: encode Arm SVE vector length in arch_capabilities
tools: add physinfo arch_capabilities handling for Arm
xen/tools: add sve parameter in XL configuration
xen/arm: add sve property for dom0less domUs
xen/changelog: Add SVE and "dom0" options to the changelog for Arm
CHANGELOG.md | 3 +
SUPPORT.md | 6 +
docs/man/xl.cfg.5.pod.in | 16 ++
docs/misc/arm/device-tree/booting.txt | 16 ++
docs/misc/xen-command-line.pandoc | 20 +-
tools/golang/xenlight/helpers.gen.go | 4 +
tools/golang/xenlight/types.gen.go | 24 +++
tools/include/libxl.h | 11 +
.../include/xen-tools/arm-arch-capabilities.h | 28 +++
tools/include/xen-tools/common-macros.h | 2 +
tools/libs/light/libxl.c | 1 +
tools/libs/light/libxl_arm.c | 33 +++
tools/libs/light/libxl_internal.h | 1 -
tools/libs/light/libxl_types.idl | 23 +++
tools/ocaml/libs/xc/xenctrl.ml | 4 +-
tools/ocaml/libs/xc/xenctrl.mli | 4 +-
tools/ocaml/libs/xc/xenctrl_stubs.c | 8 +-
tools/python/xen/lowlevel/xc/xc.c | 8 +-
tools/xl/xl_info.c | 8 +
tools/xl/xl_parse.c | 8 +
xen/arch/arm/Kconfig | 10 +-
xen/arch/arm/README.LinuxPrimitives | 11 +
xen/arch/arm/arm64/Makefile | 1 +
xen/arch/arm/arm64/cpufeature.c | 7 +-
xen/arch/arm/arm64/domctl.c | 4 +
xen/arch/arm/arm64/sve-asm.S | 195 ++++++++++++++++++
xen/arch/arm/arm64/sve.c | 182 ++++++++++++++++
xen/arch/arm/arm64/vfp.c | 79 ++++---
xen/arch/arm/arm64/vsysreg.c | 41 +++-
xen/arch/arm/cpufeature.c | 6 +-
xen/arch/arm/domain.c | 55 ++++-
xen/arch/arm/domain_build.c | 66 ++++++
xen/arch/arm/include/asm/arm64/sve.h | 72 +++++++
xen/arch/arm/include/asm/arm64/sysregs.h | 4 +
xen/arch/arm/include/asm/arm64/vfp.h | 12 ++
xen/arch/arm/include/asm/cpufeature.h | 14 ++
xen/arch/arm/include/asm/domain.h | 8 +
xen/arch/arm/include/asm/processor.h | 3 +
xen/arch/arm/setup.c | 5 +-
xen/arch/arm/sysctl.c | 4 +
xen/arch/arm/traps.c | 36 +++-
xen/arch/x86/dom0_build.c | 48 ++---
xen/common/domain.c | 23 +++
xen/common/kernel.c | 28 +++
xen/include/public/arch-arm.h | 2 +
xen/include/public/sysctl.h | 4 +
xen/include/xen/domain.h | 1 +
xen/include/xen/lib.h | 10 +
48 files changed, 1052 insertions(+), 107 deletions(-)
create mode 100644 tools/include/xen-tools/arm-arch-capabilities.h
create mode 100644 xen/arch/arm/arm64/sve-asm.S
create mode 100644 xen/arch/arm/arm64/sve.c
create mode 100644 xen/arch/arm/include/asm/arm64/sve.h
--
2.34.1
^ permalink raw reply [flat|nested] 49+ messages in thread
* [PATCH v7 01/12] xen/arm: enable SVE extension for Xen
2023-05-23 7:43 [PATCH v7 00/12] SVE feature for arm guests Luca Fancellu
@ 2023-05-23 7:43 ` Luca Fancellu
2023-05-24 9:01 ` Bertrand Marquis
` (2 more replies)
2023-05-23 7:43 ` [PATCH v7 02/12] xen/arm: add SVE vector length field to the domain Luca Fancellu
` (11 subsequent siblings)
12 siblings, 3 replies; 49+ messages in thread
From: Luca Fancellu @ 2023-05-23 7:43 UTC (permalink / raw)
To: xen-devel
Cc: bertrand.marquis, wei.chen, Stefano Stabellini, Julien Grall,
Volodymyr Babchuk
Enable Xen to handle the SVE extension, add code in cpufeature module
to handle ZCR SVE register, disable trapping SVE feature on system
boot only when SVE resources are accessed.
While there, correct coding style for the comment on coprocessor
trapping.
Now cptr_el2 is part of the domain context and it will be restored
on context switch, this is a preparation for saving the SVE context
which will be part of VFP operations, so restore it before the call
to save VFP registers.
To save an additional isb barrier, restore cptr_el2 before an
existing isb barrier and move the call for saving VFP context after
that barrier. To keep a (mostly) specularity of ctxt_switch_to()
and ctxt_switch_from(), move vfp_save_state() up in the function.
Change the KConfig entry to make ARM64_SVE symbol selectable, by
default it will be not selected.
Create sve module and sve_asm.S that contains assembly routines for
the SVE feature, this code is inspired from linux and it uses
instruction encoding to be compatible with compilers that does not
support SVE, imported instructions are documented in
README.LinuxPrimitives.
Signed-off-by: Luca Fancellu <luca.fancellu@arm.com>
---
Changes from v6:
- modified licence, add emacs block, move vfp_save_state up in the
function, add comments to CPTR_EL2 and vfp_restore_state, don't
use variable in init_traps(), code style fixes,
add entries to README.LinuxPrimitives (Julien)
- vl_to_zcr is moved into sve.c module as changes to the series led
to its usage only inside it, remove stub for compute_max_zcr and
rely on compiler DCE.
Changes from v5:
- Add R-by Bertrand
Changes from v4:
- don't use fixed types in vl_to_zcr, forgot to address that in
v3, by mistake I changed that in patch 2, fixing now (Jan)
Changes from v3:
- no changes
Changes from v2:
- renamed sve_asm.S in sve-asm.S, new files should not contain
underscore in the name (Jan)
Changes from v1:
- Add assert to vl_to_zcr, it is never called with vl==0, but just
to be sure it won't in the future.
Changes from RFC:
- Moved restoring of cptr before an existing barrier (Julien)
- Marked the feature as unsupported for now (Julien)
- Trap and un-trap only when using SVE resources in
compute_max_zcr() (Julien)
---
xen/arch/arm/Kconfig | 10 ++--
xen/arch/arm/README.LinuxPrimitives | 9 ++++
xen/arch/arm/arm64/Makefile | 1 +
xen/arch/arm/arm64/cpufeature.c | 7 ++-
xen/arch/arm/arm64/sve-asm.S | 48 +++++++++++++++++++
xen/arch/arm/arm64/sve.c | 59 ++++++++++++++++++++++++
xen/arch/arm/cpufeature.c | 6 ++-
xen/arch/arm/domain.c | 20 +++++---
xen/arch/arm/include/asm/arm64/sve.h | 27 +++++++++++
xen/arch/arm/include/asm/arm64/sysregs.h | 1 +
xen/arch/arm/include/asm/cpufeature.h | 14 ++++++
xen/arch/arm/include/asm/domain.h | 1 +
xen/arch/arm/include/asm/processor.h | 2 +
xen/arch/arm/setup.c | 5 +-
xen/arch/arm/traps.c | 27 ++++++-----
15 files changed, 210 insertions(+), 27 deletions(-)
create mode 100644 xen/arch/arm/arm64/sve-asm.S
create mode 100644 xen/arch/arm/arm64/sve.c
create mode 100644 xen/arch/arm/include/asm/arm64/sve.h
diff --git a/xen/arch/arm/Kconfig b/xen/arch/arm/Kconfig
index 239d3aed3c7f..41f45d8d1203 100644
--- a/xen/arch/arm/Kconfig
+++ b/xen/arch/arm/Kconfig
@@ -112,11 +112,15 @@ config ARM64_PTR_AUTH
This feature is not supported in Xen.
config ARM64_SVE
- def_bool n
+ bool "Enable Scalar Vector Extension support (UNSUPPORTED)" if UNSUPPORTED
depends on ARM_64
help
- Scalar Vector Extension support.
- This feature is not supported in Xen.
+ Scalar Vector Extension (SVE/SVE2) support for guests.
+
+ Please be aware that currently, enabling this feature will add latency on
+ VM context switch between SVE enabled guests, between not-enabled SVE
+ guests and SVE enabled guests and viceversa, compared to the time
+ required to switch between not-enabled SVE guests.
config ARM64_MTE
def_bool n
diff --git a/xen/arch/arm/README.LinuxPrimitives b/xen/arch/arm/README.LinuxPrimitives
index 1d53e6a898da..76c8df29e416 100644
--- a/xen/arch/arm/README.LinuxPrimitives
+++ b/xen/arch/arm/README.LinuxPrimitives
@@ -62,6 +62,15 @@ done
linux/arch/arm64/lib/clear_page.S xen/arch/arm/arm64/lib/clear_page.S
linux/arch/arm64/lib/copy_page.S unused in Xen
+---------------------------------------------------------------------
+
+SVE assembly macro: last sync @ v6.3.0 (last commit: 457391b03803)
+
+linux/arch/arm64/include/asm/fpsimdmacros.h xen/arch/arm/include/asm/arm64/sve-asm.S
+
+The following macros were taken from Linux:
+ _check_general_reg, _check_num, _sve_rdvl
+
=====================================================================
arm32
=====================================================================
diff --git a/xen/arch/arm/arm64/Makefile b/xen/arch/arm/arm64/Makefile
index 28481393e98f..54ad55c75cda 100644
--- a/xen/arch/arm/arm64/Makefile
+++ b/xen/arch/arm/arm64/Makefile
@@ -13,6 +13,7 @@ obj-$(CONFIG_LIVEPATCH) += livepatch.o
obj-y += mm.o
obj-y += smc.o
obj-y += smpboot.o
+obj-$(CONFIG_ARM64_SVE) += sve.o sve-asm.o
obj-y += traps.o
obj-y += vfp.o
obj-y += vsysreg.o
diff --git a/xen/arch/arm/arm64/cpufeature.c b/xen/arch/arm/arm64/cpufeature.c
index d9039d37b2d1..b4656ff4d80f 100644
--- a/xen/arch/arm/arm64/cpufeature.c
+++ b/xen/arch/arm/arm64/cpufeature.c
@@ -455,15 +455,11 @@ static const struct arm64_ftr_bits ftr_id_dfr1[] = {
ARM64_FTR_END,
};
-#if 0
-/* TODO: use this to sanitize SVE once we support it */
-
static const struct arm64_ftr_bits ftr_zcr[] = {
ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE,
ZCR_ELx_LEN_SHIFT, ZCR_ELx_LEN_SIZE, 0), /* LEN */
ARM64_FTR_END,
};
-#endif
/*
* Common ftr bits for a 32bit register with all hidden, strict
@@ -603,6 +599,9 @@ void update_system_features(const struct cpuinfo_arm *new)
SANITIZE_ID_REG(zfr64, 0, aa64zfr0);
+ if ( cpu_has_sve )
+ SANITIZE_REG(zcr64, 0, zcr);
+
/*
* Comment from Linux:
* Userspace may perform DC ZVA instructions. Mismatched block sizes
diff --git a/xen/arch/arm/arm64/sve-asm.S b/xen/arch/arm/arm64/sve-asm.S
new file mode 100644
index 000000000000..4d1549344733
--- /dev/null
+++ b/xen/arch/arm/arm64/sve-asm.S
@@ -0,0 +1,48 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Arm SVE assembly routines
+ *
+ * Copyright (C) 2022 ARM Ltd.
+ *
+ * Some macros and instruction encoding in this file are taken from linux 6.1.1,
+ * file arch/arm64/include/asm/fpsimdmacros.h, some of them are a modified
+ * version.
+ */
+
+/* Sanity-check macros to help avoid encoding garbage instructions */
+
+.macro _check_general_reg nr
+ .if (\nr) < 0 || (\nr) > 30
+ .error "Bad register number \nr."
+ .endif
+.endm
+
+.macro _check_num n, min, max
+ .if (\n) < (\min) || (\n) > (\max)
+ .error "Number \n out of range [\min,\max]"
+ .endif
+.endm
+
+/* SVE instruction encodings for non-SVE-capable assemblers */
+/* (pre binutils 2.28, all kernel capable clang versions support SVE) */
+
+/* RDVL X\nx, #\imm */
+.macro _sve_rdvl nx, imm
+ _check_general_reg \nx
+ _check_num (\imm), -0x20, 0x1f
+ .inst 0x04bf5000 \
+ | (\nx) \
+ | (((\imm) & 0x3f) << 5)
+.endm
+
+/* Gets the current vector register size in bytes */
+GLOBAL(sve_get_hw_vl)
+ _sve_rdvl 0, 1
+ ret
+
+/*
+ * Local variables:
+ * mode: ASM
+ * indent-tabs-mode: nil
+ * End:
+ */
diff --git a/xen/arch/arm/arm64/sve.c b/xen/arch/arm/arm64/sve.c
new file mode 100644
index 000000000000..e05ccc38a896
--- /dev/null
+++ b/xen/arch/arm/arm64/sve.c
@@ -0,0 +1,59 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Arm SVE feature code
+ *
+ * Copyright (C) 2022 ARM Ltd.
+ */
+
+#include <xen/types.h>
+#include <asm/arm64/sve.h>
+#include <asm/arm64/sysregs.h>
+#include <asm/processor.h>
+#include <asm/system.h>
+
+extern unsigned int sve_get_hw_vl(void);
+
+/* Takes a vector length in bits and returns the ZCR_ELx encoding */
+static inline register_t vl_to_zcr(unsigned int vl)
+{
+ ASSERT(vl > 0);
+ return ((vl / SVE_VL_MULTIPLE_VAL) - 1U) & ZCR_ELx_LEN_MASK;
+}
+
+register_t compute_max_zcr(void)
+{
+ register_t cptr_bits = get_default_cptr_flags();
+ register_t zcr = vl_to_zcr(SVE_VL_MAX_BITS);
+ unsigned int hw_vl;
+
+ /* Remove trap for SVE resources */
+ WRITE_SYSREG(cptr_bits & ~HCPTR_CP(8), CPTR_EL2);
+ isb();
+
+ /*
+ * Set the maximum SVE vector length, doing that we will know the VL
+ * supported by the platform, calling sve_get_hw_vl()
+ */
+ WRITE_SYSREG(zcr, ZCR_EL2);
+
+ /*
+ * Read the maximum VL, which could be lower than what we imposed before,
+ * hw_vl contains VL in bytes, multiply it by 8 to use vl_to_zcr() later
+ */
+ hw_vl = sve_get_hw_vl() * 8U;
+
+ /* Restore CPTR_EL2 */
+ WRITE_SYSREG(cptr_bits, CPTR_EL2);
+ isb();
+
+ return vl_to_zcr(hw_vl);
+}
+
+/*
+ * Local variables:
+ * mode: C
+ * c-file-style: "BSD"
+ * c-basic-offset: 4
+ * indent-tabs-mode: nil
+ * End:
+ */
diff --git a/xen/arch/arm/cpufeature.c b/xen/arch/arm/cpufeature.c
index c4ec38bb2554..83b84368f6d5 100644
--- a/xen/arch/arm/cpufeature.c
+++ b/xen/arch/arm/cpufeature.c
@@ -9,6 +9,7 @@
#include <xen/init.h>
#include <xen/smp.h>
#include <xen/stop_machine.h>
+#include <asm/arm64/sve.h>
#include <asm/cpufeature.h>
DECLARE_BITMAP(cpu_hwcaps, ARM_NCAPS);
@@ -143,6 +144,9 @@ void identify_cpu(struct cpuinfo_arm *c)
c->zfr64.bits[0] = READ_SYSREG(ID_AA64ZFR0_EL1);
+ if ( cpu_has_sve )
+ c->zcr64.bits[0] = compute_max_zcr();
+
c->dczid.bits[0] = READ_SYSREG(DCZID_EL0);
c->ctr.bits[0] = READ_SYSREG(CTR_EL0);
@@ -199,7 +203,7 @@ static int __init create_guest_cpuinfo(void)
guest_cpuinfo.pfr64.mpam = 0;
guest_cpuinfo.pfr64.mpam_frac = 0;
- /* Hide SVE as Xen does not support it */
+ /* Hide SVE by default to the guests */
guest_cpuinfo.pfr64.sve = 0;
guest_cpuinfo.zfr64.bits[0] = 0;
diff --git a/xen/arch/arm/domain.c b/xen/arch/arm/domain.c
index d8ef6501ff8e..d5ab15db46c4 100644
--- a/xen/arch/arm/domain.c
+++ b/xen/arch/arm/domain.c
@@ -95,6 +95,9 @@ static void ctxt_switch_from(struct vcpu *p)
/* CP 15 */
p->arch.csselr = READ_SYSREG(CSSELR_EL1);
+ /* VFP */
+ vfp_save_state(p);
+
/* Control Registers */
p->arch.cpacr = READ_SYSREG(CPACR_EL1);
@@ -155,9 +158,6 @@ static void ctxt_switch_from(struct vcpu *p)
/* XXX MPU */
- /* VFP */
- vfp_save_state(p);
-
/* VGIC */
gic_save_state(p);
@@ -181,9 +181,6 @@ static void ctxt_switch_to(struct vcpu *n)
/* VGIC */
gic_restore_state(n);
- /* VFP */
- vfp_restore_state(n);
-
/* XXX MPU */
/* Fault Status */
@@ -256,8 +253,17 @@ static void ctxt_switch_to(struct vcpu *n)
WRITE_CP32(n->arch.joscr, JOSCR);
WRITE_CP32(n->arch.jmcr, JMCR);
#endif
+
+ /*
+ * CPTR_EL2 needs to be written before calling vfp_restore_state, a
+ * synchronization instruction is expected after the write (isb)
+ */
+ WRITE_SYSREG(n->arch.cptr_el2, CPTR_EL2);
isb();
+ /* VFP - call vfp_restore_state after writing on CPTR_EL2 + isb */
+ vfp_restore_state(n);
+
/* CP 15 */
WRITE_SYSREG(n->arch.csselr, CSSELR_EL1);
@@ -548,6 +554,8 @@ int arch_vcpu_create(struct vcpu *v)
v->arch.vmpidr = MPIDR_SMP | vcpuid_to_vaffinity(v->vcpu_id);
+ v->arch.cptr_el2 = get_default_cptr_flags();
+
v->arch.hcr_el2 = get_default_hcr_flags();
v->arch.mdcr_el2 = HDCR_TDRA | HDCR_TDOSA | HDCR_TDA;
diff --git a/xen/arch/arm/include/asm/arm64/sve.h b/xen/arch/arm/include/asm/arm64/sve.h
new file mode 100644
index 000000000000..c0466243c7bc
--- /dev/null
+++ b/xen/arch/arm/include/asm/arm64/sve.h
@@ -0,0 +1,27 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Arm SVE feature code
+ *
+ * Copyright (C) 2022 ARM Ltd.
+ */
+
+#ifndef _ARM_ARM64_SVE_H
+#define _ARM_ARM64_SVE_H
+
+#define SVE_VL_MAX_BITS 2048U
+
+/* Vector length must be multiple of 128 */
+#define SVE_VL_MULTIPLE_VAL 128U
+
+register_t compute_max_zcr(void);
+
+#endif /* _ARM_ARM64_SVE_H */
+
+/*
+ * Local variables:
+ * mode: C
+ * c-file-style: "BSD"
+ * c-basic-offset: 4
+ * indent-tabs-mode: nil
+ * End:
+ */
diff --git a/xen/arch/arm/include/asm/arm64/sysregs.h b/xen/arch/arm/include/asm/arm64/sysregs.h
index 463899951414..4cabb9eb4d5e 100644
--- a/xen/arch/arm/include/asm/arm64/sysregs.h
+++ b/xen/arch/arm/include/asm/arm64/sysregs.h
@@ -24,6 +24,7 @@
#define ICH_EISR_EL2 S3_4_C12_C11_3
#define ICH_ELSR_EL2 S3_4_C12_C11_5
#define ICH_VMCR_EL2 S3_4_C12_C11_7
+#define ZCR_EL2 S3_4_C1_C2_0
#define __LR0_EL2(x) S3_4_C12_C12_ ## x
#define __LR8_EL2(x) S3_4_C12_C13_ ## x
diff --git a/xen/arch/arm/include/asm/cpufeature.h b/xen/arch/arm/include/asm/cpufeature.h
index c62cf6293fd6..03fe684b4d36 100644
--- a/xen/arch/arm/include/asm/cpufeature.h
+++ b/xen/arch/arm/include/asm/cpufeature.h
@@ -32,6 +32,12 @@
#define cpu_has_thumbee (boot_cpu_feature32(thumbee) == 1)
#define cpu_has_aarch32 (cpu_has_arm || cpu_has_thumb)
+#ifdef CONFIG_ARM64_SVE
+#define cpu_has_sve (boot_cpu_feature64(sve) == 1)
+#else
+#define cpu_has_sve 0
+#endif
+
#ifdef CONFIG_ARM_32
#define cpu_has_gicv3 (boot_cpu_feature32(gic) >= 1)
#define cpu_has_gentimer (boot_cpu_feature32(gentimer) == 1)
@@ -323,6 +329,14 @@ struct cpuinfo_arm {
};
} isa64;
+ union {
+ register_t bits[1];
+ struct {
+ unsigned long len:4;
+ unsigned long __res0:60;
+ };
+ } zcr64;
+
struct {
register_t bits[1];
} zfr64;
diff --git a/xen/arch/arm/include/asm/domain.h b/xen/arch/arm/include/asm/domain.h
index 2a51f0ca688e..e776ee704b7d 100644
--- a/xen/arch/arm/include/asm/domain.h
+++ b/xen/arch/arm/include/asm/domain.h
@@ -190,6 +190,7 @@ struct arch_vcpu
register_t tpidrro_el0;
/* HYP configuration */
+ register_t cptr_el2;
register_t hcr_el2;
register_t mdcr_el2;
diff --git a/xen/arch/arm/include/asm/processor.h b/xen/arch/arm/include/asm/processor.h
index 54f253087718..bc683334125c 100644
--- a/xen/arch/arm/include/asm/processor.h
+++ b/xen/arch/arm/include/asm/processor.h
@@ -582,6 +582,8 @@ void do_trap_guest_serror(struct cpu_user_regs *regs);
register_t get_default_hcr_flags(void);
+register_t get_default_cptr_flags(void);
+
/*
* Synchronize SError unless the feature is selected.
* This is relying on the SErrors are currently unmasked.
diff --git a/xen/arch/arm/setup.c b/xen/arch/arm/setup.c
index 6f9f4d8c8a15..4191a766767a 100644
--- a/xen/arch/arm/setup.c
+++ b/xen/arch/arm/setup.c
@@ -135,10 +135,11 @@ static void __init processor_id(void)
cpu_has_el2_32 ? "64+32" : cpu_has_el2_64 ? "64" : "No",
cpu_has_el1_32 ? "64+32" : cpu_has_el1_64 ? "64" : "No",
cpu_has_el0_32 ? "64+32" : cpu_has_el0_64 ? "64" : "No");
- printk(" Extensions:%s%s%s\n",
+ printk(" Extensions:%s%s%s%s\n",
cpu_has_fp ? " FloatingPoint" : "",
cpu_has_simd ? " AdvancedSIMD" : "",
- cpu_has_gicv3 ? " GICv3-SysReg" : "");
+ cpu_has_gicv3 ? " GICv3-SysReg" : "",
+ cpu_has_sve ? " SVE" : "");
/* Warn user if we find unknown floating-point features */
if ( cpu_has_fp && (boot_cpu_feature64(fp) >= 2) )
diff --git a/xen/arch/arm/traps.c b/xen/arch/arm/traps.c
index d40c331a4e9c..3393e10b52e6 100644
--- a/xen/arch/arm/traps.c
+++ b/xen/arch/arm/traps.c
@@ -93,6 +93,21 @@ register_t get_default_hcr_flags(void)
HCR_TID3|HCR_TSC|HCR_TAC|HCR_SWIO|HCR_TIDCP|HCR_FB|HCR_TSW);
}
+register_t get_default_cptr_flags(void)
+{
+ /*
+ * Trap all coprocessor registers (0-13) except cp10 and
+ * cp11 for VFP.
+ *
+ * /!\ All coprocessors except cp10 and cp11 cannot be used in Xen.
+ *
+ * On ARM64 the TCPx bits which we set here (0..9,12,13) are all
+ * RES1, i.e. they would trap whether we did this write or not.
+ */
+ return ((HCPTR_CP_MASK & ~(HCPTR_CP(10) | HCPTR_CP(11))) |
+ HCPTR_TTA | HCPTR_TAM);
+}
+
static enum {
SERRORS_DIVERSE,
SERRORS_PANIC,
@@ -135,17 +150,7 @@ void init_traps(void)
/* Trap CP15 c15 used for implementation defined registers */
WRITE_SYSREG(HSTR_T(15), HSTR_EL2);
- /* Trap all coprocessor registers (0-13) except cp10 and
- * cp11 for VFP.
- *
- * /!\ All coprocessors except cp10 and cp11 cannot be used in Xen.
- *
- * On ARM64 the TCPx bits which we set here (0..9,12,13) are all
- * RES1, i.e. they would trap whether we did this write or not.
- */
- WRITE_SYSREG((HCPTR_CP_MASK & ~(HCPTR_CP(10) | HCPTR_CP(11))) |
- HCPTR_TTA | HCPTR_TAM,
- CPTR_EL2);
+ WRITE_SYSREG(get_default_cptr_flags(), CPTR_EL2);
/*
* Configure HCR_EL2 with the bare minimum to run Xen until a guest
--
2.34.1
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [PATCH v7 02/12] xen/arm: add SVE vector length field to the domain
2023-05-23 7:43 [PATCH v7 00/12] SVE feature for arm guests Luca Fancellu
2023-05-23 7:43 ` [PATCH v7 01/12] xen/arm: enable SVE extension for Xen Luca Fancellu
@ 2023-05-23 7:43 ` Luca Fancellu
2023-05-24 9:23 ` Bertrand Marquis
2023-05-25 8:59 ` Julien Grall
2023-05-23 7:43 ` [PATCH v7 03/12] xen/arm: Expose SVE feature to the guest Luca Fancellu
` (10 subsequent siblings)
12 siblings, 2 replies; 49+ messages in thread
From: Luca Fancellu @ 2023-05-23 7:43 UTC (permalink / raw)
To: xen-devel
Cc: bertrand.marquis, wei.chen, Stefano Stabellini, Julien Grall,
Volodymyr Babchuk
Add sve_vl field to arch_domain and xen_arch_domainconfig struct,
to allow the domain to have an information about the SVE feature
and the number of SVE register bits that are allowed for this
domain.
sve_vl field is the vector length in bits divided by 128, this
allows to use less space in the structures.
The field is used also to allow or forbid a domain to use SVE,
because a value equal to zero means the guest is not allowed to
use the feature.
Check that the requested vector length is lower or equal to the
platform supported vector length, otherwise fail on domain
creation.
Check that only 64 bit domains have SVE enabled, otherwise fail.
Signed-off-by: Luca Fancellu <luca.fancellu@arm.com>
---
Changes from v6:
- Style fix, have is_sve_domain as static inline instead of macro
(Julien)
Changes from v5:
- Update commit message stating the interface ver. bump (Bertrand)
- in struct arch_domain, protect sve_vl with CONFIG_ARM64_SVE,
given the change, move also is_sve_domain() where it's protected
inside sve.h and create a stub when the macro is not defined,
protect the usage of sve_vl where needed.
(Julien)
- Add a check for 32 bit guest running on top of 64 bit host that
have sve parameter enabled to stop the domain creation, added in
construct_domain() of domain_build.c and subarch_do_domctl of
domctl.c. (Julien)
Changes from v4:
- Return 0 in get_sys_vl_len() if sve is not supported, code style fix,
removed else if since the conditions can't fallthrough, removed not
needed condition checking for VL bits validity because it's already
covered, so delete is_vl_valid() function. (Jan)
Changes from v3:
- don't use fixed types when not needed, use encoded value also in
arch_domain so rename sve_vl_bits in sve_vl. (Jan)
- rename domainconfig_decode_vl to sve_decode_vl because it will now
be used also to decode from arch_domain value
- change sve_vl from uint16_t to uint8_t and move it after "type" field
to optimize space.
Changes from v2:
- rename field in xen_arch_domainconfig from "sve_vl_bits" to
"sve_vl" and use the implicit padding after gic_version to
store it, now this field is the VL/128. (Jan)
- Created domainconfig_decode_vl() function to decode the sve_vl
field and use it as plain bits value inside arch_domain.
- Changed commit message reflecting the changes
Changes from v1:
- no changes
Changes from RFC:
- restore zcr_el2 in sve_restore_state, that will be introduced
later in this serie, so remove zcr_el2 related code from this
patch and move everything to the later patch (Julien)
- add explicit padding into struct xen_arch_domainconfig (Julien)
- Don't lower down the vector length, just fail to create the
domain. (Julien)
---
xen/arch/arm/arm64/domctl.c | 4 ++++
xen/arch/arm/arm64/sve.c | 12 +++++++++++
xen/arch/arm/domain.c | 29 ++++++++++++++++++++++++++
xen/arch/arm/domain_build.c | 7 +++++++
xen/arch/arm/include/asm/arm64/sve.h | 31 ++++++++++++++++++++++++++++
xen/arch/arm/include/asm/domain.h | 5 +++++
xen/include/public/arch-arm.h | 2 ++
7 files changed, 90 insertions(+)
diff --git a/xen/arch/arm/arm64/domctl.c b/xen/arch/arm/arm64/domctl.c
index 0de89b42c448..14fc622e9956 100644
--- a/xen/arch/arm/arm64/domctl.c
+++ b/xen/arch/arm/arm64/domctl.c
@@ -10,6 +10,7 @@
#include <xen/sched.h>
#include <xen/hypercall.h>
#include <public/domctl.h>
+#include <asm/arm64/sve.h>
#include <asm/cpufeature.h>
static long switch_mode(struct domain *d, enum domain_type type)
@@ -43,6 +44,9 @@ long subarch_do_domctl(struct xen_domctl *domctl, struct domain *d,
case 32:
if ( !cpu_has_el1_32 )
return -EINVAL;
+ /* SVE is not supported for 32 bit domain */
+ if ( is_sve_domain(d) )
+ return -EINVAL;
return switch_mode(d, DOMAIN_32BIT);
case 64:
return switch_mode(d, DOMAIN_64BIT);
diff --git a/xen/arch/arm/arm64/sve.c b/xen/arch/arm/arm64/sve.c
index e05ccc38a896..a9144e48ef6b 100644
--- a/xen/arch/arm/arm64/sve.c
+++ b/xen/arch/arm/arm64/sve.c
@@ -8,6 +8,7 @@
#include <xen/types.h>
#include <asm/arm64/sve.h>
#include <asm/arm64/sysregs.h>
+#include <asm/cpufeature.h>
#include <asm/processor.h>
#include <asm/system.h>
@@ -49,6 +50,17 @@ register_t compute_max_zcr(void)
return vl_to_zcr(hw_vl);
}
+/* Get the system sanitized value for VL in bits */
+unsigned int get_sys_vl_len(void)
+{
+ if ( !cpu_has_sve )
+ return 0;
+
+ /* ZCR_ELx len field is ((len + 1) * 128) = vector bits length */
+ return ((system_cpuinfo.zcr64.bits[0] & ZCR_ELx_LEN_MASK) + 1U) *
+ SVE_VL_MULTIPLE_VAL;
+}
+
/*
* Local variables:
* mode: C
diff --git a/xen/arch/arm/domain.c b/xen/arch/arm/domain.c
index d5ab15db46c4..6c22551b0ed2 100644
--- a/xen/arch/arm/domain.c
+++ b/xen/arch/arm/domain.c
@@ -13,6 +13,7 @@
#include <xen/wait.h>
#include <asm/alternative.h>
+#include <asm/arm64/sve.h>
#include <asm/cpuerrata.h>
#include <asm/cpufeature.h>
#include <asm/current.h>
@@ -555,6 +556,8 @@ int arch_vcpu_create(struct vcpu *v)
v->arch.vmpidr = MPIDR_SMP | vcpuid_to_vaffinity(v->vcpu_id);
v->arch.cptr_el2 = get_default_cptr_flags();
+ if ( is_sve_domain(v->domain) )
+ v->arch.cptr_el2 &= ~HCPTR_CP(8);
v->arch.hcr_el2 = get_default_hcr_flags();
@@ -599,6 +602,7 @@ int arch_sanitise_domain_config(struct xen_domctl_createdomain *config)
unsigned int max_vcpus;
unsigned int flags_required = (XEN_DOMCTL_CDF_hvm | XEN_DOMCTL_CDF_hap);
unsigned int flags_optional = (XEN_DOMCTL_CDF_iommu | XEN_DOMCTL_CDF_vpmu);
+ unsigned int sve_vl_bits = sve_decode_vl(config->arch.sve_vl);
if ( (config->flags & ~flags_optional) != flags_required )
{
@@ -607,6 +611,26 @@ int arch_sanitise_domain_config(struct xen_domctl_createdomain *config)
return -EINVAL;
}
+ /* Check feature flags */
+ if ( sve_vl_bits > 0 )
+ {
+ unsigned int zcr_max_bits = get_sys_vl_len();
+
+ if ( !zcr_max_bits )
+ {
+ dprintk(XENLOG_INFO, "SVE is unsupported on this machine.\n");
+ return -EINVAL;
+ }
+
+ if ( sve_vl_bits > zcr_max_bits )
+ {
+ dprintk(XENLOG_INFO,
+ "Requested SVE vector length (%u) > supported length (%u)\n",
+ sve_vl_bits, zcr_max_bits);
+ return -EINVAL;
+ }
+ }
+
/* The P2M table must always be shared between the CPU and the IOMMU */
if ( config->iommu_opts & XEN_DOMCTL_IOMMU_no_sharept )
{
@@ -749,6 +773,11 @@ int arch_domain_create(struct domain *d,
if ( (rc = domain_vpci_init(d)) != 0 )
goto fail;
+#ifdef CONFIG_ARM64_SVE
+ /* Copy the encoded vector length sve_vl from the domain configuration */
+ d->arch.sve_vl = config->arch.sve_vl;
+#endif
+
return 0;
fail:
diff --git a/xen/arch/arm/domain_build.c b/xen/arch/arm/domain_build.c
index 71f307a572e9..9dd1ed5bce44 100644
--- a/xen/arch/arm/domain_build.c
+++ b/xen/arch/arm/domain_build.c
@@ -26,6 +26,7 @@
#include <asm/platform.h>
#include <asm/psci.h>
#include <asm/setup.h>
+#include <asm/arm64/sve.h>
#include <asm/cpufeature.h>
#include <asm/domain_build.h>
#include <xen/event.h>
@@ -3670,6 +3671,12 @@ static int __init construct_domain(struct domain *d, struct kernel_info *kinfo)
return -EINVAL;
}
+ if ( is_sve_domain(d) && (kinfo->type == DOMAIN_32BIT) )
+ {
+ printk("SVE is not available for 32-bit domain\n");
+ return -EINVAL;
+ }
+
if ( is_64bit_domain(d) )
vcpu_switch_to_aarch64_mode(v);
diff --git a/xen/arch/arm/include/asm/arm64/sve.h b/xen/arch/arm/include/asm/arm64/sve.h
index c0466243c7bc..4b63412727fc 100644
--- a/xen/arch/arm/include/asm/arm64/sve.h
+++ b/xen/arch/arm/include/asm/arm64/sve.h
@@ -8,13 +8,44 @@
#ifndef _ARM_ARM64_SVE_H
#define _ARM_ARM64_SVE_H
+#include <xen/sched.h>
+
#define SVE_VL_MAX_BITS 2048U
/* Vector length must be multiple of 128 */
#define SVE_VL_MULTIPLE_VAL 128U
+static inline unsigned int sve_decode_vl(unsigned int sve_vl)
+{
+ /* SVE vector length is stored as VL/128 in xen_arch_domainconfig */
+ return sve_vl * SVE_VL_MULTIPLE_VAL;
+}
+
register_t compute_max_zcr(void);
+#ifdef CONFIG_ARM64_SVE
+
+static inline bool is_sve_domain(const struct domain *d)
+{
+ return d->arch.sve_vl > 0;
+}
+
+unsigned int get_sys_vl_len(void);
+
+#else /* !CONFIG_ARM64_SVE */
+
+static inline bool is_sve_domain(const struct domain *d)
+{
+ return false;
+}
+
+static inline unsigned int get_sys_vl_len(void)
+{
+ return 0;
+}
+
+#endif /* CONFIG_ARM64_SVE */
+
#endif /* _ARM_ARM64_SVE_H */
/*
diff --git a/xen/arch/arm/include/asm/domain.h b/xen/arch/arm/include/asm/domain.h
index e776ee704b7d..331da0f3bcc3 100644
--- a/xen/arch/arm/include/asm/domain.h
+++ b/xen/arch/arm/include/asm/domain.h
@@ -67,6 +67,11 @@ struct arch_domain
enum domain_type type;
#endif
+#ifdef CONFIG_ARM64_SVE
+ /* max SVE encoded vector length */
+ uint8_t sve_vl;
+#endif
+
/* Virtual MMU */
struct p2m_domain p2m;
diff --git a/xen/include/public/arch-arm.h b/xen/include/public/arch-arm.h
index 1528ced5097a..38311f559581 100644
--- a/xen/include/public/arch-arm.h
+++ b/xen/include/public/arch-arm.h
@@ -300,6 +300,8 @@ DEFINE_XEN_GUEST_HANDLE(vcpu_guest_context_t);
struct xen_arch_domainconfig {
/* IN/OUT */
uint8_t gic_version;
+ /* IN - Contains SVE vector length divided by 128 */
+ uint8_t sve_vl;
/* IN */
uint16_t tee_type;
/* IN */
--
2.34.1
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [PATCH v7 03/12] xen/arm: Expose SVE feature to the guest
2023-05-23 7:43 [PATCH v7 00/12] SVE feature for arm guests Luca Fancellu
2023-05-23 7:43 ` [PATCH v7 01/12] xen/arm: enable SVE extension for Xen Luca Fancellu
2023-05-23 7:43 ` [PATCH v7 02/12] xen/arm: add SVE vector length field to the domain Luca Fancellu
@ 2023-05-23 7:43 ` Luca Fancellu
2023-05-24 9:25 ` Bertrand Marquis
2023-05-23 7:43 ` [PATCH v7 04/12] xen/arm: add SVE exception class handling Luca Fancellu
` (9 subsequent siblings)
12 siblings, 1 reply; 49+ messages in thread
From: Luca Fancellu @ 2023-05-23 7:43 UTC (permalink / raw)
To: xen-devel
Cc: bertrand.marquis, wei.chen, Stefano Stabellini, Julien Grall,
Volodymyr Babchuk, Julien Grall
When a guest is allowed to use SVE, expose the SVE features through
the identification registers.
Signed-off-by: Luca Fancellu <luca.fancellu@arm.com>
Acked-by: Julien Grall <jgrall@amazon.com>
---
Changes from v6:
- code style fix, add A-by Julien
Changes from v5:
- given the move of is_sve_domain() in asm/arm64/sve.h, add the
header to vsysreg.c
- dropping Bertrand's R-by because of the change
Changes from v4:
- no changes
Changes from v3:
- no changes
Changes from v2:
- no changes
Changes from v1:
- No changes
Changes from RFC:
- No changes
---
xen/arch/arm/arm64/vsysreg.c | 41 ++++++++++++++++++++++++++++++++++--
1 file changed, 39 insertions(+), 2 deletions(-)
diff --git a/xen/arch/arm/arm64/vsysreg.c b/xen/arch/arm/arm64/vsysreg.c
index 758750983c11..fe31f7b3827f 100644
--- a/xen/arch/arm/arm64/vsysreg.c
+++ b/xen/arch/arm/arm64/vsysreg.c
@@ -18,6 +18,8 @@
#include <xen/sched.h>
+#include <asm/arm64/cpufeature.h>
+#include <asm/arm64/sve.h>
#include <asm/current.h>
#include <asm/regs.h>
#include <asm/traps.h>
@@ -295,7 +297,28 @@ void do_sysreg(struct cpu_user_regs *regs,
GENERATE_TID3_INFO(MVFR0_EL1, mvfr, 0)
GENERATE_TID3_INFO(MVFR1_EL1, mvfr, 1)
GENERATE_TID3_INFO(MVFR2_EL1, mvfr, 2)
- GENERATE_TID3_INFO(ID_AA64PFR0_EL1, pfr64, 0)
+
+ case HSR_SYSREG_ID_AA64PFR0_EL1:
+ {
+ register_t guest_reg_value = guest_cpuinfo.pfr64.bits[0];
+
+ if ( is_sve_domain(v->domain) )
+ {
+ /* 4 is the SVE field width in id_aa64pfr0_el1 */
+ uint64_t mask = GENMASK(ID_AA64PFR0_SVE_SHIFT + 4 - 1,
+ ID_AA64PFR0_SVE_SHIFT);
+ /* sysval is the sve field on the system */
+ uint64_t sysval = cpuid_feature_extract_unsigned_field_width(
+ system_cpuinfo.pfr64.bits[0],
+ ID_AA64PFR0_SVE_SHIFT, 4);
+ guest_reg_value &= ~mask;
+ guest_reg_value |= (sysval << ID_AA64PFR0_SVE_SHIFT) & mask;
+ }
+
+ return handle_ro_read_val(regs, regidx, hsr.sysreg.read, hsr, 1,
+ guest_reg_value);
+ }
+
GENERATE_TID3_INFO(ID_AA64PFR1_EL1, pfr64, 1)
GENERATE_TID3_INFO(ID_AA64DFR0_EL1, dbg64, 0)
GENERATE_TID3_INFO(ID_AA64DFR1_EL1, dbg64, 1)
@@ -306,7 +329,21 @@ void do_sysreg(struct cpu_user_regs *regs,
GENERATE_TID3_INFO(ID_AA64MMFR2_EL1, mm64, 2)
GENERATE_TID3_INFO(ID_AA64AFR0_EL1, aux64, 0)
GENERATE_TID3_INFO(ID_AA64AFR1_EL1, aux64, 1)
- GENERATE_TID3_INFO(ID_AA64ZFR0_EL1, zfr64, 0)
+
+ case HSR_SYSREG_ID_AA64ZFR0_EL1:
+ {
+ /*
+ * When the guest has the SVE feature enabled, the whole id_aa64zfr0_el1
+ * needs to be exposed.
+ */
+ register_t guest_reg_value = guest_cpuinfo.zfr64.bits[0];
+
+ if ( is_sve_domain(v->domain) )
+ guest_reg_value = system_cpuinfo.zfr64.bits[0];
+
+ return handle_ro_read_val(regs, regidx, hsr.sysreg.read, hsr, 1,
+ guest_reg_value);
+ }
/*
* Those cases are catching all Reserved registers trapped by TID3 which
--
2.34.1
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [PATCH v7 04/12] xen/arm: add SVE exception class handling
2023-05-23 7:43 [PATCH v7 00/12] SVE feature for arm guests Luca Fancellu
` (2 preceding siblings ...)
2023-05-23 7:43 ` [PATCH v7 03/12] xen/arm: Expose SVE feature to the guest Luca Fancellu
@ 2023-05-23 7:43 ` Luca Fancellu
2023-05-23 7:43 ` [PATCH v7 05/12] arm/sve: save/restore SVE context switch Luca Fancellu
` (8 subsequent siblings)
12 siblings, 0 replies; 49+ messages in thread
From: Luca Fancellu @ 2023-05-23 7:43 UTC (permalink / raw)
To: xen-devel
Cc: bertrand.marquis, wei.chen, Stefano Stabellini, Julien Grall,
Volodymyr Babchuk, Julien Grall
SVE has a new exception class with code 0x19, introduce the new code
and handle the exception.
Signed-off-by: Luca Fancellu <luca.fancellu@arm.com>
Reviewed-by: Bertrand Marquis <bertrand.marquis@arm.com>
Reviewed-by: Julien Grall <jgrall@amazon.com>
---
Changes from v6:
- Add R-by Julien
Changes from v5:
- modified error messages (Julien)
- add R-by Bertrand
Changes from v4:
- No changes
Changes from v3:
- No changes
Changes from v2:
- No changes
Changes from v1:
- No changes
Changes from RFC:
- No changes
---
xen/arch/arm/include/asm/processor.h | 1 +
xen/arch/arm/traps.c | 9 +++++++++
2 files changed, 10 insertions(+)
diff --git a/xen/arch/arm/include/asm/processor.h b/xen/arch/arm/include/asm/processor.h
index bc683334125c..7e42ff8811fc 100644
--- a/xen/arch/arm/include/asm/processor.h
+++ b/xen/arch/arm/include/asm/processor.h
@@ -426,6 +426,7 @@
#define HSR_EC_HVC64 0x16
#define HSR_EC_SMC64 0x17
#define HSR_EC_SYSREG 0x18
+#define HSR_EC_SVE 0x19
#endif
#define HSR_EC_INSTR_ABORT_LOWER_EL 0x20
#define HSR_EC_INSTR_ABORT_CURR_EL 0x21
diff --git a/xen/arch/arm/traps.c b/xen/arch/arm/traps.c
index 3393e10b52e6..f6437f6aa9c9 100644
--- a/xen/arch/arm/traps.c
+++ b/xen/arch/arm/traps.c
@@ -2172,6 +2172,11 @@ void do_trap_guest_sync(struct cpu_user_regs *regs)
perfc_incr(trap_sysreg);
do_sysreg(regs, hsr);
break;
+ case HSR_EC_SVE:
+ GUEST_BUG_ON(regs_mode_is_32bit(regs));
+ gprintk(XENLOG_WARNING, "Domain tried to use SVE while not allowed\n");
+ inject_undef_exception(regs, hsr);
+ break;
#endif
case HSR_EC_INSTR_ABORT_LOWER_EL:
@@ -2201,6 +2206,10 @@ void do_trap_hyp_sync(struct cpu_user_regs *regs)
case HSR_EC_BRK:
do_trap_brk(regs, hsr);
break;
+ case HSR_EC_SVE:
+ /* An SVE exception is a bug somewhere in hypervisor code */
+ do_unexpected_trap("SVE trap at EL2", regs);
+ break;
#endif
case HSR_EC_DATA_ABORT_CURR_EL:
case HSR_EC_INSTR_ABORT_CURR_EL:
--
2.34.1
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [PATCH v7 05/12] arm/sve: save/restore SVE context switch
2023-05-23 7:43 [PATCH v7 00/12] SVE feature for arm guests Luca Fancellu
` (3 preceding siblings ...)
2023-05-23 7:43 ` [PATCH v7 04/12] xen/arm: add SVE exception class handling Luca Fancellu
@ 2023-05-23 7:43 ` Luca Fancellu
2023-05-24 9:47 ` Bertrand Marquis
2023-05-25 9:09 ` Julien Grall
2023-05-23 7:43 ` [PATCH v7 06/12] xen/common: add dom0 xen command line argument for Arm Luca Fancellu
` (7 subsequent siblings)
12 siblings, 2 replies; 49+ messages in thread
From: Luca Fancellu @ 2023-05-23 7:43 UTC (permalink / raw)
To: xen-devel
Cc: bertrand.marquis, wei.chen, Stefano Stabellini, Julien Grall,
Volodymyr Babchuk
Save/restore context switch for SVE, allocate memory to contain
the Z0-31 registers whose length is maximum 2048 bits each and
FFR who can be maximum 256 bits, the allocated memory depends on
how many bits is the vector length for the domain and how many bits
are supported by the platform.
Save P0-15 whose length is maximum 256 bits each, in this case the
memory used is from the fpregs field in struct vfp_state,
because V0-31 are part of Z0-31 and this space would have been
unused for SVE domain otherwise.
Create zcr_el{1,2} fields in arch_vcpu, initialise zcr_el2 on vcpu
creation given the requested vector length and restore it on
context switch, save/restore ZCR_EL1 value as well.
List import macros from Linux in README.LinuxPrimitives.
Signed-off-by: Luca Fancellu <luca.fancellu@arm.com>
---
Changes from v6:
- Add comment for explain why sve_save/sve_load are different from
Linux, add macros in xen/arch/arm/README.LinuxPrimitives (Julien)
- Add comments in sve_context_init and sve_context_free, handle the
case where sve_zreg_ctx_end is NULL, move setting of v->arch.zcr_el2
in sve_context_init (Julien)
- remove stubs for sve_context_* and sve_save_* and rely on compiler
DCE (Jan)
- Add comments for sve_save_ctx/sve_load_ctx (Julien)
Changes from v5:
- use XFREE instead of xfree, keep the headers (Julien)
- Avoid math computation for every save/restore, store the computation
in struct vfp_state once (Bertrand)
- protect access to v->domain->arch.sve_vl inside arch_vcpu_create now
that sve_vl is available only on arm64
Changes from v4:
- No changes
Changes from v3:
- don't use fixed len types when not needed (Jan)
- now VL is an encoded value, decode it before using.
Changes from v2:
- No changes
Changes from v1:
- No changes
Changes from RFC:
- Moved zcr_el2 field introduction in this patch, restore its
content inside sve_restore_state function. (Julien)
fix patch 5
Signed-off-by: Luca Fancellu <luca.fancellu@arm.com>
Change-Id: Ief65b2ff14fd579afa4fd110ce08a19980e64fa9
---
xen/arch/arm/README.LinuxPrimitives | 4 +-
xen/arch/arm/arm64/sve-asm.S | 147 +++++++++++++++++++++++
xen/arch/arm/arm64/sve.c | 91 ++++++++++++++
xen/arch/arm/arm64/vfp.c | 79 ++++++------
xen/arch/arm/domain.c | 6 +
xen/arch/arm/include/asm/arm64/sve.h | 4 +
xen/arch/arm/include/asm/arm64/sysregs.h | 3 +
xen/arch/arm/include/asm/arm64/vfp.h | 12 ++
xen/arch/arm/include/asm/domain.h | 2 +
9 files changed, 313 insertions(+), 35 deletions(-)
diff --git a/xen/arch/arm/README.LinuxPrimitives b/xen/arch/arm/README.LinuxPrimitives
index 76c8df29e416..301c0271bbe4 100644
--- a/xen/arch/arm/README.LinuxPrimitives
+++ b/xen/arch/arm/README.LinuxPrimitives
@@ -69,7 +69,9 @@ SVE assembly macro: last sync @ v6.3.0 (last commit: 457391b03803)
linux/arch/arm64/include/asm/fpsimdmacros.h xen/arch/arm/include/asm/arm64/sve-asm.S
The following macros were taken from Linux:
- _check_general_reg, _check_num, _sve_rdvl
+ _check_general_reg, _check_num, _sve_rdvl, __for, _for, _sve_check_zreg,
+ _sve_check_preg, _sve_str_v, _sve_ldr_v, _sve_str_p, _sve_ldr_p, _sve_rdffr,
+ _sve_wrffr
=====================================================================
arm32
diff --git a/xen/arch/arm/arm64/sve-asm.S b/xen/arch/arm/arm64/sve-asm.S
index 4d1549344733..59dbefbbb252 100644
--- a/xen/arch/arm/arm64/sve-asm.S
+++ b/xen/arch/arm/arm64/sve-asm.S
@@ -17,6 +17,18 @@
.endif
.endm
+.macro _sve_check_zreg znr
+ .if (\znr) < 0 || (\znr) > 31
+ .error "Bad Scalable Vector Extension vector register number \znr."
+ .endif
+.endm
+
+.macro _sve_check_preg pnr
+ .if (\pnr) < 0 || (\pnr) > 15
+ .error "Bad Scalable Vector Extension predicate register number \pnr."
+ .endif
+.endm
+
.macro _check_num n, min, max
.if (\n) < (\min) || (\n) > (\max)
.error "Number \n out of range [\min,\max]"
@@ -26,6 +38,54 @@
/* SVE instruction encodings for non-SVE-capable assemblers */
/* (pre binutils 2.28, all kernel capable clang versions support SVE) */
+/* STR (vector): STR Z\nz, [X\nxbase, #\offset, MUL VL] */
+.macro _sve_str_v nz, nxbase, offset=0
+ _sve_check_zreg \nz
+ _check_general_reg \nxbase
+ _check_num (\offset), -0x100, 0xff
+ .inst 0xe5804000 \
+ | (\nz) \
+ | ((\nxbase) << 5) \
+ | (((\offset) & 7) << 10) \
+ | (((\offset) & 0x1f8) << 13)
+.endm
+
+/* LDR (vector): LDR Z\nz, [X\nxbase, #\offset, MUL VL] */
+.macro _sve_ldr_v nz, nxbase, offset=0
+ _sve_check_zreg \nz
+ _check_general_reg \nxbase
+ _check_num (\offset), -0x100, 0xff
+ .inst 0x85804000 \
+ | (\nz) \
+ | ((\nxbase) << 5) \
+ | (((\offset) & 7) << 10) \
+ | (((\offset) & 0x1f8) << 13)
+.endm
+
+/* STR (predicate): STR P\np, [X\nxbase, #\offset, MUL VL] */
+.macro _sve_str_p np, nxbase, offset=0
+ _sve_check_preg \np
+ _check_general_reg \nxbase
+ _check_num (\offset), -0x100, 0xff
+ .inst 0xe5800000 \
+ | (\np) \
+ | ((\nxbase) << 5) \
+ | (((\offset) & 7) << 10) \
+ | (((\offset) & 0x1f8) << 13)
+.endm
+
+/* LDR (predicate): LDR P\np, [X\nxbase, #\offset, MUL VL] */
+.macro _sve_ldr_p np, nxbase, offset=0
+ _sve_check_preg \np
+ _check_general_reg \nxbase
+ _check_num (\offset), -0x100, 0xff
+ .inst 0x85800000 \
+ | (\np) \
+ | ((\nxbase) << 5) \
+ | (((\offset) & 7) << 10) \
+ | (((\offset) & 0x1f8) << 13)
+.endm
+
/* RDVL X\nx, #\imm */
.macro _sve_rdvl nx, imm
_check_general_reg \nx
@@ -35,11 +95,98 @@
| (((\imm) & 0x3f) << 5)
.endm
+/* RDFFR (unpredicated): RDFFR P\np.B */
+.macro _sve_rdffr np
+ _sve_check_preg \np
+ .inst 0x2519f000 \
+ | (\np)
+.endm
+
+/* WRFFR P\np.B */
+.macro _sve_wrffr np
+ _sve_check_preg \np
+ .inst 0x25289000 \
+ | ((\np) << 5)
+.endm
+
+.macro __for from:req, to:req
+ .if (\from) == (\to)
+ _for__body %\from
+ .else
+ __for %\from, %((\from) + ((\to) - (\from)) / 2)
+ __for %((\from) + ((\to) - (\from)) / 2 + 1), %\to
+ .endif
+.endm
+
+.macro _for var:req, from:req, to:req, insn:vararg
+ .macro _for__body \var:req
+ .noaltmacro
+ \insn
+ .altmacro
+ .endm
+
+ .altmacro
+ __for \from, \to
+ .noaltmacro
+
+ .purgem _for__body
+.endm
+
+/*
+ * sve_save and sve_load are different from the Linux version because the
+ * buffers to save the context are different from Xen and for example Linux
+ * is using this macro to save/restore also fpsr and fpcr while we do it in C
+ */
+
+.macro sve_save nxzffrctx, nxpctx, save_ffr
+ _for n, 0, 31, _sve_str_v \n, \nxzffrctx, \n - 32
+ _for n, 0, 15, _sve_str_p \n, \nxpctx, \n
+ cbz \save_ffr, 1f
+ _sve_rdffr 0
+ _sve_str_p 0, \nxzffrctx
+ _sve_ldr_p 0, \nxpctx
+ b 2f
+1:
+ str xzr, [x\nxzffrctx] // Zero out FFR
+2:
+.endm
+
+.macro sve_load nxzffrctx, nxpctx, restore_ffr
+ _for n, 0, 31, _sve_ldr_v \n, \nxzffrctx, \n - 32
+ cbz \restore_ffr, 1f
+ _sve_ldr_p 0, \nxzffrctx
+ _sve_wrffr 0
+1:
+ _for n, 0, 15, _sve_ldr_p \n, \nxpctx, \n
+.endm
+
/* Gets the current vector register size in bytes */
GLOBAL(sve_get_hw_vl)
_sve_rdvl 0, 1
ret
+/*
+ * Save the SVE context
+ *
+ * x0 - pointer to buffer for Z0-31 + FFR
+ * x1 - pointer to buffer for P0-15
+ * x2 - Save FFR if non-zero
+ */
+GLOBAL(sve_save_ctx)
+ sve_save 0, 1, x2
+ ret
+
+/*
+ * Load the SVE context
+ *
+ * x0 - pointer to buffer for Z0-31 + FFR
+ * x1 - pointer to buffer for P0-15
+ * x2 - Restore FFR if non-zero
+ */
+GLOBAL(sve_load_ctx)
+ sve_load 0, 1, x2
+ ret
+
/*
* Local variables:
* mode: ASM
diff --git a/xen/arch/arm/arm64/sve.c b/xen/arch/arm/arm64/sve.c
index a9144e48ef6b..84a6dedc1fd7 100644
--- a/xen/arch/arm/arm64/sve.c
+++ b/xen/arch/arm/arm64/sve.c
@@ -5,6 +5,7 @@
* Copyright (C) 2022 ARM Ltd.
*/
+#include <xen/sizes.h>
#include <xen/types.h>
#include <asm/arm64/sve.h>
#include <asm/arm64/sysregs.h>
@@ -14,6 +15,25 @@
extern unsigned int sve_get_hw_vl(void);
+/*
+ * Save the SVE context
+ *
+ * sve_ctx - pointer to buffer for Z0-31 + FFR
+ * pregs - pointer to buffer for P0-15
+ * save_ffr - Save FFR if non-zero
+ */
+extern void sve_save_ctx(uint64_t *sve_ctx, uint64_t *pregs, int save_ffr);
+
+/*
+ * Load the SVE context
+ *
+ * sve_ctx - pointer to buffer for Z0-31 + FFR
+ * pregs - pointer to buffer for P0-15
+ * restore_ffr - Restore FFR if non-zero
+ */
+extern void sve_load_ctx(uint64_t const *sve_ctx, uint64_t const *pregs,
+ int restore_ffr);
+
/* Takes a vector length in bits and returns the ZCR_ELx encoding */
static inline register_t vl_to_zcr(unsigned int vl)
{
@@ -21,6 +41,21 @@ static inline register_t vl_to_zcr(unsigned int vl)
return ((vl / SVE_VL_MULTIPLE_VAL) - 1U) & ZCR_ELx_LEN_MASK;
}
+static inline unsigned int sve_zreg_ctx_size(unsigned int vl)
+{
+ /*
+ * Z0-31 registers size in bytes is computed from VL that is in bits, so VL
+ * in bytes is VL/8.
+ */
+ return (vl / 8U) * 32U;
+}
+
+static inline unsigned int sve_ffrreg_ctx_size(unsigned int vl)
+{
+ /* FFR register size is VL/8, which is in bytes (VL/8)/8 */
+ return (vl / 64U);
+}
+
register_t compute_max_zcr(void)
{
register_t cptr_bits = get_default_cptr_flags();
@@ -61,6 +96,62 @@ unsigned int get_sys_vl_len(void)
SVE_VL_MULTIPLE_VAL;
}
+int sve_context_init(struct vcpu *v)
+{
+ unsigned int sve_vl_bits = sve_decode_vl(v->domain->arch.sve_vl);
+ uint64_t *ctx = _xzalloc(sve_zreg_ctx_size(sve_vl_bits) +
+ sve_ffrreg_ctx_size(sve_vl_bits),
+ L1_CACHE_BYTES);
+
+ if ( !ctx )
+ return -ENOMEM;
+
+ /*
+ * Point to the end of Z0-Z31 memory, just before FFR memory, to be kept in
+ * sync with sve_context_free()
+ */
+ v->arch.vfp.sve_zreg_ctx_end = ctx +
+ (sve_zreg_ctx_size(sve_vl_bits) / sizeof(uint64_t));
+
+ v->arch.zcr_el2 = vl_to_zcr(sve_vl_bits);
+
+ return 0;
+}
+
+void sve_context_free(struct vcpu *v)
+{
+ unsigned int sve_vl_bits;
+
+ if ( v->arch.vfp.sve_zreg_ctx_end )
+ return;
+
+ sve_vl_bits = sve_decode_vl(v->domain->arch.sve_vl);
+
+ /*
+ * Point to the end of Z0-Z31 memory, just before FFR memory, to be kept
+ * in sync with sve_context_init()
+ */
+ v->arch.vfp.sve_zreg_ctx_end -=
+ (sve_zreg_ctx_size(sve_vl_bits) / sizeof(uint64_t));
+
+ XFREE(v->arch.vfp.sve_zreg_ctx_end);
+}
+
+void sve_save_state(struct vcpu *v)
+{
+ v->arch.zcr_el1 = READ_SYSREG(ZCR_EL1);
+
+ sve_save_ctx(v->arch.vfp.sve_zreg_ctx_end, v->arch.vfp.fpregs, 1);
+}
+
+void sve_restore_state(struct vcpu *v)
+{
+ WRITE_SYSREG(v->arch.zcr_el1, ZCR_EL1);
+ WRITE_SYSREG(v->arch.zcr_el2, ZCR_EL2);
+
+ sve_load_ctx(v->arch.vfp.sve_zreg_ctx_end, v->arch.vfp.fpregs, 1);
+}
+
/*
* Local variables:
* mode: C
diff --git a/xen/arch/arm/arm64/vfp.c b/xen/arch/arm/arm64/vfp.c
index 47885e76baae..2d0d7c2e6ddb 100644
--- a/xen/arch/arm/arm64/vfp.c
+++ b/xen/arch/arm/arm64/vfp.c
@@ -2,29 +2,35 @@
#include <asm/processor.h>
#include <asm/cpufeature.h>
#include <asm/vfp.h>
+#include <asm/arm64/sve.h>
void vfp_save_state(struct vcpu *v)
{
if ( !cpu_has_fp )
return;
- asm volatile("stp q0, q1, [%1, #16 * 0]\n\t"
- "stp q2, q3, [%1, #16 * 2]\n\t"
- "stp q4, q5, [%1, #16 * 4]\n\t"
- "stp q6, q7, [%1, #16 * 6]\n\t"
- "stp q8, q9, [%1, #16 * 8]\n\t"
- "stp q10, q11, [%1, #16 * 10]\n\t"
- "stp q12, q13, [%1, #16 * 12]\n\t"
- "stp q14, q15, [%1, #16 * 14]\n\t"
- "stp q16, q17, [%1, #16 * 16]\n\t"
- "stp q18, q19, [%1, #16 * 18]\n\t"
- "stp q20, q21, [%1, #16 * 20]\n\t"
- "stp q22, q23, [%1, #16 * 22]\n\t"
- "stp q24, q25, [%1, #16 * 24]\n\t"
- "stp q26, q27, [%1, #16 * 26]\n\t"
- "stp q28, q29, [%1, #16 * 28]\n\t"
- "stp q30, q31, [%1, #16 * 30]\n\t"
- : "=Q" (*v->arch.vfp.fpregs) : "r" (v->arch.vfp.fpregs));
+ if ( is_sve_domain(v->domain) )
+ sve_save_state(v);
+ else
+ {
+ asm volatile("stp q0, q1, [%1, #16 * 0]\n\t"
+ "stp q2, q3, [%1, #16 * 2]\n\t"
+ "stp q4, q5, [%1, #16 * 4]\n\t"
+ "stp q6, q7, [%1, #16 * 6]\n\t"
+ "stp q8, q9, [%1, #16 * 8]\n\t"
+ "stp q10, q11, [%1, #16 * 10]\n\t"
+ "stp q12, q13, [%1, #16 * 12]\n\t"
+ "stp q14, q15, [%1, #16 * 14]\n\t"
+ "stp q16, q17, [%1, #16 * 16]\n\t"
+ "stp q18, q19, [%1, #16 * 18]\n\t"
+ "stp q20, q21, [%1, #16 * 20]\n\t"
+ "stp q22, q23, [%1, #16 * 22]\n\t"
+ "stp q24, q25, [%1, #16 * 24]\n\t"
+ "stp q26, q27, [%1, #16 * 26]\n\t"
+ "stp q28, q29, [%1, #16 * 28]\n\t"
+ "stp q30, q31, [%1, #16 * 30]\n\t"
+ : "=Q" (*v->arch.vfp.fpregs) : "r" (v->arch.vfp.fpregs));
+ }
v->arch.vfp.fpsr = READ_SYSREG(FPSR);
v->arch.vfp.fpcr = READ_SYSREG(FPCR);
@@ -37,23 +43,28 @@ void vfp_restore_state(struct vcpu *v)
if ( !cpu_has_fp )
return;
- asm volatile("ldp q0, q1, [%1, #16 * 0]\n\t"
- "ldp q2, q3, [%1, #16 * 2]\n\t"
- "ldp q4, q5, [%1, #16 * 4]\n\t"
- "ldp q6, q7, [%1, #16 * 6]\n\t"
- "ldp q8, q9, [%1, #16 * 8]\n\t"
- "ldp q10, q11, [%1, #16 * 10]\n\t"
- "ldp q12, q13, [%1, #16 * 12]\n\t"
- "ldp q14, q15, [%1, #16 * 14]\n\t"
- "ldp q16, q17, [%1, #16 * 16]\n\t"
- "ldp q18, q19, [%1, #16 * 18]\n\t"
- "ldp q20, q21, [%1, #16 * 20]\n\t"
- "ldp q22, q23, [%1, #16 * 22]\n\t"
- "ldp q24, q25, [%1, #16 * 24]\n\t"
- "ldp q26, q27, [%1, #16 * 26]\n\t"
- "ldp q28, q29, [%1, #16 * 28]\n\t"
- "ldp q30, q31, [%1, #16 * 30]\n\t"
- : : "Q" (*v->arch.vfp.fpregs), "r" (v->arch.vfp.fpregs));
+ if ( is_sve_domain(v->domain) )
+ sve_restore_state(v);
+ else
+ {
+ asm volatile("ldp q0, q1, [%1, #16 * 0]\n\t"
+ "ldp q2, q3, [%1, #16 * 2]\n\t"
+ "ldp q4, q5, [%1, #16 * 4]\n\t"
+ "ldp q6, q7, [%1, #16 * 6]\n\t"
+ "ldp q8, q9, [%1, #16 * 8]\n\t"
+ "ldp q10, q11, [%1, #16 * 10]\n\t"
+ "ldp q12, q13, [%1, #16 * 12]\n\t"
+ "ldp q14, q15, [%1, #16 * 14]\n\t"
+ "ldp q16, q17, [%1, #16 * 16]\n\t"
+ "ldp q18, q19, [%1, #16 * 18]\n\t"
+ "ldp q20, q21, [%1, #16 * 20]\n\t"
+ "ldp q22, q23, [%1, #16 * 22]\n\t"
+ "ldp q24, q25, [%1, #16 * 24]\n\t"
+ "ldp q26, q27, [%1, #16 * 26]\n\t"
+ "ldp q28, q29, [%1, #16 * 28]\n\t"
+ "ldp q30, q31, [%1, #16 * 30]\n\t"
+ : : "Q" (*v->arch.vfp.fpregs), "r" (v->arch.vfp.fpregs));
+ }
WRITE_SYSREG(v->arch.vfp.fpsr, FPSR);
WRITE_SYSREG(v->arch.vfp.fpcr, FPCR);
diff --git a/xen/arch/arm/domain.c b/xen/arch/arm/domain.c
index 6c22551b0ed2..add9929b7943 100644
--- a/xen/arch/arm/domain.c
+++ b/xen/arch/arm/domain.c
@@ -557,7 +557,11 @@ int arch_vcpu_create(struct vcpu *v)
v->arch.cptr_el2 = get_default_cptr_flags();
if ( is_sve_domain(v->domain) )
+ {
+ if ( (rc = sve_context_init(v)) != 0 )
+ goto fail;
v->arch.cptr_el2 &= ~HCPTR_CP(8);
+ }
v->arch.hcr_el2 = get_default_hcr_flags();
@@ -587,6 +591,8 @@ fail:
void arch_vcpu_destroy(struct vcpu *v)
{
+ if ( is_sve_domain(v->domain) )
+ sve_context_free(v);
vcpu_timer_destroy(v);
vcpu_vgic_free(v);
free_xenheap_pages(v->arch.stack, STACK_ORDER);
diff --git a/xen/arch/arm/include/asm/arm64/sve.h b/xen/arch/arm/include/asm/arm64/sve.h
index 4b63412727fc..65b46685d263 100644
--- a/xen/arch/arm/include/asm/arm64/sve.h
+++ b/xen/arch/arm/include/asm/arm64/sve.h
@@ -22,6 +22,10 @@ static inline unsigned int sve_decode_vl(unsigned int sve_vl)
}
register_t compute_max_zcr(void);
+int sve_context_init(struct vcpu *v);
+void sve_context_free(struct vcpu *v);
+void sve_save_state(struct vcpu *v);
+void sve_restore_state(struct vcpu *v);
#ifdef CONFIG_ARM64_SVE
diff --git a/xen/arch/arm/include/asm/arm64/sysregs.h b/xen/arch/arm/include/asm/arm64/sysregs.h
index 4cabb9eb4d5e..3fdeb9d8cdef 100644
--- a/xen/arch/arm/include/asm/arm64/sysregs.h
+++ b/xen/arch/arm/include/asm/arm64/sysregs.h
@@ -88,6 +88,9 @@
#ifndef ID_AA64ISAR2_EL1
#define ID_AA64ISAR2_EL1 S3_0_C0_C6_2
#endif
+#ifndef ZCR_EL1
+#define ZCR_EL1 S3_0_C1_C2_0
+#endif
/* ID registers (imported from arm64/include/asm/sysreg.h in Linux) */
diff --git a/xen/arch/arm/include/asm/arm64/vfp.h b/xen/arch/arm/include/asm/arm64/vfp.h
index e6e8c363bc16..4aa371e85d26 100644
--- a/xen/arch/arm/include/asm/arm64/vfp.h
+++ b/xen/arch/arm/include/asm/arm64/vfp.h
@@ -6,7 +6,19 @@
struct vfp_state
{
+ /*
+ * When SVE is enabled for the guest, fpregs memory will be used to
+ * save/restore P0-P15 registers, otherwise it will be used for the V0-V31
+ * registers.
+ */
uint64_t fpregs[64] __vfp_aligned;
+ /*
+ * When SVE is enabled for the guest, sve_zreg_ctx_end points to memory
+ * where Z0-Z31 registers and FFR can be saved/restored, it points at the
+ * end of the Z0-Z31 space and at the beginning of the FFR space, it's done
+ * like that to ease the save/restore assembly operations.
+ */
+ uint64_t *sve_zreg_ctx_end;
register_t fpcr;
register_t fpexc32_el2;
register_t fpsr;
diff --git a/xen/arch/arm/include/asm/domain.h b/xen/arch/arm/include/asm/domain.h
index 331da0f3bcc3..814652d92568 100644
--- a/xen/arch/arm/include/asm/domain.h
+++ b/xen/arch/arm/include/asm/domain.h
@@ -195,6 +195,8 @@ struct arch_vcpu
register_t tpidrro_el0;
/* HYP configuration */
+ register_t zcr_el1;
+ register_t zcr_el2;
register_t cptr_el2;
register_t hcr_el2;
register_t mdcr_el2;
--
2.34.1
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [PATCH v7 06/12] xen/common: add dom0 xen command line argument for Arm
2023-05-23 7:43 [PATCH v7 00/12] SVE feature for arm guests Luca Fancellu
` (4 preceding siblings ...)
2023-05-23 7:43 ` [PATCH v7 05/12] arm/sve: save/restore SVE context switch Luca Fancellu
@ 2023-05-23 7:43 ` Luca Fancellu
2023-05-23 7:43 ` [PATCH v7 07/12] xen: enable Dom0 to use SVE feature Luca Fancellu
` (6 subsequent siblings)
12 siblings, 0 replies; 49+ messages in thread
From: Luca Fancellu @ 2023-05-23 7:43 UTC (permalink / raw)
To: xen-devel
Cc: bertrand.marquis, wei.chen, Stefano Stabellini, Julien Grall,
Volodymyr Babchuk, Andrew Cooper, George Dunlap, Jan Beulich,
Wei Liu, Roger Pau Monné
Currently x86 defines a Xen command line argument dom0=<list> where
there can be specified dom0 controlling sub-options, to use it also
on Arm, move the code that loops through the list of arguments from
x86 to the common code and from there, call architecture specific
functions to handle the comma separated sub-options.
No functional changes are intended.
Signed-off-by: Luca Fancellu <luca.fancellu@arm.com>
Reviewed-by: Jan Beulich <jbeulich@suse.com>
Reviewed-by: Bertrand Marquis <bertrand.marquis@arm.com>
---
Changes from v6:
- no changes
Changes from v5:
- Add Bertrand R-by
Changes from v4:
- return EINVAL in Arm implementation of parse_arch_dom0_param,
shorten variable name in the funtion from str_begin, str_end to
s, e. Removed variable rc from x86 parse_arch_dom0_param
implementation. (Jan)
- Add R-By Jan
Changes from v3:
- new patch
---
xen/arch/arm/domain_build.c | 5 ++++
xen/arch/x86/dom0_build.c | 48 ++++++++++++++-----------------------
xen/common/domain.c | 23 ++++++++++++++++++
xen/include/xen/domain.h | 1 +
4 files changed, 47 insertions(+), 30 deletions(-)
diff --git a/xen/arch/arm/domain_build.c b/xen/arch/arm/domain_build.c
index 9dd1ed5bce44..f373a5024783 100644
--- a/xen/arch/arm/domain_build.c
+++ b/xen/arch/arm/domain_build.c
@@ -60,6 +60,11 @@ static int __init parse_dom0_mem(const char *s)
}
custom_param("dom0_mem", parse_dom0_mem);
+int __init parse_arch_dom0_param(const char *s, const char *e)
+{
+ return -EINVAL;
+}
+
/* Override macros from asm/page.h to make them work with mfn_t */
#undef virt_to_mfn
#define virt_to_mfn(va) _mfn(__virt_to_mfn(va))
diff --git a/xen/arch/x86/dom0_build.c b/xen/arch/x86/dom0_build.c
index 79234f18ff01..9f5300a3efbb 100644
--- a/xen/arch/x86/dom0_build.c
+++ b/xen/arch/x86/dom0_build.c
@@ -266,42 +266,30 @@ bool __initdata opt_dom0_pvh = !IS_ENABLED(CONFIG_PV);
bool __initdata opt_dom0_verbose = IS_ENABLED(CONFIG_VERBOSE_DEBUG);
bool __initdata opt_dom0_msr_relaxed;
-static int __init cf_check parse_dom0_param(const char *s)
+int __init parse_arch_dom0_param(const char *s, const char *e)
{
- const char *ss;
- int rc = 0;
+ int val;
- do {
- int val;
-
- ss = strchr(s, ',');
- if ( !ss )
- ss = strchr(s, '\0');
-
- if ( IS_ENABLED(CONFIG_PV) && !cmdline_strcmp(s, "pv") )
- opt_dom0_pvh = false;
- else if ( IS_ENABLED(CONFIG_HVM) && !cmdline_strcmp(s, "pvh") )
- opt_dom0_pvh = true;
+ if ( IS_ENABLED(CONFIG_PV) && !cmdline_strcmp(s, "pv") )
+ opt_dom0_pvh = false;
+ else if ( IS_ENABLED(CONFIG_HVM) && !cmdline_strcmp(s, "pvh") )
+ opt_dom0_pvh = true;
#ifdef CONFIG_SHADOW_PAGING
- else if ( (val = parse_boolean("shadow", s, ss)) >= 0 )
- opt_dom0_shadow = val;
+ else if ( (val = parse_boolean("shadow", s, e)) >= 0 )
+ opt_dom0_shadow = val;
#endif
- else if ( (val = parse_boolean("verbose", s, ss)) >= 0 )
- opt_dom0_verbose = val;
- else if ( IS_ENABLED(CONFIG_PV) &&
- (val = parse_boolean("cpuid-faulting", s, ss)) >= 0 )
- opt_dom0_cpuid_faulting = val;
- else if ( (val = parse_boolean("msr-relaxed", s, ss)) >= 0 )
- opt_dom0_msr_relaxed = val;
- else
- rc = -EINVAL;
-
- s = ss + 1;
- } while ( *ss );
+ else if ( (val = parse_boolean("verbose", s, e)) >= 0 )
+ opt_dom0_verbose = val;
+ else if ( IS_ENABLED(CONFIG_PV) &&
+ (val = parse_boolean("cpuid-faulting", s, e)) >= 0 )
+ opt_dom0_cpuid_faulting = val;
+ else if ( (val = parse_boolean("msr-relaxed", s, e)) >= 0 )
+ opt_dom0_msr_relaxed = val;
+ else
+ return -EINVAL;
- return rc;
+ return 0;
}
-custom_param("dom0", parse_dom0_param);
static char __initdata opt_dom0_ioports_disable[200] = "";
string_param("dom0_ioports_disable", opt_dom0_ioports_disable);
diff --git a/xen/common/domain.c b/xen/common/domain.c
index 6a440590fe2a..caaa40263792 100644
--- a/xen/common/domain.c
+++ b/xen/common/domain.c
@@ -364,6 +364,29 @@ static int __init cf_check parse_extra_guest_irqs(const char *s)
}
custom_param("extra_guest_irqs", parse_extra_guest_irqs);
+static int __init cf_check parse_dom0_param(const char *s)
+{
+ const char *ss;
+ int rc = 0;
+
+ do {
+ int ret;
+
+ ss = strchr(s, ',');
+ if ( !ss )
+ ss = strchr(s, '\0');
+
+ ret = parse_arch_dom0_param(s, ss);
+ if ( ret && !rc )
+ rc = ret;
+
+ s = ss + 1;
+ } while ( *ss );
+
+ return rc;
+}
+custom_param("dom0", parse_dom0_param);
+
/*
* Release resources held by a domain. There may or may not be live
* references to the domain, and it may or may not be fully constructed.
diff --git a/xen/include/xen/domain.h b/xen/include/xen/domain.h
index 26f9c4f6dd5b..1df8f933d076 100644
--- a/xen/include/xen/domain.h
+++ b/xen/include/xen/domain.h
@@ -16,6 +16,7 @@ typedef union {
struct vcpu *vcpu_create(struct domain *d, unsigned int vcpu_id);
unsigned int dom0_max_vcpus(void);
+int parse_arch_dom0_param(const char *s, const char *e);
struct vcpu *alloc_dom0_vcpu0(struct domain *dom0);
int vcpu_reset(struct vcpu *);
--
2.34.1
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [PATCH v7 07/12] xen: enable Dom0 to use SVE feature
2023-05-23 7:43 [PATCH v7 00/12] SVE feature for arm guests Luca Fancellu
` (5 preceding siblings ...)
2023-05-23 7:43 ` [PATCH v7 06/12] xen/common: add dom0 xen command line argument for Arm Luca Fancellu
@ 2023-05-23 7:43 ` Luca Fancellu
2023-05-23 10:02 ` Jan Beulich
2023-05-24 10:05 ` Bertrand Marquis
2023-05-23 7:43 ` [PATCH v7 08/12] xen/physinfo: encode Arm SVE vector length in arch_capabilities Luca Fancellu
` (5 subsequent siblings)
12 siblings, 2 replies; 49+ messages in thread
From: Luca Fancellu @ 2023-05-23 7:43 UTC (permalink / raw)
To: xen-devel
Cc: bertrand.marquis, wei.chen, Andrew Cooper, George Dunlap,
Jan Beulich, Julien Grall, Stefano Stabellini, Wei Liu,
Volodymyr Babchuk
Add a command line parameter to allow Dom0 the use of SVE resources,
the command line parameter sve=<integer>, sub argument of dom0=,
controls the feature on this domain and sets the maximum SVE vector
length for Dom0.
Add a new function, parse_signed_integer(), to parse an integer
command line argument.
Signed-off-by: Luca Fancellu <luca.fancellu@arm.com>
---
Changes from v6:
- Fixed case for e==NULL in parse_signed_integer, drop parenthesis
from if conditions, delete inline sve_domctl_vl_param and rely on
DCE from the compiler (Jan)
- Drop parenthesis from opt_dom0_sve (Julien)
- Do not continue if 'sve' is in command line args but
CONFIG_ARM64_SVE is not selected:
https://lore.kernel.org/all/7614AE25-F59D-430A-9C3E-30B1CE0E1580@arm.com/
Changes from v5:
- stop the domain if VL error occurs (Julien, Bertrand)
- update the documentation
- Rename sve_sanitize_vl_param to sve_domctl_vl_param to
mark the fact that we are sanitizing a parameter coming from
the user before encoding it into sve_vl in domctl structure.
(suggestion from Bertrand in a separate discussion)
- update comment in parse_signed_integer, return boolean in
sve_domctl_vl_param (Jan).
Changes from v4:
- Negative values as user param means max supported HW VL (Jan)
- update documentation, make use of no_config_param(), rename
parse_integer into parse_signed_integer and take long long *,
also put a comment on the -2 return condition, update
declaration comment to reflect the modifications (Jan)
Changes from v3:
- Don't use fixed len types when not needed (Jan)
- renamed domainconfig_encode_vl to sve_encode_vl
- Use a sub argument of dom0= to enable the feature (Jan)
- Add parse_integer() function
Changes from v2:
- xen_domctl_createdomain field has changed into sve_vl and its
value now is the VL / 128, create an helper function for that.
Changes from v1:
- No changes
Changes from RFC:
- Changed docs to explain that the domain won't be created if the
requested vector length is above the supported one from the
platform.
---
docs/misc/xen-command-line.pandoc | 20 ++++++++++++++++++--
xen/arch/arm/arm64/sve.c | 20 ++++++++++++++++++++
xen/arch/arm/domain_build.c | 26 ++++++++++++++++++++++++++
xen/arch/arm/include/asm/arm64/sve.h | 10 ++++++++++
xen/common/kernel.c | 28 ++++++++++++++++++++++++++++
xen/include/xen/lib.h | 10 ++++++++++
6 files changed, 112 insertions(+), 2 deletions(-)
diff --git a/docs/misc/xen-command-line.pandoc b/docs/misc/xen-command-line.pandoc
index e0b89b7d3319..47e5b4eb6199 100644
--- a/docs/misc/xen-command-line.pandoc
+++ b/docs/misc/xen-command-line.pandoc
@@ -777,9 +777,9 @@ Specify the bit width of the DMA heap.
### dom0
= List of [ pv | pvh, shadow=<bool>, verbose=<bool>,
- cpuid-faulting=<bool>, msr-relaxed=<bool> ]
+ cpuid-faulting=<bool>, msr-relaxed=<bool> ] (x86)
- Applicability: x86
+ = List of [ sve=<integer> ] (Arm)
Controls for how dom0 is constructed on x86 systems.
@@ -838,6 +838,22 @@ Controls for how dom0 is constructed on x86 systems.
If using this option is necessary to fix an issue, please report a bug.
+Enables features on dom0 on Arm systems.
+
+* The `sve` integer parameter enables Arm SVE usage for Dom0 domain and sets
+ the maximum SVE vector length, the option is applicable only to AArch64
+ guests.
+ A value equal to 0 disables the feature, this is the default value.
+ Values below 0 means the feature uses the maximum SVE vector length
+ supported by hardware, if SVE is supported.
+ Values above 0 explicitly set the maximum SVE vector length for Dom0,
+ allowed values are from 128 to maximum 2048, being multiple of 128.
+ Please note that when the user explicitly specifies the value, if that value
+ is above the hardware supported maximum SVE vector length, the domain
+ creation will fail and the system will stop, the same will occur if the
+ option is provided with a non zero value, but the platform doesn't support
+ SVE.
+
### dom0-cpuid
= List of comma separated booleans
diff --git a/xen/arch/arm/arm64/sve.c b/xen/arch/arm/arm64/sve.c
index 84a6dedc1fd7..feaca2cf647d 100644
--- a/xen/arch/arm/arm64/sve.c
+++ b/xen/arch/arm/arm64/sve.c
@@ -13,6 +13,9 @@
#include <asm/processor.h>
#include <asm/system.h>
+/* opt_dom0_sve: allow Dom0 to use SVE and set maximum vector length. */
+int __initdata opt_dom0_sve;
+
extern unsigned int sve_get_hw_vl(void);
/*
@@ -152,6 +155,23 @@ void sve_restore_state(struct vcpu *v)
sve_load_ctx(v->arch.vfp.sve_zreg_ctx_end, v->arch.vfp.fpregs, 1);
}
+bool __init sve_domctl_vl_param(int val, unsigned int *out)
+{
+ /*
+ * Negative SVE parameter value means to use the maximum supported
+ * vector length, otherwise if a positive value is provided, check if the
+ * vector length is a multiple of 128
+ */
+ if ( val < 0 )
+ *out = get_sys_vl_len();
+ else if ( (val % SVE_VL_MULTIPLE_VAL) == 0 )
+ *out = val;
+ else
+ return false;
+
+ return true;
+}
+
/*
* Local variables:
* mode: C
diff --git a/xen/arch/arm/domain_build.c b/xen/arch/arm/domain_build.c
index f373a5024783..9202a96d9c28 100644
--- a/xen/arch/arm/domain_build.c
+++ b/xen/arch/arm/domain_build.c
@@ -62,6 +62,22 @@ custom_param("dom0_mem", parse_dom0_mem);
int __init parse_arch_dom0_param(const char *s, const char *e)
{
+ long long val;
+
+ if ( !parse_signed_integer("sve", s, e, &val) )
+ {
+#ifdef CONFIG_ARM64_SVE
+ if ( (val >= INT_MIN) && (val <= INT_MAX) )
+ opt_dom0_sve = val;
+ else
+ printk(XENLOG_INFO "'sve=%lld' value out of range!\n", val);
+
+ return 0;
+#else
+ panic("'sve' property found, but CONFIG_ARM64_SVE not selected");
+#endif
+ }
+
return -EINVAL;
}
@@ -4113,6 +4129,16 @@ void __init create_dom0(void)
if ( iommu_enabled )
dom0_cfg.flags |= XEN_DOMCTL_CDF_iommu;
+ if ( opt_dom0_sve )
+ {
+ unsigned int vl;
+
+ if ( sve_domctl_vl_param(opt_dom0_sve, &vl) )
+ dom0_cfg.arch.sve_vl = sve_encode_vl(vl);
+ else
+ panic("SVE vector length error\n");
+ }
+
dom0 = domain_create(0, &dom0_cfg, CDF_privileged | CDF_directmap);
if ( IS_ERR(dom0) )
panic("Error creating domain 0 (rc = %ld)\n", PTR_ERR(dom0));
diff --git a/xen/arch/arm/include/asm/arm64/sve.h b/xen/arch/arm/include/asm/arm64/sve.h
index 65b46685d263..a71d6a295dcc 100644
--- a/xen/arch/arm/include/asm/arm64/sve.h
+++ b/xen/arch/arm/include/asm/arm64/sve.h
@@ -21,14 +21,22 @@ static inline unsigned int sve_decode_vl(unsigned int sve_vl)
return sve_vl * SVE_VL_MULTIPLE_VAL;
}
+static inline unsigned int sve_encode_vl(unsigned int sve_vl_bits)
+{
+ return sve_vl_bits / SVE_VL_MULTIPLE_VAL;
+}
+
register_t compute_max_zcr(void);
int sve_context_init(struct vcpu *v);
void sve_context_free(struct vcpu *v);
void sve_save_state(struct vcpu *v);
void sve_restore_state(struct vcpu *v);
+bool sve_domctl_vl_param(int val, unsigned int *out);
#ifdef CONFIG_ARM64_SVE
+extern int opt_dom0_sve;
+
static inline bool is_sve_domain(const struct domain *d)
{
return d->arch.sve_vl > 0;
@@ -38,6 +46,8 @@ unsigned int get_sys_vl_len(void);
#else /* !CONFIG_ARM64_SVE */
+#define opt_dom0_sve 0
+
static inline bool is_sve_domain(const struct domain *d)
{
return false;
diff --git a/xen/common/kernel.c b/xen/common/kernel.c
index f7b1f65f373c..7cd00a4c999a 100644
--- a/xen/common/kernel.c
+++ b/xen/common/kernel.c
@@ -314,6 +314,34 @@ int parse_boolean(const char *name, const char *s, const char *e)
return -1;
}
+int __init parse_signed_integer(const char *name, const char *s, const char *e,
+ long long *val)
+{
+ size_t slen, nlen;
+ const char *str;
+ long long pval;
+
+ slen = e ? ({ ASSERT(e >= s); e - s; }) : strlen(s);
+ nlen = strlen(name);
+
+ if ( !e )
+ e = s + slen;
+
+ /* Check that this is the name we're looking for and a value was provided */
+ if ( slen <= nlen || strncmp(s, name, nlen) || s[nlen] != '=' )
+ return -1;
+
+ pval = simple_strtoll(&s[nlen + 1], &str, 10);
+
+ /* Number not recognised */
+ if ( str != e )
+ return -2;
+
+ *val = pval;
+
+ return 0;
+}
+
int cmdline_strcmp(const char *frag, const char *name)
{
for ( ; ; frag++, name++ )
diff --git a/xen/include/xen/lib.h b/xen/include/xen/lib.h
index e914ccade095..5343ee7a944a 100644
--- a/xen/include/xen/lib.h
+++ b/xen/include/xen/lib.h
@@ -94,6 +94,16 @@ int parse_bool(const char *s, const char *e);
*/
int parse_boolean(const char *name, const char *s, const char *e);
+/**
+ * Given a specific name, parses a string of the form:
+ * $NAME=<integer number>
+ * returning 0 and a value in val, for a recognised integer.
+ * Returns -1 for name not found, general errors, or -2 if name is found but
+ * not recognised number.
+ */
+int parse_signed_integer(const char *name, const char *s, const char *e,
+ long long *val);
+
/**
* Very similar to strcmp(), but will declare a match if the NUL in 'name'
* lines up with comma, colon, semicolon or equals in 'frag'. Designed for
--
2.34.1
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [PATCH v7 08/12] xen/physinfo: encode Arm SVE vector length in arch_capabilities
2023-05-23 7:43 [PATCH v7 00/12] SVE feature for arm guests Luca Fancellu
` (6 preceding siblings ...)
2023-05-23 7:43 ` [PATCH v7 07/12] xen: enable Dom0 to use SVE feature Luca Fancellu
@ 2023-05-23 7:43 ` Luca Fancellu
2023-05-23 7:43 ` [PATCH v7 09/12] tools: add physinfo arch_capabilities handling for Arm Luca Fancellu
` (4 subsequent siblings)
12 siblings, 0 replies; 49+ messages in thread
From: Luca Fancellu @ 2023-05-23 7:43 UTC (permalink / raw)
To: xen-devel
Cc: bertrand.marquis, wei.chen, Stefano Stabellini, Julien Grall,
Volodymyr Babchuk, Andrew Cooper, George Dunlap, Jan Beulich,
Wei Liu
When the arm platform supports SVE, advertise the feature in the
field arch_capabilities in struct xen_sysctl_physinfo by encoding
the SVE vector length in it.
Signed-off-by: Luca Fancellu <luca.fancellu@arm.com>
Reviewed-by: Bertrand Marquis <bertrand.marquis@arm.com>
---
Changes from v6:
- no changes
Changes from v5:
- Add R-by from Bertrand
Changes from v4:
- Write arch_capabilities from arch_do_physinfo instead of using
stub functions (Jan)
Changes from v3:
- domainconfig_encode_vl is now named sve_encode_vl
Changes from v2:
- Remove XEN_SYSCTL_PHYSCAP_ARM_SVE_SHFT, use MASK_INSR and
protect with ifdef XEN_SYSCTL_PHYSCAP_ARM_SVE_MASK (Jan)
- Use the helper function sve_arch_cap_physinfo to encode
the VL into physinfo arch_capabilities field.
Changes from v1:
- Use only arch_capabilities and some defines to encode SVE VL
(Bertrand, Stefano, Jan)
Changes from RFC:
- new patch
---
xen/arch/arm/sysctl.c | 4 ++++
xen/include/public/sysctl.h | 4 ++++
2 files changed, 8 insertions(+)
diff --git a/xen/arch/arm/sysctl.c b/xen/arch/arm/sysctl.c
index b0a78a8b10d0..e9a0661146e4 100644
--- a/xen/arch/arm/sysctl.c
+++ b/xen/arch/arm/sysctl.c
@@ -11,11 +11,15 @@
#include <xen/lib.h>
#include <xen/errno.h>
#include <xen/hypercall.h>
+#include <asm/arm64/sve.h>
#include <public/sysctl.h>
void arch_do_physinfo(struct xen_sysctl_physinfo *pi)
{
pi->capabilities |= XEN_SYSCTL_PHYSCAP_hvm | XEN_SYSCTL_PHYSCAP_hap;
+
+ pi->arch_capabilities |= MASK_INSR(sve_encode_vl(get_sys_vl_len()),
+ XEN_SYSCTL_PHYSCAP_ARM_SVE_MASK);
}
long arch_do_sysctl(struct xen_sysctl *sysctl,
diff --git a/xen/include/public/sysctl.h b/xen/include/public/sysctl.h
index 2b24d6bfd00e..9d06e92d0f6a 100644
--- a/xen/include/public/sysctl.h
+++ b/xen/include/public/sysctl.h
@@ -94,6 +94,10 @@ struct xen_sysctl_tbuf_op {
/* Max XEN_SYSCTL_PHYSCAP_* constant. Used for ABI checking. */
#define XEN_SYSCTL_PHYSCAP_MAX XEN_SYSCTL_PHYSCAP_gnttab_v2
+#if defined(__arm__) || defined(__aarch64__)
+#define XEN_SYSCTL_PHYSCAP_ARM_SVE_MASK (0x1FU)
+#endif
+
struct xen_sysctl_physinfo {
uint32_t threads_per_core;
uint32_t cores_per_socket;
--
2.34.1
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [PATCH v7 09/12] tools: add physinfo arch_capabilities handling for Arm
2023-05-23 7:43 [PATCH v7 00/12] SVE feature for arm guests Luca Fancellu
` (7 preceding siblings ...)
2023-05-23 7:43 ` [PATCH v7 08/12] xen/physinfo: encode Arm SVE vector length in arch_capabilities Luca Fancellu
@ 2023-05-23 7:43 ` Luca Fancellu
2023-05-25 8:39 ` Marek Marczykowski-Górecki
2023-05-23 7:43 ` [PATCH v7 10/12] xen/tools: add sve parameter in XL configuration Luca Fancellu
` (3 subsequent siblings)
12 siblings, 1 reply; 49+ messages in thread
From: Luca Fancellu @ 2023-05-23 7:43 UTC (permalink / raw)
To: xen-devel
Cc: bertrand.marquis, wei.chen, George Dunlap, Nick Rosbrook,
Wei Liu, Anthony PERARD, Juergen Gross, Christian Lindig,
David Scott, Marek Marczykowski-Górecki, Christian Lindig
On Arm, the SVE vector length is encoded in arch_capabilities field
of struct xen_sysctl_physinfo, make use of this field in the tools
when building for arm.
Create header arm-arch-capabilities.h to handle the arch_capabilities
field of physinfo for Arm.
Removed include for xen-tools/common-macros.h in
python/xen/lowlevel/xc/xc.c because it is already included by the
arm-arch-capabilities.h header.
Signed-off-by: Luca Fancellu <luca.fancellu@arm.com>
Acked-by: George Dunlap <george.dunlap@citrix.com>
Acked-by: Christian Lindig <christian.lindig@cloud.com>
Reviewed-by: Anthony PERARD <anthony.perard@citrix.com>
---
Changes from v6:
- Fix licence header in arm-atch-capabilities.h, add R-by (Anthony)
Changes from v5:
- no changes
Changes from v4:
- Move arm-arch-capabilities.h into xen-tools/, add LIBXL_HAVE_,
fixed python return type to I instead of i. (Anthony)
Changes from v3:
- add Ack-by for the Golang bits (George)
- add Ack-by for the OCaml tools (Christian)
- now xen-tools/libs.h is named xen-tools/common-macros.h
- changed commit message to explain why the header modification
in python/xen/lowlevel/xc/xc.c
Changes from v2:
- rename arm_arch_capabilities.h in arm-arch-capabilities.h, use
MASK_EXTR.
- Now arm-arch-capabilities.h needs MASK_EXTR macro, but it is
defined in libxl_internal.h, it doesn't feel right to include
that header so move MASK_EXTR into xen-tools/libs.h that is also
included in libxl_internal.h
Changes from v1:
- now SVE VL is encoded in arch_capabilities on Arm
Changes from RFC:
- new patch
---
tools/golang/xenlight/helpers.gen.go | 2 ++
tools/golang/xenlight/types.gen.go | 1 +
tools/include/libxl.h | 6 ++++
.../include/xen-tools/arm-arch-capabilities.h | 28 +++++++++++++++++++
tools/include/xen-tools/common-macros.h | 2 ++
tools/libs/light/libxl.c | 1 +
tools/libs/light/libxl_internal.h | 1 -
tools/libs/light/libxl_types.idl | 1 +
tools/ocaml/libs/xc/xenctrl.ml | 4 +--
tools/ocaml/libs/xc/xenctrl.mli | 4 +--
tools/ocaml/libs/xc/xenctrl_stubs.c | 8 ++++--
tools/python/xen/lowlevel/xc/xc.c | 8 ++++--
tools/xl/xl_info.c | 8 ++++++
13 files changed, 62 insertions(+), 12 deletions(-)
create mode 100644 tools/include/xen-tools/arm-arch-capabilities.h
diff --git a/tools/golang/xenlight/helpers.gen.go b/tools/golang/xenlight/helpers.gen.go
index 0a203d22321f..35397be2f9e2 100644
--- a/tools/golang/xenlight/helpers.gen.go
+++ b/tools/golang/xenlight/helpers.gen.go
@@ -3506,6 +3506,7 @@ x.CapVmtrace = bool(xc.cap_vmtrace)
x.CapVpmu = bool(xc.cap_vpmu)
x.CapGnttabV1 = bool(xc.cap_gnttab_v1)
x.CapGnttabV2 = bool(xc.cap_gnttab_v2)
+x.ArchCapabilities = uint32(xc.arch_capabilities)
return nil}
@@ -3540,6 +3541,7 @@ xc.cap_vmtrace = C.bool(x.CapVmtrace)
xc.cap_vpmu = C.bool(x.CapVpmu)
xc.cap_gnttab_v1 = C.bool(x.CapGnttabV1)
xc.cap_gnttab_v2 = C.bool(x.CapGnttabV2)
+xc.arch_capabilities = C.uint32_t(x.ArchCapabilities)
return nil
}
diff --git a/tools/golang/xenlight/types.gen.go b/tools/golang/xenlight/types.gen.go
index a7c17699f80e..3d968a496744 100644
--- a/tools/golang/xenlight/types.gen.go
+++ b/tools/golang/xenlight/types.gen.go
@@ -1079,6 +1079,7 @@ CapVmtrace bool
CapVpmu bool
CapGnttabV1 bool
CapGnttabV2 bool
+ArchCapabilities uint32
}
type Connectorinfo struct {
diff --git a/tools/include/libxl.h b/tools/include/libxl.h
index cfa1a191318c..4fa09ff7635a 100644
--- a/tools/include/libxl.h
+++ b/tools/include/libxl.h
@@ -525,6 +525,12 @@
*/
#define LIBXL_HAVE_PHYSINFO_CAP_GNTTAB 1
+/*
+ * LIBXL_HAVE_PHYSINFO_ARCH_CAPABILITIES indicates that libxl_physinfo has a
+ * arch_capabilities field.
+ */
+#define LIBXL_HAVE_PHYSINFO_ARCH_CAPABILITIES 1
+
/*
* LIBXL_HAVE_MAX_GRANT_VERSION indicates libxl_domain_build_info has a
* max_grant_version field for setting the max grant table version per
diff --git a/tools/include/xen-tools/arm-arch-capabilities.h b/tools/include/xen-tools/arm-arch-capabilities.h
new file mode 100644
index 000000000000..3849e897925d
--- /dev/null
+++ b/tools/include/xen-tools/arm-arch-capabilities.h
@@ -0,0 +1,28 @@
+/* SPDX-License-Identifier: LGPL-2.1-only */
+/*
+ * Copyright (C) 2023 ARM Ltd.
+ */
+
+#ifndef ARM_ARCH_CAPABILITIES_H
+#define ARM_ARCH_CAPABILITIES_H
+
+#include <stdint.h>
+#include <xen/sysctl.h>
+
+#include <xen-tools/common-macros.h>
+
+static inline
+unsigned int arch_capabilities_arm_sve(unsigned int arch_capabilities)
+{
+#if defined(__aarch64__)
+ unsigned int sve_vl = MASK_EXTR(arch_capabilities,
+ XEN_SYSCTL_PHYSCAP_ARM_SVE_MASK);
+
+ /* Vector length is divided by 128 before storing it in arch_capabilities */
+ return sve_vl * 128U;
+#else
+ return 0;
+#endif
+}
+
+#endif /* ARM_ARCH_CAPABILITIES_H */
diff --git a/tools/include/xen-tools/common-macros.h b/tools/include/xen-tools/common-macros.h
index 76b55bf62085..d53b88182560 100644
--- a/tools/include/xen-tools/common-macros.h
+++ b/tools/include/xen-tools/common-macros.h
@@ -72,6 +72,8 @@
#define ROUNDUP(_x,_w) (((unsigned long)(_x)+(1UL<<(_w))-1) & ~((1UL<<(_w))-1))
#endif
+#define MASK_EXTR(v, m) (((v) & (m)) / ((m) & -(m)))
+
#ifndef __must_check
#define __must_check __attribute__((__warn_unused_result__))
#endif
diff --git a/tools/libs/light/libxl.c b/tools/libs/light/libxl.c
index a0bf7d186f69..175d6dde0b80 100644
--- a/tools/libs/light/libxl.c
+++ b/tools/libs/light/libxl.c
@@ -409,6 +409,7 @@ int libxl_get_physinfo(libxl_ctx *ctx, libxl_physinfo *physinfo)
!!(xcphysinfo.capabilities & XEN_SYSCTL_PHYSCAP_gnttab_v1);
physinfo->cap_gnttab_v2 =
!!(xcphysinfo.capabilities & XEN_SYSCTL_PHYSCAP_gnttab_v2);
+ physinfo->arch_capabilities = xcphysinfo.arch_capabilities;
GC_FREE;
return 0;
diff --git a/tools/libs/light/libxl_internal.h b/tools/libs/light/libxl_internal.h
index 5244fde6239a..8aba3e138909 100644
--- a/tools/libs/light/libxl_internal.h
+++ b/tools/libs/light/libxl_internal.h
@@ -132,7 +132,6 @@
#define DIV_ROUNDUP(n, d) (((n) + (d) - 1) / (d))
-#define MASK_EXTR(v, m) (((v) & (m)) / ((m) & -(m)))
#define MASK_INSR(v, m) (((v) * ((m) & -(m))) & (m))
#define LIBXL__LOGGING_ENABLED
diff --git a/tools/libs/light/libxl_types.idl b/tools/libs/light/libxl_types.idl
index c10292e0d7e3..fd31dacf7d5a 100644
--- a/tools/libs/light/libxl_types.idl
+++ b/tools/libs/light/libxl_types.idl
@@ -1133,6 +1133,7 @@ libxl_physinfo = Struct("physinfo", [
("cap_vpmu", bool),
("cap_gnttab_v1", bool),
("cap_gnttab_v2", bool),
+ ("arch_capabilities", uint32),
], dir=DIR_OUT)
libxl_connectorinfo = Struct("connectorinfo", [
diff --git a/tools/ocaml/libs/xc/xenctrl.ml b/tools/ocaml/libs/xc/xenctrl.ml
index e4096bf92c1d..bf23ca50bb15 100644
--- a/tools/ocaml/libs/xc/xenctrl.ml
+++ b/tools/ocaml/libs/xc/xenctrl.ml
@@ -128,12 +128,10 @@ type physinfo_cap_flag =
| CAP_Gnttab_v1
| CAP_Gnttab_v2
-type arm_physinfo_cap_flag
-
type x86_physinfo_cap_flag
type arch_physinfo_cap_flags =
- | ARM of arm_physinfo_cap_flag list
+ | ARM of int
| X86 of x86_physinfo_cap_flag list
type physinfo =
diff --git a/tools/ocaml/libs/xc/xenctrl.mli b/tools/ocaml/libs/xc/xenctrl.mli
index ef2254537430..ed1e28ea30a0 100644
--- a/tools/ocaml/libs/xc/xenctrl.mli
+++ b/tools/ocaml/libs/xc/xenctrl.mli
@@ -113,12 +113,10 @@ type physinfo_cap_flag =
| CAP_Gnttab_v1
| CAP_Gnttab_v2
-type arm_physinfo_cap_flag
-
type x86_physinfo_cap_flag
type arch_physinfo_cap_flags =
- | ARM of arm_physinfo_cap_flag list
+ | ARM of int
| X86 of x86_physinfo_cap_flag list
type physinfo = {
diff --git a/tools/ocaml/libs/xc/xenctrl_stubs.c b/tools/ocaml/libs/xc/xenctrl_stubs.c
index f686db3124ee..a03da31f6f2c 100644
--- a/tools/ocaml/libs/xc/xenctrl_stubs.c
+++ b/tools/ocaml/libs/xc/xenctrl_stubs.c
@@ -851,13 +851,15 @@ CAMLprim value stub_xc_physinfo(value xch_val)
arch_cap_list = Tag_cons;
arch_cap_flags_tag = 1; /* tag x86 */
-#else
- caml_failwith("Unhandled architecture");
-#endif
arch_cap_flags = caml_alloc_small(1, arch_cap_flags_tag);
Store_field(arch_cap_flags, 0, arch_cap_list);
Store_field(physinfo, 10, arch_cap_flags);
+#elif defined(__aarch64__)
+ Store_field(physinfo, 10, Val_int(c_physinfo.arch_capabilities));
+#else
+ caml_failwith("Unhandled architecture");
+#endif
CAMLreturn(physinfo);
}
diff --git a/tools/python/xen/lowlevel/xc/xc.c b/tools/python/xen/lowlevel/xc/xc.c
index 9728b34185ac..b3699fdac58e 100644
--- a/tools/python/xen/lowlevel/xc/xc.c
+++ b/tools/python/xen/lowlevel/xc/xc.c
@@ -22,6 +22,7 @@
#include <xen/hvm/hvm_info_table.h>
#include <xen/hvm/params.h>
+#include <xen-tools/arm-arch-capabilities.h>
#include <xen-tools/common-macros.h>
/* Needed for Python versions earlier than 2.3. */
@@ -897,7 +898,7 @@ static PyObject *pyxc_physinfo(XcObject *self)
if ( p != virt_caps )
*(p-1) = '\0';
- return Py_BuildValue("{s:i,s:i,s:i,s:i,s:l,s:l,s:l,s:i,s:s,s:s}",
+ return Py_BuildValue("{s:i,s:i,s:i,s:i,s:l,s:l,s:l,s:i,s:s,s:s,s:I}",
"nr_nodes", pinfo.nr_nodes,
"threads_per_core", pinfo.threads_per_core,
"cores_per_socket", pinfo.cores_per_socket,
@@ -907,7 +908,10 @@ static PyObject *pyxc_physinfo(XcObject *self)
"scrub_memory", pages_to_kib(pinfo.scrub_pages),
"cpu_khz", pinfo.cpu_khz,
"hw_caps", cpu_cap,
- "virt_caps", virt_caps);
+ "virt_caps", virt_caps,
+ "arm_sve_vl",
+ arch_capabilities_arm_sve(pinfo.arch_capabilities)
+ );
}
static PyObject *pyxc_getcpuinfo(XcObject *self, PyObject *args, PyObject *kwds)
diff --git a/tools/xl/xl_info.c b/tools/xl/xl_info.c
index 712b7638b013..ddc42f96b979 100644
--- a/tools/xl/xl_info.c
+++ b/tools/xl/xl_info.c
@@ -27,6 +27,7 @@
#include <libxl_json.h>
#include <libxl_utils.h>
#include <libxlutil.h>
+#include <xen-tools/arm-arch-capabilities.h>
#include "xl.h"
#include "xl_utils.h"
@@ -224,6 +225,13 @@ static void output_physinfo(void)
info.cap_gnttab_v2 ? " gnttab-v2" : ""
);
+ /* Print arm SVE vector length only on ARM platforms */
+#if defined(__aarch64__)
+ maybe_printf("arm_sve_vector_length : %u\n",
+ arch_capabilities_arm_sve(info.arch_capabilities)
+ );
+#endif
+
vinfo = libxl_get_version_info(ctx);
if (vinfo) {
i = (1 << 20) / vinfo->pagesize;
--
2.34.1
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [PATCH v7 10/12] xen/tools: add sve parameter in XL configuration
2023-05-23 7:43 [PATCH v7 00/12] SVE feature for arm guests Luca Fancellu
` (8 preceding siblings ...)
2023-05-23 7:43 ` [PATCH v7 09/12] tools: add physinfo arch_capabilities handling for Arm Luca Fancellu
@ 2023-05-23 7:43 ` Luca Fancellu
2023-05-23 16:49 ` Anthony PERARD
2023-05-23 7:43 ` [PATCH v7 11/12] xen/arm: add sve property for dom0less domUs Luca Fancellu
` (2 subsequent siblings)
12 siblings, 1 reply; 49+ messages in thread
From: Luca Fancellu @ 2023-05-23 7:43 UTC (permalink / raw)
To: xen-devel
Cc: bertrand.marquis, wei.chen, Wei Liu, Anthony PERARD,
George Dunlap, Nick Rosbrook, Juergen Gross
Add sve parameter in XL configuration to allow guests to use
SVE feature.
Signed-off-by: Luca Fancellu <luca.fancellu@arm.com>
---
Changes from v6:
- Add check for sve_vl be multiple of 128 (Anthony)
Changes from v5:
- Update documentation
- re-generated golang files
Changes from v4:
- Rename sve field to sve_vl (Anthony), changed type to
libxl_sve_type
- Sanity check of sve field in libxl instead of xl, update docs
(Anthony)
- drop Ack-by from George because of the changes in the Golang bits
Changes from v3:
- no changes
Changes from v2:
- domain configuration field name has changed to sve_vl,
also its value now is VL/128.
- Add Ack-by George for the Golang bits
Changes from v1:
- updated to use arch_capabilities field for vector length
Changes from RFC:
- changed libxl_types.idl sve field to uint16
- now toolstack uses info from physinfo to check against the
sve XL value
- Changed documentation
---
docs/man/xl.cfg.5.pod.in | 16 ++++++++++++++
tools/golang/xenlight/helpers.gen.go | 2 ++
tools/golang/xenlight/types.gen.go | 23 +++++++++++++++++++
tools/include/libxl.h | 5 +++++
tools/libs/light/libxl_arm.c | 33 ++++++++++++++++++++++++++++
tools/libs/light/libxl_types.idl | 22 +++++++++++++++++++
tools/xl/xl_parse.c | 8 +++++++
7 files changed, 109 insertions(+)
diff --git a/docs/man/xl.cfg.5.pod.in b/docs/man/xl.cfg.5.pod.in
index 24ac92718288..1b4e13ab647b 100644
--- a/docs/man/xl.cfg.5.pod.in
+++ b/docs/man/xl.cfg.5.pod.in
@@ -2955,6 +2955,22 @@ Currently, only the "sbsa_uart" model is supported for ARM.
=back
+=item B<sve="vl">
+
+The `sve` parameter enables Arm Scalable Vector Extension (SVE) usage for the
+guest and sets the maximum SVE vector length, the option is applicable only to
+AArch64 guests.
+A value equal to "disabled" disables the feature, this is the default value.
+Allowed values are "disabled", "128", "256", "384", "512", "640", "768", "896",
+"1024", "1152", "1280", "1408", "1536", "1664", "1792", "1920", "2048", "hw".
+Specifying "hw" means that the maximum vector length supported by the platform
+will be used.
+Please be aware that if a specific vector length is passed and its value is
+above the maximum vector length supported by the platform, an error will be
+raised.
+
+=back
+
=head3 x86
=over 4
diff --git a/tools/golang/xenlight/helpers.gen.go b/tools/golang/xenlight/helpers.gen.go
index 35397be2f9e2..cd1a16e32eac 100644
--- a/tools/golang/xenlight/helpers.gen.go
+++ b/tools/golang/xenlight/helpers.gen.go
@@ -1149,6 +1149,7 @@ default:
return fmt.Errorf("invalid union key '%v'", x.Type)}
x.ArchArm.GicVersion = GicVersion(xc.arch_arm.gic_version)
x.ArchArm.Vuart = VuartType(xc.arch_arm.vuart)
+x.ArchArm.SveVl = SveType(xc.arch_arm.sve_vl)
if err := x.ArchX86.MsrRelaxed.fromC(&xc.arch_x86.msr_relaxed);err != nil {
return fmt.Errorf("converting field ArchX86.MsrRelaxed: %v", err)
}
@@ -1653,6 +1654,7 @@ default:
return fmt.Errorf("invalid union key '%v'", x.Type)}
xc.arch_arm.gic_version = C.libxl_gic_version(x.ArchArm.GicVersion)
xc.arch_arm.vuart = C.libxl_vuart_type(x.ArchArm.Vuart)
+xc.arch_arm.sve_vl = C.libxl_sve_type(x.ArchArm.SveVl)
if err := x.ArchX86.MsrRelaxed.toC(&xc.arch_x86.msr_relaxed); err != nil {
return fmt.Errorf("converting field ArchX86.MsrRelaxed: %v", err)
}
diff --git a/tools/golang/xenlight/types.gen.go b/tools/golang/xenlight/types.gen.go
index 3d968a496744..b131a7eedc9d 100644
--- a/tools/golang/xenlight/types.gen.go
+++ b/tools/golang/xenlight/types.gen.go
@@ -490,6 +490,28 @@ TeeTypeNone TeeType = 0
TeeTypeOptee TeeType = 1
)
+type SveType int
+const(
+SveTypeHw SveType = -1
+SveTypeDisabled SveType = 0
+SveType128 SveType = 128
+SveType256 SveType = 256
+SveType384 SveType = 384
+SveType512 SveType = 512
+SveType640 SveType = 640
+SveType768 SveType = 768
+SveType896 SveType = 896
+SveType1024 SveType = 1024
+SveType1152 SveType = 1152
+SveType1280 SveType = 1280
+SveType1408 SveType = 1408
+SveType1536 SveType = 1536
+SveType1664 SveType = 1664
+SveType1792 SveType = 1792
+SveType1920 SveType = 1920
+SveType2048 SveType = 2048
+)
+
type RdmReserve struct {
Strategy RdmReserveStrategy
Policy RdmReservePolicy
@@ -564,6 +586,7 @@ TypeUnion DomainBuildInfoTypeUnion
ArchArm struct {
GicVersion GicVersion
Vuart VuartType
+SveVl SveType
}
ArchX86 struct {
MsrRelaxed Defbool
diff --git a/tools/include/libxl.h b/tools/include/libxl.h
index 4fa09ff7635a..cac641a7eba2 100644
--- a/tools/include/libxl.h
+++ b/tools/include/libxl.h
@@ -283,6 +283,11 @@
*/
#define LIBXL_HAVE_BUILDINFO_ARCH_ARM_TEE 1
+/*
+ * libxl_domain_build_info has the arch_arm.sve_vl field.
+ */
+#define LIBXL_HAVE_BUILDINFO_ARCH_ARM_SVE_VL 1
+
/*
* LIBXL_HAVE_SOFT_RESET indicates that libxl supports performing
* 'soft reset' for domains and there is 'soft_reset' shutdown reason
diff --git a/tools/libs/light/libxl_arm.c b/tools/libs/light/libxl_arm.c
index 97c80d7ed0fa..35f76dfc21e4 100644
--- a/tools/libs/light/libxl_arm.c
+++ b/tools/libs/light/libxl_arm.c
@@ -3,6 +3,8 @@
#include "libxl_libfdt_compat.h"
#include "libxl_arm.h"
+#include <xen-tools/arm-arch-capabilities.h>
+
#include <stdbool.h>
#include <libfdt.h>
#include <assert.h>
@@ -211,6 +213,12 @@ int libxl__arch_domain_prepare_config(libxl__gc *gc,
return ERROR_FAIL;
}
+ /* Parameter is sanitised in libxl__arch_domain_build_info_setdefault */
+ if (d_config->b_info.arch_arm.sve_vl) {
+ /* Vector length is divided by 128 in struct xen_domctl_createdomain */
+ config->arch.sve_vl = d_config->b_info.arch_arm.sve_vl / 128U;
+ }
+
return 0;
}
@@ -1685,6 +1693,31 @@ int libxl__arch_domain_build_info_setdefault(libxl__gc *gc,
/* ACPI is disabled by default */
libxl_defbool_setdefault(&b_info->acpi, false);
+ /* Sanitise SVE parameter */
+ if (b_info->arch_arm.sve_vl) {
+ unsigned int max_sve_vl =
+ arch_capabilities_arm_sve(physinfo->arch_capabilities);
+
+ if (!max_sve_vl) {
+ LOG(ERROR, "SVE is unsupported on this machine.");
+ return ERROR_FAIL;
+ }
+
+ if (LIBXL_SVE_TYPE_HW == b_info->arch_arm.sve_vl) {
+ b_info->arch_arm.sve_vl = max_sve_vl;
+ } else if (b_info->arch_arm.sve_vl > max_sve_vl) {
+ LOG(ERROR,
+ "Invalid sve value: %d. Platform supports up to %u bits",
+ b_info->arch_arm.sve_vl, max_sve_vl);
+ return ERROR_FAIL;
+ } else if (b_info->arch_arm.sve_vl % 128) {
+ LOG(ERROR,
+ "Invalid sve value: %d. It must be multiple of 128",
+ b_info->arch_arm.sve_vl);
+ return ERROR_FAIL;
+ }
+ }
+
if (b_info->type != LIBXL_DOMAIN_TYPE_PV)
return 0;
diff --git a/tools/libs/light/libxl_types.idl b/tools/libs/light/libxl_types.idl
index fd31dacf7d5a..9e48bb772646 100644
--- a/tools/libs/light/libxl_types.idl
+++ b/tools/libs/light/libxl_types.idl
@@ -523,6 +523,27 @@ libxl_tee_type = Enumeration("tee_type", [
(1, "optee")
], init_val = "LIBXL_TEE_TYPE_NONE")
+libxl_sve_type = Enumeration("sve_type", [
+ (-1, "hw"),
+ (0, "disabled"),
+ (128, "128"),
+ (256, "256"),
+ (384, "384"),
+ (512, "512"),
+ (640, "640"),
+ (768, "768"),
+ (896, "896"),
+ (1024, "1024"),
+ (1152, "1152"),
+ (1280, "1280"),
+ (1408, "1408"),
+ (1536, "1536"),
+ (1664, "1664"),
+ (1792, "1792"),
+ (1920, "1920"),
+ (2048, "2048")
+ ], init_val = "LIBXL_SVE_TYPE_DISABLED")
+
libxl_rdm_reserve = Struct("rdm_reserve", [
("strategy", libxl_rdm_reserve_strategy),
("policy", libxl_rdm_reserve_policy),
@@ -690,6 +711,7 @@ libxl_domain_build_info = Struct("domain_build_info",[
("arch_arm", Struct(None, [("gic_version", libxl_gic_version),
("vuart", libxl_vuart_type),
+ ("sve_vl", libxl_sve_type),
])),
("arch_x86", Struct(None, [("msr_relaxed", libxl_defbool),
])),
diff --git a/tools/xl/xl_parse.c b/tools/xl/xl_parse.c
index 1f6f47daf4e1..f036e56fc239 100644
--- a/tools/xl/xl_parse.c
+++ b/tools/xl/xl_parse.c
@@ -2887,6 +2887,14 @@ skip_usbdev:
}
}
+ if (!xlu_cfg_get_string (config, "sve", &buf, 1)) {
+ e = libxl_sve_type_from_string(buf, &b_info->arch_arm.sve_vl);
+ if (e) {
+ fprintf(stderr, "Unknown sve \"%s\" specified\n", buf);
+ exit(EXIT_FAILURE);
+ }
+ }
+
parse_vkb_list(config, d_config);
d_config->virtios = NULL;
--
2.34.1
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [PATCH v7 11/12] xen/arm: add sve property for dom0less domUs
2023-05-23 7:43 [PATCH v7 00/12] SVE feature for arm guests Luca Fancellu
` (9 preceding siblings ...)
2023-05-23 7:43 ` [PATCH v7 10/12] xen/tools: add sve parameter in XL configuration Luca Fancellu
@ 2023-05-23 7:43 ` Luca Fancellu
2023-05-24 15:20 ` Bertrand Marquis
2023-05-25 9:30 ` Julien Grall
2023-05-23 7:43 ` [PATCH v7 12/12] xen/changelog: Add SVE and "dom0" options to the changelog for Arm Luca Fancellu
2023-05-25 8:15 ` [PATCH v7 00/12] SVE feature for arm guests Luca Fancellu
12 siblings, 2 replies; 49+ messages in thread
From: Luca Fancellu @ 2023-05-23 7:43 UTC (permalink / raw)
To: xen-devel
Cc: bertrand.marquis, wei.chen, Stefano Stabellini, Julien Grall,
Volodymyr Babchuk
Add a device tree property in the dom0less domU configuration
to enable the guest to use SVE.
Update documentation.
Signed-off-by: Luca Fancellu <luca.fancellu@arm.com>
---
Changes from v6:
- Use ifdef in create_domUs and fail if 'sve' is used on systems
with CONFIG_ARM64_SVE not selected (Bertrand, Julien, Jan)
Changes from v5:
- Stop the domain creation if SVE not supported or SVE VL
errors (Julien, Bertrand)
- now sve_sanitize_vl_param is renamed to sve_domctl_vl_param
and returns a boolean, change the affected code.
- Reworded documentation.
Changes from v4:
- Now it is possible to specify the property "sve" for dom0less
device tree node without any value, that means the platform
supported VL will be used.
Changes from v3:
- Now domainconfig_encode_vl is named sve_encode_vl
Changes from v2:
- xen_domctl_createdomain field name has changed into sve_vl
and its value is the VL/128, use domainconfig_encode_vl
to encode a plain VL in bits.
Changes from v1:
- No changes
Changes from RFC:
- Changed documentation
---
docs/misc/arm/device-tree/booting.txt | 16 +++++++++++++++
xen/arch/arm/domain_build.c | 28 +++++++++++++++++++++++++++
2 files changed, 44 insertions(+)
diff --git a/docs/misc/arm/device-tree/booting.txt b/docs/misc/arm/device-tree/booting.txt
index 3879340b5e0a..32a0e508c471 100644
--- a/docs/misc/arm/device-tree/booting.txt
+++ b/docs/misc/arm/device-tree/booting.txt
@@ -193,6 +193,22 @@ with the following properties:
Optional. Handle to a xen,cpupool device tree node that identifies the
cpupool where the guest will be started at boot.
+- sve
+
+ Optional. The `sve` property enables Arm SVE usage for the domain and sets
+ the maximum SVE vector length, the option is applicable only to AArch64
+ guests.
+ A value equal to 0 disables the feature, this is the default value.
+ Specifying this property with no value, means that the SVE vector length
+ will be set equal to the maximum vector length supported by the platform.
+ Values above 0 explicitly set the maximum SVE vector length for the domain,
+ allowed values are from 128 to maximum 2048, being multiple of 128.
+ Please note that when the user explicitly specifies the value, if that value
+ is above the hardware supported maximum SVE vector length, the domain
+ creation will fail and the system will stop, the same will occur if the
+ option is provided with a non zero value, but the platform doesn't support
+ SVE.
+
- xen,enhanced
A string property. Possible property values are:
diff --git a/xen/arch/arm/domain_build.c b/xen/arch/arm/domain_build.c
index 9202a96d9c28..ba4fe9e165ee 100644
--- a/xen/arch/arm/domain_build.c
+++ b/xen/arch/arm/domain_build.c
@@ -4008,6 +4008,34 @@ void __init create_domUs(void)
d_cfg.max_maptrack_frames = val;
}
+ if ( dt_get_property(node, "sve", &val) )
+ {
+#ifdef CONFIG_ARM64_SVE
+ unsigned int sve_vl_bits;
+ bool ret = false;
+
+ if ( !val )
+ {
+ /* Property found with no value, means max HW VL supported */
+ ret = sve_domctl_vl_param(-1, &sve_vl_bits);
+ }
+ else
+ {
+ if ( dt_property_read_u32(node, "sve", &val) )
+ ret = sve_domctl_vl_param(val, &sve_vl_bits);
+ else
+ panic("Error reading 'sve' property");
+ }
+
+ if ( ret )
+ d_cfg.arch.sve_vl = sve_encode_vl(sve_vl_bits);
+ else
+ panic("SVE vector length error\n");
+#else
+ panic("'sve' property found, but CONFIG_ARM64_SVE not selected");
+#endif
+ }
+
/*
* The variable max_init_domid is initialized with zero, so here it's
* very important to use the pre-increment operator to call
--
2.34.1
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [PATCH v7 12/12] xen/changelog: Add SVE and "dom0" options to the changelog for Arm
2023-05-23 7:43 [PATCH v7 00/12] SVE feature for arm guests Luca Fancellu
` (10 preceding siblings ...)
2023-05-23 7:43 ` [PATCH v7 11/12] xen/arm: add sve property for dom0less domUs Luca Fancellu
@ 2023-05-23 7:43 ` Luca Fancellu
2023-05-24 15:22 ` Bertrand Marquis
2023-05-25 9:41 ` Julien Grall
2023-05-25 8:15 ` [PATCH v7 00/12] SVE feature for arm guests Luca Fancellu
12 siblings, 2 replies; 49+ messages in thread
From: Luca Fancellu @ 2023-05-23 7:43 UTC (permalink / raw)
To: xen-devel
Cc: bertrand.marquis, wei.chen, Henry Wang, Community Manager,
Andrew Cooper, George Dunlap, Jan Beulich, Julien Grall,
Stefano Stabellini, Wei Liu
Arm now can use the "dom0=" Xen command line option and the support
for guests running SVE instructions is added, put entries in the
changelog.
Mention the "Tech Preview" status and add an entry in SUPPORT.md
Signed-off-by: Luca Fancellu <luca.fancellu@arm.com>
Acked-by: Henry Wang <Henry.Wang@arm.com> # CHANGELOG
---
Changes from v6:
- Add Henry's A-by to CHANGELOG
Changes from v5:
- Add Tech Preview status and add entry in SUPPORT.md (Bertrand)
Changes from v4:
- No changes
Change from v3:
- new patch
---
CHANGELOG.md | 3 +++
SUPPORT.md | 6 ++++++
2 files changed, 9 insertions(+)
diff --git a/CHANGELOG.md b/CHANGELOG.md
index 5bfd3aa5c0d5..512b7bdc0fcb 100644
--- a/CHANGELOG.md
+++ b/CHANGELOG.md
@@ -11,6 +11,8 @@ The format is based on [Keep a Changelog](https://keepachangelog.com/en/1.0.0/)
cap toolstack provided values.
- Ignore VCPUOP_set_singleshot_timer's VCPU_SSHOTTMR_future flag. The only
known user doesn't use it properly, leading to in-guest breakage.
+ - The "dom0" option is now supported on Arm and "sve=" sub-option can be used
+ to enable dom0 guest to use SVE/SVE2 instructions.
### Added
- On x86, support for features new in Intel Sapphire Rapids CPUs:
@@ -20,6 +22,7 @@ The format is based on [Keep a Changelog](https://keepachangelog.com/en/1.0.0/)
- Bus-lock detection, used by Xen to mitigate (by rate-limiting) the system
wide impact of a guest misusing atomic instructions.
- xl/libxl can customize SMBIOS strings for HVM guests.
+ - On Arm, Xen supports guests running SVE/SVE2 instructions. (Tech Preview)
## [4.17.0](https://xenbits.xen.org/gitweb/?p=xen.git;a=shortlog;h=RELEASE-4.17.0) - 2022-12-12
diff --git a/SUPPORT.md b/SUPPORT.md
index 6dbed9d5d029..e0fa2246807b 100644
--- a/SUPPORT.md
+++ b/SUPPORT.md
@@ -99,6 +99,12 @@ Extension to the GICv3 interrupt controller to support MSI.
Status: Experimental
+### ARM Scalable Vector Extension (SVE/SVE2)
+
+AArch64 guest can use Scalable Vector Extension (SVE/SVE2).
+
+ Status: Tech Preview
+
## Guest Type
### x86/PV
--
2.34.1
^ permalink raw reply related [flat|nested] 49+ messages in thread
* Re: [PATCH v7 07/12] xen: enable Dom0 to use SVE feature
2023-05-23 7:43 ` [PATCH v7 07/12] xen: enable Dom0 to use SVE feature Luca Fancellu
@ 2023-05-23 10:02 ` Jan Beulich
2023-05-23 10:21 ` Luca Fancellu
2023-05-24 10:05 ` Bertrand Marquis
1 sibling, 1 reply; 49+ messages in thread
From: Jan Beulich @ 2023-05-23 10:02 UTC (permalink / raw)
To: Luca Fancellu
Cc: bertrand.marquis, wei.chen, Andrew Cooper, George Dunlap,
Julien Grall, Stefano Stabellini, Wei Liu, Volodymyr Babchuk,
xen-devel
On 23.05.2023 09:43, Luca Fancellu wrote:
> Add a command line parameter to allow Dom0 the use of SVE resources,
> the command line parameter sve=<integer>, sub argument of dom0=,
> controls the feature on this domain and sets the maximum SVE vector
> length for Dom0.
>
> Add a new function, parse_signed_integer(), to parse an integer
> command line argument.
>
> Signed-off-by: Luca Fancellu <luca.fancellu@arm.com>
Reviewed-by: Jan Beulich <jbeulich@suse.com> # !arm
> --- a/docs/misc/xen-command-line.pandoc
> +++ b/docs/misc/xen-command-line.pandoc
> @@ -777,9 +777,9 @@ Specify the bit width of the DMA heap.
>
> ### dom0
> = List of [ pv | pvh, shadow=<bool>, verbose=<bool>,
> - cpuid-faulting=<bool>, msr-relaxed=<bool> ]
> + cpuid-faulting=<bool>, msr-relaxed=<bool> ] (x86)
>
> - Applicability: x86
> + = List of [ sve=<integer> ] (Arm)
While in the text below you mention this is Arm64 only, I think the tag
here would better express this as well.
> @@ -838,6 +838,22 @@ Controls for how dom0 is constructed on x86 systems.
>
> If using this option is necessary to fix an issue, please report a bug.
>
> +Enables features on dom0 on Arm systems.
> +
> +* The `sve` integer parameter enables Arm SVE usage for Dom0 domain and sets
> + the maximum SVE vector length, the option is applicable only to AArch64
> + guests.
Why "guests"? Does the option affect more than Dom0?
> + A value equal to 0 disables the feature, this is the default value.
> + Values below 0 means the feature uses the maximum SVE vector length
> + supported by hardware, if SVE is supported.
> + Values above 0 explicitly set the maximum SVE vector length for Dom0,
> + allowed values are from 128 to maximum 2048, being multiple of 128.
> + Please note that when the user explicitly specifies the value, if that value
> + is above the hardware supported maximum SVE vector length, the domain
> + creation will fail and the system will stop, the same will occur if the
> + option is provided with a non zero value, but the platform doesn't support
> + SVE.
Assuming this also covers the -1 case, I wonder if that isn't a little too
strict. "Maximum supported" imo can very well be 0.
Jan
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [PATCH v7 07/12] xen: enable Dom0 to use SVE feature
2023-05-23 10:02 ` Jan Beulich
@ 2023-05-23 10:21 ` Luca Fancellu
2023-05-23 10:31 ` Jan Beulich
0 siblings, 1 reply; 49+ messages in thread
From: Luca Fancellu @ 2023-05-23 10:21 UTC (permalink / raw)
To: Jan Beulich
Cc: Bertrand Marquis, Wei Chen, Andrew Cooper, George Dunlap,
Julien Grall, Stefano Stabellini, Wei Liu, Volodymyr Babchuk,
xen-devel
> On 23 May 2023, at 11:02, Jan Beulich <jbeulich@suse.com> wrote:
>
> On 23.05.2023 09:43, Luca Fancellu wrote:
>> Add a command line parameter to allow Dom0 the use of SVE resources,
>> the command line parameter sve=<integer>, sub argument of dom0=,
>> controls the feature on this domain and sets the maximum SVE vector
>> length for Dom0.
>>
>> Add a new function, parse_signed_integer(), to parse an integer
>> command line argument.
>>
>> Signed-off-by: Luca Fancellu <luca.fancellu@arm.com>
>
> Reviewed-by: Jan Beulich <jbeulich@suse.com> # !arm
>
>> --- a/docs/misc/xen-command-line.pandoc
>> +++ b/docs/misc/xen-command-line.pandoc
>> @@ -777,9 +777,9 @@ Specify the bit width of the DMA heap.
>>
>> ### dom0
>> = List of [ pv | pvh, shadow=<bool>, verbose=<bool>,
>> - cpuid-faulting=<bool>, msr-relaxed=<bool> ]
>> + cpuid-faulting=<bool>, msr-relaxed=<bool> ] (x86)
>>
>> - Applicability: x86
>> + = List of [ sve=<integer> ] (Arm)
>
> While in the text below you mention this is Arm64 only, I think the tag
> here would better express this as well.
Ok I can use Arm64 instead if there is no opposition from others
>
>> @@ -838,6 +838,22 @@ Controls for how dom0 is constructed on x86 systems.
>>
>> If using this option is necessary to fix an issue, please report a bug.
>>
>> +Enables features on dom0 on Arm systems.
>> +
>> +* The `sve` integer parameter enables Arm SVE usage for Dom0 domain and sets
>> + the maximum SVE vector length, the option is applicable only to AArch64
>> + guests.
>
> Why "guests"? Does the option affect more than Dom0?
I used “guests” because in my mind I was referring to all the aarch64 OS that can be used
as control domain, I can change it if it sounds bad.
>
>> + A value equal to 0 disables the feature, this is the default value.
>> + Values below 0 means the feature uses the maximum SVE vector length
>> + supported by hardware, if SVE is supported.
>> + Values above 0 explicitly set the maximum SVE vector length for Dom0,
>> + allowed values are from 128 to maximum 2048, being multiple of 128.
>> + Please note that when the user explicitly specifies the value, if that value
>> + is above the hardware supported maximum SVE vector length, the domain
>> + creation will fail and the system will stop, the same will occur if the
>> + option is provided with a non zero value, but the platform doesn't support
>> + SVE.
>
> Assuming this also covers the -1 case, I wonder if that isn't a little too
> strict. "Maximum supported" imo can very well be 0.
Maximum supported, when platforms uses SVE, can be at minimum 128 by arm specs.
>
> Jan
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [PATCH v7 07/12] xen: enable Dom0 to use SVE feature
2023-05-23 10:21 ` Luca Fancellu
@ 2023-05-23 10:31 ` Jan Beulich
2023-05-23 11:50 ` Luca Fancellu
0 siblings, 1 reply; 49+ messages in thread
From: Jan Beulich @ 2023-05-23 10:31 UTC (permalink / raw)
To: Luca Fancellu
Cc: Bertrand Marquis, Wei Chen, Andrew Cooper, George Dunlap,
Julien Grall, Stefano Stabellini, Wei Liu, Volodymyr Babchuk,
xen-devel
On 23.05.2023 12:21, Luca Fancellu wrote:
>> On 23 May 2023, at 11:02, Jan Beulich <jbeulich@suse.com> wrote:
>> On 23.05.2023 09:43, Luca Fancellu wrote:
>>> @@ -838,6 +838,22 @@ Controls for how dom0 is constructed on x86 systems.
>>>
>>> If using this option is necessary to fix an issue, please report a bug.
>>>
>>> +Enables features on dom0 on Arm systems.
>>> +
>>> +* The `sve` integer parameter enables Arm SVE usage for Dom0 domain and sets
>>> + the maximum SVE vector length, the option is applicable only to AArch64
>>> + guests.
>>
>> Why "guests"? Does the option affect more than Dom0?
>
> I used “guests” because in my mind I was referring to all the aarch64 OS that can be used
> as control domain, I can change it if it sounds bad.
If you means OSes then better also say OSes. But maybe this doesn't need
specifically expressing, by saying e.g. "..., the option is applicable
only on AArch64"? Or can a Dom0 be 32-bit on Arm64 Xen?
>>> + A value equal to 0 disables the feature, this is the default value.
>>> + Values below 0 means the feature uses the maximum SVE vector length
>>> + supported by hardware, if SVE is supported.
>>> + Values above 0 explicitly set the maximum SVE vector length for Dom0,
>>> + allowed values are from 128 to maximum 2048, being multiple of 128.
>>> + Please note that when the user explicitly specifies the value, if that value
>>> + is above the hardware supported maximum SVE vector length, the domain
>>> + creation will fail and the system will stop, the same will occur if the
>>> + option is provided with a non zero value, but the platform doesn't support
>>> + SVE.
>>
>> Assuming this also covers the -1 case, I wonder if that isn't a little too
>> strict. "Maximum supported" imo can very well be 0.
>
> Maximum supported, when platforms uses SVE, can be at minimum 128 by arm specs.
When there is SVE - sure. But when there's no SVE, 0 is kind of the implied
length. And I'd view a command line option value of -1 quite okay in that
case: They've asked for the maximum supported, so they'll get 0. No reason
to crash the system during boot.
Jan
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [PATCH v7 07/12] xen: enable Dom0 to use SVE feature
2023-05-23 10:31 ` Jan Beulich
@ 2023-05-23 11:50 ` Luca Fancellu
2023-05-23 11:53 ` Jan Beulich
0 siblings, 1 reply; 49+ messages in thread
From: Luca Fancellu @ 2023-05-23 11:50 UTC (permalink / raw)
To: Jan Beulich
Cc: Bertrand Marquis, Wei Chen, Andrew Cooper, George Dunlap,
Julien Grall, Stefano Stabellini, Wei Liu, Volodymyr Babchuk,
xen-devel
> On 23 May 2023, at 11:31, Jan Beulich <jbeulich@suse.com> wrote:
>
> On 23.05.2023 12:21, Luca Fancellu wrote:
>>> On 23 May 2023, at 11:02, Jan Beulich <jbeulich@suse.com> wrote:
>>> On 23.05.2023 09:43, Luca Fancellu wrote:
>>>> @@ -838,6 +838,22 @@ Controls for how dom0 is constructed on x86 systems.
>>>>
>>>> If using this option is necessary to fix an issue, please report a bug.
>>>>
>>>> +Enables features on dom0 on Arm systems.
>>>> +
>>>> +* The `sve` integer parameter enables Arm SVE usage for Dom0 domain and sets
>>>> + the maximum SVE vector length, the option is applicable only to AArch64
>>>> + guests.
>>>
>>> Why "guests"? Does the option affect more than Dom0?
>>
>> I used “guests” because in my mind I was referring to all the aarch64 OS that can be used
>> as control domain, I can change it if it sounds bad.
>
> If you means OSes then better also say OSes. But maybe this doesn't need
> specifically expressing, by saying e.g. "..., the option is applicable
> only on AArch64"? Or can a Dom0 be 32-bit on Arm64 Xen?
I think there is no limitation so Dom0 can be 32 bit or 64. Maybe I can say
“... AArch64 kernel guests.”?
>
>>>> + A value equal to 0 disables the feature, this is the default value.
>>>> + Values below 0 means the feature uses the maximum SVE vector length
>>>> + supported by hardware, if SVE is supported.
>>>> + Values above 0 explicitly set the maximum SVE vector length for Dom0,
>>>> + allowed values are from 128 to maximum 2048, being multiple of 128.
>>>> + Please note that when the user explicitly specifies the value, if that value
>>>> + is above the hardware supported maximum SVE vector length, the domain
>>>> + creation will fail and the system will stop, the same will occur if the
>>>> + option is provided with a non zero value, but the platform doesn't support
>>>> + SVE.
>>>
>>> Assuming this also covers the -1 case, I wonder if that isn't a little too
>>> strict. "Maximum supported" imo can very well be 0.
>>
>> Maximum supported, when platforms uses SVE, can be at minimum 128 by arm specs.
>
> When there is SVE - sure. But when there's no SVE, 0 is kind of the implied
> length. And I'd view a command line option value of -1 quite okay in that
> case: They've asked for the maximum supported, so they'll get 0. No reason
> to crash the system during boot.
Ok I see what you mean, for example when Kconfig SVE is enabled, but the platform doesn’t
have SVE feature, requesting sve=-1 will keep the value to 0, and no system will be stopped.
Maybe I can say:
“... the same will occur if the option is provided with a positive non zero value,
but the platform doesn't support SVE."
>
> Jan
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [PATCH v7 07/12] xen: enable Dom0 to use SVE feature
2023-05-23 11:50 ` Luca Fancellu
@ 2023-05-23 11:53 ` Jan Beulich
2023-05-23 11:57 ` Luca Fancellu
0 siblings, 1 reply; 49+ messages in thread
From: Jan Beulich @ 2023-05-23 11:53 UTC (permalink / raw)
To: Luca Fancellu
Cc: Bertrand Marquis, Wei Chen, Andrew Cooper, George Dunlap,
Julien Grall, Stefano Stabellini, Wei Liu, Volodymyr Babchuk,
xen-devel
On 23.05.2023 13:50, Luca Fancellu wrote:
>> On 23 May 2023, at 11:31, Jan Beulich <jbeulich@suse.com> wrote:
>> On 23.05.2023 12:21, Luca Fancellu wrote:
>>>> On 23 May 2023, at 11:02, Jan Beulich <jbeulich@suse.com> wrote:
>>>> On 23.05.2023 09:43, Luca Fancellu wrote:
>>>>> @@ -838,6 +838,22 @@ Controls for how dom0 is constructed on x86 systems.
>>>>>
>>>>> If using this option is necessary to fix an issue, please report a bug.
>>>>>
>>>>> +Enables features on dom0 on Arm systems.
>>>>> +
>>>>> +* The `sve` integer parameter enables Arm SVE usage for Dom0 domain and sets
>>>>> + the maximum SVE vector length, the option is applicable only to AArch64
>>>>> + guests.
>>>>
>>>> Why "guests"? Does the option affect more than Dom0?
>>>
>>> I used “guests” because in my mind I was referring to all the aarch64 OS that can be used
>>> as control domain, I can change it if it sounds bad.
>>
>> If you means OSes then better also say OSes. But maybe this doesn't need
>> specifically expressing, by saying e.g. "..., the option is applicable
>> only on AArch64"? Or can a Dom0 be 32-bit on Arm64 Xen?
>
> I think there is no limitation so Dom0 can be 32 bit or 64. Maybe I can say
> “... AArch64 kernel guests.”?
I'd recommend to avoid the term "guest" when you talk about Dom0 alone.
Commonly "guest" means ordinary domains only, i.e. in particular excluding
Dom0. What's wrong with "AArch64 Dom0 kernels"?
>>>>> + A value equal to 0 disables the feature, this is the default value.
>>>>> + Values below 0 means the feature uses the maximum SVE vector length
>>>>> + supported by hardware, if SVE is supported.
>>>>> + Values above 0 explicitly set the maximum SVE vector length for Dom0,
>>>>> + allowed values are from 128 to maximum 2048, being multiple of 128.
>>>>> + Please note that when the user explicitly specifies the value, if that value
>>>>> + is above the hardware supported maximum SVE vector length, the domain
>>>>> + creation will fail and the system will stop, the same will occur if the
>>>>> + option is provided with a non zero value, but the platform doesn't support
>>>>> + SVE.
>>>>
>>>> Assuming this also covers the -1 case, I wonder if that isn't a little too
>>>> strict. "Maximum supported" imo can very well be 0.
>>>
>>> Maximum supported, when platforms uses SVE, can be at minimum 128 by arm specs.
>>
>> When there is SVE - sure. But when there's no SVE, 0 is kind of the implied
>> length. And I'd view a command line option value of -1 quite okay in that
>> case: They've asked for the maximum supported, so they'll get 0. No reason
>> to crash the system during boot.
>
> Ok I see what you mean, for example when Kconfig SVE is enabled, but the platform doesn’t
> have SVE feature, requesting sve=-1 will keep the value to 0, and no system will be stopped.
>
> Maybe I can say:
>
> “... the same will occur if the option is provided with a positive non zero value,
> but the platform doesn't support SVE."
Right, provided that matches the implementation.
Jan
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [PATCH v7 07/12] xen: enable Dom0 to use SVE feature
2023-05-23 11:53 ` Jan Beulich
@ 2023-05-23 11:57 ` Luca Fancellu
2023-05-23 12:40 ` Jan Beulich
0 siblings, 1 reply; 49+ messages in thread
From: Luca Fancellu @ 2023-05-23 11:57 UTC (permalink / raw)
To: Jan Beulich
Cc: Bertrand Marquis, Wei Chen, Andrew Cooper, George Dunlap,
Julien Grall, Stefano Stabellini, Wei Liu, Volodymyr Babchuk,
xen-devel
> On 23 May 2023, at 12:53, Jan Beulich <jbeulich@suse.com> wrote:
>
> On 23.05.2023 13:50, Luca Fancellu wrote:
>>> On 23 May 2023, at 11:31, Jan Beulich <jbeulich@suse.com> wrote:
>>> On 23.05.2023 12:21, Luca Fancellu wrote:
>>>>> On 23 May 2023, at 11:02, Jan Beulich <jbeulich@suse.com> wrote:
>>>>> On 23.05.2023 09:43, Luca Fancellu wrote:
>>>>>> @@ -838,6 +838,22 @@ Controls for how dom0 is constructed on x86 systems.
>>>>>>
>>>>>> If using this option is necessary to fix an issue, please report a bug.
>>>>>>
>>>>>> +Enables features on dom0 on Arm systems.
>>>>>> +
>>>>>> +* The `sve` integer parameter enables Arm SVE usage for Dom0 domain and sets
>>>>>> + the maximum SVE vector length, the option is applicable only to AArch64
>>>>>> + guests.
>>>>>
>>>>> Why "guests"? Does the option affect more than Dom0?
>>>>
>>>> I used “guests” because in my mind I was referring to all the aarch64 OS that can be used
>>>> as control domain, I can change it if it sounds bad.
>>>
>>> If you means OSes then better also say OSes. But maybe this doesn't need
>>> specifically expressing, by saying e.g. "..., the option is applicable
>>> only on AArch64"? Or can a Dom0 be 32-bit on Arm64 Xen?
>>
>> I think there is no limitation so Dom0 can be 32 bit or 64. Maybe I can say
>> “... AArch64 kernel guests.”?
>
> I'd recommend to avoid the term "guest" when you talk about Dom0 alone.
> Commonly "guest" means ordinary domains only, i.e. in particular excluding
> Dom0. What's wrong with "AArch64 Dom0 kernels"?
Ok works for me, I will use “AArch64 Dom0 kernels", I thought “guests” were a generic category
and then we have “privileged guests”, for example Dom0 or driver domain, and “unprivileged guests”
like DomUs.
>
>>>>>> + A value equal to 0 disables the feature, this is the default value.
>>>>>> + Values below 0 means the feature uses the maximum SVE vector length
>>>>>> + supported by hardware, if SVE is supported.
>>>>>> + Values above 0 explicitly set the maximum SVE vector length for Dom0,
>>>>>> + allowed values are from 128 to maximum 2048, being multiple of 128.
>>>>>> + Please note that when the user explicitly specifies the value, if that value
>>>>>> + is above the hardware supported maximum SVE vector length, the domain
>>>>>> + creation will fail and the system will stop, the same will occur if the
>>>>>> + option is provided with a non zero value, but the platform doesn't support
>>>>>> + SVE.
>>>>>
>>>>> Assuming this also covers the -1 case, I wonder if that isn't a little too
>>>>> strict. "Maximum supported" imo can very well be 0.
>>>>
>>>> Maximum supported, when platforms uses SVE, can be at minimum 128 by arm specs.
>>>
>>> When there is SVE - sure. But when there's no SVE, 0 is kind of the implied
>>> length. And I'd view a command line option value of -1 quite okay in that
>>> case: They've asked for the maximum supported, so they'll get 0. No reason
>>> to crash the system during boot.
>>
>> Ok I see what you mean, for example when Kconfig SVE is enabled, but the platform doesn’t
>> have SVE feature, requesting sve=-1 will keep the value to 0, and no system will be stopped.
>>
>> Maybe I can say:
>>
>> “... the same will occur if the option is provided with a positive non zero value,
>> but the platform doesn't support SVE."
>
> Right, provided that matches the implementation.
Ok I will do the changes, can I retain your R-by? I suppose it covers also documentation right?
>
> Jan
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [PATCH v7 07/12] xen: enable Dom0 to use SVE feature
2023-05-23 11:57 ` Luca Fancellu
@ 2023-05-23 12:40 ` Jan Beulich
0 siblings, 0 replies; 49+ messages in thread
From: Jan Beulich @ 2023-05-23 12:40 UTC (permalink / raw)
To: Luca Fancellu
Cc: Bertrand Marquis, Wei Chen, Andrew Cooper, George Dunlap,
Julien Grall, Stefano Stabellini, Wei Liu, Volodymyr Babchuk,
xen-devel
On 23.05.2023 13:57, Luca Fancellu wrote:
>> On 23 May 2023, at 12:53, Jan Beulich <jbeulich@suse.com> wrote:
>> On 23.05.2023 13:50, Luca Fancellu wrote:
>>>> On 23 May 2023, at 11:31, Jan Beulich <jbeulich@suse.com> wrote:
>>>> On 23.05.2023 12:21, Luca Fancellu wrote:
>>>>>> On 23 May 2023, at 11:02, Jan Beulich <jbeulich@suse.com> wrote:
>>>>>> On 23.05.2023 09:43, Luca Fancellu wrote:
>>>>>>> @@ -838,6 +838,22 @@ Controls for how dom0 is constructed on x86 systems.
>>>>>>>
>>>>>>> If using this option is necessary to fix an issue, please report a bug.
>>>>>>>
>>>>>>> +Enables features on dom0 on Arm systems.
>>>>>>> +
>>>>>>> +* The `sve` integer parameter enables Arm SVE usage for Dom0 domain and sets
>>>>>>> + the maximum SVE vector length, the option is applicable only to AArch64
>>>>>>> + guests.
>>>>>>
>>>>>> Why "guests"? Does the option affect more than Dom0?
>>>>>
>>>>> I used “guests” because in my mind I was referring to all the aarch64 OS that can be used
>>>>> as control domain, I can change it if it sounds bad.
>>>>
>>>> If you means OSes then better also say OSes. But maybe this doesn't need
>>>> specifically expressing, by saying e.g. "..., the option is applicable
>>>> only on AArch64"? Or can a Dom0 be 32-bit on Arm64 Xen?
>>>
>>> I think there is no limitation so Dom0 can be 32 bit or 64. Maybe I can say
>>> “... AArch64 kernel guests.”?
>>
>> I'd recommend to avoid the term "guest" when you talk about Dom0 alone.
>> Commonly "guest" means ordinary domains only, i.e. in particular excluding
>> Dom0. What's wrong with "AArch64 Dom0 kernels"?
>
> Ok works for me, I will use “AArch64 Dom0 kernels", I thought “guests” were a generic category
> and then we have “privileged guests”, for example Dom0 or driver domain, and “unprivileged guests”
> like DomUs.
Well, yes - "commonly" doesn't mean "always".
>>>>>>> + A value equal to 0 disables the feature, this is the default value.
>>>>>>> + Values below 0 means the feature uses the maximum SVE vector length
>>>>>>> + supported by hardware, if SVE is supported.
>>>>>>> + Values above 0 explicitly set the maximum SVE vector length for Dom0,
>>>>>>> + allowed values are from 128 to maximum 2048, being multiple of 128.
>>>>>>> + Please note that when the user explicitly specifies the value, if that value
>>>>>>> + is above the hardware supported maximum SVE vector length, the domain
>>>>>>> + creation will fail and the system will stop, the same will occur if the
>>>>>>> + option is provided with a non zero value, but the platform doesn't support
>>>>>>> + SVE.
>>>>>>
>>>>>> Assuming this also covers the -1 case, I wonder if that isn't a little too
>>>>>> strict. "Maximum supported" imo can very well be 0.
>>>>>
>>>>> Maximum supported, when platforms uses SVE, can be at minimum 128 by arm specs.
>>>>
>>>> When there is SVE - sure. But when there's no SVE, 0 is kind of the implied
>>>> length. And I'd view a command line option value of -1 quite okay in that
>>>> case: They've asked for the maximum supported, so they'll get 0. No reason
>>>> to crash the system during boot.
>>>
>>> Ok I see what you mean, for example when Kconfig SVE is enabled, but the platform doesn’t
>>> have SVE feature, requesting sve=-1 will keep the value to 0, and no system will be stopped.
>>>
>>> Maybe I can say:
>>>
>>> “... the same will occur if the option is provided with a positive non zero value,
>>> but the platform doesn't support SVE."
>>
>> Right, provided that matches the implementation.
>
> Ok I will do the changes, can I retain your R-by? I suppose it covers also documentation right?
I guess whether doc is covered is fuzzy. Since the doc part is Arm-
specific, I'd probably consider it not covered with the "!arm" that
I appended. But whichever way you look at it, you can keep the tag
in place.
Jan
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [PATCH v7 10/12] xen/tools: add sve parameter in XL configuration
2023-05-23 7:43 ` [PATCH v7 10/12] xen/tools: add sve parameter in XL configuration Luca Fancellu
@ 2023-05-23 16:49 ` Anthony PERARD
0 siblings, 0 replies; 49+ messages in thread
From: Anthony PERARD @ 2023-05-23 16:49 UTC (permalink / raw)
To: Luca Fancellu
Cc: xen-devel, bertrand.marquis, wei.chen, Wei Liu, George Dunlap,
Nick Rosbrook, Juergen Gross
On Tue, May 23, 2023 at 08:43:24AM +0100, Luca Fancellu wrote:
> Add sve parameter in XL configuration to allow guests to use
> SVE feature.
>
> Signed-off-by: Luca Fancellu <luca.fancellu@arm.com>
Reviewed-by: Anthony PERARD <anthony.perard@citrix.com>
Thanks,
--
Anthony PERARD
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [PATCH v7 01/12] xen/arm: enable SVE extension for Xen
2023-05-23 7:43 ` [PATCH v7 01/12] xen/arm: enable SVE extension for Xen Luca Fancellu
@ 2023-05-24 9:01 ` Bertrand Marquis
2023-05-24 9:58 ` Julien Grall
2023-05-25 8:57 ` Julien Grall
2023-05-25 8:58 ` Julien Grall
2 siblings, 1 reply; 49+ messages in thread
From: Bertrand Marquis @ 2023-05-24 9:01 UTC (permalink / raw)
To: Luca Fancellu
Cc: Xen-devel, Wei Chen, Stefano Stabellini, Julien Grall, Volodymyr Babchuk
Hi Luca,
> On 23 May 2023, at 09:43, Luca Fancellu <Luca.Fancellu@arm.com> wrote:
>
> Enable Xen to handle the SVE extension, add code in cpufeature module
> to handle ZCR SVE register, disable trapping SVE feature on system
> boot only when SVE resources are accessed.
> While there, correct coding style for the comment on coprocessor
> trapping.
>
> Now cptr_el2 is part of the domain context and it will be restored
> on context switch, this is a preparation for saving the SVE context
> which will be part of VFP operations, so restore it before the call
> to save VFP registers.
> To save an additional isb barrier, restore cptr_el2 before an
> existing isb barrier and move the call for saving VFP context after
> that barrier. To keep a (mostly) specularity of ctxt_switch_to()
> and ctxt_switch_from(), move vfp_save_state() up in the function.
>
> Change the KConfig entry to make ARM64_SVE symbol selectable, by
> default it will be not selected.
>
> Create sve module and sve_asm.S that contains assembly routines for
> the SVE feature, this code is inspired from linux and it uses
> instruction encoding to be compatible with compilers that does not
> support SVE, imported instructions are documented in
> README.LinuxPrimitives.
>
> Signed-off-by: Luca Fancellu <luca.fancellu@arm.com>
Reviewed-by: Bertrand Marquis <bertrand.marquis@arm.com>
with one minor NIT that could be fixed on commit...
> ---
> Changes from v6:
> - modified licence, add emacs block, move vfp_save_state up in the
> function, add comments to CPTR_EL2 and vfp_restore_state, don't
> use variable in init_traps(), code style fixes,
> add entries to README.LinuxPrimitives (Julien)
> - vl_to_zcr is moved into sve.c module as changes to the series led
> to its usage only inside it, remove stub for compute_max_zcr and
> rely on compiler DCE.
> Changes from v5:
> - Add R-by Bertrand
> Changes from v4:
> - don't use fixed types in vl_to_zcr, forgot to address that in
> v3, by mistake I changed that in patch 2, fixing now (Jan)
> Changes from v3:
> - no changes
> Changes from v2:
> - renamed sve_asm.S in sve-asm.S, new files should not contain
> underscore in the name (Jan)
> Changes from v1:
> - Add assert to vl_to_zcr, it is never called with vl==0, but just
> to be sure it won't in the future.
> Changes from RFC:
> - Moved restoring of cptr before an existing barrier (Julien)
> - Marked the feature as unsupported for now (Julien)
> - Trap and un-trap only when using SVE resources in
> compute_max_zcr() (Julien)
> ---
> xen/arch/arm/Kconfig | 10 ++--
> xen/arch/arm/README.LinuxPrimitives | 9 ++++
> xen/arch/arm/arm64/Makefile | 1 +
> xen/arch/arm/arm64/cpufeature.c | 7 ++-
> xen/arch/arm/arm64/sve-asm.S | 48 +++++++++++++++++++
> xen/arch/arm/arm64/sve.c | 59 ++++++++++++++++++++++++
> xen/arch/arm/cpufeature.c | 6 ++-
> xen/arch/arm/domain.c | 20 +++++---
> xen/arch/arm/include/asm/arm64/sve.h | 27 +++++++++++
> xen/arch/arm/include/asm/arm64/sysregs.h | 1 +
> xen/arch/arm/include/asm/cpufeature.h | 14 ++++++
> xen/arch/arm/include/asm/domain.h | 1 +
> xen/arch/arm/include/asm/processor.h | 2 +
> xen/arch/arm/setup.c | 5 +-
> xen/arch/arm/traps.c | 27 ++++++-----
> 15 files changed, 210 insertions(+), 27 deletions(-)
> create mode 100644 xen/arch/arm/arm64/sve-asm.S
> create mode 100644 xen/arch/arm/arm64/sve.c
> create mode 100644 xen/arch/arm/include/asm/arm64/sve.h
>
> diff --git a/xen/arch/arm/Kconfig b/xen/arch/arm/Kconfig
> index 239d3aed3c7f..41f45d8d1203 100644
> --- a/xen/arch/arm/Kconfig
> +++ b/xen/arch/arm/Kconfig
> @@ -112,11 +112,15 @@ config ARM64_PTR_AUTH
> This feature is not supported in Xen.
>
> config ARM64_SVE
> - def_bool n
> + bool "Enable Scalar Vector Extension support (UNSUPPORTED)" if UNSUPPORTED
> depends on ARM_64
> help
> - Scalar Vector Extension support.
> - This feature is not supported in Xen.
> + Scalar Vector Extension (SVE/SVE2) support for guests.
> +
> + Please be aware that currently, enabling this feature will add latency on
> + VM context switch between SVE enabled guests, between not-enabled SVE
> + guests and SVE enabled guests and viceversa, compared to the time
> + required to switch between not-enabled SVE guests.
>
> config ARM64_MTE
> def_bool n
> diff --git a/xen/arch/arm/README.LinuxPrimitives b/xen/arch/arm/README.LinuxPrimitives
> index 1d53e6a898da..76c8df29e416 100644
> --- a/xen/arch/arm/README.LinuxPrimitives
> +++ b/xen/arch/arm/README.LinuxPrimitives
> @@ -62,6 +62,15 @@ done
> linux/arch/arm64/lib/clear_page.S xen/arch/arm/arm64/lib/clear_page.S
> linux/arch/arm64/lib/copy_page.S unused in Xen
>
> +---------------------------------------------------------------------
> +
> +SVE assembly macro: last sync @ v6.3.0 (last commit: 457391b03803)
> +
> +linux/arch/arm64/include/asm/fpsimdmacros.h xen/arch/arm/include/asm/arm64/sve-asm.S
> +
> +The following macros were taken from Linux:
> + _check_general_reg, _check_num, _sve_rdvl
> +
> =====================================================================
> arm32
> =====================================================================
> diff --git a/xen/arch/arm/arm64/Makefile b/xen/arch/arm/arm64/Makefile
> index 28481393e98f..54ad55c75cda 100644
> --- a/xen/arch/arm/arm64/Makefile
> +++ b/xen/arch/arm/arm64/Makefile
> @@ -13,6 +13,7 @@ obj-$(CONFIG_LIVEPATCH) += livepatch.o
> obj-y += mm.o
> obj-y += smc.o
> obj-y += smpboot.o
> +obj-$(CONFIG_ARM64_SVE) += sve.o sve-asm.o
> obj-y += traps.o
> obj-y += vfp.o
> obj-y += vsysreg.o
> diff --git a/xen/arch/arm/arm64/cpufeature.c b/xen/arch/arm/arm64/cpufeature.c
> index d9039d37b2d1..b4656ff4d80f 100644
> --- a/xen/arch/arm/arm64/cpufeature.c
> +++ b/xen/arch/arm/arm64/cpufeature.c
> @@ -455,15 +455,11 @@ static const struct arm64_ftr_bits ftr_id_dfr1[] = {
> ARM64_FTR_END,
> };
>
> -#if 0
> -/* TODO: use this to sanitize SVE once we support it */
> -
> static const struct arm64_ftr_bits ftr_zcr[] = {
> ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE,
> ZCR_ELx_LEN_SHIFT, ZCR_ELx_LEN_SIZE, 0), /* LEN */
> ARM64_FTR_END,
> };
> -#endif
>
> /*
> * Common ftr bits for a 32bit register with all hidden, strict
> @@ -603,6 +599,9 @@ void update_system_features(const struct cpuinfo_arm *new)
>
> SANITIZE_ID_REG(zfr64, 0, aa64zfr0);
>
> + if ( cpu_has_sve )
> + SANITIZE_REG(zcr64, 0, zcr);
> +
> /*
> * Comment from Linux:
> * Userspace may perform DC ZVA instructions. Mismatched block sizes
> diff --git a/xen/arch/arm/arm64/sve-asm.S b/xen/arch/arm/arm64/sve-asm.S
> new file mode 100644
> index 000000000000..4d1549344733
> --- /dev/null
> +++ b/xen/arch/arm/arm64/sve-asm.S
> @@ -0,0 +1,48 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +/*
> + * Arm SVE assembly routines
> + *
> + * Copyright (C) 2022 ARM Ltd.
> + *
> + * Some macros and instruction encoding in this file are taken from linux 6.1.1,
> + * file arch/arm64/include/asm/fpsimdmacros.h, some of them are a modified
> + * version.
> + */
> +
> +/* Sanity-check macros to help avoid encoding garbage instructions */
> +
> +.macro _check_general_reg nr
> + .if (\nr) < 0 || (\nr) > 30
> + .error "Bad register number \nr."
> + .endif
> +.endm
> +
> +.macro _check_num n, min, max
> + .if (\n) < (\min) || (\n) > (\max)
> + .error "Number \n out of range [\min,\max]"
> + .endif
> +.endm
> +
> +/* SVE instruction encodings for non-SVE-capable assemblers */
> +/* (pre binutils 2.28, all kernel capable clang versions support SVE) */
> +
> +/* RDVL X\nx, #\imm */
> +.macro _sve_rdvl nx, imm
> + _check_general_reg \nx
> + _check_num (\imm), -0x20, 0x1f
> + .inst 0x04bf5000 \
> + | (\nx) \
> + | (((\imm) & 0x3f) << 5)
> +.endm
> +
> +/* Gets the current vector register size in bytes */
> +GLOBAL(sve_get_hw_vl)
> + _sve_rdvl 0, 1
> + ret
> +
> +/*
> + * Local variables:
> + * mode: ASM
> + * indent-tabs-mode: nil
> + * End:
> + */
> diff --git a/xen/arch/arm/arm64/sve.c b/xen/arch/arm/arm64/sve.c
> new file mode 100644
> index 000000000000..e05ccc38a896
> --- /dev/null
> +++ b/xen/arch/arm/arm64/sve.c
> @@ -0,0 +1,59 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +/*
> + * Arm SVE feature code
> + *
> + * Copyright (C) 2022 ARM Ltd.
> + */
> +
> +#include <xen/types.h>
> +#include <asm/arm64/sve.h>
> +#include <asm/arm64/sysregs.h>
> +#include <asm/processor.h>
> +#include <asm/system.h>
> +
> +extern unsigned int sve_get_hw_vl(void);
> +
> +/* Takes a vector length in bits and returns the ZCR_ELx encoding */
> +static inline register_t vl_to_zcr(unsigned int vl)
> +{
> + ASSERT(vl > 0);
> + return ((vl / SVE_VL_MULTIPLE_VAL) - 1U) & ZCR_ELx_LEN_MASK;
> +}
> +
> +register_t compute_max_zcr(void)
> +{
> + register_t cptr_bits = get_default_cptr_flags();
> + register_t zcr = vl_to_zcr(SVE_VL_MAX_BITS);
> + unsigned int hw_vl;
> +
> + /* Remove trap for SVE resources */
> + WRITE_SYSREG(cptr_bits & ~HCPTR_CP(8), CPTR_EL2);
> + isb();
> +
> + /*
> + * Set the maximum SVE vector length, doing that we will know the VL
> + * supported by the platform, calling sve_get_hw_vl()
> + */
> + WRITE_SYSREG(zcr, ZCR_EL2);
> +
> + /*
> + * Read the maximum VL, which could be lower than what we imposed before,
> + * hw_vl contains VL in bytes, multiply it by 8 to use vl_to_zcr() later
> + */
> + hw_vl = sve_get_hw_vl() * 8U;
> +
> + /* Restore CPTR_EL2 */
> + WRITE_SYSREG(cptr_bits, CPTR_EL2);
> + isb();
> +
> + return vl_to_zcr(hw_vl);
> +}
> +
> +/*
> + * Local variables:
> + * mode: C
> + * c-file-style: "BSD"
> + * c-basic-offset: 4
> + * indent-tabs-mode: nil
> + * End:
> + */
> diff --git a/xen/arch/arm/cpufeature.c b/xen/arch/arm/cpufeature.c
> index c4ec38bb2554..83b84368f6d5 100644
> --- a/xen/arch/arm/cpufeature.c
> +++ b/xen/arch/arm/cpufeature.c
> @@ -9,6 +9,7 @@
> #include <xen/init.h>
> #include <xen/smp.h>
> #include <xen/stop_machine.h>
> +#include <asm/arm64/sve.h>
> #include <asm/cpufeature.h>
>
> DECLARE_BITMAP(cpu_hwcaps, ARM_NCAPS);
> @@ -143,6 +144,9 @@ void identify_cpu(struct cpuinfo_arm *c)
>
> c->zfr64.bits[0] = READ_SYSREG(ID_AA64ZFR0_EL1);
>
> + if ( cpu_has_sve )
> + c->zcr64.bits[0] = compute_max_zcr();
> +
> c->dczid.bits[0] = READ_SYSREG(DCZID_EL0);
>
> c->ctr.bits[0] = READ_SYSREG(CTR_EL0);
> @@ -199,7 +203,7 @@ static int __init create_guest_cpuinfo(void)
> guest_cpuinfo.pfr64.mpam = 0;
> guest_cpuinfo.pfr64.mpam_frac = 0;
>
> - /* Hide SVE as Xen does not support it */
> + /* Hide SVE by default to the guests */
Everything is for guests and as Jan mentioned in an other comment
this could be wrongly interpreted.
Here I would suggest to just stick to:
/* Hide SVE by default */
Cheers
Bertrand
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [PATCH v7 02/12] xen/arm: add SVE vector length field to the domain
2023-05-23 7:43 ` [PATCH v7 02/12] xen/arm: add SVE vector length field to the domain Luca Fancellu
@ 2023-05-24 9:23 ` Bertrand Marquis
2023-05-25 8:59 ` Julien Grall
1 sibling, 0 replies; 49+ messages in thread
From: Bertrand Marquis @ 2023-05-24 9:23 UTC (permalink / raw)
To: Luca Fancellu
Cc: Xen-devel, Wei Chen, Stefano Stabellini, Julien Grall, Volodymyr Babchuk
Hi Luca,
> On 23 May 2023, at 09:43, Luca Fancellu <Luca.Fancellu@arm.com> wrote:
>
> Add sve_vl field to arch_domain and xen_arch_domainconfig struct,
> to allow the domain to have an information about the SVE feature
> and the number of SVE register bits that are allowed for this
> domain.
>
> sve_vl field is the vector length in bits divided by 128, this
> allows to use less space in the structures.
>
> The field is used also to allow or forbid a domain to use SVE,
> because a value equal to zero means the guest is not allowed to
> use the feature.
>
> Check that the requested vector length is lower or equal to the
> platform supported vector length, otherwise fail on domain
> creation.
>
> Check that only 64 bit domains have SVE enabled, otherwise fail.
>
> Signed-off-by: Luca Fancellu <luca.fancellu@arm.com>
Reviewed-by: Bertrand Marquis <bertrand.marquis@arm.com>
Cheers
Bertrand
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [PATCH v7 03/12] xen/arm: Expose SVE feature to the guest
2023-05-23 7:43 ` [PATCH v7 03/12] xen/arm: Expose SVE feature to the guest Luca Fancellu
@ 2023-05-24 9:25 ` Bertrand Marquis
0 siblings, 0 replies; 49+ messages in thread
From: Bertrand Marquis @ 2023-05-24 9:25 UTC (permalink / raw)
To: Luca Fancellu
Cc: Xen-devel, Wei Chen, Stefano Stabellini, Julien Grall,
Volodymyr Babchuk, Julien Grall
Hi Luca,
> On 23 May 2023, at 09:43, Luca Fancellu <Luca.Fancellu@arm.com> wrote:
>
> When a guest is allowed to use SVE, expose the SVE features through
> the identification registers.
>
> Signed-off-by: Luca Fancellu <luca.fancellu@arm.com>
> Acked-by: Julien Grall <jgrall@amazon.com>
Reviewed-by: Bertrand Marquis <bertrand.marquis@arm.com>
Cheers
Bertrand
> ---
> Changes from v6:
> - code style fix, add A-by Julien
> Changes from v5:
> - given the move of is_sve_domain() in asm/arm64/sve.h, add the
> header to vsysreg.c
> - dropping Bertrand's R-by because of the change
> Changes from v4:
> - no changes
> Changes from v3:
> - no changes
> Changes from v2:
> - no changes
> Changes from v1:
> - No changes
> Changes from RFC:
> - No changes
> ---
> xen/arch/arm/arm64/vsysreg.c | 41 ++++++++++++++++++++++++++++++++++--
> 1 file changed, 39 insertions(+), 2 deletions(-)
>
> diff --git a/xen/arch/arm/arm64/vsysreg.c b/xen/arch/arm/arm64/vsysreg.c
> index 758750983c11..fe31f7b3827f 100644
> --- a/xen/arch/arm/arm64/vsysreg.c
> +++ b/xen/arch/arm/arm64/vsysreg.c
> @@ -18,6 +18,8 @@
>
> #include <xen/sched.h>
>
> +#include <asm/arm64/cpufeature.h>
> +#include <asm/arm64/sve.h>
> #include <asm/current.h>
> #include <asm/regs.h>
> #include <asm/traps.h>
> @@ -295,7 +297,28 @@ void do_sysreg(struct cpu_user_regs *regs,
> GENERATE_TID3_INFO(MVFR0_EL1, mvfr, 0)
> GENERATE_TID3_INFO(MVFR1_EL1, mvfr, 1)
> GENERATE_TID3_INFO(MVFR2_EL1, mvfr, 2)
> - GENERATE_TID3_INFO(ID_AA64PFR0_EL1, pfr64, 0)
> +
> + case HSR_SYSREG_ID_AA64PFR0_EL1:
> + {
> + register_t guest_reg_value = guest_cpuinfo.pfr64.bits[0];
> +
> + if ( is_sve_domain(v->domain) )
> + {
> + /* 4 is the SVE field width in id_aa64pfr0_el1 */
> + uint64_t mask = GENMASK(ID_AA64PFR0_SVE_SHIFT + 4 - 1,
> + ID_AA64PFR0_SVE_SHIFT);
> + /* sysval is the sve field on the system */
> + uint64_t sysval = cpuid_feature_extract_unsigned_field_width(
> + system_cpuinfo.pfr64.bits[0],
> + ID_AA64PFR0_SVE_SHIFT, 4);
> + guest_reg_value &= ~mask;
> + guest_reg_value |= (sysval << ID_AA64PFR0_SVE_SHIFT) & mask;
> + }
> +
> + return handle_ro_read_val(regs, regidx, hsr.sysreg.read, hsr, 1,
> + guest_reg_value);
> + }
> +
> GENERATE_TID3_INFO(ID_AA64PFR1_EL1, pfr64, 1)
> GENERATE_TID3_INFO(ID_AA64DFR0_EL1, dbg64, 0)
> GENERATE_TID3_INFO(ID_AA64DFR1_EL1, dbg64, 1)
> @@ -306,7 +329,21 @@ void do_sysreg(struct cpu_user_regs *regs,
> GENERATE_TID3_INFO(ID_AA64MMFR2_EL1, mm64, 2)
> GENERATE_TID3_INFO(ID_AA64AFR0_EL1, aux64, 0)
> GENERATE_TID3_INFO(ID_AA64AFR1_EL1, aux64, 1)
> - GENERATE_TID3_INFO(ID_AA64ZFR0_EL1, zfr64, 0)
> +
> + case HSR_SYSREG_ID_AA64ZFR0_EL1:
> + {
> + /*
> + * When the guest has the SVE feature enabled, the whole id_aa64zfr0_el1
> + * needs to be exposed.
> + */
> + register_t guest_reg_value = guest_cpuinfo.zfr64.bits[0];
> +
> + if ( is_sve_domain(v->domain) )
> + guest_reg_value = system_cpuinfo.zfr64.bits[0];
> +
> + return handle_ro_read_val(regs, regidx, hsr.sysreg.read, hsr, 1,
> + guest_reg_value);
> + }
>
> /*
> * Those cases are catching all Reserved registers trapped by TID3 which
> --
> 2.34.1
>
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [PATCH v7 05/12] arm/sve: save/restore SVE context switch
2023-05-23 7:43 ` [PATCH v7 05/12] arm/sve: save/restore SVE context switch Luca Fancellu
@ 2023-05-24 9:47 ` Bertrand Marquis
2023-05-24 9:55 ` Luca Fancellu
2023-05-25 9:09 ` Julien Grall
1 sibling, 1 reply; 49+ messages in thread
From: Bertrand Marquis @ 2023-05-24 9:47 UTC (permalink / raw)
To: Luca Fancellu
Cc: Xen-devel, Wei Chen, Stefano Stabellini, Julien Grall, Volodymyr Babchuk
Hi Luca,
> On 23 May 2023, at 09:43, Luca Fancellu <Luca.Fancellu@arm.com> wrote:
>
> Save/restore context switch for SVE, allocate memory to contain
> the Z0-31 registers whose length is maximum 2048 bits each and
> FFR who can be maximum 256 bits, the allocated memory depends on
> how many bits is the vector length for the domain and how many bits
> are supported by the platform.
>
> Save P0-15 whose length is maximum 256 bits each, in this case the
> memory used is from the fpregs field in struct vfp_state,
> because V0-31 are part of Z0-31 and this space would have been
> unused for SVE domain otherwise.
>
> Create zcr_el{1,2} fields in arch_vcpu, initialise zcr_el2 on vcpu
> creation given the requested vector length and restore it on
> context switch, save/restore ZCR_EL1 value as well.
>
> List import macros from Linux in README.LinuxPrimitives.
>
> Signed-off-by: Luca Fancellu <luca.fancellu@arm.com>
Reviewed-by: Bertrand Marquis <bertrand.marquis@arm.com>
Just ...
> ---
> Changes from v6:
> - Add comment for explain why sve_save/sve_load are different from
> Linux, add macros in xen/arch/arm/README.LinuxPrimitives (Julien)
> - Add comments in sve_context_init and sve_context_free, handle the
> case where sve_zreg_ctx_end is NULL, move setting of v->arch.zcr_el2
> in sve_context_init (Julien)
> - remove stubs for sve_context_* and sve_save_* and rely on compiler
> DCE (Jan)
> - Add comments for sve_save_ctx/sve_load_ctx (Julien)
> Changes from v5:
> - use XFREE instead of xfree, keep the headers (Julien)
> - Avoid math computation for every save/restore, store the computation
> in struct vfp_state once (Bertrand)
> - protect access to v->domain->arch.sve_vl inside arch_vcpu_create now
> that sve_vl is available only on arm64
> Changes from v4:
> - No changes
> Changes from v3:
> - don't use fixed len types when not needed (Jan)
> - now VL is an encoded value, decode it before using.
> Changes from v2:
> - No changes
> Changes from v1:
> - No changes
> Changes from RFC:
> - Moved zcr_el2 field introduction in this patch, restore its
> content inside sve_restore_state function. (Julien)
>
> fix patch 5
>
> Signed-off-by: Luca Fancellu <luca.fancellu@arm.com>
> Change-Id: Ief65b2ff14fd579afa4fd110ce08a19980e64fa9
You have a signed off and a change-id that should not be here.
They are in the comment section so should be removed during push so might be ok :-)
Cheers
Bertrand
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [PATCH v7 05/12] arm/sve: save/restore SVE context switch
2023-05-24 9:47 ` Bertrand Marquis
@ 2023-05-24 9:55 ` Luca Fancellu
0 siblings, 0 replies; 49+ messages in thread
From: Luca Fancellu @ 2023-05-24 9:55 UTC (permalink / raw)
To: Bertrand Marquis
Cc: Xen-devel, Wei Chen, Stefano Stabellini, Julien Grall, Volodymyr Babchuk
> On 24 May 2023, at 10:47, Bertrand Marquis <Bertrand.Marquis@arm.com> wrote:
>
> Hi Luca,
>
>> On 23 May 2023, at 09:43, Luca Fancellu <Luca.Fancellu@arm.com> wrote:
>>
>> Save/restore context switch for SVE, allocate memory to contain
>> the Z0-31 registers whose length is maximum 2048 bits each and
>> FFR who can be maximum 256 bits, the allocated memory depends on
>> how many bits is the vector length for the domain and how many bits
>> are supported by the platform.
>>
>> Save P0-15 whose length is maximum 256 bits each, in this case the
>> memory used is from the fpregs field in struct vfp_state,
>> because V0-31 are part of Z0-31 and this space would have been
>> unused for SVE domain otherwise.
>>
>> Create zcr_el{1,2} fields in arch_vcpu, initialise zcr_el2 on vcpu
>> creation given the requested vector length and restore it on
>> context switch, save/restore ZCR_EL1 value as well.
>>
>> List import macros from Linux in README.LinuxPrimitives.
>>
>> Signed-off-by: Luca Fancellu <luca.fancellu@arm.com>
> Reviewed-by: Bertrand Marquis <bertrand.marquis@arm.com>
>
> Just ...
>
>> ---
>> Changes from v6:
>> - Add comment for explain why sve_save/sve_load are different from
>> Linux, add macros in xen/arch/arm/README.LinuxPrimitives (Julien)
>> - Add comments in sve_context_init and sve_context_free, handle the
>> case where sve_zreg_ctx_end is NULL, move setting of v->arch.zcr_el2
>> in sve_context_init (Julien)
>> - remove stubs for sve_context_* and sve_save_* and rely on compiler
>> DCE (Jan)
>> - Add comments for sve_save_ctx/sve_load_ctx (Julien)
>> Changes from v5:
>> - use XFREE instead of xfree, keep the headers (Julien)
>> - Avoid math computation for every save/restore, store the computation
>> in struct vfp_state once (Bertrand)
>> - protect access to v->domain->arch.sve_vl inside arch_vcpu_create now
>> that sve_vl is available only on arm64
>> Changes from v4:
>> - No changes
>> Changes from v3:
>> - don't use fixed len types when not needed (Jan)
>> - now VL is an encoded value, decode it before using.
>> Changes from v2:
>> - No changes
>> Changes from v1:
>> - No changes
>> Changes from RFC:
>> - Moved zcr_el2 field introduction in this patch, restore its
>> content inside sve_restore_state function. (Julien)
>>
>> fix patch 5
>>
>> Signed-off-by: Luca Fancellu <luca.fancellu@arm.com>
>> Change-Id: Ief65b2ff14fd579afa4fd110ce08a19980e64fa9
>
> You have a signed off and a change-id that should not be here.
> They are in the comment section so should be removed during push so might be ok :-)
Ohh yeah I missed that, probably it’s from a squash!
>
> Cheers
> Bertrand
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [PATCH v7 01/12] xen/arm: enable SVE extension for Xen
2023-05-24 9:01 ` Bertrand Marquis
@ 2023-05-24 9:58 ` Julien Grall
2023-05-24 14:30 ` Bertrand Marquis
0 siblings, 1 reply; 49+ messages in thread
From: Julien Grall @ 2023-05-24 9:58 UTC (permalink / raw)
To: Bertrand Marquis, Luca Fancellu
Cc: Xen-devel, Wei Chen, Stefano Stabellini, Volodymyr Babchuk
Hi,
On 24/05/2023 10:01, Bertrand Marquis wrote:
>> diff --git a/xen/arch/arm/cpufeature.c b/xen/arch/arm/cpufeature.c
>> index c4ec38bb2554..83b84368f6d5 100644
>> --- a/xen/arch/arm/cpufeature.c
>> +++ b/xen/arch/arm/cpufeature.c
>> @@ -9,6 +9,7 @@
>> #include <xen/init.h>
>> #include <xen/smp.h>
>> #include <xen/stop_machine.h>
>> +#include <asm/arm64/sve.h>
>> #include <asm/cpufeature.h>
>>
>> DECLARE_BITMAP(cpu_hwcaps, ARM_NCAPS);
>> @@ -143,6 +144,9 @@ void identify_cpu(struct cpuinfo_arm *c)
>>
>> c->zfr64.bits[0] = READ_SYSREG(ID_AA64ZFR0_EL1);
>>
>> + if ( cpu_has_sve )
>> + c->zcr64.bits[0] = compute_max_zcr();
>> +
>> c->dczid.bits[0] = READ_SYSREG(DCZID_EL0);
>>
>> c->ctr.bits[0] = READ_SYSREG(CTR_EL0);
>> @@ -199,7 +203,7 @@ static int __init create_guest_cpuinfo(void)
>> guest_cpuinfo.pfr64.mpam = 0;
>> guest_cpuinfo.pfr64.mpam_frac = 0;
>>
>> - /* Hide SVE as Xen does not support it */
>> + /* Hide SVE by default to the guests */
>
> Everything is for guests and as Jan mentioned in an other comment
> this could be wrongly interpreted.
(Not directly related to this patch, so no changes expected here)
Hmmm... The name of the function/variable is confusing as well given
that the cpuinfo should also apply to dom0. Should we s/guest/domain/?
Cheers,
--
Julien Grall
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [PATCH v7 07/12] xen: enable Dom0 to use SVE feature
2023-05-23 7:43 ` [PATCH v7 07/12] xen: enable Dom0 to use SVE feature Luca Fancellu
2023-05-23 10:02 ` Jan Beulich
@ 2023-05-24 10:05 ` Bertrand Marquis
2023-05-25 9:18 ` Julien Grall
1 sibling, 1 reply; 49+ messages in thread
From: Bertrand Marquis @ 2023-05-24 10:05 UTC (permalink / raw)
To: Luca Fancellu
Cc: Xen-devel, Wei Chen, Andrew Cooper, George Dunlap, Jan Beulich,
Julien Grall, Stefano Stabellini, Wei Liu, Volodymyr Babchuk
Hi Luca,
> On 23 May 2023, at 09:43, Luca Fancellu <Luca.Fancellu@arm.com> wrote:
>
> Add a command line parameter to allow Dom0 the use of SVE resources,
> the command line parameter sve=<integer>, sub argument of dom0=,
> controls the feature on this domain and sets the maximum SVE vector
> length for Dom0.
>
> Add a new function, parse_signed_integer(), to parse an integer
> command line argument.
>
> Signed-off-by: Luca Fancellu <luca.fancellu@arm.com>
Reviewed-by: Bertrand Marquis <bertrand.marquis@arm.com>
with ...
> ---
> Changes from v6:
> - Fixed case for e==NULL in parse_signed_integer, drop parenthesis
> from if conditions, delete inline sve_domctl_vl_param and rely on
> DCE from the compiler (Jan)
> - Drop parenthesis from opt_dom0_sve (Julien)
> - Do not continue if 'sve' is in command line args but
> CONFIG_ARM64_SVE is not selected:
> https://lore.kernel.org/all/7614AE25-F59D-430A-9C3E-30B1CE0E1580@arm.com/
> Changes from v5:
> - stop the domain if VL error occurs (Julien, Bertrand)
> - update the documentation
> - Rename sve_sanitize_vl_param to sve_domctl_vl_param to
> mark the fact that we are sanitizing a parameter coming from
> the user before encoding it into sve_vl in domctl structure.
> (suggestion from Bertrand in a separate discussion)
> - update comment in parse_signed_integer, return boolean in
> sve_domctl_vl_param (Jan).
> Changes from v4:
> - Negative values as user param means max supported HW VL (Jan)
> - update documentation, make use of no_config_param(), rename
> parse_integer into parse_signed_integer and take long long *,
> also put a comment on the -2 return condition, update
> declaration comment to reflect the modifications (Jan)
> Changes from v3:
> - Don't use fixed len types when not needed (Jan)
> - renamed domainconfig_encode_vl to sve_encode_vl
> - Use a sub argument of dom0= to enable the feature (Jan)
> - Add parse_integer() function
> Changes from v2:
> - xen_domctl_createdomain field has changed into sve_vl and its
> value now is the VL / 128, create an helper function for that.
> Changes from v1:
> - No changes
> Changes from RFC:
> - Changed docs to explain that the domain won't be created if the
> requested vector length is above the supported one from the
> platform.
> ---
> docs/misc/xen-command-line.pandoc | 20 ++++++++++++++++++--
> xen/arch/arm/arm64/sve.c | 20 ++++++++++++++++++++
> xen/arch/arm/domain_build.c | 26 ++++++++++++++++++++++++++
> xen/arch/arm/include/asm/arm64/sve.h | 10 ++++++++++
> xen/common/kernel.c | 28 ++++++++++++++++++++++++++++
> xen/include/xen/lib.h | 10 ++++++++++
> 6 files changed, 112 insertions(+), 2 deletions(-)
>
> diff --git a/docs/misc/xen-command-line.pandoc b/docs/misc/xen-command-line.pandoc
> index e0b89b7d3319..47e5b4eb6199 100644
> --- a/docs/misc/xen-command-line.pandoc
> +++ b/docs/misc/xen-command-line.pandoc
> @@ -777,9 +777,9 @@ Specify the bit width of the DMA heap.
>
> ### dom0
> = List of [ pv | pvh, shadow=<bool>, verbose=<bool>,
> - cpuid-faulting=<bool>, msr-relaxed=<bool> ]
> + cpuid-faulting=<bool>, msr-relaxed=<bool> ] (x86)
>
> - Applicability: x86
> + = List of [ sve=<integer> ] (Arm)
>
> Controls for how dom0 is constructed on x86 systems.
>
> @@ -838,6 +838,22 @@ Controls for how dom0 is constructed on x86 systems.
>
> If using this option is necessary to fix an issue, please report a bug.
>
> +Enables features on dom0 on Arm systems.
> +
> +* The `sve` integer parameter enables Arm SVE usage for Dom0 domain and sets
> + the maximum SVE vector length, the option is applicable only to AArch64
> + guests.
Here i would just remove "guests", just AArch64 is enough.
I am ok if you choose to use "AArch64 Dom0 kernels"
> + A value equal to 0 disables the feature, this is the default value.
> + Values below 0 means the feature uses the maximum SVE vector length
> + supported by hardware, if SVE is supported.
> + Values above 0 explicitly set the maximum SVE vector length for Dom0,
> + allowed values are from 128 to maximum 2048, being multiple of 128.
> + Please note that when the user explicitly specifies the value, if that value
> + is above the hardware supported maximum SVE vector length, the domain
> + creation will fail and the system will stop, the same will occur if the
> + option is provided with a non zero value, but the platform doesn't support
> + SVE.
> +
I agree on the discussion with Jan here so you can keep my R-b if modified as discussed.
Cheers
Bertrand
> ### dom0-cpuid
> = List of comma separated booleans
>
> diff --git a/xen/arch/arm/arm64/sve.c b/xen/arch/arm/arm64/sve.c
> index 84a6dedc1fd7..feaca2cf647d 100644
> --- a/xen/arch/arm/arm64/sve.c
> +++ b/xen/arch/arm/arm64/sve.c
> @@ -13,6 +13,9 @@
> #include <asm/processor.h>
> #include <asm/system.h>
>
> +/* opt_dom0_sve: allow Dom0 to use SVE and set maximum vector length. */
> +int __initdata opt_dom0_sve;
> +
> extern unsigned int sve_get_hw_vl(void);
>
> /*
> @@ -152,6 +155,23 @@ void sve_restore_state(struct vcpu *v)
> sve_load_ctx(v->arch.vfp.sve_zreg_ctx_end, v->arch.vfp.fpregs, 1);
> }
>
> +bool __init sve_domctl_vl_param(int val, unsigned int *out)
> +{
> + /*
> + * Negative SVE parameter value means to use the maximum supported
> + * vector length, otherwise if a positive value is provided, check if the
> + * vector length is a multiple of 128
> + */
> + if ( val < 0 )
> + *out = get_sys_vl_len();
> + else if ( (val % SVE_VL_MULTIPLE_VAL) == 0 )
> + *out = val;
> + else
> + return false;
> +
> + return true;
> +}
> +
> /*
> * Local variables:
> * mode: C
> diff --git a/xen/arch/arm/domain_build.c b/xen/arch/arm/domain_build.c
> index f373a5024783..9202a96d9c28 100644
> --- a/xen/arch/arm/domain_build.c
> +++ b/xen/arch/arm/domain_build.c
> @@ -62,6 +62,22 @@ custom_param("dom0_mem", parse_dom0_mem);
>
> int __init parse_arch_dom0_param(const char *s, const char *e)
> {
> + long long val;
> +
> + if ( !parse_signed_integer("sve", s, e, &val) )
> + {
> +#ifdef CONFIG_ARM64_SVE
> + if ( (val >= INT_MIN) && (val <= INT_MAX) )
> + opt_dom0_sve = val;
> + else
> + printk(XENLOG_INFO "'sve=%lld' value out of range!\n", val);
> +
> + return 0;
> +#else
> + panic("'sve' property found, but CONFIG_ARM64_SVE not selected");
> +#endif
> + }
> +
> return -EINVAL;
> }
>
> @@ -4113,6 +4129,16 @@ void __init create_dom0(void)
> if ( iommu_enabled )
> dom0_cfg.flags |= XEN_DOMCTL_CDF_iommu;
>
> + if ( opt_dom0_sve )
> + {
> + unsigned int vl;
> +
> + if ( sve_domctl_vl_param(opt_dom0_sve, &vl) )
> + dom0_cfg.arch.sve_vl = sve_encode_vl(vl);
> + else
> + panic("SVE vector length error\n");
> + }
> +
> dom0 = domain_create(0, &dom0_cfg, CDF_privileged | CDF_directmap);
> if ( IS_ERR(dom0) )
> panic("Error creating domain 0 (rc = %ld)\n", PTR_ERR(dom0));
> diff --git a/xen/arch/arm/include/asm/arm64/sve.h b/xen/arch/arm/include/asm/arm64/sve.h
> index 65b46685d263..a71d6a295dcc 100644
> --- a/xen/arch/arm/include/asm/arm64/sve.h
> +++ b/xen/arch/arm/include/asm/arm64/sve.h
> @@ -21,14 +21,22 @@ static inline unsigned int sve_decode_vl(unsigned int sve_vl)
> return sve_vl * SVE_VL_MULTIPLE_VAL;
> }
>
> +static inline unsigned int sve_encode_vl(unsigned int sve_vl_bits)
> +{
> + return sve_vl_bits / SVE_VL_MULTIPLE_VAL;
> +}
> +
> register_t compute_max_zcr(void);
> int sve_context_init(struct vcpu *v);
> void sve_context_free(struct vcpu *v);
> void sve_save_state(struct vcpu *v);
> void sve_restore_state(struct vcpu *v);
> +bool sve_domctl_vl_param(int val, unsigned int *out);
>
> #ifdef CONFIG_ARM64_SVE
>
> +extern int opt_dom0_sve;
> +
> static inline bool is_sve_domain(const struct domain *d)
> {
> return d->arch.sve_vl > 0;
> @@ -38,6 +46,8 @@ unsigned int get_sys_vl_len(void);
>
> #else /* !CONFIG_ARM64_SVE */
>
> +#define opt_dom0_sve 0
> +
> static inline bool is_sve_domain(const struct domain *d)
> {
> return false;
> diff --git a/xen/common/kernel.c b/xen/common/kernel.c
> index f7b1f65f373c..7cd00a4c999a 100644
> --- a/xen/common/kernel.c
> +++ b/xen/common/kernel.c
> @@ -314,6 +314,34 @@ int parse_boolean(const char *name, const char *s, const char *e)
> return -1;
> }
>
> +int __init parse_signed_integer(const char *name, const char *s, const char *e,
> + long long *val)
> +{
> + size_t slen, nlen;
> + const char *str;
> + long long pval;
> +
> + slen = e ? ({ ASSERT(e >= s); e - s; }) : strlen(s);
> + nlen = strlen(name);
> +
> + if ( !e )
> + e = s + slen;
> +
> + /* Check that this is the name we're looking for and a value was provided */
> + if ( slen <= nlen || strncmp(s, name, nlen) || s[nlen] != '=' )
> + return -1;
> +
> + pval = simple_strtoll(&s[nlen + 1], &str, 10);
> +
> + /* Number not recognised */
> + if ( str != e )
> + return -2;
> +
> + *val = pval;
> +
> + return 0;
> +}
> +
> int cmdline_strcmp(const char *frag, const char *name)
> {
> for ( ; ; frag++, name++ )
> diff --git a/xen/include/xen/lib.h b/xen/include/xen/lib.h
> index e914ccade095..5343ee7a944a 100644
> --- a/xen/include/xen/lib.h
> +++ b/xen/include/xen/lib.h
> @@ -94,6 +94,16 @@ int parse_bool(const char *s, const char *e);
> */
> int parse_boolean(const char *name, const char *s, const char *e);
>
> +/**
> + * Given a specific name, parses a string of the form:
> + * $NAME=<integer number>
> + * returning 0 and a value in val, for a recognised integer.
> + * Returns -1 for name not found, general errors, or -2 if name is found but
> + * not recognised number.
> + */
> +int parse_signed_integer(const char *name, const char *s, const char *e,
> + long long *val);
> +
> /**
> * Very similar to strcmp(), but will declare a match if the NUL in 'name'
> * lines up with comma, colon, semicolon or equals in 'frag'. Designed for
> --
> 2.34.1
>
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [PATCH v7 01/12] xen/arm: enable SVE extension for Xen
2023-05-24 9:58 ` Julien Grall
@ 2023-05-24 14:30 ` Bertrand Marquis
0 siblings, 0 replies; 49+ messages in thread
From: Bertrand Marquis @ 2023-05-24 14:30 UTC (permalink / raw)
To: Julien Grall
Cc: Luca Fancellu, Xen-devel, Wei Chen, Stefano Stabellini,
Volodymyr Babchuk
Hi Julien,
> On 24 May 2023, at 11:58, Julien Grall <julien@xen.org> wrote:
>
> Hi,
>
> On 24/05/2023 10:01, Bertrand Marquis wrote:
>>> diff --git a/xen/arch/arm/cpufeature.c b/xen/arch/arm/cpufeature.c
>>> index c4ec38bb2554..83b84368f6d5 100644
>>> --- a/xen/arch/arm/cpufeature.c
>>> +++ b/xen/arch/arm/cpufeature.c
>>> @@ -9,6 +9,7 @@
>>> #include <xen/init.h>
>>> #include <xen/smp.h>
>>> #include <xen/stop_machine.h>
>>> +#include <asm/arm64/sve.h>
>>> #include <asm/cpufeature.h>
>>>
>>> DECLARE_BITMAP(cpu_hwcaps, ARM_NCAPS);
>>> @@ -143,6 +144,9 @@ void identify_cpu(struct cpuinfo_arm *c)
>>>
>>> c->zfr64.bits[0] = READ_SYSREG(ID_AA64ZFR0_EL1);
>>>
>>> + if ( cpu_has_sve )
>>> + c->zcr64.bits[0] = compute_max_zcr();
>>> +
>>> c->dczid.bits[0] = READ_SYSREG(DCZID_EL0);
>>>
>>> c->ctr.bits[0] = READ_SYSREG(CTR_EL0);
>>> @@ -199,7 +203,7 @@ static int __init create_guest_cpuinfo(void)
>>> guest_cpuinfo.pfr64.mpam = 0;
>>> guest_cpuinfo.pfr64.mpam_frac = 0;
>>>
>>> - /* Hide SVE as Xen does not support it */
>>> + /* Hide SVE by default to the guests */
>> Everything is for guests and as Jan mentioned in an other comment
>> this could be wrongly interpreted.
>
> (Not directly related to this patch, so no changes expected here)
>
> Hmmm... The name of the function/variable is confusing as well given that the cpuinfo should also apply to dom0. Should we s/guest/domain/?
Would make sense to do some kind of coherency check here to use domain whenever something is for dom0 or guest.
So yes that would be a good idea and I can add this to my todolist (after SVE is merged to prevent conflicts).
Cheers
Bertrand
>
> Cheers,
>
> --
> Julien Grall
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [PATCH v7 11/12] xen/arm: add sve property for dom0less domUs
2023-05-23 7:43 ` [PATCH v7 11/12] xen/arm: add sve property for dom0less domUs Luca Fancellu
@ 2023-05-24 15:20 ` Bertrand Marquis
2023-05-25 8:52 ` Michal Orzel
2023-05-25 9:30 ` Julien Grall
1 sibling, 1 reply; 49+ messages in thread
From: Bertrand Marquis @ 2023-05-24 15:20 UTC (permalink / raw)
To: Luca Fancellu
Cc: Xen-devel, Wei Chen, Stefano Stabellini, Julien Grall, Volodymyr Babchuk
Hi Luca,
> On 23 May 2023, at 09:43, Luca Fancellu <Luca.Fancellu@arm.com> wrote:
>
> Add a device tree property in the dom0less domU configuration
> to enable the guest to use SVE.
>
> Update documentation.
>
> Signed-off-by: Luca Fancellu <luca.fancellu@arm.com>
Reviewed-by: Bertrand Marquis <bertrand.marquis@arm.com>
Cheers
Bertrand
> ---
> Changes from v6:
> - Use ifdef in create_domUs and fail if 'sve' is used on systems
> with CONFIG_ARM64_SVE not selected (Bertrand, Julien, Jan)
> Changes from v5:
> - Stop the domain creation if SVE not supported or SVE VL
> errors (Julien, Bertrand)
> - now sve_sanitize_vl_param is renamed to sve_domctl_vl_param
> and returns a boolean, change the affected code.
> - Reworded documentation.
> Changes from v4:
> - Now it is possible to specify the property "sve" for dom0less
> device tree node without any value, that means the platform
> supported VL will be used.
> Changes from v3:
> - Now domainconfig_encode_vl is named sve_encode_vl
> Changes from v2:
> - xen_domctl_createdomain field name has changed into sve_vl
> and its value is the VL/128, use domainconfig_encode_vl
> to encode a plain VL in bits.
> Changes from v1:
> - No changes
> Changes from RFC:
> - Changed documentation
> ---
> docs/misc/arm/device-tree/booting.txt | 16 +++++++++++++++
> xen/arch/arm/domain_build.c | 28 +++++++++++++++++++++++++++
> 2 files changed, 44 insertions(+)
>
> diff --git a/docs/misc/arm/device-tree/booting.txt b/docs/misc/arm/device-tree/booting.txt
> index 3879340b5e0a..32a0e508c471 100644
> --- a/docs/misc/arm/device-tree/booting.txt
> +++ b/docs/misc/arm/device-tree/booting.txt
> @@ -193,6 +193,22 @@ with the following properties:
> Optional. Handle to a xen,cpupool device tree node that identifies the
> cpupool where the guest will be started at boot.
>
> +- sve
> +
> + Optional. The `sve` property enables Arm SVE usage for the domain and sets
> + the maximum SVE vector length, the option is applicable only to AArch64
> + guests.
> + A value equal to 0 disables the feature, this is the default value.
> + Specifying this property with no value, means that the SVE vector length
> + will be set equal to the maximum vector length supported by the platform.
> + Values above 0 explicitly set the maximum SVE vector length for the domain,
> + allowed values are from 128 to maximum 2048, being multiple of 128.
> + Please note that when the user explicitly specifies the value, if that value
> + is above the hardware supported maximum SVE vector length, the domain
> + creation will fail and the system will stop, the same will occur if the
> + option is provided with a non zero value, but the platform doesn't support
> + SVE.
> +
> - xen,enhanced
>
> A string property. Possible property values are:
> diff --git a/xen/arch/arm/domain_build.c b/xen/arch/arm/domain_build.c
> index 9202a96d9c28..ba4fe9e165ee 100644
> --- a/xen/arch/arm/domain_build.c
> +++ b/xen/arch/arm/domain_build.c
> @@ -4008,6 +4008,34 @@ void __init create_domUs(void)
> d_cfg.max_maptrack_frames = val;
> }
>
> + if ( dt_get_property(node, "sve", &val) )
> + {
> +#ifdef CONFIG_ARM64_SVE
> + unsigned int sve_vl_bits;
> + bool ret = false;
> +
> + if ( !val )
> + {
> + /* Property found with no value, means max HW VL supported */
> + ret = sve_domctl_vl_param(-1, &sve_vl_bits);
> + }
> + else
> + {
> + if ( dt_property_read_u32(node, "sve", &val) )
> + ret = sve_domctl_vl_param(val, &sve_vl_bits);
> + else
> + panic("Error reading 'sve' property");
> + }
> +
> + if ( ret )
> + d_cfg.arch.sve_vl = sve_encode_vl(sve_vl_bits);
> + else
> + panic("SVE vector length error\n");
> +#else
> + panic("'sve' property found, but CONFIG_ARM64_SVE not selected");
> +#endif
> + }
> +
> /*
> * The variable max_init_domid is initialized with zero, so here it's
> * very important to use the pre-increment operator to call
> --
> 2.34.1
>
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [PATCH v7 12/12] xen/changelog: Add SVE and "dom0" options to the changelog for Arm
2023-05-23 7:43 ` [PATCH v7 12/12] xen/changelog: Add SVE and "dom0" options to the changelog for Arm Luca Fancellu
@ 2023-05-24 15:22 ` Bertrand Marquis
2023-05-25 9:41 ` Julien Grall
1 sibling, 0 replies; 49+ messages in thread
From: Bertrand Marquis @ 2023-05-24 15:22 UTC (permalink / raw)
To: Luca Fancellu
Cc: Xen-devel, Wei Chen, Henry Wang, Community Manager,
Andrew Cooper, George Dunlap, Jan Beulich, Julien Grall,
Stefano Stabellini, Wei Liu
Hi Luca,
> On 23 May 2023, at 09:43, Luca Fancellu <Luca.Fancellu@arm.com> wrote:
>
> Arm now can use the "dom0=" Xen command line option and the support
> for guests running SVE instructions is added, put entries in the
> changelog.
>
> Mention the "Tech Preview" status and add an entry in SUPPORT.md
>
> Signed-off-by: Luca Fancellu <luca.fancellu@arm.com>
> Acked-by: Henry Wang <Henry.Wang@arm.com> # CHANGELOG
Reviewed-by: Bertrand Marquis <bertrand.marquis@arm.com>
Cheers
Bertrand
> ---
> Changes from v6:
> - Add Henry's A-by to CHANGELOG
> Changes from v5:
> - Add Tech Preview status and add entry in SUPPORT.md (Bertrand)
> Changes from v4:
> - No changes
> Change from v3:
> - new patch
> ---
> CHANGELOG.md | 3 +++
> SUPPORT.md | 6 ++++++
> 2 files changed, 9 insertions(+)
>
> diff --git a/CHANGELOG.md b/CHANGELOG.md
> index 5bfd3aa5c0d5..512b7bdc0fcb 100644
> --- a/CHANGELOG.md
> +++ b/CHANGELOG.md
> @@ -11,6 +11,8 @@ The format is based on [Keep a Changelog](https://keepachangelog.com/en/1.0.0/)
> cap toolstack provided values.
> - Ignore VCPUOP_set_singleshot_timer's VCPU_SSHOTTMR_future flag. The only
> known user doesn't use it properly, leading to in-guest breakage.
> + - The "dom0" option is now supported on Arm and "sve=" sub-option can be used
> + to enable dom0 guest to use SVE/SVE2 instructions.
>
> ### Added
> - On x86, support for features new in Intel Sapphire Rapids CPUs:
> @@ -20,6 +22,7 @@ The format is based on [Keep a Changelog](https://keepachangelog.com/en/1.0.0/)
> - Bus-lock detection, used by Xen to mitigate (by rate-limiting) the system
> wide impact of a guest misusing atomic instructions.
> - xl/libxl can customize SMBIOS strings for HVM guests.
> + - On Arm, Xen supports guests running SVE/SVE2 instructions. (Tech Preview)
>
> ## [4.17.0](https://xenbits.xen.org/gitweb/?p=xen.git;a=shortlog;h=RELEASE-4.17.0) - 2022-12-12
>
> diff --git a/SUPPORT.md b/SUPPORT.md
> index 6dbed9d5d029..e0fa2246807b 100644
> --- a/SUPPORT.md
> +++ b/SUPPORT.md
> @@ -99,6 +99,12 @@ Extension to the GICv3 interrupt controller to support MSI.
>
> Status: Experimental
>
> +### ARM Scalable Vector Extension (SVE/SVE2)
> +
> +AArch64 guest can use Scalable Vector Extension (SVE/SVE2).
> +
> + Status: Tech Preview
> +
> ## Guest Type
>
> ### x86/PV
> --
> 2.34.1
>
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [PATCH v7 00/12] SVE feature for arm guests
2023-05-23 7:43 [PATCH v7 00/12] SVE feature for arm guests Luca Fancellu
` (11 preceding siblings ...)
2023-05-23 7:43 ` [PATCH v7 12/12] xen/changelog: Add SVE and "dom0" options to the changelog for Arm Luca Fancellu
@ 2023-05-25 8:15 ` Luca Fancellu
12 siblings, 0 replies; 49+ messages in thread
From: Luca Fancellu @ 2023-05-25 8:15 UTC (permalink / raw)
To: Xen-devel
Cc: Bertrand Marquis, Wei Chen, Stefano Stabellini, Julien Grall,
Volodymyr Babchuk, Andrew Cooper, George Dunlap, Jan Beulich,
Wei Liu, Roger Pau Monné,
Nick Rosbrook, Anthony PERARD, Juergen Gross, Christian Lindig,
David Scott, Marek Marczykowski-Górecki, Henry Wang,
Community Manager
> On 23 May 2023, at 08:43, Luca Fancellu <Luca.Fancellu@arm.com> wrote:
>
> This serie is introducing the possibility for Dom0 and DomU guests to use
> sve/sve2 instructions.
>
> SVE feature introduces new instruction and registers to improve performances on
> floating point operations.
>
> The SVE feature is advertised using the ID_AA64PFR0_EL1 register, SVE field, and
> when available the ID_AA64ZFR0_EL1 register provides additional information
> about the implemented version and other SVE feature.
>
> New registers added by the SVE feature are Z0-Z31, P0-P15, FFR, ZCR_ELx.
>
> Z0-Z31 are scalable vector register whose size is implementation defined and
> goes from 128 bits to maximum 2048, the term vector length will be used to refer
> to this quantity.
> P0-P15 are predicate registers and the size is the vector length divided by 8,
> same size is the FFR (First Fault Register).
> ZCR_ELx is a register that can control and restrict the maximum vector length
> used by the <x> exception level and all the lower exception levels, so for
> example EL3 can restrict the vector length usable by EL3,2,1,0.
>
> The platform has a maximum implemented vector length, so for every value
> written in ZCR register, if this value is above the implemented length, then the
> lower value will be used. The RDVL instruction can be used to check what vector
> length is the HW using after setting ZCR.
>
> For an SVE guest, the V0-V31 registers are part of the Z0-Z31, so there is no
> need to save them separately, saving Z0-Z31 will save implicitly also V0-V31.
>
> SVE usage can be trapped using a flag in CPTR_EL2, hence in this serie the
> register is added to the domain state, to be able to trap only the guests that
> are not allowed to use SVE.
>
> This serie is introducing a command line parameter to enable Dom0 to use SVE and
> to set its maximum vector length that by default is 0 which means the guest is
> not allowed to use SVE. Values from 128 to 2048 mean the guest can use SVE with
> the selected value used as maximum allowed vector length (which could be lower
> if the implemented one is lower).
> For DomUs, an XL parameter with the same way of use is introduced and a dom0less
> DTB binding is created.
>
> The context switch is the most critical part because there can be big registers
> to be saved, in this serie an easy approach is used and the context is
> saved/restored every time for the guests that are allowed to use SVE.
>
> Luca Fancellu (12):
> xen/arm: enable SVE extension for Xen
> xen/arm: add SVE vector length field to the domain
> xen/arm: Expose SVE feature to the guest
> xen/arm: add SVE exception class handling
> arm/sve: save/restore SVE context switch
> xen/common: add dom0 xen command line argument for Arm
> xen: enable Dom0 to use SVE feature
> xen/physinfo: encode Arm SVE vector length in arch_capabilities
> tools: add physinfo arch_capabilities handling for Arm
> xen/tools: add sve parameter in XL configuration
> xen/arm: add sve property for dom0less domUs
> xen/changelog: Add SVE and "dom0" options to the changelog for Arm
>
> CHANGELOG.md | 3 +
> SUPPORT.md | 6 +
> docs/man/xl.cfg.5.pod.in | 16 ++
> docs/misc/arm/device-tree/booting.txt | 16 ++
> docs/misc/xen-command-line.pandoc | 20 +-
> tools/golang/xenlight/helpers.gen.go | 4 +
> tools/golang/xenlight/types.gen.go | 24 +++
> tools/include/libxl.h | 11 +
> .../include/xen-tools/arm-arch-capabilities.h | 28 +++
> tools/include/xen-tools/common-macros.h | 2 +
> tools/libs/light/libxl.c | 1 +
> tools/libs/light/libxl_arm.c | 33 +++
> tools/libs/light/libxl_internal.h | 1 -
> tools/libs/light/libxl_types.idl | 23 +++
> tools/ocaml/libs/xc/xenctrl.ml | 4 +-
> tools/ocaml/libs/xc/xenctrl.mli | 4 +-
> tools/ocaml/libs/xc/xenctrl_stubs.c | 8 +-
> tools/python/xen/lowlevel/xc/xc.c | 8 +-
> tools/xl/xl_info.c | 8 +
> tools/xl/xl_parse.c | 8 +
> xen/arch/arm/Kconfig | 10 +-
> xen/arch/arm/README.LinuxPrimitives | 11 +
> xen/arch/arm/arm64/Makefile | 1 +
> xen/arch/arm/arm64/cpufeature.c | 7 +-
> xen/arch/arm/arm64/domctl.c | 4 +
> xen/arch/arm/arm64/sve-asm.S | 195 ++++++++++++++++++
> xen/arch/arm/arm64/sve.c | 182 ++++++++++++++++
> xen/arch/arm/arm64/vfp.c | 79 ++++---
> xen/arch/arm/arm64/vsysreg.c | 41 +++-
> xen/arch/arm/cpufeature.c | 6 +-
> xen/arch/arm/domain.c | 55 ++++-
> xen/arch/arm/domain_build.c | 66 ++++++
> xen/arch/arm/include/asm/arm64/sve.h | 72 +++++++
> xen/arch/arm/include/asm/arm64/sysregs.h | 4 +
> xen/arch/arm/include/asm/arm64/vfp.h | 12 ++
> xen/arch/arm/include/asm/cpufeature.h | 14 ++
> xen/arch/arm/include/asm/domain.h | 8 +
> xen/arch/arm/include/asm/processor.h | 3 +
> xen/arch/arm/setup.c | 5 +-
> xen/arch/arm/sysctl.c | 4 +
> xen/arch/arm/traps.c | 36 +++-
> xen/arch/x86/dom0_build.c | 48 ++---
> xen/common/domain.c | 23 +++
> xen/common/kernel.c | 28 +++
> xen/include/public/arch-arm.h | 2 +
> xen/include/public/sysctl.h | 4 +
> xen/include/xen/domain.h | 1 +
> xen/include/xen/lib.h | 10 +
> 48 files changed, 1052 insertions(+), 107 deletions(-)
> create mode 100644 tools/include/xen-tools/arm-arch-capabilities.h
> create mode 100644 xen/arch/arm/arm64/sve-asm.S
> create mode 100644 xen/arch/arm/arm64/sve.c
> create mode 100644 xen/arch/arm/include/asm/arm64/sve.h
Hi All,
I received some r-by for this serie dependent on some fix, so I will wait until next
week for further comments and then I will push the series with the fixes and with
the tags to ease the committers work
>
> --
> 2.34.1
>
>
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [PATCH v7 09/12] tools: add physinfo arch_capabilities handling for Arm
2023-05-23 7:43 ` [PATCH v7 09/12] tools: add physinfo arch_capabilities handling for Arm Luca Fancellu
@ 2023-05-25 8:39 ` Marek Marczykowski-Górecki
2023-05-25 9:16 ` Luca Fancellu
0 siblings, 1 reply; 49+ messages in thread
From: Marek Marczykowski-Górecki @ 2023-05-25 8:39 UTC (permalink / raw)
To: Luca Fancellu
Cc: xen-devel, bertrand.marquis, wei.chen, George Dunlap,
Nick Rosbrook, Wei Liu, Anthony PERARD, Juergen Gross,
Christian Lindig, David Scott, Christian Lindig
[-- Attachment #1: Type: text/plain, Size: 4482 bytes --]
On Tue, May 23, 2023 at 08:43:23AM +0100, Luca Fancellu wrote:
> On Arm, the SVE vector length is encoded in arch_capabilities field
> of struct xen_sysctl_physinfo, make use of this field in the tools
> when building for arm.
>
> Create header arm-arch-capabilities.h to handle the arch_capabilities
> field of physinfo for Arm.
>
> Removed include for xen-tools/common-macros.h in
> python/xen/lowlevel/xc/xc.c because it is already included by the
> arm-arch-capabilities.h header.
>
> Signed-off-by: Luca Fancellu <luca.fancellu@arm.com>
> Acked-by: George Dunlap <george.dunlap@citrix.com>
> Acked-by: Christian Lindig <christian.lindig@cloud.com>
> Reviewed-by: Anthony PERARD <anthony.perard@citrix.com>
> ---
> Changes from v6:
> - Fix licence header in arm-atch-capabilities.h, add R-by (Anthony)
> Changes from v5:
> - no changes
> Changes from v4:
> - Move arm-arch-capabilities.h into xen-tools/, add LIBXL_HAVE_,
> fixed python return type to I instead of i. (Anthony)
> Changes from v3:
> - add Ack-by for the Golang bits (George)
> - add Ack-by for the OCaml tools (Christian)
> - now xen-tools/libs.h is named xen-tools/common-macros.h
> - changed commit message to explain why the header modification
> in python/xen/lowlevel/xc/xc.c
> Changes from v2:
> - rename arm_arch_capabilities.h in arm-arch-capabilities.h, use
> MASK_EXTR.
> - Now arm-arch-capabilities.h needs MASK_EXTR macro, but it is
> defined in libxl_internal.h, it doesn't feel right to include
> that header so move MASK_EXTR into xen-tools/libs.h that is also
> included in libxl_internal.h
> Changes from v1:
> - now SVE VL is encoded in arch_capabilities on Arm
> Changes from RFC:
> - new patch
> ---
> tools/golang/xenlight/helpers.gen.go | 2 ++
> tools/golang/xenlight/types.gen.go | 1 +
> tools/include/libxl.h | 6 ++++
> .../include/xen-tools/arm-arch-capabilities.h | 28 +++++++++++++++++++
> tools/include/xen-tools/common-macros.h | 2 ++
> tools/libs/light/libxl.c | 1 +
> tools/libs/light/libxl_internal.h | 1 -
> tools/libs/light/libxl_types.idl | 1 +
> tools/ocaml/libs/xc/xenctrl.ml | 4 +--
> tools/ocaml/libs/xc/xenctrl.mli | 4 +--
> tools/ocaml/libs/xc/xenctrl_stubs.c | 8 ++++--
> tools/python/xen/lowlevel/xc/xc.c | 8 ++++--
> tools/xl/xl_info.c | 8 ++++++
> 13 files changed, 62 insertions(+), 12 deletions(-)
> create mode 100644 tools/include/xen-tools/arm-arch-capabilities.h
>
(...)
> diff --git a/tools/python/xen/lowlevel/xc/xc.c b/tools/python/xen/lowlevel/xc/xc.c
> index 9728b34185ac..b3699fdac58e 100644
> --- a/tools/python/xen/lowlevel/xc/xc.c
> +++ b/tools/python/xen/lowlevel/xc/xc.c
> @@ -22,6 +22,7 @@
> #include <xen/hvm/hvm_info_table.h>
> #include <xen/hvm/params.h>
>
> +#include <xen-tools/arm-arch-capabilities.h>
> #include <xen-tools/common-macros.h>
>
> /* Needed for Python versions earlier than 2.3. */
> @@ -897,7 +898,7 @@ static PyObject *pyxc_physinfo(XcObject *self)
> if ( p != virt_caps )
> *(p-1) = '\0';
>
> - return Py_BuildValue("{s:i,s:i,s:i,s:i,s:l,s:l,s:l,s:i,s:s,s:s}",
> + return Py_BuildValue("{s:i,s:i,s:i,s:i,s:l,s:l,s:l,s:i,s:s,s:s,s:I}",
> "nr_nodes", pinfo.nr_nodes,
> "threads_per_core", pinfo.threads_per_core,
> "cores_per_socket", pinfo.cores_per_socket,
> @@ -907,7 +908,10 @@ static PyObject *pyxc_physinfo(XcObject *self)
> "scrub_memory", pages_to_kib(pinfo.scrub_pages),
> "cpu_khz", pinfo.cpu_khz,
> "hw_caps", cpu_cap,
> - "virt_caps", virt_caps);
> + "virt_caps", virt_caps,
> + "arm_sve_vl",
> + arch_capabilities_arm_sve(pinfo.arch_capabilities)
> + );
This should be added only when building for ARM, similar as for other
bindings.
> }
>
> static PyObject *pyxc_getcpuinfo(XcObject *self, PyObject *args, PyObject *kwds)
--
Best Regards,
Marek Marczykowski-Górecki
Invisible Things Lab
[-- Attachment #2: signature.asc --]
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^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [PATCH v7 11/12] xen/arm: add sve property for dom0less domUs
2023-05-24 15:20 ` Bertrand Marquis
@ 2023-05-25 8:52 ` Michal Orzel
2023-05-25 8:55 ` Luca Fancellu
0 siblings, 1 reply; 49+ messages in thread
From: Michal Orzel @ 2023-05-25 8:52 UTC (permalink / raw)
To: Bertrand Marquis, Luca Fancellu
Cc: Xen-devel, Wei Chen, Stefano Stabellini, Julien Grall, Volodymyr Babchuk
Hi Luca,
Sorry for jumping into this but I just wanted to read the dt binding doc and spotted one thing by accident.
On 24/05/2023 17:20, Bertrand Marquis wrote:
>
>
> Hi Luca,
>
>> On 23 May 2023, at 09:43, Luca Fancellu <Luca.Fancellu@arm.com> wrote:
>>
>> Add a device tree property in the dom0less domU configuration
>> to enable the guest to use SVE.
>>
>> Update documentation.
>>
>> Signed-off-by: Luca Fancellu <luca.fancellu@arm.com>
>
> Reviewed-by: Bertrand Marquis <bertrand.marquis@arm.com>
(...)
>> diff --git a/xen/arch/arm/domain_build.c b/xen/arch/arm/domain_build.c
>> index 9202a96d9c28..ba4fe9e165ee 100644
>> --- a/xen/arch/arm/domain_build.c
>> +++ b/xen/arch/arm/domain_build.c
>> @@ -4008,6 +4008,34 @@ void __init create_domUs(void)
>> d_cfg.max_maptrack_frames = val;
>> }
>>
>> + if ( dt_get_property(node, "sve", &val) )
>> + {
>> +#ifdef CONFIG_ARM64_SVE
>> + unsigned int sve_vl_bits;
>> + bool ret = false;
>> +
>> + if ( !val )
>> + {
>> + /* Property found with no value, means max HW VL supported */
>> + ret = sve_domctl_vl_param(-1, &sve_vl_bits);
>> + }
>> + else
>> + {
>> + if ( dt_property_read_u32(node, "sve", &val) )
>> + ret = sve_domctl_vl_param(val, &sve_vl_bits);
>> + else
>> + panic("Error reading 'sve' property");
Both here and ...
>> + }
>> +
>> + if ( ret )
>> + d_cfg.arch.sve_vl = sve_encode_vl(sve_vl_bits);
>> + else
>> + panic("SVE vector length error\n");
>> +#else
>> + panic("'sve' property found, but CONFIG_ARM64_SVE not selected");
here you are missing \n at the end of string. If you take a look at panic() implementation,
new line char is not added so in your case it would result in an ugly formatted panic message.
~Michal
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [PATCH v7 11/12] xen/arm: add sve property for dom0less domUs
2023-05-25 8:52 ` Michal Orzel
@ 2023-05-25 8:55 ` Luca Fancellu
2023-05-25 9:03 ` Bertrand Marquis
2023-05-25 9:03 ` Michal Orzel
0 siblings, 2 replies; 49+ messages in thread
From: Luca Fancellu @ 2023-05-25 8:55 UTC (permalink / raw)
To: Michal Orzel
Cc: Bertrand Marquis, Xen-devel, Wei Chen, Stefano Stabellini,
Julien Grall, Volodymyr Babchuk
> On 25 May 2023, at 09:52, Michal Orzel <michal.orzel@amd.com> wrote:
>
> Hi Luca,
>
> Sorry for jumping into this but I just wanted to read the dt binding doc and spotted one thing by accident.
>
> On 24/05/2023 17:20, Bertrand Marquis wrote:
>>
>>
>> Hi Luca,
>>
>>> On 23 May 2023, at 09:43, Luca Fancellu <Luca.Fancellu@arm.com> wrote:
>>>
>>> Add a device tree property in the dom0less domU configuration
>>> to enable the guest to use SVE.
>>>
>>> Update documentation.
>>>
>>> Signed-off-by: Luca Fancellu <luca.fancellu@arm.com>
>>
>> Reviewed-by: Bertrand Marquis <bertrand.marquis@arm.com>
>
> (...)
>>> diff --git a/xen/arch/arm/domain_build.c b/xen/arch/arm/domain_build.c
>>> index 9202a96d9c28..ba4fe9e165ee 100644
>>> --- a/xen/arch/arm/domain_build.c
>>> +++ b/xen/arch/arm/domain_build.c
>>> @@ -4008,6 +4008,34 @@ void __init create_domUs(void)
>>> d_cfg.max_maptrack_frames = val;
>>> }
>>>
>>> + if ( dt_get_property(node, "sve", &val) )
>>> + {
>>> +#ifdef CONFIG_ARM64_SVE
>>> + unsigned int sve_vl_bits;
>>> + bool ret = false;
>>> +
>>> + if ( !val )
>>> + {
>>> + /* Property found with no value, means max HW VL supported */
>>> + ret = sve_domctl_vl_param(-1, &sve_vl_bits);
>>> + }
>>> + else
>>> + {
>>> + if ( dt_property_read_u32(node, "sve", &val) )
>>> + ret = sve_domctl_vl_param(val, &sve_vl_bits);
>>> + else
>>> + panic("Error reading 'sve' property");
> Both here and ...
>
>>> + }
>>> +
>>> + if ( ret )
>>> + d_cfg.arch.sve_vl = sve_encode_vl(sve_vl_bits);
>>> + else
>>> + panic("SVE vector length error\n");
>>> +#else
>>> + panic("'sve' property found, but CONFIG_ARM64_SVE not selected");
> here you are missing \n at the end of string. If you take a look at panic() implementation,
> new line char is not added so in your case it would result in an ugly formatted panic message.
Hi Michal,
Thank you for pointing that out! Indeed there might be some issues, I will fix in the next push.
@Bertrand, can I retain your R-by with this fix?
>
> ~Michal
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [PATCH v7 01/12] xen/arm: enable SVE extension for Xen
2023-05-23 7:43 ` [PATCH v7 01/12] xen/arm: enable SVE extension for Xen Luca Fancellu
2023-05-24 9:01 ` Bertrand Marquis
@ 2023-05-25 8:57 ` Julien Grall
2023-05-25 8:58 ` Julien Grall
2 siblings, 0 replies; 49+ messages in thread
From: Julien Grall @ 2023-05-25 8:57 UTC (permalink / raw)
To: Luca Fancellu, xen-devel
Cc: bertrand.marquis, wei.chen, Stefano Stabellini, Volodymyr Babchuk
On 23/05/2023 08:43, Luca Fancellu wrote:
> Enable Xen to handle the SVE extension, add code in cpufeature module
> to handle ZCR SVE register, disable trapping SVE feature on system
> boot only when SVE resources are accessed.
> While there, correct coding style for the comment on coprocessor
> trapping.
>
> Now cptr_el2 is part of the domain context and it will be restored
> on context switch, this is a preparation for saving the SVE context
> which will be part of VFP operations, so restore it before the call
> to save VFP registers.
> To save an additional isb barrier, restore cptr_el2 before an
> existing isb barrier and move the call for saving VFP context after
> that barrier. To keep a (mostly) specularity of ctxt_switch_to()
> and ctxt_switch_from(), move vfp_save_state() up in the function.
>
> Change the KConfig entry to make ARM64_SVE symbol selectable, by
> default it will be not selected.
>
> Create sve module and sve_asm.S that contains assembly routines for
> the SVE feature, this code is inspired from linux and it uses
> instruction encoding to be compatible with compilers that does not
> support SVE, imported instructions are documented in
> README.LinuxPrimitives.
>
> Signed-off-by: Luca Fancellu <luca.fancellu@arm.com>
Acked-by: Julien Grall <jgrall@amazon.com>
Cheers,
--
Julien Grall
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [PATCH v7 01/12] xen/arm: enable SVE extension for Xen
2023-05-23 7:43 ` [PATCH v7 01/12] xen/arm: enable SVE extension for Xen Luca Fancellu
2023-05-24 9:01 ` Bertrand Marquis
2023-05-25 8:57 ` Julien Grall
@ 2023-05-25 8:58 ` Julien Grall
2 siblings, 0 replies; 49+ messages in thread
From: Julien Grall @ 2023-05-25 8:58 UTC (permalink / raw)
To: Luca Fancellu, xen-devel
Cc: bertrand.marquis, wei.chen, Stefano Stabellini, Volodymyr Babchuk
On 23/05/2023 08:43, Luca Fancellu wrote:
> Enable Xen to handle the SVE extension, add code in cpufeature module
> to handle ZCR SVE register, disable trapping SVE feature on system
> boot only when SVE resources are accessed.
> While there, correct coding style for the comment on coprocessor
> trapping.
>
> Now cptr_el2 is part of the domain context and it will be restored
> on context switch, this is a preparation for saving the SVE context
> which will be part of VFP operations, so restore it before the call
> to save VFP registers.
> To save an additional isb barrier, restore cptr_el2 before an
> existing isb barrier and move the call for saving VFP context after
> that barrier. To keep a (mostly) specularity of ctxt_switch_to()
> and ctxt_switch_from(), move vfp_save_state() up in the function.
>
> Change the KConfig entry to make ARM64_SVE symbol selectable, by
> default it will be not selected.
>
> Create sve module and sve_asm.S that contains assembly routines for
> the SVE feature, this code is inspired from linux and it uses
> instruction encoding to be compatible with compilers that does not
> support SVE, imported instructions are documented in
> README.LinuxPrimitives.
>
> Signed-off-by: Luca Fancellu <luca.fancellu@arm.com>
Acked-by: Julien Grall <jgrall@amazon.com>
Cheers,
--
Julien Grall
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [PATCH v7 02/12] xen/arm: add SVE vector length field to the domain
2023-05-23 7:43 ` [PATCH v7 02/12] xen/arm: add SVE vector length field to the domain Luca Fancellu
2023-05-24 9:23 ` Bertrand Marquis
@ 2023-05-25 8:59 ` Julien Grall
1 sibling, 0 replies; 49+ messages in thread
From: Julien Grall @ 2023-05-25 8:59 UTC (permalink / raw)
To: Luca Fancellu, xen-devel
Cc: bertrand.marquis, wei.chen, Stefano Stabellini, Volodymyr Babchuk
Hi,
On 23/05/2023 08:43, Luca Fancellu wrote:
> Add sve_vl field to arch_domain and xen_arch_domainconfig struct,
> to allow the domain to have an information about the SVE feature
> and the number of SVE register bits that are allowed for this
> domain.
>
> sve_vl field is the vector length in bits divided by 128, this
> allows to use less space in the structures.
>
> The field is used also to allow or forbid a domain to use SVE,
> because a value equal to zero means the guest is not allowed to
> use the feature.
>
> Check that the requested vector length is lower or equal to the
> platform supported vector length, otherwise fail on domain
> creation.
>
> Check that only 64 bit domains have SVE enabled, otherwise fail.
>
> Signed-off-by: Luca Fancellu <luca.fancellu@arm.com>
Acked-by: Julien Grall <jgrall@amazon.com>
Cheers,
> ---
> Changes from v6:
> - Style fix, have is_sve_domain as static inline instead of macro
> (Julien)
> Changes from v5:
> - Update commit message stating the interface ver. bump (Bertrand)
> - in struct arch_domain, protect sve_vl with CONFIG_ARM64_SVE,
> given the change, move also is_sve_domain() where it's protected
> inside sve.h and create a stub when the macro is not defined,
> protect the usage of sve_vl where needed.
> (Julien)
> - Add a check for 32 bit guest running on top of 64 bit host that
> have sve parameter enabled to stop the domain creation, added in
> construct_domain() of domain_build.c and subarch_do_domctl of
> domctl.c. (Julien)
> Changes from v4:
> - Return 0 in get_sys_vl_len() if sve is not supported, code style fix,
> removed else if since the conditions can't fallthrough, removed not
> needed condition checking for VL bits validity because it's already
> covered, so delete is_vl_valid() function. (Jan)
> Changes from v3:
> - don't use fixed types when not needed, use encoded value also in
> arch_domain so rename sve_vl_bits in sve_vl. (Jan)
> - rename domainconfig_decode_vl to sve_decode_vl because it will now
> be used also to decode from arch_domain value
> - change sve_vl from uint16_t to uint8_t and move it after "type" field
> to optimize space.
> Changes from v2:
> - rename field in xen_arch_domainconfig from "sve_vl_bits" to
> "sve_vl" and use the implicit padding after gic_version to
> store it, now this field is the VL/128. (Jan)
> - Created domainconfig_decode_vl() function to decode the sve_vl
> field and use it as plain bits value inside arch_domain.
> - Changed commit message reflecting the changes
> Changes from v1:
> - no changes
> Changes from RFC:
> - restore zcr_el2 in sve_restore_state, that will be introduced
> later in this serie, so remove zcr_el2 related code from this
> patch and move everything to the later patch (Julien)
> - add explicit padding into struct xen_arch_domainconfig (Julien)
> - Don't lower down the vector length, just fail to create the
> domain. (Julien)
> ---
> xen/arch/arm/arm64/domctl.c | 4 ++++
> xen/arch/arm/arm64/sve.c | 12 +++++++++++
> xen/arch/arm/domain.c | 29 ++++++++++++++++++++++++++
> xen/arch/arm/domain_build.c | 7 +++++++
> xen/arch/arm/include/asm/arm64/sve.h | 31 ++++++++++++++++++++++++++++
> xen/arch/arm/include/asm/domain.h | 5 +++++
> xen/include/public/arch-arm.h | 2 ++
> 7 files changed, 90 insertions(+)
>
> diff --git a/xen/arch/arm/arm64/domctl.c b/xen/arch/arm/arm64/domctl.c
> index 0de89b42c448..14fc622e9956 100644
> --- a/xen/arch/arm/arm64/domctl.c
> +++ b/xen/arch/arm/arm64/domctl.c
> @@ -10,6 +10,7 @@
> #include <xen/sched.h>
> #include <xen/hypercall.h>
> #include <public/domctl.h>
> +#include <asm/arm64/sve.h>
> #include <asm/cpufeature.h>
>
> static long switch_mode(struct domain *d, enum domain_type type)
> @@ -43,6 +44,9 @@ long subarch_do_domctl(struct xen_domctl *domctl, struct domain *d,
> case 32:
> if ( !cpu_has_el1_32 )
> return -EINVAL;
> + /* SVE is not supported for 32 bit domain */
> + if ( is_sve_domain(d) )
> + return -EINVAL;
> return switch_mode(d, DOMAIN_32BIT);
> case 64:
> return switch_mode(d, DOMAIN_64BIT);
> diff --git a/xen/arch/arm/arm64/sve.c b/xen/arch/arm/arm64/sve.c
> index e05ccc38a896..a9144e48ef6b 100644
> --- a/xen/arch/arm/arm64/sve.c
> +++ b/xen/arch/arm/arm64/sve.c
> @@ -8,6 +8,7 @@
> #include <xen/types.h>
> #include <asm/arm64/sve.h>
> #include <asm/arm64/sysregs.h>
> +#include <asm/cpufeature.h>
> #include <asm/processor.h>
> #include <asm/system.h>
>
> @@ -49,6 +50,17 @@ register_t compute_max_zcr(void)
> return vl_to_zcr(hw_vl);
> }
>
> +/* Get the system sanitized value for VL in bits */
> +unsigned int get_sys_vl_len(void)
> +{
> + if ( !cpu_has_sve )
> + return 0;
> +
> + /* ZCR_ELx len field is ((len + 1) * 128) = vector bits length */
> + return ((system_cpuinfo.zcr64.bits[0] & ZCR_ELx_LEN_MASK) + 1U) *
> + SVE_VL_MULTIPLE_VAL;
> +}
> +
> /*
> * Local variables:
> * mode: C
> diff --git a/xen/arch/arm/domain.c b/xen/arch/arm/domain.c
> index d5ab15db46c4..6c22551b0ed2 100644
> --- a/xen/arch/arm/domain.c
> +++ b/xen/arch/arm/domain.c
> @@ -13,6 +13,7 @@
> #include <xen/wait.h>
>
> #include <asm/alternative.h>
> +#include <asm/arm64/sve.h>
> #include <asm/cpuerrata.h>
> #include <asm/cpufeature.h>
> #include <asm/current.h>
> @@ -555,6 +556,8 @@ int arch_vcpu_create(struct vcpu *v)
> v->arch.vmpidr = MPIDR_SMP | vcpuid_to_vaffinity(v->vcpu_id);
>
> v->arch.cptr_el2 = get_default_cptr_flags();
> + if ( is_sve_domain(v->domain) )
> + v->arch.cptr_el2 &= ~HCPTR_CP(8);
>
> v->arch.hcr_el2 = get_default_hcr_flags();
>
> @@ -599,6 +602,7 @@ int arch_sanitise_domain_config(struct xen_domctl_createdomain *config)
> unsigned int max_vcpus;
> unsigned int flags_required = (XEN_DOMCTL_CDF_hvm | XEN_DOMCTL_CDF_hap);
> unsigned int flags_optional = (XEN_DOMCTL_CDF_iommu | XEN_DOMCTL_CDF_vpmu);
> + unsigned int sve_vl_bits = sve_decode_vl(config->arch.sve_vl);
>
> if ( (config->flags & ~flags_optional) != flags_required )
> {
> @@ -607,6 +611,26 @@ int arch_sanitise_domain_config(struct xen_domctl_createdomain *config)
> return -EINVAL;
> }
>
> + /* Check feature flags */
> + if ( sve_vl_bits > 0 )
> + {
> + unsigned int zcr_max_bits = get_sys_vl_len();
> +
> + if ( !zcr_max_bits )
> + {
> + dprintk(XENLOG_INFO, "SVE is unsupported on this machine.\n");
> + return -EINVAL;
> + }
> +
> + if ( sve_vl_bits > zcr_max_bits )
> + {
> + dprintk(XENLOG_INFO,
> + "Requested SVE vector length (%u) > supported length (%u)\n",
> + sve_vl_bits, zcr_max_bits);
> + return -EINVAL;
> + }
> + }
> +
> /* The P2M table must always be shared between the CPU and the IOMMU */
> if ( config->iommu_opts & XEN_DOMCTL_IOMMU_no_sharept )
> {
> @@ -749,6 +773,11 @@ int arch_domain_create(struct domain *d,
> if ( (rc = domain_vpci_init(d)) != 0 )
> goto fail;
>
> +#ifdef CONFIG_ARM64_SVE
> + /* Copy the encoded vector length sve_vl from the domain configuration */
> + d->arch.sve_vl = config->arch.sve_vl;
> +#endif
> +
> return 0;
>
> fail:
> diff --git a/xen/arch/arm/domain_build.c b/xen/arch/arm/domain_build.c
> index 71f307a572e9..9dd1ed5bce44 100644
> --- a/xen/arch/arm/domain_build.c
> +++ b/xen/arch/arm/domain_build.c
> @@ -26,6 +26,7 @@
> #include <asm/platform.h>
> #include <asm/psci.h>
> #include <asm/setup.h>
> +#include <asm/arm64/sve.h>
> #include <asm/cpufeature.h>
> #include <asm/domain_build.h>
> #include <xen/event.h>
> @@ -3670,6 +3671,12 @@ static int __init construct_domain(struct domain *d, struct kernel_info *kinfo)
> return -EINVAL;
> }
>
> + if ( is_sve_domain(d) && (kinfo->type == DOMAIN_32BIT) )
> + {
> + printk("SVE is not available for 32-bit domain\n");
> + return -EINVAL;
> + }
> +
> if ( is_64bit_domain(d) )
> vcpu_switch_to_aarch64_mode(v);
>
> diff --git a/xen/arch/arm/include/asm/arm64/sve.h b/xen/arch/arm/include/asm/arm64/sve.h
> index c0466243c7bc..4b63412727fc 100644
> --- a/xen/arch/arm/include/asm/arm64/sve.h
> +++ b/xen/arch/arm/include/asm/arm64/sve.h
> @@ -8,13 +8,44 @@
> #ifndef _ARM_ARM64_SVE_H
> #define _ARM_ARM64_SVE_H
>
> +#include <xen/sched.h>
> +
> #define SVE_VL_MAX_BITS 2048U
>
> /* Vector length must be multiple of 128 */
> #define SVE_VL_MULTIPLE_VAL 128U
>
> +static inline unsigned int sve_decode_vl(unsigned int sve_vl)
> +{
> + /* SVE vector length is stored as VL/128 in xen_arch_domainconfig */
> + return sve_vl * SVE_VL_MULTIPLE_VAL;
> +}
> +
> register_t compute_max_zcr(void);
>
> +#ifdef CONFIG_ARM64_SVE
> +
> +static inline bool is_sve_domain(const struct domain *d)
> +{
> + return d->arch.sve_vl > 0;
> +}
> +
> +unsigned int get_sys_vl_len(void);
> +
> +#else /* !CONFIG_ARM64_SVE */
> +
> +static inline bool is_sve_domain(const struct domain *d)
> +{
> + return false;
> +}
> +
> +static inline unsigned int get_sys_vl_len(void)
> +{
> + return 0;
> +}
> +
> +#endif /* CONFIG_ARM64_SVE */
> +
> #endif /* _ARM_ARM64_SVE_H */
>
> /*
> diff --git a/xen/arch/arm/include/asm/domain.h b/xen/arch/arm/include/asm/domain.h
> index e776ee704b7d..331da0f3bcc3 100644
> --- a/xen/arch/arm/include/asm/domain.h
> +++ b/xen/arch/arm/include/asm/domain.h
> @@ -67,6 +67,11 @@ struct arch_domain
> enum domain_type type;
> #endif
>
> +#ifdef CONFIG_ARM64_SVE
> + /* max SVE encoded vector length */
> + uint8_t sve_vl;
> +#endif
> +
> /* Virtual MMU */
> struct p2m_domain p2m;
>
> diff --git a/xen/include/public/arch-arm.h b/xen/include/public/arch-arm.h
> index 1528ced5097a..38311f559581 100644
> --- a/xen/include/public/arch-arm.h
> +++ b/xen/include/public/arch-arm.h
> @@ -300,6 +300,8 @@ DEFINE_XEN_GUEST_HANDLE(vcpu_guest_context_t);
> struct xen_arch_domainconfig {
> /* IN/OUT */
> uint8_t gic_version;
> + /* IN - Contains SVE vector length divided by 128 */
> + uint8_t sve_vl;
> /* IN */
> uint16_t tee_type;
> /* IN */
--
Julien Grall
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [PATCH v7 11/12] xen/arm: add sve property for dom0less domUs
2023-05-25 8:55 ` Luca Fancellu
@ 2023-05-25 9:03 ` Bertrand Marquis
2023-05-25 9:03 ` Michal Orzel
1 sibling, 0 replies; 49+ messages in thread
From: Bertrand Marquis @ 2023-05-25 9:03 UTC (permalink / raw)
To: Luca Fancellu
Cc: Michal Orzel, Xen-devel, Wei Chen, Stefano Stabellini,
Julien Grall, Volodymyr Babchuk
Hi Luca,
> On 25 May 2023, at 10:55, Luca Fancellu <Luca.Fancellu@arm.com> wrote:
>
>
>
>> On 25 May 2023, at 09:52, Michal Orzel <michal.orzel@amd.com> wrote:
>>
>> Hi Luca,
>>
>> Sorry for jumping into this but I just wanted to read the dt binding doc and spotted one thing by accident.
>>
>> On 24/05/2023 17:20, Bertrand Marquis wrote:
>>>
>>>
>>> Hi Luca,
>>>
>>>> On 23 May 2023, at 09:43, Luca Fancellu <Luca.Fancellu@arm.com> wrote:
>>>>
>>>> Add a device tree property in the dom0less domU configuration
>>>> to enable the guest to use SVE.
>>>>
>>>> Update documentation.
>>>>
>>>> Signed-off-by: Luca Fancellu <luca.fancellu@arm.com>
>>>
>>> Reviewed-by: Bertrand Marquis <bertrand.marquis@arm.com>
>>
>> (...)
>>>> diff --git a/xen/arch/arm/domain_build.c b/xen/arch/arm/domain_build.c
>>>> index 9202a96d9c28..ba4fe9e165ee 100644
>>>> --- a/xen/arch/arm/domain_build.c
>>>> +++ b/xen/arch/arm/domain_build.c
>>>> @@ -4008,6 +4008,34 @@ void __init create_domUs(void)
>>>> d_cfg.max_maptrack_frames = val;
>>>> }
>>>>
>>>> + if ( dt_get_property(node, "sve", &val) )
>>>> + {
>>>> +#ifdef CONFIG_ARM64_SVE
>>>> + unsigned int sve_vl_bits;
>>>> + bool ret = false;
>>>> +
>>>> + if ( !val )
>>>> + {
>>>> + /* Property found with no value, means max HW VL supported */
>>>> + ret = sve_domctl_vl_param(-1, &sve_vl_bits);
>>>> + }
>>>> + else
>>>> + {
>>>> + if ( dt_property_read_u32(node, "sve", &val) )
>>>> + ret = sve_domctl_vl_param(val, &sve_vl_bits);
>>>> + else
>>>> + panic("Error reading 'sve' property");
>> Both here and ...
>>
>>>> + }
>>>> +
>>>> + if ( ret )
>>>> + d_cfg.arch.sve_vl = sve_encode_vl(sve_vl_bits);
>>>> + else
>>>> + panic("SVE vector length error\n");
>>>> +#else
>>>> + panic("'sve' property found, but CONFIG_ARM64_SVE not selected");
>> here you are missing \n at the end of string. If you take a look at panic() implementation,
>> new line char is not added so in your case it would result in an ugly formatted panic message.
>
> Hi Michal,
>
> Thank you for pointing that out! Indeed there might be some issues, I will fix in the next push.
>
> @Bertrand, can I retain your R-by with this fix?
Yes
Bertrand
>
>>
>> ~Michal
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [PATCH v7 11/12] xen/arm: add sve property for dom0less domUs
2023-05-25 8:55 ` Luca Fancellu
2023-05-25 9:03 ` Bertrand Marquis
@ 2023-05-25 9:03 ` Michal Orzel
1 sibling, 0 replies; 49+ messages in thread
From: Michal Orzel @ 2023-05-25 9:03 UTC (permalink / raw)
To: Luca Fancellu
Cc: Bertrand Marquis, Xen-devel, Wei Chen, Stefano Stabellini,
Julien Grall, Volodymyr Babchuk
On 25/05/2023 10:55, Luca Fancellu wrote:
>
>
>> On 25 May 2023, at 09:52, Michal Orzel <michal.orzel@amd.com> wrote:
>>
>> Hi Luca,
>>
>> Sorry for jumping into this but I just wanted to read the dt binding doc and spotted one thing by accident.
>>
>> On 24/05/2023 17:20, Bertrand Marquis wrote:
>>>
>>>
>>> Hi Luca,
>>>
>>>> On 23 May 2023, at 09:43, Luca Fancellu <Luca.Fancellu@arm.com> wrote:
>>>>
>>>> Add a device tree property in the dom0less domU configuration
>>>> to enable the guest to use SVE.
>>>>
>>>> Update documentation.
>>>>
>>>> Signed-off-by: Luca Fancellu <luca.fancellu@arm.com>
>>>
>>> Reviewed-by: Bertrand Marquis <bertrand.marquis@arm.com>
>>
>> (...)
>>>> diff --git a/xen/arch/arm/domain_build.c b/xen/arch/arm/domain_build.c
>>>> index 9202a96d9c28..ba4fe9e165ee 100644
>>>> --- a/xen/arch/arm/domain_build.c
>>>> +++ b/xen/arch/arm/domain_build.c
>>>> @@ -4008,6 +4008,34 @@ void __init create_domUs(void)
>>>> d_cfg.max_maptrack_frames = val;
>>>> }
>>>>
>>>> + if ( dt_get_property(node, "sve", &val) )
>>>> + {
>>>> +#ifdef CONFIG_ARM64_SVE
>>>> + unsigned int sve_vl_bits;
>>>> + bool ret = false;
>>>> +
>>>> + if ( !val )
>>>> + {
>>>> + /* Property found with no value, means max HW VL supported */
>>>> + ret = sve_domctl_vl_param(-1, &sve_vl_bits);
>>>> + }
>>>> + else
>>>> + {
>>>> + if ( dt_property_read_u32(node, "sve", &val) )
>>>> + ret = sve_domctl_vl_param(val, &sve_vl_bits);
>>>> + else
>>>> + panic("Error reading 'sve' property");
>> Both here and ...
>>
>>>> + }
>>>> +
>>>> + if ( ret )
>>>> + d_cfg.arch.sve_vl = sve_encode_vl(sve_vl_bits);
>>>> + else
>>>> + panic("SVE vector length error\n");
>>>> +#else
>>>> + panic("'sve' property found, but CONFIG_ARM64_SVE not selected");
>> here you are missing \n at the end of string. If you take a look at panic() implementation,
>> new line char is not added so in your case it would result in an ugly formatted panic message.
>
> Hi Michal,
>
> Thank you for pointing that out! Indeed there might be some issues, I will fix in the next push.
With that fixed,
Reviewed-by: Michal Orzel <michal.orzel@amd.com>
~Michal
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [PATCH v7 05/12] arm/sve: save/restore SVE context switch
2023-05-23 7:43 ` [PATCH v7 05/12] arm/sve: save/restore SVE context switch Luca Fancellu
2023-05-24 9:47 ` Bertrand Marquis
@ 2023-05-25 9:09 ` Julien Grall
2023-05-25 10:01 ` Luca Fancellu
1 sibling, 1 reply; 49+ messages in thread
From: Julien Grall @ 2023-05-25 9:09 UTC (permalink / raw)
To: Luca Fancellu, xen-devel
Cc: bertrand.marquis, wei.chen, Stefano Stabellini, Volodymyr Babchuk
Hi Luca,
On 23/05/2023 08:43, Luca Fancellu wrote:
> +int sve_context_init(struct vcpu *v)
> +{
> + unsigned int sve_vl_bits = sve_decode_vl(v->domain->arch.sve_vl);
> + uint64_t *ctx = _xzalloc(sve_zreg_ctx_size(sve_vl_bits) +
> + sve_ffrreg_ctx_size(sve_vl_bits),
> + L1_CACHE_BYTES);
> +
> + if ( !ctx )
> + return -ENOMEM;
> +
> + /*
> + * Point to the end of Z0-Z31 memory, just before FFR memory, to be kept in
> + * sync with sve_context_free()
Nit: Missing a full stop.
> + */
> + v->arch.vfp.sve_zreg_ctx_end = ctx +
> + (sve_zreg_ctx_size(sve_vl_bits) / sizeof(uint64_t));
> +
> + v->arch.zcr_el2 = vl_to_zcr(sve_vl_bits);
> +
> + return 0;
> +}
> +
> +void sve_context_free(struct vcpu *v)
> +{
> + unsigned int sve_vl_bits;
> +
> + if ( v->arch.vfp.sve_zreg_ctx_end )
> + return;
> +
> + sve_vl_bits = sve_decode_vl(v->domain->arch.sve_vl);
> +
> + /*
> + * Point to the end of Z0-Z31 memory, just before FFR memory, to be kept
> + * in sync with sve_context_init()
> + */
The spacing looks a bit odd in this comment. Did you miss an extra space?
Also, I notice this comment is the exact same as on top as
sve_context_init(). I think this is a bit misleading because the logic
is different. I would suggest the following:
"Currently points to the end of Z0-Z31 memory which is not the start of
the buffer. To be kept in sync with the sve_context_init()."
Lastly, nit: Missing a full stop.
> + v->arch.vfp.sve_zreg_ctx_end -=
> + (sve_zreg_ctx_size(sve_vl_bits) / sizeof(uint64_t));
> +
> + XFREE(v->arch.vfp.sve_zreg_ctx_end);
> +}
> +
[...]
> diff --git a/xen/arch/arm/include/asm/arm64/vfp.h b/xen/arch/arm/include/asm/arm64/vfp.h
> index e6e8c363bc16..4aa371e85d26 100644
> --- a/xen/arch/arm/include/asm/arm64/vfp.h
> +++ b/xen/arch/arm/include/asm/arm64/vfp.h
> @@ -6,7 +6,19 @@
>
> struct vfp_state
> {
> + /*
> + * When SVE is enabled for the guest, fpregs memory will be used to
> + * save/restore P0-P15 registers, otherwise it will be used for the V0-V31
> + * registers.
> + */
> uint64_t fpregs[64] __vfp_aligned;
> + /*
> + * When SVE is enabled for the guest, sve_zreg_ctx_end points to memory
> + * where Z0-Z31 registers and FFR can be saved/restored, it points at the
> + * end of the Z0-Z31 space and at the beginning of the FFR space, it's done
> + * like that to ease the save/restore assembly operations.
> + */
> + uint64_t *sve_zreg_ctx_end;
Sorry I only noticed now. But shouldn't this be protected with #ifdef
CONFIG_SVE? Same...
> register_t fpcr;
> register_t fpexc32_el2;
> register_t fpsr;
> diff --git a/xen/arch/arm/include/asm/domain.h b/xen/arch/arm/include/asm/domain.h
> index 331da0f3bcc3..814652d92568 100644
> --- a/xen/arch/arm/include/asm/domain.h
> +++ b/xen/arch/arm/include/asm/domain.h
> @@ -195,6 +195,8 @@ struct arch_vcpu
> register_t tpidrro_el0;
>
> /* HYP configuration */
> + register_t zcr_el1;
> + register_t zcr_el2;
... here.
> register_t cptr_el2;
> register_t hcr_el2;
> register_t mdcr_el2;
Cheers,
--
Julien Grall
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [PATCH v7 09/12] tools: add physinfo arch_capabilities handling for Arm
2023-05-25 8:39 ` Marek Marczykowski-Górecki
@ 2023-05-25 9:16 ` Luca Fancellu
2023-05-25 9:21 ` Luca Fancellu
0 siblings, 1 reply; 49+ messages in thread
From: Luca Fancellu @ 2023-05-25 9:16 UTC (permalink / raw)
To: Marek Marczykowski-Górecki
Cc: Xen-devel, Bertrand Marquis, Wei Chen, George Dunlap,
Nick Rosbrook, Wei Liu, Anthony PERARD, Juergen Gross,
Christian Lindig, David Scott, Christian Lindig
> On 25 May 2023, at 09:39, Marek Marczykowski-Górecki <marmarek@invisiblethingslab.com> wrote:
>
> On Tue, May 23, 2023 at 08:43:23AM +0100, Luca Fancellu wrote:
>> On Arm, the SVE vector length is encoded in arch_capabilities field
>> of struct xen_sysctl_physinfo, make use of this field in the tools
>> when building for arm.
>>
>> Create header arm-arch-capabilities.h to handle the arch_capabilities
>> field of physinfo for Arm.
>>
>> Removed include for xen-tools/common-macros.h in
>> python/xen/lowlevel/xc/xc.c because it is already included by the
>> arm-arch-capabilities.h header.
>>
>> Signed-off-by: Luca Fancellu <luca.fancellu@arm.com>
>> Acked-by: George Dunlap <george.dunlap@citrix.com>
>> Acked-by: Christian Lindig <christian.lindig@cloud.com>
>> Reviewed-by: Anthony PERARD <anthony.perard@citrix.com>
>> ---
>> Changes from v6:
>> - Fix licence header in arm-atch-capabilities.h, add R-by (Anthony)
>> Changes from v5:
>> - no changes
>> Changes from v4:
>> - Move arm-arch-capabilities.h into xen-tools/, add LIBXL_HAVE_,
>> fixed python return type to I instead of i. (Anthony)
>> Changes from v3:
>> - add Ack-by for the Golang bits (George)
>> - add Ack-by for the OCaml tools (Christian)
>> - now xen-tools/libs.h is named xen-tools/common-macros.h
>> - changed commit message to explain why the header modification
>> in python/xen/lowlevel/xc/xc.c
>> Changes from v2:
>> - rename arm_arch_capabilities.h in arm-arch-capabilities.h, use
>> MASK_EXTR.
>> - Now arm-arch-capabilities.h needs MASK_EXTR macro, but it is
>> defined in libxl_internal.h, it doesn't feel right to include
>> that header so move MASK_EXTR into xen-tools/libs.h that is also
>> included in libxl_internal.h
>> Changes from v1:
>> - now SVE VL is encoded in arch_capabilities on Arm
>> Changes from RFC:
>> - new patch
>> ---
>> tools/golang/xenlight/helpers.gen.go | 2 ++
>> tools/golang/xenlight/types.gen.go | 1 +
>> tools/include/libxl.h | 6 ++++
>> .../include/xen-tools/arm-arch-capabilities.h | 28 +++++++++++++++++++
>> tools/include/xen-tools/common-macros.h | 2 ++
>> tools/libs/light/libxl.c | 1 +
>> tools/libs/light/libxl_internal.h | 1 -
>> tools/libs/light/libxl_types.idl | 1 +
>> tools/ocaml/libs/xc/xenctrl.ml | 4 +--
>> tools/ocaml/libs/xc/xenctrl.mli | 4 +--
>> tools/ocaml/libs/xc/xenctrl_stubs.c | 8 ++++--
>> tools/python/xen/lowlevel/xc/xc.c | 8 ++++--
>> tools/xl/xl_info.c | 8 ++++++
>> 13 files changed, 62 insertions(+), 12 deletions(-)
>> create mode 100644 tools/include/xen-tools/arm-arch-capabilities.h
>>
>
> (...)
>
>> diff --git a/tools/python/xen/lowlevel/xc/xc.c b/tools/python/xen/lowlevel/xc/xc.c
>> index 9728b34185ac..b3699fdac58e 100644
>> --- a/tools/python/xen/lowlevel/xc/xc.c
>> +++ b/tools/python/xen/lowlevel/xc/xc.c
>> @@ -22,6 +22,7 @@
>> #include <xen/hvm/hvm_info_table.h>
>> #include <xen/hvm/params.h>
>>
>> +#include <xen-tools/arm-arch-capabilities.h>
>> #include <xen-tools/common-macros.h>
>>
>> /* Needed for Python versions earlier than 2.3. */
>> @@ -897,7 +898,7 @@ static PyObject *pyxc_physinfo(XcObject *self)
>> if ( p != virt_caps )
>> *(p-1) = '\0';
>>
>> - return Py_BuildValue("{s:i,s:i,s:i,s:i,s:l,s:l,s:l,s:i,s:s,s:s}",
>> + return Py_BuildValue("{s:i,s:i,s:i,s:i,s:l,s:l,s:l,s:i,s:s,s:s,s:I}",
>> "nr_nodes", pinfo.nr_nodes,
>> "threads_per_core", pinfo.threads_per_core,
>> "cores_per_socket", pinfo.cores_per_socket,
>> @@ -907,7 +908,10 @@ static PyObject *pyxc_physinfo(XcObject *self)
>> "scrub_memory", pages_to_kib(pinfo.scrub_pages),
>> "cpu_khz", pinfo.cpu_khz,
>> "hw_caps", cpu_cap,
>> - "virt_caps", virt_caps);
>> + "virt_caps", virt_caps,
>> + "arm_sve_vl",
>> + arch_capabilities_arm_sve(pinfo.arch_capabilities)
>> + );
>
> This should be added only when building for ARM, similar as for other
> bindings.
Hi Marek,
Thank you for taking the time to review this, are you ok if I make these changes to the code?
diff --git a/tools/python/xen/lowlevel/xc/xc.c b/tools/python/xen/lowlevel/xc/xc.c
index b3699fdac58e..c7f690189770 100644
--- a/tools/python/xen/lowlevel/xc/xc.c
+++ b/tools/python/xen/lowlevel/xc/xc.c
@@ -872,6 +872,8 @@ static PyObject *pyxc_physinfo(XcObject *self)
const char *virtcap_names[] = { "hvm", "pv" };
const unsigned virtcaps_bits[] = { XEN_SYSCTL_PHYSCAP_hvm,
XEN_SYSCTL_PHYSCAP_pv };
+ PyObject *objret;
+ int retcode;
if ( xc_physinfo(self->xc_handle, &pinfo) != 0 )
return pyxc_error_to_exception(self->xc_handle);
@@ -898,20 +900,31 @@ static PyObject *pyxc_physinfo(XcObject *self)
if ( p != virt_caps )
*(p-1) = '\0';
- return Py_BuildValue("{s:i,s:i,s:i,s:i,s:l,s:l,s:l,s:i,s:s,s:s,s:I}",
- "nr_nodes", pinfo.nr_nodes,
- "threads_per_core", pinfo.threads_per_core,
- "cores_per_socket", pinfo.cores_per_socket,
- "nr_cpus", pinfo.nr_cpus,
- "total_memory", pages_to_kib(pinfo.total_pages),
- "free_memory", pages_to_kib(pinfo.free_pages),
- "scrub_memory", pages_to_kib(pinfo.scrub_pages),
- "cpu_khz", pinfo.cpu_khz,
- "hw_caps", cpu_cap,
- "virt_caps", virt_caps,
- "arm_sve_vl",
- arch_capabilities_arm_sve(pinfo.arch_capabilities)
+ objret = Py_BuildValue("{s:i,s:i,s:i,s:i,s:l,s:l,s:l,s:i,s:s,s:s}",
+ "nr_nodes", pinfo.nr_nodes,
+ "threads_per_core", pinfo.threads_per_core,
+ "cores_per_socket", pinfo.cores_per_socket,
+ "nr_cpus", pinfo.nr_cpus,
+ "total_memory", pages_to_kib(pinfo.total_pages),
+ "free_memory", pages_to_kib(pinfo.free_pages),
+ "scrub_memory", pages_to_kib(pinfo.scrub_pages),
+ "cpu_khz", pinfo.cpu_khz,
+ "hw_caps", cpu_cap,
+ "virt_caps", virt_caps
);
+
+ #if defined(__aarch64__)
+ if (objret) {
+ retcode = PyDict_SetItemString(
+ objret, "arm_sve_vl",
+ arch_capabilities_arm_sve(pinfo.arch_capabilities)
+ );
+ if ( retcode < 0 )
+ return NULL;
+ }
+ #endif
+
+ return objret;
}
static PyObject *pyxc_getcpuinfo(XcObject *self, PyObject *args, PyObject *kwds)
Please notice that now we can have a path that could return NULL, are you ok for
It or should I just ignore the return code for PyDict_SetItemString?
Also, do you want me to protect the include to <xen-tools/arm-arch-capabilities.h>
with ifdef?
>
>> }
>>
>> static PyObject *pyxc_getcpuinfo(XcObject *self, PyObject *args, PyObject *kwds)
>
> --
> Best Regards,
> Marek Marczykowski-Górecki
> Invisible Things Lab
^ permalink raw reply related [flat|nested] 49+ messages in thread
* Re: [PATCH v7 07/12] xen: enable Dom0 to use SVE feature
2023-05-24 10:05 ` Bertrand Marquis
@ 2023-05-25 9:18 ` Julien Grall
0 siblings, 0 replies; 49+ messages in thread
From: Julien Grall @ 2023-05-25 9:18 UTC (permalink / raw)
To: Bertrand Marquis, Luca Fancellu
Cc: Xen-devel, Wei Chen, Andrew Cooper, George Dunlap, Jan Beulich,
Stefano Stabellini, Wei Liu, Volodymyr Babchuk
On 24/05/2023 11:05, Bertrand Marquis wrote:
> Hi Luca,
Hi,
>> On 23 May 2023, at 09:43, Luca Fancellu <Luca.Fancellu@arm.com> wrote:
>>
>> Add a command line parameter to allow Dom0 the use of SVE resources,
>> the command line parameter sve=<integer>, sub argument of dom0=,
>> controls the feature on this domain and sets the maximum SVE vector
>> length for Dom0.
>>
>> Add a new function, parse_signed_integer(), to parse an integer
>> command line argument.
>>
>> Signed-off-by: Luca Fancellu <luca.fancellu@arm.com>
>
> Reviewed-by: Bertrand Marquis <bertrand.marquis@arm.com>
>
> with ...
>
>> ---
>> Changes from v6:
>> - Fixed case for e==NULL in parse_signed_integer, drop parenthesis
>> from if conditions, delete inline sve_domctl_vl_param and rely on
>> DCE from the compiler (Jan)
>> - Drop parenthesis from opt_dom0_sve (Julien)
>> - Do not continue if 'sve' is in command line args but
>> CONFIG_ARM64_SVE is not selected:
>> https://lore.kernel.org/all/7614AE25-F59D-430A-9C3E-30B1CE0E1580@arm.com/
>> Changes from v5:
>> - stop the domain if VL error occurs (Julien, Bertrand)
>> - update the documentation
>> - Rename sve_sanitize_vl_param to sve_domctl_vl_param to
>> mark the fact that we are sanitizing a parameter coming from
>> the user before encoding it into sve_vl in domctl structure.
>> (suggestion from Bertrand in a separate discussion)
>> - update comment in parse_signed_integer, return boolean in
>> sve_domctl_vl_param (Jan).
>> Changes from v4:
>> - Negative values as user param means max supported HW VL (Jan)
>> - update documentation, make use of no_config_param(), rename
>> parse_integer into parse_signed_integer and take long long *,
>> also put a comment on the -2 return condition, update
>> declaration comment to reflect the modifications (Jan)
>> Changes from v3:
>> - Don't use fixed len types when not needed (Jan)
>> - renamed domainconfig_encode_vl to sve_encode_vl
>> - Use a sub argument of dom0= to enable the feature (Jan)
>> - Add parse_integer() function
>> Changes from v2:
>> - xen_domctl_createdomain field has changed into sve_vl and its
>> value now is the VL / 128, create an helper function for that.
>> Changes from v1:
>> - No changes
>> Changes from RFC:
>> - Changed docs to explain that the domain won't be created if the
>> requested vector length is above the supported one from the
>> platform.
>> ---
>> docs/misc/xen-command-line.pandoc | 20 ++++++++++++++++++--
>> xen/arch/arm/arm64/sve.c | 20 ++++++++++++++++++++
>> xen/arch/arm/domain_build.c | 26 ++++++++++++++++++++++++++
>> xen/arch/arm/include/asm/arm64/sve.h | 10 ++++++++++
>> xen/common/kernel.c | 28 ++++++++++++++++++++++++++++
>> xen/include/xen/lib.h | 10 ++++++++++
>> 6 files changed, 112 insertions(+), 2 deletions(-)
>>
>> diff --git a/docs/misc/xen-command-line.pandoc b/docs/misc/xen-command-line.pandoc
>> index e0b89b7d3319..47e5b4eb6199 100644
>> --- a/docs/misc/xen-command-line.pandoc
>> +++ b/docs/misc/xen-command-line.pandoc
>> @@ -777,9 +777,9 @@ Specify the bit width of the DMA heap.
>>
>> ### dom0
>> = List of [ pv | pvh, shadow=<bool>, verbose=<bool>,
>> - cpuid-faulting=<bool>, msr-relaxed=<bool> ]
>> + cpuid-faulting=<bool>, msr-relaxed=<bool> ] (x86)
>>
>> - Applicability: x86
>> + = List of [ sve=<integer> ] (Arm)
>>
>> Controls for how dom0 is constructed on x86 systems.
>>
>> @@ -838,6 +838,22 @@ Controls for how dom0 is constructed on x86 systems.
>>
>> If using this option is necessary to fix an issue, please report a bug.
>>
>> +Enables features on dom0 on Arm systems.
>> +
>> +* The `sve` integer parameter enables Arm SVE usage for Dom0 domain and sets
NIT: "Domain" is bit redundant here.
>> + the maximum SVE vector length, the option is applicable only to AArch64
>> + guests.
>
> Here i would just remove "guests", just AArch64 is enough.
> I am ok if you choose to use "AArch64 Dom0 kernels"
So far we have no use of AArch64 in our documentation. We have a few use
of Arm64 (with various uppercase).
In the code base, we seem to have a mix of AArch64 and Arm64. At the
moment, I am not going to ask for consistency in the code. But we should
aim to not introduce inconsistency in the documentation.
I don't have a strong opinion whether we should use aarch64 or arm64. My
only request is to be consistent.
Cheers,
--
Julien Grall
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [PATCH v7 09/12] tools: add physinfo arch_capabilities handling for Arm
2023-05-25 9:16 ` Luca Fancellu
@ 2023-05-25 9:21 ` Luca Fancellu
2023-05-25 10:01 ` Luca Fancellu
0 siblings, 1 reply; 49+ messages in thread
From: Luca Fancellu @ 2023-05-25 9:21 UTC (permalink / raw)
To: Marek Marczykowski-Górecki
Cc: Xen-devel, Bertrand Marquis, Wei Chen, George Dunlap,
Nick Rosbrook, Wei Liu, Anthony PERARD, Juergen Gross,
Christian Lindig, David Scott, Christian Lindig
>>
>> (...)
>>
>>> diff --git a/tools/python/xen/lowlevel/xc/xc.c b/tools/python/xen/lowlevel/xc/xc.c
>>> index 9728b34185ac..b3699fdac58e 100644
>>> --- a/tools/python/xen/lowlevel/xc/xc.c
>>> +++ b/tools/python/xen/lowlevel/xc/xc.c
>>> @@ -22,6 +22,7 @@
>>> #include <xen/hvm/hvm_info_table.h>
>>> #include <xen/hvm/params.h>
>>>
>>> +#include <xen-tools/arm-arch-capabilities.h>
>>> #include <xen-tools/common-macros.h>
>>>
>>> /* Needed for Python versions earlier than 2.3. */
>>> @@ -897,7 +898,7 @@ static PyObject *pyxc_physinfo(XcObject *self)
>>> if ( p != virt_caps )
>>> *(p-1) = '\0';
>>>
>>> - return Py_BuildValue("{s:i,s:i,s:i,s:i,s:l,s:l,s:l,s:i,s:s,s:s}",
>>> + return Py_BuildValue("{s:i,s:i,s:i,s:i,s:l,s:l,s:l,s:i,s:s,s:s,s:I}",
>>> "nr_nodes", pinfo.nr_nodes,
>>> "threads_per_core", pinfo.threads_per_core,
>>> "cores_per_socket", pinfo.cores_per_socket,
>>> @@ -907,7 +908,10 @@ static PyObject *pyxc_physinfo(XcObject *self)
>>> "scrub_memory", pages_to_kib(pinfo.scrub_pages),
>>> "cpu_khz", pinfo.cpu_khz,
>>> "hw_caps", cpu_cap,
>>> - "virt_caps", virt_caps);
>>> + "virt_caps", virt_caps,
>>> + "arm_sve_vl",
>>> + arch_capabilities_arm_sve(pinfo.arch_capabilities)
>>> + );
>>
>> This should be added only when building for ARM, similar as for other
>> bindings.
>
> Hi Marek,
>
> Thank you for taking the time to review this, are you ok if I make these changes to the code?
>
> diff --git a/tools/python/xen/lowlevel/xc/xc.c b/tools/python/xen/lowlevel/xc/xc.c
> index b3699fdac58e..c7f690189770 100644
> --- a/tools/python/xen/lowlevel/xc/xc.c
> +++ b/tools/python/xen/lowlevel/xc/xc.c
> @@ -872,6 +872,8 @@ static PyObject *pyxc_physinfo(XcObject *self)
> const char *virtcap_names[] = { "hvm", "pv" };
> const unsigned virtcaps_bits[] = { XEN_SYSCTL_PHYSCAP_hvm,
> XEN_SYSCTL_PHYSCAP_pv };
> + PyObject *objret;
> + int retcode;
>
> if ( xc_physinfo(self->xc_handle, &pinfo) != 0 )
> return pyxc_error_to_exception(self->xc_handle);
> @@ -898,20 +900,31 @@ static PyObject *pyxc_physinfo(XcObject *self)
> if ( p != virt_caps )
> *(p-1) = '\0';
>
> - return Py_BuildValue("{s:i,s:i,s:i,s:i,s:l,s:l,s:l,s:i,s:s,s:s,s:I}",
> - "nr_nodes", pinfo.nr_nodes,
> - "threads_per_core", pinfo.threads_per_core,
> - "cores_per_socket", pinfo.cores_per_socket,
> - "nr_cpus", pinfo.nr_cpus,
> - "total_memory", pages_to_kib(pinfo.total_pages),
> - "free_memory", pages_to_kib(pinfo.free_pages),
> - "scrub_memory", pages_to_kib(pinfo.scrub_pages),
> - "cpu_khz", pinfo.cpu_khz,
> - "hw_caps", cpu_cap,
> - "virt_caps", virt_caps,
> - "arm_sve_vl",
> - arch_capabilities_arm_sve(pinfo.arch_capabilities)
> + objret = Py_BuildValue("{s:i,s:i,s:i,s:i,s:l,s:l,s:l,s:i,s:s,s:s}",
> + "nr_nodes", pinfo.nr_nodes,
> + "threads_per_core", pinfo.threads_per_core,
> + "cores_per_socket", pinfo.cores_per_socket,
> + "nr_cpus", pinfo.nr_cpus,
> + "total_memory", pages_to_kib(pinfo.total_pages),
> + "free_memory", pages_to_kib(pinfo.free_pages),
> + "scrub_memory", pages_to_kib(pinfo.scrub_pages),
> + "cpu_khz", pinfo.cpu_khz,
> + "hw_caps", cpu_cap,
> + "virt_caps", virt_caps
> );
> +
> + #if defined(__aarch64__)
> + if (objret) {
> + retcode = PyDict_SetItemString(
> + objret, "arm_sve_vl",
> + arch_capabilities_arm_sve(pinfo.arch_capabilities)
> + );
> + if ( retcode < 0 )
> + return NULL;
> + }
> + #endif
> +
> + return objret;
> }
>
> static PyObject *pyxc_getcpuinfo(XcObject *self, PyObject *args, PyObject *kwds)
>
>
> Please notice that now we can have a path that could return NULL, are you ok for
> It or should I just ignore the return code for PyDict_SetItemString?
>
> Also, do you want me to protect the include to <xen-tools/arm-arch-capabilities.h>
> with ifdef?
>
EDIT: I saw this doesn’t even compile, I will ask later when I will have something working,
I saw PyDict_SetItemString is used somewhere else so I will use that approach before
Proposing you a solution
>>
>>> }
>>>
>>> static PyObject *pyxc_getcpuinfo(XcObject *self, PyObject *args, PyObject *kwds)
>>
>> --
>> Best Regards,
>> Marek Marczykowski-Górecki
>> Invisible Things Lab
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [PATCH v7 11/12] xen/arm: add sve property for dom0less domUs
2023-05-23 7:43 ` [PATCH v7 11/12] xen/arm: add sve property for dom0less domUs Luca Fancellu
2023-05-24 15:20 ` Bertrand Marquis
@ 2023-05-25 9:30 ` Julien Grall
1 sibling, 0 replies; 49+ messages in thread
From: Julien Grall @ 2023-05-25 9:30 UTC (permalink / raw)
To: xen-devel
Hi,
On 23/05/2023 08:43, Luca Fancellu wrote:
> Add a device tree property in the dom0less domU configuration
> to enable the guest to use SVE.
>
> Update documentation.
>
> Signed-off-by: Luca Fancellu <luca.fancellu@arm.com>
> ---
> Changes from v6:
> - Use ifdef in create_domUs and fail if 'sve' is used on systems
> with CONFIG_ARM64_SVE not selected (Bertrand, Julien, Jan)
> Changes from v5:
> - Stop the domain creation if SVE not supported or SVE VL
> errors (Julien, Bertrand)
> - now sve_sanitize_vl_param is renamed to sve_domctl_vl_param
> and returns a boolean, change the affected code.
> - Reworded documentation.
> Changes from v4:
> - Now it is possible to specify the property "sve" for dom0less
> device tree node without any value, that means the platform
> supported VL will be used.
> Changes from v3:
> - Now domainconfig_encode_vl is named sve_encode_vl
> Changes from v2:
> - xen_domctl_createdomain field name has changed into sve_vl
> and its value is the VL/128, use domainconfig_encode_vl
> to encode a plain VL in bits.
> Changes from v1:
> - No changes
> Changes from RFC:
> - Changed documentation
> ---
> docs/misc/arm/device-tree/booting.txt | 16 +++++++++++++++
> xen/arch/arm/domain_build.c | 28 +++++++++++++++++++++++++++
> 2 files changed, 44 insertions(+)
>
> diff --git a/docs/misc/arm/device-tree/booting.txt b/docs/misc/arm/device-tree/booting.txt
> index 3879340b5e0a..32a0e508c471 100644
> --- a/docs/misc/arm/device-tree/booting.txt
> +++ b/docs/misc/arm/device-tree/booting.txt
> @@ -193,6 +193,22 @@ with the following properties:
> Optional. Handle to a xen,cpupool device tree node that identifies the
> cpupool where the guest will be started at boot.
>
> +- sve
> +
> + Optional. The `sve` property enables Arm SVE usage for the domain and sets
> + the maximum SVE vector length, the option is applicable only to AArch64
Depending on the discussion on the other patch, s/aarch64/arm64/. With
the other comments addressed:
Acked-by: Julien Grall <jgrall@amazon.com>
> + guests.
> + A value equal to 0 disables the feature, this is the default value.
> + Specifying this property with no value, means that the SVE vector length
> + will be set equal to the maximum vector length supported by the platform.
> + Values above 0 explicitly set the maximum SVE vector length for the domain,
> + allowed values are from 128 to maximum 2048, being multiple of 128.
> + Please note that when the user explicitly specifies the value, if that value
> + is above the hardware supported maximum SVE vector length, the domain
> + creation will fail and the system will stop, the same will occur if the
> + option is provided with a non zero value, but the platform doesn't support
> + SVE.
> +
> - xen,enhanced
>
> A string property. Possible property values are:
> diff --git a/xen/arch/arm/domain_build.c b/xen/arch/arm/domain_build.c
> index 9202a96d9c28..ba4fe9e165ee 100644
> --- a/xen/arch/arm/domain_build.c
> +++ b/xen/arch/arm/domain_build.c
> @@ -4008,6 +4008,34 @@ void __init create_domUs(void)
> d_cfg.max_maptrack_frames = val;
> }
>
> + if ( dt_get_property(node, "sve", &val) )
> + {
> +#ifdef CONFIG_ARM64_SVE
> + unsigned int sve_vl_bits;
> + bool ret = false;
> +
> + if ( !val )
> + {
> + /* Property found with no value, means max HW VL supported */
> + ret = sve_domctl_vl_param(-1, &sve_vl_bits);
> + }
> + else
> + {
> + if ( dt_property_read_u32(node, "sve", &val) )
> + ret = sve_domctl_vl_param(val, &sve_vl_bits);
> + else
> + panic("Error reading 'sve' property");
> + }
> +
> + if ( ret )
> + d_cfg.arch.sve_vl = sve_encode_vl(sve_vl_bits);
> + else
> + panic("SVE vector length error\n");
> +#else
> + panic("'sve' property found, but CONFIG_ARM64_SVE not selected");
> +#endif
> + }
> +
> /*
> * The variable max_init_domid is initialized with zero, so here it's
> * very important to use the pre-increment operator to call
--
Julien Grall
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [PATCH v7 12/12] xen/changelog: Add SVE and "dom0" options to the changelog for Arm
2023-05-23 7:43 ` [PATCH v7 12/12] xen/changelog: Add SVE and "dom0" options to the changelog for Arm Luca Fancellu
2023-05-24 15:22 ` Bertrand Marquis
@ 2023-05-25 9:41 ` Julien Grall
1 sibling, 0 replies; 49+ messages in thread
From: Julien Grall @ 2023-05-25 9:41 UTC (permalink / raw)
To: Luca Fancellu, xen-devel
Cc: bertrand.marquis, wei.chen, Henry Wang, Community Manager,
Andrew Cooper, George Dunlap, Jan Beulich, Stefano Stabellini,
Wei Liu
Hi,
On 23/05/2023 08:43, Luca Fancellu wrote:
> Arm now can use the "dom0=" Xen command line option and the support
> for guests running SVE instructions is added, put entries in the
> changelog.
>
> Mention the "Tech Preview" status and add an entry in SUPPORT.md
>
> Signed-off-by: Luca Fancellu <luca.fancellu@arm.com>
> Acked-by: Henry Wang <Henry.Wang@arm.com> # CHANGELOG
> ---
> Changes from v6:
> - Add Henry's A-by to CHANGELOG
> Changes from v5:
> - Add Tech Preview status and add entry in SUPPORT.md (Bertrand)
> Changes from v4:
> - No changes
> Change from v3:
> - new patch
> ---
> CHANGELOG.md | 3 +++
> SUPPORT.md | 6 ++++++
> 2 files changed, 9 insertions(+)
>
> diff --git a/CHANGELOG.md b/CHANGELOG.md
> index 5bfd3aa5c0d5..512b7bdc0fcb 100644
> --- a/CHANGELOG.md
> +++ b/CHANGELOG.md
> @@ -11,6 +11,8 @@ The format is based on [Keep a Changelog](https://keepachangelog.com/en/1.0.0/)
> cap toolstack provided values.
> - Ignore VCPUOP_set_singleshot_timer's VCPU_SSHOTTMR_future flag. The only
> known user doesn't use it properly, leading to in-guest breakage.
> + - The "dom0" option is now supported on Arm and "sve=" sub-option can be used
> + to enable dom0 guest to use SVE/SVE2 instructions.
>
> ### Added
> - On x86, support for features new in Intel Sapphire Rapids CPUs:
> @@ -20,6 +22,7 @@ The format is based on [Keep a Changelog](https://keepachangelog.com/en/1.0.0/)
> - Bus-lock detection, used by Xen to mitigate (by rate-limiting) the system
> wide impact of a guest misusing atomic instructions.
> - xl/libxl can customize SMBIOS strings for HVM guests.
> + - On Arm, Xen supports guests running SVE/SVE2 instructions. (Tech Preview)
>
> ## [4.17.0](https://xenbits.xen.org/gitweb/?p=xen.git;a=shortlog;h=RELEASE-4.17.0) - 2022-12-12
>
> diff --git a/SUPPORT.md b/SUPPORT.md
> index 6dbed9d5d029..e0fa2246807b 100644
> --- a/SUPPORT.md
> +++ b/SUPPORT.md
> @@ -99,6 +99,12 @@ Extension to the GICv3 interrupt controller to support MSI.
>
> Status: Experimental
>
> +### ARM Scalable Vector Extension (SVE/SVE2)
> +
> +AArch64 guest can use Scalable Vector Extension (SVE/SVE2).
I think we should cover dom0 here as well. So s/guest/domain/.
Also, we don't use AArch64 in SUPPORT.MD so far. So please use
ARM64/arm64. At some point we will need to do some renaming for consistency.
Cheers,
--
Julien Grall
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [PATCH v7 05/12] arm/sve: save/restore SVE context switch
2023-05-25 9:09 ` Julien Grall
@ 2023-05-25 10:01 ` Luca Fancellu
2023-05-25 10:07 ` Julien Grall
0 siblings, 1 reply; 49+ messages in thread
From: Luca Fancellu @ 2023-05-25 10:01 UTC (permalink / raw)
To: Julien Grall
Cc: Xen-devel, Bertrand Marquis, Wei Chen, Stefano Stabellini,
Volodymyr Babchuk
> On 25 May 2023, at 10:09, Julien Grall <julien@xen.org> wrote:
>
> Hi Luca,
>
> On 23/05/2023 08:43, Luca Fancellu wrote:
>> +int sve_context_init(struct vcpu *v)
>> +{
>> + unsigned int sve_vl_bits = sve_decode_vl(v->domain->arch.sve_vl);
>> + uint64_t *ctx = _xzalloc(sve_zreg_ctx_size(sve_vl_bits) +
>> + sve_ffrreg_ctx_size(sve_vl_bits),
>> + L1_CACHE_BYTES);
>> +
>> + if ( !ctx )
>> + return -ENOMEM;
>> +
>> + /*
>> + * Point to the end of Z0-Z31 memory, just before FFR memory, to be kept in
>> + * sync with sve_context_free()
>
> Nit: Missing a full stop.
I’ll fix
>
>> + */
>> + v->arch.vfp.sve_zreg_ctx_end = ctx +
>> + (sve_zreg_ctx_size(sve_vl_bits) / sizeof(uint64_t));
>> +
>> + v->arch.zcr_el2 = vl_to_zcr(sve_vl_bits);
>> +
>> + return 0;
>> +}
>> +
>> +void sve_context_free(struct vcpu *v)
>> +{
>> + unsigned int sve_vl_bits;
>> +
>> + if ( v->arch.vfp.sve_zreg_ctx_end )
>> + return;
>> +
>> + sve_vl_bits = sve_decode_vl(v->domain->arch.sve_vl);
>> +
>> + /*
>> + * Point to the end of Z0-Z31 memory, just before FFR memory, to be kept
>> + * in sync with sve_context_init()
>> + */
>
> The spacing looks a bit odd in this comment. Did you miss an extra space?
>
> Also, I notice this comment is the exact same as on top as sve_context_init(). I think this is a bit misleading because the logic is different. I would suggest the following:
>
> "Currently points to the end of Z0-Z31 memory which is not the start of the buffer. To be kept in sync with the sve_context_init()."
>
> Lastly, nit: Missing a full stop.
Ok I’ll change it
>
>> + v->arch.vfp.sve_zreg_ctx_end -=
>> + (sve_zreg_ctx_size(sve_vl_bits) / sizeof(uint64_t));
>> +
>> + XFREE(v->arch.vfp.sve_zreg_ctx_end);
>> +}
>> +
>
> [...]
>
>> diff --git a/xen/arch/arm/include/asm/arm64/vfp.h b/xen/arch/arm/include/asm/arm64/vfp.h
>> index e6e8c363bc16..4aa371e85d26 100644
>> --- a/xen/arch/arm/include/asm/arm64/vfp.h
>> +++ b/xen/arch/arm/include/asm/arm64/vfp.h
>> @@ -6,7 +6,19 @@
>> struct vfp_state
>> {
>> + /*
>> + * When SVE is enabled for the guest, fpregs memory will be used to
>> + * save/restore P0-P15 registers, otherwise it will be used for the V0-V31
>> + * registers.
>> + */
>> uint64_t fpregs[64] __vfp_aligned;
>> + /*
>> + * When SVE is enabled for the guest, sve_zreg_ctx_end points to memory
>> + * where Z0-Z31 registers and FFR can be saved/restored, it points at the
>> + * end of the Z0-Z31 space and at the beginning of the FFR space, it's done
>> + * like that to ease the save/restore assembly operations.
>> + */
>> + uint64_t *sve_zreg_ctx_end;
>
> Sorry I only noticed now. But shouldn't this be protected with #ifdef CONFIG_SVE? Same...
>
>> register_t fpcr;
>> register_t fpexc32_el2;
>> register_t fpsr;
>> diff --git a/xen/arch/arm/include/asm/domain.h b/xen/arch/arm/include/asm/domain.h
>> index 331da0f3bcc3..814652d92568 100644
>> --- a/xen/arch/arm/include/asm/domain.h
>> +++ b/xen/arch/arm/include/asm/domain.h
>> @@ -195,6 +195,8 @@ struct arch_vcpu
>> register_t tpidrro_el0;
>> /* HYP configuration */
>> + register_t zcr_el1;
>> + register_t zcr_el2;
>
> ... here.
Sure I can protect them. It was done on purpose before to avoid ifdefs but I think saving space
is better here and also there won’t be any use of them when the config is off.
>
>> register_t cptr_el2;
>> register_t hcr_el2;
>> register_t mdcr_el2;
>
> Cheers,
>
> --
> Julien Grall
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [PATCH v7 09/12] tools: add physinfo arch_capabilities handling for Arm
2023-05-25 9:21 ` Luca Fancellu
@ 2023-05-25 10:01 ` Luca Fancellu
0 siblings, 0 replies; 49+ messages in thread
From: Luca Fancellu @ 2023-05-25 10:01 UTC (permalink / raw)
To: Marek Marczykowski-Górecki
Cc: Xen-devel, Bertrand Marquis, Wei Chen, George Dunlap,
Nick Rosbrook, Wei Liu, Anthony PERARD, Juergen Gross,
Christian Lindig, David Scott, Christian Lindig
> On 25 May 2023, at 10:21, Luca Fancellu <Luca.Fancellu@arm.com> wrote:
>
>>>
>>> (...)
>>>
>>>> diff --git a/tools/python/xen/lowlevel/xc/xc.c b/tools/python/xen/lowlevel/xc/xc.c
>>>> index 9728b34185ac..b3699fdac58e 100644
>>>> --- a/tools/python/xen/lowlevel/xc/xc.c
>>>> +++ b/tools/python/xen/lowlevel/xc/xc.c
>>>> @@ -22,6 +22,7 @@
>>>> #include <xen/hvm/hvm_info_table.h>
>>>> #include <xen/hvm/params.h>
>>>>
>>>> +#include <xen-tools/arm-arch-capabilities.h>
>>>> #include <xen-tools/common-macros.h>
>>>>
>>>> /* Needed for Python versions earlier than 2.3. */
>>>> @@ -897,7 +898,7 @@ static PyObject *pyxc_physinfo(XcObject *self)
>>>> if ( p != virt_caps )
>>>> *(p-1) = '\0';
>>>>
>>>> - return Py_BuildValue("{s:i,s:i,s:i,s:i,s:l,s:l,s:l,s:i,s:s,s:s}",
>>>> + return Py_BuildValue("{s:i,s:i,s:i,s:i,s:l,s:l,s:l,s:i,s:s,s:s,s:I}",
>>>> "nr_nodes", pinfo.nr_nodes,
>>>> "threads_per_core", pinfo.threads_per_core,
>>>> "cores_per_socket", pinfo.cores_per_socket,
>>>> @@ -907,7 +908,10 @@ static PyObject *pyxc_physinfo(XcObject *self)
>>>> "scrub_memory", pages_to_kib(pinfo.scrub_pages),
>>>> "cpu_khz", pinfo.cpu_khz,
>>>> "hw_caps", cpu_cap,
>>>> - "virt_caps", virt_caps);
>>>> + "virt_caps", virt_caps,
>>>> + "arm_sve_vl",
>>>> + arch_capabilities_arm_sve(pinfo.arch_capabilities)
>>>> + );
>>>
>>> This should be added only when building for ARM, similar as for other
>>> bindings.
>>
>> Hi Marek,
>>
>> Thank you for taking the time to review this, are you ok if I make these changes to the code?
>>
>> diff --git a/tools/python/xen/lowlevel/xc/xc.c b/tools/python/xen/lowlevel/xc/xc.c
>> index b3699fdac58e..c7f690189770 100644
>> --- a/tools/python/xen/lowlevel/xc/xc.c
>> +++ b/tools/python/xen/lowlevel/xc/xc.c
>> @@ -872,6 +872,8 @@ static PyObject *pyxc_physinfo(XcObject *self)
>> const char *virtcap_names[] = { "hvm", "pv" };
>> const unsigned virtcaps_bits[] = { XEN_SYSCTL_PHYSCAP_hvm,
>> XEN_SYSCTL_PHYSCAP_pv };
>> + PyObject *objret;
>> + int retcode;
>>
>> if ( xc_physinfo(self->xc_handle, &pinfo) != 0 )
>> return pyxc_error_to_exception(self->xc_handle);
>> @@ -898,20 +900,31 @@ static PyObject *pyxc_physinfo(XcObject *self)
>> if ( p != virt_caps )
>> *(p-1) = '\0';
>>
>> - return Py_BuildValue("{s:i,s:i,s:i,s:i,s:l,s:l,s:l,s:i,s:s,s:s,s:I}",
>> - "nr_nodes", pinfo.nr_nodes,
>> - "threads_per_core", pinfo.threads_per_core,
>> - "cores_per_socket", pinfo.cores_per_socket,
>> - "nr_cpus", pinfo.nr_cpus,
>> - "total_memory", pages_to_kib(pinfo.total_pages),
>> - "free_memory", pages_to_kib(pinfo.free_pages),
>> - "scrub_memory", pages_to_kib(pinfo.scrub_pages),
>> - "cpu_khz", pinfo.cpu_khz,
>> - "hw_caps", cpu_cap,
>> - "virt_caps", virt_caps,
>> - "arm_sve_vl",
>> - arch_capabilities_arm_sve(pinfo.arch_capabilities)
>> + objret = Py_BuildValue("{s:i,s:i,s:i,s:i,s:l,s:l,s:l,s:i,s:s,s:s}",
>> + "nr_nodes", pinfo.nr_nodes,
>> + "threads_per_core", pinfo.threads_per_core,
>> + "cores_per_socket", pinfo.cores_per_socket,
>> + "nr_cpus", pinfo.nr_cpus,
>> + "total_memory", pages_to_kib(pinfo.total_pages),
>> + "free_memory", pages_to_kib(pinfo.free_pages),
>> + "scrub_memory", pages_to_kib(pinfo.scrub_pages),
>> + "cpu_khz", pinfo.cpu_khz,
>> + "hw_caps", cpu_cap,
>> + "virt_caps", virt_caps
>> );
>> +
>> + #if defined(__aarch64__)
>> + if (objret) {
>> + retcode = PyDict_SetItemString(
>> + objret, "arm_sve_vl",
>> + arch_capabilities_arm_sve(pinfo.arch_capabilities)
>> + );
>> + if ( retcode < 0 )
>> + return NULL;
>> + }
>> + #endif
>> +
>> + return objret;
>> }
>>
>> static PyObject *pyxc_getcpuinfo(XcObject *self, PyObject *args, PyObject *kwds)
>>
>>
>> Please notice that now we can have a path that could return NULL, are you ok for
>> It or should I just ignore the return code for PyDict_SetItemString?
>>
>> Also, do you want me to protect the include to <xen-tools/arm-arch-capabilities.h>
>> with ifdef?
>>
>
> EDIT: I saw this doesn’t even compile, I will ask later when I will have something working,
> I saw PyDict_SetItemString is used somewhere else so I will use that approach before
> Proposing you a solution
>
>
Ok, so this is my proposed solution:
diff --git a/tools/python/xen/lowlevel/xc/xc.c b/tools/python/xen/lowlevel/xc/xc.c
index b3699fdac58e..e52aa88f3c5f 100644
--- a/tools/python/xen/lowlevel/xc/xc.c
+++ b/tools/python/xen/lowlevel/xc/xc.c
@@ -872,6 +872,7 @@ static PyObject *pyxc_physinfo(XcObject *self)
const char *virtcap_names[] = { "hvm", "pv" };
const unsigned virtcaps_bits[] = { XEN_SYSCTL_PHYSCAP_hvm,
XEN_SYSCTL_PHYSCAP_pv };
+ PyObject *objret;
if ( xc_physinfo(self->xc_handle, &pinfo) != 0 )
return pyxc_error_to_exception(self->xc_handle);
@@ -898,20 +899,36 @@ static PyObject *pyxc_physinfo(XcObject *self)
if ( p != virt_caps )
*(p-1) = '\0';
- return Py_BuildValue("{s:i,s:i,s:i,s:i,s:l,s:l,s:l,s:i,s:s,s:s,s:I}",
- "nr_nodes", pinfo.nr_nodes,
- "threads_per_core", pinfo.threads_per_core,
- "cores_per_socket", pinfo.cores_per_socket,
- "nr_cpus", pinfo.nr_cpus,
- "total_memory", pages_to_kib(pinfo.total_pages),
- "free_memory", pages_to_kib(pinfo.free_pages),
- "scrub_memory", pages_to_kib(pinfo.scrub_pages),
- "cpu_khz", pinfo.cpu_khz,
- "hw_caps", cpu_cap,
- "virt_caps", virt_caps,
- "arm_sve_vl",
- arch_capabilities_arm_sve(pinfo.arch_capabilities)
+ objret = Py_BuildValue("{s:i,s:i,s:i,s:i,s:l,s:l,s:l,s:i,s:s,s:s}",
+ "nr_nodes", pinfo.nr_nodes,
+ "threads_per_core", pinfo.threads_per_core,
+ "cores_per_socket", pinfo.cores_per_socket,
+ "nr_cpus", pinfo.nr_cpus,
+ "total_memory", pages_to_kib(pinfo.total_pages),
+ "free_memory", pages_to_kib(pinfo.free_pages),
+ "scrub_memory", pages_to_kib(pinfo.scrub_pages),
+ "cpu_khz", pinfo.cpu_khz,
+ "hw_caps", cpu_cap,
+ "virt_caps", virt_caps
);
+
+ #if defined(__aarch64__)
+ if ( objret ) {
+ unsigned int sve_vl_bits;
+ PyObject *py_arm_sve_vl;
+
+ sve_vl_bits = arch_capabilities_arm_sve(pinfo.arch_capabilities);
+ py_arm_sve_vl = PyLong_FromUnsignedLong(sve_vl_bits);
+
+ if ( !py_arm_sve_vl )
+ return NULL;
+
+ if( PyDict_SetItemString(objret, "arm_sve_vl", py_arm_sve_vl) )
+ return NULL;
+ }
+ #endif
+
+ return objret;
}
static PyObject *pyxc_getcpuinfo(XcObject *self, PyObject *args, PyObject *kwds)
Would it work for you?
>
>>>
>>>> }
>>>>
>>>> static PyObject *pyxc_getcpuinfo(XcObject *self, PyObject *args, PyObject *kwds)
>>>
>>> --
>>> Best Regards,
>>> Marek Marczykowski-Górecki
>>> Invisible Things Lab
^ permalink raw reply related [flat|nested] 49+ messages in thread
* Re: [PATCH v7 05/12] arm/sve: save/restore SVE context switch
2023-05-25 10:01 ` Luca Fancellu
@ 2023-05-25 10:07 ` Julien Grall
0 siblings, 0 replies; 49+ messages in thread
From: Julien Grall @ 2023-05-25 10:07 UTC (permalink / raw)
To: Luca Fancellu
Cc: Xen-devel, Bertrand Marquis, Wei Chen, Stefano Stabellini,
Volodymyr Babchuk
Hi Luca,
On 25/05/2023 11:01, Luca Fancellu wrote:
>> On 25 May 2023, at 10:09, Julien Grall <julien@xen.org> wrote:
>>> diff --git a/xen/arch/arm/include/asm/arm64/vfp.h b/xen/arch/arm/include/asm/arm64/vfp.h
>>> index e6e8c363bc16..4aa371e85d26 100644
>>> --- a/xen/arch/arm/include/asm/arm64/vfp.h
>>> +++ b/xen/arch/arm/include/asm/arm64/vfp.h
>>> @@ -6,7 +6,19 @@
>>> struct vfp_state
>>> {
>>> + /*
>>> + * When SVE is enabled for the guest, fpregs memory will be used to
>>> + * save/restore P0-P15 registers, otherwise it will be used for the V0-V31
>>> + * registers.
>>> + */
>>> uint64_t fpregs[64] __vfp_aligned;
>>> + /*
>>> + * When SVE is enabled for the guest, sve_zreg_ctx_end points to memory
>>> + * where Z0-Z31 registers and FFR can be saved/restored, it points at the
>>> + * end of the Z0-Z31 space and at the beginning of the FFR space, it's done
>>> + * like that to ease the save/restore assembly operations.
>>> + */
>>> + uint64_t *sve_zreg_ctx_end;
>>
>> Sorry I only noticed now. But shouldn't this be protected with #ifdef CONFIG_SVE? Same...
>>
>>> register_t fpcr;
>>> register_t fpexc32_el2;
>>> register_t fpsr;
>>> diff --git a/xen/arch/arm/include/asm/domain.h b/xen/arch/arm/include/asm/domain.h
>>> index 331da0f3bcc3..814652d92568 100644
>>> --- a/xen/arch/arm/include/asm/domain.h
>>> +++ b/xen/arch/arm/include/asm/domain.h
>>> @@ -195,6 +195,8 @@ struct arch_vcpu
>>> register_t tpidrro_el0;
>>> /* HYP configuration */
>>> + register_t zcr_el1;
>>> + register_t zcr_el2;
>>
>> ... here.
>
> Sure I can protect them. It was done on purpose before to avoid ifdefs but I think saving space
> is better here and also there won’t be any use of them when the config is off.
I wasn't thinking about saving space. I was more thinking about catching
any (mis)use of the fields in common code. With the #ifdef, the
compilation would fail.
Cheers,
--
Julien Grall
^ permalink raw reply [flat|nested] 49+ messages in thread
end of thread, other threads:[~2023-05-25 10:07 UTC | newest]
Thread overview: 49+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2023-05-23 7:43 [PATCH v7 00/12] SVE feature for arm guests Luca Fancellu
2023-05-23 7:43 ` [PATCH v7 01/12] xen/arm: enable SVE extension for Xen Luca Fancellu
2023-05-24 9:01 ` Bertrand Marquis
2023-05-24 9:58 ` Julien Grall
2023-05-24 14:30 ` Bertrand Marquis
2023-05-25 8:57 ` Julien Grall
2023-05-25 8:58 ` Julien Grall
2023-05-23 7:43 ` [PATCH v7 02/12] xen/arm: add SVE vector length field to the domain Luca Fancellu
2023-05-24 9:23 ` Bertrand Marquis
2023-05-25 8:59 ` Julien Grall
2023-05-23 7:43 ` [PATCH v7 03/12] xen/arm: Expose SVE feature to the guest Luca Fancellu
2023-05-24 9:25 ` Bertrand Marquis
2023-05-23 7:43 ` [PATCH v7 04/12] xen/arm: add SVE exception class handling Luca Fancellu
2023-05-23 7:43 ` [PATCH v7 05/12] arm/sve: save/restore SVE context switch Luca Fancellu
2023-05-24 9:47 ` Bertrand Marquis
2023-05-24 9:55 ` Luca Fancellu
2023-05-25 9:09 ` Julien Grall
2023-05-25 10:01 ` Luca Fancellu
2023-05-25 10:07 ` Julien Grall
2023-05-23 7:43 ` [PATCH v7 06/12] xen/common: add dom0 xen command line argument for Arm Luca Fancellu
2023-05-23 7:43 ` [PATCH v7 07/12] xen: enable Dom0 to use SVE feature Luca Fancellu
2023-05-23 10:02 ` Jan Beulich
2023-05-23 10:21 ` Luca Fancellu
2023-05-23 10:31 ` Jan Beulich
2023-05-23 11:50 ` Luca Fancellu
2023-05-23 11:53 ` Jan Beulich
2023-05-23 11:57 ` Luca Fancellu
2023-05-23 12:40 ` Jan Beulich
2023-05-24 10:05 ` Bertrand Marquis
2023-05-25 9:18 ` Julien Grall
2023-05-23 7:43 ` [PATCH v7 08/12] xen/physinfo: encode Arm SVE vector length in arch_capabilities Luca Fancellu
2023-05-23 7:43 ` [PATCH v7 09/12] tools: add physinfo arch_capabilities handling for Arm Luca Fancellu
2023-05-25 8:39 ` Marek Marczykowski-Górecki
2023-05-25 9:16 ` Luca Fancellu
2023-05-25 9:21 ` Luca Fancellu
2023-05-25 10:01 ` Luca Fancellu
2023-05-23 7:43 ` [PATCH v7 10/12] xen/tools: add sve parameter in XL configuration Luca Fancellu
2023-05-23 16:49 ` Anthony PERARD
2023-05-23 7:43 ` [PATCH v7 11/12] xen/arm: add sve property for dom0less domUs Luca Fancellu
2023-05-24 15:20 ` Bertrand Marquis
2023-05-25 8:52 ` Michal Orzel
2023-05-25 8:55 ` Luca Fancellu
2023-05-25 9:03 ` Bertrand Marquis
2023-05-25 9:03 ` Michal Orzel
2023-05-25 9:30 ` Julien Grall
2023-05-23 7:43 ` [PATCH v7 12/12] xen/changelog: Add SVE and "dom0" options to the changelog for Arm Luca Fancellu
2023-05-24 15:22 ` Bertrand Marquis
2023-05-25 9:41 ` Julien Grall
2023-05-25 8:15 ` [PATCH v7 00/12] SVE feature for arm guests Luca Fancellu
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