* [PATCH 1/2] target/riscv: Lower bound of VLEN is 32, and check VLEN >= ELEN
@ 2022-07-08 7:39 Kito Cheng
2022-07-08 7:39 ` [PATCH 2/2] target/riscv: Auto set elen from vector extension by default Kito Cheng
` (2 more replies)
0 siblings, 3 replies; 7+ messages in thread
From: Kito Cheng @ 2022-07-08 7:39 UTC (permalink / raw)
To: alistair.francis, palmer, frank.chang, qemu-devel, qemu-riscv, liweiwei
Cc: Kito Cheng
According RVV spec 1.0, the minmal requirement of VLEN is great than or
equal to ELEN, and minmal possible ELEN is 32, and also spec has mention
`Minimum VLEN` for zve32* is 32, so the lower bound of VLEN is 32 I
think.
[1] https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#2-implementation-defined-constant-parameters
[2] https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#182-zve-vector-extensions-for-embedded-processors
Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
---
target/riscv/cpu.c | 10 ++++++++--
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 1bb3973806..487d0faa63 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -740,10 +740,10 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
"Vector extension VLEN must be power of 2");
return;
}
- if (cpu->cfg.vlen > RV_VLEN_MAX || cpu->cfg.vlen < 128) {
+ if (cpu->cfg.vlen > RV_VLEN_MAX || cpu->cfg.vlen < 32) {
error_setg(errp,
"Vector extension implementation only supports VLEN "
- "in the range [128, %d]", RV_VLEN_MAX);
+ "in the range [32, %d]", RV_VLEN_MAX);
return;
}
if (!is_power_of_2(cpu->cfg.elen)) {
@@ -757,6 +757,12 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
"in the range [8, 64]");
return;
}
+ if (cpu->cfg.vlen < cpu->cfg.elen) {
+ error_setg(errp,
+ "Vector extension VLEN must be greater than or equal "
+ "to ELEN");
+ return;
+ }
if (cpu->cfg.vext_spec) {
if (!g_strcmp0(cpu->cfg.vext_spec, "v1.0")) {
vext_version = VEXT_VERSION_1_00_0;
--
2.34.0
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH 2/2] target/riscv: Auto set elen from vector extension by default
2022-07-08 7:39 [PATCH 1/2] target/riscv: Lower bound of VLEN is 32, and check VLEN >= ELEN Kito Cheng
@ 2022-07-08 7:39 ` Kito Cheng
2022-07-09 8:11 ` Weiwei Li
2022-07-11 8:13 ` Frank Chang
2022-07-09 8:30 ` [PATCH 1/2] target/riscv: Lower bound of VLEN is 32, and check VLEN >= ELEN Weiwei Li
2022-07-09 9:48 ` Weiwei Li
2 siblings, 2 replies; 7+ messages in thread
From: Kito Cheng @ 2022-07-08 7:39 UTC (permalink / raw)
To: alistair.francis, palmer, frank.chang, qemu-devel, qemu-riscv, liweiwei
Cc: Kito Cheng
Default ELEN is setting to 64 for now, which is incorrect setting for
Zve32*, and spec has mention minimum VLEN and supported EEW in chapter
"Zve*: Vector Extensions for Embedded Processors" is 32 for Zve32.
ELEN actaully could be derived from which extensions are enabled,
so this patch set elen to 0 as auto detect, and keep the capability to
let user could configure that.
Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
---
target/riscv/cpu.c | 16 +++++++++++++---
1 file changed, 13 insertions(+), 3 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 487d0faa63..c1b96da7da 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -751,13 +751,22 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
"Vector extension ELEN must be power of 2");
return;
}
- if (cpu->cfg.elen > 64 || cpu->cfg.vlen < 8) {
+ if (cpu->cfg.elen == 0) {
+ if (cpu->cfg.ext_zve32f) {
+ cpu->cfg.elen = 32;
+ }
+ if (cpu->cfg.ext_zve64f || cpu->cfg.ext_v) {
+ cpu->cfg.elen = 64;
+ }
+ }
+ if (cpu->cfg.elen != 0 && (cpu->cfg.elen > 64 ||
+ cpu->cfg.elen < 8)) {
error_setg(errp,
"Vector extension implementation only supports ELEN "
"in the range [8, 64]");
return;
}
- if (cpu->cfg.vlen < cpu->cfg.elen) {
+ if (cpu->cfg.elen != 0 && cpu->cfg.vlen < cpu->cfg.elen) {
error_setg(errp,
"Vector extension VLEN must be greater than or equal "
"to ELEN");
@@ -901,7 +910,8 @@ static Property riscv_cpu_extensions[] = {
DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec),
DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec),
DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128),
- DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64),
+ /* elen = 0 means set from v or zve* extension */
+ DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 0),
DEFINE_PROP_BOOL("svinval", RISCVCPU, cfg.ext_svinval, false),
DEFINE_PROP_BOOL("svnapot", RISCVCPU, cfg.ext_svnapot, false),
--
2.34.0
^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [PATCH 2/2] target/riscv: Auto set elen from vector extension by default
2022-07-08 7:39 ` [PATCH 2/2] target/riscv: Auto set elen from vector extension by default Kito Cheng
@ 2022-07-09 8:11 ` Weiwei Li
2022-07-09 9:53 ` Weiwei Li
2022-07-11 8:13 ` Frank Chang
1 sibling, 1 reply; 7+ messages in thread
From: Weiwei Li @ 2022-07-09 8:11 UTC (permalink / raw)
To: Kito Cheng, alistair.francis, palmer, frank.chang, qemu-devel,
qemu-riscv, liweiwei
在 2022/7/8 下午3:39, Kito Cheng 写道:
> Default ELEN is setting to 64 for now, which is incorrect setting for
> Zve32*, and spec has mention minimum VLEN and supported EEW in chapter
> "Zve*: Vector Extensions for Embedded Processors" is 32 for Zve32.
>
> ELEN actaully could be derived from which extensions are enabled,
> so this patch set elen to 0 as auto detect, and keep the capability to
> let user could configure that.
>
> Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
> ---
> target/riscv/cpu.c | 16 +++++++++++++---
> 1 file changed, 13 insertions(+), 3 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 487d0faa63..c1b96da7da 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -751,13 +751,22 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
> "Vector extension ELEN must be power of 2");
> return;
> }
> - if (cpu->cfg.elen > 64 || cpu->cfg.vlen < 8) {
> + if (cpu->cfg.elen == 0) {
> + if (cpu->cfg.ext_zve32f) {
> + cpu->cfg.elen = 32;
> + }
> + if (cpu->cfg.ext_zve64f || cpu->cfg.ext_v) {
> + cpu->cfg.elen = 64;
> + }
This code is in the "if(cpu->cfg.ext_v){...}", so "cpu->cfg.ext_zve64f
|| cpu->cfg.ext_v" will always be true.
It can use "else ... " directly.
> + }
> + if (cpu->cfg.elen != 0 && (cpu->cfg.elen > 64 ||
> + cpu->cfg.elen < 8)) {
> error_setg(errp,
> "Vector extension implementation only supports ELEN "
> "in the range [8, 64]");
> return;
> }
> - if (cpu->cfg.vlen < cpu->cfg.elen) {
> + if (cpu->cfg.elen != 0 && cpu->cfg.vlen < cpu->cfg.elen) {
when cfg.elen is set to zero, it will be changed to the auto detect
value(32/64) before this two check.
So this two modifications seem unnecessary.
Regards,
Weiwei Li
> error_setg(errp,
> "Vector extension VLEN must be greater than or equal "
> "to ELEN");
> @@ -901,7 +910,8 @@ static Property riscv_cpu_extensions[] = {
> DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec),
> DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec),
> DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128),
> - DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64),
> + /* elen = 0 means set from v or zve* extension */
> + DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 0),
>
> DEFINE_PROP_BOOL("svinval", RISCVCPU, cfg.ext_svinval, false),
> DEFINE_PROP_BOOL("svnapot", RISCVCPU, cfg.ext_svnapot, false),
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH 1/2] target/riscv: Lower bound of VLEN is 32, and check VLEN >= ELEN
2022-07-08 7:39 [PATCH 1/2] target/riscv: Lower bound of VLEN is 32, and check VLEN >= ELEN Kito Cheng
2022-07-08 7:39 ` [PATCH 2/2] target/riscv: Auto set elen from vector extension by default Kito Cheng
@ 2022-07-09 8:30 ` Weiwei Li
2022-07-09 9:48 ` Weiwei Li
2 siblings, 0 replies; 7+ messages in thread
From: Weiwei Li @ 2022-07-09 8:30 UTC (permalink / raw)
To: Kito Cheng, alistair.francis, palmer, frank.chang, qemu-devel,
qemu-riscv, liweiwei
在 2022/7/8 下午3:39, Kito Cheng 写道:
> According RVV spec 1.0, the minmal requirement of VLEN is great than or
> equal to ELEN, and minmal possible ELEN is 32, and also spec has mention
> `Minimum VLEN` for zve32* is 32, so the lower bound of VLEN is 32 I
> think.
Sorry. I have a question about how to decide the minmal possible ELEN to
be 32?
In current implementation, elen should be in the range [8, 64](and there
seems to be a typo in the check for this).
If the minmal possible ELEN is 32, maybe we need change the check to
"elen >= 32" too.
Regards,
Weiwei Li
> [1] https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#2-implementation-defined-constant-parameters
> [2] https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#182-zve-vector-extensions-for-embedded-processors
>
> Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
> ---
> target/riscv/cpu.c | 10 ++++++++--
> 1 file changed, 8 insertions(+), 2 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 1bb3973806..487d0faa63 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -740,10 +740,10 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
> "Vector extension VLEN must be power of 2");
> return;
> }
> - if (cpu->cfg.vlen > RV_VLEN_MAX || cpu->cfg.vlen < 128) {
> + if (cpu->cfg.vlen > RV_VLEN_MAX || cpu->cfg.vlen < 32) {
> error_setg(errp,
> "Vector extension implementation only supports VLEN "
> - "in the range [128, %d]", RV_VLEN_MAX);
> + "in the range [32, %d]", RV_VLEN_MAX);
> return;
> }
> if (!is_power_of_2(cpu->cfg.elen)) {
> @@ -757,6 +757,12 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
> "in the range [8, 64]");
> return;
> }
> + if (cpu->cfg.vlen < cpu->cfg.elen) {
> + error_setg(errp,
> + "Vector extension VLEN must be greater than or equal "
> + "to ELEN");
> + return;
> + }
> if (cpu->cfg.vext_spec) {
> if (!g_strcmp0(cpu->cfg.vext_spec, "v1.0")) {
> vext_version = VEXT_VERSION_1_00_0;
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH 1/2] target/riscv: Lower bound of VLEN is 32, and check VLEN >= ELEN
2022-07-08 7:39 [PATCH 1/2] target/riscv: Lower bound of VLEN is 32, and check VLEN >= ELEN Kito Cheng
2022-07-08 7:39 ` [PATCH 2/2] target/riscv: Auto set elen from vector extension by default Kito Cheng
2022-07-09 8:30 ` [PATCH 1/2] target/riscv: Lower bound of VLEN is 32, and check VLEN >= ELEN Weiwei Li
@ 2022-07-09 9:48 ` Weiwei Li
2 siblings, 0 replies; 7+ messages in thread
From: Weiwei Li @ 2022-07-09 9:48 UTC (permalink / raw)
To: Kito Cheng, alistair.francis, palmer, frank.chang, qemu-devel,
qemu-riscv, liweiwei
在 2022/7/8 下午3:39, Kito Cheng 写道:
> According RVV spec 1.0, the minmal requirement of VLEN is great than or
> equal to ELEN, and minmal possible ELEN is 32, and also spec has mention
> `Minimum VLEN` for zve32* is 32, so the lower bound of VLEN is 32 I
> think.
>
> [1] https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#2-implementation-defined-constant-parameters
> [2] https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#182-zve-vector-extensions-for-embedded-processors
>
> Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
> ---
> target/riscv/cpu.c | 10 ++++++++--
> 1 file changed, 8 insertions(+), 2 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 1bb3973806..487d0faa63 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -740,10 +740,10 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
> "Vector extension VLEN must be power of 2");
> return;
> }
> - if (cpu->cfg.vlen > RV_VLEN_MAX || cpu->cfg.vlen < 128) {
> + if (cpu->cfg.vlen > RV_VLEN_MAX || cpu->cfg.vlen < 32) {
> error_setg(errp,
> "Vector extension implementation only supports VLEN "
> - "in the range [128, %d]", RV_VLEN_MAX);
> + "in the range [32, %d]", RV_VLEN_MAX);
> return;
> }
The check for "VLEN in the range [128, RV_VLEN_MAX]" seems right here,
since this check is for
V vector extension in current implementation and "The V vector
extension requires Zvl128b"(in section 18.3).
Regards,
Weiwei Li
> if (!is_power_of_2(cpu->cfg.elen)) {
> @@ -757,6 +757,12 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
> "in the range [8, 64]");
> return;
> }
> + if (cpu->cfg.vlen < cpu->cfg.elen) {
> + error_setg(errp,
> + "Vector extension VLEN must be greater than or equal "
> + "to ELEN");
> + return;
> + }
> if (cpu->cfg.vext_spec) {
> if (!g_strcmp0(cpu->cfg.vext_spec, "v1.0")) {
> vext_version = VEXT_VERSION_1_00_0;
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH 2/2] target/riscv: Auto set elen from vector extension by default
2022-07-09 8:11 ` Weiwei Li
@ 2022-07-09 9:53 ` Weiwei Li
0 siblings, 0 replies; 7+ messages in thread
From: Weiwei Li @ 2022-07-09 9:53 UTC (permalink / raw)
To: Weiwei Li, Kito Cheng, alistair.francis, palmer, frank.chang,
qemu-devel, qemu-riscv
在 2022/7/9 下午4:11, Weiwei Li 写道:
> 在 2022/7/8 下午3:39, Kito Cheng 写道:
>> Default ELEN is setting to 64 for now, which is incorrect setting for
>> Zve32*, and spec has mention minimum VLEN and supported EEW in chapter
>> "Zve*: Vector Extensions for Embedded Processors" is 32 for Zve32.
>>
>> ELEN actaully could be derived from which extensions are enabled,
>> so this patch set elen to 0 as auto detect, and keep the capability to
>> let user could configure that.
>>
>> Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
>> ---
>> target/riscv/cpu.c | 16 +++++++++++++---
>> 1 file changed, 13 insertions(+), 3 deletions(-)
>>
>> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
>> index 487d0faa63..c1b96da7da 100644
>> --- a/target/riscv/cpu.c
>> +++ b/target/riscv/cpu.c
>> @@ -751,13 +751,22 @@ static void riscv_cpu_realize(DeviceState *dev,
>> Error **errp)
>> "Vector extension ELEN must be power of 2");
>> return;
>> }
>> - if (cpu->cfg.elen > 64 || cpu->cfg.vlen < 8) {
>> + if (cpu->cfg.elen == 0) {
>> + if (cpu->cfg.ext_zve32f) {
>> + cpu->cfg.elen = 32;
>> + }
>> + if (cpu->cfg.ext_zve64f || cpu->cfg.ext_v) {
>> + cpu->cfg.elen = 64;
>> + }
>
> This code is in the "if(cpu->cfg.ext_v){...}", so
> "cpu->cfg.ext_zve64f || cpu->cfg.ext_v" will always be true.
>
> It can use "else ... " directly.
Sorry, misunderstood the logic. It seems that we should set
cpu->cfg.elen=64 directly here.
Regards,
Weiwei Li
>> + }
>> + if (cpu->cfg.elen != 0 && (cpu->cfg.elen > 64 ||
>> + cpu->cfg.elen < 8)) {
>> error_setg(errp,
>> "Vector extension implementation only
>> supports ELEN "
>> "in the range [8, 64]");
>> return;
>> }
>> - if (cpu->cfg.vlen < cpu->cfg.elen) {
>> + if (cpu->cfg.elen != 0 && cpu->cfg.vlen < cpu->cfg.elen) {
>
> when cfg.elen is set to zero, it will be changed to the auto detect
> value(32/64) before this two check.
>
> So this two modifications seem unnecessary.
>
> Regards,
>
> Weiwei Li
>
>> error_setg(errp,
>> "Vector extension VLEN must be greater than
>> or equal "
>> "to ELEN");
>> @@ -901,7 +910,8 @@ static Property riscv_cpu_extensions[] = {
>> DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec),
>> DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec),
>> DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128),
>> - DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64),
>> + /* elen = 0 means set from v or zve* extension */
>> + DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 0),
>> DEFINE_PROP_BOOL("svinval", RISCVCPU, cfg.ext_svinval, false),
>> DEFINE_PROP_BOOL("svnapot", RISCVCPU, cfg.ext_svnapot, false),
>
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH 2/2] target/riscv: Auto set elen from vector extension by default
2022-07-08 7:39 ` [PATCH 2/2] target/riscv: Auto set elen from vector extension by default Kito Cheng
2022-07-09 8:11 ` Weiwei Li
@ 2022-07-11 8:13 ` Frank Chang
1 sibling, 0 replies; 7+ messages in thread
From: Frank Chang @ 2022-07-11 8:13 UTC (permalink / raw)
To: Kito Cheng; +Cc: alistair.francis, palmer, qemu-devel, qemu-riscv, liweiwei
[-- Attachment #1: Type: text/plain, Size: 2664 bytes --]
On Fri, Jul 8, 2022 at 3:39 PM Kito Cheng <kito.cheng@sifive.com> wrote:
> Default ELEN is setting to 64 for now, which is incorrect setting for
> Zve32*, and spec has mention minimum VLEN and supported EEW in chapter
> "Zve*: Vector Extensions for Embedded Processors" is 32 for Zve32.
>
> ELEN actaully could be derived from which extensions are enabled,
> so this patch set elen to 0 as auto detect, and keep the capability to
> let user could configure that.
>
> Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
> ---
> target/riscv/cpu.c | 16 +++++++++++++---
> 1 file changed, 13 insertions(+), 3 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 487d0faa63..c1b96da7da 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -751,13 +751,22 @@ static void riscv_cpu_realize(DeviceState *dev,
> Error **errp)
> "Vector extension ELEN must be power of 2");
> return;
> }
> - if (cpu->cfg.elen > 64 || cpu->cfg.vlen < 8) {
> + if (cpu->cfg.elen == 0) {
> + if (cpu->cfg.ext_zve32f) {
> + cpu->cfg.elen = 32;
> + }
> + if (cpu->cfg.ext_zve64f || cpu->cfg.ext_v) {
> + cpu->cfg.elen = 64;
> + }
> + }
> + if (cpu->cfg.elen != 0 && (cpu->cfg.elen > 64 ||
> + cpu->cfg.elen < 8)) {
> error_setg(errp,
> "Vector extension implementation only supports
> ELEN "
> "in the range [8, 64]");
> return;
> }
>
Should we also check whether cpu->cfg.elen set by user must >= 32 if Zve32f
is enabled?
Same for Zve64f.
Regards,
Frank Chang
> - if (cpu->cfg.vlen < cpu->cfg.elen) {
> + if (cpu->cfg.elen != 0 && cpu->cfg.vlen < cpu->cfg.elen) {
> error_setg(errp,
> "Vector extension VLEN must be greater than or
> equal "
> "to ELEN");
> @@ -901,7 +910,8 @@ static Property riscv_cpu_extensions[] = {
> DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec),
> DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec),
> DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128),
> - DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64),
> + /* elen = 0 means set from v or zve* extension */
> + DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 0),
>
> DEFINE_PROP_BOOL("svinval", RISCVCPU, cfg.ext_svinval, false),
> DEFINE_PROP_BOOL("svnapot", RISCVCPU, cfg.ext_svnapot, false),
> --
> 2.34.0
>
>
[-- Attachment #2: Type: text/html, Size: 3819 bytes --]
^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2022-07-11 8:17 UTC | newest]
Thread overview: 7+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-07-08 7:39 [PATCH 1/2] target/riscv: Lower bound of VLEN is 32, and check VLEN >= ELEN Kito Cheng
2022-07-08 7:39 ` [PATCH 2/2] target/riscv: Auto set elen from vector extension by default Kito Cheng
2022-07-09 8:11 ` Weiwei Li
2022-07-09 9:53 ` Weiwei Li
2022-07-11 8:13 ` Frank Chang
2022-07-09 8:30 ` [PATCH 1/2] target/riscv: Lower bound of VLEN is 32, and check VLEN >= ELEN Weiwei Li
2022-07-09 9:48 ` Weiwei Li
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