* [PATCH 0/4] drm/i915/skl: Support for edp1.4 intermediate frequencies
@ 2015-02-21 5:42 Sonika Jindal
2015-02-21 5:42 ` [PATCH 1/4] drm: Adding edp1.4 specific dpcd macros Sonika Jindal
` (4 more replies)
0 siblings, 5 replies; 14+ messages in thread
From: Sonika Jindal @ 2015-02-21 5:42 UTC (permalink / raw)
To: intel-gfx
This series adds support for edp1.4 intermediate frequencies supported by Skylake
This addresses review comments by Ville and some reformatting.
Sonika Jindal (4):
drm: Adding edp1.4 specific dpcd macros
drm/i915/skl: Read sink supported rates from edp panel
drm/i915/skl: Add support for edp 1.4 intermediate frequencies
drm/i915/skl: Program PLL for edp1.4 intermediate frequencies
drivers/gpu/drm/i915/intel_ddi.c | 9 ++
drivers/gpu/drm/i915/intel_dp.c | 179 +++++++++++++++++++++++++++++++++++---
drivers/gpu/drm/i915/intel_drv.h | 2 +
include/drm/drm_dp_helper.h | 8 ++
4 files changed, 184 insertions(+), 14 deletions(-)
--
1.7.10.4
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH 1/4] drm: Adding edp1.4 specific dpcd macros
2015-02-21 5:42 [PATCH 0/4] drm/i915/skl: Support for edp1.4 intermediate frequencies Sonika Jindal
@ 2015-02-21 5:42 ` Sonika Jindal
2015-02-21 5:42 ` [PATCH 2/4] drm/i915/skl: Read sink supported rates from edp panel Sonika Jindal
` (3 subsequent siblings)
4 siblings, 0 replies; 14+ messages in thread
From: Sonika Jindal @ 2015-02-21 5:42 UTC (permalink / raw)
To: intel-gfx; +Cc: dri-devel
Adding dpcd macros related to edp1.4 and link rates
v2: Added DP_SUPPORTED_LINK_RATES macros
Cc: dri-devel@lists.freedesktop.org
Signed-off-by: Sonika Jindal <sonika.jindal@intel.com>
Reviewed-by: Todd Previte <tprevite@gmail.com>
---
include/drm/drm_dp_helper.h | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index 11f8c84..77a55e2 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -92,6 +92,9 @@
# define DP_MSA_TIMING_PAR_IGNORED (1 << 6) /* eDP */
# define DP_OUI_SUPPORT (1 << 7)
+#define DP_SUPPORTED_LINK_RATES 0x010 /*eDP 1.4*/
+#define DP_MAX_SUPPORTED_RATES 0x8
+
#define DP_I2C_SPEED_CAP 0x00c /* DPI */
# define DP_I2C_SPEED_1K 0x01
# define DP_I2C_SPEED_5K 0x02
@@ -101,6 +104,7 @@
# define DP_I2C_SPEED_1M 0x20
#define DP_EDP_CONFIGURATION_CAP 0x00d /* XXX 1.2? */
+# define DP_DPCD_DISPLAY_CONTROL_CAPABLE (1 << 3) /* edp v1.2 or higher */
#define DP_TRAINING_AUX_RD_INTERVAL 0x00e /* XXX 1.2? */
/* Multiple stream transport */
@@ -221,6 +225,8 @@
# define DP_UP_REQ_EN (1 << 1)
# define DP_UPSTREAM_IS_SRC (1 << 2)
+#define DP_LINK_RATE_SET 0x115
+
#define DP_PSR_EN_CFG 0x170 /* XXX 1.2? */
# define DP_PSR_ENABLE (1 << 0)
# define DP_PSR_MAIN_LINK_ACTIVE (1 << 1)
@@ -332,6 +338,8 @@
# define DP_SET_POWER_D3 0x2
# define DP_SET_POWER_MASK 0x3
+#define DP_EDP_DPCD_REV 0x700
+
#define DP_SIDEBAND_MSG_DOWN_REQ_BASE 0x1000 /* 1.2 MST */
#define DP_SIDEBAND_MSG_UP_REP_BASE 0x1200 /* 1.2 MST */
#define DP_SIDEBAND_MSG_DOWN_REP_BASE 0x1400 /* 1.2 MST */
--
1.7.10.4
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH 2/4] drm/i915/skl: Read sink supported rates from edp panel
2015-02-21 5:42 [PATCH 0/4] drm/i915/skl: Support for edp1.4 intermediate frequencies Sonika Jindal
2015-02-21 5:42 ` [PATCH 1/4] drm: Adding edp1.4 specific dpcd macros Sonika Jindal
@ 2015-02-21 5:42 ` Sonika Jindal
2015-03-04 10:00 ` Ville Syrjälä
2015-02-21 5:42 ` [PATCH 3/4] drm/i915/skl: Add support for edp 1.4 intermediate frequencies Sonika Jindal
` (2 subsequent siblings)
4 siblings, 1 reply; 14+ messages in thread
From: Sonika Jindal @ 2015-02-21 5:42 UTC (permalink / raw)
To: intel-gfx
v2: Using DP_SUPPORTED_LINK_RATES macro for supported_rates array (Satheesh).
v3: Reading dpcd's supported link rates tables based upon edp version in the
same patch.
v4: Move version check under is_edp (Satheesh)
v5: Using le16 for rates, some naming, and removing nested if block (Ville)
v6: Correctly using DP_MAX_SUPPORTED_RATES and removing DP_SUPPORTED_LINK_RATES
(Ville)
v7: Incorrectly removed DP_SUPPORTED_LINK_RATES in v6, re-adding it
Signed-off-by: Sonika Jindal <sonika.jindal@intel.com>
---
drivers/gpu/drm/i915/intel_dp.c | 38 ++++++++++++++++++++++++++++++++++++++
drivers/gpu/drm/i915/intel_drv.h | 1 +
2 files changed, 39 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 42ac99f..72deac6 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1116,6 +1116,33 @@ hsw_dp_set_ddi_pll_sel(struct intel_crtc_state *pipe_config, int link_bw)
}
}
+static int
+intel_read_sink_rates(struct intel_dp *intel_dp, uint32_t *sink_rates)
+{
+ struct drm_device *dev = intel_dp_to_dev(intel_dp);
+ int i = 0;
+ uint16_t val;
+
+ if (INTEL_INFO(dev)->gen >= 9 && intel_dp->supported_rates[0]) {
+ /*
+ * Receiver supports only main-link rate selection by
+ * link rate table method, so read link rates from
+ * supported_link_rates
+ */
+ for (i = 0; i < DP_MAX_SUPPORTED_RATES; ++i) {
+ val = le16_to_cpu(intel_dp->supported_rates[i]);
+ if (val == 0)
+ break;
+
+ sink_rates[i] = val * 200;
+ }
+
+ if (i <= 0)
+ DRM_ERROR("No rates in SUPPORTED_LINK_RATES");
+ }
+ return i;
+}
+
static void
intel_dp_set_clock(struct intel_encoder *encoder,
struct intel_crtc_state *pipe_config, int link_bw)
@@ -3592,6 +3619,7 @@ intel_dp_get_dpcd(struct intel_dp *intel_dp)
struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
struct drm_device *dev = dig_port->base.base.dev;
struct drm_i915_private *dev_priv = dev->dev_private;
+ uint8_t rev;
if (intel_dp_dpcd_read_wake(&intel_dp->aux, 0x000, intel_dp->dpcd,
sizeof(intel_dp->dpcd)) < 0)
@@ -3623,6 +3651,16 @@ intel_dp_get_dpcd(struct intel_dp *intel_dp)
} else
intel_dp->use_tps3 = false;
+ /* Intermediate frequency support */
+ if (is_edp(intel_dp) &&
+ (intel_dp->dpcd[DP_EDP_CONFIGURATION_CAP] & DP_DPCD_DISPLAY_CONTROL_CAPABLE) &&
+ intel_dp_dpcd_read_wake(&intel_dp->aux, DP_EDP_DPCD_REV, &rev, 1) &&
+ (rev >= 0x03)) { /* eDp v1.4 or higher */
+ intel_dp_dpcd_read_wake(&intel_dp->aux,
+ DP_SUPPORTED_LINK_RATES,
+ intel_dp->supported_rates,
+ sizeof(intel_dp->supported_rates));
+ }
if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
DP_DWN_STRM_PORT_PRESENT))
return true; /* native DP sink */
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 6832eb8..24e5411 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -602,6 +602,7 @@ struct intel_dp {
uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
+ __le16 supported_rates[DP_MAX_SUPPORTED_RATES];
struct drm_dp_aux aux;
uint8_t train_set[4];
int panel_power_up_delay;
--
1.7.10.4
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH 3/4] drm/i915/skl: Add support for edp 1.4 intermediate frequencies
2015-02-21 5:42 [PATCH 0/4] drm/i915/skl: Support for edp1.4 intermediate frequencies Sonika Jindal
2015-02-21 5:42 ` [PATCH 1/4] drm: Adding edp1.4 specific dpcd macros Sonika Jindal
2015-02-21 5:42 ` [PATCH 2/4] drm/i915/skl: Read sink supported rates from edp panel Sonika Jindal
@ 2015-02-21 5:42 ` Sonika Jindal
2015-03-04 11:24 ` Ville Syrjälä
2015-02-21 5:42 ` [PATCH 4/4] drm/i915/skl: Program PLL for edp1.4 " Sonika Jindal
2015-02-27 6:08 ` [PATCH 0/4] drm/i915/skl: Support " Jindal, Sonika
4 siblings, 1 reply; 14+ messages in thread
From: Sonika Jindal @ 2015-02-21 5:42 UTC (permalink / raw)
To: intel-gfx
eDp 1.4 supports custom frequencies.
Skylake supports following intermediate frequencies : 3.24 GHz, 2.16 GHz and
4.32 GHz along with usual LBR, HBR and HBR2 frequencies.
Read sink supported frequencies and get common frequencies from sink and
source and use these for link training.
v2: Rebased, removed calculation of min_clock since for edp it is taken as
max_clock (as per comment).
v3: Keeping single array for link rates (Satheesh)
v4: Setting LINK_BW_SET to 0 when setting LINK_RATE_SET (Satheesh)
v5: Some minor nits (Ville)
v6: Keeping separate arrays for source and sink rates (Ville)
Signed-off-by: Sonika Jindal <sonika.jindal@intel.com>
---
drivers/gpu/drm/i915/intel_ddi.c | 9 +++
drivers/gpu/drm/i915/intel_dp.c | 113 +++++++++++++++++++++++++++++++++++---
drivers/gpu/drm/i915/intel_drv.h | 1 +
3 files changed, 115 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 4d8c38d..db00db8 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -803,9 +803,18 @@ static void skl_ddi_clock_get(struct intel_encoder *encoder,
case DPLL_CRTL1_LINK_RATE_810:
link_clock = 81000;
break;
+ case DPLL_CRTL1_LINK_RATE_1080:
+ link_clock = 108000;
+ break;
case DPLL_CRTL1_LINK_RATE_1350:
link_clock = 135000;
break;
+ case DPLL_CRTL1_LINK_RATE_1620:
+ link_clock = 162000;
+ break;
+ case DPLL_CRTL1_LINK_RATE_2160:
+ link_clock = 216000;
+ break;
case DPLL_CRTL1_LINK_RATE_2700:
link_clock = 270000;
break;
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 72deac6..cf7a0f5 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -83,6 +83,11 @@ static const struct dp_link_dpll chv_dpll[] = {
{ DP_LINK_BW_5_4, /* m2_int = 27, m2_fraction = 0 */
{ .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }
};
+/* Skylake supports following rates */
+static const uint32_t gen9_rates[] = { 162000, 216000, 270000, 324000,
+ 432000, 540000 };
+
+static const uint32_t default_rates[] = { 162000, 270000, 540000 };
/**
* is_edp - is the given port attached to an eDP panel (either CPU or PCH)
@@ -1143,6 +1148,25 @@ intel_read_sink_rates(struct intel_dp *intel_dp, uint32_t *sink_rates)
return i;
}
+static int
+intel_read_source_rates(struct intel_dp *intel_dp, uint32_t *source_rates)
+{
+ struct drm_device *dev = intel_dp_to_dev(intel_dp);
+ int i;
+ int max_default_rate;
+
+ if (INTEL_INFO(dev)->gen >= 9 && intel_dp->supported_rates[0]) {
+ for (i = 0; i < ARRAY_SIZE(gen9_rates); ++i)
+ source_rates[i] = gen9_rates[i];
+ } else {
+ /* Index of the max_link_bw supported + 1 */
+ max_default_rate = (intel_dp_max_link_bw(intel_dp) >> 3) + 1;
+ for (i = 0; i < max_default_rate; ++i)
+ source_rates[i] = default_rates[i];
+ }
+ return i;
+}
+
static void
intel_dp_set_clock(struct intel_encoder *encoder,
struct intel_crtc_state *pipe_config, int link_bw)
@@ -1176,6 +1200,45 @@ intel_dp_set_clock(struct intel_encoder *encoder,
}
}
+static int intel_supported_rates(const uint32_t *source_rates, int source_len,
+const uint32_t *sink_rates, int sink_len, uint32_t *supported_rates)
+{
+ int i = 0, j = 0, k = 0;
+
+ /* For panels with edp version less than 1.4 */
+ if (sink_len == 0) {
+ for (i = 0; i < source_len; ++i)
+ supported_rates[i] = source_rates[i];
+ return source_len;
+ }
+
+ /* For edp1.4 panels, find the common rates between source and sink */
+ while (i < source_len && j < sink_len) {
+ if (source_rates[i] == sink_rates[j]) {
+ supported_rates[k] = source_rates[i];
+ ++k;
+ ++i;
+ ++j;
+ } else if (source_rates[i] < sink_rates[j]) {
+ ++i;
+ } else {
+ ++j;
+ }
+ }
+ return k;
+}
+
+static int rate_to_index(uint32_t find, const uint32_t *rates)
+{
+ int i = 0;
+
+ for (i = 0; i < DP_MAX_SUPPORTED_RATES; ++i)
+ if (find == rates[i])
+ break;
+
+ return i;
+}
+
bool
intel_dp_compute_config(struct intel_encoder *encoder,
struct intel_crtc_state *pipe_config)
@@ -1192,10 +1255,25 @@ intel_dp_compute_config(struct intel_encoder *encoder,
int max_lane_count = intel_dp_max_lane_count(intel_dp);
/* Conveniently, the link BW constants become indices with a shift...*/
int min_clock = 0;
- int max_clock = intel_dp_max_link_bw(intel_dp) >> 3;
+ int max_clock;
int bpp, mode_rate;
- static int bws[] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7, DP_LINK_BW_5_4 };
int link_avail, link_clock;
+ uint32_t sink_rates[8];
+ uint32_t supported_rates[8] = {0};
+ uint32_t source_rates[8];
+ int source_len, sink_len, supported_len;
+
+ sink_len = intel_read_sink_rates(intel_dp, sink_rates);
+
+ source_len = intel_read_source_rates(intel_dp, source_rates);
+
+ supported_len = intel_supported_rates(source_rates, source_len,
+ sink_rates, sink_len, supported_rates);
+
+ /* No common link rates between source and sink */
+ WARN_ON(supported_len <= 0);
+
+ max_clock = supported_len - 1;
if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A)
pipe_config->has_pch_encoder = true;
@@ -1219,8 +1297,8 @@ intel_dp_compute_config(struct intel_encoder *encoder,
return false;
DRM_DEBUG_KMS("DP link computation with max lane count %i "
- "max bw %02x pixel clock %iKHz\n",
- max_lane_count, bws[max_clock],
+ "max bw %d pixel clock %iKHz\n",
+ max_lane_count, supported_rates[max_clock],
adjusted_mode->crtc_clock);
/* Walk through all bpp values. Luckily they're all nicely spaced with 2
@@ -1249,8 +1327,11 @@ intel_dp_compute_config(struct intel_encoder *encoder,
bpp);
for (clock = min_clock; clock <= max_clock; clock++) {
- for (lane_count = min_lane_count; lane_count <= max_lane_count; lane_count <<= 1) {
- link_clock = drm_dp_bw_code_to_link_rate(bws[clock]);
+ for (lane_count = min_lane_count;
+ lane_count <= max_lane_count;
+ lane_count <<= 1) {
+
+ link_clock = supported_rates[clock];
link_avail = intel_dp_max_data_rate(link_clock,
lane_count);
@@ -1279,10 +1360,19 @@ found:
if (intel_dp->color_range)
pipe_config->limited_color_range = true;
- intel_dp->link_bw = bws[clock];
intel_dp->lane_count = lane_count;
+
+ intel_dp->link_bw =
+ drm_dp_link_rate_to_bw_code(supported_rates[clock]);
+
+ if (INTEL_INFO(dev)->gen >= 9 && intel_dp->supported_rates[0]) {
+ intel_dp->rate_select =
+ rate_to_index(supported_rates[clock], sink_rates);
+ intel_dp->link_bw = 0;
+ }
+
pipe_config->pipe_bpp = bpp;
- pipe_config->port_clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
+ pipe_config->port_clock = supported_rates[clock];
DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
intel_dp->link_bw, intel_dp->lane_count,
@@ -3392,6 +3482,13 @@ intel_dp_start_link_train(struct intel_dp *intel_dp)
if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2);
+ if (INTEL_INFO(dev)->gen >= 9 && intel_dp->supported_rates[0]) {
+ link_config[0] = 0;
+ drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET,
+ link_config, 1);
+ drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_RATE_SET,
+ &intel_dp->rate_select, 1);
+ }
link_config[0] = 0;
link_config[1] = DP_SET_ANSI_8B10B;
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 24e5411..b54b5f0 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -598,6 +598,7 @@ struct intel_dp {
uint32_t color_range;
bool color_range_auto;
uint8_t link_bw;
+ uint8_t rate_select;
uint8_t lane_count;
uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
--
1.7.10.4
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH 4/4] drm/i915/skl: Program PLL for edp1.4 intermediate frequencies
2015-02-21 5:42 [PATCH 0/4] drm/i915/skl: Support for edp1.4 intermediate frequencies Sonika Jindal
` (2 preceding siblings ...)
2015-02-21 5:42 ` [PATCH 3/4] drm/i915/skl: Add support for edp 1.4 intermediate frequencies Sonika Jindal
@ 2015-02-21 5:42 ` Sonika Jindal
2015-02-21 8:23 ` shuang.he
2015-03-04 11:25 ` Ville Syrjälä
2015-02-27 6:08 ` [PATCH 0/4] drm/i915/skl: Support " Jindal, Sonika
4 siblings, 2 replies; 14+ messages in thread
From: Sonika Jindal @ 2015-02-21 5:42 UTC (permalink / raw)
To: intel-gfx
v2: Making the link_clock half in switch inline with the DPLL_CTRL1_* macros
(Ville)
Signed-off-by: Sonika Jindal <sonika.jindal@intel.com>
---
drivers/gpu/drm/i915/intel_dp.c | 28 ++++++++++++++++++++++------
1 file changed, 22 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index cf7a0f5..62bc6c1 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1079,7 +1079,7 @@ intel_dp_connector_unregister(struct intel_connector *intel_connector)
}
static void
-skl_edp_set_pll_config(struct intel_crtc_state *pipe_config, int link_bw)
+skl_edp_set_pll_config(struct intel_crtc_state *pipe_config, int link_clock)
{
u32 ctrl1;
@@ -1088,19 +1088,35 @@ skl_edp_set_pll_config(struct intel_crtc_state *pipe_config, int link_bw)
pipe_config->dpll_hw_state.cfgcr2 = 0;
ctrl1 = DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
- switch (link_bw) {
- case DP_LINK_BW_1_62:
+ switch (link_clock / 2) {
+ case 81000:
ctrl1 |= DPLL_CRTL1_LINK_RATE(DPLL_CRTL1_LINK_RATE_810,
SKL_DPLL0);
break;
- case DP_LINK_BW_2_7:
+ case 135000:
ctrl1 |= DPLL_CRTL1_LINK_RATE(DPLL_CRTL1_LINK_RATE_1350,
SKL_DPLL0);
break;
- case DP_LINK_BW_5_4:
+ case 270000:
ctrl1 |= DPLL_CRTL1_LINK_RATE(DPLL_CRTL1_LINK_RATE_2700,
SKL_DPLL0);
break;
+ case 162000:
+ ctrl1 |= DPLL_CRTL1_LINK_RATE(DPLL_CRTL1_LINK_RATE_1620,
+ SKL_DPLL0);
+ break;
+ /* TBD: For DP link rates 2.16 GHz and 4.32 GHz, VCO is 8640 which
+ results in CDCLK change. Need to handle the change of CDCLK by
+ disabling pipes and re-enabling them */
+ case 108000:
+ ctrl1 |= DPLL_CRTL1_LINK_RATE(DPLL_CRTL1_LINK_RATE_1080,
+ SKL_DPLL0);
+ break;
+ case 216000:
+ ctrl1 |= DPLL_CRTL1_LINK_RATE(DPLL_CRTL1_LINK_RATE_2160,
+ SKL_DPLL0);
+ break;
+
}
pipe_config->dpll_hw_state.ctrl1 = ctrl1;
}
@@ -1395,7 +1411,7 @@ found:
}
if (IS_SKYLAKE(dev) && is_edp(intel_dp))
- skl_edp_set_pll_config(pipe_config, intel_dp->link_bw);
+ skl_edp_set_pll_config(pipe_config, supported_rates[clock]);
else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
hsw_dp_set_ddi_pll_sel(pipe_config, intel_dp->link_bw);
else
--
1.7.10.4
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 14+ messages in thread
* Re: [PATCH 4/4] drm/i915/skl: Program PLL for edp1.4 intermediate frequencies
2015-02-21 5:42 ` [PATCH 4/4] drm/i915/skl: Program PLL for edp1.4 " Sonika Jindal
@ 2015-02-21 8:23 ` shuang.he
2015-03-04 11:25 ` Ville Syrjälä
1 sibling, 0 replies; 14+ messages in thread
From: shuang.he @ 2015-02-21 8:23 UTC (permalink / raw)
To: shuang.he, ethan.gao, intel-gfx, sonika.jindal
Tested-By: PRC QA PRTS (Patch Regression Test System Contact: shuang.he@intel.com)
Task id: 5802
-------------------------------------Summary-------------------------------------
Platform Delta drm-intel-nightly Series Applied
PNV -5 277/277 272/277
ILK 313/313 313/313
SNB 309/309 309/309
IVB 382/382 382/382
BYT 296/296 296/296
HSW 425/425 425/425
BDW -1 318/318 317/318
-------------------------------------Detailed-------------------------------------
Platform Test drm-intel-nightly Series Applied
*PNV igt_gem_fence_thrash_bo-write-verify-none NRUN(1)PASS(6) FAIL(1)PASS(1)
*PNV igt_gem_fence_thrash_bo-write-verify-x PASS(7) FAIL(1)NO_RESULT(1)
*PNV igt_gem_fence_thrash_bo-write-verify-y NO_RESULT(1)PASS(7) FAIL(1)NO_RESULT(1)
PNV igt_gem_userptr_blits_coherency-sync NO_RESULT(1)CRASH(6)NRUN(1)PASS(6) NO_RESULT(1)CRASH(1)
*PNV igt_gem_userptr_blits_coherency-unsync CRASH(4)NRUN(1)PASS(4) NO_RESULT(1)CRASH(1)
*BDW igt_gem_gtt_hog PASS(19) DMESG_WARN(1)PASS(1)
Note: You need to pay more attention to line start with '*'
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH 0/4] drm/i915/skl: Support for edp1.4 intermediate frequencies
2015-02-21 5:42 [PATCH 0/4] drm/i915/skl: Support for edp1.4 intermediate frequencies Sonika Jindal
` (3 preceding siblings ...)
2015-02-21 5:42 ` [PATCH 4/4] drm/i915/skl: Program PLL for edp1.4 " Sonika Jindal
@ 2015-02-27 6:08 ` Jindal, Sonika
4 siblings, 0 replies; 14+ messages in thread
From: Jindal, Sonika @ 2015-02-27 6:08 UTC (permalink / raw)
To: intel-gfx
Hi,
Did anybody get a chance to look into these patches?
The first patch in the series is merged in -nightly
Thanks,
Sonika
-----Original Message-----
From: Jindal, Sonika
Sent: Saturday, February 21, 2015 11:12 AM
To: intel-gfx@lists.freedesktop.org
Cc: ville.syrjala@linux.intel.com; Jindal, Sonika
Subject: [PATCH 0/4] drm/i915/skl: Support for edp1.4 intermediate frequencies
This series adds support for edp1.4 intermediate frequencies supported by Skylake This addresses review comments by Ville and some reformatting.
Sonika Jindal (4):
drm: Adding edp1.4 specific dpcd macros
drm/i915/skl: Read sink supported rates from edp panel
drm/i915/skl: Add support for edp 1.4 intermediate frequencies
drm/i915/skl: Program PLL for edp1.4 intermediate frequencies
drivers/gpu/drm/i915/intel_ddi.c | 9 ++
drivers/gpu/drm/i915/intel_dp.c | 179 +++++++++++++++++++++++++++++++++++---
drivers/gpu/drm/i915/intel_drv.h | 2 +
include/drm/drm_dp_helper.h | 8 ++
4 files changed, 184 insertions(+), 14 deletions(-)
--
1.7.10.4
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH 2/4] drm/i915/skl: Read sink supported rates from edp panel
2015-02-21 5:42 ` [PATCH 2/4] drm/i915/skl: Read sink supported rates from edp panel Sonika Jindal
@ 2015-03-04 10:00 ` Ville Syrjälä
2015-03-05 4:33 ` [PATCH] " Sonika Jindal
0 siblings, 1 reply; 14+ messages in thread
From: Ville Syrjälä @ 2015-03-04 10:00 UTC (permalink / raw)
To: Sonika Jindal; +Cc: intel-gfx
On Sat, Feb 21, 2015 at 11:12:11AM +0530, Sonika Jindal wrote:
> v2: Using DP_SUPPORTED_LINK_RATES macro for supported_rates array (Satheesh).
> v3: Reading dpcd's supported link rates tables based upon edp version in the
> same patch.
> v4: Move version check under is_edp (Satheesh)
> v5: Using le16 for rates, some naming, and removing nested if block (Ville)
> v6: Correctly using DP_MAX_SUPPORTED_RATES and removing DP_SUPPORTED_LINK_RATES
> (Ville)
> v7: Incorrectly removed DP_SUPPORTED_LINK_RATES in v6, re-adding it
>
> Signed-off-by: Sonika Jindal <sonika.jindal@intel.com>
> ---
> drivers/gpu/drm/i915/intel_dp.c | 38 ++++++++++++++++++++++++++++++++++++++
> drivers/gpu/drm/i915/intel_drv.h | 1 +
> 2 files changed, 39 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 42ac99f..72deac6 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -1116,6 +1116,33 @@ hsw_dp_set_ddi_pll_sel(struct intel_crtc_state *pipe_config, int link_bw)
> }
> }
>
> +static int
> +intel_read_sink_rates(struct intel_dp *intel_dp, uint32_t *sink_rates)
> +{
> + struct drm_device *dev = intel_dp_to_dev(intel_dp);
> + int i = 0;
> + uint16_t val;
> +
> + if (INTEL_INFO(dev)->gen >= 9 && intel_dp->supported_rates[0]) {
> + /*
> + * Receiver supports only main-link rate selection by
> + * link rate table method, so read link rates from
> + * supported_link_rates
> + */
> + for (i = 0; i < DP_MAX_SUPPORTED_RATES; ++i) {
> + val = le16_to_cpu(intel_dp->supported_rates[i]);
> + if (val == 0)
> + break;
> +
> + sink_rates[i] = val * 200;
> + }
> +
> + if (i <= 0)
> + DRM_ERROR("No rates in SUPPORTED_LINK_RATES");
> + }
> + return i;
> +}
> +
> static void
> intel_dp_set_clock(struct intel_encoder *encoder,
> struct intel_crtc_state *pipe_config, int link_bw)
> @@ -3592,6 +3619,7 @@ intel_dp_get_dpcd(struct intel_dp *intel_dp)
> struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> struct drm_device *dev = dig_port->base.base.dev;
> struct drm_i915_private *dev_priv = dev->dev_private;
> + uint8_t rev;
>
> if (intel_dp_dpcd_read_wake(&intel_dp->aux, 0x000, intel_dp->dpcd,
> sizeof(intel_dp->dpcd)) < 0)
> @@ -3623,6 +3651,16 @@ intel_dp_get_dpcd(struct intel_dp *intel_dp)
> } else
> intel_dp->use_tps3 = false;
>
> + /* Intermediate frequency support */
> + if (is_edp(intel_dp) &&
> + (intel_dp->dpcd[DP_EDP_CONFIGURATION_CAP] & DP_DPCD_DISPLAY_CONTROL_CAPABLE) &&
> + intel_dp_dpcd_read_wake(&intel_dp->aux, DP_EDP_DPCD_REV, &rev, 1) &&
intel_dp_dpcd_read_wake() == 1
would be the right thing to check I think.
With that fixed:
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> + (rev >= 0x03)) { /* eDp v1.4 or higher */
> + intel_dp_dpcd_read_wake(&intel_dp->aux,
> + DP_SUPPORTED_LINK_RATES,
> + intel_dp->supported_rates,
> + sizeof(intel_dp->supported_rates));
> + }
> if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
> DP_DWN_STRM_PORT_PRESENT))
> return true; /* native DP sink */
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index 6832eb8..24e5411 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -602,6 +602,7 @@ struct intel_dp {
> uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
> uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
> uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
> + __le16 supported_rates[DP_MAX_SUPPORTED_RATES];
> struct drm_dp_aux aux;
> uint8_t train_set[4];
> int panel_power_up_delay;
> --
> 1.7.10.4
--
Ville Syrjälä
Intel OTC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH 3/4] drm/i915/skl: Add support for edp 1.4 intermediate frequencies
2015-02-21 5:42 ` [PATCH 3/4] drm/i915/skl: Add support for edp 1.4 intermediate frequencies Sonika Jindal
@ 2015-03-04 11:24 ` Ville Syrjälä
2015-03-05 4:32 ` [PATCH] " Sonika Jindal
0 siblings, 1 reply; 14+ messages in thread
From: Ville Syrjälä @ 2015-03-04 11:24 UTC (permalink / raw)
To: Sonika Jindal; +Cc: intel-gfx
On Sat, Feb 21, 2015 at 11:12:12AM +0530, Sonika Jindal wrote:
> eDp 1.4 supports custom frequencies.
> Skylake supports following intermediate frequencies : 3.24 GHz, 2.16 GHz and
> 4.32 GHz along with usual LBR, HBR and HBR2 frequencies.
> Read sink supported frequencies and get common frequencies from sink and
> source and use these for link training.
>
> v2: Rebased, removed calculation of min_clock since for edp it is taken as
> max_clock (as per comment).
> v3: Keeping single array for link rates (Satheesh)
> v4: Setting LINK_BW_SET to 0 when setting LINK_RATE_SET (Satheesh)
> v5: Some minor nits (Ville)
> v6: Keeping separate arrays for source and sink rates (Ville)
>
> Signed-off-by: Sonika Jindal <sonika.jindal@intel.com>
> ---
> drivers/gpu/drm/i915/intel_ddi.c | 9 +++
> drivers/gpu/drm/i915/intel_dp.c | 113 +++++++++++++++++++++++++++++++++++---
> drivers/gpu/drm/i915/intel_drv.h | 1 +
> 3 files changed, 115 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index 4d8c38d..db00db8 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -803,9 +803,18 @@ static void skl_ddi_clock_get(struct intel_encoder *encoder,
> case DPLL_CRTL1_LINK_RATE_810:
> link_clock = 81000;
> break;
> + case DPLL_CRTL1_LINK_RATE_1080:
> + link_clock = 108000;
> + break;
> case DPLL_CRTL1_LINK_RATE_1350:
> link_clock = 135000;
> break;
> + case DPLL_CRTL1_LINK_RATE_1620:
> + link_clock = 162000;
> + break;
> + case DPLL_CRTL1_LINK_RATE_2160:
> + link_clock = 216000;
> + break;
> case DPLL_CRTL1_LINK_RATE_2700:
> link_clock = 270000;
> break;
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 72deac6..cf7a0f5 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -83,6 +83,11 @@ static const struct dp_link_dpll chv_dpll[] = {
> { DP_LINK_BW_5_4, /* m2_int = 27, m2_fraction = 0 */
> { .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }
> };
> +/* Skylake supports following rates */
> +static const uint32_t gen9_rates[] = { 162000, 216000, 270000, 324000,
> + 432000, 540000 };
> +
> +static const uint32_t default_rates[] = { 162000, 270000, 540000 };
>
> /**
> * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
> @@ -1143,6 +1148,25 @@ intel_read_sink_rates(struct intel_dp *intel_dp, uint32_t *sink_rates)
> return i;
> }
>
> +static int
> +intel_read_source_rates(struct intel_dp *intel_dp, uint32_t *source_rates)
> +{
> + struct drm_device *dev = intel_dp_to_dev(intel_dp);
> + int i;
> + int max_default_rate;
> +
> + if (INTEL_INFO(dev)->gen >= 9 && intel_dp->supported_rates[0]) {
> + for (i = 0; i < ARRAY_SIZE(gen9_rates); ++i)
> + source_rates[i] = gen9_rates[i];
> + } else {
> + /* Index of the max_link_bw supported + 1 */
> + max_default_rate = (intel_dp_max_link_bw(intel_dp) >> 3) + 1;
> + for (i = 0; i < max_default_rate; ++i)
> + source_rates[i] = default_rates[i];
> + }
> + return i;
> +}
> +
> static void
> intel_dp_set_clock(struct intel_encoder *encoder,
> struct intel_crtc_state *pipe_config, int link_bw)
> @@ -1176,6 +1200,45 @@ intel_dp_set_clock(struct intel_encoder *encoder,
> }
> }
>
> +static int intel_supported_rates(const uint32_t *source_rates, int source_len,
> +const uint32_t *sink_rates, int sink_len, uint32_t *supported_rates)
> +{
> + int i = 0, j = 0, k = 0;
> +
> + /* For panels with edp version less than 1.4 */
> + if (sink_len == 0) {
> + for (i = 0; i < source_len; ++i)
> + supported_rates[i] = source_rates[i];
> + return source_len;
> + }
> +
> + /* For edp1.4 panels, find the common rates between source and sink */
> + while (i < source_len && j < sink_len) {
> + if (source_rates[i] == sink_rates[j]) {
> + supported_rates[k] = source_rates[i];
> + ++k;
> + ++i;
> + ++j;
> + } else if (source_rates[i] < sink_rates[j]) {
> + ++i;
> + } else {
> + ++j;
> + }
> + }
> + return k;
> +}
> +
> +static int rate_to_index(uint32_t find, const uint32_t *rates)
> +{
> + int i = 0;
> +
> + for (i = 0; i < DP_MAX_SUPPORTED_RATES; ++i)
> + if (find == rates[i])
> + break;
> +
> + return i;
> +}
> +
> bool
> intel_dp_compute_config(struct intel_encoder *encoder,
> struct intel_crtc_state *pipe_config)
> @@ -1192,10 +1255,25 @@ intel_dp_compute_config(struct intel_encoder *encoder,
> int max_lane_count = intel_dp_max_lane_count(intel_dp);
> /* Conveniently, the link BW constants become indices with a shift...*/
> int min_clock = 0;
> - int max_clock = intel_dp_max_link_bw(intel_dp) >> 3;
> + int max_clock;
> int bpp, mode_rate;
> - static int bws[] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7, DP_LINK_BW_5_4 };
> int link_avail, link_clock;
> + uint32_t sink_rates[8];
> + uint32_t supported_rates[8] = {0};
> + uint32_t source_rates[8];
> + int source_len, sink_len, supported_len;
> +
> + sink_len = intel_read_sink_rates(intel_dp, sink_rates);
> +
> + source_len = intel_read_source_rates(intel_dp, source_rates);
> +
> + supported_len = intel_supported_rates(source_rates, source_len,
> + sink_rates, sink_len, supported_rates);
> +
> + /* No common link rates between source and sink */
> + WARN_ON(supported_len <= 0);
> +
> + max_clock = supported_len - 1;
>
> if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A)
> pipe_config->has_pch_encoder = true;
> @@ -1219,8 +1297,8 @@ intel_dp_compute_config(struct intel_encoder *encoder,
> return false;
>
> DRM_DEBUG_KMS("DP link computation with max lane count %i "
> - "max bw %02x pixel clock %iKHz\n",
> - max_lane_count, bws[max_clock],
> + "max bw %d pixel clock %iKHz\n",
> + max_lane_count, supported_rates[max_clock],
> adjusted_mode->crtc_clock);
>
> /* Walk through all bpp values. Luckily they're all nicely spaced with 2
> @@ -1249,8 +1327,11 @@ intel_dp_compute_config(struct intel_encoder *encoder,
> bpp);
>
> for (clock = min_clock; clock <= max_clock; clock++) {
> - for (lane_count = min_lane_count; lane_count <= max_lane_count; lane_count <<= 1) {
> - link_clock = drm_dp_bw_code_to_link_rate(bws[clock]);
> + for (lane_count = min_lane_count;
> + lane_count <= max_lane_count;
> + lane_count <<= 1) {
> +
> + link_clock = supported_rates[clock];
> link_avail = intel_dp_max_data_rate(link_clock,
> lane_count);
>
> @@ -1279,10 +1360,19 @@ found:
> if (intel_dp->color_range)
> pipe_config->limited_color_range = true;
>
> - intel_dp->link_bw = bws[clock];
> intel_dp->lane_count = lane_count;
> +
> + intel_dp->link_bw =
> + drm_dp_link_rate_to_bw_code(supported_rates[clock]);
> +
> + if (INTEL_INFO(dev)->gen >= 9 && intel_dp->supported_rates[0]) {
> + intel_dp->rate_select =
> + rate_to_index(supported_rates[clock], sink_rates);
> + intel_dp->link_bw = 0;
> + }
> +
> pipe_config->pipe_bpp = bpp;
> - pipe_config->port_clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
> + pipe_config->port_clock = supported_rates[clock];
>
> DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
> intel_dp->link_bw, intel_dp->lane_count,
> @@ -3392,6 +3482,13 @@ intel_dp_start_link_train(struct intel_dp *intel_dp)
> if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
> link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
> drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2);
> + if (INTEL_INFO(dev)->gen >= 9 && intel_dp->supported_rates[0]) {
> + link_config[0] = 0;
> + drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET,
> + link_config, 1);
LINK_BW_SET was already written just above. So this second write isn't
needed.
With that fixed this looks pretty good to me, so
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> + drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_RATE_SET,
> + &intel_dp->rate_select, 1);
> + }
>
> link_config[0] = 0;
> link_config[1] = DP_SET_ANSI_8B10B;
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index 24e5411..b54b5f0 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -598,6 +598,7 @@ struct intel_dp {
> uint32_t color_range;
> bool color_range_auto;
> uint8_t link_bw;
> + uint8_t rate_select;
> uint8_t lane_count;
> uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
> uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
> --
> 1.7.10.4
--
Ville Syrjälä
Intel OTC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH 4/4] drm/i915/skl: Program PLL for edp1.4 intermediate frequencies
2015-02-21 5:42 ` [PATCH 4/4] drm/i915/skl: Program PLL for edp1.4 " Sonika Jindal
2015-02-21 8:23 ` shuang.he
@ 2015-03-04 11:25 ` Ville Syrjälä
1 sibling, 0 replies; 14+ messages in thread
From: Ville Syrjälä @ 2015-03-04 11:25 UTC (permalink / raw)
To: Sonika Jindal; +Cc: intel-gfx
On Sat, Feb 21, 2015 at 11:12:13AM +0530, Sonika Jindal wrote:
> v2: Making the link_clock half in switch inline with the DPLL_CTRL1_* macros
> (Ville)
>
> Signed-off-by: Sonika Jindal <sonika.jindal@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/intel_dp.c | 28 ++++++++++++++++++++++------
> 1 file changed, 22 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index cf7a0f5..62bc6c1 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -1079,7 +1079,7 @@ intel_dp_connector_unregister(struct intel_connector *intel_connector)
> }
>
> static void
> -skl_edp_set_pll_config(struct intel_crtc_state *pipe_config, int link_bw)
> +skl_edp_set_pll_config(struct intel_crtc_state *pipe_config, int link_clock)
> {
> u32 ctrl1;
>
> @@ -1088,19 +1088,35 @@ skl_edp_set_pll_config(struct intel_crtc_state *pipe_config, int link_bw)
> pipe_config->dpll_hw_state.cfgcr2 = 0;
>
> ctrl1 = DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
> - switch (link_bw) {
> - case DP_LINK_BW_1_62:
> + switch (link_clock / 2) {
> + case 81000:
> ctrl1 |= DPLL_CRTL1_LINK_RATE(DPLL_CRTL1_LINK_RATE_810,
> SKL_DPLL0);
> break;
> - case DP_LINK_BW_2_7:
> + case 135000:
> ctrl1 |= DPLL_CRTL1_LINK_RATE(DPLL_CRTL1_LINK_RATE_1350,
> SKL_DPLL0);
> break;
> - case DP_LINK_BW_5_4:
> + case 270000:
> ctrl1 |= DPLL_CRTL1_LINK_RATE(DPLL_CRTL1_LINK_RATE_2700,
> SKL_DPLL0);
> break;
> + case 162000:
> + ctrl1 |= DPLL_CRTL1_LINK_RATE(DPLL_CRTL1_LINK_RATE_1620,
> + SKL_DPLL0);
> + break;
> + /* TBD: For DP link rates 2.16 GHz and 4.32 GHz, VCO is 8640 which
> + results in CDCLK change. Need to handle the change of CDCLK by
> + disabling pipes and re-enabling them */
> + case 108000:
> + ctrl1 |= DPLL_CRTL1_LINK_RATE(DPLL_CRTL1_LINK_RATE_1080,
> + SKL_DPLL0);
> + break;
> + case 216000:
> + ctrl1 |= DPLL_CRTL1_LINK_RATE(DPLL_CRTL1_LINK_RATE_2160,
> + SKL_DPLL0);
> + break;
> +
> }
> pipe_config->dpll_hw_state.ctrl1 = ctrl1;
> }
> @@ -1395,7 +1411,7 @@ found:
> }
>
> if (IS_SKYLAKE(dev) && is_edp(intel_dp))
> - skl_edp_set_pll_config(pipe_config, intel_dp->link_bw);
> + skl_edp_set_pll_config(pipe_config, supported_rates[clock]);
> else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
> hsw_dp_set_ddi_pll_sel(pipe_config, intel_dp->link_bw);
> else
> --
> 1.7.10.4
--
Ville Syrjälä
Intel OTC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH] drm/i915/skl: Add support for edp 1.4 intermediate frequencies
2015-03-04 11:24 ` Ville Syrjälä
@ 2015-03-05 4:32 ` Sonika Jindal
2015-03-05 12:02 ` Daniel Vetter
0 siblings, 1 reply; 14+ messages in thread
From: Sonika Jindal @ 2015-03-05 4:32 UTC (permalink / raw)
To: intel-gfx
eDp 1.4 supports custom frequencies.
Skylake supports following intermediate frequencies : 3.24 GHz, 2.16 GHz and
4.32 GHz along with usual LBR, HBR and HBR2 frequencies.
Read sink supported frequencies and get common frequencies from sink and
source and use these for link training.
v2: Rebased, removed calculation of min_clock since for edp it is taken as
max_clock (as per comment).
v3: Keeping single array for link rates (Satheesh)
v4: Setting LINK_BW_SET to 0 when setting LINK_RATE_SET (Satheesh)
v5: Some minor nits (Ville)
v6: Keeping separate arrays for source and sink rates (Ville)
v7: Remove redundant setting of DP_LINK_BW_SET to 0 (Ville)
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Sonika Jindal <sonika.jindal@intel.com>
---
drivers/gpu/drm/i915/intel_ddi.c | 9 ++++
drivers/gpu/drm/i915/intel_dp.c | 109 +++++++++++++++++++++++++++++++++++---
drivers/gpu/drm/i915/intel_drv.h | 1 +
3 files changed, 111 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 985d531..437d285 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -786,9 +786,18 @@ static void skl_ddi_clock_get(struct intel_encoder *encoder,
case DPLL_CRTL1_LINK_RATE_810:
link_clock = 81000;
break;
+ case DPLL_CRTL1_LINK_RATE_1080:
+ link_clock = 108000;
+ break;
case DPLL_CRTL1_LINK_RATE_1350:
link_clock = 135000;
break;
+ case DPLL_CRTL1_LINK_RATE_1620:
+ link_clock = 162000;
+ break;
+ case DPLL_CRTL1_LINK_RATE_2160:
+ link_clock = 216000;
+ break;
case DPLL_CRTL1_LINK_RATE_2700:
link_clock = 270000;
break;
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 0ae8454..2e451de 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -84,6 +84,11 @@ static const struct dp_link_dpll chv_dpll[] = {
{ DP_LINK_BW_5_4, /* m2_int = 27, m2_fraction = 0 */
{ .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }
};
+/* Skylake supports following rates */
+static const uint32_t gen9_rates[] = { 162000, 216000, 270000, 324000,
+ 432000, 540000 };
+
+static const uint32_t default_rates[] = { 162000, 270000, 540000 };
/**
* is_edp - is the given port attached to an eDP panel (either CPU or PCH)
@@ -1144,6 +1149,25 @@ intel_read_sink_rates(struct intel_dp *intel_dp, uint32_t *sink_rates)
return i;
}
+static int
+intel_read_source_rates(struct intel_dp *intel_dp, uint32_t *source_rates)
+{
+ struct drm_device *dev = intel_dp_to_dev(intel_dp);
+ int i;
+ int max_default_rate;
+
+ if (INTEL_INFO(dev)->gen >= 9 && intel_dp->supported_rates[0]) {
+ for (i = 0; i < ARRAY_SIZE(gen9_rates); ++i)
+ source_rates[i] = gen9_rates[i];
+ } else {
+ /* Index of the max_link_bw supported + 1 */
+ max_default_rate = (intel_dp_max_link_bw(intel_dp) >> 3) + 1;
+ for (i = 0; i < max_default_rate; ++i)
+ source_rates[i] = default_rates[i];
+ }
+ return i;
+}
+
static void
intel_dp_set_clock(struct intel_encoder *encoder,
struct intel_crtc_state *pipe_config, int link_bw)
@@ -1177,6 +1201,45 @@ intel_dp_set_clock(struct intel_encoder *encoder,
}
}
+static int intel_supported_rates(const uint32_t *source_rates, int source_len,
+const uint32_t *sink_rates, int sink_len, uint32_t *supported_rates)
+{
+ int i = 0, j = 0, k = 0;
+
+ /* For panels with edp version less than 1.4 */
+ if (sink_len == 0) {
+ for (i = 0; i < source_len; ++i)
+ supported_rates[i] = source_rates[i];
+ return source_len;
+ }
+
+ /* For edp1.4 panels, find the common rates between source and sink */
+ while (i < source_len && j < sink_len) {
+ if (source_rates[i] == sink_rates[j]) {
+ supported_rates[k] = source_rates[i];
+ ++k;
+ ++i;
+ ++j;
+ } else if (source_rates[i] < sink_rates[j]) {
+ ++i;
+ } else {
+ ++j;
+ }
+ }
+ return k;
+}
+
+static int rate_to_index(uint32_t find, const uint32_t *rates)
+{
+ int i = 0;
+
+ for (i = 0; i < DP_MAX_SUPPORTED_RATES; ++i)
+ if (find == rates[i])
+ break;
+
+ return i;
+}
+
bool
intel_dp_compute_config(struct intel_encoder *encoder,
struct intel_crtc_state *pipe_config)
@@ -1193,10 +1256,25 @@ intel_dp_compute_config(struct intel_encoder *encoder,
int max_lane_count = intel_dp_max_lane_count(intel_dp);
/* Conveniently, the link BW constants become indices with a shift...*/
int min_clock = 0;
- int max_clock = intel_dp_max_link_bw(intel_dp) >> 3;
+ int max_clock;
int bpp, mode_rate;
- static int bws[] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7, DP_LINK_BW_5_4 };
int link_avail, link_clock;
+ uint32_t sink_rates[8];
+ uint32_t supported_rates[8] = {0};
+ uint32_t source_rates[8];
+ int source_len, sink_len, supported_len;
+
+ sink_len = intel_read_sink_rates(intel_dp, sink_rates);
+
+ source_len = intel_read_source_rates(intel_dp, source_rates);
+
+ supported_len = intel_supported_rates(source_rates, source_len,
+ sink_rates, sink_len, supported_rates);
+
+ /* No common link rates between source and sink */
+ WARN_ON(supported_len <= 0);
+
+ max_clock = supported_len - 1;
if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A)
pipe_config->has_pch_encoder = true;
@@ -1220,8 +1298,8 @@ intel_dp_compute_config(struct intel_encoder *encoder,
return false;
DRM_DEBUG_KMS("DP link computation with max lane count %i "
- "max bw %02x pixel clock %iKHz\n",
- max_lane_count, bws[max_clock],
+ "max bw %d pixel clock %iKHz\n",
+ max_lane_count, supported_rates[max_clock],
adjusted_mode->crtc_clock);
/* Walk through all bpp values. Luckily they're all nicely spaced with 2
@@ -1250,8 +1328,11 @@ intel_dp_compute_config(struct intel_encoder *encoder,
bpp);
for (clock = min_clock; clock <= max_clock; clock++) {
- for (lane_count = min_lane_count; lane_count <= max_lane_count; lane_count <<= 1) {
- link_clock = drm_dp_bw_code_to_link_rate(bws[clock]);
+ for (lane_count = min_lane_count;
+ lane_count <= max_lane_count;
+ lane_count <<= 1) {
+
+ link_clock = supported_rates[clock];
link_avail = intel_dp_max_data_rate(link_clock,
lane_count);
@@ -1280,10 +1361,19 @@ found:
if (intel_dp->color_range)
pipe_config->limited_color_range = true;
- intel_dp->link_bw = bws[clock];
intel_dp->lane_count = lane_count;
+
+ intel_dp->link_bw =
+ drm_dp_link_rate_to_bw_code(supported_rates[clock]);
+
+ if (INTEL_INFO(dev)->gen >= 9 && intel_dp->supported_rates[0]) {
+ intel_dp->rate_select =
+ rate_to_index(supported_rates[clock], sink_rates);
+ intel_dp->link_bw = 0;
+ }
+
pipe_config->pipe_bpp = bpp;
- pipe_config->port_clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
+ pipe_config->port_clock = supported_rates[clock];
DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
intel_dp->link_bw, intel_dp->lane_count,
@@ -3393,6 +3483,9 @@ intel_dp_start_link_train(struct intel_dp *intel_dp)
if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2);
+ if (INTEL_INFO(dev)->gen >= 9 && intel_dp->supported_rates[0])
+ drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_RATE_SET,
+ &intel_dp->rate_select, 1);
link_config[0] = 0;
link_config[1] = DP_SET_ANSI_8B10B;
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 1f41a83..a2a5cbd 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -622,6 +622,7 @@ struct intel_dp {
uint32_t color_range;
bool color_range_auto;
uint8_t link_bw;
+ uint8_t rate_select;
uint8_t lane_count;
uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
--
1.7.10.4
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH] drm/i915/skl: Read sink supported rates from edp panel
2015-03-04 10:00 ` Ville Syrjälä
@ 2015-03-05 4:33 ` Sonika Jindal
2015-03-05 13:11 ` shuang.he
0 siblings, 1 reply; 14+ messages in thread
From: Sonika Jindal @ 2015-03-05 4:33 UTC (permalink / raw)
To: intel-gfx
v2: Using DP_SUPPORTED_LINK_RATES macro for supported_rates array (Satheesh).
v3: Reading dpcd's supported link rates tables based upon edp version in the
same patch.
v4: Move version check under is_edp (Satheesh)
v5: Using le16 for rates, some naming, and removing nested if block (Ville)
v6: Correctly using DP_MAX_SUPPORTED_RATES and removing DP_SUPPORTED_LINK_RATES
(Ville)
v7: Incorrectly removed DP_SUPPORTED_LINK_RATES in v6, re-adding it
v8: Checking return value of intel_dp_dpcd_read_wake() (Ville)
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Sonika Jindal <sonika.jindal@intel.com>
---
drivers/gpu/drm/i915/intel_dp.c | 38 ++++++++++++++++++++++++++++++++++++++
drivers/gpu/drm/i915/intel_drv.h | 1 +
2 files changed, 39 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index d1141d3..0ae8454 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1117,6 +1117,33 @@ hsw_dp_set_ddi_pll_sel(struct intel_crtc_state *pipe_config, int link_bw)
}
}
+static int
+intel_read_sink_rates(struct intel_dp *intel_dp, uint32_t *sink_rates)
+{
+ struct drm_device *dev = intel_dp_to_dev(intel_dp);
+ int i = 0;
+ uint16_t val;
+
+ if (INTEL_INFO(dev)->gen >= 9 && intel_dp->supported_rates[0]) {
+ /*
+ * Receiver supports only main-link rate selection by
+ * link rate table method, so read link rates from
+ * supported_link_rates
+ */
+ for (i = 0; i < DP_MAX_SUPPORTED_RATES; ++i) {
+ val = le16_to_cpu(intel_dp->supported_rates[i]);
+ if (val == 0)
+ break;
+
+ sink_rates[i] = val * 200;
+ }
+
+ if (i <= 0)
+ DRM_ERROR("No rates in SUPPORTED_LINK_RATES");
+ }
+ return i;
+}
+
static void
intel_dp_set_clock(struct intel_encoder *encoder,
struct intel_crtc_state *pipe_config, int link_bw)
@@ -3578,6 +3605,7 @@ intel_dp_get_dpcd(struct intel_dp *intel_dp)
struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
struct drm_device *dev = dig_port->base.base.dev;
struct drm_i915_private *dev_priv = dev->dev_private;
+ uint8_t rev;
if (intel_dp_dpcd_read_wake(&intel_dp->aux, 0x000, intel_dp->dpcd,
sizeof(intel_dp->dpcd)) < 0)
@@ -3609,6 +3637,16 @@ intel_dp_get_dpcd(struct intel_dp *intel_dp)
} else
intel_dp->use_tps3 = false;
+ /* Intermediate frequency support */
+ if (is_edp(intel_dp) &&
+ (intel_dp->dpcd[DP_EDP_CONFIGURATION_CAP] & DP_DPCD_DISPLAY_CONTROL_CAPABLE) &&
+ (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_EDP_DPCD_REV, &rev, 1) == 1) &&
+ (rev >= 0x03)) { /* eDp v1.4 or higher */
+ intel_dp_dpcd_read_wake(&intel_dp->aux,
+ DP_SUPPORTED_LINK_RATES,
+ intel_dp->supported_rates,
+ sizeof(intel_dp->supported_rates));
+ }
if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
DP_DWN_STRM_PORT_PRESENT))
return true; /* native DP sink */
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 1fb1529..1f41a83 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -626,6 +626,7 @@ struct intel_dp {
uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
+ __le16 supported_rates[DP_MAX_SUPPORTED_RATES];
struct drm_dp_aux aux;
uint8_t train_set[4];
int panel_power_up_delay;
--
1.7.10.4
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 14+ messages in thread
* Re: [PATCH] drm/i915/skl: Add support for edp 1.4 intermediate frequencies
2015-03-05 4:32 ` [PATCH] " Sonika Jindal
@ 2015-03-05 12:02 ` Daniel Vetter
0 siblings, 0 replies; 14+ messages in thread
From: Daniel Vetter @ 2015-03-05 12:02 UTC (permalink / raw)
To: Sonika Jindal; +Cc: intel-gfx
On Thu, Mar 05, 2015 at 10:02:30AM +0530, Sonika Jindal wrote:
> eDp 1.4 supports custom frequencies.
> Skylake supports following intermediate frequencies : 3.24 GHz, 2.16 GHz and
> 4.32 GHz along with usual LBR, HBR and HBR2 frequencies.
> Read sink supported frequencies and get common frequencies from sink and
> source and use these for link training.
>
> v2: Rebased, removed calculation of min_clock since for edp it is taken as
> max_clock (as per comment).
> v3: Keeping single array for link rates (Satheesh)
> v4: Setting LINK_BW_SET to 0 when setting LINK_RATE_SET (Satheesh)
> v5: Some minor nits (Ville)
> v6: Keeping separate arrays for source and sink rates (Ville)
> v7: Remove redundant setting of DP_LINK_BW_SET to 0 (Ville)
>
> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Sonika Jindal <sonika.jindal@intel.com>
> ---
> drivers/gpu/drm/i915/intel_ddi.c | 9 ++++
> drivers/gpu/drm/i915/intel_dp.c | 109 +++++++++++++++++++++++++++++++++++---
> drivers/gpu/drm/i915/intel_drv.h | 1 +
> 3 files changed, 111 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index 985d531..437d285 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -786,9 +786,18 @@ static void skl_ddi_clock_get(struct intel_encoder *encoder,
> case DPLL_CRTL1_LINK_RATE_810:
> link_clock = 81000;
> break;
> + case DPLL_CRTL1_LINK_RATE_1080:
> + link_clock = 108000;
> + break;
> case DPLL_CRTL1_LINK_RATE_1350:
> link_clock = 135000;
> break;
> + case DPLL_CRTL1_LINK_RATE_1620:
> + link_clock = 162000;
> + break;
> + case DPLL_CRTL1_LINK_RATE_2160:
> + link_clock = 216000;
> + break;
> case DPLL_CRTL1_LINK_RATE_2700:
> link_clock = 270000;
> break;
This part here should have been in the next patch imo to handle the dpll
programming, with this patch here just handling the DP port side of
things. As-is the patch split doesn't make that much sense really since
you add new hw programming without adding the necessary state readout in
the last patch.
Anyway, pulled in the entire series, thanks.
-Daniel
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 0ae8454..2e451de 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -84,6 +84,11 @@ static const struct dp_link_dpll chv_dpll[] = {
> { DP_LINK_BW_5_4, /* m2_int = 27, m2_fraction = 0 */
> { .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }
> };
> +/* Skylake supports following rates */
> +static const uint32_t gen9_rates[] = { 162000, 216000, 270000, 324000,
> + 432000, 540000 };
> +
> +static const uint32_t default_rates[] = { 162000, 270000, 540000 };
>
> /**
> * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
> @@ -1144,6 +1149,25 @@ intel_read_sink_rates(struct intel_dp *intel_dp, uint32_t *sink_rates)
> return i;
> }
>
> +static int
> +intel_read_source_rates(struct intel_dp *intel_dp, uint32_t *source_rates)
> +{
> + struct drm_device *dev = intel_dp_to_dev(intel_dp);
> + int i;
> + int max_default_rate;
> +
> + if (INTEL_INFO(dev)->gen >= 9 && intel_dp->supported_rates[0]) {
> + for (i = 0; i < ARRAY_SIZE(gen9_rates); ++i)
> + source_rates[i] = gen9_rates[i];
> + } else {
> + /* Index of the max_link_bw supported + 1 */
> + max_default_rate = (intel_dp_max_link_bw(intel_dp) >> 3) + 1;
> + for (i = 0; i < max_default_rate; ++i)
> + source_rates[i] = default_rates[i];
> + }
> + return i;
> +}
> +
> static void
> intel_dp_set_clock(struct intel_encoder *encoder,
> struct intel_crtc_state *pipe_config, int link_bw)
> @@ -1177,6 +1201,45 @@ intel_dp_set_clock(struct intel_encoder *encoder,
> }
> }
>
> +static int intel_supported_rates(const uint32_t *source_rates, int source_len,
> +const uint32_t *sink_rates, int sink_len, uint32_t *supported_rates)
> +{
> + int i = 0, j = 0, k = 0;
> +
> + /* For panels with edp version less than 1.4 */
> + if (sink_len == 0) {
> + for (i = 0; i < source_len; ++i)
> + supported_rates[i] = source_rates[i];
> + return source_len;
> + }
> +
> + /* For edp1.4 panels, find the common rates between source and sink */
> + while (i < source_len && j < sink_len) {
> + if (source_rates[i] == sink_rates[j]) {
> + supported_rates[k] = source_rates[i];
> + ++k;
> + ++i;
> + ++j;
> + } else if (source_rates[i] < sink_rates[j]) {
> + ++i;
> + } else {
> + ++j;
> + }
> + }
> + return k;
> +}
> +
> +static int rate_to_index(uint32_t find, const uint32_t *rates)
> +{
> + int i = 0;
> +
> + for (i = 0; i < DP_MAX_SUPPORTED_RATES; ++i)
> + if (find == rates[i])
> + break;
> +
> + return i;
> +}
> +
> bool
> intel_dp_compute_config(struct intel_encoder *encoder,
> struct intel_crtc_state *pipe_config)
> @@ -1193,10 +1256,25 @@ intel_dp_compute_config(struct intel_encoder *encoder,
> int max_lane_count = intel_dp_max_lane_count(intel_dp);
> /* Conveniently, the link BW constants become indices with a shift...*/
> int min_clock = 0;
> - int max_clock = intel_dp_max_link_bw(intel_dp) >> 3;
> + int max_clock;
> int bpp, mode_rate;
> - static int bws[] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7, DP_LINK_BW_5_4 };
> int link_avail, link_clock;
> + uint32_t sink_rates[8];
> + uint32_t supported_rates[8] = {0};
> + uint32_t source_rates[8];
> + int source_len, sink_len, supported_len;
> +
> + sink_len = intel_read_sink_rates(intel_dp, sink_rates);
> +
> + source_len = intel_read_source_rates(intel_dp, source_rates);
> +
> + supported_len = intel_supported_rates(source_rates, source_len,
> + sink_rates, sink_len, supported_rates);
> +
> + /* No common link rates between source and sink */
> + WARN_ON(supported_len <= 0);
> +
> + max_clock = supported_len - 1;
>
> if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A)
> pipe_config->has_pch_encoder = true;
> @@ -1220,8 +1298,8 @@ intel_dp_compute_config(struct intel_encoder *encoder,
> return false;
>
> DRM_DEBUG_KMS("DP link computation with max lane count %i "
> - "max bw %02x pixel clock %iKHz\n",
> - max_lane_count, bws[max_clock],
> + "max bw %d pixel clock %iKHz\n",
> + max_lane_count, supported_rates[max_clock],
> adjusted_mode->crtc_clock);
>
> /* Walk through all bpp values. Luckily they're all nicely spaced with 2
> @@ -1250,8 +1328,11 @@ intel_dp_compute_config(struct intel_encoder *encoder,
> bpp);
>
> for (clock = min_clock; clock <= max_clock; clock++) {
> - for (lane_count = min_lane_count; lane_count <= max_lane_count; lane_count <<= 1) {
> - link_clock = drm_dp_bw_code_to_link_rate(bws[clock]);
> + for (lane_count = min_lane_count;
> + lane_count <= max_lane_count;
> + lane_count <<= 1) {
> +
> + link_clock = supported_rates[clock];
> link_avail = intel_dp_max_data_rate(link_clock,
> lane_count);
>
> @@ -1280,10 +1361,19 @@ found:
> if (intel_dp->color_range)
> pipe_config->limited_color_range = true;
>
> - intel_dp->link_bw = bws[clock];
> intel_dp->lane_count = lane_count;
> +
> + intel_dp->link_bw =
> + drm_dp_link_rate_to_bw_code(supported_rates[clock]);
> +
> + if (INTEL_INFO(dev)->gen >= 9 && intel_dp->supported_rates[0]) {
> + intel_dp->rate_select =
> + rate_to_index(supported_rates[clock], sink_rates);
> + intel_dp->link_bw = 0;
> + }
> +
> pipe_config->pipe_bpp = bpp;
> - pipe_config->port_clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
> + pipe_config->port_clock = supported_rates[clock];
>
> DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
> intel_dp->link_bw, intel_dp->lane_count,
> @@ -3393,6 +3483,9 @@ intel_dp_start_link_train(struct intel_dp *intel_dp)
> if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
> link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
> drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2);
> + if (INTEL_INFO(dev)->gen >= 9 && intel_dp->supported_rates[0])
> + drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_RATE_SET,
> + &intel_dp->rate_select, 1);
>
> link_config[0] = 0;
> link_config[1] = DP_SET_ANSI_8B10B;
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index 1f41a83..a2a5cbd 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -622,6 +622,7 @@ struct intel_dp {
> uint32_t color_range;
> bool color_range_auto;
> uint8_t link_bw;
> + uint8_t rate_select;
> uint8_t lane_count;
> uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
> uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
> --
> 1.7.10.4
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH] drm/i915/skl: Read sink supported rates from edp panel
2015-03-05 4:33 ` [PATCH] " Sonika Jindal
@ 2015-03-05 13:11 ` shuang.he
0 siblings, 0 replies; 14+ messages in thread
From: shuang.he @ 2015-03-05 13:11 UTC (permalink / raw)
To: shuang.he, ethan.gao, intel-gfx, sonika.jindal
Tested-By: PRC QA PRTS (Patch Regression Test System Contact: shuang.he@intel.com)
Task id: 5892
-------------------------------------Summary-------------------------------------
Platform Delta drm-intel-nightly Series Applied
PNV 280/280 280/280
ILK 308/308 308/308
SNB -21 328/328 307/328
IVB 379/379 379/379
BYT 294/294 294/294
HSW 387/387 387/387
BDW -1 316/316 315/316
-------------------------------------Detailed-------------------------------------
Platform Test drm-intel-nightly Series Applied
SNB igt_kms_cursor_crc_cursor-size-change NSPT(1)DMESG_WARN(1)PASS(3) NSPT(2)
SNB igt_kms_mmio_vs_cs_flip_setcrtc_vs_cs_flip NSPT(1)DMESG_WARN(1)PASS(3) NSPT(2)
SNB igt_kms_mmio_vs_cs_flip_setplane_vs_cs_flip NSPT(1)DMESG_WARN(1)PASS(3) NSPT(2)
SNB igt_kms_rotation_crc_primary-rotation NSPT(2)DMESG_WARN(1)PASS(3) NSPT(2)
SNB igt_kms_rotation_crc_sprite-rotation NSPT(2)DMESG_WARN(1)PASS(4) NSPT(2)
SNB igt_pm_rpm_cursor NSPT(2)DMESG_WARN(1)PASS(3) NSPT(2)
SNB igt_pm_rpm_cursor-dpms NSPT(2)DMESG_WARN(1)PASS(3) NSPT(2)
SNB igt_pm_rpm_dpms-mode-unset-non-lpsp NSPT(2)DMESG_WARN(1)PASS(3) NSPT(2)
SNB igt_pm_rpm_dpms-non-lpsp NSPT(2)DMESG_WARN(1)PASS(3) NSPT(2)
SNB igt_pm_rpm_drm-resources-equal NSPT(2)DMESG_WARN(1)PASS(3) NSPT(2)
SNB igt_pm_rpm_fences NSPT(2)DMESG_WARN(1)PASS(3) NSPT(2)
SNB igt_pm_rpm_fences-dpms NSPT(2)DMESG_WARN(1)PASS(3) NSPT(2)
SNB igt_pm_rpm_gem-execbuf NSPT(2)DMESG_WARN(1)PASS(3) NSPT(2)
SNB igt_pm_rpm_gem-mmap-cpu NSPT(2)DMESG_WARN(1)PASS(3) NSPT(2)
SNB igt_pm_rpm_gem-mmap-gtt NSPT(2)DMESG_WARN(1)PASS(3) NSPT(2)
SNB igt_pm_rpm_gem-pread NSPT(2)DMESG_WARN(1)PASS(1) NSPT(2)
SNB igt_pm_rpm_i2c NSPT(2)DMESG_WARN(1)PASS(1) NSPT(2)
SNB igt_pm_rpm_modeset-non-lpsp NSPT(2)DMESG_WARN(1)PASS(1) NSPT(2)
SNB igt_pm_rpm_modeset-non-lpsp-stress-no-wait NSPT(2)DMESG_WARN(1)PASS(1) NSPT(2)
SNB igt_pm_rpm_pci-d3-state NSPT(2)DMESG_WARN(1)PASS(1) NSPT(2)
SNB igt_pm_rpm_rte NSPT(2)DMESG_WARN(1)PASS(1) NSPT(2)
*BDW igt_gem_gtt_hog PASS(6) DMESG_WARN(1)PASS(1)
Note: You need to pay more attention to line start with '*'
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 14+ messages in thread
end of thread, other threads:[~2015-03-05 13:11 UTC | newest]
Thread overview: 14+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2015-02-21 5:42 [PATCH 0/4] drm/i915/skl: Support for edp1.4 intermediate frequencies Sonika Jindal
2015-02-21 5:42 ` [PATCH 1/4] drm: Adding edp1.4 specific dpcd macros Sonika Jindal
2015-02-21 5:42 ` [PATCH 2/4] drm/i915/skl: Read sink supported rates from edp panel Sonika Jindal
2015-03-04 10:00 ` Ville Syrjälä
2015-03-05 4:33 ` [PATCH] " Sonika Jindal
2015-03-05 13:11 ` shuang.he
2015-02-21 5:42 ` [PATCH 3/4] drm/i915/skl: Add support for edp 1.4 intermediate frequencies Sonika Jindal
2015-03-04 11:24 ` Ville Syrjälä
2015-03-05 4:32 ` [PATCH] " Sonika Jindal
2015-03-05 12:02 ` Daniel Vetter
2015-02-21 5:42 ` [PATCH 4/4] drm/i915/skl: Program PLL for edp1.4 " Sonika Jindal
2015-02-21 8:23 ` shuang.he
2015-03-04 11:25 ` Ville Syrjälä
2015-02-27 6:08 ` [PATCH 0/4] drm/i915/skl: Support " Jindal, Sonika
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.