* [PATCH] target/riscv: Pass the same value to oprsz and maxsz for vmv.v.v
@ 2021-10-07 8:17 ` frank.chang
0 siblings, 0 replies; 6+ messages in thread
From: frank.chang @ 2021-10-07 8:17 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Frank Chang, Bin Meng, Richard Henderson,
Philippe Mathieu-Daudé,
Alistair Francis, Palmer Dabbelt, LIU Zhiwei
From: Frank Chang <frank.chang@sifive.com>
oprsz and maxsz are passed with the same value in commit: eee2d61e202.
However, vmv.v.v was missed in that commit and should pass the same
value as well in its tcg_gen_gvec_2_ptr() call.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/insn_trans/trans_rvv.c.inc | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index fa451938f1e..f730bd68d18 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -1619,7 +1619,8 @@ static bool trans_vmv_v_v(DisasContext *s, arg_vmv_v_v *a)
tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
tcg_gen_gvec_2_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, a->rs1),
- cpu_env, 0, s->vlen / 8, data, fns[s->sew]);
+ cpu_env, s->vlen / 8, s->vlen / 8, data,
+ fns[s->sew]);
gen_set_label(over);
}
return true;
--
2.25.1
^ permalink raw reply related [flat|nested] 6+ messages in thread* [PATCH] target/riscv: Pass the same value to oprsz and maxsz for vmv.v.v
@ 2021-10-07 8:17 ` frank.chang
0 siblings, 0 replies; 6+ messages in thread
From: frank.chang @ 2021-10-07 8:17 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Frank Chang, Palmer Dabbelt, Alistair Francis, Bin Meng,
Richard Henderson, Philippe Mathieu-Daudé,
LIU Zhiwei
From: Frank Chang <frank.chang@sifive.com>
oprsz and maxsz are passed with the same value in commit: eee2d61e202.
However, vmv.v.v was missed in that commit and should pass the same
value as well in its tcg_gen_gvec_2_ptr() call.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/insn_trans/trans_rvv.c.inc | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index fa451938f1e..f730bd68d18 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -1619,7 +1619,8 @@ static bool trans_vmv_v_v(DisasContext *s, arg_vmv_v_v *a)
tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
tcg_gen_gvec_2_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, a->rs1),
- cpu_env, 0, s->vlen / 8, data, fns[s->sew]);
+ cpu_env, s->vlen / 8, s->vlen / 8, data,
+ fns[s->sew]);
gen_set_label(over);
}
return true;
--
2.25.1
^ permalink raw reply related [flat|nested] 6+ messages in thread* Re: [PATCH] target/riscv: Pass the same value to oprsz and maxsz for vmv.v.v
2021-10-07 8:17 ` frank.chang
@ 2021-10-07 17:53 ` Richard Henderson
-1 siblings, 0 replies; 6+ messages in thread
From: Richard Henderson @ 2021-10-07 17:53 UTC (permalink / raw)
To: frank.chang, qemu-devel, qemu-riscv
Cc: Alistair Francis, Bin Meng, Palmer Dabbelt,
Philippe Mathieu-Daudé,
LIU Zhiwei
On 10/7/21 1:17 AM, frank.chang@sifive.com wrote:
> From: Frank Chang<frank.chang@sifive.com>
>
> oprsz and maxsz are passed with the same value in commit: eee2d61e202.
> However, vmv.v.v was missed in that commit and should pass the same
> value as well in its tcg_gen_gvec_2_ptr() call.
>
> Signed-off-by: Frank Chang<frank.chang@sifive.com>
> ---
> target/riscv/insn_trans/trans_rvv.c.inc | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] target/riscv: Pass the same value to oprsz and maxsz for vmv.v.v
@ 2021-10-07 17:53 ` Richard Henderson
0 siblings, 0 replies; 6+ messages in thread
From: Richard Henderson @ 2021-10-07 17:53 UTC (permalink / raw)
To: frank.chang, qemu-devel, qemu-riscv
Cc: Palmer Dabbelt, Alistair Francis, Bin Meng,
Philippe Mathieu-Daudé,
LIU Zhiwei
On 10/7/21 1:17 AM, frank.chang@sifive.com wrote:
> From: Frank Chang<frank.chang@sifive.com>
>
> oprsz and maxsz are passed with the same value in commit: eee2d61e202.
> However, vmv.v.v was missed in that commit and should pass the same
> value as well in its tcg_gen_gvec_2_ptr() call.
>
> Signed-off-by: Frank Chang<frank.chang@sifive.com>
> ---
> target/riscv/insn_trans/trans_rvv.c.inc | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] target/riscv: Pass the same value to oprsz and maxsz for vmv.v.v
2021-10-07 8:17 ` frank.chang
@ 2021-10-08 3:40 ` Alistair Francis
-1 siblings, 0 replies; 6+ messages in thread
From: Alistair Francis @ 2021-10-08 3:40 UTC (permalink / raw)
To: Frank Chang
Cc: open list:RISC-V, Bin Meng, Richard Henderson,
qemu-devel@nongnu.org Developers, Philippe Mathieu-Daudé,
Alistair Francis, Palmer Dabbelt, LIU Zhiwei
On Thu, Oct 7, 2021 at 6:18 PM <frank.chang@sifive.com> wrote:
>
> From: Frank Chang <frank.chang@sifive.com>
>
> oprsz and maxsz are passed with the same value in commit: eee2d61e202.
> However, vmv.v.v was missed in that commit and should pass the same
> value as well in its tcg_gen_gvec_2_ptr() call.
>
> Signed-off-by: Frank Chang <frank.chang@sifive.com>
Thanks!
Applied to riscv-to-apply.next
Alistair
> ---
> target/riscv/insn_trans/trans_rvv.c.inc | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
> index fa451938f1e..f730bd68d18 100644
> --- a/target/riscv/insn_trans/trans_rvv.c.inc
> +++ b/target/riscv/insn_trans/trans_rvv.c.inc
> @@ -1619,7 +1619,8 @@ static bool trans_vmv_v_v(DisasContext *s, arg_vmv_v_v *a)
> tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
>
> tcg_gen_gvec_2_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, a->rs1),
> - cpu_env, 0, s->vlen / 8, data, fns[s->sew]);
> + cpu_env, s->vlen / 8, s->vlen / 8, data,
> + fns[s->sew]);
> gen_set_label(over);
> }
> return true;
> --
> 2.25.1
>
>
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] target/riscv: Pass the same value to oprsz and maxsz for vmv.v.v
@ 2021-10-08 3:40 ` Alistair Francis
0 siblings, 0 replies; 6+ messages in thread
From: Alistair Francis @ 2021-10-08 3:40 UTC (permalink / raw)
To: Frank Chang
Cc: qemu-devel@nongnu.org Developers, open list:RISC-V, Bin Meng,
Richard Henderson, Philippe Mathieu-Daudé,
Alistair Francis, Palmer Dabbelt, LIU Zhiwei
On Thu, Oct 7, 2021 at 6:18 PM <frank.chang@sifive.com> wrote:
>
> From: Frank Chang <frank.chang@sifive.com>
>
> oprsz and maxsz are passed with the same value in commit: eee2d61e202.
> However, vmv.v.v was missed in that commit and should pass the same
> value as well in its tcg_gen_gvec_2_ptr() call.
>
> Signed-off-by: Frank Chang <frank.chang@sifive.com>
Thanks!
Applied to riscv-to-apply.next
Alistair
> ---
> target/riscv/insn_trans/trans_rvv.c.inc | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
> index fa451938f1e..f730bd68d18 100644
> --- a/target/riscv/insn_trans/trans_rvv.c.inc
> +++ b/target/riscv/insn_trans/trans_rvv.c.inc
> @@ -1619,7 +1619,8 @@ static bool trans_vmv_v_v(DisasContext *s, arg_vmv_v_v *a)
> tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
>
> tcg_gen_gvec_2_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, a->rs1),
> - cpu_env, 0, s->vlen / 8, data, fns[s->sew]);
> + cpu_env, s->vlen / 8, s->vlen / 8, data,
> + fns[s->sew]);
> gen_set_label(over);
> }
> return true;
> --
> 2.25.1
>
>
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2021-10-08 3:41 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-10-07 8:17 [PATCH] target/riscv: Pass the same value to oprsz and maxsz for vmv.v.v frank.chang
2021-10-07 8:17 ` frank.chang
2021-10-07 17:53 ` Richard Henderson
2021-10-07 17:53 ` Richard Henderson
2021-10-08 3:40 ` Alistair Francis
2021-10-08 3:40 ` Alistair Francis
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.