* [PATCH v4 0/2] Fix Guest random crash on Cortex-N1/A76/A75 cores
@ 2020-08-25 16:06 Wei Chen
2020-08-25 16:06 ` [PATCH v4 1/2] xen/arm: Missing N1/A76/A75 FP registers in vCPU context switch Wei Chen
2020-08-25 16:06 ` [PATCH v4 2/2] xen/arm: Throw messages for unknown FP/SIMD implement ID Wei Chen
0 siblings, 2 replies; 6+ messages in thread
From: Wei Chen @ 2020-08-25 16:06 UTC (permalink / raw)
To: xen-devel, sstabellini, julien
Cc: Andre.Przywara, Bertrand.Marquis, Penny.Zheng, Kaly.Xin, nd
On latest Arm Cortex-N1/A76/A75 cores, Xen guests will encouter random
crash when they have wordloads. It's because Xen will ignore FP/SIMD
registers in vCPU context switch (see patch#1 for more details).
This patch set fix guest random crash on these new cores, and throw
messages when Xen detects known FP/SIMD features.
---
v3 --> v4:
1. Use open-code instead of new cpu_has_unknown_{fp,simd} macros.
v2 --> v3:
1. Improve the warning messages to give clear meanings
2. Fix typos
v1 --> v2:
1. Use "< 8" instead of "<= 1" to detect FP/SIMD features.
2. Give messages for unknown FP/SIMD features.
3. Fix typos.
v1:
https://lists.xenproject.org/archives/html/xen-devel/2020-08/msg00857.html
Wei Chen (2):
xen/arm: Missing N1/A76/A75 FP registers in vCPU context switch
xen/arm: Throw messages for unknown FP/SIMD implement ID
xen/arch/arm/setup.c | 12 ++++++++++++
xen/include/asm-arm/cpufeature.h | 4 ++--
2 files changed, 14 insertions(+), 2 deletions(-)
--
2.17.1
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH v4 1/2] xen/arm: Missing N1/A76/A75 FP registers in vCPU context switch
2020-08-25 16:06 [PATCH v4 0/2] Fix Guest random crash on Cortex-N1/A76/A75 cores Wei Chen
@ 2020-08-25 16:06 ` Wei Chen
2020-08-25 16:06 ` [PATCH v4 2/2] xen/arm: Throw messages for unknown FP/SIMD implement ID Wei Chen
1 sibling, 0 replies; 6+ messages in thread
From: Wei Chen @ 2020-08-25 16:06 UTC (permalink / raw)
To: xen-devel, sstabellini, julien
Cc: Andre.Przywara, Bertrand.Marquis, Penny.Zheng, Kaly.Xin, nd
Xen has cpu_has_fp/cpu_has_simd to detect whether the CPU supports
FP/SIMD or not. But currently, these two MACROs only consider value 0
of ID_AA64PFR0_EL1.FP/SIMD as FP/SIMD features enabled. But for CPUs
that support FP/SIMD and half-precision floating-point arithmetic, the
ID_AA64PFR0_EL1.FP/SIMD are 1 (see Arm ARM DDI0487F.b, D13.2.64).
For these CPUs, xen will treat them as no FP/SIMD support, the
vfp_save/restore_state will not take effect.
From the TRM documents of Cortex-A75/A76/N1, we know these CPUs support
basic Advanced SIMD/FP and half-precision floating-point arithmetic. In
this case, on N1/A76/A75 platforms, Xen will always miss the floating
pointer registers save/restore. If different vCPUs are running on the
same pCPU, the floating pointer registers will be corrupted randomly.
This patch fixes Xen on these new cores.
Signed-off-by: Wei Chen <wei.chen@arm.com>
Reviewed-by: Bertrand Marquis <bertrand.marquis@arm.com>
Reviewed-by: Julien Grall <jgrall@amazon.com>
---
xen/include/asm-arm/cpufeature.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/xen/include/asm-arm/cpufeature.h b/xen/include/asm-arm/cpufeature.h
index 674beb0353..10878ead8a 100644
--- a/xen/include/asm-arm/cpufeature.h
+++ b/xen/include/asm-arm/cpufeature.h
@@ -13,8 +13,8 @@
#define cpu_has_el2_64 (boot_cpu_feature64(el2) >= 1)
#define cpu_has_el3_32 (boot_cpu_feature64(el3) == 2)
#define cpu_has_el3_64 (boot_cpu_feature64(el3) >= 1)
-#define cpu_has_fp (boot_cpu_feature64(fp) == 0)
-#define cpu_has_simd (boot_cpu_feature64(simd) == 0)
+#define cpu_has_fp (boot_cpu_feature64(fp) < 8)
+#define cpu_has_simd (boot_cpu_feature64(simd) < 8)
#define cpu_has_gicv3 (boot_cpu_feature64(gic) == 1)
#endif
--
2.17.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH v4 2/2] xen/arm: Throw messages for unknown FP/SIMD implement ID
2020-08-25 16:06 [PATCH v4 0/2] Fix Guest random crash on Cortex-N1/A76/A75 cores Wei Chen
2020-08-25 16:06 ` [PATCH v4 1/2] xen/arm: Missing N1/A76/A75 FP registers in vCPU context switch Wei Chen
@ 2020-08-25 16:06 ` Wei Chen
2020-08-27 14:12 ` Bertrand Marquis
2020-08-27 18:04 ` Julien Grall
1 sibling, 2 replies; 6+ messages in thread
From: Wei Chen @ 2020-08-25 16:06 UTC (permalink / raw)
To: xen-devel, sstabellini, julien
Cc: Andre.Przywara, Bertrand.Marquis, Penny.Zheng, Kaly.Xin, nd
Arm ID_AA64PFR0_EL1 register provides two fields to describe CPU
FP/SIMD implementations. Currently, we exactly know the meaning of
0x0, 0x1 and 0xf of these fields. Xen treats value < 8 as FP/SIMD
features presented. If there is a value 0x2 bumped in the future,
Xen behaviors for value <= 0x1 can also take effect. But what Xen
done for value <= 0x1 may not always cover new value 0x2 required.
We throw these messages to break the silence when Xen detected
unknown FP/SIMD IDs to notice user to check.
Signed-off-by: Wei Chen <wei.chen@arm.com>
---
xen/arch/arm/setup.c | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/xen/arch/arm/setup.c b/xen/arch/arm/setup.c
index 7968cee47d..6a31eca984 100644
--- a/xen/arch/arm/setup.c
+++ b/xen/arch/arm/setup.c
@@ -133,6 +133,18 @@ static void __init processor_id(void)
cpu_has_simd ? " AdvancedSIMD" : "",
cpu_has_gicv3 ? " GICv3-SysReg" : "");
+ /* Warn user if we find unknown floating-point features */
+ if ( cpu_has_fp && (boot_cpu_feature64(fp) >= 2) )
+ printk(XENLOG_WARNING "WARNING: Unknown Floating-point ID:%d, "
+ "this may result to corruption on the platform\n",
+ boot_cpu_feature64(fp));
+
+ /* Warn user if we find unknown AdvancedSIMD features */
+ if ( cpu_has_simd && (boot_cpu_feature64(simd) >= 2) )
+ printk(XENLOG_WARNING "WARNING: Unknown AdvancedSIMD ID:%d, "
+ "this may result to corruption on the platform\n",
+ boot_cpu_feature64(simd));
+
printk(" Debug Features: %016"PRIx64" %016"PRIx64"\n",
boot_cpu_data.dbg64.bits[0], boot_cpu_data.dbg64.bits[1]);
printk(" Auxiliary Features: %016"PRIx64" %016"PRIx64"\n",
--
2.17.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH v4 2/2] xen/arm: Throw messages for unknown FP/SIMD implement ID
2020-08-25 16:06 ` [PATCH v4 2/2] xen/arm: Throw messages for unknown FP/SIMD implement ID Wei Chen
@ 2020-08-27 14:12 ` Bertrand Marquis
2020-08-28 2:23 ` Wei Chen
2020-08-27 18:04 ` Julien Grall
1 sibling, 1 reply; 6+ messages in thread
From: Bertrand Marquis @ 2020-08-27 14:12 UTC (permalink / raw)
To: Wei Chen
Cc: Xen-devel, sstabellini, julien, Andre Przywara, Penny Zheng,
Kaly Xin, nd
> On 25 Aug 2020, at 17:06, Wei Chen <Wei.Chen@arm.com> wrote:
>
> Arm ID_AA64PFR0_EL1 register provides two fields to describe CPU
> FP/SIMD implementations. Currently, we exactly know the meaning of
> 0x0, 0x1 and 0xf of these fields. Xen treats value < 8 as FP/SIMD
> features presented. If there is a value 0x2 bumped in the future,
> Xen behaviors for value <= 0x1 can also take effect. But what Xen
> done for value <= 0x1 may not always cover new value 0x2 required.
> We throw these messages to break the silence when Xen detected
> unknown FP/SIMD IDs to notice user to check.
>
> Signed-off-by: Wei Chen <wei.chen@arm.com>
With the small typo after fixed:
Reviewed-by: Bertrand Marquis <bertrand.marquis@arm.com>
> ---
> xen/arch/arm/setup.c | 12 ++++++++++++
> 1 file changed, 12 insertions(+)
>
> diff --git a/xen/arch/arm/setup.c b/xen/arch/arm/setup.c
> index 7968cee47d..6a31eca984 100644
> --- a/xen/arch/arm/setup.c
> +++ b/xen/arch/arm/setup.c
> @@ -133,6 +133,18 @@ static void __init processor_id(void)
> cpu_has_simd ? " AdvancedSIMD" : "",
> cpu_has_gicv3 ? " GICv3-SysReg" : "");
>
> + /* Warn user if we find unknown floating-point features */
> + if ( cpu_has_fp && (boot_cpu_feature64(fp) >= 2) )
> + printk(XENLOG_WARNING "WARNING: Unknown Floating-point ID:%d, "
> + "this may result to corruption on the platform\n",
s/to/in/
> + boot_cpu_feature64(fp));
> +
> + /* Warn user if we find unknown AdvancedSIMD features */
> + if ( cpu_has_simd && (boot_cpu_feature64(simd) >= 2) )
> + printk(XENLOG_WARNING "WARNING: Unknown AdvancedSIMD ID:%d, "
> + "this may result to corruption on the platform\n",
same as upper
> + boot_cpu_feature64(simd));
> +
> printk(" Debug Features: %016"PRIx64" %016"PRIx64"\n",
> boot_cpu_data.dbg64.bits[0], boot_cpu_data.dbg64.bits[1]);
> printk(" Auxiliary Features: %016"PRIx64" %016"PRIx64"\n",
> --
> 2.17.1
>
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH v4 2/2] xen/arm: Throw messages for unknown FP/SIMD implement ID
2020-08-25 16:06 ` [PATCH v4 2/2] xen/arm: Throw messages for unknown FP/SIMD implement ID Wei Chen
2020-08-27 14:12 ` Bertrand Marquis
@ 2020-08-27 18:04 ` Julien Grall
1 sibling, 0 replies; 6+ messages in thread
From: Julien Grall @ 2020-08-27 18:04 UTC (permalink / raw)
To: Wei Chen, xen-devel, sstabellini
Cc: Andre.Przywara, Bertrand.Marquis, Penny.Zheng, Kaly.Xin, nd
Hi,
On 25/08/2020 17:06, Wei Chen wrote:
> Arm ID_AA64PFR0_EL1 register provides two fields to describe CPU
> FP/SIMD implementations. Currently, we exactly know the meaning of
> 0x0, 0x1 and 0xf of these fields. Xen treats value < 8 as FP/SIMD
> features presented. If there is a value 0x2 bumped in the future,
> Xen behaviors for value <= 0x1 can also take effect. But what Xen
> done for value <= 0x1 may not always cover new value 0x2 required.
> We throw these messages to break the silence when Xen detected
> unknown FP/SIMD IDs to notice user to check.
>
> Signed-off-by: Wei Chen <wei.chen@arm.com>
Acked-by: Julien Grall <jgrall@amazon.com>
Cheers,
--
Julien Grall
^ permalink raw reply [flat|nested] 6+ messages in thread
* RE: [PATCH v4 2/2] xen/arm: Throw messages for unknown FP/SIMD implement ID
2020-08-27 14:12 ` Bertrand Marquis
@ 2020-08-28 2:23 ` Wei Chen
0 siblings, 0 replies; 6+ messages in thread
From: Wei Chen @ 2020-08-28 2:23 UTC (permalink / raw)
To: Bertrand Marquis
Cc: Xen-devel, sstabellini, julien, Andre Przywara, Penny Zheng,
Kaly Xin, nd
Hi Bertand,
> -----Original Message-----
> From: Bertrand Marquis <Bertrand.Marquis@arm.com>
> Sent: 2020年8月27日 22:13
> To: Wei Chen <Wei.Chen@arm.com>
> Cc: Xen-devel <xen-devel@lists.xenproject.org>; sstabellini@kernel.org;
> julien@xen.org; Andre Przywara <Andre.Przywara@arm.com>; Penny Zheng
> <Penny.Zheng@arm.com>; Kaly Xin <Kaly.Xin@arm.com>; nd <nd@arm.com>
> Subject: Re: [PATCH v4 2/2] xen/arm: Throw messages for unknown
> FP/SIMD implement ID
>
>
>
> > On 25 Aug 2020, at 17:06, Wei Chen <Wei.Chen@arm.com> wrote:
> >
> > Arm ID_AA64PFR0_EL1 register provides two fields to describe CPU
> > FP/SIMD implementations. Currently, we exactly know the meaning of
> > 0x0, 0x1 and 0xf of these fields. Xen treats value < 8 as FP/SIMD
> > features presented. If there is a value 0x2 bumped in the future,
> > Xen behaviors for value <= 0x1 can also take effect. But what Xen
> > done for value <= 0x1 may not always cover new value 0x2 required.
> > We throw these messages to break the silence when Xen detected
> > unknown FP/SIMD IDs to notice user to check.
> >
> > Signed-off-by: Wei Chen <wei.chen@arm.com>
>
> With the small typo after fixed:
> Reviewed-by: Bertrand Marquis <bertrand.marquis@arm.com>
>
> > ---
> > xen/arch/arm/setup.c | 12 ++++++++++++
> > 1 file changed, 12 insertions(+)
> >
> > diff --git a/xen/arch/arm/setup.c b/xen/arch/arm/setup.c
> > index 7968cee47d..6a31eca984 100644
> > --- a/xen/arch/arm/setup.c
> > +++ b/xen/arch/arm/setup.c
> > @@ -133,6 +133,18 @@ static void __init processor_id(void)
> > cpu_has_simd ? " AdvancedSIMD" : "",
> > cpu_has_gicv3 ? " GICv3-SysReg" : "");
> >
> > + /* Warn user if we find unknown floating-point features */
> > + if ( cpu_has_fp && (boot_cpu_feature64(fp) >= 2) )
> > + printk(XENLOG_WARNING "WARNING: Unknown Floating-point
> ID:%d, "
> > + "this may result to corruption on the platform\n",
>
> s/to/in/
>
> > + boot_cpu_feature64(fp));
> > +
> > + /* Warn user if we find unknown AdvancedSIMD features */
> > + if ( cpu_has_simd && (boot_cpu_feature64(simd) >= 2) )
> > + printk(XENLOG_WARNING "WARNING: Unknown AdvancedSIMD
> ID:%d, "
> > + "this may result to corruption on the platform\n",
>
> same as upper
I would fix above two typos and send a new version.
>
> > + boot_cpu_feature64(simd));
> > +
> > printk(" Debug Features: %016"PRIx64" %016"PRIx64"\n",
> > boot_cpu_data.dbg64.bits[0], boot_cpu_data.dbg64.bits[1]);
> > printk(" Auxiliary Features: %016"PRIx64" %016"PRIx64"\n",
> > --
> > 2.17.1
> >
>
>
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2020-08-28 2:23 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-08-25 16:06 [PATCH v4 0/2] Fix Guest random crash on Cortex-N1/A76/A75 cores Wei Chen
2020-08-25 16:06 ` [PATCH v4 1/2] xen/arm: Missing N1/A76/A75 FP registers in vCPU context switch Wei Chen
2020-08-25 16:06 ` [PATCH v4 2/2] xen/arm: Throw messages for unknown FP/SIMD implement ID Wei Chen
2020-08-27 14:12 ` Bertrand Marquis
2020-08-28 2:23 ` Wei Chen
2020-08-27 18:04 ` Julien Grall
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.