* [Qemu-devel] [PULL 00/67] ppc-for-2.9 queue 20170112
@ 2017-01-12 2:02 David Gibson
2017-01-12 2:02 ` [Qemu-devel] [PULL 01/67] disas/ppc: Fix indefinite articles in comments David Gibson
` (68 more replies)
0 siblings, 69 replies; 73+ messages in thread
From: David Gibson @ 2017-01-12 2:02 UTC (permalink / raw)
To: peter.maydell
Cc: agraf, qemu-ppc, qemu-devel, thuth, lvivier, aik, mdroth, David Gibson
The following changes since commit b44486dfb9447c88e4b216e730adcc780190852c:
Merge remote-tracking branch 'remotes/kraxel/tags/pull-ui-20170110-1' into staging (2017-01-10 14:52:34 +0000)
are available in the git repository at:
git://github.com/dgibson/qemu.git tags/ppc-for-2.9-20170112
for you to fetch changes up to 229b5b6b56db9c3e6b8f44b4b55a62fa32979f47:
ppc: Fix a warning in bcdcfz code and improve BCD_DIG_BYTE macro (2017-01-12 10:21:49 +1100)
----------------------------------------------------------------
ppc patch queue 2017-01-12
This is the first ppc pull request for qemu-2.9. It's been a while
coming, partly due to dealing with some problems running my usual set
of tests. So, there's quite a lot in here.
* More POWER9 instruction implementations for TCG
* The simpler parts of my CPU compatibility mode cleanup
* This changes behaviour to prefer compatibility modes over
"raW" mode for new machine type versions
* New "40p" machine type which is essentially a modernized and
cleaned up "prep". The intention is that it will replace "prep"
once it has some more testing and polish.
* Add pseries-2.9 machine type
* Implement H_SIGNAL_SYS_RESET hypercall
* Consolidate the two alternate CPU init paths in pseries by
making it always go through CPU core objects to initialize CPU
* A handful of bugfixes and cleanups
There are also some changes not strictly related to ppc code, but for
its benefit:
* Limit the pxi-expander-bridge (PXB) device to x86 guests only
(it's essentially a hack to work around historical x86
limitations)
* Revise a number of qtests and enable them for ppc
----------------------------------------------------------------
Avinesh Kumar (1):
target-ppc: add vextu[bhw][lr]x instructions
Bharata B Rao (13):
target-ppc: Consolidate instruction decode helpers
target-ppc: Fix xscmpodp and xscmpudp instructions
target-ppc: Add xscmpexp[dp,qp] instructions
target-ppc: Add xscmpoqp and xscmpuqp instructions
target-ppc: Add xxperm and xxpermr instructions
target-ppc: Use float64 arg in helper_compute_fprf()
target-ppc: Replace isden by float64_is_zero_or_denormal
target-ppc: Rename helper_compute_fprf to helper_compute_fprf_float64
target-ppc: Add xscvdphp, xscvhpdp
target-ppc: Use correct precision for FPRF setting
target-ppc: Add xsaddqp instructions
target-ppc: Add xscvdpqp instruction
target-ppc: Add xscvqpdp instruction
David Gibson (12):
pseries: Always use core objects for CPU construction
pseries: Make cpu_update during CAS unconditional
ppc: Clean up and QOMify hypercall emulation
ppc: Rename cpu_version to compat_pvr
target-ppc: implement xsabsqp/xsnabsqp instruction
pseries: Add pseries-2.9 machine type
ppc: Rewrite ppc_set_compat()
ppc: Rewrite ppc_get_compat_smt_threads()
ppc: Validate compatibility modes when setting
pxb: Restrict to x86
pseries: Rewrite CAS PVR compatibility logic
ppc: Add ppc_set_compat_all()
Hervé Poussineau (4):
prep: do not use global variable to access nvram
prep: add PReP System I/O
prep: add IBM RS/6000 7020 (40p) memory controller
prep: add IBM RS/6000 7020 (40p) machine emulation
Jose Ricardo Ziviani (6):
target-ppc: Implement bcdcfsq. instruction
target-ppc: Implement bcdctsq. instruction
target-ppc: Implement bcdcpsgn. instruction
target-ppc: Implement bcdsetsgn. instruction
target-ppc: Implement bcd_is_valid function
ppc: Fix a warning in bcdcfz code and improve BCD_DIG_BYTE macro
Laurent Vivier (5):
qtest: add netfilter tests for ppc64
qtest: add display-vga-test to ppc64
libqos: fix spapr qpci_map()
qtest: convert ivshmem-test to use libqos
qtest: add ivshmem-test for ppc64
Nicholas Piggin (1):
ppc/spapr: implement H_SIGNAL_SYS_RESET
Nikunj A Dadhania (18):
target-ppc: rename CRF_* defines as CRF_*_BIT
target-ppc: implement lxsd and lxssp instructions
target-ppc: implement stxsd and stxssp
target-ppc: implement lxv/lxvx and stxv/stxvx
target-ppc: move ppc_vsr_t to common header
target-ppc: implement stop instruction
target-ppc: implement xsnegqp instruction
target-ppc: implement xscpsgnqp instruction
target-ppc: implement lxvl instruction
target-ppc: implement lxvll instruction
target-ppc: implement stxvl instruction
target-ppc: implement stxvll instructions
target-ppc: Add xxextractuw instruction
target-ppc: Add xxinsertw instruction
target-ppc: Add xsxexpdp instruction
target-ppc: Add xsxexpqp instruction
target-ppc: Add xsxsigdp instruction
target-ppc: Add xsxsigqp instructions
Roman Kapl (1):
ppc: Prevent inifnite loop in decrementer auto-reload.
Stefan Weil (1):
disas/ppc: Fix indefinite articles in comments
Thomas Huth (1):
hw/ppc/spapr: Fix boot path of usb-host storage devices
xiaoqiang zhao (4):
hw/gpio: QOM'ify mpc8xxx.c
hw/ppc: QOM'ify e500.c
hw/ppc: QOM'ify ppce500_spin.c
hw/ppc: QOM'ify spapr_vio.c
default-configs/i386-softmmu.mak | 1 +
default-configs/ppc-softmmu.mak | 2 +
default-configs/ppc64-softmmu.mak | 1 +
default-configs/x86_64-softmmu.mak | 1 +
disas/ppc.c | 12 +-
hw/gpio/mpc8xxx.c | 20 +-
hw/pci-bridge/Makefile.objs | 2 +-
hw/ppc/Makefile.objs | 2 +
hw/ppc/e500.c | 17 +-
hw/ppc/ppc_booke.c | 8 +-
hw/ppc/ppce500_spin.c | 18 +-
hw/ppc/prep.c | 234 ++++++++++++++++-
hw/ppc/prep_systemio.c | 303 ++++++++++++++++++++++
hw/ppc/rs6000_mc.c | 232 +++++++++++++++++
hw/ppc/spapr.c | 190 +++++++++-----
hw/ppc/spapr_cpu_core.c | 38 +--
hw/ppc/spapr_hcall.c | 160 +++++-------
hw/ppc/spapr_vio.c | 10 -
hw/ppc/trace-events | 13 +-
hw/usb/host-libusb.c | 29 +++
hw/usb/host-stub.c | 5 +
include/fpu/softfloat.h | 20 ++
include/hw/ppc/spapr.h | 7 +-
include/hw/usb.h | 1 +
target/ppc/Makefile.objs | 2 +-
target/ppc/compat.c | 184 +++++++++++++
target/ppc/cpu.h | 66 ++++-
target/ppc/excp_helper.c | 11 +-
target/ppc/fpu_helper.c | 505 ++++++++++++++++++++++++++----------
target/ppc/helper.h | 31 ++-
target/ppc/int_helper.c | 256 ++++++++++++++++--
target/ppc/internal.h | 200 ++++++++++++++
target/ppc/kvm.c | 4 +-
target/ppc/kvm_ppc.h | 4 +-
target/ppc/mem_helper.c | 66 +++++
target/ppc/translate.c | 236 ++++++-----------
target/ppc/translate/fp-impl.inc.c | 20 +-
target/ppc/translate/fp-ops.inc.c | 2 -
target/ppc/translate/vmx-impl.inc.c | 48 ++++
target/ppc/translate/vmx-ops.inc.c | 10 +-
target/ppc/translate/vsx-impl.inc.c | 301 +++++++++++++++++++++
target/ppc/translate/vsx-ops.inc.c | 45 ++++
target/ppc/translate_init.c | 73 +-----
tests/Makefile.include | 7 +-
tests/display-vga-test.c | 7 +-
tests/ivshmem-test.c | 46 ++--
tests/libqos/pci-spapr.c | 4 +-
47 files changed, 2784 insertions(+), 670 deletions(-)
create mode 100644 hw/ppc/prep_systemio.c
create mode 100644 hw/ppc/rs6000_mc.c
create mode 100644 target/ppc/compat.c
^ permalink raw reply [flat|nested] 73+ messages in thread
* [Qemu-devel] [PULL 01/67] disas/ppc: Fix indefinite articles in comments
2017-01-12 2:02 [Qemu-devel] [PULL 00/67] ppc-for-2.9 queue 20170112 David Gibson
@ 2017-01-12 2:02 ` David Gibson
2017-01-12 2:02 ` [Qemu-devel] [PULL 02/67] target-ppc: Consolidate instruction decode helpers David Gibson
` (67 subsequent siblings)
68 siblings, 0 replies; 73+ messages in thread
From: David Gibson @ 2017-01-12 2:02 UTC (permalink / raw)
To: peter.maydell
Cc: agraf, qemu-ppc, qemu-devel, thuth, lvivier, aik, mdroth,
Stefan Weil, David Gibson
From: Stefan Weil <sw@weilnetz.de>
Signed-off-by: Stefan Weil <sw@weilnetz.de>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
disas/ppc.c | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/disas/ppc.c b/disas/ppc.c
index bd05623..9b5a0e7 100644
--- a/disas/ppc.c
+++ b/disas/ppc.c
@@ -1653,11 +1653,11 @@ extract_tbr (unsigned long insn,
#define BBOYBI_MASK (BBOYCB_MASK | BI_MASK)
#define BBOATBI_MASK (BBOAT2CB_MASK | BI_MASK)
-/* An Context form instruction. */
+/* A Context form instruction. */
#define CTX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7))
#define CTX_MASK CTX(0x3f, 0x7)
-/* An User Context form instruction. */
+/* A User Context form instruction. */
#define UCTX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f))
#define UCTX_MASK UCTX(0x3f, 0x1f)
@@ -1710,19 +1710,19 @@ extract_tbr (unsigned long insn,
#define SC(op, sa, lk) (OP (op) | ((((unsigned long)(sa)) & 1) << 1) | ((lk) & 1))
#define SC_MASK (OP_MASK | (((unsigned long)0x3ff) << 16) | (((unsigned long)1) << 1) | 1)
-/* An VX form instruction. */
+/* A VX form instruction. */
#define VX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7ff))
/* The mask for an VX form instruction. */
#define VX_MASK VX(0x3f, 0x7ff)
-/* An VA form instruction. */
+/* A VA form instruction. */
#define VXA(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x03f))
-/* The mask for an VA form instruction. */
+/* The mask for a VA form instruction. */
#define VXA_MASK VXA(0x3f, 0x3f)
-/* An VXR form instruction. */
+/* A VXR form instruction. */
#define VXR(op, xop, rc) (OP (op) | (((rc) & 1) << 10) | (((unsigned long)(xop)) & 0x3ff))
/* The mask for a VXR form instruction. */
--
2.9.3
^ permalink raw reply related [flat|nested] 73+ messages in thread
* [Qemu-devel] [PULL 02/67] target-ppc: Consolidate instruction decode helpers
2017-01-12 2:02 [Qemu-devel] [PULL 00/67] ppc-for-2.9 queue 20170112 David Gibson
2017-01-12 2:02 ` [Qemu-devel] [PULL 01/67] disas/ppc: Fix indefinite articles in comments David Gibson
@ 2017-01-12 2:02 ` David Gibson
2017-01-12 2:02 ` [Qemu-devel] [PULL 03/67] target-ppc: rename CRF_* defines as CRF_*_BIT David Gibson
` (66 subsequent siblings)
68 siblings, 0 replies; 73+ messages in thread
From: David Gibson @ 2017-01-12 2:02 UTC (permalink / raw)
To: peter.maydell
Cc: agraf, qemu-ppc, qemu-devel, thuth, lvivier, aik, mdroth,
Bharata B Rao, Nikunj A Dadhania, David Gibson
From: Bharata B Rao <bharata@linux.vnet.ibm.com>
Move instruction decode helpers to target-ppc/internal.h so that some
of these can be used from outside of translate.c. This movement also
helps to get rid of some duplicate helpers from target-ppc/fpu_helper.c.
Suggested-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
Signed-off-by: Bharata B Rao <bharata@linux.vnet.ibm.com>
Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
target/ppc/fpu_helper.c | 11 +---
target/ppc/internal.h | 151 ++++++++++++++++++++++++++++++++++++++++++++++++
target/ppc/translate.c | 151 ------------------------------------------------
3 files changed, 152 insertions(+), 161 deletions(-)
diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c
index 8a389e1..d3741b4 100644
--- a/target/ppc/fpu_helper.c
+++ b/target/ppc/fpu_helper.c
@@ -20,6 +20,7 @@
#include "cpu.h"
#include "exec/helper-proto.h"
#include "exec/exec-all.h"
+#include "internal.h"
#define float64_snan_to_qnan(x) ((x) | 0x0008000000000000ULL)
#define float32_snan_to_qnan(x) ((x) | 0x00400000)
@@ -1776,16 +1777,6 @@ uint32_t helper_efdcmpeq(CPUPPCState *env, uint64_t op1, uint64_t op2)
return helper_efdtsteq(env, op1, op2);
}
-#define DECODE_SPLIT(opcode, shift1, nb1, shift2, nb2) \
- (((((opcode) >> (shift1)) & ((1 << (nb1)) - 1)) << nb2) | \
- (((opcode) >> (shift2)) & ((1 << (nb2)) - 1)))
-
-#define xT(opcode) DECODE_SPLIT(opcode, 0, 1, 21, 5)
-#define xA(opcode) DECODE_SPLIT(opcode, 2, 1, 16, 5)
-#define xB(opcode) DECODE_SPLIT(opcode, 1, 1, 11, 5)
-#define xC(opcode) DECODE_SPLIT(opcode, 3, 1, 6, 5)
-#define BF(opcode) (((opcode) >> (31-8)) & 7)
-
typedef union _ppc_vsr_t {
uint64_t u64[2];
uint32_t u32[4];
diff --git a/target/ppc/internal.h b/target/ppc/internal.h
index 1ff4896..9a4a74a 100644
--- a/target/ppc/internal.h
+++ b/target/ppc/internal.h
@@ -47,4 +47,155 @@ FUNC_MASK(MASK, target_ulong, 32, UINT32_MAX);
FUNC_MASK(mask_u32, uint32_t, 32, UINT32_MAX);
FUNC_MASK(mask_u64, uint64_t, 64, UINT64_MAX);
+/*****************************************************************************/
+/*** Instruction decoding ***/
+#define EXTRACT_HELPER(name, shift, nb) \
+static inline uint32_t name(uint32_t opcode) \
+{ \
+ return (opcode >> (shift)) & ((1 << (nb)) - 1); \
+}
+
+#define EXTRACT_SHELPER(name, shift, nb) \
+static inline int32_t name(uint32_t opcode) \
+{ \
+ return (int16_t)((opcode >> (shift)) & ((1 << (nb)) - 1)); \
+}
+
+#define EXTRACT_HELPER_SPLIT(name, shift1, nb1, shift2, nb2) \
+static inline uint32_t name(uint32_t opcode) \
+{ \
+ return (((opcode >> (shift1)) & ((1 << (nb1)) - 1)) << nb2) | \
+ ((opcode >> (shift2)) & ((1 << (nb2)) - 1)); \
+}
+
+#define EXTRACT_HELPER_DXFORM(name, \
+ d0_bits, shift_op_d0, shift_d0, \
+ d1_bits, shift_op_d1, shift_d1, \
+ d2_bits, shift_op_d2, shift_d2) \
+static inline int16_t name(uint32_t opcode) \
+{ \
+ return \
+ (((opcode >> (shift_op_d0)) & ((1 << (d0_bits)) - 1)) << (shift_d0)) | \
+ (((opcode >> (shift_op_d1)) & ((1 << (d1_bits)) - 1)) << (shift_d1)) | \
+ (((opcode >> (shift_op_d2)) & ((1 << (d2_bits)) - 1)) << (shift_d2)); \
+}
+
+
+/* Opcode part 1 */
+EXTRACT_HELPER(opc1, 26, 6);
+/* Opcode part 2 */
+EXTRACT_HELPER(opc2, 1, 5);
+/* Opcode part 3 */
+EXTRACT_HELPER(opc3, 6, 5);
+/* Opcode part 4 */
+EXTRACT_HELPER(opc4, 16, 5);
+/* Update Cr0 flags */
+EXTRACT_HELPER(Rc, 0, 1);
+/* Update Cr6 flags (Altivec) */
+EXTRACT_HELPER(Rc21, 10, 1);
+/* Destination */
+EXTRACT_HELPER(rD, 21, 5);
+/* Source */
+EXTRACT_HELPER(rS, 21, 5);
+/* First operand */
+EXTRACT_HELPER(rA, 16, 5);
+/* Second operand */
+EXTRACT_HELPER(rB, 11, 5);
+/* Third operand */
+EXTRACT_HELPER(rC, 6, 5);
+/*** Get CRn ***/
+EXTRACT_HELPER(crfD, 23, 3);
+EXTRACT_HELPER(BF, 23, 3);
+EXTRACT_HELPER(crfS, 18, 3);
+EXTRACT_HELPER(crbD, 21, 5);
+EXTRACT_HELPER(crbA, 16, 5);
+EXTRACT_HELPER(crbB, 11, 5);
+/* SPR / TBL */
+EXTRACT_HELPER(_SPR, 11, 10);
+static inline uint32_t SPR(uint32_t opcode)
+{
+ uint32_t sprn = _SPR(opcode);
+
+ return ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
+}
+/*** Get constants ***/
+/* 16 bits signed immediate value */
+EXTRACT_SHELPER(SIMM, 0, 16);
+/* 16 bits unsigned immediate value */
+EXTRACT_HELPER(UIMM, 0, 16);
+/* 5 bits signed immediate value */
+EXTRACT_HELPER(SIMM5, 16, 5);
+/* 5 bits signed immediate value */
+EXTRACT_HELPER(UIMM5, 16, 5);
+/* 4 bits unsigned immediate value */
+EXTRACT_HELPER(UIMM4, 16, 4);
+/* Bit count */
+EXTRACT_HELPER(NB, 11, 5);
+/* Shift count */
+EXTRACT_HELPER(SH, 11, 5);
+/* Vector shift count */
+EXTRACT_HELPER(VSH, 6, 4);
+/* Mask start */
+EXTRACT_HELPER(MB, 6, 5);
+/* Mask end */
+EXTRACT_HELPER(ME, 1, 5);
+/* Trap operand */
+EXTRACT_HELPER(TO, 21, 5);
+
+EXTRACT_HELPER(CRM, 12, 8);
+
+#ifndef CONFIG_USER_ONLY
+EXTRACT_HELPER(SR, 16, 4);
+#endif
+
+/* mtfsf/mtfsfi */
+EXTRACT_HELPER(FPBF, 23, 3);
+EXTRACT_HELPER(FPIMM, 12, 4);
+EXTRACT_HELPER(FPL, 25, 1);
+EXTRACT_HELPER(FPFLM, 17, 8);
+EXTRACT_HELPER(FPW, 16, 1);
+
+/* addpcis */
+EXTRACT_HELPER_DXFORM(DX, 10, 6, 6, 5, 16, 1, 1, 0, 0)
+#if defined(TARGET_PPC64)
+/* darn */
+EXTRACT_HELPER(L, 16, 2);
+#endif
+
+/*** Jump target decoding ***/
+/* Immediate address */
+static inline target_ulong LI(uint32_t opcode)
+{
+ return (opcode >> 0) & 0x03FFFFFC;
+}
+
+static inline uint32_t BD(uint32_t opcode)
+{
+ return (opcode >> 0) & 0xFFFC;
+}
+
+EXTRACT_HELPER(BO, 21, 5);
+EXTRACT_HELPER(BI, 16, 5);
+/* Absolute/relative address */
+EXTRACT_HELPER(AA, 1, 1);
+/* Link */
+EXTRACT_HELPER(LK, 0, 1);
+
+/* DFP Z22-form */
+EXTRACT_HELPER(DCM, 10, 6)
+
+/* DFP Z23-form */
+EXTRACT_HELPER(RMC, 9, 2)
+
+EXTRACT_HELPER_SPLIT(xT, 0, 1, 21, 5);
+EXTRACT_HELPER_SPLIT(xS, 0, 1, 21, 5);
+EXTRACT_HELPER_SPLIT(xA, 2, 1, 16, 5);
+EXTRACT_HELPER_SPLIT(xB, 1, 1, 11, 5);
+EXTRACT_HELPER_SPLIT(xC, 3, 1, 6, 5);
+EXTRACT_HELPER(DM, 8, 2);
+EXTRACT_HELPER(UIM, 16, 2);
+EXTRACT_HELPER(SHW, 8, 2);
+EXTRACT_HELPER(SP, 19, 2);
+EXTRACT_HELPER(IMM8, 11, 8);
+
#endif /* PPC_INTERNAL_H */
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 59e9552..6bdc433 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -422,157 +422,6 @@ typedef struct opcode_t {
#define CHK_NONE
-
-/*****************************************************************************/
-/*** Instruction decoding ***/
-#define EXTRACT_HELPER(name, shift, nb) \
-static inline uint32_t name(uint32_t opcode) \
-{ \
- return (opcode >> (shift)) & ((1 << (nb)) - 1); \
-}
-
-#define EXTRACT_SHELPER(name, shift, nb) \
-static inline int32_t name(uint32_t opcode) \
-{ \
- return (int16_t)((opcode >> (shift)) & ((1 << (nb)) - 1)); \
-}
-
-#define EXTRACT_HELPER_SPLIT(name, shift1, nb1, shift2, nb2) \
-static inline uint32_t name(uint32_t opcode) \
-{ \
- return (((opcode >> (shift1)) & ((1 << (nb1)) - 1)) << nb2) | \
- ((opcode >> (shift2)) & ((1 << (nb2)) - 1)); \
-}
-
-#define EXTRACT_HELPER_DXFORM(name, \
- d0_bits, shift_op_d0, shift_d0, \
- d1_bits, shift_op_d1, shift_d1, \
- d2_bits, shift_op_d2, shift_d2) \
-static inline int16_t name(uint32_t opcode) \
-{ \
- return \
- (((opcode >> (shift_op_d0)) & ((1 << (d0_bits)) - 1)) << (shift_d0)) | \
- (((opcode >> (shift_op_d1)) & ((1 << (d1_bits)) - 1)) << (shift_d1)) | \
- (((opcode >> (shift_op_d2)) & ((1 << (d2_bits)) - 1)) << (shift_d2)); \
-}
-
-
-/* Opcode part 1 */
-EXTRACT_HELPER(opc1, 26, 6);
-/* Opcode part 2 */
-EXTRACT_HELPER(opc2, 1, 5);
-/* Opcode part 3 */
-EXTRACT_HELPER(opc3, 6, 5);
-/* Opcode part 4 */
-EXTRACT_HELPER(opc4, 16, 5);
-/* Update Cr0 flags */
-EXTRACT_HELPER(Rc, 0, 1);
-/* Update Cr6 flags (Altivec) */
-EXTRACT_HELPER(Rc21, 10, 1);
-/* Destination */
-EXTRACT_HELPER(rD, 21, 5);
-/* Source */
-EXTRACT_HELPER(rS, 21, 5);
-/* First operand */
-EXTRACT_HELPER(rA, 16, 5);
-/* Second operand */
-EXTRACT_HELPER(rB, 11, 5);
-/* Third operand */
-EXTRACT_HELPER(rC, 6, 5);
-/*** Get CRn ***/
-EXTRACT_HELPER(crfD, 23, 3);
-EXTRACT_HELPER(crfS, 18, 3);
-EXTRACT_HELPER(crbD, 21, 5);
-EXTRACT_HELPER(crbA, 16, 5);
-EXTRACT_HELPER(crbB, 11, 5);
-/* SPR / TBL */
-EXTRACT_HELPER(_SPR, 11, 10);
-static inline uint32_t SPR(uint32_t opcode)
-{
- uint32_t sprn = _SPR(opcode);
-
- return ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
-}
-/*** Get constants ***/
-/* 16 bits signed immediate value */
-EXTRACT_SHELPER(SIMM, 0, 16);
-/* 16 bits unsigned immediate value */
-EXTRACT_HELPER(UIMM, 0, 16);
-/* 5 bits signed immediate value */
-EXTRACT_HELPER(SIMM5, 16, 5);
-/* 5 bits signed immediate value */
-EXTRACT_HELPER(UIMM5, 16, 5);
-/* 4 bits unsigned immediate value */
-EXTRACT_HELPER(UIMM4, 16, 4);
-/* Bit count */
-EXTRACT_HELPER(NB, 11, 5);
-/* Shift count */
-EXTRACT_HELPER(SH, 11, 5);
-/* Vector shift count */
-EXTRACT_HELPER(VSH, 6, 4);
-/* Mask start */
-EXTRACT_HELPER(MB, 6, 5);
-/* Mask end */
-EXTRACT_HELPER(ME, 1, 5);
-/* Trap operand */
-EXTRACT_HELPER(TO, 21, 5);
-
-EXTRACT_HELPER(CRM, 12, 8);
-
-#ifndef CONFIG_USER_ONLY
-EXTRACT_HELPER(SR, 16, 4);
-#endif
-
-/* mtfsf/mtfsfi */
-EXTRACT_HELPER(FPBF, 23, 3);
-EXTRACT_HELPER(FPIMM, 12, 4);
-EXTRACT_HELPER(FPL, 25, 1);
-EXTRACT_HELPER(FPFLM, 17, 8);
-EXTRACT_HELPER(FPW, 16, 1);
-
-/* addpcis */
-EXTRACT_HELPER_DXFORM(DX, 10, 6, 6, 5, 16, 1, 1, 0, 0)
-#if defined(TARGET_PPC64)
-/* darn */
-EXTRACT_HELPER(L, 16, 2);
-#endif
-
-/*** Jump target decoding ***/
-/* Immediate address */
-static inline target_ulong LI(uint32_t opcode)
-{
- return (opcode >> 0) & 0x03FFFFFC;
-}
-
-static inline uint32_t BD(uint32_t opcode)
-{
- return (opcode >> 0) & 0xFFFC;
-}
-
-EXTRACT_HELPER(BO, 21, 5);
-EXTRACT_HELPER(BI, 16, 5);
-/* Absolute/relative address */
-EXTRACT_HELPER(AA, 1, 1);
-/* Link */
-EXTRACT_HELPER(LK, 0, 1);
-
-/* DFP Z22-form */
-EXTRACT_HELPER(DCM, 10, 6)
-
-/* DFP Z23-form */
-EXTRACT_HELPER(RMC, 9, 2)
-
-EXTRACT_HELPER_SPLIT(xT, 0, 1, 21, 5);
-EXTRACT_HELPER_SPLIT(xS, 0, 1, 21, 5);
-EXTRACT_HELPER_SPLIT(xA, 2, 1, 16, 5);
-EXTRACT_HELPER_SPLIT(xB, 1, 1, 11, 5);
-EXTRACT_HELPER_SPLIT(xC, 3, 1, 6, 5);
-EXTRACT_HELPER(DM, 8, 2);
-EXTRACT_HELPER(UIM, 16, 2);
-EXTRACT_HELPER(SHW, 8, 2);
-EXTRACT_HELPER(SP, 19, 2);
-EXTRACT_HELPER(IMM8, 11, 8);
-
/*****************************************************************************/
/* PowerPC instructions table */
--
2.9.3
^ permalink raw reply related [flat|nested] 73+ messages in thread
* [Qemu-devel] [PULL 03/67] target-ppc: rename CRF_* defines as CRF_*_BIT
2017-01-12 2:02 [Qemu-devel] [PULL 00/67] ppc-for-2.9 queue 20170112 David Gibson
2017-01-12 2:02 ` [Qemu-devel] [PULL 01/67] disas/ppc: Fix indefinite articles in comments David Gibson
2017-01-12 2:02 ` [Qemu-devel] [PULL 02/67] target-ppc: Consolidate instruction decode helpers David Gibson
@ 2017-01-12 2:02 ` David Gibson
2017-01-12 2:02 ` [Qemu-devel] [PULL 04/67] target-ppc: Fix xscmpodp and xscmpudp instructions David Gibson
` (65 subsequent siblings)
68 siblings, 0 replies; 73+ messages in thread
From: David Gibson @ 2017-01-12 2:02 UTC (permalink / raw)
To: peter.maydell
Cc: agraf, qemu-ppc, qemu-devel, thuth, lvivier, aik, mdroth,
Nikunj A Dadhania, David Gibson
From: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
Add _BIT to CRF_[GT,LT,EQ_SO] and introduce CRF_[GT,LT,EQ,SO] for usage
without shifts in the code. This would simplify the code.
Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
target/ppc/cpu.h | 21 +++++++++++++--------
target/ppc/int_helper.c | 30 +++++++++++++++---------------
target/ppc/translate.c | 14 +++++++-------
3 files changed, 35 insertions(+), 30 deletions(-)
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index 2a50c43..b6782ba 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -1301,14 +1301,19 @@ static inline int cpu_mmu_index (CPUPPCState *env, bool ifetch)
/*****************************************************************************/
/* CRF definitions */
-#define CRF_LT 3
-#define CRF_GT 2
-#define CRF_EQ 1
-#define CRF_SO 0
-#define CRF_CH (1 << CRF_LT)
-#define CRF_CL (1 << CRF_GT)
-#define CRF_CH_OR_CL (1 << CRF_EQ)
-#define CRF_CH_AND_CL (1 << CRF_SO)
+#define CRF_LT_BIT 3
+#define CRF_GT_BIT 2
+#define CRF_EQ_BIT 1
+#define CRF_SO_BIT 0
+#define CRF_LT (1 << CRF_LT_BIT)
+#define CRF_GT (1 << CRF_GT_BIT)
+#define CRF_EQ (1 << CRF_EQ_BIT)
+#define CRF_SO (1 << CRF_SO_BIT)
+/* For SPE extensions */
+#define CRF_CH (1 << CRF_LT_BIT)
+#define CRF_CL (1 << CRF_GT_BIT)
+#define CRF_CH_OR_CL (1 << CRF_EQ_BIT)
+#define CRF_CH_AND_CL (1 << CRF_SO_BIT)
/* XER definitions */
#define XER_SO 31
diff --git a/target/ppc/int_helper.c b/target/ppc/int_helper.c
index 2d57c9a..1667c94 100644
--- a/target/ppc/int_helper.c
+++ b/target/ppc/int_helper.c
@@ -167,7 +167,7 @@ target_ulong helper_cnttzw(target_ulong t)
uint32_t helper_cmpeqb(target_ulong ra, target_ulong rb)
{
- return hasvalue(rb, ra) ? 1 << CRF_GT : 0;
+ return hasvalue(rb, ra) ? CRF_GT : 0;
}
#undef pattern
@@ -2563,9 +2563,9 @@ static void bcd_put_digit(ppc_avr_t *bcd, uint8_t digit, int n)
static int bcd_cmp_zero(ppc_avr_t *bcd)
{
if (bcd->u64[HI_IDX] == 0 && (bcd->u64[LO_IDX] >> 4) == 0) {
- return 1 << CRF_EQ;
+ return CRF_EQ;
} else {
- return (bcd_get_sgn(bcd) == 1) ? 1 << CRF_GT : 1 << CRF_LT;
+ return (bcd_get_sgn(bcd) == 1) ? CRF_GT : CRF_LT;
}
}
@@ -2677,25 +2677,25 @@ uint32_t helper_bcdadd(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, uint32_t ps)
if (sgna == sgnb) {
result.u8[BCD_DIG_BYTE(0)] = bcd_preferred_sgn(sgna, ps);
zero = bcd_add_mag(&result, a, b, &invalid, &overflow);
- cr = (sgna > 0) ? 1 << CRF_GT : 1 << CRF_LT;
+ cr = (sgna > 0) ? CRF_GT : CRF_LT;
} else if (bcd_cmp_mag(a, b) > 0) {
result.u8[BCD_DIG_BYTE(0)] = bcd_preferred_sgn(sgna, ps);
zero = bcd_sub_mag(&result, a, b, &invalid, &overflow);
- cr = (sgna > 0) ? 1 << CRF_GT : 1 << CRF_LT;
+ cr = (sgna > 0) ? CRF_GT : CRF_LT;
} else {
result.u8[BCD_DIG_BYTE(0)] = bcd_preferred_sgn(sgnb, ps);
zero = bcd_sub_mag(&result, b, a, &invalid, &overflow);
- cr = (sgnb > 0) ? 1 << CRF_GT : 1 << CRF_LT;
+ cr = (sgnb > 0) ? CRF_GT : CRF_LT;
}
}
if (unlikely(invalid)) {
result.u64[HI_IDX] = result.u64[LO_IDX] = -1;
- cr = 1 << CRF_SO;
+ cr = CRF_SO;
} else if (overflow) {
- cr |= 1 << CRF_SO;
+ cr |= CRF_SO;
} else if (zero) {
- cr = 1 << CRF_EQ;
+ cr = CRF_EQ;
}
*r = result;
@@ -2745,7 +2745,7 @@ uint32_t helper_bcdcfn(ppc_avr_t *r, ppc_avr_t *b, uint32_t ps)
cr = bcd_cmp_zero(&ret);
if (unlikely(invalid)) {
- cr = 1 << CRF_SO;
+ cr = CRF_SO;
}
*r = ret;
@@ -2775,11 +2775,11 @@ uint32_t helper_bcdctn(ppc_avr_t *r, ppc_avr_t *b, uint32_t ps)
cr = bcd_cmp_zero(b);
if (ox_flag) {
- cr |= 1 << CRF_SO;
+ cr |= CRF_SO;
}
if (unlikely(invalid)) {
- cr = 1 << CRF_SO;
+ cr = CRF_SO;
}
*r = ret;
@@ -2823,7 +2823,7 @@ uint32_t helper_bcdcfz(ppc_avr_t *r, ppc_avr_t *b, uint32_t ps)
cr = bcd_cmp_zero(&ret);
if (unlikely(invalid)) {
- cr = 1 << CRF_SO;
+ cr = CRF_SO;
}
*r = ret;
@@ -2862,11 +2862,11 @@ uint32_t helper_bcdctz(ppc_avr_t *r, ppc_avr_t *b, uint32_t ps)
cr = bcd_cmp_zero(b);
if (ox_flag) {
- cr |= 1 << CRF_SO;
+ cr |= CRF_SO;
}
if (unlikely(invalid)) {
- cr = 1 << CRF_SO;
+ cr = CRF_SO;
}
*r = ret;
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 6bdc433..d3bda1b 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -612,17 +612,17 @@ static inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf)
tcg_gen_setcond_tl((s ? TCG_COND_LT: TCG_COND_LTU), t0, arg0, arg1);
tcg_gen_trunc_tl_i32(t1, t0);
- tcg_gen_shli_i32(t1, t1, CRF_LT);
+ tcg_gen_shli_i32(t1, t1, CRF_LT_BIT);
tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
tcg_gen_setcond_tl((s ? TCG_COND_GT: TCG_COND_GTU), t0, arg0, arg1);
tcg_gen_trunc_tl_i32(t1, t0);
- tcg_gen_shli_i32(t1, t1, CRF_GT);
+ tcg_gen_shli_i32(t1, t1, CRF_GT_BIT);
tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
tcg_gen_setcond_tl(TCG_COND_EQ, t0, arg0, arg1);
tcg_gen_trunc_tl_i32(t1, t0);
- tcg_gen_shli_i32(t1, t1, CRF_EQ);
+ tcg_gen_shli_i32(t1, t1, CRF_EQ_BIT);
tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
tcg_temp_free(t0);
@@ -748,7 +748,7 @@ static void gen_cmprb(DisasContext *ctx)
tcg_gen_and_i32(src2lo, src2lo, src2hi);
tcg_gen_or_i32(crf, crf, src2lo);
}
- tcg_gen_shli_i32(crf, crf, CRF_GT);
+ tcg_gen_shli_i32(crf, crf, CRF_GT_BIT);
tcg_temp_free_i32(src1);
tcg_temp_free_i32(src2);
tcg_temp_free_i32(src2lo);
@@ -2978,7 +2978,7 @@ static void gen_conditional_store(DisasContext *ctx, TCGv EA,
tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
l1 = gen_new_label();
tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, l1);
- tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ);
+ tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], CRF_EQ);
tcg_gen_qemu_st_tl(cpu_gpr[reg], EA, ctx->mem_idx, memop);
gen_set_label(l1);
tcg_gen_movi_tl(cpu_reserve, -1);
@@ -3072,7 +3072,7 @@ static void gen_stqcx_(DisasContext *ctx)
tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
l1 = gen_new_label();
tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, l1);
- tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ);
+ tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], CRF_EQ);
if (unlikely(ctx->le_mode)) {
gpr1 = cpu_gpr[reg + 1];
@@ -4253,7 +4253,7 @@ static void gen_slbfee_(DisasContext *ctx)
l2 = gen_new_label();
tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rS(ctx->opcode)], -1, l1);
- tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ);
+ tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], CRF_EQ);
tcg_gen_br(l2);
gen_set_label(l1);
tcg_gen_movi_tl(cpu_gpr[rS(ctx->opcode)], 0);
--
2.9.3
^ permalink raw reply related [flat|nested] 73+ messages in thread
* [Qemu-devel] [PULL 04/67] target-ppc: Fix xscmpodp and xscmpudp instructions
2017-01-12 2:02 [Qemu-devel] [PULL 00/67] ppc-for-2.9 queue 20170112 David Gibson
` (2 preceding siblings ...)
2017-01-12 2:02 ` [Qemu-devel] [PULL 03/67] target-ppc: rename CRF_* defines as CRF_*_BIT David Gibson
@ 2017-01-12 2:02 ` David Gibson
2017-01-12 2:02 ` [Qemu-devel] [PULL 05/67] target-ppc: Add xscmpexp[dp, qp] instructions David Gibson
` (64 subsequent siblings)
68 siblings, 0 replies; 73+ messages in thread
From: David Gibson @ 2017-01-12 2:02 UTC (permalink / raw)
To: peter.maydell
Cc: agraf, qemu-ppc, qemu-devel, thuth, lvivier, aik, mdroth,
Bharata B Rao, Nikunj A Dadhania, David Gibson
From: Bharata B Rao <bharata@linux.vnet.ibm.com>
- xscmpodp & xscmpudp are missing flags reset.
- In xscmpodp, VXCC should be set only if VE is 0 for signalling NaN case
and VXCC should be set by explicitly checking for quiet NaN case.
- Comparison is being done only if the operands are not NaNs. However as
per ISA, it should be done even when operands are NaNs.
Signed-off-by: Bharata B Rao <bharata@linux.vnet.ibm.com>
Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
target/ppc/fpu_helper.c | 40 +++++++++++++++++++++++++---------------
1 file changed, 25 insertions(+), 15 deletions(-)
diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c
index d3741b4..fdd3216 100644
--- a/target/ppc/fpu_helper.c
+++ b/target/ppc/fpu_helper.c
@@ -2410,29 +2410,39 @@ void helper_##op(CPUPPCState *env, uint32_t opcode) \
{ \
ppc_vsr_t xa, xb; \
uint32_t cc = 0; \
+ bool vxsnan_flag = false, vxvc_flag = false; \
\
+ helper_reset_fpstatus(env); \
getVSR(xA(opcode), &xa, env); \
getVSR(xB(opcode), &xb, env); \
\
- if (unlikely(float64_is_any_nan(xa.VsrD(0)) || \
- float64_is_any_nan(xb.VsrD(0)))) { \
- if (float64_is_signaling_nan(xa.VsrD(0), &env->fp_status) || \
- float64_is_signaling_nan(xb.VsrD(0), &env->fp_status)) { \
- float_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 0); \
+ if (float64_is_signaling_nan(xa.VsrD(0), &env->fp_status) || \
+ float64_is_signaling_nan(xb.VsrD(0), &env->fp_status)) { \
+ vxsnan_flag = true; \
+ cc = CRF_SO; \
+ if (fpscr_ve == 0 && ordered) { \
+ vxvc_flag = true; \
} \
+ } else if (float64_is_quiet_nan(xa.VsrD(0), &env->fp_status) || \
+ float64_is_quiet_nan(xb.VsrD(0), &env->fp_status)) { \
+ cc = CRF_SO; \
if (ordered) { \
- float_invalid_op_excp(env, POWERPC_EXCP_FP_VXVC, 0); \
+ vxvc_flag = true; \
} \
- cc = 1; \
+ } \
+ if (vxsnan_flag) { \
+ float_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 0); \
+ } \
+ if (vxvc_flag) { \
+ float_invalid_op_excp(env, POWERPC_EXCP_FP_VXVC, 0); \
+ } \
+ \
+ if (float64_lt(xa.VsrD(0), xb.VsrD(0), &env->fp_status)) { \
+ cc |= CRF_LT; \
+ } else if (!float64_le(xa.VsrD(0), xb.VsrD(0), &env->fp_status)) { \
+ cc |= CRF_GT; \
} else { \
- if (float64_lt(xa.VsrD(0), xb.VsrD(0), &env->fp_status)) { \
- cc = 8; \
- } else if (!float64_le(xa.VsrD(0), xb.VsrD(0), \
- &env->fp_status)) { \
- cc = 4; \
- } else { \
- cc = 2; \
- } \
+ cc |= CRF_EQ; \
} \
\
env->fpscr &= ~(0x0F << FPSCR_FPRF); \
--
2.9.3
^ permalink raw reply related [flat|nested] 73+ messages in thread
* [Qemu-devel] [PULL 05/67] target-ppc: Add xscmpexp[dp, qp] instructions
2017-01-12 2:02 [Qemu-devel] [PULL 00/67] ppc-for-2.9 queue 20170112 David Gibson
` (3 preceding siblings ...)
2017-01-12 2:02 ` [Qemu-devel] [PULL 04/67] target-ppc: Fix xscmpodp and xscmpudp instructions David Gibson
@ 2017-01-12 2:02 ` David Gibson
2017-01-12 2:02 ` [Qemu-devel] [PULL 06/67] target-ppc: Add xscmpoqp and xscmpuqp instructions David Gibson
` (63 subsequent siblings)
68 siblings, 0 replies; 73+ messages in thread
From: David Gibson @ 2017-01-12 2:02 UTC (permalink / raw)
To: peter.maydell
Cc: agraf, qemu-ppc, qemu-devel, thuth, lvivier, aik, mdroth,
Bharata B Rao, Nikunj A Dadhania, David Gibson
From: Bharata B Rao <bharata@linux.vnet.ibm.com>
xscmpexpdp: VSX Scalar Compare Exponents Double-Precision
xscmpexpqp: VSX Scalar Compare Exponents Quad-Precision
Signed-off-by: Bharata B Rao <bharata@linux.vnet.ibm.com>
Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
target/ppc/fpu_helper.c | 64 +++++++++++++++++++++++++++++++++++++
target/ppc/helper.h | 2 ++
target/ppc/translate/vsx-impl.inc.c | 2 ++
target/ppc/translate/vsx-ops.inc.c | 6 ++++
4 files changed, 74 insertions(+)
diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c
index fdd3216..8bffafb 100644
--- a/target/ppc/fpu_helper.c
+++ b/target/ppc/fpu_helper.c
@@ -2405,6 +2405,70 @@ VSX_SCALAR_CMP_DP(xscmpgedp, le, 1, 1)
VSX_SCALAR_CMP_DP(xscmpgtdp, lt, 1, 1)
VSX_SCALAR_CMP_DP(xscmpnedp, eq, 0, 0)
+void helper_xscmpexpdp(CPUPPCState *env, uint32_t opcode)
+{
+ ppc_vsr_t xa, xb;
+ int64_t exp_a, exp_b;
+ uint32_t cc;
+
+ getVSR(xA(opcode), &xa, env);
+ getVSR(xB(opcode), &xb, env);
+
+ exp_a = extract64(xa.VsrD(0), 52, 11);
+ exp_b = extract64(xb.VsrD(0), 52, 11);
+
+ if (unlikely(float64_is_any_nan(xa.VsrD(0)) ||
+ float64_is_any_nan(xb.VsrD(0)))) {
+ cc = CRF_SO;
+ } else {
+ if (exp_a < exp_b) {
+ cc = CRF_LT;
+ } else if (exp_a > exp_b) {
+ cc = CRF_GT;
+ } else {
+ cc = CRF_EQ;
+ }
+ }
+
+ env->fpscr &= ~(0x0F << FPSCR_FPRF);
+ env->fpscr |= cc << FPSCR_FPRF;
+ env->crf[BF(opcode)] = cc;
+
+ helper_float_check_status(env);
+}
+
+void helper_xscmpexpqp(CPUPPCState *env, uint32_t opcode)
+{
+ ppc_vsr_t xa, xb;
+ int64_t exp_a, exp_b;
+ uint32_t cc;
+
+ getVSR(rA(opcode) + 32, &xa, env);
+ getVSR(rB(opcode) + 32, &xb, env);
+
+ exp_a = extract64(xa.VsrD(0), 48, 15);
+ exp_b = extract64(xb.VsrD(0), 48, 15);
+
+ if (unlikely(float128_is_any_nan(make_float128(xa.VsrD(0), xa.VsrD(1))) ||
+ float128_is_any_nan(make_float128(xb.VsrD(0), xb.VsrD(1))))) {
+ cc = CRF_SO;
+ } else {
+ if (exp_a < exp_b) {
+ cc = CRF_LT;
+ } else if (exp_a > exp_b) {
+ cc = CRF_GT;
+ } else {
+ cc = CRF_EQ;
+ }
+ }
+
+ env->fpscr &= ~(0x0F << FPSCR_FPRF);
+ env->fpscr |= cc << FPSCR_FPRF;
+ env->crf[BF(opcode)] = cc;
+
+ helper_float_check_status(env);
+}
+
#define VSX_SCALAR_CMP(op, ordered) \
void helper_##op(CPUPPCState *env, uint32_t opcode) \
{ \
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index da00f0a..ba42015 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -404,6 +404,8 @@ DEF_HELPER_2(xscmpeqdp, void, env, i32)
DEF_HELPER_2(xscmpgtdp, void, env, i32)
DEF_HELPER_2(xscmpgedp, void, env, i32)
DEF_HELPER_2(xscmpnedp, void, env, i32)
+DEF_HELPER_2(xscmpexpdp, void, env, i32)
+DEF_HELPER_2(xscmpexpqp, void, env, i32)
DEF_HELPER_2(xscmpodp, void, env, i32)
DEF_HELPER_2(xscmpudp, void, env, i32)
DEF_HELPER_2(xsmaxdp, void, env, i32)
diff --git a/target/ppc/translate/vsx-impl.inc.c b/target/ppc/translate/vsx-impl.inc.c
index 5a27be4..5206258 100644
--- a/target/ppc/translate/vsx-impl.inc.c
+++ b/target/ppc/translate/vsx-impl.inc.c
@@ -624,6 +624,8 @@ GEN_VSX_HELPER_2(xscmpeqdp, 0x0C, 0x00, 0, PPC2_ISA300)
GEN_VSX_HELPER_2(xscmpgtdp, 0x0C, 0x01, 0, PPC2_ISA300)
GEN_VSX_HELPER_2(xscmpgedp, 0x0C, 0x02, 0, PPC2_ISA300)
GEN_VSX_HELPER_2(xscmpnedp, 0x0C, 0x03, 0, PPC2_ISA300)
+GEN_VSX_HELPER_2(xscmpexpdp, 0x0C, 0x07, 0, PPC2_ISA300)
+GEN_VSX_HELPER_2(xscmpexpqp, 0x04, 0x05, 0, PPC2_ISA300)
GEN_VSX_HELPER_2(xscmpodp, 0x0C, 0x05, 0, PPC2_VSX)
GEN_VSX_HELPER_2(xscmpudp, 0x0C, 0x04, 0, PPC2_VSX)
GEN_VSX_HELPER_2(xsmaxdp, 0x00, 0x14, 0, PPC2_VSX)
diff --git a/target/ppc/translate/vsx-ops.inc.c b/target/ppc/translate/vsx-ops.inc.c
index 3d91041..2468ee9 100644
--- a/target/ppc/translate/vsx-ops.inc.c
+++ b/target/ppc/translate/vsx-ops.inc.c
@@ -83,6 +83,10 @@ GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x0C, 0, PPC_NONE, PPC2_VSX),\
GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x0C, 0, PPC_NONE, PPC2_VSX),\
GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x0C, 0, PPC_NONE, PPC2_VSX)
+#define GEN_VSX_XFORM_300(name, opc2, opc3, inval) \
+GEN_HANDLER_E(name, 0x3F, opc2, opc3, inval, PPC_NONE, PPC2_ISA300)
+
+
GEN_XX2FORM(xsabsdp, 0x12, 0x15, PPC2_VSX),
GEN_XX2FORM(xsnabsdp, 0x12, 0x16, PPC2_VSX),
GEN_XX2FORM(xsnegdp, 0x12, 0x17, PPC2_VSX),
@@ -118,6 +122,8 @@ GEN_XX3FORM(xscmpeqdp, 0x0C, 0x00, PPC2_ISA300),
GEN_XX3FORM(xscmpgtdp, 0x0C, 0x01, PPC2_ISA300),
GEN_XX3FORM(xscmpgedp, 0x0C, 0x02, PPC2_ISA300),
GEN_XX3FORM(xscmpnedp, 0x0C, 0x03, PPC2_ISA300),
+GEN_XX3FORM(xscmpexpdp, 0x0C, 0x07, PPC2_ISA300),
+GEN_VSX_XFORM_300(xscmpexpqp, 0x04, 0x05, 0x00600001),
GEN_XX2IFORM(xscmpodp, 0x0C, 0x05, PPC2_VSX),
GEN_XX2IFORM(xscmpudp, 0x0C, 0x04, PPC2_VSX),
GEN_XX3FORM(xsmaxdp, 0x00, 0x14, PPC2_VSX),
--
2.9.3
^ permalink raw reply related [flat|nested] 73+ messages in thread
* [Qemu-devel] [PULL 06/67] target-ppc: Add xscmpoqp and xscmpuqp instructions
2017-01-12 2:02 [Qemu-devel] [PULL 00/67] ppc-for-2.9 queue 20170112 David Gibson
` (4 preceding siblings ...)
2017-01-12 2:02 ` [Qemu-devel] [PULL 05/67] target-ppc: Add xscmpexp[dp, qp] instructions David Gibson
@ 2017-01-12 2:02 ` David Gibson
2017-01-12 2:02 ` [Qemu-devel] [PULL 07/67] target-ppc: implement lxsd and lxssp instructions David Gibson
` (62 subsequent siblings)
68 siblings, 0 replies; 73+ messages in thread
From: David Gibson @ 2017-01-12 2:02 UTC (permalink / raw)
To: peter.maydell
Cc: agraf, qemu-ppc, qemu-devel, thuth, lvivier, aik, mdroth,
Bharata B Rao, Nikunj A Dadhania, David Gibson
From: Bharata B Rao <bharata@linux.vnet.ibm.com>
xscmpoqp - VSX Scalar Compare Ordered Quad-Precision
xscmpuqp - VSX Scalar Compare Unordered Quad-Precision
Signed-off-by: Bharata B Rao <bharata@linux.vnet.ibm.com>
Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
target/ppc/fpu_helper.c | 54 +++++++++++++++++++++++++++++++++++++
target/ppc/helper.h | 2 ++
target/ppc/translate/vsx-impl.inc.c | 2 ++
target/ppc/translate/vsx-ops.inc.c | 2 ++
4 files changed, 60 insertions(+)
diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c
index 8bffafb..696f537 100644
--- a/target/ppc/fpu_helper.c
+++ b/target/ppc/fpu_helper.c
@@ -2519,6 +2519,60 @@ void helper_##op(CPUPPCState *env, uint32_t opcode) \
VSX_SCALAR_CMP(xscmpodp, 1)
VSX_SCALAR_CMP(xscmpudp, 0)
+#define VSX_SCALAR_CMPQ(op, ordered) \
+void helper_##op(CPUPPCState *env, uint32_t opcode) \
+{ \
+ ppc_vsr_t xa, xb; \
+ uint32_t cc = 0; \
+ bool vxsnan_flag = false, vxvc_flag = false; \
+ float128 a, b; \
+ \
+ helper_reset_fpstatus(env); \
+ getVSR(rA(opcode) + 32, &xa, env); \
+ getVSR(rB(opcode) + 32, &xb, env); \
+ \
+ a = make_float128(xa.VsrD(0), xa.VsrD(1)); \
+ b = make_float128(xb.VsrD(0), xb.VsrD(1)); \
+ \
+ if (float128_is_signaling_nan(a, &env->fp_status) || \
+ float128_is_signaling_nan(b, &env->fp_status)) { \
+ vxsnan_flag = true; \
+ cc = CRF_SO; \
+ if (fpscr_ve == 0 && ordered) { \
+ vxvc_flag = true; \
+ } \
+ } else if (float128_is_quiet_nan(a, &env->fp_status) || \
+ float128_is_quiet_nan(b, &env->fp_status)) { \
+ cc = CRF_SO; \
+ if (ordered) { \
+ vxvc_flag = true; \
+ } \
+ } \
+ if (vxsnan_flag) { \
+ float_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 0); \
+ } \
+ if (vxvc_flag) { \
+ float_invalid_op_excp(env, POWERPC_EXCP_FP_VXVC, 0); \
+ } \
+ \
+ if (float128_lt(a, b, &env->fp_status)) { \
+ cc |= CRF_LT; \
+ } else if (!float128_le(a, b, &env->fp_status)) { \
+ cc |= CRF_GT; \
+ } else { \
+ cc |= CRF_EQ; \
+ } \
+ \
+ env->fpscr &= ~(0x0F << FPSCR_FPRF); \
+ env->fpscr |= cc << FPSCR_FPRF; \
+ env->crf[BF(opcode)] = cc; \
+ \
+ float_check_status(env); \
+}
+
+VSX_SCALAR_CMPQ(xscmpoqp, 1)
+VSX_SCALAR_CMPQ(xscmpuqp, 0)
+
/* VSX_MAX_MIN - VSX floating point maximum/minimum
* name - instruction mnemonic
* op - operation (max or min)
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index ba42015..3b26678 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -408,6 +408,8 @@ DEF_HELPER_2(xscmpexpdp, void, env, i32)
DEF_HELPER_2(xscmpexpqp, void, env, i32)
DEF_HELPER_2(xscmpodp, void, env, i32)
DEF_HELPER_2(xscmpudp, void, env, i32)
+DEF_HELPER_2(xscmpoqp, void, env, i32)
+DEF_HELPER_2(xscmpuqp, void, env, i32)
DEF_HELPER_2(xsmaxdp, void, env, i32)
DEF_HELPER_2(xsmindp, void, env, i32)
DEF_HELPER_2(xscvdpsp, void, env, i32)
diff --git a/target/ppc/translate/vsx-impl.inc.c b/target/ppc/translate/vsx-impl.inc.c
index 5206258..ed9588e 100644
--- a/target/ppc/translate/vsx-impl.inc.c
+++ b/target/ppc/translate/vsx-impl.inc.c
@@ -628,6 +628,8 @@ GEN_VSX_HELPER_2(xscmpexpdp, 0x0C, 0x07, 0, PPC2_ISA300)
GEN_VSX_HELPER_2(xscmpexpqp, 0x04, 0x05, 0, PPC2_ISA300)
GEN_VSX_HELPER_2(xscmpodp, 0x0C, 0x05, 0, PPC2_VSX)
GEN_VSX_HELPER_2(xscmpudp, 0x0C, 0x04, 0, PPC2_VSX)
+GEN_VSX_HELPER_2(xscmpoqp, 0x04, 0x04, 0, PPC2_VSX)
+GEN_VSX_HELPER_2(xscmpuqp, 0x04, 0x14, 0, PPC2_VSX)
GEN_VSX_HELPER_2(xsmaxdp, 0x00, 0x14, 0, PPC2_VSX)
GEN_VSX_HELPER_2(xsmindp, 0x00, 0x15, 0, PPC2_VSX)
GEN_VSX_HELPER_2(xscvdpsp, 0x12, 0x10, 0, PPC2_VSX)
diff --git a/target/ppc/translate/vsx-ops.inc.c b/target/ppc/translate/vsx-ops.inc.c
index 2468ee9..7f09527 100644
--- a/target/ppc/translate/vsx-ops.inc.c
+++ b/target/ppc/translate/vsx-ops.inc.c
@@ -126,6 +126,8 @@ GEN_XX3FORM(xscmpexpdp, 0x0C, 0x07, PPC2_ISA300),
GEN_VSX_XFORM_300(xscmpexpqp, 0x04, 0x05, 0x00600001),
GEN_XX2IFORM(xscmpodp, 0x0C, 0x05, PPC2_VSX),
GEN_XX2IFORM(xscmpudp, 0x0C, 0x04, PPC2_VSX),
+GEN_VSX_XFORM_300(xscmpoqp, 0x04, 0x04, 0x00600001),
+GEN_VSX_XFORM_300(xscmpuqp, 0x04, 0x14, 0x00600001),
GEN_XX3FORM(xsmaxdp, 0x00, 0x14, PPC2_VSX),
GEN_XX3FORM(xsmindp, 0x00, 0x15, PPC2_VSX),
GEN_XX2FORM(xscvdpsp, 0x12, 0x10, PPC2_VSX),
--
2.9.3
^ permalink raw reply related [flat|nested] 73+ messages in thread
* [Qemu-devel] [PULL 07/67] target-ppc: implement lxsd and lxssp instructions
2017-01-12 2:02 [Qemu-devel] [PULL 00/67] ppc-for-2.9 queue 20170112 David Gibson
` (5 preceding siblings ...)
2017-01-12 2:02 ` [Qemu-devel] [PULL 06/67] target-ppc: Add xscmpoqp and xscmpuqp instructions David Gibson
@ 2017-01-12 2:02 ` David Gibson
2017-01-12 2:02 ` [Qemu-devel] [PULL 08/67] target-ppc: implement stxsd and stxssp David Gibson
` (61 subsequent siblings)
68 siblings, 0 replies; 73+ messages in thread
From: David Gibson @ 2017-01-12 2:02 UTC (permalink / raw)
To: peter.maydell
Cc: agraf, qemu-ppc, qemu-devel, thuth, lvivier, aik, mdroth,
Nikunj A Dadhania, David Gibson
From: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
lxsd: Load VSX Scalar Dword
lxssp: Load VSX Scalar Single
Moreover, DS-Form instructions shares the same primary opcode, bits
30:31 are used to decode the instruction. Use a common routine to decode
primary opcode(0x39) - ds-form instructions and branch-out depending on
bits 30:31.
Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
target/ppc/translate.c | 25 +++++++++++++++++++++++++
target/ppc/translate/fp-ops.inc.c | 1 -
target/ppc/translate/vsx-impl.inc.c | 21 +++++++++++++++++++++
3 files changed, 46 insertions(+), 1 deletion(-)
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index d3bda1b..9114f85 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -6053,6 +6053,29 @@ GEN_TM_PRIV_NOOP(trechkpt);
#include "translate/spe-impl.inc.c"
+/* Handles lfdp, lxsd, lxssp */
+static void gen_dform39(DisasContext *ctx)
+{
+ switch (ctx->opcode & 0x3) {
+ case 0: /* lfdp */
+ if (ctx->insns_flags2 & PPC2_ISA205) {
+ return gen_lfdp(ctx);
+ }
+ break;
+ case 2: /* lxsd */
+ if (ctx->insns_flags2 & PPC2_ISA300) {
+ return gen_lxsd(ctx);
+ }
+ break;
+ case 3: /* lxssp */
+ if (ctx->insns_flags2 & PPC2_ISA300) {
+ return gen_lxssp(ctx);
+ }
+ break;
+ }
+ return gen_invalid(ctx);
+}
+
static opcode_t opcodes[] = {
GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE),
GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER),
@@ -6125,6 +6148,8 @@ GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B),
GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX),
GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B),
#endif
+/* handles lfdp, lxsd, lxssp */
+GEN_HANDLER_E(dform39, 0x39, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205),
GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING),
diff --git a/target/ppc/translate/fp-ops.inc.c b/target/ppc/translate/fp-ops.inc.c
index d36ab4e..3127fa0 100644
--- a/target/ppc/translate/fp-ops.inc.c
+++ b/target/ppc/translate/fp-ops.inc.c
@@ -68,7 +68,6 @@ GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT)
GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT)
GEN_HANDLER_E(lfiwax, 0x1f, 0x17, 0x1a, 0x00000001, PPC_NONE, PPC2_ISA205),
GEN_HANDLER_E(lfiwzx, 0x1f, 0x17, 0x1b, 0x1, PPC_NONE, PPC2_FP_CVT_ISA206),
-GEN_HANDLER_E(lfdp, 0x39, 0xFF, 0xFF, 0x00200003, PPC_NONE, PPC2_ISA205),
GEN_HANDLER_E(lfdpx, 0x1F, 0x17, 0x18, 0x00200001, PPC_NONE, PPC2_ISA205),
#define GEN_STF(name, stop, opc, type) \
diff --git a/target/ppc/translate/vsx-impl.inc.c b/target/ppc/translate/vsx-impl.inc.c
index ed9588e..1d7cd23 100644
--- a/target/ppc/translate/vsx-impl.inc.c
+++ b/target/ppc/translate/vsx-impl.inc.c
@@ -190,6 +190,27 @@ static void gen_lxvb16x(DisasContext *ctx)
tcg_temp_free(EA);
}
+#define VSX_LOAD_SCALAR_DS(name, operation) \
+static void gen_##name(DisasContext *ctx) \
+{ \
+ TCGv EA; \
+ TCGv_i64 xth = cpu_vsrh(rD(ctx->opcode) + 32); \
+ \
+ if (unlikely(!ctx->altivec_enabled)) { \
+ gen_exception(ctx, POWERPC_EXCP_VPU); \
+ return; \
+ } \
+ gen_set_access_type(ctx, ACCESS_INT); \
+ EA = tcg_temp_new(); \
+ gen_addr_imm_index(ctx, EA, 0x03); \
+ gen_qemu_##operation(ctx, xth, EA); \
+ /* NOTE: cpu_vsrl is undefined */ \
+ tcg_temp_free(EA); \
+}
+
+VSX_LOAD_SCALAR_DS(lxsd, ld64_i64)
+VSX_LOAD_SCALAR_DS(lxssp, ld32fs)
+
#define VSX_STORE_SCALAR(name, operation) \
static void gen_##name(DisasContext *ctx) \
{ \
--
2.9.3
^ permalink raw reply related [flat|nested] 73+ messages in thread
* [Qemu-devel] [PULL 08/67] target-ppc: implement stxsd and stxssp
2017-01-12 2:02 [Qemu-devel] [PULL 00/67] ppc-for-2.9 queue 20170112 David Gibson
` (6 preceding siblings ...)
2017-01-12 2:02 ` [Qemu-devel] [PULL 07/67] target-ppc: implement lxsd and lxssp instructions David Gibson
@ 2017-01-12 2:02 ` David Gibson
2017-01-12 2:02 ` [Qemu-devel] [PULL 09/67] target-ppc: implement lxv/lxvx and stxv/stxvx David Gibson
` (60 subsequent siblings)
68 siblings, 0 replies; 73+ messages in thread
From: David Gibson @ 2017-01-12 2:02 UTC (permalink / raw)
To: peter.maydell
Cc: agraf, qemu-ppc, qemu-devel, thuth, lvivier, aik, mdroth,
Nikunj A Dadhania, David Gibson
From: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
stxsd: Store VSX Scalar Dword
stxssp: Store VSX Scalar SP
Moreover, DQ-Form/DS-FORM instructions shares the same primary
opcode(0x3D). For DQ-FORM bits 29:31 are used, for DS-FORM bits 30:31
are used. Common routine to decode primary opcode(0x3D) -
ds-form/dq-form instructions is required.
Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
target/ppc/translate.c | 34 ++++++++++++++++++++++++++++++++++
target/ppc/translate/fp-ops.inc.c | 1 -
target/ppc/translate/vsx-impl.inc.c | 21 +++++++++++++++++++++
3 files changed, 55 insertions(+), 1 deletion(-)
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 9114f85..a1bf74c 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -6076,6 +6076,38 @@ static void gen_dform39(DisasContext *ctx)
return gen_invalid(ctx);
}
+/* handles stfdp, stxsd, stxssp */
+static void gen_dform3D(DisasContext *ctx)
+{
+ if ((ctx->opcode & 3) == 1) { /* DQ-FORM */
+ switch (ctx->opcode & 0x7) {
+ case 1: /* lxv */
+ break;
+ case 5: /* stxv */
+ break;
+ }
+ } else { /* DS-FORM */
+ switch (ctx->opcode & 0x3) {
+ case 0: /* stfdp */
+ if (ctx->insns_flags2 & PPC2_ISA205) {
+ return gen_stfdp(ctx);
+ }
+ break;
+ case 2: /* stxsd */
+ if (ctx->insns_flags2 & PPC2_ISA300) {
+ return gen_stxsd(ctx);
+ }
+ break;
+ case 3: /* stxssp */
+ if (ctx->insns_flags2 & PPC2_ISA300) {
+ return gen_stxssp(ctx);
+ }
+ break;
+ }
+ }
+ return gen_invalid(ctx);
+}
+
static opcode_t opcodes[] = {
GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE),
GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER),
@@ -6150,6 +6182,8 @@ GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B),
#endif
/* handles lfdp, lxsd, lxssp */
GEN_HANDLER_E(dform39, 0x39, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205),
+/* handles stfdp, stxsd, stxssp */
+GEN_HANDLER_E(dform3D, 0x3D, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205),
GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING),
diff --git a/target/ppc/translate/fp-ops.inc.c b/target/ppc/translate/fp-ops.inc.c
index 3127fa0..3c6d05a 100644
--- a/target/ppc/translate/fp-ops.inc.c
+++ b/target/ppc/translate/fp-ops.inc.c
@@ -87,7 +87,6 @@ GEN_STXF(name, stop, 0x17, op | 0x00, type)
GEN_STFS(stfd, st64_i64, 0x16, PPC_FLOAT)
GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT)
GEN_STXF(stfiw, st32fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX)
-GEN_HANDLER_E(stfdp, 0x3D, 0xFF, 0xFF, 0x00200003, PPC_NONE, PPC2_ISA205),
GEN_HANDLER_E(stfdpx, 0x1F, 0x17, 0x1C, 0x00200001, PPC_NONE, PPC2_ISA205),
GEN_HANDLER(frsqrtes, 0x3B, 0x1A, 0xFF, 0x001F07C0, PPC_FLOAT_FRSQRTES),
diff --git a/target/ppc/translate/vsx-impl.inc.c b/target/ppc/translate/vsx-impl.inc.c
index 1d7cd23..8ee44cf 100644
--- a/target/ppc/translate/vsx-impl.inc.c
+++ b/target/ppc/translate/vsx-impl.inc.c
@@ -332,6 +332,27 @@ static void gen_stxvb16x(DisasContext *ctx)
tcg_temp_free(EA);
}
+#define VSX_STORE_SCALAR_DS(name, operation) \
+static void gen_##name(DisasContext *ctx) \
+{ \
+ TCGv EA; \
+ TCGv_i64 xth = cpu_vsrh(rD(ctx->opcode) + 32); \
+ \
+ if (unlikely(!ctx->altivec_enabled)) { \
+ gen_exception(ctx, POWERPC_EXCP_VPU); \
+ return; \
+ } \
+ gen_set_access_type(ctx, ACCESS_INT); \
+ EA = tcg_temp_new(); \
+ gen_addr_imm_index(ctx, EA, 0x03); \
+ gen_qemu_##operation(ctx, xth, EA); \
+ /* NOTE: cpu_vsrl is undefined */ \
+ tcg_temp_free(EA); \
+}
+
+VSX_LOAD_SCALAR_DS(stxsd, st64_i64)
+VSX_LOAD_SCALAR_DS(stxssp, st32fs)
+
#define MV_VSRW(name, tcgop1, tcgop2, target, source) \
static void gen_##name(DisasContext *ctx) \
{ \
--
2.9.3
^ permalink raw reply related [flat|nested] 73+ messages in thread
* [Qemu-devel] [PULL 09/67] target-ppc: implement lxv/lxvx and stxv/stxvx
2017-01-12 2:02 [Qemu-devel] [PULL 00/67] ppc-for-2.9 queue 20170112 David Gibson
` (7 preceding siblings ...)
2017-01-12 2:02 ` [Qemu-devel] [PULL 08/67] target-ppc: implement stxsd and stxssp David Gibson
@ 2017-01-12 2:02 ` David Gibson
2017-01-12 2:02 ` [Qemu-devel] [PULL 10/67] target-ppc: Implement bcdcfsq. instruction David Gibson
` (59 subsequent siblings)
68 siblings, 0 replies; 73+ messages in thread
From: David Gibson @ 2017-01-12 2:02 UTC (permalink / raw)
To: peter.maydell
Cc: agraf, qemu-ppc, qemu-devel, thuth, lvivier, aik, mdroth,
Nikunj A Dadhania, David Gibson
From: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
lxv: Load VSX Vector
lxvx: Load VSX Vector Indexed
Little/Big-endian Storage
+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
|F0|F1|F2|F3|F4|F5|F6|F7|E0|E1|E2|E3|E4|E5|E6|E7|
+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
Vector load results:
BE:
+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
|F0|F1|F2|F3|F4|F5|F6|F7|E0|E1|E2|E3|E4|E5|E6|E7|
+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
LE:
+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
|E7|E6|E5|E4|E3|E2|E1|E0|F7|F6|F5|F4|F3|F2|F1|F0|
+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
stxv: Store VSX Vector
stxvx: Store VSX Vector Indexed
Vector (8-bit elements) in BE:
+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
|F0|F1|F2|F3|F4|F5|F6|F7|E0|E1|E2|E3|E4|E5|E6|E7|
+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
Vector (8-bit elements) in LE:
+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
|E7|E6|E5|E4|E3|E2|E1|E0|F7|F6|F5|F4|F3|F2|F1|F0|
+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
Store results in following:
+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
|F0|F1|F2|F3|F4|F5|F6|F7|E0|E1|E2|E3|E4|E5|E6|E7|
+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
target/ppc/internal.h | 1 +
target/ppc/translate.c | 10 ++++++--
target/ppc/translate/vsx-impl.inc.c | 50 +++++++++++++++++++++++++++++++++++++
target/ppc/translate/vsx-ops.inc.c | 2 ++
4 files changed, 61 insertions(+), 2 deletions(-)
diff --git a/target/ppc/internal.h b/target/ppc/internal.h
index 9a4a74a..e83ea45 100644
--- a/target/ppc/internal.h
+++ b/target/ppc/internal.h
@@ -187,6 +187,7 @@ EXTRACT_HELPER(DCM, 10, 6)
/* DFP Z23-form */
EXTRACT_HELPER(RMC, 9, 2)
+EXTRACT_HELPER_SPLIT(DQxT, 3, 1, 21, 5);
EXTRACT_HELPER_SPLIT(xT, 0, 1, 21, 5);
EXTRACT_HELPER_SPLIT(xS, 0, 1, 21, 5);
EXTRACT_HELPER_SPLIT(xA, 2, 1, 16, 5);
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index a1bf74c..f68f427 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -6076,14 +6076,20 @@ static void gen_dform39(DisasContext *ctx)
return gen_invalid(ctx);
}
-/* handles stfdp, stxsd, stxssp */
+/* handles stfdp, lxv, stxsd, stxssp lxvx */
static void gen_dform3D(DisasContext *ctx)
{
if ((ctx->opcode & 3) == 1) { /* DQ-FORM */
switch (ctx->opcode & 0x7) {
case 1: /* lxv */
+ if (ctx->insns_flags2 & PPC2_ISA300) {
+ return gen_lxv(ctx);
+ }
break;
case 5: /* stxv */
+ if (ctx->insns_flags2 & PPC2_ISA300) {
+ return gen_stxv(ctx);
+ }
break;
}
} else { /* DS-FORM */
@@ -6182,7 +6188,7 @@ GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B),
#endif
/* handles lfdp, lxsd, lxssp */
GEN_HANDLER_E(dform39, 0x39, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205),
-/* handles stfdp, stxsd, stxssp */
+/* handles stfdp, lxv, stxsd, stxssp, stxv */
GEN_HANDLER_E(dform3D, 0x3D, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205),
GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
diff --git a/target/ppc/translate/vsx-impl.inc.c b/target/ppc/translate/vsx-impl.inc.c
index 8ee44cf..2fbdbd2 100644
--- a/target/ppc/translate/vsx-impl.inc.c
+++ b/target/ppc/translate/vsx-impl.inc.c
@@ -190,6 +190,56 @@ static void gen_lxvb16x(DisasContext *ctx)
tcg_temp_free(EA);
}
+#define VSX_VECTOR_LOAD_STORE(name, op, indexed) \
+static void gen_##name(DisasContext *ctx) \
+{ \
+ int xt; \
+ TCGv EA; \
+ TCGv_i64 xth, xtl; \
+ \
+ if (indexed) { \
+ xt = xT(ctx->opcode); \
+ } else { \
+ xt = DQxT(ctx->opcode); \
+ } \
+ xth = cpu_vsrh(xt); \
+ xtl = cpu_vsrl(xt); \
+ \
+ if (xt < 32) { \
+ if (unlikely(!ctx->vsx_enabled)) { \
+ gen_exception(ctx, POWERPC_EXCP_VSXU); \
+ return; \
+ } \
+ } else { \
+ if (unlikely(!ctx->altivec_enabled)) { \
+ gen_exception(ctx, POWERPC_EXCP_VPU); \
+ return; \
+ } \
+ } \
+ gen_set_access_type(ctx, ACCESS_INT); \
+ EA = tcg_temp_new(); \
+ if (indexed) { \
+ gen_addr_reg_index(ctx, EA); \
+ } else { \
+ gen_addr_imm_index(ctx, EA, 0x0F); \
+ } \
+ if (ctx->le_mode) { \
+ tcg_gen_qemu_##op(xtl, EA, ctx->mem_idx, MO_LEQ); \
+ tcg_gen_addi_tl(EA, EA, 8); \
+ tcg_gen_qemu_##op(xth, EA, ctx->mem_idx, MO_LEQ); \
+ } else { \
+ tcg_gen_qemu_##op(xth, EA, ctx->mem_idx, MO_BEQ); \
+ tcg_gen_addi_tl(EA, EA, 8); \
+ tcg_gen_qemu_##op(xtl, EA, ctx->mem_idx, MO_BEQ); \
+ } \
+ tcg_temp_free(EA); \
+}
+
+VSX_VECTOR_LOAD_STORE(lxv, ld_i64, 0)
+VSX_VECTOR_LOAD_STORE(stxv, st_i64, 0)
+VSX_VECTOR_LOAD_STORE(lxvx, ld_i64, 1)
+VSX_VECTOR_LOAD_STORE(stxvx, st_i64, 1)
+
#define VSX_LOAD_SCALAR_DS(name, operation) \
static void gen_##name(DisasContext *ctx) \
{ \
diff --git a/target/ppc/translate/vsx-ops.inc.c b/target/ppc/translate/vsx-ops.inc.c
index 7f09527..8a1cbe0 100644
--- a/target/ppc/translate/vsx-ops.inc.c
+++ b/target/ppc/translate/vsx-ops.inc.c
@@ -9,6 +9,7 @@ GEN_HANDLER_E(lxvdsx, 0x1F, 0x0C, 0x0A, 0, PPC_NONE, PPC2_VSX),
GEN_HANDLER_E(lxvw4x, 0x1F, 0x0C, 0x18, 0, PPC_NONE, PPC2_VSX),
GEN_HANDLER_E(lxvh8x, 0x1F, 0x0C, 0x19, 0, PPC_NONE, PPC2_ISA300),
GEN_HANDLER_E(lxvb16x, 0x1F, 0x0C, 0x1B, 0, PPC_NONE, PPC2_ISA300),
+GEN_HANDLER_E(lxvx, 0x1F, 0x0C, 0x08, 0x00000040, PPC_NONE, PPC2_ISA300),
GEN_HANDLER_E(stxsdx, 0x1F, 0xC, 0x16, 0, PPC_NONE, PPC2_VSX),
GEN_HANDLER_E(stxsibx, 0x1F, 0xD, 0x1C, 0, PPC_NONE, PPC2_ISA300),
@@ -19,6 +20,7 @@ GEN_HANDLER_E(stxvd2x, 0x1F, 0xC, 0x1E, 0, PPC_NONE, PPC2_VSX),
GEN_HANDLER_E(stxvw4x, 0x1F, 0xC, 0x1C, 0, PPC_NONE, PPC2_VSX),
GEN_HANDLER_E(stxvh8x, 0x1F, 0x0C, 0x1D, 0, PPC_NONE, PPC2_ISA300),
GEN_HANDLER_E(stxvb16x, 0x1F, 0x0C, 0x1F, 0, PPC_NONE, PPC2_ISA300),
+GEN_HANDLER_E(stxvx, 0x1F, 0x0C, 0x0C, 0, PPC_NONE, PPC2_ISA300),
GEN_HANDLER_E(mfvsrwz, 0x1F, 0x13, 0x03, 0x0000F800, PPC_NONE, PPC2_VSX207),
GEN_HANDLER_E(mtvsrwa, 0x1F, 0x13, 0x06, 0x0000F800, PPC_NONE, PPC2_VSX207),
--
2.9.3
^ permalink raw reply related [flat|nested] 73+ messages in thread
* [Qemu-devel] [PULL 10/67] target-ppc: Implement bcdcfsq. instruction
2017-01-12 2:02 [Qemu-devel] [PULL 00/67] ppc-for-2.9 queue 20170112 David Gibson
` (8 preceding siblings ...)
2017-01-12 2:02 ` [Qemu-devel] [PULL 09/67] target-ppc: implement lxv/lxvx and stxv/stxvx David Gibson
@ 2017-01-12 2:02 ` David Gibson
2017-01-12 2:02 ` [Qemu-devel] [PULL 11/67] target-ppc: Implement bcdctsq. instruction David Gibson
` (58 subsequent siblings)
68 siblings, 0 replies; 73+ messages in thread
From: David Gibson @ 2017-01-12 2:02 UTC (permalink / raw)
To: peter.maydell
Cc: agraf, qemu-ppc, qemu-devel, thuth, lvivier, aik, mdroth,
Jose Ricardo Ziviani, David Gibson
From: Jose Ricardo Ziviani <joserz@linux.vnet.ibm.com>
bcdcfsq.: Decimal convert from signed quadword. It is not possible
to convert values less than -10^31-1 or greater than 10^31-1 to be
represented in packed decimal format.
Signed-off-by: Jose Ricardo Ziviani <joserz@linux.vnet.ibm.com>
[dwg: Corrected constant which should be 10^16-1 but was 10^17-1]
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
target/ppc/helper.h | 1 +
target/ppc/int_helper.c | 38 +++++++++++++++++++++++++++++++++++++
target/ppc/translate/vmx-impl.inc.c | 7 +++++++
3 files changed, 46 insertions(+)
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index 3b26678..efb384a 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -382,6 +382,7 @@ DEF_HELPER_3(bcdcfn, i32, avr, avr, i32)
DEF_HELPER_3(bcdctn, i32, avr, avr, i32)
DEF_HELPER_3(bcdcfz, i32, avr, avr, i32)
DEF_HELPER_3(bcdctz, i32, avr, avr, i32)
+DEF_HELPER_3(bcdcfsq, i32, avr, avr, i32)
DEF_HELPER_2(xsadddp, void, env, i32)
DEF_HELPER_2(xssubdp, void, env, i32)
diff --git a/target/ppc/int_helper.c b/target/ppc/int_helper.c
index 1667c94..e077251 100644
--- a/target/ppc/int_helper.c
+++ b/target/ppc/int_helper.c
@@ -2874,6 +2874,44 @@ uint32_t helper_bcdctz(ppc_avr_t *r, ppc_avr_t *b, uint32_t ps)
return cr;
}
+uint32_t helper_bcdcfsq(ppc_avr_t *r, ppc_avr_t *b, uint32_t ps)
+{
+ int i;
+ int cr = 0;
+ uint64_t lo_value;
+ uint64_t hi_value;
+ ppc_avr_t ret = { .u64 = { 0, 0 } };
+
+ if (b->s64[HI_IDX] < 0) {
+ lo_value = -b->s64[LO_IDX];
+ hi_value = ~b->u64[HI_IDX] + !lo_value;
+ bcd_put_digit(&ret, 0xD, 0);
+ } else {
+ lo_value = b->u64[LO_IDX];
+ hi_value = b->u64[HI_IDX];
+ bcd_put_digit(&ret, bcd_preferred_sgn(0, ps), 0);
+ }
+
+ if (divu128(&lo_value, &hi_value, 1000000000000000ULL) ||
+ lo_value > 9999999999999999ULL) {
+ cr = CRF_SO;
+ }
+
+ for (i = 1; i < 16; hi_value /= 10, i++) {
+ bcd_put_digit(&ret, hi_value % 10, i);
+ }
+
+ for (; i < 32; lo_value /= 10, i++) {
+ bcd_put_digit(&ret, lo_value % 10, i);
+ }
+
+ cr |= bcd_cmp_zero(&ret);
+
+ *r = ret;
+
+ return cr;
+}
+
void helper_vsbox(ppc_avr_t *r, ppc_avr_t *a)
{
int i;
diff --git a/target/ppc/translate/vmx-impl.inc.c b/target/ppc/translate/vmx-impl.inc.c
index 7143eb3..36141e5 100644
--- a/target/ppc/translate/vmx-impl.inc.c
+++ b/target/ppc/translate/vmx-impl.inc.c
@@ -989,10 +989,14 @@ GEN_BCD2(bcdcfn)
GEN_BCD2(bcdctn)
GEN_BCD2(bcdcfz)
GEN_BCD2(bcdctz)
+GEN_BCD2(bcdcfsq)
static void gen_xpnd04_1(DisasContext *ctx)
{
switch (opc4(ctx->opcode)) {
+ case 2:
+ gen_bcdcfsq(ctx);
+ break;
case 4:
gen_bcdctz(ctx);
break;
@@ -1014,6 +1018,9 @@ static void gen_xpnd04_1(DisasContext *ctx)
static void gen_xpnd04_2(DisasContext *ctx)
{
switch (opc4(ctx->opcode)) {
+ case 2:
+ gen_bcdcfsq(ctx);
+ break;
case 4:
gen_bcdctz(ctx);
break;
--
2.9.3
^ permalink raw reply related [flat|nested] 73+ messages in thread
* [Qemu-devel] [PULL 11/67] target-ppc: Implement bcdctsq. instruction
2017-01-12 2:02 [Qemu-devel] [PULL 00/67] ppc-for-2.9 queue 20170112 David Gibson
` (9 preceding siblings ...)
2017-01-12 2:02 ` [Qemu-devel] [PULL 10/67] target-ppc: Implement bcdcfsq. instruction David Gibson
@ 2017-01-12 2:02 ` David Gibson
2017-01-12 2:02 ` [Qemu-devel] [PULL 12/67] target-ppc: Implement bcdcpsgn. instruction David Gibson
` (57 subsequent siblings)
68 siblings, 0 replies; 73+ messages in thread
From: David Gibson @ 2017-01-12 2:02 UTC (permalink / raw)
To: peter.maydell
Cc: agraf, qemu-ppc, qemu-devel, thuth, lvivier, aik, mdroth,
Jose Ricardo Ziviani, David Gibson
From: Jose Ricardo Ziviani <joserz@linux.vnet.ibm.com>
bcdctsq.: Decimal convert to signed quadword. It is possible to
convert packed decimal values to signed quadwords.
Signed-off-by: Jose Ricardo Ziviani <joserz@linux.vnet.ibm.com>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
target/ppc/helper.h | 1 +
target/ppc/int_helper.c | 40 +++++++++++++++++++++++++++++++++++++
target/ppc/translate/vmx-impl.inc.c | 7 +++++++
3 files changed, 48 insertions(+)
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index efb384a..d404e0b 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -383,6 +383,7 @@ DEF_HELPER_3(bcdctn, i32, avr, avr, i32)
DEF_HELPER_3(bcdcfz, i32, avr, avr, i32)
DEF_HELPER_3(bcdctz, i32, avr, avr, i32)
DEF_HELPER_3(bcdcfsq, i32, avr, avr, i32)
+DEF_HELPER_3(bcdctsq, i32, avr, avr, i32)
DEF_HELPER_2(xsadddp, void, env, i32)
DEF_HELPER_2(xssubdp, void, env, i32)
diff --git a/target/ppc/int_helper.c b/target/ppc/int_helper.c
index e077251..5a7ceb8 100644
--- a/target/ppc/int_helper.c
+++ b/target/ppc/int_helper.c
@@ -2912,6 +2912,46 @@ uint32_t helper_bcdcfsq(ppc_avr_t *r, ppc_avr_t *b, uint32_t ps)
return cr;
}
+uint32_t helper_bcdctsq(ppc_avr_t *r, ppc_avr_t *b, uint32_t ps)
+{
+ uint8_t i;
+ int cr;
+ uint64_t carry;
+ uint64_t unused;
+ uint64_t lo_value;
+ uint64_t hi_value = 0;
+ int sgnb = bcd_get_sgn(b);
+ int invalid = (sgnb == 0);
+
+ lo_value = bcd_get_digit(b, 31, &invalid);
+ for (i = 30; i > 0; i--) {
+ mulu64(&lo_value, &carry, lo_value, 10ULL);
+ mulu64(&hi_value, &unused, hi_value, 10ULL);
+ lo_value += bcd_get_digit(b, i, &invalid);
+ hi_value += carry;
+
+ if (unlikely(invalid)) {
+ break;
+ }
+ }
+
+ if (sgnb == -1) {
+ r->s64[LO_IDX] = -lo_value;
+ r->s64[HI_IDX] = ~hi_value + !r->s64[LO_IDX];
+ } else {
+ r->s64[LO_IDX] = lo_value;
+ r->s64[HI_IDX] = hi_value;
+ }
+
+ cr = bcd_cmp_zero(b);
+
+ if (unlikely(invalid)) {
+ cr = CRF_SO;
+ }
+
+ return cr;
+}
+
void helper_vsbox(ppc_avr_t *r, ppc_avr_t *a)
{
int i;
diff --git a/target/ppc/translate/vmx-impl.inc.c b/target/ppc/translate/vmx-impl.inc.c
index 36141e5..1579b58 100644
--- a/target/ppc/translate/vmx-impl.inc.c
+++ b/target/ppc/translate/vmx-impl.inc.c
@@ -990,10 +990,14 @@ GEN_BCD2(bcdctn)
GEN_BCD2(bcdcfz)
GEN_BCD2(bcdctz)
GEN_BCD2(bcdcfsq)
+GEN_BCD2(bcdctsq)
static void gen_xpnd04_1(DisasContext *ctx)
{
switch (opc4(ctx->opcode)) {
+ case 0:
+ gen_bcdctsq(ctx);
+ break;
case 2:
gen_bcdcfsq(ctx);
break;
@@ -1018,6 +1022,9 @@ static void gen_xpnd04_1(DisasContext *ctx)
static void gen_xpnd04_2(DisasContext *ctx)
{
switch (opc4(ctx->opcode)) {
+ case 0:
+ gen_bcdctsq(ctx);
+ break;
case 2:
gen_bcdcfsq(ctx);
break;
--
2.9.3
^ permalink raw reply related [flat|nested] 73+ messages in thread
* [Qemu-devel] [PULL 12/67] target-ppc: Implement bcdcpsgn. instruction
2017-01-12 2:02 [Qemu-devel] [PULL 00/67] ppc-for-2.9 queue 20170112 David Gibson
` (10 preceding siblings ...)
2017-01-12 2:02 ` [Qemu-devel] [PULL 11/67] target-ppc: Implement bcdctsq. instruction David Gibson
@ 2017-01-12 2:02 ` David Gibson
2017-01-12 2:02 ` [Qemu-devel] [PULL 13/67] target-ppc: Implement bcdsetsgn. instruction David Gibson
` (56 subsequent siblings)
68 siblings, 0 replies; 73+ messages in thread
From: David Gibson @ 2017-01-12 2:02 UTC (permalink / raw)
To: peter.maydell
Cc: agraf, qemu-ppc, qemu-devel, thuth, lvivier, aik, mdroth,
Jose Ricardo Ziviani, David Gibson
From: Jose Ricardo Ziviani <joserz@linux.vnet.ibm.com>
bcdcpsgn.: Decimal copy sign. Given two registers vra and vrb, it
copies the vra value with vrb sign to the result register vrt.
Signed-off-by: Jose Ricardo Ziviani <joserz@linux.vnet.ibm.com>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
target/ppc/helper.h | 1 +
target/ppc/int_helper.c | 23 +++++++++++++++++++++++
target/ppc/translate/vmx-impl.inc.c | 3 +++
target/ppc/translate/vmx-ops.inc.c | 2 +-
4 files changed, 28 insertions(+), 1 deletion(-)
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index d404e0b..2974101 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -384,6 +384,7 @@ DEF_HELPER_3(bcdcfz, i32, avr, avr, i32)
DEF_HELPER_3(bcdctz, i32, avr, avr, i32)
DEF_HELPER_3(bcdcfsq, i32, avr, avr, i32)
DEF_HELPER_3(bcdctsq, i32, avr, avr, i32)
+DEF_HELPER_4(bcdcpsgn, i32, avr, avr, avr, i32)
DEF_HELPER_2(xsadddp, void, env, i32)
DEF_HELPER_2(xssubdp, void, env, i32)
diff --git a/target/ppc/int_helper.c b/target/ppc/int_helper.c
index 5a7ceb8..8021c48 100644
--- a/target/ppc/int_helper.c
+++ b/target/ppc/int_helper.c
@@ -2952,6 +2952,29 @@ uint32_t helper_bcdctsq(ppc_avr_t *r, ppc_avr_t *b, uint32_t ps)
return cr;
}
+uint32_t helper_bcdcpsgn(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, uint32_t ps)
+{
+ int i;
+ int invalid = 0;
+
+ if (bcd_get_sgn(a) == 0 || bcd_get_sgn(b) == 0) {
+ return CRF_SO;
+ }
+
+ *r = *a;
+ bcd_put_digit(r, b->u8[BCD_DIG_BYTE(0)] & 0xF, 0);
+
+ for (i = 1; i < 32; i++) {
+ bcd_get_digit(a, i, &invalid);
+ bcd_get_digit(b, i, &invalid);
+ if (unlikely(invalid)) {
+ return CRF_SO;
+ }
+ }
+
+ return bcd_cmp_zero(r);
+}
+
void helper_vsbox(ppc_avr_t *r, ppc_avr_t *a)
{
int i;
diff --git a/target/ppc/translate/vmx-impl.inc.c b/target/ppc/translate/vmx-impl.inc.c
index 1579b58..c14b666 100644
--- a/target/ppc/translate/vmx-impl.inc.c
+++ b/target/ppc/translate/vmx-impl.inc.c
@@ -991,6 +991,7 @@ GEN_BCD2(bcdcfz)
GEN_BCD2(bcdctz)
GEN_BCD2(bcdcfsq)
GEN_BCD2(bcdctsq)
+GEN_BCD(bcdcpsgn);
static void gen_xpnd04_1(DisasContext *ctx)
{
@@ -1056,6 +1057,8 @@ GEN_VXFORM_DUAL(vsubuhm, PPC_ALTIVEC, PPC_NONE, \
bcdsub, PPC_NONE, PPC2_ALTIVEC_207)
GEN_VXFORM_DUAL(vsubuhs, PPC_ALTIVEC, PPC_NONE, \
bcdsub, PPC_NONE, PPC2_ALTIVEC_207)
+GEN_VXFORM_DUAL(vaddshs, PPC_ALTIVEC, PPC_NONE, \
+ bcdcpsgn, PPC_NONE, PPC2_ISA300)
static void gen_vsbox(DisasContext *ctx)
{
diff --git a/target/ppc/translate/vmx-ops.inc.c b/target/ppc/translate/vmx-ops.inc.c
index f02b3be..70d7d2b 100644
--- a/target/ppc/translate/vmx-ops.inc.c
+++ b/target/ppc/translate/vmx-ops.inc.c
@@ -131,7 +131,7 @@ GEN_VXFORM_DUAL(vaddubs, vmul10uq, 0, 8, PPC_ALTIVEC, PPC_NONE),
GEN_VXFORM_DUAL(vadduhs, vmul10euq, 0, 9, PPC_ALTIVEC, PPC_NONE),
GEN_VXFORM(vadduws, 0, 10),
GEN_VXFORM(vaddsbs, 0, 12),
-GEN_VXFORM(vaddshs, 0, 13),
+GEN_VXFORM_DUAL(vaddshs, bcdcpsgn, 0, 13, PPC_ALTIVEC, PPC_NONE),
GEN_VXFORM(vaddsws, 0, 14),
GEN_VXFORM_DUAL(vsububs, bcdadd, 0, 24, PPC_ALTIVEC, PPC_NONE),
GEN_VXFORM_DUAL(vsubuhs, bcdsub, 0, 25, PPC_ALTIVEC, PPC_NONE),
--
2.9.3
^ permalink raw reply related [flat|nested] 73+ messages in thread
* [Qemu-devel] [PULL 13/67] target-ppc: Implement bcdsetsgn. instruction
2017-01-12 2:02 [Qemu-devel] [PULL 00/67] ppc-for-2.9 queue 20170112 David Gibson
` (11 preceding siblings ...)
2017-01-12 2:02 ` [Qemu-devel] [PULL 12/67] target-ppc: Implement bcdcpsgn. instruction David Gibson
@ 2017-01-12 2:02 ` David Gibson
2017-01-12 2:02 ` [Qemu-devel] [PULL 14/67] target-ppc: add vextu[bhw][lr]x instructions David Gibson
` (55 subsequent siblings)
68 siblings, 0 replies; 73+ messages in thread
From: David Gibson @ 2017-01-12 2:02 UTC (permalink / raw)
To: peter.maydell
Cc: agraf, qemu-ppc, qemu-devel, thuth, lvivier, aik, mdroth,
Jose Ricardo Ziviani, David Gibson
From: Jose Ricardo Ziviani <joserz@linux.vnet.ibm.com>
bcdsetsgn.: Decimal set sign. This instruction copies the register
value to the result register but adjust the signal according to
the preferred sign value.
Signed-off-by: Jose Ricardo Ziviani <joserz@linux.vnet.ibm.com>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
target/ppc/helper.h | 1 +
target/ppc/int_helper.c | 19 +++++++++++++++++++
target/ppc/translate/vmx-impl.inc.c | 8 ++++++++
3 files changed, 28 insertions(+)
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index 2974101..ac8901f 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -385,6 +385,7 @@ DEF_HELPER_3(bcdctz, i32, avr, avr, i32)
DEF_HELPER_3(bcdcfsq, i32, avr, avr, i32)
DEF_HELPER_3(bcdctsq, i32, avr, avr, i32)
DEF_HELPER_4(bcdcpsgn, i32, avr, avr, avr, i32)
+DEF_HELPER_3(bcdsetsgn, i32, avr, avr, i32)
DEF_HELPER_2(xsadddp, void, env, i32)
DEF_HELPER_2(xssubdp, void, env, i32)
diff --git a/target/ppc/int_helper.c b/target/ppc/int_helper.c
index 8021c48..4259876 100644
--- a/target/ppc/int_helper.c
+++ b/target/ppc/int_helper.c
@@ -2975,6 +2975,25 @@ uint32_t helper_bcdcpsgn(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, uint32_t ps)
return bcd_cmp_zero(r);
}
+uint32_t helper_bcdsetsgn(ppc_avr_t *r, ppc_avr_t *b, uint32_t ps)
+{
+ int i;
+ int invalid = 0;
+ int sgnb = bcd_get_sgn(b);
+
+ *r = *b;
+ bcd_put_digit(r, bcd_preferred_sgn(sgnb, ps), 0);
+
+ for (i = 1; i < 32; i++) {
+ bcd_get_digit(b, i, &invalid);
+ if (unlikely(invalid)) {
+ return CRF_SO;
+ }
+ }
+
+ return bcd_cmp_zero(r);
+}
+
void helper_vsbox(ppc_avr_t *r, ppc_avr_t *a)
{
int i;
diff --git a/target/ppc/translate/vmx-impl.inc.c b/target/ppc/translate/vmx-impl.inc.c
index c14b666..b188e60 100644
--- a/target/ppc/translate/vmx-impl.inc.c
+++ b/target/ppc/translate/vmx-impl.inc.c
@@ -991,6 +991,7 @@ GEN_BCD2(bcdcfz)
GEN_BCD2(bcdctz)
GEN_BCD2(bcdcfsq)
GEN_BCD2(bcdctsq)
+GEN_BCD2(bcdsetsgn)
GEN_BCD(bcdcpsgn);
static void gen_xpnd04_1(DisasContext *ctx)
@@ -1014,6 +1015,9 @@ static void gen_xpnd04_1(DisasContext *ctx)
case 7:
gen_bcdcfn(ctx);
break;
+ case 31:
+ gen_bcdsetsgn(ctx);
+ break;
default:
gen_invalid(ctx);
break;
@@ -1038,12 +1042,16 @@ static void gen_xpnd04_2(DisasContext *ctx)
case 7:
gen_bcdcfn(ctx);
break;
+ case 31:
+ gen_bcdsetsgn(ctx);
+ break;
default:
gen_invalid(ctx);
break;
}
}
+
GEN_VXFORM_DUAL(vsubcuw, PPC_ALTIVEC, PPC_NONE, \
xpnd04_1, PPC_NONE, PPC2_ISA300)
GEN_VXFORM_DUAL(vsubsws, PPC_ALTIVEC, PPC_NONE, \
--
2.9.3
^ permalink raw reply related [flat|nested] 73+ messages in thread
* [Qemu-devel] [PULL 14/67] target-ppc: add vextu[bhw][lr]x instructions
2017-01-12 2:02 [Qemu-devel] [PULL 00/67] ppc-for-2.9 queue 20170112 David Gibson
` (12 preceding siblings ...)
2017-01-12 2:02 ` [Qemu-devel] [PULL 13/67] target-ppc: Implement bcdsetsgn. instruction David Gibson
@ 2017-01-12 2:02 ` David Gibson
2017-01-12 2:02 ` [Qemu-devel] [PULL 15/67] pseries: Always use core objects for CPU construction David Gibson
` (54 subsequent siblings)
68 siblings, 0 replies; 73+ messages in thread
From: David Gibson @ 2017-01-12 2:02 UTC (permalink / raw)
To: peter.maydell
Cc: agraf, qemu-ppc, qemu-devel, thuth, lvivier, aik, mdroth,
Avinesh Kumar, Hariharan T . S .,
Nikunj A Dadhania, David Gibson
From: Avinesh Kumar <avinesku@linux.vnet.ibm.com>
vextublx: Vector Extract Unsigned Byte Left
vextuhlx: Vector Extract Unsigned Halfword Left
vextuwlx: Vector Extract Unsigned Word Left
vextubrx: Vector Extract Unsigned Byte Right-Indexed VX-form
vextuhrx: Vector Extract Unsigned Halfword Right-Indexed VX-form
vextuwrx: Vector Extract Unsigned Word Right-Indexed VX-form
Signed-off-by: Avinesh Kumar <avinesku@linux.vnet.ibm.com>
Signed-off-by: Hariharan T.S. <hari@linux.vnet.ibm.com>
[ implement using int128_rshift ]
Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
target/ppc/cpu.h | 2 ++
target/ppc/helper.h | 6 ++++++
target/ppc/int_helper.c | 36 ++++++++++++++++++++++++++++++++++++
target/ppc/translate/vmx-impl.inc.c | 23 +++++++++++++++++++++++
target/ppc/translate/vmx-ops.inc.c | 8 ++++++--
5 files changed, 73 insertions(+), 2 deletions(-)
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index b6782ba..7a6ee3f 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -21,6 +21,7 @@
#define PPC_CPU_H
#include "qemu-common.h"
+#include "qemu/int128.h"
//#define PPC_EMULATE_32BITS_HYPV
@@ -262,6 +263,7 @@ union ppc_avr_t {
#ifdef CONFIG_INT128
__uint128_t u128;
#endif
+ Int128 s128;
};
#if !defined(CONFIG_USER_ONLY)
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index ac8901f..bc39efb 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -366,6 +366,12 @@ DEF_HELPER_3(vpmsumb, void, avr, avr, avr)
DEF_HELPER_3(vpmsumh, void, avr, avr, avr)
DEF_HELPER_3(vpmsumw, void, avr, avr, avr)
DEF_HELPER_3(vpmsumd, void, avr, avr, avr)
+DEF_HELPER_2(vextublx, tl, tl, avr)
+DEF_HELPER_2(vextuhlx, tl, tl, avr)
+DEF_HELPER_2(vextuwlx, tl, tl, avr)
+DEF_HELPER_2(vextubrx, tl, tl, avr)
+DEF_HELPER_2(vextuhrx, tl, tl, avr)
+DEF_HELPER_2(vextuwrx, tl, tl, avr)
DEF_HELPER_2(vsbox, void, avr, avr)
DEF_HELPER_3(vcipher, void, avr, avr, avr)
diff --git a/target/ppc/int_helper.c b/target/ppc/int_helper.c
index 4259876..34dfe02 100644
--- a/target/ppc/int_helper.c
+++ b/target/ppc/int_helper.c
@@ -1805,6 +1805,42 @@ void helper_vlogefp(CPUPPCState *env, ppc_avr_t *r, ppc_avr_t *b)
}
}
+#if defined(HOST_WORDS_BIGENDIAN)
+#define VEXTU_X_DO(name, size, left) \
+ target_ulong glue(helper_, name)(target_ulong a, ppc_avr_t *b) \
+ { \
+ int index; \
+ if (left) { \
+ index = (a & 0xf) * 8; \
+ } else { \
+ index = ((15 - (a & 0xf) + 1) * 8) - size; \
+ } \
+ return int128_getlo(int128_rshift(b->s128, index)) & \
+ MAKE_64BIT_MASK(0, size); \
+ }
+#else
+#define VEXTU_X_DO(name, size, left) \
+ target_ulong glue(helper_, name)(target_ulong a, ppc_avr_t *b) \
+ { \
+ int index; \
+ if (left) { \
+ index = ((15 - (a & 0xf) + 1) * 8) - size; \
+ } else { \
+ index = (a & 0xf) * 8; \
+ } \
+ return int128_getlo(int128_rshift(b->s128, index)) & \
+ MAKE_64BIT_MASK(0, size); \
+ }
+#endif
+
+VEXTU_X_DO(vextublx, 8, 1)
+VEXTU_X_DO(vextuhlx, 16, 1)
+VEXTU_X_DO(vextuwlx, 32, 1)
+VEXTU_X_DO(vextubrx, 8, 0)
+VEXTU_X_DO(vextuhrx, 16, 0)
+VEXTU_X_DO(vextuwrx, 32, 0)
+#undef VEXTU_X_DO
+
/* The specification says that the results are undefined if all of the
* shift counts are not identical. We check to make sure that they are
* to conform to what real hardware appears to do. */
diff --git a/target/ppc/translate/vmx-impl.inc.c b/target/ppc/translate/vmx-impl.inc.c
index b188e60..e8e527f 100644
--- a/target/ppc/translate/vmx-impl.inc.c
+++ b/target/ppc/translate/vmx-impl.inc.c
@@ -340,6 +340,19 @@ static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
} \
}
+#define GEN_VXFORM_HETRO(name, opc2, opc3) \
+static void glue(gen_, name)(DisasContext *ctx) \
+{ \
+ TCGv_ptr rb; \
+ if (unlikely(!ctx->altivec_enabled)) { \
+ gen_exception(ctx, POWERPC_EXCP_VPU); \
+ return; \
+ } \
+ rb = gen_avr_ptr(rB(ctx->opcode)); \
+ gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], rb); \
+ tcg_temp_free_ptr(rb); \
+}
+
GEN_VXFORM(vaddubm, 0, 0);
GEN_VXFORM_DUAL_EXT(vaddubm, PPC_ALTIVEC, PPC_NONE, 0, \
vmul10cuq, PPC_NONE, PPC2_ISA300, 0x0000F800)
@@ -525,6 +538,16 @@ GEN_VXFORM_ENV(vaddfp, 5, 0);
GEN_VXFORM_ENV(vsubfp, 5, 1);
GEN_VXFORM_ENV(vmaxfp, 5, 16);
GEN_VXFORM_ENV(vminfp, 5, 17);
+GEN_VXFORM_HETRO(vextublx, 6, 24)
+GEN_VXFORM_HETRO(vextuhlx, 6, 25)
+GEN_VXFORM_HETRO(vextuwlx, 6, 26)
+GEN_VXFORM_DUAL(vmrgow, PPC_NONE, PPC2_ALTIVEC_207,
+ vextuwlx, PPC_NONE, PPC2_ISA300)
+GEN_VXFORM_HETRO(vextubrx, 6, 28)
+GEN_VXFORM_HETRO(vextuhrx, 6, 29)
+GEN_VXFORM_HETRO(vextuwrx, 6, 30)
+GEN_VXFORM_DUAL(vmrgew, PPC_NONE, PPC2_ALTIVEC_207, \
+ vextuwrx, PPC_NONE, PPC2_ISA300)
#define GEN_VXRFORM1(opname, name, str, opc2, opc3) \
static void glue(gen_, name)(DisasContext *ctx) \
diff --git a/target/ppc/translate/vmx-ops.inc.c b/target/ppc/translate/vmx-ops.inc.c
index 70d7d2b..57dce6e 100644
--- a/target/ppc/translate/vmx-ops.inc.c
+++ b/target/ppc/translate/vmx-ops.inc.c
@@ -91,8 +91,12 @@ GEN_VXFORM(vmrghw, 6, 2),
GEN_VXFORM(vmrglb, 6, 4),
GEN_VXFORM(vmrglh, 6, 5),
GEN_VXFORM(vmrglw, 6, 6),
-GEN_VXFORM_207(vmrgew, 6, 30),
-GEN_VXFORM_207(vmrgow, 6, 26),
+GEN_VXFORM_300(vextublx, 6, 24),
+GEN_VXFORM_300(vextuhlx, 6, 25),
+GEN_VXFORM_DUAL(vmrgow, vextuwlx, 6, 26, PPC_NONE, PPC2_ALTIVEC_207),
+GEN_VXFORM_300(vextubrx, 6, 28),
+GEN_VXFORM_300(vextuhrx, 6, 29),
+GEN_VXFORM_DUAL(vmrgew, vextuwrx, 6, 30, PPC_NONE, PPC2_ALTIVEC_207),
GEN_VXFORM(vmuloub, 4, 0),
GEN_VXFORM(vmulouh, 4, 1),
GEN_VXFORM_DUAL(vmulouw, vmuluwm, 4, 2, PPC_ALTIVEC, PPC_NONE),
--
2.9.3
^ permalink raw reply related [flat|nested] 73+ messages in thread
* [Qemu-devel] [PULL 15/67] pseries: Always use core objects for CPU construction
2017-01-12 2:02 [Qemu-devel] [PULL 00/67] ppc-for-2.9 queue 20170112 David Gibson
` (13 preceding siblings ...)
2017-01-12 2:02 ` [Qemu-devel] [PULL 14/67] target-ppc: add vextu[bhw][lr]x instructions David Gibson
@ 2017-01-12 2:02 ` David Gibson
2017-01-12 2:02 ` [Qemu-devel] [PULL 16/67] pseries: Make cpu_update during CAS unconditional David Gibson
` (53 subsequent siblings)
68 siblings, 0 replies; 73+ messages in thread
From: David Gibson @ 2017-01-12 2:02 UTC (permalink / raw)
To: peter.maydell
Cc: agraf, qemu-ppc, qemu-devel, thuth, lvivier, aik, mdroth, David Gibson
Currently the pseries machine has two paths for constructing CPUs. On
newer machine type versions, which support cpu hotplug, it constructs
cpu core objects, which in turn construct CPU threads. For older machine
versions it individually constructs the CPU threads.
This division is going to make some future changes to the cpu construction
harder, so this patch unifies them. Now cpu core objects are always
created. This requires some updates to allow core objects to be created
without a full complement of threads (since older versions allowed a
number of cpus not a multiple of the threads-per-core). Likewise it needs
some changes to the cpu core hot/cold plug path so as not to choke on the
old machine types without hotplug support.
For good measure, we move the cpu construction to its own subfunction,
spapr_init_cpus().
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Reviewed-by: Greg Kurz <groug@kaod.org>
---
hw/ppc/spapr.c | 125 +++++++++++++++++++++++++++---------------------
hw/ppc/spapr_cpu_core.c | 37 +++++++-------
include/hw/ppc/spapr.h | 1 -
3 files changed, 90 insertions(+), 73 deletions(-)
diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
index 208ef7b..4869fce 100644
--- a/hw/ppc/spapr.c
+++ b/hw/ppc/spapr.c
@@ -1753,11 +1753,80 @@ static void spapr_validate_node_memory(MachineState *machine, Error **errp)
}
}
+static void spapr_init_cpus(sPAPRMachineState *spapr)
+{
+ MachineState *machine = MACHINE(spapr);
+ MachineClass *mc = MACHINE_GET_CLASS(machine);
+ char *type = spapr_get_cpu_core_type(machine->cpu_model);
+ int smt = kvmppc_smt_threads();
+ int spapr_max_cores, spapr_cores;
+ int i;
+
+ if (!type) {
+ error_report("Unable to find sPAPR CPU Core definition");
+ exit(1);
+ }
+
+ if (mc->query_hotpluggable_cpus) {
+ if (smp_cpus % smp_threads) {
+ error_report("smp_cpus (%u) must be multiple of threads (%u)",
+ smp_cpus, smp_threads);
+ exit(1);
+ }
+ if (max_cpus % smp_threads) {
+ error_report("max_cpus (%u) must be multiple of threads (%u)",
+ max_cpus, smp_threads);
+ exit(1);
+ }
+
+ spapr_max_cores = max_cpus / smp_threads;
+ spapr_cores = smp_cpus / smp_threads;
+ } else {
+ if (max_cpus != smp_cpus) {
+ error_report("This machine version does not support CPU hotplug");
+ exit(1);
+ }
+
+ spapr_max_cores = QEMU_ALIGN_UP(smp_cpus, smp_threads) / smp_threads;
+ spapr_cores = spapr_max_cores;
+ }
+
+ spapr->cores = g_new0(Object *, spapr_max_cores);
+ for (i = 0; i < spapr_max_cores; i++) {
+ int core_id = i * smp_threads;
+
+ if (mc->query_hotpluggable_cpus) {
+ sPAPRDRConnector *drc =
+ spapr_dr_connector_new(OBJECT(spapr),
+ SPAPR_DR_CONNECTOR_TYPE_CPU,
+ (core_id / smp_threads) * smt);
+
+ qemu_register_reset(spapr_drc_reset, drc);
+ }
+
+ if (i < spapr_cores) {
+ Object *core = object_new(type);
+ int nr_threads = smp_threads;
+
+ /* Handle the partially filled core for older machine types */
+ if ((i + 1) * smp_threads >= smp_cpus) {
+ nr_threads = smp_cpus - i * smp_threads;
+ }
+
+ object_property_set_int(core, nr_threads, "nr-threads",
+ &error_fatal);
+ object_property_set_int(core, core_id, CPU_CORE_PROP_CORE_ID,
+ &error_fatal);
+ object_property_set_bool(core, true, "realized", &error_fatal);
+ }
+ }
+ g_free(type);
+}
+
/* pSeries LPAR / sPAPR hardware init */
static void ppc_spapr_init(MachineState *machine)
{
sPAPRMachineState *spapr = SPAPR_MACHINE(machine);
- MachineClass *mc = MACHINE_GET_CLASS(machine);
sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine);
const char *kernel_filename = machine->kernel_filename;
const char *initrd_filename = machine->initrd_filename;
@@ -1772,21 +1841,6 @@ static void ppc_spapr_init(MachineState *machine)
long load_limit, fw_size;
char *filename;
int smt = kvmppc_smt_threads();
- int spapr_cores = smp_cpus / smp_threads;
- int spapr_max_cores = max_cpus / smp_threads;
-
- if (mc->query_hotpluggable_cpus) {
- if (smp_cpus % smp_threads) {
- error_report("smp_cpus (%u) must be multiple of threads (%u)",
- smp_cpus, smp_threads);
- exit(1);
- }
- if (max_cpus % smp_threads) {
- error_report("max_cpus (%u) must be multiple of threads (%u)",
- max_cpus, smp_threads);
- exit(1);
- }
- }
msi_nonbroken = true;
@@ -1866,44 +1920,7 @@ static void ppc_spapr_init(MachineState *machine)
ppc_cpu_parse_features(machine->cpu_model);
- if (mc->query_hotpluggable_cpus) {
- char *type = spapr_get_cpu_core_type(machine->cpu_model);
-
- if (type == NULL) {
- error_report("Unable to find sPAPR CPU Core definition");
- exit(1);
- }
-
- spapr->cores = g_new0(Object *, spapr_max_cores);
- for (i = 0; i < spapr_max_cores; i++) {
- int core_id = i * smp_threads;
- sPAPRDRConnector *drc =
- spapr_dr_connector_new(OBJECT(spapr),
- SPAPR_DR_CONNECTOR_TYPE_CPU,
- (core_id / smp_threads) * smt);
-
- qemu_register_reset(spapr_drc_reset, drc);
-
- if (i < spapr_cores) {
- Object *core = object_new(type);
- object_property_set_int(core, smp_threads, "nr-threads",
- &error_fatal);
- object_property_set_int(core, core_id, CPU_CORE_PROP_CORE_ID,
- &error_fatal);
- object_property_set_bool(core, true, "realized", &error_fatal);
- }
- }
- g_free(type);
- } else {
- for (i = 0; i < smp_cpus; i++) {
- PowerPCCPU *cpu = cpu_ppc_init(machine->cpu_model);
- if (cpu == NULL) {
- error_report("Unable to find PowerPC CPU definition");
- exit(1);
- }
- spapr_cpu_init(spapr, cpu, &error_fatal);
- }
- }
+ spapr_init_cpus(spapr);
if (kvm_enabled()) {
/* Enable H_LOGICAL_CI_* so SLOF can talk to in-kernel devices */
diff --git a/hw/ppc/spapr_cpu_core.c b/hw/ppc/spapr_cpu_core.c
index c18632b..f532689 100644
--- a/hw/ppc/spapr_cpu_core.c
+++ b/hw/ppc/spapr_cpu_core.c
@@ -46,7 +46,8 @@ static void spapr_cpu_destroy(PowerPCCPU *cpu)
qemu_unregister_reset(spapr_cpu_reset, cpu);
}
-void spapr_cpu_init(sPAPRMachineState *spapr, PowerPCCPU *cpu, Error **errp)
+static void spapr_cpu_init(sPAPRMachineState *spapr, PowerPCCPU *cpu,
+ Error **errp)
{
CPUPPCState *env = &cpu->env;
CPUState *cs = CPU(cpu);
@@ -166,11 +167,11 @@ void spapr_core_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
Error **errp)
{
sPAPRMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev));
+ MachineClass *mc = MACHINE_GET_CLASS(spapr);
sPAPRCPUCore *core = SPAPR_CPU_CORE(OBJECT(dev));
CPUCore *cc = CPU_CORE(dev);
CPUState *cs = CPU(core->threads);
sPAPRDRConnector *drc;
- sPAPRDRConnectorClass *drck;
Error *local_err = NULL;
void *fdt = NULL;
int fdt_offset = 0;
@@ -180,7 +181,7 @@ void spapr_core_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_CPU, index * smt);
spapr->cores[index] = OBJECT(dev);
- g_assert(drc);
+ g_assert(drc || !mc->query_hotpluggable_cpus);
/*
* Setup CPU DT entries only for hotplugged CPUs. For boot time or
@@ -190,13 +191,15 @@ void spapr_core_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
fdt = spapr_populate_hotplug_cpu_dt(cs, &fdt_offset, spapr);
}
- drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc);
- drck->attach(drc, dev, fdt, fdt_offset, !dev->hotplugged, &local_err);
- if (local_err) {
- g_free(fdt);
- spapr->cores[index] = NULL;
- error_propagate(errp, local_err);
- return;
+ if (drc) {
+ sPAPRDRConnectorClass *drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc);
+ drck->attach(drc, dev, fdt, fdt_offset, !dev->hotplugged, &local_err);
+ if (local_err) {
+ g_free(fdt);
+ spapr->cores[index] = NULL;
+ error_propagate(errp, local_err);
+ return;
+ }
}
if (dev->hotplugged) {
@@ -209,8 +212,11 @@ void spapr_core_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
/*
* Set the right DRC states for cold plugged CPU.
*/
- drck->set_allocation_state(drc, SPAPR_DR_ALLOCATION_STATE_USABLE);
- drck->set_isolation_state(drc, SPAPR_DR_ISOLATION_STATE_UNISOLATED);
+ if (drc) {
+ sPAPRDRConnectorClass *drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc);
+ drck->set_allocation_state(drc, SPAPR_DR_ALLOCATION_STATE_USABLE);
+ drck->set_isolation_state(drc, SPAPR_DR_ISOLATION_STATE_UNISOLATED);
+ }
}
}
@@ -227,7 +233,7 @@ void spapr_core_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
char *base_core_type = spapr_get_cpu_core_type(machine->cpu_model);
const char *type = object_get_typename(OBJECT(dev));
- if (!mc->query_hotpluggable_cpus) {
+ if (dev->hotplugged && !mc->query_hotpluggable_cpus) {
error_setg(&local_err, "CPU hotplug not supported for this machine");
goto out;
}
@@ -237,11 +243,6 @@ void spapr_core_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
goto out;
}
- if (cc->nr_threads != smp_threads) {
- error_setg(&local_err, "threads must be %d", smp_threads);
- goto out;
- }
-
if (cc->core_id % smp_threads) {
error_setg(&local_err, "invalid core id %d", cc->core_id);
goto out;
diff --git a/include/hw/ppc/spapr.h b/include/hw/ppc/spapr.h
index bd5bcf7..f8d444d 100644
--- a/include/hw/ppc/spapr.h
+++ b/include/hw/ppc/spapr.h
@@ -614,7 +614,6 @@ void spapr_hotplug_req_add_by_count_indexed(sPAPRDRConnectorType drc_type,
uint32_t count, uint32_t index);
void spapr_hotplug_req_remove_by_count_indexed(sPAPRDRConnectorType drc_type,
uint32_t count, uint32_t index);
-void spapr_cpu_init(sPAPRMachineState *spapr, PowerPCCPU *cpu, Error **errp);
void *spapr_populate_hotplug_cpu_dt(CPUState *cs, int *fdt_offset,
sPAPRMachineState *spapr);
--
2.9.3
^ permalink raw reply related [flat|nested] 73+ messages in thread
* [Qemu-devel] [PULL 16/67] pseries: Make cpu_update during CAS unconditional
2017-01-12 2:02 [Qemu-devel] [PULL 00/67] ppc-for-2.9 queue 20170112 David Gibson
` (14 preceding siblings ...)
2017-01-12 2:02 ` [Qemu-devel] [PULL 15/67] pseries: Always use core objects for CPU construction David Gibson
@ 2017-01-12 2:02 ` David Gibson
2017-01-12 2:02 ` [Qemu-devel] [PULL 17/67] ppc: Clean up and QOMify hypercall emulation David Gibson
` (52 subsequent siblings)
68 siblings, 0 replies; 73+ messages in thread
From: David Gibson @ 2017-01-12 2:02 UTC (permalink / raw)
To: peter.maydell
Cc: agraf, qemu-ppc, qemu-devel, thuth, lvivier, aik, mdroth, David Gibson
spapr_h_cas_compose_response() includes a cpu_update parameter which
controls whether it includes updated information on the CPUs in the device
tree fragment returned from the ibm,client-architecture-support (CAS) call.
Providing the updated information is essential when CAS has negotiated
compatibility options which require different cpu information to be
presented to the guest. However, it should be safe to provide in other
cases (it will just override the existing data in the device tree with
identical data). This simplifies the code by removing the parameter and
always providing the cpu update information.
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Reviewed-by: Alexey Kardashevskiy <aik@ozlabs.ru>
---
hw/ppc/spapr.c | 5 +----
hw/ppc/spapr_hcall.c | 8 ++------
include/hw/ppc/spapr.h | 1 -
3 files changed, 3 insertions(+), 11 deletions(-)
diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
index 4869fce..52970db 100644
--- a/hw/ppc/spapr.c
+++ b/hw/ppc/spapr.c
@@ -685,7 +685,6 @@ out:
int spapr_h_cas_compose_response(sPAPRMachineState *spapr,
target_ulong addr, target_ulong size,
- bool cpu_update,
sPAPROptionVector *ov5_updates)
{
void *fdt, *fdt_skel;
@@ -704,9 +703,7 @@ int spapr_h_cas_compose_response(sPAPRMachineState *spapr,
g_free(fdt_skel);
/* Fixup cpu nodes */
- if (cpu_update) {
- _FDT((spapr_fixup_cpu_dt(fdt, spapr)));
- }
+ _FDT((spapr_fixup_cpu_dt(fdt, spapr)));
if (spapr_dt_cas_updates(spapr, fdt, ov5_updates)) {
return -1;
diff --git a/hw/ppc/spapr_hcall.c b/hw/ppc/spapr_hcall.c
index 9a9bedf..3f08b8a 100644
--- a/hw/ppc/spapr_hcall.c
+++ b/hw/ppc/spapr_hcall.c
@@ -945,7 +945,7 @@ static target_ulong h_client_architecture_support(PowerPCCPU *cpu_,
target_ulong ov_table;
PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu_);
CPUState *cs;
- bool cpu_match = false, cpu_update = true;
+ bool cpu_match = false;
unsigned old_cpu_version = cpu_->cpu_version;
unsigned compat_lvl = 0, cpu_version = 0;
unsigned max_lvl = get_compat_level(cpu_->max_compat);
@@ -999,10 +999,6 @@ static target_ulong h_client_architecture_support(PowerPCCPU *cpu_,
}
}
- if (!cpu_version) {
- cpu_update = false;
- }
-
/* For the future use: here @ov_table points to the first option vector */
ov_table = list;
@@ -1028,7 +1024,7 @@ static target_ulong h_client_architecture_support(PowerPCCPU *cpu_,
if (!spapr->cas_reboot) {
spapr->cas_reboot =
- (spapr_h_cas_compose_response(spapr, args[1], args[2], cpu_update,
+ (spapr_h_cas_compose_response(spapr, args[1], args[2],
ov5_updates) != 0);
}
spapr_ovec_cleanup(ov5_updates);
diff --git a/include/hw/ppc/spapr.h b/include/hw/ppc/spapr.h
index f8d444d..04d2821 100644
--- a/include/hw/ppc/spapr.h
+++ b/include/hw/ppc/spapr.h
@@ -589,7 +589,6 @@ void spapr_events_init(sPAPRMachineState *sm);
void spapr_dt_events(sPAPRMachineState *sm, void *fdt);
int spapr_h_cas_compose_response(sPAPRMachineState *sm,
target_ulong addr, target_ulong size,
- bool cpu_update,
sPAPROptionVector *ov5_updates);
sPAPRTCETable *spapr_tce_new_table(DeviceState *owner, uint32_t liobn);
void spapr_tce_table_enable(sPAPRTCETable *tcet,
--
2.9.3
^ permalink raw reply related [flat|nested] 73+ messages in thread
* [Qemu-devel] [PULL 17/67] ppc: Clean up and QOMify hypercall emulation
2017-01-12 2:02 [Qemu-devel] [PULL 00/67] ppc-for-2.9 queue 20170112 David Gibson
` (15 preceding siblings ...)
2017-01-12 2:02 ` [Qemu-devel] [PULL 16/67] pseries: Make cpu_update during CAS unconditional David Gibson
@ 2017-01-12 2:02 ` David Gibson
2017-01-12 2:02 ` [Qemu-devel] [PULL 18/67] ppc: Rename cpu_version to compat_pvr David Gibson
` (51 subsequent siblings)
68 siblings, 0 replies; 73+ messages in thread
From: David Gibson @ 2017-01-12 2:02 UTC (permalink / raw)
To: peter.maydell
Cc: agraf, qemu-ppc, qemu-devel, thuth, lvivier, aik, mdroth, David Gibson
The pseries machine type is a bit unusual in that it runs a paravirtualized
guest. The guest expects to interact with a hypervisor, and qemu
emulates the functions of that hypervisor directly, rather than executing
hypervisor code within the emulated system.
To implement this in TCG, we need to intercept hypercall instructions and
direct them to the machine's hypercall handlers, rather than attempting to
perform a privilege change within TCG. This is controlled by a global
hook - cpu_ppc_hypercall.
This cleanup makes the handling a little cleaner and more extensible than
a single global variable. Instead, each CPU to have hypercalls intercepted
has a pointer set to a QOM object implementing a new virtual hypervisor
interface. A method in that interface is called by TCG when it sees a
hypercall instruction. It's possible we may want to add other methods in
future.
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Reviewed-by: Alexey Kardashevskiy <aik@ozlabs.ru>
---
hw/ppc/spapr.c | 8 +++++---
hw/ppc/spapr_cpu_core.c | 1 +
target/ppc/cpu.h | 26 ++++++++++++++++++++++++--
target/ppc/excp_helper.c | 11 ++++-------
target/ppc/translate_init.c | 12 ++++++++++++
5 files changed, 46 insertions(+), 12 deletions(-)
diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
index 52970db..b3bbad0 100644
--- a/hw/ppc/spapr.c
+++ b/hw/ppc/spapr.c
@@ -1005,7 +1005,8 @@ static uint64_t translate_kernel_address(void *opaque, uint64_t addr)
return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR;
}
-static void emulate_spapr_hypercall(PowerPCCPU *cpu)
+static void emulate_spapr_hypercall(PPCVirtualHypervisor *vhyp,
+ PowerPCCPU *cpu)
{
CPUPPCState *env = &cpu->env;
@@ -1843,8 +1844,6 @@ static void ppc_spapr_init(MachineState *machine)
QLIST_INIT(&spapr->phbs);
- cpu_ppc_hypercall = emulate_spapr_hypercall;
-
/* Allocate RMA if necessary */
rma_alloc_size = kvmppc_alloc_rma(&rma);
@@ -2680,6 +2679,7 @@ static void spapr_machine_class_init(ObjectClass *oc, void *data)
FWPathProviderClass *fwc = FW_PATH_PROVIDER_CLASS(oc);
NMIClass *nc = NMI_CLASS(oc);
HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc);
+ PPCVirtualHypervisorClass *vhc = PPC_VIRTUAL_HYPERVISOR_CLASS(oc);
mc->desc = "pSeries Logical Partition (PAPR compliant)";
@@ -2711,6 +2711,7 @@ static void spapr_machine_class_init(ObjectClass *oc, void *data)
fwc->get_dev_path = spapr_get_fw_dev_path;
nc->nmi_monitor_handler = spapr_nmi;
smc->phb_placement = spapr_phb_placement;
+ vhc->hypercall = emulate_spapr_hypercall;
}
static const TypeInfo spapr_machine_info = {
@@ -2726,6 +2727,7 @@ static const TypeInfo spapr_machine_info = {
{ TYPE_FW_PATH_PROVIDER },
{ TYPE_NMI },
{ TYPE_HOTPLUG_HANDLER },
+ { TYPE_PPC_VIRTUAL_HYPERVISOR },
{ }
},
};
diff --git a/hw/ppc/spapr_cpu_core.c b/hw/ppc/spapr_cpu_core.c
index f532689..9dddaeb 100644
--- a/hw/ppc/spapr_cpu_core.c
+++ b/hw/ppc/spapr_cpu_core.c
@@ -57,6 +57,7 @@ static void spapr_cpu_init(sPAPRMachineState *spapr, PowerPCCPU *cpu,
cpu_ppc_tb_init(env, SPAPR_TIMEBASE_FREQ);
/* Enable PAPR mode in TCG or KVM */
+ cpu_ppc_set_vhyp(cpu, PPC_VIRTUAL_HYPERVISOR(spapr));
cpu_ppc_set_papr(cpu);
if (cpu->max_compat) {
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index 7a6ee3f..4fb4c20 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -1150,6 +1150,9 @@ do { \
env->wdt_period[3] = (d_); \
} while (0)
+typedef struct PPCVirtualHypervisor PPCVirtualHypervisor;
+typedef struct PPCVirtualHypervisorClass PPCVirtualHypervisorClass;
+
/**
* PowerPCCPU:
* @env: #CPUPPCState
@@ -1168,6 +1171,7 @@ struct PowerPCCPU {
int cpu_dt_id;
uint32_t max_compat;
uint32_t cpu_version;
+ PPCVirtualHypervisor *vhyp;
/* Fields related to migration compatibility hacks */
bool pre_2_8_migration;
@@ -1189,6 +1193,25 @@ static inline PowerPCCPU *ppc_env_get_cpu(CPUPPCState *env)
PowerPCCPUClass *ppc_cpu_class_by_pvr(uint32_t pvr);
PowerPCCPUClass *ppc_cpu_class_by_pvr_mask(uint32_t pvr);
+struct PPCVirtualHypervisor {
+ Object parent;
+};
+
+struct PPCVirtualHypervisorClass {
+ InterfaceClass parent;
+ void (*hypercall)(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu);
+};
+
+#define TYPE_PPC_VIRTUAL_HYPERVISOR "ppc-virtual-hypervisor"
+#define PPC_VIRTUAL_HYPERVISOR(obj) \
+ OBJECT_CHECK(PPCVirtualHypervisor, (obj), TYPE_PPC_VIRTUAL_HYPERVISOR)
+#define PPC_VIRTUAL_HYPERVISOR_CLASS(klass) \
+ OBJECT_CLASS_CHECK(PPCVirtualHypervisorClass, (klass), \
+ TYPE_PPC_VIRTUAL_HYPERVISOR)
+#define PPC_VIRTUAL_HYPERVISOR_GET_CLASS(obj) \
+ OBJECT_GET_CLASS(PPCVirtualHypervisorClass, (obj), \
+ TYPE_PPC_VIRTUAL_HYPERVISOR)
+
void ppc_cpu_do_interrupt(CPUState *cpu);
bool ppc_cpu_exec_interrupt(CPUState *cpu, int int_req);
void ppc_cpu_dump_state(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf,
@@ -1261,6 +1284,7 @@ void store_booke_tcr (CPUPPCState *env, target_ulong val);
void store_booke_tsr (CPUPPCState *env, target_ulong val);
void ppc_tlb_invalidate_all (CPUPPCState *env);
void ppc_tlb_invalidate_one (CPUPPCState *env, target_ulong addr);
+void cpu_ppc_set_vhyp(PowerPCCPU *cpu, PPCVirtualHypervisor *vhyp);
void cpu_ppc_set_papr(PowerPCCPU *cpu);
#endif
#endif
@@ -2435,8 +2459,6 @@ static inline bool lsw_reg_in_range(int start, int nregs, int rx)
(start + nregs > 32 && (rx >= start || rx < start + nregs - 32));
}
-extern void (*cpu_ppc_hypercall)(PowerPCCPU *);
-
void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUPPCState *env);
/**
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index 93369d4..f4ee7aa 100644
--- a/target/ppc/excp_helper.c
+++ b/target/ppc/excp_helper.c
@@ -35,11 +35,6 @@
#endif
/*****************************************************************************/
-/* PowerPC Hypercall emulation */
-
-void (*cpu_ppc_hypercall)(PowerPCCPU *);
-
-/*****************************************************************************/
/* Exception processing */
#if defined(CONFIG_USER_ONLY)
void ppc_cpu_do_interrupt(CPUState *cs)
@@ -318,8 +313,10 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp)
env->nip += 4;
/* "PAPR mode" built-in hypercall emulation */
- if ((lev == 1) && cpu_ppc_hypercall) {
- cpu_ppc_hypercall(cpu);
+ if ((lev == 1) && cpu->vhyp) {
+ PPCVirtualHypervisorClass *vhc =
+ PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp);
+ vhc->hypercall(cpu->vhyp, cpu);
return;
}
if (lev == 1) {
diff --git a/target/ppc/translate_init.c b/target/ppc/translate_init.c
index 626e031..82ed83b 100644
--- a/target/ppc/translate_init.c
+++ b/target/ppc/translate_init.c
@@ -8857,6 +8857,11 @@ POWERPC_FAMILY(POWER9)(ObjectClass *oc, void *data)
#if !defined(CONFIG_USER_ONLY)
+void cpu_ppc_set_vhyp(PowerPCCPU *cpu, PPCVirtualHypervisor *vhyp)
+{
+ cpu->vhyp = vhyp;
+}
+
void cpu_ppc_set_papr(PowerPCCPU *cpu)
{
CPUPPCState *env = &cpu->env;
@@ -10593,9 +10598,16 @@ static const TypeInfo ppc_cpu_type_info = {
.class_init = ppc_cpu_class_init,
};
+static const TypeInfo ppc_vhyp_type_info = {
+ .name = TYPE_PPC_VIRTUAL_HYPERVISOR,
+ .parent = TYPE_INTERFACE,
+ .class_size = sizeof(PPCVirtualHypervisorClass),
+};
+
static void ppc_cpu_register_types(void)
{
type_register_static(&ppc_cpu_type_info);
+ type_register_static(&ppc_vhyp_type_info);
}
type_init(ppc_cpu_register_types)
--
2.9.3
^ permalink raw reply related [flat|nested] 73+ messages in thread
* [Qemu-devel] [PULL 18/67] ppc: Rename cpu_version to compat_pvr
2017-01-12 2:02 [Qemu-devel] [PULL 00/67] ppc-for-2.9 queue 20170112 David Gibson
` (16 preceding siblings ...)
2017-01-12 2:02 ` [Qemu-devel] [PULL 17/67] ppc: Clean up and QOMify hypercall emulation David Gibson
@ 2017-01-12 2:02 ` David Gibson
2017-01-12 2:02 ` [Qemu-devel] [PULL 19/67] ppc/spapr: implement H_SIGNAL_SYS_RESET David Gibson
` (50 subsequent siblings)
68 siblings, 0 replies; 73+ messages in thread
From: David Gibson @ 2017-01-12 2:02 UTC (permalink / raw)
To: peter.maydell
Cc: agraf, qemu-ppc, qemu-devel, thuth, lvivier, aik, mdroth, David Gibson
The 'cpu_version' field in PowerPCCPU is badly named. It's named after the
'cpu-version' device tree property where it is advertised, but that meaning
may not be obvious in most places it appears.
Worse, it doesn't even really correspond to that device tree property. The
property contains either the processor's PVR, or, if the CPU is running in
a compatibility mode, a special "logical PVR" representing which mode.
Rename the cpu_version field, and a number of related variables to
compat_pvr to make this clearer.
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Reviewed-by: Alexey Kardashevskiy <aik@ozlabs.ru>
Reviewed-by: Thomas Huth <thuth@redhat.com>
---
hw/ppc/spapr.c | 4 ++--
hw/ppc/spapr_hcall.c | 30 +++++++++++++++---------------
target/ppc/cpu.h | 6 +++---
target/ppc/kvm.c | 4 ++--
target/ppc/kvm_ppc.h | 4 ++--
target/ppc/translate_init.c | 10 +++++-----
6 files changed, 29 insertions(+), 29 deletions(-)
diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
index b3bbad0..f921be3 100644
--- a/hw/ppc/spapr.c
+++ b/hw/ppc/spapr.c
@@ -148,8 +148,8 @@ static int spapr_fixup_cpu_smt_dt(void *fdt, int offset, PowerPCCPU *cpu,
uint32_t gservers_prop[smt_threads * 2];
int index = ppc_get_vcpu_dt_id(cpu);
- if (cpu->cpu_version) {
- ret = fdt_setprop_cell(fdt, offset, "cpu-version", cpu->cpu_version);
+ if (cpu->compat_pvr) {
+ ret = fdt_setprop_cell(fdt, offset, "cpu-version", cpu->compat_pvr);
if (ret < 0) {
return ret;
}
diff --git a/hw/ppc/spapr_hcall.c b/hw/ppc/spapr_hcall.c
index 3f08b8a..35499ae 100644
--- a/hw/ppc/spapr_hcall.c
+++ b/hw/ppc/spapr_hcall.c
@@ -882,7 +882,7 @@ static target_ulong h_set_mode(PowerPCCPU *cpu, sPAPRMachineState *spapr,
}
typedef struct {
- uint32_t cpu_version;
+ uint32_t compat_pvr;
Error *err;
} SetCompatState;
@@ -892,7 +892,7 @@ static void do_set_compat(CPUState *cs, run_on_cpu_data arg)
SetCompatState *s = arg.host_ptr;
cpu_synchronize_state(cs);
- ppc_set_compat(cpu, s->cpu_version, &s->err);
+ ppc_set_compat(cpu, s->compat_pvr, &s->err);
}
#define get_compat_level(cpuver) ( \
@@ -903,7 +903,7 @@ static void do_set_compat(CPUState *cs, run_on_cpu_data arg)
static void cas_handle_compat_cpu(PowerPCCPUClass *pcc, uint32_t pvr,
unsigned max_lvl, unsigned *compat_lvl,
- unsigned *cpu_version)
+ unsigned *compat_pvr)
{
unsigned lvl = get_compat_level(pvr);
bool is205, is206, is207;
@@ -926,12 +926,12 @@ static void cas_handle_compat_cpu(PowerPCCPUClass *pcc, uint32_t pvr,
/* User did not set the level, choose the highest */
if (*compat_lvl <= lvl) {
*compat_lvl = lvl;
- *cpu_version = pvr;
+ *compat_pvr = pvr;
}
} else if (max_lvl >= lvl) {
/* User chose the level, don't set higher than this */
*compat_lvl = lvl;
- *cpu_version = pvr;
+ *compat_pvr = pvr;
}
}
}
@@ -946,8 +946,8 @@ static target_ulong h_client_architecture_support(PowerPCCPU *cpu_,
PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu_);
CPUState *cs;
bool cpu_match = false;
- unsigned old_cpu_version = cpu_->cpu_version;
- unsigned compat_lvl = 0, cpu_version = 0;
+ unsigned old_compat_pvr = cpu_->compat_pvr;
+ unsigned compat_lvl = 0, compat_pvr = 0;
unsigned max_lvl = get_compat_level(cpu_->max_compat);
int counter;
sPAPROptionVector *ov5_guest, *ov5_cas_old, *ov5_updates;
@@ -965,12 +965,12 @@ static target_ulong h_client_architecture_support(PowerPCCPU *cpu_,
if (!max_lvl &&
((cpu_->env.spr[SPR_PVR] & pvr_mask) == (pvr & pvr_mask))) {
cpu_match = true;
- cpu_version = 0;
- } else if (pvr == cpu_->cpu_version) {
+ compat_pvr = 0;
+ } else if (pvr == cpu_->compat_pvr) {
cpu_match = true;
- cpu_version = cpu_->cpu_version;
+ compat_pvr = cpu_->compat_pvr;
} else if (!cpu_match) {
- cas_handle_compat_cpu(pcc, pvr, max_lvl, &compat_lvl, &cpu_version);
+ cas_handle_compat_cpu(pcc, pvr, max_lvl, &compat_lvl, &compat_pvr);
}
/* Terminator record */
if (~pvr_mask & pvr) {
@@ -979,14 +979,14 @@ static target_ulong h_client_architecture_support(PowerPCCPU *cpu_,
}
/* Parsing finished */
- trace_spapr_cas_pvr(cpu_->cpu_version, cpu_match,
- cpu_version, pcc->pcr_mask);
+ trace_spapr_cas_pvr(cpu_->compat_pvr, cpu_match,
+ compat_pvr, pcc->pcr_mask);
/* Update CPUs */
- if (old_cpu_version != cpu_version) {
+ if (old_compat_pvr != compat_pvr) {
CPU_FOREACH(cs) {
SetCompatState s = {
- .cpu_version = cpu_version,
+ .compat_pvr = compat_pvr,
.err = NULL,
};
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index 4fb4c20..b62f775 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -1158,7 +1158,7 @@ typedef struct PPCVirtualHypervisorClass PPCVirtualHypervisorClass;
* @env: #CPUPPCState
* @cpu_dt_id: CPU index used in the device tree. KVM uses this index too
* @max_compat: Maximal supported logical PVR from the command line
- * @cpu_version: Current logical PVR, zero if in "raw" mode
+ * @compat_pvr: Current logical PVR, zero if in "raw" mode
*
* A PowerPC CPU.
*/
@@ -1170,7 +1170,7 @@ struct PowerPCCPU {
CPUPPCState env;
int cpu_dt_id;
uint32_t max_compat;
- uint32_t cpu_version;
+ uint32_t compat_pvr;
PPCVirtualHypervisor *vhyp;
/* Fields related to migration compatibility hacks */
@@ -1252,7 +1252,7 @@ void ppc_store_msr (CPUPPCState *env, target_ulong value);
void ppc_cpu_list (FILE *f, fprintf_function cpu_fprintf);
int ppc_get_compat_smt_threads(PowerPCCPU *cpu);
#if defined(TARGET_PPC64)
-void ppc_set_compat(PowerPCCPU *cpu, uint32_t cpu_version, Error **errp);
+void ppc_set_compat(PowerPCCPU *cpu, uint32_t compat_pvr, Error **errp);
#endif
/* Time-base and decrementer management */
diff --git a/target/ppc/kvm.c b/target/ppc/kvm.c
index 9c4834c..15e12f3 100644
--- a/target/ppc/kvm.c
+++ b/target/ppc/kvm.c
@@ -2103,9 +2103,9 @@ void kvmppc_set_papr(PowerPCCPU *cpu)
cap_papr = 1;
}
-int kvmppc_set_compat(PowerPCCPU *cpu, uint32_t cpu_version)
+int kvmppc_set_compat(PowerPCCPU *cpu, uint32_t compat_pvr)
{
- return kvm_set_one_reg(CPU(cpu), KVM_REG_PPC_ARCH_COMPAT, &cpu_version);
+ return kvm_set_one_reg(CPU(cpu), KVM_REG_PPC_ARCH_COMPAT, &compat_pvr);
}
void kvmppc_set_mpic_proxy(PowerPCCPU *cpu, int mpic_proxy)
diff --git a/target/ppc/kvm_ppc.h b/target/ppc/kvm_ppc.h
index bd1d78b..841a29b 100644
--- a/target/ppc/kvm_ppc.h
+++ b/target/ppc/kvm_ppc.h
@@ -26,7 +26,7 @@ void kvmppc_enable_logical_ci_hcalls(void);
void kvmppc_enable_set_mode_hcall(void);
void kvmppc_enable_clear_ref_mod_hcalls(void);
void kvmppc_set_papr(PowerPCCPU *cpu);
-int kvmppc_set_compat(PowerPCCPU *cpu, uint32_t cpu_version);
+int kvmppc_set_compat(PowerPCCPU *cpu, uint32_t compat_pvr);
void kvmppc_set_mpic_proxy(PowerPCCPU *cpu, int mpic_proxy);
int kvmppc_smt_threads(void);
int kvmppc_clear_tsr_bits(PowerPCCPU *cpu, uint32_t tsr_bits);
@@ -123,7 +123,7 @@ static inline void kvmppc_set_papr(PowerPCCPU *cpu)
{
}
-static inline int kvmppc_set_compat(PowerPCCPU *cpu, uint32_t cpu_version)
+static inline int kvmppc_set_compat(PowerPCCPU *cpu, uint32_t compat_pvr)
{
return 0;
}
diff --git a/target/ppc/translate_init.c b/target/ppc/translate_init.c
index 82ed83b..60552c1 100644
--- a/target/ppc/translate_init.c
+++ b/target/ppc/translate_init.c
@@ -9957,7 +9957,7 @@ int ppc_get_compat_smt_threads(PowerPCCPU *cpu)
CPUState *cs = CPU(cpu);
int ret = MIN(cs->nr_threads, kvmppc_smt_threads());
- switch (cpu->cpu_version) {
+ switch (cpu->compat_pvr) {
case CPU_POWERPC_LOGICAL_2_05:
ret = MIN(ret, 2);
break;
@@ -9973,15 +9973,15 @@ int ppc_get_compat_smt_threads(PowerPCCPU *cpu)
}
#ifdef TARGET_PPC64
-void ppc_set_compat(PowerPCCPU *cpu, uint32_t cpu_version, Error **errp)
+void ppc_set_compat(PowerPCCPU *cpu, uint32_t compat_pvr, Error **errp)
{
int ret = 0;
CPUPPCState *env = &cpu->env;
PowerPCCPUClass *host_pcc;
- cpu->cpu_version = cpu_version;
+ cpu->compat_pvr = compat_pvr;
- switch (cpu_version) {
+ switch (compat_pvr) {
case CPU_POWERPC_LOGICAL_2_05:
env->spr[SPR_PCR] = PCR_TM_DIS | PCR_VSX_DIS | PCR_COMPAT_2_07 |
PCR_COMPAT_2_06 | PCR_COMPAT_2_05;
@@ -10004,7 +10004,7 @@ void ppc_set_compat(PowerPCCPU *cpu, uint32_t cpu_version, Error **errp)
}
if (kvm_enabled()) {
- ret = kvmppc_set_compat(cpu, cpu->cpu_version);
+ ret = kvmppc_set_compat(cpu, cpu->compat_pvr);
if (ret < 0) {
error_setg_errno(errp, -ret,
"Unable to set CPU compatibility mode in KVM");
--
2.9.3
^ permalink raw reply related [flat|nested] 73+ messages in thread
* [Qemu-devel] [PULL 19/67] ppc/spapr: implement H_SIGNAL_SYS_RESET
2017-01-12 2:02 [Qemu-devel] [PULL 00/67] ppc-for-2.9 queue 20170112 David Gibson
` (17 preceding siblings ...)
2017-01-12 2:02 ` [Qemu-devel] [PULL 18/67] ppc: Rename cpu_version to compat_pvr David Gibson
@ 2017-01-12 2:02 ` David Gibson
2017-01-12 2:02 ` [Qemu-devel] [PULL 20/67] target-ppc: move ppc_vsr_t to common header David Gibson
` (49 subsequent siblings)
68 siblings, 0 replies; 73+ messages in thread
From: David Gibson @ 2017-01-12 2:02 UTC (permalink / raw)
To: peter.maydell
Cc: agraf, qemu-ppc, qemu-devel, thuth, lvivier, aik, mdroth,
Nicholas Piggin, David Gibson
From: Nicholas Piggin <npiggin@gmail.com>
The H_SIGNAL_SYS_RESET hcall allows a guest CPU to raise a system reset
exception on CPUs within the same guest -- all CPUs, all-but-self, or a
specific CPU (including self).
This has not made its way to a PAPR release yet, but we have an hcall
number assigned.
H_SIGNAL_SYS_RESET = 0x380
Syntax:
hcall(uint64 H_SIGNAL_SYS_RESET, int64 target);
Generate a system reset NMI on the threads indicated by target.
Values for target:
-1 = target all online threads including the caller
-2 = target all online threads except for the caller
All other negative values: reserved
Positive values: The thread to be targeted, obtained from the value
of the "ibm,ppc-interrupt-server#s" property of the CPU in the OF
device tree.
Semantics:
- Invalid target: return H_Parameter.
- Otherwise: Generate a system reset NMI on target thread(s),
return H_Success.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/ppc/spapr.c | 4 ++--
hw/ppc/spapr_hcall.c | 41 +++++++++++++++++++++++++++++++++++++++++
include/hw/ppc/spapr.h | 5 ++++-
3 files changed, 47 insertions(+), 3 deletions(-)
diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
index f921be3..cfadc46 100644
--- a/hw/ppc/spapr.c
+++ b/hw/ppc/spapr.c
@@ -2265,7 +2265,7 @@ static void spapr_machine_finalizefn(Object *obj)
g_free(spapr->kvm_type);
}
-static void ppc_cpu_do_nmi_on_cpu(CPUState *cs, run_on_cpu_data arg)
+void spapr_do_system_reset_on_cpu(CPUState *cs, run_on_cpu_data arg)
{
cpu_synchronize_state(cs);
ppc_cpu_do_system_reset(cs);
@@ -2276,7 +2276,7 @@ static void spapr_nmi(NMIState *n, int cpu_index, Error **errp)
CPUState *cs;
CPU_FOREACH(cs) {
- async_run_on_cpu(cs, ppc_cpu_do_nmi_on_cpu, RUN_ON_CPU_NULL);
+ async_run_on_cpu(cs, spapr_do_system_reset_on_cpu, RUN_ON_CPU_NULL);
}
}
diff --git a/hw/ppc/spapr_hcall.c b/hw/ppc/spapr_hcall.c
index 35499ae..fd9f1d4 100644
--- a/hw/ppc/spapr_hcall.c
+++ b/hw/ppc/spapr_hcall.c
@@ -881,6 +881,46 @@ static target_ulong h_set_mode(PowerPCCPU *cpu, sPAPRMachineState *spapr,
return ret;
}
+#define H_SIGNAL_SYS_RESET_ALL -1
+#define H_SIGNAL_SYS_RESET_ALLBUTSELF -2
+
+static target_ulong h_signal_sys_reset(PowerPCCPU *cpu,
+ sPAPRMachineState *spapr,
+ target_ulong opcode, target_ulong *args)
+{
+ target_long target = args[0];
+ CPUState *cs;
+
+ if (target < 0) {
+ /* Broadcast */
+ if (target < H_SIGNAL_SYS_RESET_ALLBUTSELF) {
+ return H_PARAMETER;
+ }
+
+ CPU_FOREACH(cs) {
+ PowerPCCPU *c = POWERPC_CPU(cs);
+
+ if (target == H_SIGNAL_SYS_RESET_ALLBUTSELF) {
+ if (c == cpu) {
+ continue;
+ }
+ }
+ run_on_cpu(cs, spapr_do_system_reset_on_cpu, RUN_ON_CPU_NULL);
+ }
+ return H_SUCCESS;
+
+ } else {
+ /* Unicast */
+ CPU_FOREACH(cs) {
+ if (cpu->cpu_dt_id == target) {
+ run_on_cpu(cs, spapr_do_system_reset_on_cpu, RUN_ON_CPU_NULL);
+ return H_SUCCESS;
+ }
+ }
+ return H_PARAMETER;
+ }
+}
+
typedef struct {
uint32_t compat_pvr;
Error *err;
@@ -1097,6 +1137,7 @@ static void hypercall_register_types(void)
/* hcall-splpar */
spapr_register_hypercall(H_REGISTER_VPA, h_register_vpa);
spapr_register_hypercall(H_CEDE, h_cede);
+ spapr_register_hypercall(H_SIGNAL_SYS_RESET, h_signal_sys_reset);
/* processor register resource access h-calls */
spapr_register_hypercall(H_SET_SPRG0, h_set_sprg0);
diff --git a/include/hw/ppc/spapr.h b/include/hw/ppc/spapr.h
index 04d2821..a2d8964 100644
--- a/include/hw/ppc/spapr.h
+++ b/include/hw/ppc/spapr.h
@@ -347,7 +347,8 @@ struct sPAPRMachineState {
#define H_XIRR_X 0x2FC
#define H_RANDOM 0x300
#define H_SET_MODE 0x31C
-#define MAX_HCALL_OPCODE H_SET_MODE
+#define H_SIGNAL_SYS_RESET 0x380
+#define MAX_HCALL_OPCODE H_SIGNAL_SYS_RESET
/* The hcalls above are standardized in PAPR and implemented by pHyp
* as well.
@@ -660,4 +661,6 @@ int spapr_rng_populate_dt(void *fdt);
#define SPAPR_LMB_FLAGS_DRC_INVALID 0x00000020
#define SPAPR_LMB_FLAGS_RESERVED 0x00000080
+void spapr_do_system_reset_on_cpu(CPUState *cs, run_on_cpu_data arg);
+
#endif /* HW_SPAPR_H */
--
2.9.3
^ permalink raw reply related [flat|nested] 73+ messages in thread
* [Qemu-devel] [PULL 20/67] target-ppc: move ppc_vsr_t to common header
2017-01-12 2:02 [Qemu-devel] [PULL 00/67] ppc-for-2.9 queue 20170112 David Gibson
` (18 preceding siblings ...)
2017-01-12 2:02 ` [Qemu-devel] [PULL 19/67] ppc/spapr: implement H_SIGNAL_SYS_RESET David Gibson
@ 2017-01-12 2:02 ` David Gibson
2017-01-12 2:02 ` [Qemu-devel] [PULL 21/67] target-ppc: implement stop instruction David Gibson
` (48 subsequent siblings)
68 siblings, 0 replies; 73+ messages in thread
From: David Gibson @ 2017-01-12 2:02 UTC (permalink / raw)
To: peter.maydell
Cc: agraf, qemu-ppc, qemu-devel, thuth, lvivier, aik, mdroth,
Nikunj A Dadhania, David Gibson
From: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
The structure and corresponding defines and functions need to be used
outside of fpu_helper.c as well.
Add u8, u16, u32 and Int128 to the structure.
Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
target/ppc/fpu_helper.c | 37 -------------------------------------
target/ppc/internal.h | 42 ++++++++++++++++++++++++++++++++++++++++++
2 files changed, 42 insertions(+), 37 deletions(-)
diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c
index 696f537..3b867cf 100644
--- a/target/ppc/fpu_helper.c
+++ b/target/ppc/fpu_helper.c
@@ -1777,43 +1777,6 @@ uint32_t helper_efdcmpeq(CPUPPCState *env, uint64_t op1, uint64_t op2)
return helper_efdtsteq(env, op1, op2);
}
-typedef union _ppc_vsr_t {
- uint64_t u64[2];
- uint32_t u32[4];
- float32 f32[4];
- float64 f64[2];
-} ppc_vsr_t;
-
-#if defined(HOST_WORDS_BIGENDIAN)
-#define VsrW(i) u32[i]
-#define VsrD(i) u64[i]
-#else
-#define VsrW(i) u32[3-(i)]
-#define VsrD(i) u64[1-(i)]
-#endif
-
-static void getVSR(int n, ppc_vsr_t *vsr, CPUPPCState *env)
-{
- if (n < 32) {
- vsr->VsrD(0) = env->fpr[n];
- vsr->VsrD(1) = env->vsr[n];
- } else {
- vsr->u64[0] = env->avr[n-32].u64[0];
- vsr->u64[1] = env->avr[n-32].u64[1];
- }
-}
-
-static void putVSR(int n, ppc_vsr_t *vsr, CPUPPCState *env)
-{
- if (n < 32) {
- env->fpr[n] = vsr->VsrD(0);
- env->vsr[n] = vsr->VsrD(1);
- } else {
- env->avr[n-32].u64[0] = vsr->u64[0];
- env->avr[n-32].u64[1] = vsr->u64[1];
- }
-}
-
#define float64_to_float64(x, env) x
diff --git a/target/ppc/internal.h b/target/ppc/internal.h
index e83ea45..66cde46 100644
--- a/target/ppc/internal.h
+++ b/target/ppc/internal.h
@@ -199,4 +199,46 @@ EXTRACT_HELPER(SHW, 8, 2);
EXTRACT_HELPER(SP, 19, 2);
EXTRACT_HELPER(IMM8, 11, 8);
+typedef union _ppc_vsr_t {
+ uint8_t u8[16];
+ uint16_t u16[8];
+ uint32_t u32[4];
+ uint64_t u64[2];
+ float32 f32[4];
+ float64 f64[2];
+ Int128 s128;
+} ppc_vsr_t;
+
+#if defined(HOST_WORDS_BIGENDIAN)
+#define VsrB(i) u8[i]
+#define VsrW(i) u32[i]
+#define VsrD(i) u64[i]
+#else
+#define VsrB(i) u8[15 - (i)]
+#define VsrW(i) u32[3 - (i)]
+#define VsrD(i) u64[1 - (i)]
+#endif
+
+static inline void getVSR(int n, ppc_vsr_t *vsr, CPUPPCState *env)
+{
+ if (n < 32) {
+ vsr->VsrD(0) = env->fpr[n];
+ vsr->VsrD(1) = env->vsr[n];
+ } else {
+ vsr->u64[0] = env->avr[n - 32].u64[0];
+ vsr->u64[1] = env->avr[n - 32].u64[1];
+ }
+}
+
+static inline void putVSR(int n, ppc_vsr_t *vsr, CPUPPCState *env)
+{
+ if (n < 32) {
+ env->fpr[n] = vsr->VsrD(0);
+ env->vsr[n] = vsr->VsrD(1);
+ } else {
+ env->avr[n - 32].u64[0] = vsr->u64[0];
+ env->avr[n - 32].u64[1] = vsr->u64[1];
+ }
+}
+
#endif /* PPC_INTERNAL_H */
--
2.9.3
^ permalink raw reply related [flat|nested] 73+ messages in thread
* [Qemu-devel] [PULL 21/67] target-ppc: implement stop instruction
2017-01-12 2:02 [Qemu-devel] [PULL 00/67] ppc-for-2.9 queue 20170112 David Gibson
` (19 preceding siblings ...)
2017-01-12 2:02 ` [Qemu-devel] [PULL 20/67] target-ppc: move ppc_vsr_t to common header David Gibson
@ 2017-01-12 2:02 ` David Gibson
2017-01-12 2:02 ` [Qemu-devel] [PULL 22/67] target-ppc: implement xsabsqp/xsnabsqp instruction David Gibson
` (47 subsequent siblings)
68 siblings, 0 replies; 73+ messages in thread
From: David Gibson @ 2017-01-12 2:02 UTC (permalink / raw)
To: peter.maydell
Cc: agraf, qemu-ppc, qemu-devel, thuth, lvivier, aik, mdroth,
Nikunj A Dadhania, David Gibson
From: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
Use the nap code.
Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
target/ppc/translate.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index f68f427..47349e7 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -3153,6 +3153,11 @@ static void gen_nap(DisasContext *ctx)
#endif /* defined(CONFIG_USER_ONLY) */
}
+static void gen_stop(DisasContext *ctx)
+{
+ gen_nap(ctx);
+}
+
static void gen_sleep(DisasContext *ctx)
{
#if defined(CONFIG_USER_ONLY)
@@ -6221,6 +6226,7 @@ GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER),
GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW),
#if defined(TARGET_PPC64)
GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B),
+GEN_HANDLER_E(stop, 0x13, 0x12, 0x0b, 0x03FFF801, PPC_NONE, PPC2_ISA300),
GEN_HANDLER_E(doze, 0x13, 0x12, 0x0c, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206),
GEN_HANDLER_E(nap, 0x13, 0x12, 0x0d, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206),
GEN_HANDLER_E(sleep, 0x13, 0x12, 0x0e, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206),
--
2.9.3
^ permalink raw reply related [flat|nested] 73+ messages in thread
* [Qemu-devel] [PULL 22/67] target-ppc: implement xsabsqp/xsnabsqp instruction
2017-01-12 2:02 [Qemu-devel] [PULL 00/67] ppc-for-2.9 queue 20170112 David Gibson
` (20 preceding siblings ...)
2017-01-12 2:02 ` [Qemu-devel] [PULL 21/67] target-ppc: implement stop instruction David Gibson
@ 2017-01-12 2:02 ` David Gibson
2017-01-12 2:02 ` [Qemu-devel] [PULL 23/67] target-ppc: Implement bcd_is_valid function David Gibson
` (46 subsequent siblings)
68 siblings, 0 replies; 73+ messages in thread
From: David Gibson @ 2017-01-12 2:02 UTC (permalink / raw)
To: peter.maydell
Cc: agraf, qemu-ppc, qemu-devel, thuth, lvivier, aik, mdroth,
David Gibson, Nikunj A Dadhania
xsabsqp: VSX Scalar Absolute Quad-Precision
xsnabsqp: VSX Scalar Negative Absolute Quad-Precision
Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
target/ppc/translate/vsx-impl.inc.c | 35 +++++++++++++++++++++++++++++++++++
target/ppc/translate/vsx-ops.inc.c | 5 +++++
2 files changed, 40 insertions(+)
diff --git a/target/ppc/translate/vsx-impl.inc.c b/target/ppc/translate/vsx-impl.inc.c
index 2fbdbd2..808ee48 100644
--- a/target/ppc/translate/vsx-impl.inc.c
+++ b/target/ppc/translate/vsx-impl.inc.c
@@ -609,6 +609,41 @@ VSX_SCALAR_MOVE(xsnabsdp, OP_NABS, SGN_MASK_DP)
VSX_SCALAR_MOVE(xsnegdp, OP_NEG, SGN_MASK_DP)
VSX_SCALAR_MOVE(xscpsgndp, OP_CPSGN, SGN_MASK_DP)
+#define VSX_SCALAR_MOVE_QP(name, op, sgn_mask) \
+static void glue(gen_, name)(DisasContext *ctx) \
+{ \
+ int xt = rD(ctx->opcode) + 32; \
+ int xb = rB(ctx->opcode) + 32; \
+ TCGv_i64 xbh, xbl, sgm; \
+ \
+ if (unlikely(!ctx->vsx_enabled)) { \
+ gen_exception(ctx, POWERPC_EXCP_VSXU); \
+ return; \
+ } \
+ xbh = tcg_temp_new_i64(); \
+ xbl = tcg_temp_new_i64(); \
+ sgm = tcg_temp_new_i64(); \
+ tcg_gen_mov_i64(xbh, cpu_vsrh(xb)); \
+ tcg_gen_mov_i64(xbl, cpu_vsrl(xb)); \
+ tcg_gen_movi_i64(sgm, sgn_mask); \
+ switch (op) { \
+ case OP_ABS: \
+ tcg_gen_andc_i64(xbh, xbh, sgm); \
+ break; \
+ case OP_NABS: \
+ tcg_gen_or_i64(xbh, xbh, sgm); \
+ break; \
+ } \
+ tcg_gen_mov_i64(cpu_vsrh(xt), xbh); \
+ tcg_gen_mov_i64(cpu_vsrl(xt), xbl); \
+ tcg_temp_free_i64(xbl); \
+ tcg_temp_free_i64(xbh); \
+ tcg_temp_free_i64(sgm); \
+}
+
+VSX_SCALAR_MOVE_QP(xsabsqp, OP_ABS, SGN_MASK_DP)
+VSX_SCALAR_MOVE_QP(xsnabsqp, OP_NABS, SGN_MASK_DP)
+
#define VSX_VECTOR_MOVE(name, op, sgn_mask) \
static void glue(gen_, name)(DisasContext * ctx) \
{ \
diff --git a/target/ppc/translate/vsx-ops.inc.c b/target/ppc/translate/vsx-ops.inc.c
index 8a1cbe0..daf6a56 100644
--- a/target/ppc/translate/vsx-ops.inc.c
+++ b/target/ppc/translate/vsx-ops.inc.c
@@ -88,12 +88,17 @@ GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x0C, 0, PPC_NONE, PPC2_VSX)
#define GEN_VSX_XFORM_300(name, opc2, opc3, inval) \
GEN_HANDLER_E(name, 0x3F, opc2, opc3, inval, PPC_NONE, PPC2_ISA300)
+#define GEN_VSX_XFORM_300_EO(name, opc2, opc3, opc4, inval) \
+GEN_HANDLER_E_2(name, 0x3F, opc2, opc3, opc4, inval, PPC_NONE, PPC2_ISA300)
GEN_XX2FORM(xsabsdp, 0x12, 0x15, PPC2_VSX),
GEN_XX2FORM(xsnabsdp, 0x12, 0x16, PPC2_VSX),
GEN_XX2FORM(xsnegdp, 0x12, 0x17, PPC2_VSX),
GEN_XX3FORM(xscpsgndp, 0x00, 0x16, PPC2_VSX),
+GEN_VSX_XFORM_300_EO(xsabsqp, 0x04, 0x19, 0x00, 0x00000001),
+GEN_VSX_XFORM_300_EO(xsnabsqp, 0x04, 0x19, 0x08, 0x00000001),
+
GEN_XX2FORM(xvabsdp, 0x12, 0x1D, PPC2_VSX),
GEN_XX2FORM(xvnabsdp, 0x12, 0x1E, PPC2_VSX),
GEN_XX2FORM(xvnegdp, 0x12, 0x1F, PPC2_VSX),
--
2.9.3
^ permalink raw reply related [flat|nested] 73+ messages in thread
* [Qemu-devel] [PULL 23/67] target-ppc: Implement bcd_is_valid function
2017-01-12 2:02 [Qemu-devel] [PULL 00/67] ppc-for-2.9 queue 20170112 David Gibson
` (21 preceding siblings ...)
2017-01-12 2:02 ` [Qemu-devel] [PULL 22/67] target-ppc: implement xsabsqp/xsnabsqp instruction David Gibson
@ 2017-01-12 2:02 ` David Gibson
2017-01-12 2:02 ` [Qemu-devel] [PULL 24/67] target-ppc: implement xsnegqp instruction David Gibson
` (45 subsequent siblings)
68 siblings, 0 replies; 73+ messages in thread
From: David Gibson @ 2017-01-12 2:02 UTC (permalink / raw)
To: peter.maydell
Cc: agraf, qemu-ppc, qemu-devel, thuth, lvivier, aik, mdroth,
Jose Ricardo Ziviani, David Gibson
From: Jose Ricardo Ziviani <joserz@linux.vnet.ibm.com>
A function to check if all digits of a given BCD number is valid is
here presented because more instructions will need to reuse the
same code.
Signed-off-by: Jose Ricardo Ziviani <joserz@linux.vnet.ibm.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
target/ppc/int_helper.c | 27 ++++++++++++++++++++-------
1 file changed, 20 insertions(+), 7 deletions(-)
diff --git a/target/ppc/int_helper.c b/target/ppc/int_helper.c
index 34dfe02..2bb628f 100644
--- a/target/ppc/int_helper.c
+++ b/target/ppc/int_helper.c
@@ -2596,6 +2596,24 @@ static void bcd_put_digit(ppc_avr_t *bcd, uint8_t digit, int n)
}
}
+static bool bcd_is_valid(ppc_avr_t *bcd)
+{
+ int i;
+ int invalid = 0;
+
+ if (bcd_get_sgn(bcd) == 0) {
+ return false;
+ }
+
+ for (i = 1; i < 32; i++) {
+ bcd_get_digit(bcd, i, &invalid);
+ if (unlikely(invalid)) {
+ return false;
+ }
+ }
+ return true;
+}
+
static int bcd_cmp_zero(ppc_avr_t *bcd)
{
if (bcd->u64[HI_IDX] == 0 && (bcd->u64[LO_IDX] >> 4) == 0) {
@@ -3013,18 +3031,13 @@ uint32_t helper_bcdcpsgn(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, uint32_t ps)
uint32_t helper_bcdsetsgn(ppc_avr_t *r, ppc_avr_t *b, uint32_t ps)
{
- int i;
- int invalid = 0;
int sgnb = bcd_get_sgn(b);
*r = *b;
bcd_put_digit(r, bcd_preferred_sgn(sgnb, ps), 0);
- for (i = 1; i < 32; i++) {
- bcd_get_digit(b, i, &invalid);
- if (unlikely(invalid)) {
- return CRF_SO;
- }
+ if (bcd_is_valid(b) == false) {
+ return CRF_SO;
}
return bcd_cmp_zero(r);
--
2.9.3
^ permalink raw reply related [flat|nested] 73+ messages in thread
* [Qemu-devel] [PULL 24/67] target-ppc: implement xsnegqp instruction
2017-01-12 2:02 [Qemu-devel] [PULL 00/67] ppc-for-2.9 queue 20170112 David Gibson
` (22 preceding siblings ...)
2017-01-12 2:02 ` [Qemu-devel] [PULL 23/67] target-ppc: Implement bcd_is_valid function David Gibson
@ 2017-01-12 2:02 ` David Gibson
2017-01-12 2:02 ` [Qemu-devel] [PULL 25/67] target-ppc: implement xscpsgnqp instruction David Gibson
` (44 subsequent siblings)
68 siblings, 0 replies; 73+ messages in thread
From: David Gibson @ 2017-01-12 2:02 UTC (permalink / raw)
To: peter.maydell
Cc: agraf, qemu-ppc, qemu-devel, thuth, lvivier, aik, mdroth,
Nikunj A Dadhania, David Gibson
From: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
xsnegqp: VSX Scalar Negate Quad-Precision
Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
target/ppc/translate/vsx-impl.inc.c | 4 ++++
target/ppc/translate/vsx-ops.inc.c | 1 +
2 files changed, 5 insertions(+)
diff --git a/target/ppc/translate/vsx-impl.inc.c b/target/ppc/translate/vsx-impl.inc.c
index 808ee48..e74e16e 100644
--- a/target/ppc/translate/vsx-impl.inc.c
+++ b/target/ppc/translate/vsx-impl.inc.c
@@ -633,6 +633,9 @@ static void glue(gen_, name)(DisasContext *ctx) \
case OP_NABS: \
tcg_gen_or_i64(xbh, xbh, sgm); \
break; \
+ case OP_NEG: \
+ tcg_gen_xor_i64(xbh, xbh, sgm); \
+ break; \
} \
tcg_gen_mov_i64(cpu_vsrh(xt), xbh); \
tcg_gen_mov_i64(cpu_vsrl(xt), xbl); \
@@ -643,6 +646,7 @@ static void glue(gen_, name)(DisasContext *ctx) \
VSX_SCALAR_MOVE_QP(xsabsqp, OP_ABS, SGN_MASK_DP)
VSX_SCALAR_MOVE_QP(xsnabsqp, OP_NABS, SGN_MASK_DP)
+VSX_SCALAR_MOVE_QP(xsnegqp, OP_NEG, SGN_MASK_DP)
#define VSX_VECTOR_MOVE(name, op, sgn_mask) \
static void glue(gen_, name)(DisasContext * ctx) \
diff --git a/target/ppc/translate/vsx-ops.inc.c b/target/ppc/translate/vsx-ops.inc.c
index daf6a56..f7132b4 100644
--- a/target/ppc/translate/vsx-ops.inc.c
+++ b/target/ppc/translate/vsx-ops.inc.c
@@ -98,6 +98,7 @@ GEN_XX3FORM(xscpsgndp, 0x00, 0x16, PPC2_VSX),
GEN_VSX_XFORM_300_EO(xsabsqp, 0x04, 0x19, 0x00, 0x00000001),
GEN_VSX_XFORM_300_EO(xsnabsqp, 0x04, 0x19, 0x08, 0x00000001),
+GEN_VSX_XFORM_300_EO(xsnegqp, 0x04, 0x19, 0x10, 0x00000001),
GEN_XX2FORM(xvabsdp, 0x12, 0x1D, PPC2_VSX),
GEN_XX2FORM(xvnabsdp, 0x12, 0x1E, PPC2_VSX),
--
2.9.3
^ permalink raw reply related [flat|nested] 73+ messages in thread
* [Qemu-devel] [PULL 25/67] target-ppc: implement xscpsgnqp instruction
2017-01-12 2:02 [Qemu-devel] [PULL 00/67] ppc-for-2.9 queue 20170112 David Gibson
` (23 preceding siblings ...)
2017-01-12 2:02 ` [Qemu-devel] [PULL 24/67] target-ppc: implement xsnegqp instruction David Gibson
@ 2017-01-12 2:02 ` David Gibson
2017-01-12 2:02 ` [Qemu-devel] [PULL 26/67] target-ppc: Add xxperm and xxpermr instructions David Gibson
` (43 subsequent siblings)
68 siblings, 0 replies; 73+ messages in thread
From: David Gibson @ 2017-01-12 2:02 UTC (permalink / raw)
To: peter.maydell
Cc: agraf, qemu-ppc, qemu-devel, thuth, lvivier, aik, mdroth,
Nikunj A Dadhania, David Gibson
From: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
xscpsgnqp: VSX Scalar Copy Sign Quad-Precision
Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
target/ppc/translate/vsx-impl.inc.c | 12 +++++++++++-
target/ppc/translate/vsx-ops.inc.c | 1 +
2 files changed, 12 insertions(+), 1 deletion(-)
diff --git a/target/ppc/translate/vsx-impl.inc.c b/target/ppc/translate/vsx-impl.inc.c
index e74e16e..90d26a2 100644
--- a/target/ppc/translate/vsx-impl.inc.c
+++ b/target/ppc/translate/vsx-impl.inc.c
@@ -612,9 +612,10 @@ VSX_SCALAR_MOVE(xscpsgndp, OP_CPSGN, SGN_MASK_DP)
#define VSX_SCALAR_MOVE_QP(name, op, sgn_mask) \
static void glue(gen_, name)(DisasContext *ctx) \
{ \
+ int xa; \
int xt = rD(ctx->opcode) + 32; \
int xb = rB(ctx->opcode) + 32; \
- TCGv_i64 xbh, xbl, sgm; \
+ TCGv_i64 xah, xbh, xbl, sgm; \
\
if (unlikely(!ctx->vsx_enabled)) { \
gen_exception(ctx, POWERPC_EXCP_VSXU); \
@@ -636,6 +637,14 @@ static void glue(gen_, name)(DisasContext *ctx) \
case OP_NEG: \
tcg_gen_xor_i64(xbh, xbh, sgm); \
break; \
+ case OP_CPSGN: \
+ xah = tcg_temp_new_i64(); \
+ xa = rA(ctx->opcode) + 32; \
+ tcg_gen_and_i64(xah, cpu_vsrh(xa), sgm); \
+ tcg_gen_andc_i64(xbh, xbh, sgm); \
+ tcg_gen_or_i64(xbh, xbh, xah); \
+ tcg_temp_free_i64(xah); \
+ break; \
} \
tcg_gen_mov_i64(cpu_vsrh(xt), xbh); \
tcg_gen_mov_i64(cpu_vsrl(xt), xbl); \
@@ -647,6 +656,7 @@ static void glue(gen_, name)(DisasContext *ctx) \
VSX_SCALAR_MOVE_QP(xsabsqp, OP_ABS, SGN_MASK_DP)
VSX_SCALAR_MOVE_QP(xsnabsqp, OP_NABS, SGN_MASK_DP)
VSX_SCALAR_MOVE_QP(xsnegqp, OP_NEG, SGN_MASK_DP)
+VSX_SCALAR_MOVE_QP(xscpsgnqp, OP_CPSGN, SGN_MASK_DP)
#define VSX_VECTOR_MOVE(name, op, sgn_mask) \
static void glue(gen_, name)(DisasContext * ctx) \
diff --git a/target/ppc/translate/vsx-ops.inc.c b/target/ppc/translate/vsx-ops.inc.c
index f7132b4..68fa171 100644
--- a/target/ppc/translate/vsx-ops.inc.c
+++ b/target/ppc/translate/vsx-ops.inc.c
@@ -99,6 +99,7 @@ GEN_XX3FORM(xscpsgndp, 0x00, 0x16, PPC2_VSX),
GEN_VSX_XFORM_300_EO(xsabsqp, 0x04, 0x19, 0x00, 0x00000001),
GEN_VSX_XFORM_300_EO(xsnabsqp, 0x04, 0x19, 0x08, 0x00000001),
GEN_VSX_XFORM_300_EO(xsnegqp, 0x04, 0x19, 0x10, 0x00000001),
+GEN_VSX_XFORM_300(xscpsgnqp, 0x04, 0x03, 0x00000001),
GEN_XX2FORM(xvabsdp, 0x12, 0x1D, PPC2_VSX),
GEN_XX2FORM(xvnabsdp, 0x12, 0x1E, PPC2_VSX),
--
2.9.3
^ permalink raw reply related [flat|nested] 73+ messages in thread
* [Qemu-devel] [PULL 26/67] target-ppc: Add xxperm and xxpermr instructions
2017-01-12 2:02 [Qemu-devel] [PULL 00/67] ppc-for-2.9 queue 20170112 David Gibson
` (24 preceding siblings ...)
2017-01-12 2:02 ` [Qemu-devel] [PULL 25/67] target-ppc: implement xscpsgnqp instruction David Gibson
@ 2017-01-12 2:02 ` David Gibson
2017-01-12 2:02 ` [Qemu-devel] [PULL 27/67] target-ppc: implement lxvl instruction David Gibson
` (42 subsequent siblings)
68 siblings, 0 replies; 73+ messages in thread
From: David Gibson @ 2017-01-12 2:02 UTC (permalink / raw)
To: peter.maydell
Cc: agraf, qemu-ppc, qemu-devel, thuth, lvivier, aik, mdroth,
Bharata B Rao, Nikunj A Dadhania, David Gibson
From: Bharata B Rao <bharata@linux.vnet.ibm.com>
xxperm: VSX Vector Permute
xxpermr: VSX Vector Permute Right-indexed
Signed-off-by: Bharata B Rao <bharata@linux.vnet.ibm.com>
Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
target/ppc/fpu_helper.c | 23 +++++++++++++++++++++++
target/ppc/helper.h | 2 ++
target/ppc/translate/vsx-impl.inc.c | 2 ++
target/ppc/translate/vsx-ops.inc.c | 2 ++
4 files changed, 29 insertions(+)
diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c
index 3b867cf..1ccd5e6 100644
--- a/target/ppc/fpu_helper.c
+++ b/target/ppc/fpu_helper.c
@@ -2869,3 +2869,26 @@ uint64_t helper_xsrsp(CPUPPCState *env, uint64_t xb)
float_check_status(env);
return xt;
}
+
+#define VSX_XXPERM(op, indexed) \
+void helper_##op(CPUPPCState *env, uint32_t opcode) \
+{ \
+ ppc_vsr_t xt, xa, pcv, xto; \
+ int i, idx; \
+ \
+ getVSR(xA(opcode), &xa, env); \
+ getVSR(xT(opcode), &xt, env); \
+ getVSR(xB(opcode), &pcv, env); \
+ \
+ for (i = 0; i < 16; i++) { \
+ idx = pcv.VsrB(i) & 0x1F; \
+ if (indexed) { \
+ idx = 31 - idx; \
+ } \
+ xto.VsrB(i) = (idx <= 15) ? xa.VsrB(idx) : xt.VsrB(idx - 16); \
+ } \
+ putVSR(xT(opcode), &xto, env); \
+}
+
+VSX_XXPERM(xxperm, 0)
+VSX_XXPERM(xxpermr, 1)
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index bc39efb..c3df982 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -532,6 +532,8 @@ DEF_HELPER_2(xvrspic, void, env, i32)
DEF_HELPER_2(xvrspim, void, env, i32)
DEF_HELPER_2(xvrspip, void, env, i32)
DEF_HELPER_2(xvrspiz, void, env, i32)
+DEF_HELPER_2(xxperm, void, env, i32)
+DEF_HELPER_2(xxpermr, void, env, i32)
DEF_HELPER_2(efscfsi, i32, env, i32)
DEF_HELPER_2(efscfui, i32, env, i32)
diff --git a/target/ppc/translate/vsx-impl.inc.c b/target/ppc/translate/vsx-impl.inc.c
index 90d26a2..7000035 100644
--- a/target/ppc/translate/vsx-impl.inc.c
+++ b/target/ppc/translate/vsx-impl.inc.c
@@ -883,6 +883,8 @@ GEN_VSX_HELPER_2(xvrspic, 0x16, 0x0A, 0, PPC2_VSX)
GEN_VSX_HELPER_2(xvrspim, 0x12, 0x0B, 0, PPC2_VSX)
GEN_VSX_HELPER_2(xvrspip, 0x12, 0x0A, 0, PPC2_VSX)
GEN_VSX_HELPER_2(xvrspiz, 0x12, 0x09, 0, PPC2_VSX)
+GEN_VSX_HELPER_2(xxperm, 0x08, 0x03, 0, PPC2_ISA300)
+GEN_VSX_HELPER_2(xxpermr, 0x08, 0x07, 0, PPC2_ISA300)
static void gen_xxbrd(DisasContext *ctx)
{
diff --git a/target/ppc/translate/vsx-ops.inc.c b/target/ppc/translate/vsx-ops.inc.c
index 68fa171..f684066 100644
--- a/target/ppc/translate/vsx-ops.inc.c
+++ b/target/ppc/translate/vsx-ops.inc.c
@@ -267,6 +267,8 @@ VSX_LOGICAL(xxlnand, 0x8, 0x16, PPC2_VSX207),
VSX_LOGICAL(xxlorc, 0x8, 0x15, PPC2_VSX207),
GEN_XX3FORM(xxmrghw, 0x08, 0x02, PPC2_VSX),
GEN_XX3FORM(xxmrglw, 0x08, 0x06, PPC2_VSX),
+GEN_XX3FORM(xxperm, 0x08, 0x03, PPC2_ISA300),
+GEN_XX3FORM(xxpermr, 0x08, 0x07, PPC2_ISA300),
GEN_XX2FORM(xxspltw, 0x08, 0x0A, PPC2_VSX),
GEN_XX1FORM(xxspltib, 0x08, 0x0B, PPC2_ISA300),
GEN_XX3FORM_DM(xxsldwi, 0x08, 0x00),
--
2.9.3
^ permalink raw reply related [flat|nested] 73+ messages in thread
* [Qemu-devel] [PULL 27/67] target-ppc: implement lxvl instruction
2017-01-12 2:02 [Qemu-devel] [PULL 00/67] ppc-for-2.9 queue 20170112 David Gibson
` (25 preceding siblings ...)
2017-01-12 2:02 ` [Qemu-devel] [PULL 26/67] target-ppc: Add xxperm and xxpermr instructions David Gibson
@ 2017-01-12 2:02 ` David Gibson
2017-01-12 2:02 ` [Qemu-devel] [PULL 28/67] target-ppc: implement lxvll instruction David Gibson
` (41 subsequent siblings)
68 siblings, 0 replies; 73+ messages in thread
From: David Gibson @ 2017-01-12 2:02 UTC (permalink / raw)
To: peter.maydell
Cc: agraf, qemu-ppc, qemu-devel, thuth, lvivier, aik, mdroth,
Nikunj A Dadhania, David Gibson
From: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
lxvl: Load VSX Vector with Length
Little/Big-endian Storage:
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--+--+
|“T”|“h”|“i”|“s”|“ ”|“i”|“s”|“ ”|“a”|“ ”|“T”|“E”|“S”|“T”|FF|FF|
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--+--+
Loading 14 bytes results in:
Vector (8-bit elements) in BE:
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--+--+
|“T”|“h”|“i”|“s”|“ ”|“i”|“s”|“ ”|“a”|“ ”|“T”|“E”|“S”|“T”|00|00|
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--+--+
Vector (8-bit elements) in LE:
+--+--+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
|00|00|“T”|“S”|“E”|“T”|“ ”|“a”|“ ”|“s”|“i”|“ ”|“s”|“i”|"h"|"T"|
+--+--+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
target/ppc/helper.h | 3 +++
target/ppc/mem_helper.c | 35 +++++++++++++++++++++++++++++++++++
target/ppc/translate/vsx-impl.inc.c | 29 +++++++++++++++++++++++++++++
target/ppc/translate/vsx-ops.inc.c | 3 +++
4 files changed, 70 insertions(+)
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index c3df982..16ed2c1 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -317,6 +317,9 @@ DEF_HELPER_3(lvewx, void, env, avr, tl)
DEF_HELPER_3(stvebx, void, env, avr, tl)
DEF_HELPER_3(stvehx, void, env, avr, tl)
DEF_HELPER_3(stvewx, void, env, avr, tl)
+#if defined(TARGET_PPC64)
+DEF_HELPER_4(lxvl, void, env, tl, tl, tl)
+#endif
DEF_HELPER_4(vsumsws, void, env, avr, avr, avr)
DEF_HELPER_4(vsum2sws, void, env, avr, avr, avr)
DEF_HELPER_4(vsum4sbs, void, env, avr, avr, avr)
diff --git a/target/ppc/mem_helper.c b/target/ppc/mem_helper.c
index 1ab8a6e..c4ddc5b 100644
--- a/target/ppc/mem_helper.c
+++ b/target/ppc/mem_helper.c
@@ -24,6 +24,7 @@
#include "helper_regs.h"
#include "exec/cpu_ldst.h"
+#include "internal.h"
//#define DEBUG_OP
@@ -284,6 +285,40 @@ STVE(stvewx, cpu_stl_data_ra, bswap32, u32)
#undef I
#undef LVE
+#ifdef TARGET_PPC64
+#define GET_NB(rb) ((rb >> 56) & 0xFF)
+
+#define VSX_LXVL(name, lj) \
+void helper_##name(CPUPPCState *env, target_ulong addr, \
+ target_ulong xt_num, target_ulong rb) \
+{ \
+ int i; \
+ ppc_vsr_t xt; \
+ uint64_t nb = GET_NB(rb); \
+ \
+ xt.s128 = int128_zero(); \
+ if (nb) { \
+ nb = (nb >= 16) ? 16 : nb; \
+ if (msr_le && !lj) { \
+ for (i = 16; i > 16 - nb; i--) { \
+ xt.VsrB(i - 1) = cpu_ldub_data_ra(env, addr, GETPC()); \
+ addr = addr_add(env, addr, 1); \
+ } \
+ } else { \
+ for (i = 0; i < nb; i++) { \
+ xt.VsrB(i) = cpu_ldub_data_ra(env, addr, GETPC()); \
+ addr = addr_add(env, addr, 1); \
+ } \
+ } \
+ } \
+ putVSR(xt_num, &xt, env); \
+}
+
+VSX_LXVL(lxvl, 0)
+#undef VSX_LXVL
+#undef GET_NB
+#endif /* TARGET_PPC64 */
+
#undef HI_IDX
#undef LO_IDX
diff --git a/target/ppc/translate/vsx-impl.inc.c b/target/ppc/translate/vsx-impl.inc.c
index 7000035..1f64fb7 100644
--- a/target/ppc/translate/vsx-impl.inc.c
+++ b/target/ppc/translate/vsx-impl.inc.c
@@ -240,6 +240,35 @@ VSX_VECTOR_LOAD_STORE(stxv, st_i64, 0)
VSX_VECTOR_LOAD_STORE(lxvx, ld_i64, 1)
VSX_VECTOR_LOAD_STORE(stxvx, st_i64, 1)
+#ifdef TARGET_PPC64
+#define VSX_VECTOR_LOAD_STORE_LENGTH(name) \
+static void gen_##name(DisasContext *ctx) \
+{ \
+ TCGv EA, xt; \
+ \
+ if (xT(ctx->opcode) < 32) { \
+ if (unlikely(!ctx->vsx_enabled)) { \
+ gen_exception(ctx, POWERPC_EXCP_VSXU); \
+ return; \
+ } \
+ } else { \
+ if (unlikely(!ctx->altivec_enabled)) { \
+ gen_exception(ctx, POWERPC_EXCP_VPU); \
+ return; \
+ } \
+ } \
+ EA = tcg_temp_new(); \
+ xt = tcg_const_tl(xT(ctx->opcode)); \
+ gen_set_access_type(ctx, ACCESS_INT); \
+ gen_addr_register(ctx, EA); \
+ gen_helper_##name(cpu_env, EA, xt, cpu_gpr[rB(ctx->opcode)]); \
+ tcg_temp_free(EA); \
+ tcg_temp_free(xt); \
+}
+
+VSX_VECTOR_LOAD_STORE_LENGTH(lxvl)
+#endif
+
#define VSX_LOAD_SCALAR_DS(name, operation) \
static void gen_##name(DisasContext *ctx) \
{ \
diff --git a/target/ppc/translate/vsx-ops.inc.c b/target/ppc/translate/vsx-ops.inc.c
index f684066..62a0afc 100644
--- a/target/ppc/translate/vsx-ops.inc.c
+++ b/target/ppc/translate/vsx-ops.inc.c
@@ -10,6 +10,9 @@ GEN_HANDLER_E(lxvw4x, 0x1F, 0x0C, 0x18, 0, PPC_NONE, PPC2_VSX),
GEN_HANDLER_E(lxvh8x, 0x1F, 0x0C, 0x19, 0, PPC_NONE, PPC2_ISA300),
GEN_HANDLER_E(lxvb16x, 0x1F, 0x0C, 0x1B, 0, PPC_NONE, PPC2_ISA300),
GEN_HANDLER_E(lxvx, 0x1F, 0x0C, 0x08, 0x00000040, PPC_NONE, PPC2_ISA300),
+#if defined(TARGET_PPC64)
+GEN_HANDLER_E(lxvl, 0x1F, 0x0D, 0x08, 0, PPC_NONE, PPC2_ISA300),
+#endif
GEN_HANDLER_E(stxsdx, 0x1F, 0xC, 0x16, 0, PPC_NONE, PPC2_VSX),
GEN_HANDLER_E(stxsibx, 0x1F, 0xD, 0x1C, 0, PPC_NONE, PPC2_ISA300),
--
2.9.3
^ permalink raw reply related [flat|nested] 73+ messages in thread
* [Qemu-devel] [PULL 28/67] target-ppc: implement lxvll instruction
2017-01-12 2:02 [Qemu-devel] [PULL 00/67] ppc-for-2.9 queue 20170112 David Gibson
` (26 preceding siblings ...)
2017-01-12 2:02 ` [Qemu-devel] [PULL 27/67] target-ppc: implement lxvl instruction David Gibson
@ 2017-01-12 2:02 ` David Gibson
2017-01-12 2:02 ` [Qemu-devel] [PULL 29/67] target-ppc: implement stxvl instruction David Gibson
` (40 subsequent siblings)
68 siblings, 0 replies; 73+ messages in thread
From: David Gibson @ 2017-01-12 2:02 UTC (permalink / raw)
To: peter.maydell
Cc: agraf, qemu-ppc, qemu-devel, thuth, lvivier, aik, mdroth,
Nikunj A Dadhania, David Gibson
From: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
lxvll: Load VSX Vector Left-justified with Length
Little/Big-endian Storage:
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--+--+
|“T”|“h”|“i”|“s”|“ ”|“i”|“s”|“ ”|“a”|“ ”|“T”|“E”|“S”|“T”|FF|FF|
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--+--+
Loading 14 bytes to vector (8-bit elements) in BE/LE:
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--+--+
|“T”|“h”|“i”|“s”|“ ”|“i”|“s”|“ ”|“a”|“ ”|“T”|“E”|“S”|“T”|00|00|
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--+--+
Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
target/ppc/helper.h | 1 +
target/ppc/mem_helper.c | 1 +
target/ppc/translate/vsx-impl.inc.c | 1 +
target/ppc/translate/vsx-ops.inc.c | 1 +
4 files changed, 4 insertions(+)
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index 16ed2c1..6c44731 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -319,6 +319,7 @@ DEF_HELPER_3(stvehx, void, env, avr, tl)
DEF_HELPER_3(stvewx, void, env, avr, tl)
#if defined(TARGET_PPC64)
DEF_HELPER_4(lxvl, void, env, tl, tl, tl)
+DEF_HELPER_4(lxvll, void, env, tl, tl, tl)
#endif
DEF_HELPER_4(vsumsws, void, env, avr, avr, avr)
DEF_HELPER_4(vsum2sws, void, env, avr, avr, avr)
diff --git a/target/ppc/mem_helper.c b/target/ppc/mem_helper.c
index c4ddc5b..da51465 100644
--- a/target/ppc/mem_helper.c
+++ b/target/ppc/mem_helper.c
@@ -315,6 +315,7 @@ void helper_##name(CPUPPCState *env, target_ulong addr, \
}
VSX_LXVL(lxvl, 0)
+VSX_LXVL(lxvll, 1)
#undef VSX_LXVL
#undef GET_NB
#endif /* TARGET_PPC64 */
diff --git a/target/ppc/translate/vsx-impl.inc.c b/target/ppc/translate/vsx-impl.inc.c
index 1f64fb7..ce20579 100644
--- a/target/ppc/translate/vsx-impl.inc.c
+++ b/target/ppc/translate/vsx-impl.inc.c
@@ -267,6 +267,7 @@ static void gen_##name(DisasContext *ctx) \
}
VSX_VECTOR_LOAD_STORE_LENGTH(lxvl)
+VSX_VECTOR_LOAD_STORE_LENGTH(lxvll)
#endif
#define VSX_LOAD_SCALAR_DS(name, operation) \
diff --git a/target/ppc/translate/vsx-ops.inc.c b/target/ppc/translate/vsx-ops.inc.c
index 62a0afc..c207804 100644
--- a/target/ppc/translate/vsx-ops.inc.c
+++ b/target/ppc/translate/vsx-ops.inc.c
@@ -12,6 +12,7 @@ GEN_HANDLER_E(lxvb16x, 0x1F, 0x0C, 0x1B, 0, PPC_NONE, PPC2_ISA300),
GEN_HANDLER_E(lxvx, 0x1F, 0x0C, 0x08, 0x00000040, PPC_NONE, PPC2_ISA300),
#if defined(TARGET_PPC64)
GEN_HANDLER_E(lxvl, 0x1F, 0x0D, 0x08, 0, PPC_NONE, PPC2_ISA300),
+GEN_HANDLER_E(lxvll, 0x1F, 0x0D, 0x09, 0, PPC_NONE, PPC2_ISA300),
#endif
GEN_HANDLER_E(stxsdx, 0x1F, 0xC, 0x16, 0, PPC_NONE, PPC2_VSX),
--
2.9.3
^ permalink raw reply related [flat|nested] 73+ messages in thread
* [Qemu-devel] [PULL 29/67] target-ppc: implement stxvl instruction
2017-01-12 2:02 [Qemu-devel] [PULL 00/67] ppc-for-2.9 queue 20170112 David Gibson
` (27 preceding siblings ...)
2017-01-12 2:02 ` [Qemu-devel] [PULL 28/67] target-ppc: implement lxvll instruction David Gibson
@ 2017-01-12 2:02 ` David Gibson
2017-01-12 2:02 ` [Qemu-devel] [PULL 30/67] target-ppc: implement stxvll instructions David Gibson
` (39 subsequent siblings)
68 siblings, 0 replies; 73+ messages in thread
From: David Gibson @ 2017-01-12 2:02 UTC (permalink / raw)
To: peter.maydell
Cc: agraf, qemu-ppc, qemu-devel, thuth, lvivier, aik, mdroth,
Nikunj A Dadhania, David Gibson
From: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
stxvl: Store VSX Vector with Length
Vector (8-bit elements) in BE:
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--+--+
|“T”|“h”|“i”|“s”|“ ”|“i”|“s”|“ ”|“a”|“ ”|“T”|“E”|“S”|“T”|00|00|
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--+--+
Vector (8-bit elements) in LE:
+--+--+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
|00|00|“T”|“S”|“E”|“T”|“ ”|“a”|“ ”|“s”|“i”|“ ”|“s”|“i”|"h"|"T"|
+--+--+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
Storing 14 bytes would result in following Little/Big-endian Storage:
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--+--+
|“T”|“h”|“i”|“s”|“ ”|“i”|“s”|“ ”|“a”|“ ”|“T”|“E”|“S”|“T”|FF|FF|
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--+--+
Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
target/ppc/helper.h | 1 +
target/ppc/mem_helper.c | 29 +++++++++++++++++++++++++++++
target/ppc/translate/vsx-impl.inc.c | 1 +
target/ppc/translate/vsx-ops.inc.c | 3 +++
4 files changed, 34 insertions(+)
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index 6c44731..211313d 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -320,6 +320,7 @@ DEF_HELPER_3(stvewx, void, env, avr, tl)
#if defined(TARGET_PPC64)
DEF_HELPER_4(lxvl, void, env, tl, tl, tl)
DEF_HELPER_4(lxvll, void, env, tl, tl, tl)
+DEF_HELPER_4(stxvl, void, env, tl, tl, tl)
#endif
DEF_HELPER_4(vsumsws, void, env, avr, avr, avr)
DEF_HELPER_4(vsum2sws, void, env, avr, avr, avr)
diff --git a/target/ppc/mem_helper.c b/target/ppc/mem_helper.c
index da51465..2427b49 100644
--- a/target/ppc/mem_helper.c
+++ b/target/ppc/mem_helper.c
@@ -317,6 +317,35 @@ void helper_##name(CPUPPCState *env, target_ulong addr, \
VSX_LXVL(lxvl, 0)
VSX_LXVL(lxvll, 1)
#undef VSX_LXVL
+
+#define VSX_STXVL(name, lj) \
+void helper_##name(CPUPPCState *env, target_ulong addr, \
+ target_ulong xt_num, target_ulong rb) \
+{ \
+ int i; \
+ ppc_vsr_t xt; \
+ target_ulong nb = GET_NB(rb); \
+ \
+ if (!nb) { \
+ return; \
+ } \
+ getVSR(xt_num, &xt, env); \
+ nb = (nb >= 16) ? 16 : nb; \
+ if (msr_le && !lj) { \
+ for (i = 16; i > 16 - nb; i--) { \
+ cpu_stb_data_ra(env, addr, xt.VsrB(i - 1), GETPC()); \
+ addr = addr_add(env, addr, 1); \
+ } \
+ } else { \
+ for (i = 0; i < nb; i++) { \
+ cpu_stb_data_ra(env, addr, xt.VsrB(i), GETPC()); \
+ addr = addr_add(env, addr, 1); \
+ } \
+ } \
+}
+
+VSX_STXVL(stxvl, 0)
+#undef VSX_STXVL
#undef GET_NB
#endif /* TARGET_PPC64 */
diff --git a/target/ppc/translate/vsx-impl.inc.c b/target/ppc/translate/vsx-impl.inc.c
index ce20579..5099d44 100644
--- a/target/ppc/translate/vsx-impl.inc.c
+++ b/target/ppc/translate/vsx-impl.inc.c
@@ -268,6 +268,7 @@ static void gen_##name(DisasContext *ctx) \
VSX_VECTOR_LOAD_STORE_LENGTH(lxvl)
VSX_VECTOR_LOAD_STORE_LENGTH(lxvll)
+VSX_VECTOR_LOAD_STORE_LENGTH(stxvl)
#endif
#define VSX_LOAD_SCALAR_DS(name, operation) \
diff --git a/target/ppc/translate/vsx-ops.inc.c b/target/ppc/translate/vsx-ops.inc.c
index c207804..3afded2 100644
--- a/target/ppc/translate/vsx-ops.inc.c
+++ b/target/ppc/translate/vsx-ops.inc.c
@@ -25,6 +25,9 @@ GEN_HANDLER_E(stxvw4x, 0x1F, 0xC, 0x1C, 0, PPC_NONE, PPC2_VSX),
GEN_HANDLER_E(stxvh8x, 0x1F, 0x0C, 0x1D, 0, PPC_NONE, PPC2_ISA300),
GEN_HANDLER_E(stxvb16x, 0x1F, 0x0C, 0x1F, 0, PPC_NONE, PPC2_ISA300),
GEN_HANDLER_E(stxvx, 0x1F, 0x0C, 0x0C, 0, PPC_NONE, PPC2_ISA300),
+#if defined(TARGET_PPC64)
+GEN_HANDLER_E(stxvl, 0x1F, 0x0D, 0x0C, 0, PPC_NONE, PPC2_ISA300),
+#endif
GEN_HANDLER_E(mfvsrwz, 0x1F, 0x13, 0x03, 0x0000F800, PPC_NONE, PPC2_VSX207),
GEN_HANDLER_E(mtvsrwa, 0x1F, 0x13, 0x06, 0x0000F800, PPC_NONE, PPC2_VSX207),
--
2.9.3
^ permalink raw reply related [flat|nested] 73+ messages in thread
* [Qemu-devel] [PULL 30/67] target-ppc: implement stxvll instructions
2017-01-12 2:02 [Qemu-devel] [PULL 00/67] ppc-for-2.9 queue 20170112 David Gibson
` (28 preceding siblings ...)
2017-01-12 2:02 ` [Qemu-devel] [PULL 29/67] target-ppc: implement stxvl instruction David Gibson
@ 2017-01-12 2:02 ` David Gibson
2017-01-12 2:02 ` [Qemu-devel] [PULL 31/67] hw/ppc/spapr: Fix boot path of usb-host storage devices David Gibson
` (38 subsequent siblings)
68 siblings, 0 replies; 73+ messages in thread
From: David Gibson @ 2017-01-12 2:02 UTC (permalink / raw)
To: peter.maydell
Cc: agraf, qemu-ppc, qemu-devel, thuth, lvivier, aik, mdroth,
Nikunj A Dadhania, David Gibson
From: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
stxvll: Store VSX Vector Left-justified with Length
Vector (8-bit elements) in BE/LE:
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--+--+
|“T”|“h”|“i”|“s”|“ ”|“i”|“s”|“ ”|“a”|“ ”|“T”|“E”|“S”|“T”|00|00|
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--+--+
Storing 14 bytes would result in following Little/Big-endian Storage:
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--+--+
|“T”|“h”|“i”|“s”|“ ”|“i”|“s”|“ ”|“a”|“ ”|“T”|“E”|“S”|“T”|FF|FF|
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--+--+
Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
target/ppc/helper.h | 1 +
target/ppc/mem_helper.c | 1 +
target/ppc/translate/vsx-impl.inc.c | 1 +
target/ppc/translate/vsx-ops.inc.c | 1 +
4 files changed, 4 insertions(+)
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index 211313d..4707db4 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -321,6 +321,7 @@ DEF_HELPER_3(stvewx, void, env, avr, tl)
DEF_HELPER_4(lxvl, void, env, tl, tl, tl)
DEF_HELPER_4(lxvll, void, env, tl, tl, tl)
DEF_HELPER_4(stxvl, void, env, tl, tl, tl)
+DEF_HELPER_4(stxvll, void, env, tl, tl, tl)
#endif
DEF_HELPER_4(vsumsws, void, env, avr, avr, avr)
DEF_HELPER_4(vsum2sws, void, env, avr, avr, avr)
diff --git a/target/ppc/mem_helper.c b/target/ppc/mem_helper.c
index 2427b49..e6383c6 100644
--- a/target/ppc/mem_helper.c
+++ b/target/ppc/mem_helper.c
@@ -345,6 +345,7 @@ void helper_##name(CPUPPCState *env, target_ulong addr, \
}
VSX_STXVL(stxvl, 0)
+VSX_STXVL(stxvll, 1)
#undef VSX_STXVL
#undef GET_NB
#endif /* TARGET_PPC64 */
diff --git a/target/ppc/translate/vsx-impl.inc.c b/target/ppc/translate/vsx-impl.inc.c
index 5099d44..2a17c35 100644
--- a/target/ppc/translate/vsx-impl.inc.c
+++ b/target/ppc/translate/vsx-impl.inc.c
@@ -269,6 +269,7 @@ static void gen_##name(DisasContext *ctx) \
VSX_VECTOR_LOAD_STORE_LENGTH(lxvl)
VSX_VECTOR_LOAD_STORE_LENGTH(lxvll)
VSX_VECTOR_LOAD_STORE_LENGTH(stxvl)
+VSX_VECTOR_LOAD_STORE_LENGTH(stxvll)
#endif
#define VSX_LOAD_SCALAR_DS(name, operation) \
diff --git a/target/ppc/translate/vsx-ops.inc.c b/target/ppc/translate/vsx-ops.inc.c
index 3afded2..46b95e3 100644
--- a/target/ppc/translate/vsx-ops.inc.c
+++ b/target/ppc/translate/vsx-ops.inc.c
@@ -27,6 +27,7 @@ GEN_HANDLER_E(stxvb16x, 0x1F, 0x0C, 0x1F, 0, PPC_NONE, PPC2_ISA300),
GEN_HANDLER_E(stxvx, 0x1F, 0x0C, 0x0C, 0, PPC_NONE, PPC2_ISA300),
#if defined(TARGET_PPC64)
GEN_HANDLER_E(stxvl, 0x1F, 0x0D, 0x0C, 0, PPC_NONE, PPC2_ISA300),
+GEN_HANDLER_E(stxvll, 0x1F, 0x0D, 0x0D, 0, PPC_NONE, PPC2_ISA300),
#endif
GEN_HANDLER_E(mfvsrwz, 0x1F, 0x13, 0x03, 0x0000F800, PPC_NONE, PPC2_VSX207),
--
2.9.3
^ permalink raw reply related [flat|nested] 73+ messages in thread
* [Qemu-devel] [PULL 31/67] hw/ppc/spapr: Fix boot path of usb-host storage devices
2017-01-12 2:02 [Qemu-devel] [PULL 00/67] ppc-for-2.9 queue 20170112 David Gibson
` (29 preceding siblings ...)
2017-01-12 2:02 ` [Qemu-devel] [PULL 30/67] target-ppc: implement stxvll instructions David Gibson
@ 2017-01-12 2:02 ` David Gibson
2017-01-12 2:02 ` [Qemu-devel] [PULL 32/67] prep: do not use global variable to access nvram David Gibson
` (37 subsequent siblings)
68 siblings, 0 replies; 73+ messages in thread
From: David Gibson @ 2017-01-12 2:02 UTC (permalink / raw)
To: peter.maydell
Cc: agraf, qemu-ppc, qemu-devel, thuth, lvivier, aik, mdroth, David Gibson
From: Thomas Huth <thuth@redhat.com>
When passing through an USB storage device to a pseries guest, it
is currently not possible to automatically boot from the device
if the "bootindex" property has been specified, too (e.g. when using
"-device nec-usb-xhci -device usb-host,hostbus=1,hostaddr=2,bootindex=0"
at the command line). The problem is that QEMU builds a device tree path
like "/pci@800000020000000/usb@0/usb-host@1" and passes it to SLOF
in the /chosen/qemu,boot-list property. SLOF, however, probes the
USB device, recognizes that it is a storage device and thus changes
its name to "storage", and additionally adds a child node for the
SCSI LUN, so the correct boot path in SLOF is something like
"/pci@800000020000000/usb@0/storage@1/disk@101000000000000" instead.
So when we detect an USB mass storage device with SCSI interface,
we've got to adjust the firmware boot-device path properly that
SLOF can automatically boot from the device.
Buglink: https://bugzilla.redhat.com/show_bug.cgi?id=1354177
Signed-off-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/ppc/spapr.c | 13 +++++++++++++
hw/usb/host-libusb.c | 29 +++++++++++++++++++++++++++++
hw/usb/host-stub.c | 5 +++++
include/hw/usb.h | 1 +
4 files changed, 48 insertions(+)
diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
index cfadc46..31210b3 100644
--- a/hw/ppc/spapr.c
+++ b/hw/ppc/spapr.c
@@ -2198,6 +2198,19 @@ static char *spapr_get_fw_dev_path(FWPathProvider *p, BusState *bus,
}
}
+ /*
+ * SLOF probes the USB devices, and if it recognizes that the device is a
+ * storage device, it changes its name to "storage" instead of "usb-host",
+ * and additionally adds a child node for the SCSI LUN, so the correct
+ * boot path in SLOF is something like .../storage@1/disk@xxx" instead.
+ */
+ if (strcmp("usb-host", qdev_fw_name(dev)) == 0) {
+ USBDevice *usbdev = CAST(USBDevice, dev, TYPE_USB_DEVICE);
+ if (usb_host_dev_is_scsi_storage(usbdev)) {
+ return g_strdup_printf("storage@%s/disk", usbdev->port->path);
+ }
+ }
+
if (phb) {
/* Replace "pci" with "pci@800000020000000" */
return g_strdup_printf("pci@%"PRIX64, phb->buid);
diff --git a/hw/usb/host-libusb.c b/hw/usb/host-libusb.c
index bd81d71..7791c6d 100644
--- a/hw/usb/host-libusb.c
+++ b/hw/usb/host-libusb.c
@@ -1707,6 +1707,35 @@ static void usb_host_auto_check(void *unused)
timer_mod(usb_auto_timer, qemu_clock_get_ms(QEMU_CLOCK_REALTIME) + 2000);
}
+/**
+ * Check whether USB host device has a USB mass storage SCSI interface
+ */
+bool usb_host_dev_is_scsi_storage(USBDevice *ud)
+{
+ USBHostDevice *uhd = USB_HOST_DEVICE(ud);
+ struct libusb_config_descriptor *conf;
+ const struct libusb_interface_descriptor *intf;
+ bool is_scsi_storage = false;
+ int i;
+
+ if (!uhd || libusb_get_active_config_descriptor(uhd->dev, &conf) != 0) {
+ return false;
+ }
+
+ for (i = 0; i < conf->bNumInterfaces; i++) {
+ intf = &conf->interface[i].altsetting[ud->altsetting[i]];
+ if (intf->bInterfaceClass == LIBUSB_CLASS_MASS_STORAGE &&
+ intf->bInterfaceSubClass == 6) { /* 6 means SCSI */
+ is_scsi_storage = true;
+ break;
+ }
+ }
+
+ libusb_free_config_descriptor(conf);
+
+ return is_scsi_storage;
+}
+
void hmp_info_usbhost(Monitor *mon, const QDict *qdict)
{
libusb_device **devs = NULL;
diff --git a/hw/usb/host-stub.c b/hw/usb/host-stub.c
index 6ba65a1..d0268ba 100644
--- a/hw/usb/host-stub.c
+++ b/hw/usb/host-stub.c
@@ -46,3 +46,8 @@ USBDevice *usb_host_device_open(USBBus *bus, const char *devname)
{
return NULL;
}
+
+bool usb_host_dev_is_scsi_storage(USBDevice *ud)
+{
+ return false;
+}
diff --git a/include/hw/usb.h b/include/hw/usb.h
index 847c9de..43838c9 100644
--- a/include/hw/usb.h
+++ b/include/hw/usb.h
@@ -471,6 +471,7 @@ void usb_generic_async_ctrl_complete(USBDevice *s, USBPacket *p);
/* usb-linux.c */
USBDevice *usb_host_device_open(USBBus *bus, const char *devname);
void hmp_info_usbhost(Monitor *mon, const QDict *qdict);
+bool usb_host_dev_is_scsi_storage(USBDevice *usbdev);
/* usb ports of the VM */
--
2.9.3
^ permalink raw reply related [flat|nested] 73+ messages in thread
* [Qemu-devel] [PULL 32/67] prep: do not use global variable to access nvram
2017-01-12 2:02 [Qemu-devel] [PULL 00/67] ppc-for-2.9 queue 20170112 David Gibson
` (30 preceding siblings ...)
2017-01-12 2:02 ` [Qemu-devel] [PULL 31/67] hw/ppc/spapr: Fix boot path of usb-host storage devices David Gibson
@ 2017-01-12 2:02 ` David Gibson
2017-01-12 2:02 ` [Qemu-devel] [PULL 33/67] pseries: Add pseries-2.9 machine type David Gibson
` (36 subsequent siblings)
68 siblings, 0 replies; 73+ messages in thread
From: David Gibson @ 2017-01-12 2:02 UTC (permalink / raw)
To: peter.maydell
Cc: agraf, qemu-ppc, qemu-devel, thuth, lvivier, aik, mdroth,
Hervé Poussineau, David Gibson
From: Hervé Poussineau <hpoussin@reactos.org>
Signed-off-by: Hervé Poussineau <hpoussin@reactos.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/ppc/prep.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/ppc/prep.c b/hw/ppc/prep.c
index 054af1e..9fb89d3 100644
--- a/hw/ppc/prep.c
+++ b/hw/ppc/prep.c
@@ -339,13 +339,13 @@ static PortioList prep_port_list;
/* NVRAM helpers */
static inline uint32_t nvram_read(Nvram *nvram, uint32_t addr)
{
- NvramClass *k = NVRAM_GET_CLASS(sysctrl->nvram);
+ NvramClass *k = NVRAM_GET_CLASS(nvram);
return (k->read)(nvram, addr);
}
static inline void nvram_write(Nvram *nvram, uint32_t addr, uint32_t val)
{
- NvramClass *k = NVRAM_GET_CLASS(sysctrl->nvram);
+ NvramClass *k = NVRAM_GET_CLASS(nvram);
(k->write)(nvram, addr, val);
}
--
2.9.3
^ permalink raw reply related [flat|nested] 73+ messages in thread
* [Qemu-devel] [PULL 33/67] pseries: Add pseries-2.9 machine type
2017-01-12 2:02 [Qemu-devel] [PULL 00/67] ppc-for-2.9 queue 20170112 David Gibson
` (31 preceding siblings ...)
2017-01-12 2:02 ` [Qemu-devel] [PULL 32/67] prep: do not use global variable to access nvram David Gibson
@ 2017-01-12 2:02 ` David Gibson
2017-01-12 2:02 ` [Qemu-devel] [PULL 34/67] ppc: Rewrite ppc_set_compat() David Gibson
` (35 subsequent siblings)
68 siblings, 0 replies; 73+ messages in thread
From: David Gibson @ 2017-01-12 2:02 UTC (permalink / raw)
To: peter.maydell
Cc: agraf, qemu-ppc, qemu-devel, thuth, lvivier, aik, mdroth, David Gibson
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Laurent Vivier <lvivier@redhat.com>
---
hw/ppc/spapr.c | 23 +++++++++++++++++++++--
1 file changed, 21 insertions(+), 2 deletions(-)
diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
index 31210b3..fcaa2a5 100644
--- a/hw/ppc/spapr.c
+++ b/hw/ppc/spapr.c
@@ -2774,18 +2774,37 @@ static const TypeInfo spapr_machine_info = {
type_init(spapr_machine_register_##suffix)
/*
+ * pseries-2.9
+ */
+static void spapr_machine_2_9_instance_options(MachineState *machine)
+{
+}
+
+static void spapr_machine_2_9_class_options(MachineClass *mc)
+{
+ /* Defaults for the latest behaviour inherited from the base class */
+}
+
+DEFINE_SPAPR_MACHINE(2_9, "2.9", true);
+
+/*
* pseries-2.8
*/
+#define SPAPR_COMPAT_2_8 \
+ HW_COMPAT_2_8
+
static void spapr_machine_2_8_instance_options(MachineState *machine)
{
+ spapr_machine_2_9_instance_options(machine);
}
static void spapr_machine_2_8_class_options(MachineClass *mc)
{
- /* Defaults for the latest behaviour inherited from the base class */
+ spapr_machine_2_9_class_options(mc);
+ SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_8);
}
-DEFINE_SPAPR_MACHINE(2_8, "2.8", true);
+DEFINE_SPAPR_MACHINE(2_8, "2.8", false);
/*
* pseries-2.7
--
2.9.3
^ permalink raw reply related [flat|nested] 73+ messages in thread
* [Qemu-devel] [PULL 34/67] ppc: Rewrite ppc_set_compat()
2017-01-12 2:02 [Qemu-devel] [PULL 00/67] ppc-for-2.9 queue 20170112 David Gibson
` (32 preceding siblings ...)
2017-01-12 2:02 ` [Qemu-devel] [PULL 33/67] pseries: Add pseries-2.9 machine type David Gibson
@ 2017-01-12 2:02 ` David Gibson
2017-01-12 2:02 ` [Qemu-devel] [PULL 35/67] ppc: Rewrite ppc_get_compat_smt_threads() David Gibson
` (34 subsequent siblings)
68 siblings, 0 replies; 73+ messages in thread
From: David Gibson @ 2017-01-12 2:02 UTC (permalink / raw)
To: peter.maydell
Cc: agraf, qemu-ppc, qemu-devel, thuth, lvivier, aik, mdroth, David Gibson
This rewrites the ppc_set_compat() function so that instead of open coding
the various compatibility modes, it reads the relevant data from a table.
This is a first step in consolidating the information on compatibility
modes scattered across the code into a single place.
It also makes one change to the logic. The old code masked the bits
to be set in the PCR (Processor Compatibility Register) by which bits
are valid on the host CPU. This made no sense, since it was done
regardless of whether our guest CPU was the same as the host CPU or
not. Furthermore, the actual PCR bits are only relevant for TCG[1] -
KVM instead uses the compatibility mode we tell it in
kvmppc_set_compat(). When using TCG host cpu information usually
isn't even present.
While we're at it, we put the new implementation in a new file to make the
enormous translate_init.c a little smaller.
[1] Actually it doesn't even do anything in TCG, but it will if / when we
get to implementing compatibility mode logic at that level.
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Reviewed-by: Alexey Kardashevskiy <aik@ozlabs.ru>
---
target/ppc/Makefile.objs | 2 +-
target/ppc/compat.c | 91 +++++++++++++++++++++++++++++++++++++++++++++
target/ppc/cpu.h | 6 ++-
target/ppc/translate_init.c | 41 --------------------
4 files changed, 97 insertions(+), 43 deletions(-)
create mode 100644 target/ppc/compat.c
diff --git a/target/ppc/Makefile.objs b/target/ppc/Makefile.objs
index e667e69..a8c7a30 100644
--- a/target/ppc/Makefile.objs
+++ b/target/ppc/Makefile.objs
@@ -2,7 +2,7 @@ obj-y += cpu-models.o
obj-y += translate.o
ifeq ($(CONFIG_SOFTMMU),y)
obj-y += machine.o mmu_helper.o mmu-hash32.o monitor.o
-obj-$(TARGET_PPC64) += mmu-hash64.o arch_dump.o
+obj-$(TARGET_PPC64) += mmu-hash64.o arch_dump.o compat.o
endif
obj-$(CONFIG_KVM) += kvm.o
obj-$(call lnot,$(CONFIG_KVM)) += kvm-stub.o
diff --git a/target/ppc/compat.c b/target/ppc/compat.c
new file mode 100644
index 0000000..f3fd9c6
--- /dev/null
+++ b/target/ppc/compat.c
@@ -0,0 +1,91 @@
+/*
+ * PowerPC CPU initialization for qemu.
+ *
+ * Copyright 2016, David Gibson, Red Hat Inc. <dgibson@redhat.com>
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "qemu/osdep.h"
+#include "sysemu/kvm.h"
+#include "kvm_ppc.h"
+#include "sysemu/cpus.h"
+#include "qemu/error-report.h"
+#include "qapi/error.h"
+#include "cpu-models.h"
+
+typedef struct {
+ uint32_t pvr;
+ uint64_t pcr;
+} CompatInfo;
+
+static const CompatInfo compat_table[] = {
+ { /* POWER6, ISA2.05 */
+ .pvr = CPU_POWERPC_LOGICAL_2_05,
+ .pcr = PCR_COMPAT_2_07 | PCR_COMPAT_2_06 | PCR_COMPAT_2_05
+ | PCR_TM_DIS | PCR_VSX_DIS,
+ },
+ { /* POWER7, ISA2.06 */
+ .pvr = CPU_POWERPC_LOGICAL_2_06,
+ .pcr = PCR_COMPAT_2_07 | PCR_COMPAT_2_06 | PCR_TM_DIS,
+ },
+ {
+ .pvr = CPU_POWERPC_LOGICAL_2_06_PLUS,
+ .pcr = PCR_COMPAT_2_07 | PCR_COMPAT_2_06 | PCR_TM_DIS,
+ },
+ { /* POWER8, ISA2.07 */
+ .pvr = CPU_POWERPC_LOGICAL_2_07,
+ .pcr = PCR_COMPAT_2_07,
+ },
+};
+
+static const CompatInfo *compat_by_pvr(uint32_t pvr)
+{
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(compat_table); i++) {
+ if (compat_table[i].pvr == pvr) {
+ return &compat_table[i];
+ }
+ }
+ return NULL;
+}
+
+void ppc_set_compat(PowerPCCPU *cpu, uint32_t compat_pvr, Error **errp)
+{
+ const CompatInfo *compat = compat_by_pvr(compat_pvr);
+ CPUPPCState *env = &cpu->env;
+ PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
+ uint64_t pcr;
+
+ if (!compat_pvr) {
+ pcr = 0;
+ } else if (!compat) {
+ error_setg(errp, "Unknown compatibility PVR 0x%08"PRIx32, compat_pvr);
+ return;
+ } else {
+ pcr = compat->pcr;
+ }
+
+ cpu->compat_pvr = compat_pvr;
+ env->spr[SPR_PCR] = pcr & pcc->pcr_mask;
+
+ if (kvm_enabled()) {
+ int ret = kvmppc_set_compat(cpu, cpu->compat_pvr);
+ if (ret < 0) {
+ error_setg_errno(errp, -ret,
+ "Unable to set CPU compatibility mode in KVM");
+ }
+ }
+}
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index b62f775..c859547 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -1252,7 +1252,6 @@ void ppc_store_msr (CPUPPCState *env, target_ulong value);
void ppc_cpu_list (FILE *f, fprintf_function cpu_fprintf);
int ppc_get_compat_smt_threads(PowerPCCPU *cpu);
#if defined(TARGET_PPC64)
-void ppc_set_compat(PowerPCCPU *cpu, uint32_t compat_pvr, Error **errp);
#endif
/* Time-base and decrementer management */
@@ -1323,6 +1322,11 @@ static inline int cpu_mmu_index (CPUPPCState *env, bool ifetch)
return ifetch ? env->immu_idx : env->dmmu_idx;
}
+/* Compatibility modes */
+#if defined(TARGET_PPC64)
+void ppc_set_compat(PowerPCCPU *cpu, uint32_t compat_pvr, Error **errp);
+#endif /* defined(TARGET_PPC64) */
+
#include "exec/cpu-all.h"
/*****************************************************************************/
diff --git a/target/ppc/translate_init.c b/target/ppc/translate_init.c
index 60552c1..abdb842 100644
--- a/target/ppc/translate_init.c
+++ b/target/ppc/translate_init.c
@@ -9972,47 +9972,6 @@ int ppc_get_compat_smt_threads(PowerPCCPU *cpu)
return ret;
}
-#ifdef TARGET_PPC64
-void ppc_set_compat(PowerPCCPU *cpu, uint32_t compat_pvr, Error **errp)
-{
- int ret = 0;
- CPUPPCState *env = &cpu->env;
- PowerPCCPUClass *host_pcc;
-
- cpu->compat_pvr = compat_pvr;
-
- switch (compat_pvr) {
- case CPU_POWERPC_LOGICAL_2_05:
- env->spr[SPR_PCR] = PCR_TM_DIS | PCR_VSX_DIS | PCR_COMPAT_2_07 |
- PCR_COMPAT_2_06 | PCR_COMPAT_2_05;
- break;
- case CPU_POWERPC_LOGICAL_2_06:
- case CPU_POWERPC_LOGICAL_2_06_PLUS:
- env->spr[SPR_PCR] = PCR_TM_DIS | PCR_COMPAT_2_07 | PCR_COMPAT_2_06;
- break;
- case CPU_POWERPC_LOGICAL_2_07:
- env->spr[SPR_PCR] = PCR_COMPAT_2_07;
- break;
- default:
- env->spr[SPR_PCR] = 0;
- break;
- }
-
- host_pcc = kvm_ppc_get_host_cpu_class();
- if (host_pcc) {
- env->spr[SPR_PCR] &= host_pcc->pcr_mask;
- }
-
- if (kvm_enabled()) {
- ret = kvmppc_set_compat(cpu, cpu->compat_pvr);
- if (ret < 0) {
- error_setg_errno(errp, -ret,
- "Unable to set CPU compatibility mode in KVM");
- }
- }
-}
-#endif
-
static gint ppc_cpu_compare_class_pvr(gconstpointer a, gconstpointer b)
{
ObjectClass *oc = (ObjectClass *)a;
--
2.9.3
^ permalink raw reply related [flat|nested] 73+ messages in thread
* [Qemu-devel] [PULL 35/67] ppc: Rewrite ppc_get_compat_smt_threads()
2017-01-12 2:02 [Qemu-devel] [PULL 00/67] ppc-for-2.9 queue 20170112 David Gibson
` (33 preceding siblings ...)
2017-01-12 2:02 ` [Qemu-devel] [PULL 34/67] ppc: Rewrite ppc_set_compat() David Gibson
@ 2017-01-12 2:02 ` David Gibson
2017-01-12 2:02 ` [Qemu-devel] [PULL 36/67] ppc: Validate compatibility modes when setting David Gibson
` (33 subsequent siblings)
68 siblings, 0 replies; 73+ messages in thread
From: David Gibson @ 2017-01-12 2:02 UTC (permalink / raw)
To: peter.maydell
Cc: agraf, qemu-ppc, qemu-devel, thuth, lvivier, aik, mdroth, David Gibson
To continue consolidation of compatibility mode information, this rewrites
the ppc_get_compat_smt_threads() function using the table of compatiblity
modes in target-ppc/compat.c.
It's not a direct replacement, the new ppc_compat_max_threads() function
has simpler semantics - it just returns the number of threads the cpu
model has, taking into account any compatiblity mode it is in.
This no longer takes into account kvmppc_smt_threads() as the previous
version did. That check wasn't useful because we check in
ppc_cpu_realizefn() that CPUs aren't instantiated with more threads
than kvm allows (or if we didn't things will already be broken and
this won't make it any worse).
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Reviewed-by: Alexey Kardashevskiy <aik@ozlabs.ru>
---
hw/ppc/spapr.c | 8 ++++----
target/ppc/compat.c | 18 ++++++++++++++++++
target/ppc/cpu.h | 2 +-
target/ppc/translate_init.c | 20 --------------------
4 files changed, 23 insertions(+), 25 deletions(-)
diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
index fcaa2a5..70dffcb 100644
--- a/hw/ppc/spapr.c
+++ b/hw/ppc/spapr.c
@@ -206,6 +206,7 @@ static int spapr_fixup_cpu_dt(void *fdt, sPAPRMachineState *spapr)
PowerPCCPU *cpu = POWERPC_CPU(cs);
DeviceClass *dc = DEVICE_GET_CLASS(cs);
int index = ppc_get_vcpu_dt_id(cpu);
+ int compat_smt = MIN(smp_threads, ppc_compat_max_threads(cpu));
if ((index % smt) != 0) {
continue;
@@ -240,8 +241,7 @@ static int spapr_fixup_cpu_dt(void *fdt, sPAPRMachineState *spapr)
return ret;
}
- ret = spapr_fixup_cpu_smt_dt(fdt, offset, cpu,
- ppc_get_compat_smt_threads(cpu));
+ ret = spapr_fixup_cpu_smt_dt(fdt, offset, cpu, compat_smt);
if (ret < 0) {
return ret;
}
@@ -407,6 +407,7 @@ static void spapr_populate_cpu_dt(CPUState *cs, void *fdt, int offset,
size_t page_sizes_prop_size;
uint32_t vcpus_per_socket = smp_threads * smp_cores;
uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)};
+ int compat_smt = MIN(smp_threads, ppc_compat_max_threads(cpu));
sPAPRDRConnector *drc;
sPAPRDRConnectorClass *drck;
int drc_index;
@@ -494,8 +495,7 @@ static void spapr_populate_cpu_dt(CPUState *cs, void *fdt, int offset,
_FDT(spapr_fixup_cpu_numa_dt(fdt, offset, cs));
- _FDT(spapr_fixup_cpu_smt_dt(fdt, offset, cpu,
- ppc_get_compat_smt_threads(cpu)));
+ _FDT(spapr_fixup_cpu_smt_dt(fdt, offset, cpu, compat_smt));
}
static void spapr_populate_cpus_dt_node(void *fdt, sPAPRMachineState *spapr)
diff --git a/target/ppc/compat.c b/target/ppc/compat.c
index f3fd9c6..66529a6 100644
--- a/target/ppc/compat.c
+++ b/target/ppc/compat.c
@@ -28,6 +28,7 @@
typedef struct {
uint32_t pvr;
uint64_t pcr;
+ int max_threads;
} CompatInfo;
static const CompatInfo compat_table[] = {
@@ -35,18 +36,22 @@ static const CompatInfo compat_table[] = {
.pvr = CPU_POWERPC_LOGICAL_2_05,
.pcr = PCR_COMPAT_2_07 | PCR_COMPAT_2_06 | PCR_COMPAT_2_05
| PCR_TM_DIS | PCR_VSX_DIS,
+ .max_threads = 2,
},
{ /* POWER7, ISA2.06 */
.pvr = CPU_POWERPC_LOGICAL_2_06,
.pcr = PCR_COMPAT_2_07 | PCR_COMPAT_2_06 | PCR_TM_DIS,
+ .max_threads = 4,
},
{
.pvr = CPU_POWERPC_LOGICAL_2_06_PLUS,
.pcr = PCR_COMPAT_2_07 | PCR_COMPAT_2_06 | PCR_TM_DIS,
+ .max_threads = 4,
},
{ /* POWER8, ISA2.07 */
.pvr = CPU_POWERPC_LOGICAL_2_07,
.pcr = PCR_COMPAT_2_07,
+ .max_threads = 8,
},
};
@@ -89,3 +94,16 @@ void ppc_set_compat(PowerPCCPU *cpu, uint32_t compat_pvr, Error **errp)
}
}
}
+
+int ppc_compat_max_threads(PowerPCCPU *cpu)
+{
+ const CompatInfo *compat = compat_by_pvr(cpu->compat_pvr);
+ int n_threads = CPU(cpu)->nr_threads;
+
+ if (cpu->compat_pvr) {
+ g_assert(compat);
+ n_threads = MIN(n_threads, compat->max_threads);
+ }
+
+ return n_threads;
+}
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index c859547..cd76053 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -1250,7 +1250,6 @@ void ppc_store_sdr1 (CPUPPCState *env, target_ulong value);
void ppc_store_msr (CPUPPCState *env, target_ulong value);
void ppc_cpu_list (FILE *f, fprintf_function cpu_fprintf);
-int ppc_get_compat_smt_threads(PowerPCCPU *cpu);
#if defined(TARGET_PPC64)
#endif
@@ -1325,6 +1324,7 @@ static inline int cpu_mmu_index (CPUPPCState *env, bool ifetch)
/* Compatibility modes */
#if defined(TARGET_PPC64)
void ppc_set_compat(PowerPCCPU *cpu, uint32_t compat_pvr, Error **errp);
+int ppc_compat_max_threads(PowerPCCPU *cpu);
#endif /* defined(TARGET_PPC64) */
#include "exec/cpu-all.h"
diff --git a/target/ppc/translate_init.c b/target/ppc/translate_init.c
index abdb842..953d27d 100644
--- a/target/ppc/translate_init.c
+++ b/target/ppc/translate_init.c
@@ -9952,26 +9952,6 @@ static void ppc_cpu_unrealizefn(DeviceState *dev, Error **errp)
}
}
-int ppc_get_compat_smt_threads(PowerPCCPU *cpu)
-{
- CPUState *cs = CPU(cpu);
- int ret = MIN(cs->nr_threads, kvmppc_smt_threads());
-
- switch (cpu->compat_pvr) {
- case CPU_POWERPC_LOGICAL_2_05:
- ret = MIN(ret, 2);
- break;
- case CPU_POWERPC_LOGICAL_2_06:
- ret = MIN(ret, 4);
- break;
- case CPU_POWERPC_LOGICAL_2_07:
- ret = MIN(ret, 8);
- break;
- }
-
- return ret;
-}
-
static gint ppc_cpu_compare_class_pvr(gconstpointer a, gconstpointer b)
{
ObjectClass *oc = (ObjectClass *)a;
--
2.9.3
^ permalink raw reply related [flat|nested] 73+ messages in thread
* [Qemu-devel] [PULL 36/67] ppc: Validate compatibility modes when setting
2017-01-12 2:02 [Qemu-devel] [PULL 00/67] ppc-for-2.9 queue 20170112 David Gibson
` (34 preceding siblings ...)
2017-01-12 2:02 ` [Qemu-devel] [PULL 35/67] ppc: Rewrite ppc_get_compat_smt_threads() David Gibson
@ 2017-01-12 2:02 ` David Gibson
2017-01-12 2:02 ` [Qemu-devel] [PULL 37/67] qtest: add netfilter tests for ppc64 David Gibson
` (32 subsequent siblings)
68 siblings, 0 replies; 73+ messages in thread
From: David Gibson @ 2017-01-12 2:02 UTC (permalink / raw)
To: peter.maydell
Cc: agraf, qemu-ppc, qemu-devel, thuth, lvivier, aik, mdroth, David Gibson
Current ppc_set_compat() will attempt to set any compatiblity mode
specified, regardless of whether it's available on the CPU. The caller is
expected to make sure it is setting a possible mode, which is awkwward
because most of the information to make that decision is at the CPU level.
This begins to clean this up by introducing a ppc_check_compat() function
which will determine if a given compatiblity mode is supported on a CPU
(and also whether it lies within specified minimum and maximum compat
levels, which will be useful later). It also contains an assertion that
the CPU has a "virtual hypervisor"[1], that is, that the guest isn't
permitted to execute hypervisor privilege code. Without that, the guest
would own the PCR and so could override any mode set here. Only machine
types which use a virtual hypervisor (i.e. 'pseries') should use
ppc_check_compat().
ppc_set_compat() is modified to validate the compatibility mode it is given
and fail if it's not available on this CPU.
[1] Or user-only mode, which also obviously doesn't allow access to the
hypervisor privileged PCR. We don't use that now, but could in future.
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Reviewed-by: Alexey Kardashevskiy <aik@ozlabs.ru>
---
target/ppc/compat.c | 41 +++++++++++++++++++++++++++++++++++++++++
target/ppc/cpu.h | 2 ++
2 files changed, 43 insertions(+)
diff --git a/target/ppc/compat.c b/target/ppc/compat.c
index 66529a6..1059555 100644
--- a/target/ppc/compat.c
+++ b/target/ppc/compat.c
@@ -28,29 +28,37 @@
typedef struct {
uint32_t pvr;
uint64_t pcr;
+ uint64_t pcr_level;
int max_threads;
} CompatInfo;
static const CompatInfo compat_table[] = {
+ /*
+ * Ordered from oldest to newest - the code relies on this
+ */
{ /* POWER6, ISA2.05 */
.pvr = CPU_POWERPC_LOGICAL_2_05,
.pcr = PCR_COMPAT_2_07 | PCR_COMPAT_2_06 | PCR_COMPAT_2_05
| PCR_TM_DIS | PCR_VSX_DIS,
+ .pcr_level = PCR_COMPAT_2_05,
.max_threads = 2,
},
{ /* POWER7, ISA2.06 */
.pvr = CPU_POWERPC_LOGICAL_2_06,
.pcr = PCR_COMPAT_2_07 | PCR_COMPAT_2_06 | PCR_TM_DIS,
+ .pcr_level = PCR_COMPAT_2_06,
.max_threads = 4,
},
{
.pvr = CPU_POWERPC_LOGICAL_2_06_PLUS,
.pcr = PCR_COMPAT_2_07 | PCR_COMPAT_2_06 | PCR_TM_DIS,
+ .pcr_level = PCR_COMPAT_2_06,
.max_threads = 4,
},
{ /* POWER8, ISA2.07 */
.pvr = CPU_POWERPC_LOGICAL_2_07,
.pcr = PCR_COMPAT_2_07,
+ .pcr_level = PCR_COMPAT_2_07,
.max_threads = 8,
},
};
@@ -67,6 +75,35 @@ static const CompatInfo *compat_by_pvr(uint32_t pvr)
return NULL;
}
+bool ppc_check_compat(PowerPCCPU *cpu, uint32_t compat_pvr,
+ uint32_t min_compat_pvr, uint32_t max_compat_pvr)
+{
+ PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
+ const CompatInfo *compat = compat_by_pvr(compat_pvr);
+ const CompatInfo *min = compat_by_pvr(min_compat_pvr);
+ const CompatInfo *max = compat_by_pvr(max_compat_pvr);
+
+#if !defined(CONFIG_USER_ONLY)
+ g_assert(cpu->vhyp);
+#endif
+ g_assert(!min_compat_pvr || min);
+ g_assert(!max_compat_pvr || max);
+
+ if (!compat) {
+ /* Not a recognized logical PVR */
+ return false;
+ }
+ if ((min && (compat < min)) || (max && (compat > max))) {
+ /* Outside specified range */
+ return false;
+ }
+ if (!(pcc->pcr_supported & compat->pcr_level)) {
+ /* Not supported by this CPU */
+ return false;
+ }
+ return true;
+}
+
void ppc_set_compat(PowerPCCPU *cpu, uint32_t compat_pvr, Error **errp)
{
const CompatInfo *compat = compat_by_pvr(compat_pvr);
@@ -79,6 +116,10 @@ void ppc_set_compat(PowerPCCPU *cpu, uint32_t compat_pvr, Error **errp)
} else if (!compat) {
error_setg(errp, "Unknown compatibility PVR 0x%08"PRIx32, compat_pvr);
return;
+ } else if (!ppc_check_compat(cpu, compat_pvr, 0, 0)) {
+ error_setg(errp, "Compatibility PVR 0x%08"PRIx32" not valid for CPU",
+ compat_pvr);
+ return;
} else {
pcr = compat->pcr;
}
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index cd76053..22842dd 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -1323,6 +1323,8 @@ static inline int cpu_mmu_index (CPUPPCState *env, bool ifetch)
/* Compatibility modes */
#if defined(TARGET_PPC64)
+bool ppc_check_compat(PowerPCCPU *cpu, uint32_t compat_pvr,
+ uint32_t min_compat_pvr, uint32_t max_compat_pvr);
void ppc_set_compat(PowerPCCPU *cpu, uint32_t compat_pvr, Error **errp);
int ppc_compat_max_threads(PowerPCCPU *cpu);
#endif /* defined(TARGET_PPC64) */
--
2.9.3
^ permalink raw reply related [flat|nested] 73+ messages in thread
* [Qemu-devel] [PULL 37/67] qtest: add netfilter tests for ppc64
2017-01-12 2:02 [Qemu-devel] [PULL 00/67] ppc-for-2.9 queue 20170112 David Gibson
` (35 preceding siblings ...)
2017-01-12 2:02 ` [Qemu-devel] [PULL 36/67] ppc: Validate compatibility modes when setting David Gibson
@ 2017-01-12 2:02 ` David Gibson
2017-01-12 2:02 ` [Qemu-devel] [PULL 38/67] qtest: add display-vga-test to ppc64 David Gibson
` (31 subsequent siblings)
68 siblings, 0 replies; 73+ messages in thread
From: David Gibson @ 2017-01-12 2:02 UTC (permalink / raw)
To: peter.maydell
Cc: agraf, qemu-ppc, qemu-devel, thuth, lvivier, aik, mdroth, David Gibson
From: Laurent Vivier <lvivier@redhat.com>
Signed-off-by: Laurent Vivier <lvivier@redhat.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Greg Kurz <groug@kaod.org>
Tested-by: Greg Kurz <groug@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
tests/Makefile.include | 3 +++
1 file changed, 3 insertions(+)
diff --git a/tests/Makefile.include b/tests/Makefile.include
index f776404..08ddf59 100644
--- a/tests/Makefile.include
+++ b/tests/Makefile.include
@@ -284,6 +284,9 @@ gcov-files-ppc64-y += hw/usb/hcd-uhci.c
check-qtest-ppc64-y += tests/usb-hcd-xhci-test$(EXESUF)
gcov-files-ppc64-y += hw/usb/hcd-xhci.c
check-qtest-ppc64-y += $(check-qtest-virtio-y)
+check-qtest-ppc64-y += tests/test-netfilter$(EXESUF)
+check-qtest-ppc64-y += tests/test-filter-mirror$(EXESUF)
+check-qtest-ppc64-y += tests/test-filter-redirector$(EXESUF)
check-qtest-sh4-y = tests/endianness-test$(EXESUF)
--
2.9.3
^ permalink raw reply related [flat|nested] 73+ messages in thread
* [Qemu-devel] [PULL 38/67] qtest: add display-vga-test to ppc64
2017-01-12 2:02 [Qemu-devel] [PULL 00/67] ppc-for-2.9 queue 20170112 David Gibson
` (36 preceding siblings ...)
2017-01-12 2:02 ` [Qemu-devel] [PULL 37/67] qtest: add netfilter tests for ppc64 David Gibson
@ 2017-01-12 2:02 ` David Gibson
2017-01-12 2:02 ` [Qemu-devel] [PULL 39/67] libqos: fix spapr qpci_map() David Gibson
` (30 subsequent siblings)
68 siblings, 0 replies; 73+ messages in thread
From: David Gibson @ 2017-01-12 2:02 UTC (permalink / raw)
To: peter.maydell
Cc: agraf, qemu-ppc, qemu-devel, thuth, lvivier, aik, mdroth, David Gibson
From: Laurent Vivier <lvivier@redhat.com>
Only enable for ppc64 in the Makefile, but added
code in the file to check cirrus card only on architectures
supporting it (alpha, mips, i386, x86_64).
Signed-off-by: Laurent Vivier <lvivier@redhat.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Greg Kurz <groug@kaod.org>
Tested-by: Greg Kurz <groug@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
tests/Makefile.include | 1 +
tests/display-vga-test.c | 7 ++++++-
2 files changed, 7 insertions(+), 1 deletion(-)
diff --git a/tests/Makefile.include b/tests/Makefile.include
index 08ddf59..6ed78b8 100644
--- a/tests/Makefile.include
+++ b/tests/Makefile.include
@@ -287,6 +287,7 @@ check-qtest-ppc64-y += $(check-qtest-virtio-y)
check-qtest-ppc64-y += tests/test-netfilter$(EXESUF)
check-qtest-ppc64-y += tests/test-filter-mirror$(EXESUF)
check-qtest-ppc64-y += tests/test-filter-redirector$(EXESUF)
+check-qtest-ppc64-y += tests/display-vga-test$(EXESUF)
check-qtest-sh4-y = tests/endianness-test$(EXESUF)
diff --git a/tests/display-vga-test.c b/tests/display-vga-test.c
index 9146021..2d7d24e 100644
--- a/tests/display-vga-test.c
+++ b/tests/display-vga-test.c
@@ -50,9 +50,14 @@ static void pci_virtio_vga(void)
int main(int argc, char **argv)
{
+ const char *arch = qtest_get_arch();
+
g_test_init(&argc, &argv, NULL);
- qtest_add_func("/display/pci/cirrus", pci_cirrus);
+ if (strcmp(arch, "alpha") == 0 || strcmp(arch, "i386") == 0 ||
+ strcmp(arch, "mips") == 0 || strcmp(arch, "x86_64") == 0) {
+ qtest_add_func("/display/pci/cirrus", pci_cirrus);
+ }
qtest_add_func("/display/pci/stdvga", pci_stdvga);
qtest_add_func("/display/pci/secondary", pci_secondary);
qtest_add_func("/display/pci/multihead", pci_multihead);
--
2.9.3
^ permalink raw reply related [flat|nested] 73+ messages in thread
* [Qemu-devel] [PULL 39/67] libqos: fix spapr qpci_map()
2017-01-12 2:02 [Qemu-devel] [PULL 00/67] ppc-for-2.9 queue 20170112 David Gibson
` (37 preceding siblings ...)
2017-01-12 2:02 ` [Qemu-devel] [PULL 38/67] qtest: add display-vga-test to ppc64 David Gibson
@ 2017-01-12 2:02 ` David Gibson
2017-01-12 2:03 ` [Qemu-devel] [PULL 40/67] qtest: convert ivshmem-test to use libqos David Gibson
` (29 subsequent siblings)
68 siblings, 0 replies; 73+ messages in thread
From: David Gibson @ 2017-01-12 2:02 UTC (permalink / raw)
To: peter.maydell
Cc: agraf, qemu-ppc, qemu-devel, thuth, lvivier, aik, mdroth, David Gibson
From: Laurent Vivier <lvivier@redhat.com>
Signed-off-by: Laurent Vivier <lvivier@redhat.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
tests/libqos/pci-spapr.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/tests/libqos/pci-spapr.c b/tests/libqos/pci-spapr.c
index 1e5d015..2043f1e 100644
--- a/tests/libqos/pci-spapr.c
+++ b/tests/libqos/pci-spapr.c
@@ -193,8 +193,8 @@ QPCIBus *qpci_init_spapr(QGuestAllocator *alloc)
ret->pio.size = SPAPR_PCI_IO_WIN_SIZE;
/* 32-bit portion of the MMIO window is at PCI address 2..4 GiB */
- ret->mmio32_cpu_base = SPAPR_PCI_BASE + SPAPR_PCI_MMIO32_WIN_SIZE;
- ret->mmio32.pci_base = 0x80000000; /* 2 GiB */
+ ret->mmio32_cpu_base = SPAPR_PCI_BASE;
+ ret->mmio32.pci_base = SPAPR_PCI_MMIO32_WIN_SIZE;
ret->mmio32.size = SPAPR_PCI_MMIO32_WIN_SIZE;
ret->bus.pio_alloc_ptr = 0xc000;
--
2.9.3
^ permalink raw reply related [flat|nested] 73+ messages in thread
* [Qemu-devel] [PULL 40/67] qtest: convert ivshmem-test to use libqos
2017-01-12 2:02 [Qemu-devel] [PULL 00/67] ppc-for-2.9 queue 20170112 David Gibson
` (38 preceding siblings ...)
2017-01-12 2:02 ` [Qemu-devel] [PULL 39/67] libqos: fix spapr qpci_map() David Gibson
@ 2017-01-12 2:03 ` David Gibson
2017-01-12 2:03 ` [Qemu-devel] [PULL 41/67] qtest: add ivshmem-test for ppc64 David Gibson
` (28 subsequent siblings)
68 siblings, 0 replies; 73+ messages in thread
From: David Gibson @ 2017-01-12 2:03 UTC (permalink / raw)
To: peter.maydell
Cc: agraf, qemu-ppc, qemu-devel, thuth, lvivier, aik, mdroth, David Gibson
From: Laurent Vivier <lvivier@redhat.com>
This will allow to use it with ppc64.
Signed-off-by: Laurent Vivier <lvivier@redhat.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
tests/ivshmem-test.c | 31 +++++++++++++++++--------------
1 file changed, 17 insertions(+), 14 deletions(-)
diff --git a/tests/ivshmem-test.c b/tests/ivshmem-test.c
index 04a5c5d..8095d72 100644
--- a/tests/ivshmem-test.c
+++ b/tests/ivshmem-test.c
@@ -11,7 +11,7 @@
#include "qemu/osdep.h"
#include <glib/gstdio.h>
#include "contrib/ivshmem-server/ivshmem-server.h"
-#include "libqos/pci-pc.h"
+#include "libqos/libqos-pc.h"
#include "libqtest.h"
#include "qemu-common.h"
@@ -40,9 +40,8 @@ static QPCIDevice *get_device(QPCIBus *pcibus)
}
typedef struct _IVState {
- QTestState *qtest;
+ QOSState *qs;
QPCIBar reg_bar, mem_bar;
- QPCIBus *pcibus;
QPCIDevice *dev;
} IVState;
@@ -74,7 +73,7 @@ static inline unsigned in_reg(IVState *s, enum Reg reg)
QTestState *qtest = global_qtest;
unsigned res;
- global_qtest = s->qtest;
+ global_qtest = s->qs->qts;
res = qpci_io_readl(s->dev, s->reg_bar, reg);
g_test_message("*%s -> %x\n", name, res);
global_qtest = qtest;
@@ -87,7 +86,7 @@ static inline void out_reg(IVState *s, enum Reg reg, unsigned v)
const char *name = reg2str(reg);
QTestState *qtest = global_qtest;
- global_qtest = s->qtest;
+ global_qtest = s->qs->qts;
g_test_message("%x -> *%s\n", v, name);
qpci_io_writel(s->dev, s->reg_bar, reg, v);
global_qtest = qtest;
@@ -97,7 +96,7 @@ static inline void read_mem(IVState *s, uint64_t off, void *buf, size_t len)
{
QTestState *qtest = global_qtest;
- global_qtest = s->qtest;
+ global_qtest = s->qs->qts;
qpci_memread(s->dev, s->mem_bar, off, buf, len);
global_qtest = qtest;
}
@@ -107,7 +106,7 @@ static inline void write_mem(IVState *s, uint64_t off,
{
QTestState *qtest = global_qtest;
- global_qtest = s->qtest;
+ global_qtest = s->qs->qts;
qpci_memwrite(s->dev, s->mem_bar, off, buf, len);
global_qtest = qtest;
}
@@ -115,17 +114,21 @@ static inline void write_mem(IVState *s, uint64_t off,
static void cleanup_vm(IVState *s)
{
g_free(s->dev);
- qpci_free_pc(s->pcibus);
- qtest_quit(s->qtest);
+ qtest_shutdown(s->qs);
}
static void setup_vm_cmd(IVState *s, const char *cmd, bool msix)
{
uint64_t barsize;
+ const char *arch = qtest_get_arch();
- s->qtest = qtest_start(cmd);
- s->pcibus = qpci_init_pc(NULL);
- s->dev = get_device(s->pcibus);
+ if (strcmp(arch, "i386") == 0 || strcmp(arch, "x86_64") == 0) {
+ s->qs = qtest_pc_boot(cmd);
+ } else {
+ g_printerr("ivshmem-test tests are only available on x86\n");
+ exit(EXIT_FAILURE);
+ }
+ s->dev = get_device(s->qs->pcibus);
s->reg_bar = qpci_iomap(s->dev, 0, &barsize);
g_assert_cmpuint(barsize, ==, 256);
@@ -347,7 +350,7 @@ static void test_ivshmem_server(bool msi)
g_assert_cmpint(vm1, !=, vm2);
/* check number of MSI-X vectors */
- global_qtest = s1->qtest;
+ global_qtest = s1->qs->qts;
if (msi) {
ret = qpci_msix_table_size(s1->dev);
g_assert_cmpuint(ret, ==, nvectors);
@@ -370,7 +373,7 @@ static void test_ivshmem_server(bool msi)
g_assert_cmpuint(ret, !=, 0);
/* ping vm1 -> vm2 on vector 1 */
- global_qtest = s2->qtest;
+ global_qtest = s2->qs->qts;
if (msi) {
ret = qpci_msix_pending(s2->dev, 1);
g_assert_cmpuint(ret, ==, 0);
--
2.9.3
^ permalink raw reply related [flat|nested] 73+ messages in thread
* [Qemu-devel] [PULL 41/67] qtest: add ivshmem-test for ppc64
2017-01-12 2:02 [Qemu-devel] [PULL 00/67] ppc-for-2.9 queue 20170112 David Gibson
` (39 preceding siblings ...)
2017-01-12 2:03 ` [Qemu-devel] [PULL 40/67] qtest: convert ivshmem-test to use libqos David Gibson
@ 2017-01-12 2:03 ` David Gibson
2017-01-12 2:03 ` [Qemu-devel] [PULL 42/67] hw/gpio: QOM'ify mpc8xxx.c David Gibson
` (27 subsequent siblings)
68 siblings, 0 replies; 73+ messages in thread
From: David Gibson @ 2017-01-12 2:03 UTC (permalink / raw)
To: peter.maydell
Cc: agraf, qemu-ppc, qemu-devel, thuth, lvivier, aik, mdroth, David Gibson
From: Laurent Vivier <lvivier@redhat.com>
The test has been converted to use libqos, we can
now use it on ppc64. We also make the test fail on
all other architectures.
As libqos on ppc64 is not able to manage hotplug
and IRQ/MSI, we disable this part in the test on ppc64.
Signed-off-by: Laurent Vivier <lvivier@redhat.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
tests/Makefile.include | 3 ++-
tests/ivshmem-test.c | 17 +++++++++++++----
2 files changed, 15 insertions(+), 5 deletions(-)
diff --git a/tests/Makefile.include b/tests/Makefile.include
index 6ed78b8..0bb939d 100644
--- a/tests/Makefile.include
+++ b/tests/Makefile.include
@@ -288,6 +288,7 @@ check-qtest-ppc64-y += tests/test-netfilter$(EXESUF)
check-qtest-ppc64-y += tests/test-filter-mirror$(EXESUF)
check-qtest-ppc64-y += tests/test-filter-redirector$(EXESUF)
check-qtest-ppc64-y += tests/display-vga-test$(EXESUF)
+check-qtest-ppc64-y += tests/ivshmem-test$(EXESUF)
check-qtest-sh4-y = tests/endianness-test$(EXESUF)
@@ -692,7 +693,7 @@ tests/test-netfilter$(EXESUF): tests/test-netfilter.o $(qtest-obj-y)
tests/test-filter-mirror$(EXESUF): tests/test-filter-mirror.o $(qtest-obj-y)
tests/test-filter-redirector$(EXESUF): tests/test-filter-redirector.o $(qtest-obj-y)
tests/test-x86-cpuid-compat$(EXESUF): tests/test-x86-cpuid-compat.o $(qtest-obj-y)
-tests/ivshmem-test$(EXESUF): tests/ivshmem-test.o contrib/ivshmem-server/ivshmem-server.o $(libqos-pc-obj-y)
+tests/ivshmem-test$(EXESUF): tests/ivshmem-test.o contrib/ivshmem-server/ivshmem-server.o $(libqos-pc-obj-y) $(libqos-spapr-obj-y)
tests/vhost-user-bridge$(EXESUF): tests/vhost-user-bridge.o contrib/libvhost-user/libvhost-user.o $(test-util-obj-y)
tests/test-uuid$(EXESUF): tests/test-uuid.o $(test-util-obj-y)
tests/test-arm-mptimer$(EXESUF): tests/test-arm-mptimer.o
diff --git a/tests/ivshmem-test.c b/tests/ivshmem-test.c
index 8095d72..3776342 100644
--- a/tests/ivshmem-test.c
+++ b/tests/ivshmem-test.c
@@ -12,6 +12,7 @@
#include <glib/gstdio.h>
#include "contrib/ivshmem-server/ivshmem-server.h"
#include "libqos/libqos-pc.h"
+#include "libqos/libqos-spapr.h"
#include "libqtest.h"
#include "qemu-common.h"
@@ -124,8 +125,10 @@ static void setup_vm_cmd(IVState *s, const char *cmd, bool msix)
if (strcmp(arch, "i386") == 0 || strcmp(arch, "x86_64") == 0) {
s->qs = qtest_pc_boot(cmd);
+ } else if (strcmp(arch, "ppc64") == 0) {
+ s->qs = qtest_spapr_boot(cmd);
} else {
- g_printerr("ivshmem-test tests are only available on x86\n");
+ g_printerr("ivshmem-test tests are only available on x86 or ppc64\n");
exit(EXIT_FAILURE);
}
s->dev = get_device(s->qs->pcibus);
@@ -415,6 +418,7 @@ static void test_ivshmem_server_irq(void)
static void test_ivshmem_hotplug(void)
{
+ const char *arch = qtest_get_arch();
gchar *opts;
qtest_start("");
@@ -422,7 +426,9 @@ static void test_ivshmem_hotplug(void)
opts = g_strdup_printf("'shm': '%s', 'size': '1M'", tmpshm);
qpci_plug_device_test("ivshmem", "iv1", PCI_SLOT_HP, opts);
- qpci_unplug_acpi_device_test("iv1", PCI_SLOT_HP);
+ if (strcmp(arch, "ppc64") != 0) {
+ qpci_unplug_acpi_device_test("iv1", PCI_SLOT_HP);
+ }
qtest_end();
g_free(opts);
@@ -494,6 +500,7 @@ static gchar *mktempshm(int size, int *fd)
int main(int argc, char **argv)
{
int ret, fd;
+ const char *arch = qtest_get_arch();
gchar dir[] = "/tmp/ivshmem-test.XXXXXX";
#if !GLIB_CHECK_VERSION(2, 31, 0)
@@ -524,8 +531,10 @@ int main(int argc, char **argv)
qtest_add_func("/ivshmem/memdev", test_ivshmem_memdev);
if (g_test_slow()) {
qtest_add_func("/ivshmem/pair", test_ivshmem_pair);
- qtest_add_func("/ivshmem/server-msi", test_ivshmem_server_msi);
- qtest_add_func("/ivshmem/server-irq", test_ivshmem_server_irq);
+ if (strcmp(arch, "ppc64") != 0) {
+ qtest_add_func("/ivshmem/server-msi", test_ivshmem_server_msi);
+ qtest_add_func("/ivshmem/server-irq", test_ivshmem_server_irq);
+ }
}
ret = g_test_run();
--
2.9.3
^ permalink raw reply related [flat|nested] 73+ messages in thread
* [Qemu-devel] [PULL 42/67] hw/gpio: QOM'ify mpc8xxx.c
2017-01-12 2:02 [Qemu-devel] [PULL 00/67] ppc-for-2.9 queue 20170112 David Gibson
` (40 preceding siblings ...)
2017-01-12 2:03 ` [Qemu-devel] [PULL 41/67] qtest: add ivshmem-test for ppc64 David Gibson
@ 2017-01-12 2:03 ` David Gibson
2017-01-12 2:03 ` [Qemu-devel] [PULL 43/67] hw/ppc: QOM'ify e500.c David Gibson
` (26 subsequent siblings)
68 siblings, 0 replies; 73+ messages in thread
From: David Gibson @ 2017-01-12 2:03 UTC (permalink / raw)
To: peter.maydell
Cc: agraf, qemu-ppc, qemu-devel, thuth, lvivier, aik, mdroth,
xiaoqiang zhao, David Gibson
From: xiaoqiang zhao <zxq_yx_007@163.com>
* Drop the old SysBus init function and use instance_init
* Change mpc8xxx_gpio_reset to a DeviceClass::reset function
Signed-off-by: xiaoqiang zhao <zxq_yx_007@163.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/gpio/mpc8xxx.c | 20 +++++++++++---------
1 file changed, 11 insertions(+), 9 deletions(-)
diff --git a/hw/gpio/mpc8xxx.c b/hw/gpio/mpc8xxx.c
index d149719..e12edb4 100644
--- a/hw/gpio/mpc8xxx.c
+++ b/hw/gpio/mpc8xxx.c
@@ -143,8 +143,10 @@ static void mpc8xxx_gpio_write(void *opaque, hwaddr offset,
mpc8xxx_gpio_update(s);
}
-static void mpc8xxx_gpio_reset(MPC8XXXGPIOState *s)
+static void mpc8xxx_gpio_reset(DeviceState *dev)
{
+ MPC8XXXGPIOState *s = MPC8XXX_GPIO(dev);
+
s->dir = 0;
s->odr = 0;
s->dat = 0;
@@ -180,33 +182,33 @@ static const MemoryRegionOps mpc8xxx_gpio_ops = {
.endianness = DEVICE_BIG_ENDIAN,
};
-static int mpc8xxx_gpio_initfn(SysBusDevice *sbd)
+static void mpc8xxx_gpio_initfn(Object *obj)
{
- DeviceState *dev = DEVICE(sbd);
- MPC8XXXGPIOState *s = MPC8XXX_GPIO(dev);
+ DeviceState *dev = DEVICE(obj);
+ MPC8XXXGPIOState *s = MPC8XXX_GPIO(obj);
+ SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
- memory_region_init_io(&s->iomem, OBJECT(s), &mpc8xxx_gpio_ops, s, "mpc8xxx_gpio", 0x1000);
+ memory_region_init_io(&s->iomem, obj, &mpc8xxx_gpio_ops,
+ s, "mpc8xxx_gpio", 0x1000);
sysbus_init_mmio(sbd, &s->iomem);
sysbus_init_irq(sbd, &s->irq);
qdev_init_gpio_in(dev, mpc8xxx_gpio_set_irq, 32);
qdev_init_gpio_out(dev, s->out, 32);
- mpc8xxx_gpio_reset(s);
- return 0;
}
static void mpc8xxx_gpio_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
- SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
- k->init = mpc8xxx_gpio_initfn;
dc->vmsd = &vmstate_mpc8xxx_gpio;
+ dc->reset = mpc8xxx_gpio_reset;
}
static const TypeInfo mpc8xxx_gpio_info = {
.name = TYPE_MPC8XXX_GPIO,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(MPC8XXXGPIOState),
+ .instance_init = mpc8xxx_gpio_initfn,
.class_init = mpc8xxx_gpio_class_init,
};
--
2.9.3
^ permalink raw reply related [flat|nested] 73+ messages in thread
* [Qemu-devel] [PULL 43/67] hw/ppc: QOM'ify e500.c
2017-01-12 2:02 [Qemu-devel] [PULL 00/67] ppc-for-2.9 queue 20170112 David Gibson
` (41 preceding siblings ...)
2017-01-12 2:03 ` [Qemu-devel] [PULL 42/67] hw/gpio: QOM'ify mpc8xxx.c David Gibson
@ 2017-01-12 2:03 ` David Gibson
2017-01-12 2:03 ` [Qemu-devel] [PULL 44/67] hw/ppc: QOM'ify ppce500_spin.c David Gibson
` (25 subsequent siblings)
68 siblings, 0 replies; 73+ messages in thread
From: David Gibson @ 2017-01-12 2:03 UTC (permalink / raw)
To: peter.maydell
Cc: agraf, qemu-ppc, qemu-devel, thuth, lvivier, aik, mdroth,
xiaoqiang zhao, David Gibson
From: xiaoqiang zhao <zxq_yx_007@163.com>
Drop the old SysBus init function and use instance_init
Signed-off-by: xiaoqiang zhao <zxq_yx_007@163.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/ppc/e500.c | 17 ++++-------------
1 file changed, 4 insertions(+), 13 deletions(-)
diff --git a/hw/ppc/e500.c b/hw/ppc/e500.c
index cf8b122..792bd79 100644
--- a/hw/ppc/e500.c
+++ b/hw/ppc/e500.c
@@ -1049,27 +1049,18 @@ void ppce500_init(MachineState *machine, PPCE500Params *params)
boot_info->dt_size = dt_size;
}
-static int e500_ccsr_initfn(SysBusDevice *dev)
+static void e500_ccsr_initfn(Object *obj)
{
- PPCE500CCSRState *ccsr;
-
- ccsr = CCSR(dev);
- memory_region_init(&ccsr->ccsr_space, OBJECT(ccsr), "e500-ccsr",
+ PPCE500CCSRState *ccsr = CCSR(obj);
+ memory_region_init(&ccsr->ccsr_space, obj, "e500-ccsr",
MPC8544_CCSRBAR_SIZE);
- return 0;
-}
-
-static void e500_ccsr_class_init(ObjectClass *klass, void *data)
-{
- SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
- k->init = e500_ccsr_initfn;
}
static const TypeInfo e500_ccsr_info = {
.name = TYPE_CCSR,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(PPCE500CCSRState),
- .class_init = e500_ccsr_class_init,
+ .instance_init = e500_ccsr_initfn,
};
static void e500_register_types(void)
--
2.9.3
^ permalink raw reply related [flat|nested] 73+ messages in thread
* [Qemu-devel] [PULL 44/67] hw/ppc: QOM'ify ppce500_spin.c
2017-01-12 2:02 [Qemu-devel] [PULL 00/67] ppc-for-2.9 queue 20170112 David Gibson
` (42 preceding siblings ...)
2017-01-12 2:03 ` [Qemu-devel] [PULL 43/67] hw/ppc: QOM'ify e500.c David Gibson
@ 2017-01-12 2:03 ` David Gibson
2017-01-12 2:03 ` [Qemu-devel] [PULL 45/67] hw/ppc: QOM'ify spapr_vio.c David Gibson
` (24 subsequent siblings)
68 siblings, 0 replies; 73+ messages in thread
From: David Gibson @ 2017-01-12 2:03 UTC (permalink / raw)
To: peter.maydell
Cc: agraf, qemu-ppc, qemu-devel, thuth, lvivier, aik, mdroth,
xiaoqiang zhao, David Gibson
From: xiaoqiang zhao <zxq_yx_007@163.com>
Drop the old SysBus init function and use instance_init
Signed-off-by: xiaoqiang zhao <zxq_yx_007@163.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/ppc/ppce500_spin.c | 18 ++++++++----------
1 file changed, 8 insertions(+), 10 deletions(-)
diff --git a/hw/ppc/ppce500_spin.c b/hw/ppc/ppce500_spin.c
index cf958a9..958536f 100644
--- a/hw/ppc/ppce500_spin.c
+++ b/hw/ppc/ppce500_spin.c
@@ -54,9 +54,9 @@ typedef struct SpinState {
SpinInfo spin[MAX_CPUS];
} SpinState;
-static void spin_reset(void *opaque)
+static void spin_reset(DeviceState *dev)
{
- SpinState *s = opaque;
+ SpinState *s = E500_SPIN(dev);
int i;
for (i = 0; i < MAX_CPUS; i++) {
@@ -174,30 +174,28 @@ static const MemoryRegionOps spin_rw_ops = {
.endianness = DEVICE_BIG_ENDIAN,
};
-static int ppce500_spin_initfn(SysBusDevice *dev)
+static void ppce500_spin_initfn(Object *obj)
{
+ SysBusDevice *dev = SYS_BUS_DEVICE(obj);
SpinState *s = E500_SPIN(dev);
- memory_region_init_io(&s->iomem, OBJECT(s), &spin_rw_ops, s,
+ memory_region_init_io(&s->iomem, obj, &spin_rw_ops, s,
"e500 spin pv device", sizeof(SpinInfo) * MAX_CPUS);
sysbus_init_mmio(dev, &s->iomem);
-
- qemu_register_reset(spin_reset, s);
-
- return 0;
}
static void ppce500_spin_class_init(ObjectClass *klass, void *data)
{
- SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
+ DeviceClass *dc = DEVICE_CLASS(klass);
- k->init = ppce500_spin_initfn;
+ dc->reset = spin_reset;
}
static const TypeInfo ppce500_spin_info = {
.name = TYPE_E500_SPIN,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(SpinState),
+ .instance_init = ppce500_spin_initfn,
.class_init = ppce500_spin_class_init,
};
--
2.9.3
^ permalink raw reply related [flat|nested] 73+ messages in thread
* [Qemu-devel] [PULL 45/67] hw/ppc: QOM'ify spapr_vio.c
2017-01-12 2:02 [Qemu-devel] [PULL 00/67] ppc-for-2.9 queue 20170112 David Gibson
` (43 preceding siblings ...)
2017-01-12 2:03 ` [Qemu-devel] [PULL 44/67] hw/ppc: QOM'ify ppce500_spin.c David Gibson
@ 2017-01-12 2:03 ` David Gibson
2017-01-12 2:03 ` [Qemu-devel] [PULL 46/67] target-ppc: Add xxextractuw instruction David Gibson
` (23 subsequent siblings)
68 siblings, 0 replies; 73+ messages in thread
From: David Gibson @ 2017-01-12 2:03 UTC (permalink / raw)
To: peter.maydell
Cc: agraf, qemu-ppc, qemu-devel, thuth, lvivier, aik, mdroth,
xiaoqiang zhao, David Gibson
From: xiaoqiang zhao <zxq_yx_007@163.com>
Drop the old and empty SysBus init
Signed-off-by: xiaoqiang zhao <zxq_yx_007@163.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/ppc/spapr_vio.c | 10 ----------
1 file changed, 10 deletions(-)
diff --git a/hw/ppc/spapr_vio.c b/hw/ppc/spapr_vio.c
index cc1e09c..8bfc5f9 100644
--- a/hw/ppc/spapr_vio.c
+++ b/hw/ppc/spapr_vio.c
@@ -538,21 +538,11 @@ VIOsPAPRBus *spapr_vio_bus_init(void)
return bus;
}
-/* Represents sPAPR hcall VIO devices */
-
-static int spapr_vio_bridge_init(SysBusDevice *dev)
-{
- /* nothing */
- return 0;
-}
-
static void spapr_vio_bridge_class_init(ObjectClass *klass, void *data)
{
- SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
DeviceClass *dc = DEVICE_CLASS(klass);
dc->fw_name = "vdevice";
- k->init = spapr_vio_bridge_init;
}
static const TypeInfo spapr_vio_bridge_info = {
--
2.9.3
^ permalink raw reply related [flat|nested] 73+ messages in thread
* [Qemu-devel] [PULL 46/67] target-ppc: Add xxextractuw instruction
2017-01-12 2:02 [Qemu-devel] [PULL 00/67] ppc-for-2.9 queue 20170112 David Gibson
` (44 preceding siblings ...)
2017-01-12 2:03 ` [Qemu-devel] [PULL 45/67] hw/ppc: QOM'ify spapr_vio.c David Gibson
@ 2017-01-12 2:03 ` David Gibson
2017-01-12 2:03 ` [Qemu-devel] [PULL 47/67] target-ppc: Add xxinsertw instruction David Gibson
` (22 subsequent siblings)
68 siblings, 0 replies; 73+ messages in thread
From: David Gibson @ 2017-01-12 2:03 UTC (permalink / raw)
To: peter.maydell
Cc: agraf, qemu-ppc, qemu-devel, thuth, lvivier, aik, mdroth,
Nikunj A Dadhania, David Gibson
From: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
xxextractuw: VSX Vector Extract Unsigned Word
Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
target/ppc/helper.h | 1 +
target/ppc/int_helper.c | 26 ++++++++++++++++++++++++++
target/ppc/translate/vsx-impl.inc.c | 30 ++++++++++++++++++++++++++++++
target/ppc/translate/vsx-ops.inc.c | 5 +++++
4 files changed, 62 insertions(+)
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index 4707db4..8b30420 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -540,6 +540,7 @@ DEF_HELPER_2(xvrspip, void, env, i32)
DEF_HELPER_2(xvrspiz, void, env, i32)
DEF_HELPER_2(xxperm, void, env, i32)
DEF_HELPER_2(xxpermr, void, env, i32)
+DEF_HELPER_4(xxextractuw, void, env, tl, tl, i32)
DEF_HELPER_2(efscfsi, i32, env, i32)
DEF_HELPER_2(efscfui, i32, env, i32)
diff --git a/target/ppc/int_helper.c b/target/ppc/int_helper.c
index 2bb628f..63ba0e3 100644
--- a/target/ppc/int_helper.c
+++ b/target/ppc/int_helper.c
@@ -2033,6 +2033,32 @@ VEXTRACT(uw, u32)
VEXTRACT(d, u64)
#undef VEXTRACT
+void helper_xxextractuw(CPUPPCState *env, target_ulong xtn,
+ target_ulong xbn, uint32_t index)
+{
+ ppc_vsr_t xt, xb;
+ size_t es = sizeof(uint32_t);
+ uint32_t ext_index;
+ int i;
+
+ getVSR(xbn, &xb, env);
+ memset(&xt, 0, sizeof(xt));
+
+#if defined(HOST_WORDS_BIGENDIAN)
+ ext_index = index;
+ for (i = 0; i < es; i++, ext_index++) {
+ xt.u8[8 - es + i] = xb.u8[ext_index % 16];
+ }
+#else
+ ext_index = 15 - index;
+ for (i = es - 1; i >= 0; i--, ext_index--) {
+ xt.u8[8 + i] = xb.u8[ext_index % 16];
+ }
+#endif
+
+ putVSR(xtn, &xt, env);
+}
+
#define VEXT_SIGNED(name, element, mask, cast, recast) \
void helper_##name(ppc_avr_t *r, ppc_avr_t *b) \
{ \
diff --git a/target/ppc/translate/vsx-impl.inc.c b/target/ppc/translate/vsx-impl.inc.c
index 2a17c35..7977f24 100644
--- a/target/ppc/translate/vsx-impl.inc.c
+++ b/target/ppc/translate/vsx-impl.inc.c
@@ -1180,6 +1180,36 @@ static void gen_xxsldwi(DisasContext *ctx)
tcg_temp_free_i64(xtl);
}
+#define VSX_EXTRACT(name) \
+static void gen_##name(DisasContext *ctx) \
+{ \
+ TCGv xt, xb; \
+ TCGv_i32 t0 = tcg_temp_new_i32(); \
+ uint8_t uimm = UIMM4(ctx->opcode); \
+ \
+ if (unlikely(!ctx->vsx_enabled)) { \
+ gen_exception(ctx, POWERPC_EXCP_VSXU); \
+ return; \
+ } \
+ xt = tcg_const_tl(xT(ctx->opcode)); \
+ xb = tcg_const_tl(xB(ctx->opcode)); \
+ /* uimm > 15 out of bound and for \
+ * uimm > 12 handle as per hardware in helper \
+ */ \
+ if (uimm > 15) { \
+ tcg_gen_movi_i64(cpu_vsrh(xT(ctx->opcode)), 0); \
+ tcg_gen_movi_i64(cpu_vsrl(xT(ctx->opcode)), 0); \
+ return; \
+ } \
+ tcg_gen_movi_i32(t0, uimm); \
+ gen_helper_##name(cpu_env, xt, xb, t0); \
+ tcg_temp_free(xb); \
+ tcg_temp_free(xt); \
+ tcg_temp_free_i32(t0); \
+}
+
+VSX_EXTRACT(xxextractuw)
+
#undef GEN_XX2FORM
#undef GEN_XX3FORM
#undef GEN_XX2IFORM
diff --git a/target/ppc/translate/vsx-ops.inc.c b/target/ppc/translate/vsx-ops.inc.c
index 46b95e3..473d925 100644
--- a/target/ppc/translate/vsx-ops.inc.c
+++ b/target/ppc/translate/vsx-ops.inc.c
@@ -49,6 +49,10 @@ GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 1, opc3, 0, PPC_NONE, fl2)
GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0, opc3, 0, PPC_NONE, fl2), \
GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 1, opc3, 0, PPC_NONE, fl2)
+#define GEN_XX2FORM_EXT(name, opc2, opc3, fl2) \
+GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0, opc3, 0x00100000, PPC_NONE, fl2), \
+GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 1, opc3, 0x00100000, PPC_NONE, fl2)
+
#define GEN_XX2FORM_EO(name, opc2, opc3, opc4, fl2) \
GEN_HANDLER2_E_2(name, #name, 0x3C, opc2 | 0, opc3, opc4, 0, PPC_NONE, fl2), \
GEN_HANDLER2_E_2(name, #name, 0x3C, opc2 | 1, opc3, opc4, 0, PPC_NONE, fl2)
@@ -280,6 +284,7 @@ GEN_XX3FORM(xxpermr, 0x08, 0x07, PPC2_ISA300),
GEN_XX2FORM(xxspltw, 0x08, 0x0A, PPC2_VSX),
GEN_XX1FORM(xxspltib, 0x08, 0x0B, PPC2_ISA300),
GEN_XX3FORM_DM(xxsldwi, 0x08, 0x00),
+GEN_XX2FORM_EXT(xxextractuw, 0x0A, 0x0A, PPC2_ISA300),
#define GEN_XXSEL_ROW(opc3) \
GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x18, opc3, 0, PPC_NONE, PPC2_VSX), \
--
2.9.3
^ permalink raw reply related [flat|nested] 73+ messages in thread
* [Qemu-devel] [PULL 47/67] target-ppc: Add xxinsertw instruction
2017-01-12 2:02 [Qemu-devel] [PULL 00/67] ppc-for-2.9 queue 20170112 David Gibson
` (45 preceding siblings ...)
2017-01-12 2:03 ` [Qemu-devel] [PULL 46/67] target-ppc: Add xxextractuw instruction David Gibson
@ 2017-01-12 2:03 ` David Gibson
2017-01-12 2:03 ` [Qemu-devel] [PULL 48/67] prep: add PReP System I/O David Gibson
` (21 subsequent siblings)
68 siblings, 0 replies; 73+ messages in thread
From: David Gibson @ 2017-01-12 2:03 UTC (permalink / raw)
To: peter.maydell
Cc: agraf, qemu-ppc, qemu-devel, thuth, lvivier, aik, mdroth,
Nikunj A Dadhania, David Gibson
From: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
xxinsertw: VSX Vector Insert Word
Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
target/ppc/helper.h | 1 +
target/ppc/int_helper.c | 25 +++++++++++++++++++++++++
target/ppc/translate/vsx-impl.inc.c | 5 +++--
target/ppc/translate/vsx-ops.inc.c | 1 +
4 files changed, 30 insertions(+), 2 deletions(-)
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index 8b30420..6c5b194 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -541,6 +541,7 @@ DEF_HELPER_2(xvrspiz, void, env, i32)
DEF_HELPER_2(xxperm, void, env, i32)
DEF_HELPER_2(xxpermr, void, env, i32)
DEF_HELPER_4(xxextractuw, void, env, tl, tl, i32)
+DEF_HELPER_4(xxinsertw, void, env, tl, tl, i32)
DEF_HELPER_2(efscfsi, i32, env, i32)
DEF_HELPER_2(efscfui, i32, env, i32)
diff --git a/target/ppc/int_helper.c b/target/ppc/int_helper.c
index 63ba0e3..24e5964 100644
--- a/target/ppc/int_helper.c
+++ b/target/ppc/int_helper.c
@@ -2059,6 +2059,31 @@ void helper_xxextractuw(CPUPPCState *env, target_ulong xtn,
putVSR(xtn, &xt, env);
}
+void helper_xxinsertw(CPUPPCState *env, target_ulong xtn,
+ target_ulong xbn, uint32_t index)
+{
+ ppc_vsr_t xt, xb;
+ size_t es = sizeof(uint32_t);
+ int ins_index, i = 0;
+
+ getVSR(xbn, &xb, env);
+ getVSR(xtn, &xt, env);
+
+#if defined(HOST_WORDS_BIGENDIAN)
+ ins_index = index;
+ for (i = 0; i < es && ins_index < 16; i++, ins_index++) {
+ xt.u8[ins_index] = xb.u8[8 - es + i];
+ }
+#else
+ ins_index = 15 - index;
+ for (i = es - 1; i >= 0 && ins_index >= 0; i--, ins_index--) {
+ xt.u8[ins_index] = xb.u8[8 + i];
+ }
+#endif
+
+ putVSR(xtn, &xt, env);
+}
+
#define VEXT_SIGNED(name, element, mask, cast, recast) \
void helper_##name(ppc_avr_t *r, ppc_avr_t *b) \
{ \
diff --git a/target/ppc/translate/vsx-impl.inc.c b/target/ppc/translate/vsx-impl.inc.c
index 7977f24..c9ba0f5 100644
--- a/target/ppc/translate/vsx-impl.inc.c
+++ b/target/ppc/translate/vsx-impl.inc.c
@@ -1180,7 +1180,7 @@ static void gen_xxsldwi(DisasContext *ctx)
tcg_temp_free_i64(xtl);
}
-#define VSX_EXTRACT(name) \
+#define VSX_EXTRACT_INSERT(name) \
static void gen_##name(DisasContext *ctx) \
{ \
TCGv xt, xb; \
@@ -1208,7 +1208,8 @@ static void gen_##name(DisasContext *ctx) \
tcg_temp_free_i32(t0); \
}
-VSX_EXTRACT(xxextractuw)
+VSX_EXTRACT_INSERT(xxextractuw)
+VSX_EXTRACT_INSERT(xxinsertw)
#undef GEN_XX2FORM
#undef GEN_XX3FORM
diff --git a/target/ppc/translate/vsx-ops.inc.c b/target/ppc/translate/vsx-ops.inc.c
index 473d925..096d358 100644
--- a/target/ppc/translate/vsx-ops.inc.c
+++ b/target/ppc/translate/vsx-ops.inc.c
@@ -285,6 +285,7 @@ GEN_XX2FORM(xxspltw, 0x08, 0x0A, PPC2_VSX),
GEN_XX1FORM(xxspltib, 0x08, 0x0B, PPC2_ISA300),
GEN_XX3FORM_DM(xxsldwi, 0x08, 0x00),
GEN_XX2FORM_EXT(xxextractuw, 0x0A, 0x0A, PPC2_ISA300),
+GEN_XX2FORM_EXT(xxinsertw, 0x0A, 0x0B, PPC2_ISA300),
#define GEN_XXSEL_ROW(opc3) \
GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x18, opc3, 0, PPC_NONE, PPC2_VSX), \
--
2.9.3
^ permalink raw reply related [flat|nested] 73+ messages in thread
* [Qemu-devel] [PULL 48/67] prep: add PReP System I/O
2017-01-12 2:02 [Qemu-devel] [PULL 00/67] ppc-for-2.9 queue 20170112 David Gibson
` (46 preceding siblings ...)
2017-01-12 2:03 ` [Qemu-devel] [PULL 47/67] target-ppc: Add xxinsertw instruction David Gibson
@ 2017-01-12 2:03 ` David Gibson
2017-01-12 2:03 ` [Qemu-devel] [PULL 49/67] prep: add IBM RS/6000 7020 (40p) memory controller David Gibson
` (20 subsequent siblings)
68 siblings, 0 replies; 73+ messages in thread
From: David Gibson @ 2017-01-12 2:03 UTC (permalink / raw)
To: peter.maydell
Cc: agraf, qemu-ppc, qemu-devel, thuth, lvivier, aik, mdroth,
Hervé Poussineau, David Gibson
From: Hervé Poussineau <hpoussin@reactos.org>
This device is a partial duplicate of System I/O device available in hw/ppc/prep.c
This new one doesn't have all the Motorola-specific registers.
The old one should be deprecated and removed with the 'prep' machine.
Partial documentation available at
ftp://ftp.software.ibm.com/rs6000/technology/spec/srp1_1.exe
section 6.1.5 (I/O Device Mapping)
Signed-off-by: Hervé Poussineau <hpoussin@reactos.org>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/ppc/Makefile.objs | 1 +
hw/ppc/prep_systemio.c | 303 +++++++++++++++++++++++++++++++++++++++++++++++++
hw/ppc/trace-events | 4 +
3 files changed, 308 insertions(+)
create mode 100644 hw/ppc/prep_systemio.c
diff --git a/hw/ppc/Makefile.objs b/hw/ppc/Makefile.objs
index 8025129..db72297 100644
--- a/hw/ppc/Makefile.objs
+++ b/hw/ppc/Makefile.objs
@@ -16,6 +16,7 @@ obj-y += ppc405_boards.o ppc4xx_devs.o ppc405_uc.o ppc440_bamboo.o
obj-y += ppc4xx_pci.o
# PReP
obj-$(CONFIG_PREP) += prep.o
+obj-$(CONFIG_PREP) += prep_systemio.o
# OldWorld PowerMac
obj-$(CONFIG_MAC) += mac_oldworld.o
# NewWorld PowerMac
diff --git a/hw/ppc/prep_systemio.c b/hw/ppc/prep_systemio.c
new file mode 100644
index 0000000..50893ec
--- /dev/null
+++ b/hw/ppc/prep_systemio.c
@@ -0,0 +1,303 @@
+/*
+ * QEMU PReP System I/O emulation
+ *
+ * Copyright (c) 2017 Hervé Poussineau
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "qemu/osdep.h"
+#include "hw/isa/isa.h"
+#include "exec/address-spaces.h"
+#include "qemu/error-report.h" /* for error_report() */
+#include "sysemu/sysemu.h" /* for vm_stop() */
+#include "cpu.h"
+#include "trace.h"
+
+#define TYPE_PREP_SYSTEMIO "prep-systemio"
+#define PREP_SYSTEMIO(obj) \
+ OBJECT_CHECK(PrepSystemIoState, (obj), TYPE_PREP_SYSTEMIO)
+
+/* Bit as defined in PowerPC Reference Plaform v1.1, sect. 6.1.5, p. 132 */
+#define PREP_BIT(n) (1 << (7 - (n)))
+
+typedef struct PrepSystemIoState {
+ ISADevice parent_obj;
+ MemoryRegion ppc_parity_mem;
+
+ qemu_irq non_contiguous_io_map_irq;
+ uint8_t sreset; /* 0x0092 */
+ uint8_t equipment; /* 0x080c */
+ uint8_t system_control; /* 0x081c */
+ uint8_t iomap_type; /* 0x0850 */
+ uint8_t ibm_planar_id; /* 0x0852 */
+ qemu_irq softreset_irq;
+ PortioList portio;
+} PrepSystemIoState;
+
+/* PORT 0092 -- Special Port 92 (Read/Write) */
+
+enum {
+ PORT0092_SOFTRESET = PREP_BIT(7),
+ PORT0092_LE_MODE = PREP_BIT(6),
+};
+
+static void prep_port0092_write(void *opaque, uint32_t addr, uint32_t val)
+{
+ PrepSystemIoState *s = opaque;
+
+ trace_prep_systemio_write(addr, val);
+
+ s->sreset = val & PORT0092_SOFTRESET;
+ qemu_set_irq(s->softreset_irq, s->sreset);
+
+ if ((val & PORT0092_LE_MODE) != 0) {
+ /* XXX Not supported yet */
+ error_report("little-endian mode not supported");
+ vm_stop(RUN_STATE_PAUSED);
+ } else {
+ /* Nothing to do */
+ }
+}
+
+static uint32_t prep_port0092_read(void *opaque, uint32_t addr)
+{
+ PrepSystemIoState *s = opaque;
+ trace_prep_systemio_read(addr, s->sreset);
+ return s->sreset;
+}
+
+/* PORT 0808 -- Hardfile Light Register (Write Only) */
+
+enum {
+ PORT0808_HARDFILE_LIGHT_ON = PREP_BIT(7),
+};
+
+static void prep_port0808_write(void *opaque, uint32_t addr, uint32_t val)
+{
+ trace_prep_systemio_write(addr, val);
+}
+
+/* PORT 0810 -- Password Protect 1 Register (Write Only) */
+
+/* reset by port 0x4D in the SIO */
+static void prep_port0810_write(void *opaque, uint32_t addr, uint32_t val)
+{
+ trace_prep_systemio_write(addr, val);
+}
+
+/* PORT 0812 -- Password Protect 2 Register (Write Only) */
+
+/* reset by port 0x4D in the SIO */
+static void prep_port0812_write(void *opaque, uint32_t addr, uint32_t val)
+{
+ trace_prep_systemio_write(addr, val);
+}
+
+/* PORT 0814 -- L2 Invalidate Register (Write Only) */
+
+static void prep_port0814_write(void *opaque, uint32_t addr, uint32_t val)
+{
+ trace_prep_systemio_write(addr, val);
+}
+
+/* PORT 0818 -- Reserved for Keylock (Read Only) */
+
+enum {
+ PORT0818_KEYLOCK_SIGNAL_HIGH = PREP_BIT(7),
+};
+
+static uint32_t prep_port0818_read(void *opaque, uint32_t addr)
+{
+ uint32_t val = 0;
+ trace_prep_systemio_read(addr, val);
+ return val;
+}
+
+/* PORT 080C -- Equipment */
+
+enum {
+ PORT080C_SCSIFUSE = PREP_BIT(1),
+ PORT080C_L2_COPYBACK = PREP_BIT(4),
+ PORT080C_L2_256 = PREP_BIT(5),
+ PORT080C_UPGRADE_CPU = PREP_BIT(6),
+ PORT080C_L2 = PREP_BIT(7),
+};
+
+static uint32_t prep_port080c_read(void *opaque, uint32_t addr)
+{
+ PrepSystemIoState *s = opaque;
+ trace_prep_systemio_read(addr, s->equipment);
+ return s->equipment;
+}
+
+/* PORT 081C -- System Control Register (Read/Write) */
+
+enum {
+ PORT081C_FLOPPY_MOTOR_INHIBIT = PREP_BIT(3),
+ PORT081C_MASK_TEA = PREP_BIT(2),
+ PORT081C_L2_UPDATE_INHIBIT = PREP_BIT(1),
+ PORT081C_L2_CACHEMISS_INHIBIT = PREP_BIT(0),
+};
+
+static void prep_port081c_write(void *opaque, uint32_t addr, uint32_t val)
+{
+ static const uint8_t mask = PORT081C_FLOPPY_MOTOR_INHIBIT |
+ PORT081C_MASK_TEA |
+ PORT081C_L2_UPDATE_INHIBIT |
+ PORT081C_L2_CACHEMISS_INHIBIT;
+ PrepSystemIoState *s = opaque;
+ trace_prep_systemio_write(addr, val);
+ s->system_control = val & mask;
+}
+
+static uint32_t prep_port081c_read(void *opaque, uint32_t addr)
+{
+ PrepSystemIoState *s = opaque;
+ trace_prep_systemio_read(addr, s->system_control);
+ return s->system_control;
+}
+
+/* System Board Identification */
+
+static uint32_t prep_port0852_read(void *opaque, uint32_t addr)
+{
+ PrepSystemIoState *s = opaque;
+ trace_prep_systemio_read(addr, s->ibm_planar_id);
+ return s->ibm_planar_id;
+}
+
+/* PORT 0850 -- I/O Map Type Register (Read/Write) */
+
+enum {
+ PORT0850_IOMAP_NONCONTIGUOUS = PREP_BIT(7),
+};
+
+static uint32_t prep_port0850_read(void *opaque, uint32_t addr)
+{
+ PrepSystemIoState *s = opaque;
+ trace_prep_systemio_read(addr, s->iomap_type);
+ return s->iomap_type;
+}
+
+static void prep_port0850_write(void *opaque, uint32_t addr, uint32_t val)
+{
+ PrepSystemIoState *s = opaque;
+
+ trace_prep_systemio_write(addr, val);
+ qemu_set_irq(s->non_contiguous_io_map_irq,
+ val & PORT0850_IOMAP_NONCONTIGUOUS);
+ s->iomap_type = val & PORT0850_IOMAP_NONCONTIGUOUS;
+}
+
+static const MemoryRegionPortio ppc_io800_port_list[] = {
+ { 0x092, 1, 1, .read = prep_port0092_read,
+ .write = prep_port0092_write, },
+ { 0x808, 1, 1, .write = prep_port0808_write, },
+ { 0x80c, 1, 1, .read = prep_port080c_read, },
+ { 0x810, 1, 1, .write = prep_port0810_write, },
+ { 0x812, 1, 1, .write = prep_port0812_write, },
+ { 0x814, 1, 1, .write = prep_port0814_write, },
+ { 0x818, 1, 1, .read = prep_port0818_read },
+ { 0x81c, 1, 1, .read = prep_port081c_read,
+ .write = prep_port081c_write, },
+ { 0x850, 1, 1, .read = prep_port0850_read,
+ .write = prep_port0850_write, },
+ { 0x852, 1, 1, .read = prep_port0852_read, },
+ PORTIO_END_OF_LIST()
+};
+
+static uint64_t ppc_parity_error_readl(void *opaque, hwaddr addr,
+ unsigned int size)
+{
+ uint32_t val = 0;
+ trace_prep_systemio_read((unsigned int)addr, val);
+ return val;
+}
+
+static const MemoryRegionOps ppc_parity_error_ops = {
+ .read = ppc_parity_error_readl,
+ .valid = {
+ .min_access_size = 4,
+ .max_access_size = 4,
+ },
+};
+
+static void prep_systemio_realize(DeviceState *dev, Error **errp)
+{
+ ISADevice *isa = ISA_DEVICE(dev);
+ PrepSystemIoState *s = PREP_SYSTEMIO(dev);
+ PowerPCCPU *cpu;
+
+ qdev_init_gpio_out(dev, &s->non_contiguous_io_map_irq, 1);
+ s->iomap_type = PORT0850_IOMAP_NONCONTIGUOUS;
+ qemu_set_irq(s->non_contiguous_io_map_irq,
+ s->iomap_type & PORT0850_IOMAP_NONCONTIGUOUS);
+ cpu = POWERPC_CPU(first_cpu);
+ s->softreset_irq = cpu->env.irq_inputs[PPC6xx_INPUT_HRESET];
+
+ isa_register_portio_list(isa, &s->portio, 0x0, ppc_io800_port_list, s,
+ "systemio800");
+
+ memory_region_init_io(&s->ppc_parity_mem, OBJECT(dev),
+ &ppc_parity_error_ops, s, "ppc-parity", 0x4);
+ memory_region_add_subregion(get_system_memory(), 0xbfffeff0,
+ &s->ppc_parity_mem);
+}
+
+static const VMStateDescription vmstate_prep_systemio = {
+ .name = "prep_systemio",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINT8(sreset, PrepSystemIoState),
+ VMSTATE_UINT8(system_control, PrepSystemIoState),
+ VMSTATE_UINT8(iomap_type, PrepSystemIoState),
+ VMSTATE_END_OF_LIST()
+ },
+};
+
+static Property prep_systemio_properties[] = {
+ DEFINE_PROP_UINT8("ibm-planar-id", PrepSystemIoState, ibm_planar_id, 0),
+ DEFINE_PROP_UINT8("equipment", PrepSystemIoState, equipment, 0),
+ DEFINE_PROP_END_OF_LIST()
+};
+
+static void prep_systemio_class_initfn(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+
+ dc->realize = prep_systemio_realize;
+ dc->vmsd = &vmstate_prep_systemio;
+ dc->props = prep_systemio_properties;
+}
+
+static TypeInfo prep_systemio800_info = {
+ .name = TYPE_PREP_SYSTEMIO,
+ .parent = TYPE_ISA_DEVICE,
+ .instance_size = sizeof(PrepSystemIoState),
+ .class_init = prep_systemio_class_initfn,
+};
+
+static void prep_systemio_register_types(void)
+{
+ type_register_static(&prep_systemio800_info);
+}
+
+type_init(prep_systemio_register_types)
diff --git a/hw/ppc/trace-events b/hw/ppc/trace-events
index 2297ead..2ba6166 100644
--- a/hw/ppc/trace-events
+++ b/hw/ppc/trace-events
@@ -74,3 +74,7 @@ ppc_tb_adjust(uint64_t offs1, uint64_t offs2, int64_t diff, int64_t seconds) "ad
# hw/ppc/prep.c
prep_io_800_writeb(uint32_t addr, uint32_t val) "0x%08" PRIx32 " => 0x%02" PRIx32
prep_io_800_readb(uint32_t addr, uint32_t retval) "0x%08" PRIx32 " <= 0x%02" PRIx32
+
+# hw/ppc/prep_systemio.c
+prep_systemio_read(uint32_t addr, uint32_t val) "read addr=%x val=%x"
+prep_systemio_write(uint32_t addr, uint32_t val) "write addr=%x val=%x"
--
2.9.3
^ permalink raw reply related [flat|nested] 73+ messages in thread
* [Qemu-devel] [PULL 49/67] prep: add IBM RS/6000 7020 (40p) memory controller
2017-01-12 2:02 [Qemu-devel] [PULL 00/67] ppc-for-2.9 queue 20170112 David Gibson
` (47 preceding siblings ...)
2017-01-12 2:03 ` [Qemu-devel] [PULL 48/67] prep: add PReP System I/O David Gibson
@ 2017-01-12 2:03 ` David Gibson
2017-01-12 2:03 ` [Qemu-devel] [PULL 50/67] prep: add IBM RS/6000 7020 (40p) machine emulation David Gibson
` (19 subsequent siblings)
68 siblings, 0 replies; 73+ messages in thread
From: David Gibson @ 2017-01-12 2:03 UTC (permalink / raw)
To: peter.maydell
Cc: agraf, qemu-ppc, qemu-devel, thuth, lvivier, aik, mdroth,
Hervé Poussineau, David Gibson
From: Hervé Poussineau <hpoussin@reactos.org>
Signed-off-by: Hervé Poussineau <hpoussin@reactos.org>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
[dwg: Added CONFIG_RS6000_MC to ppc64 or it breaks testcases]
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
default-configs/ppc-softmmu.mak | 1 +
default-configs/ppc64-softmmu.mak | 1 +
hw/ppc/Makefile.objs | 1 +
hw/ppc/rs6000_mc.c | 232 ++++++++++++++++++++++++++++++++++++++
hw/ppc/trace-events | 7 ++
5 files changed, 242 insertions(+)
create mode 100644 hw/ppc/rs6000_mc.c
diff --git a/default-configs/ppc-softmmu.mak b/default-configs/ppc-softmmu.mak
index d4d0f9b..e567658 100644
--- a/default-configs/ppc-softmmu.mak
+++ b/default-configs/ppc-softmmu.mak
@@ -47,3 +47,4 @@ CONFIG_LIBDECNUMBER=y
# For PReP
CONFIG_MC146818RTC=y
CONFIG_ISA_TESTDEV=y
+CONFIG_RS6000_MC=y
diff --git a/default-configs/ppc64-softmmu.mak b/default-configs/ppc64-softmmu.mak
index 67a9bca..9ae6563 100644
--- a/default-configs/ppc64-softmmu.mak
+++ b/default-configs/ppc64-softmmu.mak
@@ -55,3 +55,4 @@ CONFIG_XICS_KVM=$(and $(CONFIG_PSERIES),$(CONFIG_KVM))
CONFIG_MC146818RTC=y
CONFIG_ISA_TESTDEV=y
CONFIG_MEM_HOTPLUG=y
+CONFIG_RS6000_MC=y
diff --git a/hw/ppc/Makefile.objs b/hw/ppc/Makefile.objs
index db72297..0012934 100644
--- a/hw/ppc/Makefile.objs
+++ b/hw/ppc/Makefile.objs
@@ -17,6 +17,7 @@ obj-y += ppc4xx_pci.o
# PReP
obj-$(CONFIG_PREP) += prep.o
obj-$(CONFIG_PREP) += prep_systemio.o
+obj-${CONFIG_RS6000_MC} += rs6000_mc.o
# OldWorld PowerMac
obj-$(CONFIG_MAC) += mac_oldworld.o
# NewWorld PowerMac
diff --git a/hw/ppc/rs6000_mc.c b/hw/ppc/rs6000_mc.c
new file mode 100644
index 0000000..b613565
--- /dev/null
+++ b/hw/ppc/rs6000_mc.c
@@ -0,0 +1,232 @@
+/*
+ * QEMU RS/6000 memory controller
+ *
+ * Copyright (c) 2017 Hervé Poussineau
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option) version 3 or any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "qemu/osdep.h"
+#include "hw/isa/isa.h"
+#include "exec/address-spaces.h"
+#include "hw/boards.h"
+#include "qapi/error.h"
+#include "trace.h"
+
+#define TYPE_RS6000MC "rs6000-mc"
+#define RS6000MC_DEVICE(obj) \
+ OBJECT_CHECK(RS6000MCState, (obj), TYPE_RS6000MC)
+
+typedef struct RS6000MCState {
+ ISADevice parent_obj;
+ /* see US patent 5,684,979 for details (expired 2001-11-04) */
+ uint32_t ram_size;
+ bool autoconfigure;
+ MemoryRegion simm[6];
+ unsigned int simm_size[6];
+ uint32_t end_address[8];
+ uint8_t port0820_index;
+ PortioList portio;
+} RS6000MCState;
+
+/* P0RT 0803 -- SIMM ID Register (32/8 MB) (Read Only) */
+
+static uint32_t rs6000mc_port0803_read(void *opaque, uint32_t addr)
+{
+ RS6000MCState *s = opaque;
+ uint32_t val = 0;
+ int socket;
+
+ /* (1 << socket) indicates 32 MB SIMM at given socket */
+ for (socket = 0; socket < 6; socket++) {
+ if (s->simm_size[socket] == 32) {
+ val |= (1 << socket);
+ }
+ }
+
+ trace_rs6000mc_id_read(addr, val);
+ return val;
+}
+
+/* PORT 0804 -- SIMM Presence Register (Read Only) */
+
+static uint32_t rs6000mc_port0804_read(void *opaque, uint32_t addr)
+{
+ RS6000MCState *s = opaque;
+ uint32_t val = 0xff;
+ int socket;
+
+ /* (1 << socket) indicates SIMM absence at given socket */
+ for (socket = 0; socket < 6; socket++) {
+ if (s->simm_size[socket]) {
+ val &= ~(1 << socket);
+ }
+ }
+ s->port0820_index = 0;
+
+ trace_rs6000mc_presence_read(addr, val);
+ return val;
+}
+
+/* Memory Controller Size Programming Register */
+
+static uint32_t rs6000mc_port0820_read(void *opaque, uint32_t addr)
+{
+ RS6000MCState *s = opaque;
+ uint32_t val = s->end_address[s->port0820_index] & 0x1f;
+ s->port0820_index = (s->port0820_index + 1) & 7;
+ trace_rs6000mc_size_read(addr, val);
+ return val;
+}
+
+static void rs6000mc_port0820_write(void *opaque, uint32_t addr, uint32_t val)
+{
+ RS6000MCState *s = opaque;
+ uint8_t socket = val >> 5;
+ uint32_t end_address = val & 0x1f;
+
+ trace_rs6000mc_size_write(addr, val);
+ s->end_address[socket] = end_address;
+ if (socket > 0 && socket < 7) {
+ if (s->simm_size[socket - 1]) {
+ uint32_t size;
+ uint32_t start_address = 0;
+ if (socket > 1) {
+ start_address = s->end_address[socket - 1];
+ }
+
+ size = end_address - start_address;
+ memory_region_set_enabled(&s->simm[socket - 1], size != 0);
+ memory_region_set_address(&s->simm[socket - 1],
+ start_address * 8 * 1024 * 1024);
+ }
+ }
+}
+
+/* Read Memory Parity Error */
+
+enum {
+ PORT0841_NO_ERROR_DETECTED = 0x01,
+};
+
+static uint32_t rs6000mc_port0841_read(void *opaque, uint32_t addr)
+{
+ uint32_t val = PORT0841_NO_ERROR_DETECTED;
+ trace_rs6000mc_parity_read(addr, val);
+ return val;
+}
+
+static const MemoryRegionPortio rs6000mc_port_list[] = {
+ { 0x803, 1, 1, .read = rs6000mc_port0803_read },
+ { 0x804, 1, 1, .read = rs6000mc_port0804_read },
+ { 0x820, 1, 1, .read = rs6000mc_port0820_read,
+ .write = rs6000mc_port0820_write, },
+ { 0x841, 1, 1, .read = rs6000mc_port0841_read },
+ PORTIO_END_OF_LIST()
+};
+
+static void rs6000mc_realize(DeviceState *dev, Error **errp)
+{
+ RS6000MCState *s = RS6000MC_DEVICE(dev);
+ int socket = 0;
+ unsigned int ram_size = s->ram_size / (1024 * 1024);
+
+ while (socket < 6) {
+ if (ram_size >= 64) {
+ s->simm_size[socket] = 32;
+ s->simm_size[socket + 1] = 32;
+ ram_size -= 64;
+ } else if (ram_size >= 16) {
+ s->simm_size[socket] = 8;
+ s->simm_size[socket + 1] = 8;
+ ram_size -= 16;
+ } else {
+ /* Not enough memory */
+ break;
+ }
+ socket += 2;
+ }
+
+ for (socket = 0; socket < 6; socket++) {
+ if (s->simm_size[socket]) {
+ char name[] = "simm.?";
+ name[5] = socket + '0';
+ memory_region_allocate_system_memory(&s->simm[socket], OBJECT(dev),
+ name, s->simm_size[socket]
+ * 1024 * 1024);
+ memory_region_add_subregion_overlap(get_system_memory(), 0,
+ &s->simm[socket], socket);
+ }
+ }
+ if (ram_size) {
+ /* unable to push all requested RAM in SIMMs */
+ error_setg(errp, "RAM size incompatible with this board. "
+ "Try again with something else, like %d MB",
+ s->ram_size / 1024 / 1024 - ram_size);
+ return;
+ }
+
+ if (s->autoconfigure) {
+ uint32_t start_address = 0;
+ for (socket = 0; socket < 6; socket++) {
+ if (s->simm_size[socket]) {
+ memory_region_set_enabled(&s->simm[socket], true);
+ memory_region_set_address(&s->simm[socket], start_address);
+ start_address += memory_region_size(&s->simm[socket]);
+ }
+ }
+ }
+
+ isa_register_portio_list(ISA_DEVICE(dev), &s->portio, 0x0,
+ rs6000mc_port_list, s, "rs6000mc");
+}
+
+static const VMStateDescription vmstate_rs6000mc = {
+ .name = "rs6000-mc",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINT8(port0820_index, RS6000MCState),
+ VMSTATE_END_OF_LIST()
+ },
+};
+
+static Property rs6000mc_properties[] = {
+ DEFINE_PROP_UINT32("ram-size", RS6000MCState, ram_size, 0),
+ DEFINE_PROP_BOOL("auto-configure", RS6000MCState, autoconfigure, true),
+ DEFINE_PROP_END_OF_LIST()
+};
+
+static void rs6000mc_class_initfn(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+
+ dc->realize = rs6000mc_realize;
+ dc->vmsd = &vmstate_rs6000mc;
+ dc->props = rs6000mc_properties;
+}
+
+static const TypeInfo rs6000mc_info = {
+ .name = TYPE_RS6000MC,
+ .parent = TYPE_ISA_DEVICE,
+ .instance_size = sizeof(RS6000MCState),
+ .class_init = rs6000mc_class_initfn,
+};
+
+static void rs6000mc_types(void)
+{
+ type_register_static(&rs6000mc_info);
+}
+
+type_init(rs6000mc_types)
diff --git a/hw/ppc/trace-events b/hw/ppc/trace-events
index 2ba6166..42b8ec0 100644
--- a/hw/ppc/trace-events
+++ b/hw/ppc/trace-events
@@ -78,3 +78,10 @@ prep_io_800_readb(uint32_t addr, uint32_t retval) "0x%08" PRIx32 " <= 0x%02" PRI
# hw/ppc/prep_systemio.c
prep_systemio_read(uint32_t addr, uint32_t val) "read addr=%x val=%x"
prep_systemio_write(uint32_t addr, uint32_t val) "write addr=%x val=%x"
+
+# hw/ppc/rs6000_mc.c
+rs6000mc_id_read(uint32_t addr, uint32_t val) "read addr=%x val=%x"
+rs6000mc_presence_read(uint32_t addr, uint32_t val) "read addr=%x val=%x"
+rs6000mc_size_read(uint32_t addr, uint32_t val) "read addr=%x val=%x"
+rs6000mc_size_write(uint32_t addr, uint32_t val) "write addr=%x val=%x"
+rs6000mc_parity_read(uint32_t addr, uint32_t val) "read addr=%x val=%x"
--
2.9.3
^ permalink raw reply related [flat|nested] 73+ messages in thread
* [Qemu-devel] [PULL 50/67] prep: add IBM RS/6000 7020 (40p) machine emulation
2017-01-12 2:02 [Qemu-devel] [PULL 00/67] ppc-for-2.9 queue 20170112 David Gibson
` (48 preceding siblings ...)
2017-01-12 2:03 ` [Qemu-devel] [PULL 49/67] prep: add IBM RS/6000 7020 (40p) memory controller David Gibson
@ 2017-01-12 2:03 ` David Gibson
2017-01-12 2:03 ` [Qemu-devel] [PULL 51/67] target-ppc: Use float64 arg in helper_compute_fprf() David Gibson
` (18 subsequent siblings)
68 siblings, 0 replies; 73+ messages in thread
From: David Gibson @ 2017-01-12 2:03 UTC (permalink / raw)
To: peter.maydell
Cc: agraf, qemu-ppc, qemu-devel, thuth, lvivier, aik, mdroth,
Hervé Poussineau, David Gibson
From: Hervé Poussineau <hpoussin@reactos.org>
Machine supports both Open Hack'Ware and OpenBIOS.
Open Hack'Ware is the default because OpenBIOS is currently unable to boot
PReP boot partitions or PReP kernels.
Signed-off-by: Hervé Poussineau <hpoussin@reactos.org>
[dwg: Correct compile failure with KVM located by Thomas Huth]
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
default-configs/ppc-softmmu.mak | 1 +
hw/ppc/prep.c | 230 ++++++++++++++++++++++++++++++++++++++++
2 files changed, 231 insertions(+)
diff --git a/default-configs/ppc-softmmu.mak b/default-configs/ppc-softmmu.mak
index e567658..7dd004e 100644
--- a/default-configs/ppc-softmmu.mak
+++ b/default-configs/ppc-softmmu.mak
@@ -18,6 +18,7 @@ CONFIG_I82378=y
CONFIG_PC87312=y
CONFIG_MACIO=y
CONFIG_PCSPK=y
+CONFIG_CS4231A=y
CONFIG_CUDA=y
CONFIG_ADB=y
CONFIG_MAC_NVRAM=y
diff --git a/hw/ppc/prep.c b/hw/ppc/prep.c
index 9fb89d3..ca7959c 100644
--- a/hw/ppc/prep.c
+++ b/hw/ppc/prep.c
@@ -2,6 +2,7 @@
* QEMU PPC PREP hardware System Emulator
*
* Copyright (c) 2003-2007 Jocelyn Mayer
+ * Copyright (c) 2017 Hervé Poussineau
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
@@ -43,17 +44,21 @@
#include "hw/isa/pc87312.h"
#include "sysemu/block-backend.h"
#include "sysemu/arch_init.h"
+#include "sysemu/kvm.h"
#include "sysemu/qtest.h"
#include "exec/address-spaces.h"
#include "trace.h"
#include "elf.h"
#include "qemu/cutils.h"
+#include "kvm_ppc.h"
/* SMP is not enabled, for now */
#define MAX_CPUS 1
#define MAX_IDE_BUS 2
+#define CFG_ADDR 0xf0000510
+
#define BIOS_SIZE (1024 * 1024)
#define BIOS_FILENAME "ppc_rom.bin"
#define KERNEL_LOAD_ADDR 0x01000000
@@ -316,6 +321,12 @@ static uint32_t PREP_io_800_readb (void *opaque, uint32_t addr)
#define NVRAM_SIZE 0x2000
+static void fw_cfg_boot_set(void *opaque, const char *boot_device,
+ Error **errp)
+{
+ fw_cfg_modify_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
+}
+
static void ppc_prep_reset(void *opaque)
{
PowerPCCPU *cpu = opaque;
@@ -677,4 +688,223 @@ static void prep_machine_init(MachineClass *mc)
mc->default_boot_order = "cad";
}
+static int prep_set_cmos_checksum(DeviceState *dev, void *opaque)
+{
+ uint16_t checksum = *(uint16_t *)opaque;
+ ISADevice *rtc;
+
+ if (object_dynamic_cast(OBJECT(dev), "mc146818rtc")) {
+ rtc = ISA_DEVICE(dev);
+ rtc_set_memory(rtc, 0x2e, checksum & 0xff);
+ rtc_set_memory(rtc, 0x3e, checksum & 0xff);
+ rtc_set_memory(rtc, 0x2f, checksum >> 8);
+ rtc_set_memory(rtc, 0x3f, checksum >> 8);
+ }
+ return 0;
+}
+
+static void ibm_40p_init(MachineState *machine)
+{
+ CPUPPCState *env = NULL;
+ uint16_t cmos_checksum;
+ PowerPCCPU *cpu;
+ DeviceState *dev;
+ SysBusDevice *pcihost;
+ Nvram *m48t59 = NULL;
+ PCIBus *pci_bus;
+ ISABus *isa_bus;
+ void *fw_cfg;
+ int i;
+ uint32_t kernel_base = 0, initrd_base = 0;
+ long kernel_size = 0, initrd_size = 0;
+ char boot_device;
+
+ /* init CPU */
+ if (!machine->cpu_model) {
+ machine->cpu_model = "604";
+ }
+ cpu = cpu_ppc_init(machine->cpu_model);
+ if (!cpu) {
+ error_report("could not initialize CPU '%s'",
+ machine->cpu_model);
+ exit(1);
+ }
+ env = &cpu->env;
+ if (PPC_INPUT(env) != PPC_FLAGS_INPUT_6xx) {
+ error_report("only 6xx bus is supported on this machine");
+ exit(1);
+ }
+
+ if (env->flags & POWERPC_FLAG_RTC_CLK) {
+ /* POWER / PowerPC 601 RTC clock frequency is 7.8125 MHz */
+ cpu_ppc_tb_init(env, 7812500UL);
+ } else {
+ /* Set time-base frequency to 100 Mhz */
+ cpu_ppc_tb_init(env, 100UL * 1000UL * 1000UL);
+ }
+ qemu_register_reset(ppc_prep_reset, cpu);
+
+ /* PCI host */
+ dev = qdev_create(NULL, "raven-pcihost");
+ if (!bios_name) {
+ bios_name = BIOS_FILENAME;
+ }
+ qdev_prop_set_string(dev, "bios-name", bios_name);
+ qdev_prop_set_uint32(dev, "elf-machine", PPC_ELF_MACHINE);
+ pcihost = SYS_BUS_DEVICE(dev);
+ object_property_add_child(qdev_get_machine(), "raven", OBJECT(dev), NULL);
+ qdev_init_nofail(dev);
+ pci_bus = PCI_BUS(qdev_get_child_bus(dev, "pci.0"));
+ if (!pci_bus) {
+ error_report("could not create PCI host controller");
+ exit(1);
+ }
+
+ /* PCI -> ISA bridge */
+ dev = DEVICE(pci_create_simple(pci_bus, PCI_DEVFN(11, 0), "i82378"));
+ qdev_connect_gpio_out(dev, 0,
+ cpu->env.irq_inputs[PPC6xx_INPUT_INT]);
+ sysbus_connect_irq(pcihost, 0, qdev_get_gpio_in(dev, 15));
+ sysbus_connect_irq(pcihost, 1, qdev_get_gpio_in(dev, 13));
+ sysbus_connect_irq(pcihost, 2, qdev_get_gpio_in(dev, 15));
+ sysbus_connect_irq(pcihost, 3, qdev_get_gpio_in(dev, 13));
+ isa_bus = ISA_BUS(qdev_get_child_bus(dev, "isa.0"));
+
+ /* Memory controller */
+ dev = DEVICE(isa_create(isa_bus, "rs6000-mc"));
+ qdev_prop_set_uint32(dev, "ram-size", machine->ram_size);
+ qdev_init_nofail(dev);
+
+ /* initialize CMOS checksums */
+ cmos_checksum = 0x6aa9;
+ qbus_walk_children(BUS(isa_bus), prep_set_cmos_checksum, NULL, NULL, NULL,
+ &cmos_checksum);
+
+ /* initialize audio subsystem */
+ audio_init();
+
+ /* add some more devices */
+ if (defaults_enabled()) {
+ isa_create_simple(isa_bus, "i8042");
+ m48t59 = NVRAM(isa_create_simple(isa_bus, "isa-m48t59"));
+
+ dev = DEVICE(isa_create(isa_bus, "cs4231a"));
+ qdev_prop_set_uint32(dev, "iobase", 0x830);
+ qdev_prop_set_uint32(dev, "irq", 10);
+ qdev_init_nofail(dev);
+
+ dev = DEVICE(isa_create(isa_bus, "pc87312"));
+ qdev_prop_set_uint32(dev, "config", 12);
+ qdev_init_nofail(dev);
+
+ dev = DEVICE(isa_create(isa_bus, "prep-systemio"));
+ qdev_prop_set_uint32(dev, "ibm-planar-id", 0xfc);
+ qdev_prop_set_uint32(dev, "equipment", 0xc0);
+ qdev_init_nofail(dev);
+
+ pci_create_simple(pci_bus, PCI_DEVFN(1, 0), "lsi53c810");
+
+ /* XXX: s3-trio at PCI_DEVFN(2, 0) */
+ pci_vga_init(pci_bus);
+
+ for (i = 0; i < nb_nics; i++) {
+ pci_nic_init_nofail(&nd_table[i], pci_bus, "pcnet",
+ i == 0 ? "3" : NULL);
+ }
+ }
+
+ /* Prepare firmware configuration for OpenBIOS */
+ fw_cfg = fw_cfg_init_mem(CFG_ADDR, CFG_ADDR + 2);
+
+ if (machine->kernel_filename) {
+ /* load kernel */
+ kernel_base = KERNEL_LOAD_ADDR;
+ kernel_size = load_image_targphys(machine->kernel_filename,
+ kernel_base,
+ machine->ram_size - kernel_base);
+ if (kernel_size < 0) {
+ error_report("could not load kernel '%s'",
+ machine->kernel_filename);
+ exit(1);
+ }
+ fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, kernel_base);
+ fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
+ /* load initrd */
+ if (machine->initrd_filename) {
+ initrd_base = INITRD_LOAD_ADDR;
+ initrd_size = load_image_targphys(machine->initrd_filename,
+ initrd_base,
+ machine->ram_size - initrd_base);
+ if (initrd_size < 0) {
+ error_report("could not load initial ram disk '%s'",
+ machine->initrd_filename);
+ exit(1);
+ }
+ fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_base);
+ fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size);
+ }
+ if (machine->kernel_cmdline && *machine->kernel_cmdline) {
+ fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR);
+ pstrcpy_targphys("cmdline", CMDLINE_ADDR, TARGET_PAGE_SIZE,
+ machine->kernel_cmdline);
+ fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA,
+ machine->kernel_cmdline);
+ fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE,
+ strlen(machine->kernel_cmdline) + 1);
+ }
+ boot_device = 'm';
+ } else {
+ boot_device = machine->boot_order[0];
+ }
+
+ fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)max_cpus);
+ fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)machine->ram_size);
+ fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, ARCH_PREP);
+
+ fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_WIDTH, graphic_width);
+ fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_HEIGHT, graphic_height);
+ fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_DEPTH, graphic_depth);
+
+ fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_IS_KVM, kvm_enabled());
+ if (kvm_enabled()) {
+#ifdef CONFIG_KVM
+ uint8_t *hypercall;
+
+ fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_TBFREQ, kvmppc_get_tbfreq());
+ hypercall = g_malloc(16);
+ kvmppc_get_hypercall(env, hypercall, 16);
+ fw_cfg_add_bytes(fw_cfg, FW_CFG_PPC_KVM_HC, hypercall, 16);
+ fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_KVM_PID, getpid());
+#endif
+ } else {
+ fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_TBFREQ, NANOSECONDS_PER_SECOND);
+ }
+ fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_device);
+ qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
+
+ /* Prepare firmware configuration for Open Hack'Ware */
+ if (m48t59) {
+ PPC_NVRAM_set_params(m48t59, NVRAM_SIZE, "PREP", ram_size,
+ boot_device,
+ kernel_base, kernel_size,
+ machine->kernel_cmdline,
+ initrd_base, initrd_size,
+ /* XXX: need an option to load a NVRAM image */
+ 0,
+ graphic_width, graphic_height, graphic_depth);
+ }
+}
+
+static void ibm_40p_machine_init(MachineClass *mc)
+{
+ mc->desc = "IBM RS/6000 7020 (40p)",
+ mc->init = ibm_40p_init;
+ mc->max_cpus = 1;
+ mc->pci_allow_0_address = true;
+ mc->default_ram_size = 128 * M_BYTE;
+ mc->block_default_type = IF_SCSI;
+ mc->default_boot_order = "c";
+}
+
+DEFINE_MACHINE("40p", ibm_40p_machine_init)
DEFINE_MACHINE("prep", prep_machine_init)
--
2.9.3
^ permalink raw reply related [flat|nested] 73+ messages in thread
* [Qemu-devel] [PULL 51/67] target-ppc: Use float64 arg in helper_compute_fprf()
2017-01-12 2:02 [Qemu-devel] [PULL 00/67] ppc-for-2.9 queue 20170112 David Gibson
` (49 preceding siblings ...)
2017-01-12 2:03 ` [Qemu-devel] [PULL 50/67] prep: add IBM RS/6000 7020 (40p) machine emulation David Gibson
@ 2017-01-12 2:03 ` David Gibson
2017-01-12 2:03 ` [Qemu-devel] [PULL 52/67] target-ppc: Replace isden by float64_is_zero_or_denormal David Gibson
` (17 subsequent siblings)
68 siblings, 0 replies; 73+ messages in thread
From: David Gibson @ 2017-01-12 2:03 UTC (permalink / raw)
To: peter.maydell
Cc: agraf, qemu-ppc, qemu-devel, thuth, lvivier, aik, mdroth,
Bharata B Rao, Nikunj A Dadhania, David Gibson
From: Bharata B Rao <bharata@linux.vnet.ibm.com>
Use float64 argument instead of unit64_t in helper_compute_fprf()
This allows code in helper_compute_fprf() to be reused later to
work with float128 argument too.
Signed-off-by: Bharata B Rao <bharata@linux.vnet.ibm.com>
Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
target/ppc/fpu_helper.c | 16 +++++++---------
1 file changed, 7 insertions(+), 9 deletions(-)
diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c
index 1ccd5e6..4da991a 100644
--- a/target/ppc/fpu_helper.c
+++ b/target/ppc/fpu_helper.c
@@ -66,23 +66,21 @@ static inline int ppc_float64_get_unbiased_exp(float64 f)
return ((f >> 52) & 0x7FF) - 1023;
}
-void helper_compute_fprf(CPUPPCState *env, uint64_t arg)
+void helper_compute_fprf(CPUPPCState *env, float64 arg)
{
- CPU_DoubleU farg;
int isneg;
int fprf;
- farg.ll = arg;
- isneg = float64_is_neg(farg.d);
- if (unlikely(float64_is_any_nan(farg.d))) {
- if (float64_is_signaling_nan(farg.d, &env->fp_status)) {
+ isneg = float64_is_neg(arg);
+ if (unlikely(float64_is_any_nan(arg))) {
+ if (float64_is_signaling_nan(arg, &env->fp_status)) {
/* Signaling NaN: flags are undefined */
fprf = 0x00;
} else {
/* Quiet NaN */
fprf = 0x11;
}
- } else if (unlikely(float64_is_infinity(farg.d))) {
+ } else if (unlikely(float64_is_infinity(arg))) {
/* +/- infinity */
if (isneg) {
fprf = 0x09;
@@ -90,7 +88,7 @@ void helper_compute_fprf(CPUPPCState *env, uint64_t arg)
fprf = 0x05;
}
} else {
- if (float64_is_zero(farg.d)) {
+ if (float64_is_zero(arg)) {
/* +/- zero */
if (isneg) {
fprf = 0x12;
@@ -98,7 +96,7 @@ void helper_compute_fprf(CPUPPCState *env, uint64_t arg)
fprf = 0x02;
}
} else {
- if (isden(farg.d)) {
+ if (isden(arg)) {
/* Denormalized numbers */
fprf = 0x10;
} else {
--
2.9.3
^ permalink raw reply related [flat|nested] 73+ messages in thread
* [Qemu-devel] [PULL 52/67] target-ppc: Replace isden by float64_is_zero_or_denormal
2017-01-12 2:02 [Qemu-devel] [PULL 00/67] ppc-for-2.9 queue 20170112 David Gibson
` (50 preceding siblings ...)
2017-01-12 2:03 ` [Qemu-devel] [PULL 51/67] target-ppc: Use float64 arg in helper_compute_fprf() David Gibson
@ 2017-01-12 2:03 ` David Gibson
2017-01-12 2:03 ` [Qemu-devel] [PULL 53/67] target-ppc: Rename helper_compute_fprf to helper_compute_fprf_float64 David Gibson
` (16 subsequent siblings)
68 siblings, 0 replies; 73+ messages in thread
From: David Gibson @ 2017-01-12 2:03 UTC (permalink / raw)
To: peter.maydell
Cc: agraf, qemu-ppc, qemu-devel, thuth, lvivier, aik, mdroth,
Bharata B Rao, Nikunj A Dadhania, David Gibson
From: Bharata B Rao <bharata@linux.vnet.ibm.com>
Replace isden() by float64_is_zero_or_denormal() so that code in
helper_compute_fprf() can be reused to work with float128 argument.
Signed-off-by: Bharata B Rao <bharata@linux.vnet.ibm.com>
Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
target/ppc/fpu_helper.c | 11 +----------
1 file changed, 1 insertion(+), 10 deletions(-)
diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c
index 4da991a..5a7aa75 100644
--- a/target/ppc/fpu_helper.c
+++ b/target/ppc/fpu_helper.c
@@ -47,15 +47,6 @@ uint32_t helper_float64_to_float32(CPUPPCState *env, uint64_t arg)
return f.l;
}
-static inline int isden(float64 d)
-{
- CPU_DoubleU u;
-
- u.d = d;
-
- return ((u.ll >> 52) & 0x7FF) == 0;
-}
-
static inline int ppc_float32_get_unbiased_exp(float32 f)
{
return ((f >> 23) & 0xFF) - 127;
@@ -96,7 +87,7 @@ void helper_compute_fprf(CPUPPCState *env, float64 arg)
fprf = 0x02;
}
} else {
- if (isden(arg)) {
+ if (float64_is_zero_or_denormal(arg)) {
/* Denormalized numbers */
fprf = 0x10;
} else {
--
2.9.3
^ permalink raw reply related [flat|nested] 73+ messages in thread
* [Qemu-devel] [PULL 53/67] target-ppc: Rename helper_compute_fprf to helper_compute_fprf_float64
2017-01-12 2:02 [Qemu-devel] [PULL 00/67] ppc-for-2.9 queue 20170112 David Gibson
` (51 preceding siblings ...)
2017-01-12 2:03 ` [Qemu-devel] [PULL 52/67] target-ppc: Replace isden by float64_is_zero_or_denormal David Gibson
@ 2017-01-12 2:03 ` David Gibson
2017-01-12 2:03 ` [Qemu-devel] [PULL 54/67] target-ppc: Add xscvdphp, xscvhpdp David Gibson
` (15 subsequent siblings)
68 siblings, 0 replies; 73+ messages in thread
From: David Gibson @ 2017-01-12 2:03 UTC (permalink / raw)
To: peter.maydell
Cc: agraf, qemu-ppc, qemu-devel, thuth, lvivier, aik, mdroth,
Bharata B Rao, Nikunj A Dadhania, David Gibson
From: Bharata B Rao <bharata@linux.vnet.ibm.com>
Since helper_compute_fprf() works on float64 argument, rename it
to helper_compute_fprf_float64(). Also use a macro to generate
helper_compute_fprf_float64() so that float128 version of the same
helper can be introduced easily later.
Signed-off-by: Bharata B Rao <bharata@linux.vnet.ibm.com>
Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
target/ppc/fpu_helper.c | 121 +++++++++++++++++++------------------
target/ppc/helper.h | 2 +-
target/ppc/translate/fp-impl.inc.c | 20 +++---
3 files changed, 73 insertions(+), 70 deletions(-)
diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c
index 5a7aa75..913d54e 100644
--- a/target/ppc/fpu_helper.c
+++ b/target/ppc/fpu_helper.c
@@ -57,54 +57,57 @@ static inline int ppc_float64_get_unbiased_exp(float64 f)
return ((f >> 52) & 0x7FF) - 1023;
}
-void helper_compute_fprf(CPUPPCState *env, float64 arg)
-{
- int isneg;
- int fprf;
-
- isneg = float64_is_neg(arg);
- if (unlikely(float64_is_any_nan(arg))) {
- if (float64_is_signaling_nan(arg, &env->fp_status)) {
- /* Signaling NaN: flags are undefined */
- fprf = 0x00;
- } else {
- /* Quiet NaN */
- fprf = 0x11;
- }
- } else if (unlikely(float64_is_infinity(arg))) {
- /* +/- infinity */
- if (isneg) {
- fprf = 0x09;
- } else {
- fprf = 0x05;
- }
- } else {
- if (float64_is_zero(arg)) {
- /* +/- zero */
- if (isneg) {
- fprf = 0x12;
- } else {
- fprf = 0x02;
- }
- } else {
- if (float64_is_zero_or_denormal(arg)) {
- /* Denormalized numbers */
- fprf = 0x10;
- } else {
- /* Normalized numbers */
- fprf = 0x00;
- }
- if (isneg) {
- fprf |= 0x08;
- } else {
- fprf |= 0x04;
- }
- }
- }
- /* We update FPSCR_FPRF */
- env->fpscr &= ~(0x1F << FPSCR_FPRF);
- env->fpscr |= fprf << FPSCR_FPRF;
-}
+#define COMPUTE_FPRF(tp) \
+void helper_compute_fprf_##tp(CPUPPCState *env, tp arg) \
+{ \
+ int isneg; \
+ int fprf; \
+ \
+ isneg = tp##_is_neg(arg); \
+ if (unlikely(tp##_is_any_nan(arg))) { \
+ if (tp##_is_signaling_nan(arg, &env->fp_status)) { \
+ /* Signaling NaN: flags are undefined */ \
+ fprf = 0x00; \
+ } else { \
+ /* Quiet NaN */ \
+ fprf = 0x11; \
+ } \
+ } else if (unlikely(tp##_is_infinity(arg))) { \
+ /* +/- infinity */ \
+ if (isneg) { \
+ fprf = 0x09; \
+ } else { \
+ fprf = 0x05; \
+ } \
+ } else { \
+ if (tp##_is_zero(arg)) { \
+ /* +/- zero */ \
+ if (isneg) { \
+ fprf = 0x12; \
+ } else { \
+ fprf = 0x02; \
+ } \
+ } else { \
+ if (tp##_is_zero_or_denormal(arg)) { \
+ /* Denormalized numbers */ \
+ fprf = 0x10; \
+ } else { \
+ /* Normalized numbers */ \
+ fprf = 0x00; \
+ } \
+ if (isneg) { \
+ fprf |= 0x08; \
+ } else { \
+ fprf |= 0x04; \
+ } \
+ } \
+ } \
+ /* We update FPSCR_FPRF */ \
+ env->fpscr &= ~(0x1F << FPSCR_FPRF); \
+ env->fpscr |= fprf << FPSCR_FPRF; \
+}
+
+COMPUTE_FPRF(float64)
/* Floating-point invalid operations exception */
static inline __attribute__((__always_inline__))
@@ -1808,7 +1811,7 @@ void helper_##name(CPUPPCState *env, uint32_t opcode) \
} \
\
if (sfprf) { \
- helper_compute_fprf(env, xt.fld); \
+ helper_compute_fprf_float64(env, xt.fld); \
} \
} \
putVSR(xT(opcode), &xt, env); \
@@ -1863,7 +1866,7 @@ void helper_##op(CPUPPCState *env, uint32_t opcode) \
} \
\
if (sfprf) { \
- helper_compute_fprf(env, xt.fld); \
+ helper_compute_fprf_float64(env, xt.fld); \
} \
} \
\
@@ -1917,7 +1920,7 @@ void helper_##op(CPUPPCState *env, uint32_t opcode) \
} \
\
if (sfprf) { \
- helper_compute_fprf(env, xt.fld); \
+ helper_compute_fprf_float64(env, xt.fld); \
} \
} \
\
@@ -1958,7 +1961,7 @@ void helper_##op(CPUPPCState *env, uint32_t opcode) \
} \
\
if (sfprf) { \
- helper_compute_fprf(env, xt.fld); \
+ helper_compute_fprf_float64(env, xt.fld); \
} \
} \
\
@@ -2007,7 +2010,7 @@ void helper_##op(CPUPPCState *env, uint32_t opcode) \
} \
\
if (sfprf) { \
- helper_compute_fprf(env, xt.fld); \
+ helper_compute_fprf_float64(env, xt.fld); \
} \
} \
\
@@ -2057,7 +2060,7 @@ void helper_##op(CPUPPCState *env, uint32_t opcode) \
} \
\
if (sfprf) { \
- helper_compute_fprf(env, xt.fld); \
+ helper_compute_fprf_float64(env, xt.fld); \
} \
} \
\
@@ -2257,7 +2260,7 @@ void helper_##op(CPUPPCState *env, uint32_t opcode) \
} \
\
if (sfprf) { \
- helper_compute_fprf(env, xt_out.fld); \
+ helper_compute_fprf_float64(env, xt_out.fld); \
} \
} \
putVSR(xT(opcode), &xt_out, env); \
@@ -2647,7 +2650,7 @@ void helper_##op(CPUPPCState *env, uint32_t opcode) \
xt.tfld = ttp##_snan_to_qnan(xt.tfld); \
} \
if (sfprf) { \
- helper_compute_fprf(env, ttp##_to_float64(xt.tfld, \
+ helper_compute_fprf_float64(env, ttp##_to_float64(xt.tfld, \
&env->fp_status)); \
} \
} \
@@ -2758,7 +2761,7 @@ void helper_##op(CPUPPCState *env, uint32_t opcode) \
xt.tfld = helper_frsp(env, xt.tfld); \
} \
if (sfprf) { \
- helper_compute_fprf(env, xt.tfld); \
+ helper_compute_fprf_float64(env, xt.tfld); \
} \
} \
\
@@ -2814,7 +2817,7 @@ void helper_##op(CPUPPCState *env, uint32_t opcode) \
xt.fld = tp##_round_to_int(xb.fld, &env->fp_status); \
} \
if (sfprf) { \
- helper_compute_fprf(env, xt.fld); \
+ helper_compute_fprf_float64(env, xt.fld); \
} \
} \
\
@@ -2854,7 +2857,7 @@ uint64_t helper_xsrsp(CPUPPCState *env, uint64_t xb)
uint64_t xt = helper_frsp(env, xb);
- helper_compute_fprf(env, xt);
+ helper_compute_fprf_float64(env, xt);
float_check_status(env);
return xt;
}
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index 6c5b194..04e688d 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -61,7 +61,7 @@ DEF_HELPER_FLAGS_2(brinc, TCG_CALL_NO_RWG_SE, tl, tl, tl)
DEF_HELPER_1(float_check_status, void, env)
DEF_HELPER_1(reset_fpstatus, void, env)
-DEF_HELPER_2(compute_fprf, void, env, i64)
+DEF_HELPER_2(compute_fprf_float64, void, env, i64)
DEF_HELPER_3(store_fpscr, void, env, i64, i32)
DEF_HELPER_2(fpscr_clrbit, void, env, i32)
DEF_HELPER_2(fpscr_setbit, void, env, i32)
diff --git a/target/ppc/translate/fp-impl.inc.c b/target/ppc/translate/fp-impl.inc.c
index 872af7b..2fbd4d4 100644
--- a/target/ppc/translate/fp-impl.inc.c
+++ b/target/ppc/translate/fp-impl.inc.c
@@ -9,9 +9,9 @@ static inline void gen_reset_fpstatus(void)
gen_helper_reset_fpstatus(cpu_env);
}
-static inline void gen_compute_fprf(TCGv_i64 arg)
+static inline void gen_compute_fprf_float64(TCGv_i64 arg)
{
- gen_helper_compute_fprf(cpu_env, arg);
+ gen_helper_compute_fprf_float64(cpu_env, arg);
gen_helper_float_check_status(cpu_env);
}
@@ -47,7 +47,7 @@ static void gen_f##name(DisasContext *ctx) \
cpu_fpr[rD(ctx->opcode)]); \
} \
if (set_fprf) { \
- gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]); \
+ gen_compute_fprf_float64(cpu_fpr[rD(ctx->opcode)]); \
} \
if (unlikely(Rc(ctx->opcode) != 0)) { \
gen_set_cr1_from_fpscr(ctx); \
@@ -74,7 +74,7 @@ static void gen_f##name(DisasContext *ctx) \
cpu_fpr[rD(ctx->opcode)]); \
} \
if (set_fprf) { \
- gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]); \
+ gen_compute_fprf_float64(cpu_fpr[rD(ctx->opcode)]); \
} \
if (unlikely(Rc(ctx->opcode) != 0)) { \
gen_set_cr1_from_fpscr(ctx); \
@@ -100,7 +100,7 @@ static void gen_f##name(DisasContext *ctx) \
cpu_fpr[rD(ctx->opcode)]); \
} \
if (set_fprf) { \
- gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]); \
+ gen_compute_fprf_float64(cpu_fpr[rD(ctx->opcode)]); \
} \
if (unlikely(Rc(ctx->opcode) != 0)) { \
gen_set_cr1_from_fpscr(ctx); \
@@ -121,7 +121,7 @@ static void gen_f##name(DisasContext *ctx) \
gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_env, \
cpu_fpr[rB(ctx->opcode)]); \
if (set_fprf) { \
- gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]); \
+ gen_compute_fprf_float64(cpu_fpr[rD(ctx->opcode)]); \
} \
if (unlikely(Rc(ctx->opcode) != 0)) { \
gen_set_cr1_from_fpscr(ctx); \
@@ -139,7 +139,7 @@ static void gen_f##name(DisasContext *ctx) \
gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_env, \
cpu_fpr[rB(ctx->opcode)]); \
if (set_fprf) { \
- gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]); \
+ gen_compute_fprf_float64(cpu_fpr[rD(ctx->opcode)]); \
} \
if (unlikely(Rc(ctx->opcode) != 0)) { \
gen_set_cr1_from_fpscr(ctx); \
@@ -174,7 +174,7 @@ static void gen_frsqrtes(DisasContext *ctx)
cpu_fpr[rB(ctx->opcode)]);
gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env,
cpu_fpr[rD(ctx->opcode)]);
- gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]);
+ gen_compute_fprf_float64(cpu_fpr[rD(ctx->opcode)]);
if (unlikely(Rc(ctx->opcode) != 0)) {
gen_set_cr1_from_fpscr(ctx);
}
@@ -196,7 +196,7 @@ static void gen_fsqrt(DisasContext *ctx)
gen_reset_fpstatus();
gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_env,
cpu_fpr[rB(ctx->opcode)]);
- gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]);
+ gen_compute_fprf_float64(cpu_fpr[rD(ctx->opcode)]);
if (unlikely(Rc(ctx->opcode) != 0)) {
gen_set_cr1_from_fpscr(ctx);
}
@@ -213,7 +213,7 @@ static void gen_fsqrts(DisasContext *ctx)
cpu_fpr[rB(ctx->opcode)]);
gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env,
cpu_fpr[rD(ctx->opcode)]);
- gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]);
+ gen_compute_fprf_float64(cpu_fpr[rD(ctx->opcode)]);
if (unlikely(Rc(ctx->opcode) != 0)) {
gen_set_cr1_from_fpscr(ctx);
}
--
2.9.3
^ permalink raw reply related [flat|nested] 73+ messages in thread
* [Qemu-devel] [PULL 54/67] target-ppc: Add xscvdphp, xscvhpdp
2017-01-12 2:02 [Qemu-devel] [PULL 00/67] ppc-for-2.9 queue 20170112 David Gibson
` (52 preceding siblings ...)
2017-01-12 2:03 ` [Qemu-devel] [PULL 53/67] target-ppc: Rename helper_compute_fprf to helper_compute_fprf_float64 David Gibson
@ 2017-01-12 2:03 ` David Gibson
2017-01-12 2:03 ` [Qemu-devel] [PULL 55/67] target-ppc: Use correct precision for FPRF setting David Gibson
` (14 subsequent siblings)
68 siblings, 0 replies; 73+ messages in thread
From: David Gibson @ 2017-01-12 2:03 UTC (permalink / raw)
To: peter.maydell
Cc: agraf, qemu-ppc, qemu-devel, thuth, lvivier, aik, mdroth,
Bharata B Rao, Nikunj A Dadhania, David Gibson
From: Bharata B Rao <bharata@linux.vnet.ibm.com>
xscvdphp: VSX Scalar round & Convert Double-Precision format to
Half-Precision format
xscvhpdp: VSX Scalar Convert Half-Precision format to
Double-Precision format
Signed-off-by: Bharata B Rao <bharata@linux.vnet.ibm.com>
Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
include/fpu/softfloat.h | 20 ++++++++++++++++++++
target/ppc/fpu_helper.c | 33 +++++++++++++++++++++++++++++++++
target/ppc/helper.h | 2 ++
target/ppc/internal.h | 3 +++
target/ppc/translate/vsx-impl.inc.c | 2 ++
target/ppc/translate/vsx-ops.inc.c | 2 ++
6 files changed, 62 insertions(+)
diff --git a/include/fpu/softfloat.h b/include/fpu/softfloat.h
index 14f8383..842ec6b 100644
--- a/include/fpu/softfloat.h
+++ b/include/fpu/softfloat.h
@@ -356,6 +356,26 @@ static inline int float16_is_any_nan(float16 a)
return ((float16_val(a) & ~0x8000) > 0x7c00);
}
+static inline int float16_is_neg(float16 a)
+{
+ return float16_val(a) >> 15;
+}
+
+static inline int float16_is_infinity(float16 a)
+{
+ return (float16_val(a) & 0x7fff) == 0x7c00;
+}
+
+static inline int float16_is_zero(float16 a)
+{
+ return (float16_val(a) & 0x7fff) == 0;
+}
+
+static inline int float16_is_zero_or_denormal(float16 a)
+{
+ return (float16_val(a) & 0x7c00) == 0;
+}
+
/*----------------------------------------------------------------------------
| The pattern for a default generated half-precision NaN.
*----------------------------------------------------------------------------*/
diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c
index 913d54e..f4103f5 100644
--- a/target/ppc/fpu_helper.c
+++ b/target/ppc/fpu_helper.c
@@ -24,6 +24,7 @@
#define float64_snan_to_qnan(x) ((x) | 0x0008000000000000ULL)
#define float32_snan_to_qnan(x) ((x) | 0x00400000)
+#define float16_snan_to_qnan(x) ((x) | 0x0200)
/*****************************************************************************/
/* Floating point operations helpers */
@@ -107,6 +108,7 @@ void helper_compute_fprf_##tp(CPUPPCState *env, tp arg) \
env->fpscr |= fprf << FPSCR_FPRF; \
}
+COMPUTE_FPRF(float16)
COMPUTE_FPRF(float64)
/* Floating-point invalid operations exception */
@@ -2664,6 +2666,37 @@ VSX_CVT_FP_TO_FP(xscvspdp, 1, float32, float64, VsrW(0), VsrD(0), 1)
VSX_CVT_FP_TO_FP(xvcvdpsp, 2, float64, float32, VsrD(i), VsrW(2*i), 0)
VSX_CVT_FP_TO_FP(xvcvspdp, 2, float32, float64, VsrW(2*i), VsrD(i), 0)
+/* VSX_CVT_FP_TO_FP_HP - VSX floating point/floating point conversion
+ * involving one half precision value
+ * op - instruction mnemonic
+ * stp - source type
+ * ttp - target type
+ * sfld - source vsr_t field
+ * tfld - target vsr_t field
+ */
+#define VSX_CVT_FP_TO_FP_HP(op, stp, ttp, sfld, tfld) \
+void helper_##op(CPUPPCState *env, uint32_t opcode) \
+{ \
+ ppc_vsr_t xt, xb; \
+ \
+ getVSR(xB(opcode), &xb, env); \
+ memset(&xt, 0, sizeof(xt)); \
+ \
+ xt.tfld = stp##_to_##ttp(xb.sfld, 1, &env->fp_status); \
+ if (unlikely(stp##_is_signaling_nan(xb.sfld, \
+ &env->fp_status))) { \
+ float_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 0); \
+ xt.tfld = ttp##_snan_to_qnan(xt.tfld); \
+ } \
+ helper_compute_fprf_##ttp(env, xt.tfld); \
+ \
+ putVSR(xT(opcode), &xt, env); \
+ float_check_status(env); \
+}
+
+VSX_CVT_FP_TO_FP_HP(xscvdphp, float64, float16, VsrD(0), VsrH(3))
+VSX_CVT_FP_TO_FP_HP(xscvhpdp, float16, float64, VsrH(3), VsrD(0))
+
uint64_t helper_xscvdpspn(CPUPPCState *env, uint64_t xb)
{
float_status tstat = env->fp_status;
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index 04e688d..5f290c6 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -428,8 +428,10 @@ DEF_HELPER_2(xscmpoqp, void, env, i32)
DEF_HELPER_2(xscmpuqp, void, env, i32)
DEF_HELPER_2(xsmaxdp, void, env, i32)
DEF_HELPER_2(xsmindp, void, env, i32)
+DEF_HELPER_2(xscvdphp, void, env, i32)
DEF_HELPER_2(xscvdpsp, void, env, i32)
DEF_HELPER_2(xscvdpspn, i64, env, i64)
+DEF_HELPER_2(xscvhpdp, void, env, i32)
DEF_HELPER_2(xscvspdp, void, env, i32)
DEF_HELPER_2(xscvspdpn, i64, env, i64)
DEF_HELPER_2(xscvdpsxds, void, env, i32)
diff --git a/target/ppc/internal.h b/target/ppc/internal.h
index 66cde46..1e27209 100644
--- a/target/ppc/internal.h
+++ b/target/ppc/internal.h
@@ -211,10 +211,12 @@ typedef union _ppc_vsr_t {
#if defined(HOST_WORDS_BIGENDIAN)
#define VsrB(i) u8[i]
+#define VsrH(i) u16[i]
#define VsrW(i) u32[i]
#define VsrD(i) u64[i]
#else
#define VsrB(i) u8[15 - (i)]
+#define VsrH(i) u16[7 - (i)]
#define VsrW(i) u32[3 - (i)]
#define VsrD(i) u64[1 - (i)]
#endif
@@ -241,4 +243,5 @@ static inline void putVSR(int n, ppc_vsr_t *vsr, CPUPPCState *env)
}
}
+void helper_compute_fprf_float16(CPUPPCState *env, float16 arg);
#endif /* PPC_INTERNAL_H */
diff --git a/target/ppc/translate/vsx-impl.inc.c b/target/ppc/translate/vsx-impl.inc.c
index c9ba0f5..2a409a3 100644
--- a/target/ppc/translate/vsx-impl.inc.c
+++ b/target/ppc/translate/vsx-impl.inc.c
@@ -805,8 +805,10 @@ GEN_VSX_HELPER_2(xscmpoqp, 0x04, 0x04, 0, PPC2_VSX)
GEN_VSX_HELPER_2(xscmpuqp, 0x04, 0x14, 0, PPC2_VSX)
GEN_VSX_HELPER_2(xsmaxdp, 0x00, 0x14, 0, PPC2_VSX)
GEN_VSX_HELPER_2(xsmindp, 0x00, 0x15, 0, PPC2_VSX)
+GEN_VSX_HELPER_2(xscvdphp, 0x16, 0x15, 0x11, PPC2_ISA300)
GEN_VSX_HELPER_2(xscvdpsp, 0x12, 0x10, 0, PPC2_VSX)
GEN_VSX_HELPER_XT_XB_ENV(xscvdpspn, 0x16, 0x10, 0, PPC2_VSX207)
+GEN_VSX_HELPER_2(xscvhpdp, 0x16, 0x15, 0x10, PPC2_ISA300)
GEN_VSX_HELPER_2(xscvspdp, 0x12, 0x14, 0, PPC2_VSX)
GEN_VSX_HELPER_XT_XB_ENV(xscvspdpn, 0x16, 0x14, 0, PPC2_VSX207)
GEN_VSX_HELPER_2(xscvdpsxds, 0x10, 0x15, 0, PPC2_VSX)
diff --git a/target/ppc/translate/vsx-ops.inc.c b/target/ppc/translate/vsx-ops.inc.c
index 096d358..5c01aed 100644
--- a/target/ppc/translate/vsx-ops.inc.c
+++ b/target/ppc/translate/vsx-ops.inc.c
@@ -151,8 +151,10 @@ GEN_VSX_XFORM_300(xscmpoqp, 0x04, 0x04, 0x00600001),
GEN_VSX_XFORM_300(xscmpuqp, 0x04, 0x14, 0x00600001),
GEN_XX3FORM(xsmaxdp, 0x00, 0x14, PPC2_VSX),
GEN_XX3FORM(xsmindp, 0x00, 0x15, PPC2_VSX),
+GEN_XX2FORM_EO(xscvdphp, 0x16, 0x15, 0x11, PPC2_ISA300),
GEN_XX2FORM(xscvdpsp, 0x12, 0x10, PPC2_VSX),
GEN_XX2FORM(xscvdpspn, 0x16, 0x10, PPC2_VSX207),
+GEN_XX2FORM_EO(xscvhpdp, 0x16, 0x15, 0x10, PPC2_ISA300),
GEN_XX2FORM(xscvspdp, 0x12, 0x14, PPC2_VSX),
GEN_XX2FORM(xscvspdpn, 0x16, 0x14, PPC2_VSX207),
GEN_XX2FORM(xscvdpsxds, 0x10, 0x15, PPC2_VSX),
--
2.9.3
^ permalink raw reply related [flat|nested] 73+ messages in thread
* [Qemu-devel] [PULL 55/67] target-ppc: Use correct precision for FPRF setting
2017-01-12 2:02 [Qemu-devel] [PULL 00/67] ppc-for-2.9 queue 20170112 David Gibson
` (53 preceding siblings ...)
2017-01-12 2:03 ` [Qemu-devel] [PULL 54/67] target-ppc: Add xscvdphp, xscvhpdp David Gibson
@ 2017-01-12 2:03 ` David Gibson
2017-01-12 2:03 ` [Qemu-devel] [PULL 56/67] target-ppc: Add xsxexpdp instruction David Gibson
` (13 subsequent siblings)
68 siblings, 0 replies; 73+ messages in thread
From: David Gibson @ 2017-01-12 2:03 UTC (permalink / raw)
To: peter.maydell
Cc: agraf, qemu-ppc, qemu-devel, thuth, lvivier, aik, mdroth,
Bharata B Rao, Nikunj A Dadhania, David Gibson
From: Bharata B Rao <bharata@linux.vnet.ibm.com>
Use correct FP precision when setting FPRF in FP conversion helpers
instead of always assuming float64 precision.
Signed-off-by: Bharata B Rao <bharata@linux.vnet.ibm.com>
Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
target/ppc/fpu_helper.c | 4 ++--
target/ppc/internal.h | 1 +
2 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c
index f4103f5..01b335f 100644
--- a/target/ppc/fpu_helper.c
+++ b/target/ppc/fpu_helper.c
@@ -109,6 +109,7 @@ void helper_compute_fprf_##tp(CPUPPCState *env, tp arg) \
}
COMPUTE_FPRF(float16)
+COMPUTE_FPRF(float32)
COMPUTE_FPRF(float64)
/* Floating-point invalid operations exception */
@@ -2652,8 +2653,7 @@ void helper_##op(CPUPPCState *env, uint32_t opcode) \
xt.tfld = ttp##_snan_to_qnan(xt.tfld); \
} \
if (sfprf) { \
- helper_compute_fprf_float64(env, ttp##_to_float64(xt.tfld, \
- &env->fp_status)); \
+ helper_compute_fprf_##ttp(env, xt.tfld); \
} \
} \
\
diff --git a/target/ppc/internal.h b/target/ppc/internal.h
index 1e27209..187f024 100644
--- a/target/ppc/internal.h
+++ b/target/ppc/internal.h
@@ -244,4 +244,5 @@ static inline void putVSR(int n, ppc_vsr_t *vsr, CPUPPCState *env)
}
void helper_compute_fprf_float16(CPUPPCState *env, float16 arg);
+void helper_compute_fprf_float32(CPUPPCState *env, float32 arg);
#endif /* PPC_INTERNAL_H */
--
2.9.3
^ permalink raw reply related [flat|nested] 73+ messages in thread
* [Qemu-devel] [PULL 56/67] target-ppc: Add xsxexpdp instruction
2017-01-12 2:02 [Qemu-devel] [PULL 00/67] ppc-for-2.9 queue 20170112 David Gibson
` (54 preceding siblings ...)
2017-01-12 2:03 ` [Qemu-devel] [PULL 55/67] target-ppc: Use correct precision for FPRF setting David Gibson
@ 2017-01-12 2:03 ` David Gibson
2017-01-12 2:03 ` [Qemu-devel] [PULL 57/67] target-ppc: Add xsxexpqp instruction David Gibson
` (12 subsequent siblings)
68 siblings, 0 replies; 73+ messages in thread
From: David Gibson @ 2017-01-12 2:03 UTC (permalink / raw)
To: peter.maydell
Cc: agraf, qemu-ppc, qemu-devel, thuth, lvivier, aik, mdroth,
Nikunj A Dadhania, David Gibson
From: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
xsxexpdp: VSX Scalar Extract Exponent Dual Precision
Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
target/ppc/translate/vsx-impl.inc.c | 13 +++++++++++++
target/ppc/translate/vsx-ops.inc.c | 4 ++++
2 files changed, 17 insertions(+)
diff --git a/target/ppc/translate/vsx-impl.inc.c b/target/ppc/translate/vsx-impl.inc.c
index 2a409a3..33ca177 100644
--- a/target/ppc/translate/vsx-impl.inc.c
+++ b/target/ppc/translate/vsx-impl.inc.c
@@ -1213,6 +1213,19 @@ static void gen_##name(DisasContext *ctx) \
VSX_EXTRACT_INSERT(xxextractuw)
VSX_EXTRACT_INSERT(xxinsertw)
+#ifdef TARGET_PPC64
+static void gen_xsxexpdp(DisasContext *ctx)
+{
+ TCGv rt = cpu_gpr[rD(ctx->opcode)];
+ if (unlikely(!ctx->vsx_enabled)) {
+ gen_exception(ctx, POWERPC_EXCP_VSXU);
+ return;
+ }
+ tcg_gen_shri_i64(rt, cpu_vsrh(xB(ctx->opcode)), 52);
+ tcg_gen_andi_i64(rt, rt, 0x7FF);
+}
+#endif
+
#undef GEN_XX2FORM
#undef GEN_XX3FORM
#undef GEN_XX2IFORM
diff --git a/target/ppc/translate/vsx-ops.inc.c b/target/ppc/translate/vsx-ops.inc.c
index 5c01aed..85d3b7d 100644
--- a/target/ppc/translate/vsx-ops.inc.c
+++ b/target/ppc/translate/vsx-ops.inc.c
@@ -113,6 +113,10 @@ GEN_VSX_XFORM_300_EO(xsnabsqp, 0x04, 0x19, 0x08, 0x00000001),
GEN_VSX_XFORM_300_EO(xsnegqp, 0x04, 0x19, 0x10, 0x00000001),
GEN_VSX_XFORM_300(xscpsgnqp, 0x04, 0x03, 0x00000001),
+#ifdef TARGET_PPC64
+GEN_XX2FORM_EO(xsxexpdp, 0x16, 0x15, 0x00, PPC2_ISA300),
+#endif
+
GEN_XX2FORM(xvabsdp, 0x12, 0x1D, PPC2_VSX),
GEN_XX2FORM(xvnabsdp, 0x12, 0x1E, PPC2_VSX),
GEN_XX2FORM(xvnegdp, 0x12, 0x1F, PPC2_VSX),
--
2.9.3
^ permalink raw reply related [flat|nested] 73+ messages in thread
* [Qemu-devel] [PULL 57/67] target-ppc: Add xsxexpqp instruction
2017-01-12 2:02 [Qemu-devel] [PULL 00/67] ppc-for-2.9 queue 20170112 David Gibson
` (55 preceding siblings ...)
2017-01-12 2:03 ` [Qemu-devel] [PULL 56/67] target-ppc: Add xsxexpdp instruction David Gibson
@ 2017-01-12 2:03 ` David Gibson
2017-01-12 2:03 ` [Qemu-devel] [PULL 58/67] target-ppc: Add xsxsigdp instruction David Gibson
` (11 subsequent siblings)
68 siblings, 0 replies; 73+ messages in thread
From: David Gibson @ 2017-01-12 2:03 UTC (permalink / raw)
To: peter.maydell
Cc: agraf, qemu-ppc, qemu-devel, thuth, lvivier, aik, mdroth,
Nikunj A Dadhania, David Gibson
From: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
xsxexpqp: VSX Scalar Extract Exponent Quad Precision
Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
target/ppc/translate/vsx-impl.inc.c | 15 +++++++++++++++
target/ppc/translate/vsx-ops.inc.c | 1 +
2 files changed, 16 insertions(+)
diff --git a/target/ppc/translate/vsx-impl.inc.c b/target/ppc/translate/vsx-impl.inc.c
index 33ca177..228e2a5 100644
--- a/target/ppc/translate/vsx-impl.inc.c
+++ b/target/ppc/translate/vsx-impl.inc.c
@@ -1224,6 +1224,21 @@ static void gen_xsxexpdp(DisasContext *ctx)
tcg_gen_shri_i64(rt, cpu_vsrh(xB(ctx->opcode)), 52);
tcg_gen_andi_i64(rt, rt, 0x7FF);
}
+
+static void gen_xsxexpqp(DisasContext *ctx)
+{
+ TCGv_i64 xth = cpu_vsrh(rD(ctx->opcode) + 32);
+ TCGv_i64 xtl = cpu_vsrl(rD(ctx->opcode) + 32);
+ TCGv_i64 xbh = cpu_vsrh(rB(ctx->opcode) + 32);
+
+ if (unlikely(!ctx->vsx_enabled)) {
+ gen_exception(ctx, POWERPC_EXCP_VSXU);
+ return;
+ }
+ tcg_gen_shri_i64(xth, xbh, 48);
+ tcg_gen_andi_i64(xth, xth, 0x7FFF);
+ tcg_gen_movi_i64(xtl, 0);
+}
#endif
#undef GEN_XX2FORM
diff --git a/target/ppc/translate/vsx-ops.inc.c b/target/ppc/translate/vsx-ops.inc.c
index 85d3b7d..87f1852 100644
--- a/target/ppc/translate/vsx-ops.inc.c
+++ b/target/ppc/translate/vsx-ops.inc.c
@@ -115,6 +115,7 @@ GEN_VSX_XFORM_300(xscpsgnqp, 0x04, 0x03, 0x00000001),
#ifdef TARGET_PPC64
GEN_XX2FORM_EO(xsxexpdp, 0x16, 0x15, 0x00, PPC2_ISA300),
+GEN_VSX_XFORM_300_EO(xsxexpqp, 0x04, 0x19, 0x02, 0x00000001),
#endif
GEN_XX2FORM(xvabsdp, 0x12, 0x1D, PPC2_VSX),
--
2.9.3
^ permalink raw reply related [flat|nested] 73+ messages in thread
* [Qemu-devel] [PULL 58/67] target-ppc: Add xsxsigdp instruction
2017-01-12 2:02 [Qemu-devel] [PULL 00/67] ppc-for-2.9 queue 20170112 David Gibson
` (56 preceding siblings ...)
2017-01-12 2:03 ` [Qemu-devel] [PULL 57/67] target-ppc: Add xsxexpqp instruction David Gibson
@ 2017-01-12 2:03 ` David Gibson
2017-01-12 2:03 ` [Qemu-devel] [PULL 59/67] target-ppc: Add xsxsigqp instructions David Gibson
` (10 subsequent siblings)
68 siblings, 0 replies; 73+ messages in thread
From: David Gibson @ 2017-01-12 2:03 UTC (permalink / raw)
To: peter.maydell
Cc: agraf, qemu-ppc, qemu-devel, thuth, lvivier, aik, mdroth,
Nikunj A Dadhania, David Gibson
From: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
xsxsigdp: VSX Scalar Extract Significand Dual Precision
Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
target/ppc/translate/vsx-impl.inc.c | 29 +++++++++++++++++++++++++++++
target/ppc/translate/vsx-ops.inc.c | 1 +
2 files changed, 30 insertions(+)
diff --git a/target/ppc/translate/vsx-impl.inc.c b/target/ppc/translate/vsx-impl.inc.c
index 228e2a5..c6f2208 100644
--- a/target/ppc/translate/vsx-impl.inc.c
+++ b/target/ppc/translate/vsx-impl.inc.c
@@ -1239,6 +1239,35 @@ static void gen_xsxexpqp(DisasContext *ctx)
tcg_gen_andi_i64(xth, xth, 0x7FFF);
tcg_gen_movi_i64(xtl, 0);
}
+
+static void gen_xsxsigdp(DisasContext *ctx)
+{
+ TCGv rt = cpu_gpr[rD(ctx->opcode)];
+ TCGv_i64 t0, zr, nan, exp;
+
+ if (unlikely(!ctx->vsx_enabled)) {
+ gen_exception(ctx, POWERPC_EXCP_VSXU);
+ return;
+ }
+ exp = tcg_temp_new_i64();
+ t0 = tcg_temp_new_i64();
+ zr = tcg_const_i64(0);
+ nan = tcg_const_i64(2047);
+
+ tcg_gen_shri_i64(exp, cpu_vsrh(xB(ctx->opcode)), 52);
+ tcg_gen_andi_i64(exp, exp, 0x7FF);
+ tcg_gen_movi_i64(t0, 0x0010000000000000);
+ tcg_gen_movcond_i64(TCG_COND_EQ, t0, exp, zr, zr, t0);
+ tcg_gen_movcond_i64(TCG_COND_EQ, t0, exp, nan, zr, t0);
+ tcg_gen_andi_i64(rt, cpu_vsrh(xB(ctx->opcode)), 0x000FFFFFFFFFFFFF);
+ tcg_gen_or_i64(rt, rt, t0);
+
+ tcg_temp_free_i64(t0);
+ tcg_temp_free_i64(exp);
+ tcg_temp_free_i64(zr);
+ tcg_temp_free_i64(nan);
+}
+
#endif
#undef GEN_XX2FORM
diff --git a/target/ppc/translate/vsx-ops.inc.c b/target/ppc/translate/vsx-ops.inc.c
index 87f1852..1fd5285 100644
--- a/target/ppc/translate/vsx-ops.inc.c
+++ b/target/ppc/translate/vsx-ops.inc.c
@@ -116,6 +116,7 @@ GEN_VSX_XFORM_300(xscpsgnqp, 0x04, 0x03, 0x00000001),
#ifdef TARGET_PPC64
GEN_XX2FORM_EO(xsxexpdp, 0x16, 0x15, 0x00, PPC2_ISA300),
GEN_VSX_XFORM_300_EO(xsxexpqp, 0x04, 0x19, 0x02, 0x00000001),
+GEN_XX2FORM_EO(xsxsigdp, 0x16, 0x15, 0x01, PPC2_ISA300),
#endif
GEN_XX2FORM(xvabsdp, 0x12, 0x1D, PPC2_VSX),
--
2.9.3
^ permalink raw reply related [flat|nested] 73+ messages in thread
* [Qemu-devel] [PULL 59/67] target-ppc: Add xsxsigqp instructions
2017-01-12 2:02 [Qemu-devel] [PULL 00/67] ppc-for-2.9 queue 20170112 David Gibson
` (57 preceding siblings ...)
2017-01-12 2:03 ` [Qemu-devel] [PULL 58/67] target-ppc: Add xsxsigdp instruction David Gibson
@ 2017-01-12 2:03 ` David Gibson
2017-01-12 2:03 ` [Qemu-devel] [PULL 60/67] pxb: Restrict to x86 David Gibson
` (9 subsequent siblings)
68 siblings, 0 replies; 73+ messages in thread
From: David Gibson @ 2017-01-12 2:03 UTC (permalink / raw)
To: peter.maydell
Cc: agraf, qemu-ppc, qemu-devel, thuth, lvivier, aik, mdroth,
Nikunj A Dadhania, David Gibson
From: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
xsxsigqp: VSX Scalar Extract Significand Quad Precision
Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
target/ppc/translate/vsx-impl.inc.c | 29 +++++++++++++++++++++++++++++
target/ppc/translate/vsx-ops.inc.c | 1 +
2 files changed, 30 insertions(+)
diff --git a/target/ppc/translate/vsx-impl.inc.c b/target/ppc/translate/vsx-impl.inc.c
index c6f2208..33e934f 100644
--- a/target/ppc/translate/vsx-impl.inc.c
+++ b/target/ppc/translate/vsx-impl.inc.c
@@ -1268,6 +1268,35 @@ static void gen_xsxsigdp(DisasContext *ctx)
tcg_temp_free_i64(nan);
}
+static void gen_xsxsigqp(DisasContext *ctx)
+{
+ TCGv_i64 t0, zr, nan, exp;
+ TCGv_i64 xth = cpu_vsrh(rD(ctx->opcode) + 32);
+ TCGv_i64 xtl = cpu_vsrl(rD(ctx->opcode) + 32);
+
+ if (unlikely(!ctx->vsx_enabled)) {
+ gen_exception(ctx, POWERPC_EXCP_VSXU);
+ return;
+ }
+ exp = tcg_temp_new_i64();
+ t0 = tcg_temp_new_i64();
+ zr = tcg_const_i64(0);
+ nan = tcg_const_i64(32767);
+
+ tcg_gen_shri_i64(exp, cpu_vsrh(rB(ctx->opcode) + 32), 48);
+ tcg_gen_andi_i64(exp, exp, 0x7FFF);
+ tcg_gen_movi_i64(t0, 0x0001000000000000);
+ tcg_gen_movcond_i64(TCG_COND_EQ, t0, exp, zr, zr, t0);
+ tcg_gen_movcond_i64(TCG_COND_EQ, t0, exp, nan, zr, t0);
+ tcg_gen_andi_i64(xth, cpu_vsrh(rB(ctx->opcode) + 32), 0x0000FFFFFFFFFFFF);
+ tcg_gen_or_i64(xth, xth, t0);
+ tcg_gen_mov_i64(xtl, cpu_vsrl(rB(ctx->opcode) + 32));
+
+ tcg_temp_free_i64(t0);
+ tcg_temp_free_i64(exp);
+ tcg_temp_free_i64(zr);
+ tcg_temp_free_i64(nan);
+}
#endif
#undef GEN_XX2FORM
diff --git a/target/ppc/translate/vsx-ops.inc.c b/target/ppc/translate/vsx-ops.inc.c
index 1fd5285..bfcd09e 100644
--- a/target/ppc/translate/vsx-ops.inc.c
+++ b/target/ppc/translate/vsx-ops.inc.c
@@ -117,6 +117,7 @@ GEN_VSX_XFORM_300(xscpsgnqp, 0x04, 0x03, 0x00000001),
GEN_XX2FORM_EO(xsxexpdp, 0x16, 0x15, 0x00, PPC2_ISA300),
GEN_VSX_XFORM_300_EO(xsxexpqp, 0x04, 0x19, 0x02, 0x00000001),
GEN_XX2FORM_EO(xsxsigdp, 0x16, 0x15, 0x01, PPC2_ISA300),
+GEN_VSX_XFORM_300_EO(xsxsigqp, 0x04, 0x19, 0x12, 0x00000001),
#endif
GEN_XX2FORM(xvabsdp, 0x12, 0x1D, PPC2_VSX),
--
2.9.3
^ permalink raw reply related [flat|nested] 73+ messages in thread
* [Qemu-devel] [PULL 60/67] pxb: Restrict to x86
2017-01-12 2:02 [Qemu-devel] [PULL 00/67] ppc-for-2.9 queue 20170112 David Gibson
` (58 preceding siblings ...)
2017-01-12 2:03 ` [Qemu-devel] [PULL 59/67] target-ppc: Add xsxsigqp instructions David Gibson
@ 2017-01-12 2:03 ` David Gibson
2017-01-12 2:03 ` [Qemu-devel] [PULL 61/67] pseries: Rewrite CAS PVR compatibility logic David Gibson
` (8 subsequent siblings)
68 siblings, 0 replies; 73+ messages in thread
From: David Gibson @ 2017-01-12 2:03 UTC (permalink / raw)
To: peter.maydell
Cc: agraf, qemu-ppc, qemu-devel, thuth, lvivier, aik, mdroth, David Gibson
The PCI Expander Bridge (PXB) device is essentially a hack to allow
different PCIe devices to be assigned to different NUMA nodes on x86. Each
PXB is sort-of a separate PCI host bridge, except that its config space
is shared with the config space of the main PCI host bridge, rather than
being independent.
This is only necessary if the platform doesn't (easily) allow truly
independent PCI host bridges. AFAIK that's just x86.
This patch makes it possible to configure PXB out of the build, and adjusts
the default configs so it's only included on x86 targets.
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Acked-by: Michael S. Tsirkin <mst@redhat.com>
---
default-configs/i386-softmmu.mak | 1 +
default-configs/x86_64-softmmu.mak | 1 +
hw/pci-bridge/Makefile.objs | 2 +-
3 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/default-configs/i386-softmmu.mak b/default-configs/i386-softmmu.mak
index 0b51360..6c52d26 100644
--- a/default-configs/i386-softmmu.mak
+++ b/default-configs/i386-softmmu.mak
@@ -56,3 +56,4 @@ CONFIG_IOH3420=y
CONFIG_I82801B11=y
CONFIG_SMBIOS=y
CONFIG_HYPERV_TESTDEV=$(CONFIG_KVM)
+CONFIG_PXB=y
diff --git a/default-configs/x86_64-softmmu.mak b/default-configs/x86_64-softmmu.mak
index 7f89503..2d0341c 100644
--- a/default-configs/x86_64-softmmu.mak
+++ b/default-configs/x86_64-softmmu.mak
@@ -56,3 +56,4 @@ CONFIG_IOH3420=y
CONFIG_I82801B11=y
CONFIG_SMBIOS=y
CONFIG_HYPERV_TESTDEV=$(CONFIG_KVM)
+CONFIG_PXB=y
diff --git a/hw/pci-bridge/Makefile.objs b/hw/pci-bridge/Makefile.objs
index f2adfe3..5612bd7 100644
--- a/hw/pci-bridge/Makefile.objs
+++ b/hw/pci-bridge/Makefile.objs
@@ -1,5 +1,5 @@
common-obj-y += pci_bridge_dev.o
-common-obj-y += pci_expander_bridge.o
+common-obj-$(CONFIG_PXB) += pci_expander_bridge.o
common-obj-$(CONFIG_XIO3130) += xio3130_upstream.o xio3130_downstream.o
common-obj-$(CONFIG_IOH3420) += ioh3420.o
common-obj-$(CONFIG_I82801B11) += i82801b11.o
--
2.9.3
^ permalink raw reply related [flat|nested] 73+ messages in thread
* [Qemu-devel] [PULL 61/67] pseries: Rewrite CAS PVR compatibility logic
2017-01-12 2:02 [Qemu-devel] [PULL 00/67] ppc-for-2.9 queue 20170112 David Gibson
` (59 preceding siblings ...)
2017-01-12 2:03 ` [Qemu-devel] [PULL 60/67] pxb: Restrict to x86 David Gibson
@ 2017-01-12 2:03 ` David Gibson
2017-01-12 2:03 ` [Qemu-devel] [PULL 62/67] ppc: Add ppc_set_compat_all() David Gibson
` (7 subsequent siblings)
68 siblings, 0 replies; 73+ messages in thread
From: David Gibson @ 2017-01-12 2:03 UTC (permalink / raw)
To: peter.maydell
Cc: agraf, qemu-ppc, qemu-devel, thuth, lvivier, aik, mdroth, David Gibson
During boot, PAPR guests negotiate CPU model support with the
ibm,client-architecture-support mechanism. The logic to implement this in
qemu is very convoluted. This cleans it up to be cleaner, using the new
ppc_check_compat() call.
The new logic for choosing a compatibility mode is:
1. Usually, use the most recent compatibility mode that is
a) supported by the guest
b) supported by the CPU
and c) no later than the maximum allowed (if specified)
2. If no suitable compatibility mode was found, the guest *does*
support this CPU explicitly, and no maximum compatibility mode is
specified, then use "raw" mode for the current CPU
3. Otherwise, fail the boot.
This differs from the results of the old code: the old code preferred using
"raw" mode to a compatibility mode, whereas the new code prefers a
compatibility mode if available. Using compatibility mode preferentially
means that we're more likely to be able to migrate the guest to a similar
but not identical host.
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/ppc/spapr_hcall.c | 104 ++++++++++++++++-----------------------------------
hw/ppc/trace-events | 2 +-
2 files changed, 34 insertions(+), 72 deletions(-)
diff --git a/hw/ppc/spapr_hcall.c b/hw/ppc/spapr_hcall.c
index fd9f1d4..43a1fef 100644
--- a/hw/ppc/spapr_hcall.c
+++ b/hw/ppc/spapr_hcall.c
@@ -935,98 +935,60 @@ static void do_set_compat(CPUState *cs, run_on_cpu_data arg)
ppc_set_compat(cpu, s->compat_pvr, &s->err);
}
-#define get_compat_level(cpuver) ( \
- ((cpuver) == CPU_POWERPC_LOGICAL_2_05) ? 2050 : \
- ((cpuver) == CPU_POWERPC_LOGICAL_2_06) ? 2060 : \
- ((cpuver) == CPU_POWERPC_LOGICAL_2_06_PLUS) ? 2061 : \
- ((cpuver) == CPU_POWERPC_LOGICAL_2_07) ? 2070 : 0)
-
-static void cas_handle_compat_cpu(PowerPCCPUClass *pcc, uint32_t pvr,
- unsigned max_lvl, unsigned *compat_lvl,
- unsigned *compat_pvr)
-{
- unsigned lvl = get_compat_level(pvr);
- bool is205, is206, is207;
-
- if (!lvl) {
- return;
- }
-
- /* If it is a logical PVR, try to determine the highest level */
- is205 = (pcc->pcr_supported & PCR_COMPAT_2_05) &&
- (lvl == get_compat_level(CPU_POWERPC_LOGICAL_2_05));
- is206 = (pcc->pcr_supported & PCR_COMPAT_2_06) &&
- ((lvl == get_compat_level(CPU_POWERPC_LOGICAL_2_06)) ||
- (lvl == get_compat_level(CPU_POWERPC_LOGICAL_2_06_PLUS)));
- is207 = (pcc->pcr_supported & PCR_COMPAT_2_07) &&
- (lvl == get_compat_level(CPU_POWERPC_LOGICAL_2_07));
-
- if (is205 || is206 || is207) {
- if (!max_lvl) {
- /* User did not set the level, choose the highest */
- if (*compat_lvl <= lvl) {
- *compat_lvl = lvl;
- *compat_pvr = pvr;
- }
- } else if (max_lvl >= lvl) {
- /* User chose the level, don't set higher than this */
- *compat_lvl = lvl;
- *compat_pvr = pvr;
- }
- }
-}
-
-static target_ulong h_client_architecture_support(PowerPCCPU *cpu_,
+static target_ulong h_client_architecture_support(PowerPCCPU *cpu,
sPAPRMachineState *spapr,
target_ulong opcode,
target_ulong *args)
{
target_ulong list = ppc64_phys_to_real(args[0]);
target_ulong ov_table;
- PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu_);
CPUState *cs;
- bool cpu_match = false;
- unsigned old_compat_pvr = cpu_->compat_pvr;
- unsigned compat_lvl = 0, compat_pvr = 0;
- unsigned max_lvl = get_compat_level(cpu_->max_compat);
- int counter;
+ bool explicit_match = false; /* Matched the CPU's real PVR */
+ uint32_t max_compat = cpu->max_compat;
+ uint32_t best_compat = 0;
+ int i;
sPAPROptionVector *ov5_guest, *ov5_cas_old, *ov5_updates;
- /* Parse PVR list */
- for (counter = 0; counter < 512; ++counter) {
+ /*
+ * We scan the supplied table of PVRs looking for two things
+ * 1. Is our real CPU PVR in the list?
+ * 2. What's the "best" listed logical PVR
+ */
+ for (i = 0; i < 512; ++i) {
uint32_t pvr, pvr_mask;
pvr_mask = ldl_be_phys(&address_space_memory, list);
- list += 4;
- pvr = ldl_be_phys(&address_space_memory, list);
- list += 4;
-
- trace_spapr_cas_pvr_try(pvr);
- if (!max_lvl &&
- ((cpu_->env.spr[SPR_PVR] & pvr_mask) == (pvr & pvr_mask))) {
- cpu_match = true;
- compat_pvr = 0;
- } else if (pvr == cpu_->compat_pvr) {
- cpu_match = true;
- compat_pvr = cpu_->compat_pvr;
- } else if (!cpu_match) {
- cas_handle_compat_cpu(pcc, pvr, max_lvl, &compat_lvl, &compat_pvr);
- }
- /* Terminator record */
+ pvr = ldl_be_phys(&address_space_memory, list + 4);
+ list += 8;
+
if (~pvr_mask & pvr) {
- break;
+ break; /* Terminator record */
}
+
+ if ((cpu->env.spr[SPR_PVR] & pvr_mask) == (pvr & pvr_mask)) {
+ explicit_match = true;
+ } else {
+ if (ppc_check_compat(cpu, pvr, best_compat, max_compat)) {
+ best_compat = pvr;
+ }
+ }
+ }
+
+ if ((best_compat == 0) && (!explicit_match || max_compat)) {
+ /* We couldn't find a suitable compatibility mode, and either
+ * the guest doesn't support "raw" mode for this CPU, or raw
+ * mode is disabled because a maximum compat mode is set */
+ return H_HARDWARE;
}
/* Parsing finished */
- trace_spapr_cas_pvr(cpu_->compat_pvr, cpu_match,
- compat_pvr, pcc->pcr_mask);
+ trace_spapr_cas_pvr(cpu->compat_pvr, explicit_match, best_compat);
/* Update CPUs */
- if (old_compat_pvr != compat_pvr) {
+ if (cpu->compat_pvr != best_compat) {
CPU_FOREACH(cs) {
SetCompatState s = {
- .compat_pvr = compat_pvr,
+ .compat_pvr = best_compat,
.err = NULL,
};
diff --git a/hw/ppc/trace-events b/hw/ppc/trace-events
index 42b8ec0..f46995c 100644
--- a/hw/ppc/trace-events
+++ b/hw/ppc/trace-events
@@ -15,7 +15,7 @@ spapr_cas_continue(unsigned long n) "Copy changes to the guest: %ld bytes"
# hw/ppc/spapr_hcall.c
spapr_cas_pvr_try(uint32_t pvr) "%x"
-spapr_cas_pvr(uint32_t cur_pvr, bool cpu_match, uint32_t new_pvr, uint64_t pcr) "current=%x, cpu_match=%u, new=%x, compat flags=%"PRIx64
+spapr_cas_pvr(uint32_t cur_pvr, bool explicit_match, uint32_t new_pvr) "current=%x, explicit_match=%u, new=%x"
# hw/ppc/spapr_iommu.c
spapr_iommu_put(uint64_t liobn, uint64_t ioba, uint64_t tce, uint64_t ret) "liobn=%"PRIx64" ioba=0x%"PRIx64" tce=0x%"PRIx64" ret=%"PRId64
--
2.9.3
^ permalink raw reply related [flat|nested] 73+ messages in thread
* [Qemu-devel] [PULL 62/67] ppc: Add ppc_set_compat_all()
2017-01-12 2:02 [Qemu-devel] [PULL 00/67] ppc-for-2.9 queue 20170112 David Gibson
` (60 preceding siblings ...)
2017-01-12 2:03 ` [Qemu-devel] [PULL 61/67] pseries: Rewrite CAS PVR compatibility logic David Gibson
@ 2017-01-12 2:03 ` David Gibson
2017-01-12 2:03 ` [Qemu-devel] [PULL 63/67] target-ppc: Add xsaddqp instructions David Gibson
` (6 subsequent siblings)
68 siblings, 0 replies; 73+ messages in thread
From: David Gibson @ 2017-01-12 2:03 UTC (permalink / raw)
To: peter.maydell
Cc: agraf, qemu-ppc, qemu-devel, thuth, lvivier, aik, mdroth, David Gibson
Once a compatiblity mode is negotiated with the guest,
h_client_architecture_support() uses run_on_cpu() to update each CPU to
the new mode. We're going to want this logic somewhere else shortly,
so make a helper function to do this global update.
We put it in target-ppc/compat.c - it makes as much sense at the CPU level
as it does at the machine level. We also move the cpu_synchronize_state()
into ppc_set_compat(), since it doesn't really make any sense to call that
without synchronizing state.
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/ppc/spapr_hcall.c | 31 +++++--------------------------
target/ppc/compat.c | 34 ++++++++++++++++++++++++++++++++++
target/ppc/cpu.h | 3 +++
3 files changed, 42 insertions(+), 26 deletions(-)
diff --git a/hw/ppc/spapr_hcall.c b/hw/ppc/spapr_hcall.c
index 43a1fef..21b6334 100644
--- a/hw/ppc/spapr_hcall.c
+++ b/hw/ppc/spapr_hcall.c
@@ -921,20 +921,6 @@ static target_ulong h_signal_sys_reset(PowerPCCPU *cpu,
}
}
-typedef struct {
- uint32_t compat_pvr;
- Error *err;
-} SetCompatState;
-
-static void do_set_compat(CPUState *cs, run_on_cpu_data arg)
-{
- PowerPCCPU *cpu = POWERPC_CPU(cs);
- SetCompatState *s = arg.host_ptr;
-
- cpu_synchronize_state(cs);
- ppc_set_compat(cpu, s->compat_pvr, &s->err);
-}
-
static target_ulong h_client_architecture_support(PowerPCCPU *cpu,
sPAPRMachineState *spapr,
target_ulong opcode,
@@ -942,7 +928,6 @@ static target_ulong h_client_architecture_support(PowerPCCPU *cpu,
{
target_ulong list = ppc64_phys_to_real(args[0]);
target_ulong ov_table;
- CPUState *cs;
bool explicit_match = false; /* Matched the CPU's real PVR */
uint32_t max_compat = cpu->max_compat;
uint32_t best_compat = 0;
@@ -986,18 +971,12 @@ static target_ulong h_client_architecture_support(PowerPCCPU *cpu,
/* Update CPUs */
if (cpu->compat_pvr != best_compat) {
- CPU_FOREACH(cs) {
- SetCompatState s = {
- .compat_pvr = best_compat,
- .err = NULL,
- };
+ Error *local_err = NULL;
- run_on_cpu(cs, do_set_compat, RUN_ON_CPU_HOST_PTR(&s));
-
- if (s.err) {
- error_report_err(s.err);
- return H_HARDWARE;
- }
+ ppc_set_compat_all(best_compat, &local_err);
+ if (local_err) {
+ error_report_err(local_err);
+ return H_HARDWARE;
}
}
diff --git a/target/ppc/compat.c b/target/ppc/compat.c
index 1059555..8de9dfb 100644
--- a/target/ppc/compat.c
+++ b/target/ppc/compat.c
@@ -124,6 +124,8 @@ void ppc_set_compat(PowerPCCPU *cpu, uint32_t compat_pvr, Error **errp)
pcr = compat->pcr;
}
+ cpu_synchronize_state(CPU(cpu));
+
cpu->compat_pvr = compat_pvr;
env->spr[SPR_PCR] = pcr & pcc->pcr_mask;
@@ -136,6 +138,38 @@ void ppc_set_compat(PowerPCCPU *cpu, uint32_t compat_pvr, Error **errp)
}
}
+typedef struct {
+ uint32_t compat_pvr;
+ Error *err;
+} SetCompatState;
+
+static void do_set_compat(CPUState *cs, run_on_cpu_data arg)
+{
+ PowerPCCPU *cpu = POWERPC_CPU(cs);
+ SetCompatState *s = arg.host_ptr;
+
+ ppc_set_compat(cpu, s->compat_pvr, &s->err);
+}
+
+void ppc_set_compat_all(uint32_t compat_pvr, Error **errp)
+{
+ CPUState *cs;
+
+ CPU_FOREACH(cs) {
+ SetCompatState s = {
+ .compat_pvr = compat_pvr,
+ .err = NULL,
+ };
+
+ run_on_cpu(cs, do_set_compat, RUN_ON_CPU_HOST_PTR(&s));
+
+ if (s.err) {
+ error_propagate(errp, s.err);
+ return;
+ }
+ }
+}
+
int ppc_compat_max_threads(PowerPCCPU *cpu)
{
const CompatInfo *compat = compat_by_pvr(cpu->compat_pvr);
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index 22842dd..4d72d75 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -1326,6 +1326,9 @@ static inline int cpu_mmu_index (CPUPPCState *env, bool ifetch)
bool ppc_check_compat(PowerPCCPU *cpu, uint32_t compat_pvr,
uint32_t min_compat_pvr, uint32_t max_compat_pvr);
void ppc_set_compat(PowerPCCPU *cpu, uint32_t compat_pvr, Error **errp);
+#if !defined(CONFIG_USER_ONLY)
+void ppc_set_compat_all(uint32_t compat_pvr, Error **errp);
+#endif
int ppc_compat_max_threads(PowerPCCPU *cpu);
#endif /* defined(TARGET_PPC64) */
--
2.9.3
^ permalink raw reply related [flat|nested] 73+ messages in thread
* [Qemu-devel] [PULL 63/67] target-ppc: Add xsaddqp instructions
2017-01-12 2:02 [Qemu-devel] [PULL 00/67] ppc-for-2.9 queue 20170112 David Gibson
` (61 preceding siblings ...)
2017-01-12 2:03 ` [Qemu-devel] [PULL 62/67] ppc: Add ppc_set_compat_all() David Gibson
@ 2017-01-12 2:03 ` David Gibson
2017-01-12 2:03 ` [Qemu-devel] [PULL 64/67] target-ppc: Add xscvdpqp instruction David Gibson
` (5 subsequent siblings)
68 siblings, 0 replies; 73+ messages in thread
From: David Gibson @ 2017-01-12 2:03 UTC (permalink / raw)
To: peter.maydell
Cc: agraf, qemu-ppc, qemu-devel, thuth, lvivier, aik, mdroth,
Bharata B Rao, Nikunj A Dadhania, David Gibson
From: Bharata B Rao <bharata@linux.vnet.ibm.com>
xsaddqp: VSX Scalar Add Quad-Precision
Signed-off-by: Bharata B Rao <bharata@linux.vnet.ibm.com>
Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
target/ppc/fpu_helper.c | 36 ++++++++++++++++++++++++++++++++++++
target/ppc/helper.h | 1 +
target/ppc/internal.h | 2 ++
target/ppc/translate/vsx-impl.inc.c | 1 +
target/ppc/translate/vsx-ops.inc.c | 1 +
5 files changed, 41 insertions(+)
diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c
index 01b335f..6e7279c 100644
--- a/target/ppc/fpu_helper.c
+++ b/target/ppc/fpu_helper.c
@@ -111,6 +111,7 @@ void helper_compute_fprf_##tp(CPUPPCState *env, tp arg) \
COMPUTE_FPRF(float16)
COMPUTE_FPRF(float32)
COMPUTE_FPRF(float64)
+COMPUTE_FPRF(float128)
/* Floating-point invalid operations exception */
static inline __attribute__((__always_inline__))
@@ -1830,6 +1831,41 @@ VSX_ADD_SUB(xssubsp, sub, 1, float64, VsrD(0), 1, 1)
VSX_ADD_SUB(xvsubdp, sub, 2, float64, VsrD(i), 0, 0)
VSX_ADD_SUB(xvsubsp, sub, 4, float32, VsrW(i), 0, 0)
+void helper_xsaddqp(CPUPPCState *env, uint32_t opcode)
+{
+ ppc_vsr_t xt, xa, xb;
+ float_status tstat;
+
+ getVSR(rA(opcode) + 32, &xa, env);
+ getVSR(rB(opcode) + 32, &xb, env);
+ getVSR(rD(opcode) + 32, &xt, env);
+ helper_reset_fpstatus(env);
+
+ if (unlikely(Rc(opcode) != 0)) {
+ /* TODO: Support xsadddpo after round-to-odd is implemented */
+ abort();
+ }
+
+ tstat = env->fp_status;
+ set_float_exception_flags(0, &tstat);
+ xt.f128 = float128_add(xa.f128, xb.f128, &tstat);
+ env->fp_status.float_exception_flags |= tstat.float_exception_flags;
+
+ if (unlikely(tstat.float_exception_flags & float_flag_invalid)) {
+ if (float128_is_infinity(xa.f128) && float128_is_infinity(xb.f128)) {
+ float_invalid_op_excp(env, POWERPC_EXCP_FP_VXISI, 1);
+ } else if (float128_is_signaling_nan(xa.f128, &tstat) ||
+ float128_is_signaling_nan(xb.f128, &tstat)) {
+ float_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1);
+ }
+ }
+
+ helper_compute_fprf_float128(env, xt.f128);
+
+ putVSR(rD(opcode) + 32, &xt, env);
+ float_check_status(env);
+}
+
/* VSX_MUL - VSX floating point multiply
* op - instruction mnemonic
* nels - number of elements (1, 2 or 4)
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index 5f290c6..889fe55 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -400,6 +400,7 @@ DEF_HELPER_4(bcdcpsgn, i32, avr, avr, avr, i32)
DEF_HELPER_3(bcdsetsgn, i32, avr, avr, i32)
DEF_HELPER_2(xsadddp, void, env, i32)
+DEF_HELPER_2(xsaddqp, void, env, i32)
DEF_HELPER_2(xssubdp, void, env, i32)
DEF_HELPER_2(xsmuldp, void, env, i32)
DEF_HELPER_2(xsdivdp, void, env, i32)
diff --git a/target/ppc/internal.h b/target/ppc/internal.h
index 187f024..c22d74e 100644
--- a/target/ppc/internal.h
+++ b/target/ppc/internal.h
@@ -206,6 +206,7 @@ typedef union _ppc_vsr_t {
uint64_t u64[2];
float32 f32[4];
float64 f64[2];
+ float128 f128;
Int128 s128;
} ppc_vsr_t;
@@ -245,4 +246,5 @@ static inline void putVSR(int n, ppc_vsr_t *vsr, CPUPPCState *env)
void helper_compute_fprf_float16(CPUPPCState *env, float16 arg);
void helper_compute_fprf_float32(CPUPPCState *env, float32 arg);
+void helper_compute_fprf_float128(CPUPPCState *env, float128 arg);
#endif /* PPC_INTERNAL_H */
diff --git a/target/ppc/translate/vsx-impl.inc.c b/target/ppc/translate/vsx-impl.inc.c
index 33e934f..113ccf3 100644
--- a/target/ppc/translate/vsx-impl.inc.c
+++ b/target/ppc/translate/vsx-impl.inc.c
@@ -777,6 +777,7 @@ static void gen_##name(DisasContext * ctx) \
}
GEN_VSX_HELPER_2(xsadddp, 0x00, 0x04, 0, PPC2_VSX)
+GEN_VSX_HELPER_2(xsaddqp, 0x04, 0x00, 0, PPC2_ISA300)
GEN_VSX_HELPER_2(xssubdp, 0x00, 0x05, 0, PPC2_VSX)
GEN_VSX_HELPER_2(xsmuldp, 0x00, 0x06, 0, PPC2_VSX)
GEN_VSX_HELPER_2(xsdivdp, 0x00, 0x07, 0, PPC2_VSX)
diff --git a/target/ppc/translate/vsx-ops.inc.c b/target/ppc/translate/vsx-ops.inc.c
index bfcd09e..882e11b 100644
--- a/target/ppc/translate/vsx-ops.inc.c
+++ b/target/ppc/translate/vsx-ops.inc.c
@@ -130,6 +130,7 @@ GEN_XX2FORM(xvnegsp, 0x12, 0x1B, PPC2_VSX),
GEN_XX3FORM(xvcpsgnsp, 0x00, 0x1A, PPC2_VSX),
GEN_XX3FORM(xsadddp, 0x00, 0x04, PPC2_VSX),
+GEN_VSX_XFORM_300(xsaddqp, 0x04, 0x00, 0x0),
GEN_XX3FORM(xssubdp, 0x00, 0x05, PPC2_VSX),
GEN_XX3FORM(xsmuldp, 0x00, 0x06, PPC2_VSX),
GEN_XX3FORM(xsdivdp, 0x00, 0x07, PPC2_VSX),
--
2.9.3
^ permalink raw reply related [flat|nested] 73+ messages in thread
* [Qemu-devel] [PULL 64/67] target-ppc: Add xscvdpqp instruction
2017-01-12 2:02 [Qemu-devel] [PULL 00/67] ppc-for-2.9 queue 20170112 David Gibson
` (62 preceding siblings ...)
2017-01-12 2:03 ` [Qemu-devel] [PULL 63/67] target-ppc: Add xsaddqp instructions David Gibson
@ 2017-01-12 2:03 ` David Gibson
2017-01-12 2:03 ` [Qemu-devel] [PULL 65/67] target-ppc: Add xscvqpdp instruction David Gibson
` (4 subsequent siblings)
68 siblings, 0 replies; 73+ messages in thread
From: David Gibson @ 2017-01-12 2:03 UTC (permalink / raw)
To: peter.maydell
Cc: agraf, qemu-ppc, qemu-devel, thuth, lvivier, aik, mdroth,
Bharata B Rao, Nikunj A Dadhania, David Gibson
From: Bharata B Rao <bharata@linux.vnet.ibm.com>
xscvdpqp: VSX Scalar Convert Double-Precision format to
Quad-Precision format
Signed-off-by: Bharata B Rao <bharata@linux.vnet.ibm.com>
Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
target/ppc/fpu_helper.c | 45 +++++++++++++++++++++++++++++++++++++
target/ppc/helper.h | 1 +
target/ppc/translate/vsx-impl.inc.c | 1 +
target/ppc/translate/vsx-ops.inc.c | 1 +
4 files changed, 48 insertions(+)
diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c
index 6e7279c..16397ef 100644
--- a/target/ppc/fpu_helper.c
+++ b/target/ppc/fpu_helper.c
@@ -22,6 +22,15 @@
#include "exec/exec-all.h"
#include "internal.h"
+static inline float128 float128_snan_to_qnan(float128 x)
+{
+ float128 r;
+
+ r.high = x.high | 0x0000800000000000;
+ r.low = x.low;
+ return r;
+}
+
#define float64_snan_to_qnan(x) ((x) | 0x0008000000000000ULL)
#define float32_snan_to_qnan(x) ((x) | 0x00400000)
#define float16_snan_to_qnan(x) ((x) | 0x0200)
@@ -2702,6 +2711,42 @@ VSX_CVT_FP_TO_FP(xscvspdp, 1, float32, float64, VsrW(0), VsrD(0), 1)
VSX_CVT_FP_TO_FP(xvcvdpsp, 2, float64, float32, VsrD(i), VsrW(2*i), 0)
VSX_CVT_FP_TO_FP(xvcvspdp, 2, float32, float64, VsrW(2*i), VsrD(i), 0)
+/* VSX_CVT_FP_TO_FP_VECTOR - VSX floating point/floating point conversion
+ * op - instruction mnemonic
+ * nels - number of elements (1, 2 or 4)
+ * stp - source type (float32 or float64)
+ * ttp - target type (float32 or float64)
+ * sfld - source vsr_t field
+ * tfld - target vsr_t field (f32 or f64)
+ * sfprf - set FPRF
+ */
+#define VSX_CVT_FP_TO_FP_VECTOR(op, nels, stp, ttp, sfld, tfld, sfprf) \
+void helper_##op(CPUPPCState *env, uint32_t opcode) \
+{ \
+ ppc_vsr_t xt, xb; \
+ int i; \
+ \
+ getVSR(rB(opcode) + 32, &xb, env); \
+ getVSR(rD(opcode) + 32, &xt, env); \
+ \
+ for (i = 0; i < nels; i++) { \
+ xt.tfld = stp##_to_##ttp(xb.sfld, &env->fp_status); \
+ if (unlikely(stp##_is_signaling_nan(xb.sfld, \
+ &env->fp_status))) { \
+ float_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 0); \
+ xt.tfld = ttp##_snan_to_qnan(xt.tfld); \
+ } \
+ if (sfprf) { \
+ helper_compute_fprf_##ttp(env, xt.tfld); \
+ } \
+ } \
+ \
+ putVSR(rD(opcode) + 32, &xt, env); \
+ float_check_status(env); \
+}
+
+VSX_CVT_FP_TO_FP_VECTOR(xscvdpqp, 1, float64, float128, VsrD(0), f128, 1)
+
/* VSX_CVT_FP_TO_FP_HP - VSX floating point/floating point conversion
* involving one half precision value
* op - instruction mnemonic
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index 889fe55..3b5d0ad 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -430,6 +430,7 @@ DEF_HELPER_2(xscmpuqp, void, env, i32)
DEF_HELPER_2(xsmaxdp, void, env, i32)
DEF_HELPER_2(xsmindp, void, env, i32)
DEF_HELPER_2(xscvdphp, void, env, i32)
+DEF_HELPER_2(xscvdpqp, void, env, i32)
DEF_HELPER_2(xscvdpsp, void, env, i32)
DEF_HELPER_2(xscvdpspn, i64, env, i64)
DEF_HELPER_2(xscvhpdp, void, env, i32)
diff --git a/target/ppc/translate/vsx-impl.inc.c b/target/ppc/translate/vsx-impl.inc.c
index 113ccf3..01b5621 100644
--- a/target/ppc/translate/vsx-impl.inc.c
+++ b/target/ppc/translate/vsx-impl.inc.c
@@ -808,6 +808,7 @@ GEN_VSX_HELPER_2(xsmaxdp, 0x00, 0x14, 0, PPC2_VSX)
GEN_VSX_HELPER_2(xsmindp, 0x00, 0x15, 0, PPC2_VSX)
GEN_VSX_HELPER_2(xscvdphp, 0x16, 0x15, 0x11, PPC2_ISA300)
GEN_VSX_HELPER_2(xscvdpsp, 0x12, 0x10, 0, PPC2_VSX)
+GEN_VSX_HELPER_2(xscvdpqp, 0x04, 0x1A, 0x16, PPC2_ISA300)
GEN_VSX_HELPER_XT_XB_ENV(xscvdpspn, 0x16, 0x10, 0, PPC2_VSX207)
GEN_VSX_HELPER_2(xscvhpdp, 0x16, 0x15, 0x10, PPC2_ISA300)
GEN_VSX_HELPER_2(xscvspdp, 0x12, 0x14, 0, PPC2_VSX)
diff --git a/target/ppc/translate/vsx-ops.inc.c b/target/ppc/translate/vsx-ops.inc.c
index 882e11b..e75ecd1 100644
--- a/target/ppc/translate/vsx-ops.inc.c
+++ b/target/ppc/translate/vsx-ops.inc.c
@@ -112,6 +112,7 @@ GEN_VSX_XFORM_300_EO(xsabsqp, 0x04, 0x19, 0x00, 0x00000001),
GEN_VSX_XFORM_300_EO(xsnabsqp, 0x04, 0x19, 0x08, 0x00000001),
GEN_VSX_XFORM_300_EO(xsnegqp, 0x04, 0x19, 0x10, 0x00000001),
GEN_VSX_XFORM_300(xscpsgnqp, 0x04, 0x03, 0x00000001),
+GEN_VSX_XFORM_300_EO(xscvdpqp, 0x04, 0x1A, 0x16, 0x00000001),
#ifdef TARGET_PPC64
GEN_XX2FORM_EO(xsxexpdp, 0x16, 0x15, 0x00, PPC2_ISA300),
--
2.9.3
^ permalink raw reply related [flat|nested] 73+ messages in thread
* [Qemu-devel] [PULL 65/67] target-ppc: Add xscvqpdp instruction
2017-01-12 2:02 [Qemu-devel] [PULL 00/67] ppc-for-2.9 queue 20170112 David Gibson
` (63 preceding siblings ...)
2017-01-12 2:03 ` [Qemu-devel] [PULL 64/67] target-ppc: Add xscvdpqp instruction David Gibson
@ 2017-01-12 2:03 ` David Gibson
2017-01-12 2:03 ` [Qemu-devel] [PULL 66/67] ppc: Prevent inifnite loop in decrementer auto-reload David Gibson
` (3 subsequent siblings)
68 siblings, 0 replies; 73+ messages in thread
From: David Gibson @ 2017-01-12 2:03 UTC (permalink / raw)
To: peter.maydell
Cc: agraf, qemu-ppc, qemu-devel, thuth, lvivier, aik, mdroth,
Bharata B Rao, Nikunj A Dadhania, David Gibson
From: Bharata B Rao <bharata@linux.vnet.ibm.com>
xscvqpdp: VSX Scalar round & Convert Quad-Precision format to
Double-Precision format
Signed-off-by: Bharata B Rao <bharata@linux.vnet.ibm.com>
Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
target/ppc/fpu_helper.c | 28 ++++++++++++++++++++++++++++
target/ppc/helper.h | 1 +
target/ppc/translate/vsx-impl.inc.c | 1 +
target/ppc/translate/vsx-ops.inc.c | 1 +
4 files changed, 31 insertions(+)
diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c
index 16397ef..8c8e3c5 100644
--- a/target/ppc/fpu_helper.c
+++ b/target/ppc/fpu_helper.c
@@ -2778,6 +2778,34 @@ void helper_##op(CPUPPCState *env, uint32_t opcode) \
VSX_CVT_FP_TO_FP_HP(xscvdphp, float64, float16, VsrD(0), VsrH(3))
VSX_CVT_FP_TO_FP_HP(xscvhpdp, float16, float64, VsrH(3), VsrD(0))
+/*
+ * xscvqpdp isn't using VSX_CVT_FP_TO_FP() because xscvqpdpo will be
+ * added to this later.
+ */
+void helper_xscvqpdp(CPUPPCState *env, uint32_t opcode)
+{
+ ppc_vsr_t xt, xb;
+
+ getVSR(rB(opcode) + 32, &xb, env);
+ getVSR(rD(opcode) + 32, &xt, env);
+
+ if (unlikely(Rc(opcode) != 0)) {
+ /* TODO: Support xscvqpdpo after round-to-odd is implemented */
+ abort();
+ }
+
+ xt.VsrD(0) = float128_to_float64(xb.f128, &env->fp_status);
+ if (unlikely(float128_is_signaling_nan(xb.f128,
+ &env->fp_status))) {
+ float_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 0);
+ xt.VsrD(0) = float64_snan_to_qnan(xt.VsrD(0));
+ }
+ helper_compute_fprf_float64(env, xt.VsrD(0));
+
+ putVSR(rD(opcode) + 32, &xt, env);
+ float_check_status(env);
+}
+
uint64_t helper_xscvdpspn(CPUPPCState *env, uint64_t xb)
{
float_status tstat = env->fp_status;
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index 3b5d0ad..f28bf62 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -433,6 +433,7 @@ DEF_HELPER_2(xscvdphp, void, env, i32)
DEF_HELPER_2(xscvdpqp, void, env, i32)
DEF_HELPER_2(xscvdpsp, void, env, i32)
DEF_HELPER_2(xscvdpspn, i64, env, i64)
+DEF_HELPER_2(xscvqpdp, void, env, i32)
DEF_HELPER_2(xscvhpdp, void, env, i32)
DEF_HELPER_2(xscvspdp, void, env, i32)
DEF_HELPER_2(xscvspdpn, i64, env, i64)
diff --git a/target/ppc/translate/vsx-impl.inc.c b/target/ppc/translate/vsx-impl.inc.c
index 01b5621..2d9fe50 100644
--- a/target/ppc/translate/vsx-impl.inc.c
+++ b/target/ppc/translate/vsx-impl.inc.c
@@ -810,6 +810,7 @@ GEN_VSX_HELPER_2(xscvdphp, 0x16, 0x15, 0x11, PPC2_ISA300)
GEN_VSX_HELPER_2(xscvdpsp, 0x12, 0x10, 0, PPC2_VSX)
GEN_VSX_HELPER_2(xscvdpqp, 0x04, 0x1A, 0x16, PPC2_ISA300)
GEN_VSX_HELPER_XT_XB_ENV(xscvdpspn, 0x16, 0x10, 0, PPC2_VSX207)
+GEN_VSX_HELPER_2(xscvqpdp, 0x04, 0x1A, 0x14, PPC2_ISA300)
GEN_VSX_HELPER_2(xscvhpdp, 0x16, 0x15, 0x10, PPC2_ISA300)
GEN_VSX_HELPER_2(xscvspdp, 0x12, 0x14, 0, PPC2_VSX)
GEN_VSX_HELPER_XT_XB_ENV(xscvspdpn, 0x16, 0x14, 0, PPC2_VSX207)
diff --git a/target/ppc/translate/vsx-ops.inc.c b/target/ppc/translate/vsx-ops.inc.c
index e75ecd1..aeeaff2 100644
--- a/target/ppc/translate/vsx-ops.inc.c
+++ b/target/ppc/translate/vsx-ops.inc.c
@@ -113,6 +113,7 @@ GEN_VSX_XFORM_300_EO(xsnabsqp, 0x04, 0x19, 0x08, 0x00000001),
GEN_VSX_XFORM_300_EO(xsnegqp, 0x04, 0x19, 0x10, 0x00000001),
GEN_VSX_XFORM_300(xscpsgnqp, 0x04, 0x03, 0x00000001),
GEN_VSX_XFORM_300_EO(xscvdpqp, 0x04, 0x1A, 0x16, 0x00000001),
+GEN_VSX_XFORM_300_EO(xscvqpdp, 0x04, 0x1A, 0x14, 0x0),
#ifdef TARGET_PPC64
GEN_XX2FORM_EO(xsxexpdp, 0x16, 0x15, 0x00, PPC2_ISA300),
--
2.9.3
^ permalink raw reply related [flat|nested] 73+ messages in thread
* [Qemu-devel] [PULL 66/67] ppc: Prevent inifnite loop in decrementer auto-reload.
2017-01-12 2:02 [Qemu-devel] [PULL 00/67] ppc-for-2.9 queue 20170112 David Gibson
` (64 preceding siblings ...)
2017-01-12 2:03 ` [Qemu-devel] [PULL 65/67] target-ppc: Add xscvqpdp instruction David Gibson
@ 2017-01-12 2:03 ` David Gibson
2017-01-12 2:03 ` [Qemu-devel] [PULL 67/67] ppc: Fix a warning in bcdcfz code and improve BCD_DIG_BYTE macro David Gibson
` (2 subsequent siblings)
68 siblings, 0 replies; 73+ messages in thread
From: David Gibson @ 2017-01-12 2:03 UTC (permalink / raw)
To: peter.maydell
Cc: agraf, qemu-ppc, qemu-devel, thuth, lvivier, aik, mdroth,
Roman Kapl, David Gibson
From: Roman Kapl <rka@sysgo.com>
If the DECAR register is set to 0, QEMU tries to reload the decrementer with
zero in an inifinite loop. According to PPC documentation, the decrementer is
triggered on 1->0 transition, so avoid reloading the decrementer if if is
already zero.
The problem does not manifest under Linux, but it is valid to set DECAR to zero
(and may make sense as part of decrementer initialization when interrupts are
disabled).
Signed-off-by: Roman Kapl <rka@sysgo.com>
[dwg: Fixed style nit]
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
hw/ppc/ppc_booke.c | 8 ++++++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/hw/ppc/ppc_booke.c b/hw/ppc/ppc_booke.c
index ab8d026..60baffa 100644
--- a/hw/ppc/ppc_booke.c
+++ b/hw/ppc/ppc_booke.c
@@ -198,8 +198,12 @@ static void booke_decr_cb(void *opaque)
booke_update_irq(cpu);
if (env->spr[SPR_BOOKE_TCR] & TCR_ARE) {
- /* Auto Reload */
- cpu_ppc_store_decr(env, env->spr[SPR_BOOKE_DECAR]);
+ /* Do not reload 0, it is already there. It would just trigger
+ * the timer again and lead to infinite loop */
+ if (env->spr[SPR_BOOKE_DECAR] != 0) {
+ /* Auto Reload */
+ cpu_ppc_store_decr(env, env->spr[SPR_BOOKE_DECAR]);
+ }
}
}
--
2.9.3
^ permalink raw reply related [flat|nested] 73+ messages in thread
* [Qemu-devel] [PULL 67/67] ppc: Fix a warning in bcdcfz code and improve BCD_DIG_BYTE macro
2017-01-12 2:02 [Qemu-devel] [PULL 00/67] ppc-for-2.9 queue 20170112 David Gibson
` (65 preceding siblings ...)
2017-01-12 2:03 ` [Qemu-devel] [PULL 66/67] ppc: Prevent inifnite loop in decrementer auto-reload David Gibson
@ 2017-01-12 2:03 ` David Gibson
2017-01-12 3:42 ` [Qemu-devel] [PULL 00/67] ppc-for-2.9 queue 20170112 no-reply
2017-01-13 10:54 ` Peter Maydell
68 siblings, 0 replies; 73+ messages in thread
From: David Gibson @ 2017-01-12 2:03 UTC (permalink / raw)
To: peter.maydell
Cc: agraf, qemu-ppc, qemu-devel, thuth, lvivier, aik, mdroth,
Jose Ricardo Ziviani, David Gibson
From: Jose Ricardo Ziviani <joserz@linux.vnet.ibm.com>
This commit fixes a warning in the code "(i * 2) ? .. : ..", which
should be better as "i ? .. : ..", and improves the BCD_DIG_BYTE
macro by placing parentheses around its argument to avoid possible
expansion issues like: BCD_DIG_BYTE(i + j).
Signed-off-by: Jose Ricardo Ziviani <joserz@linux.vnet.ibm.com>
Reviewed-by: Eric Blake <eblake@redhat.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---
target/ppc/int_helper.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/target/ppc/int_helper.c b/target/ppc/int_helper.c
index 24e5964..bd8282c 100644
--- a/target/ppc/int_helper.c
+++ b/target/ppc/int_helper.c
@@ -2583,9 +2583,9 @@ void helper_vsubecuq(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, ppc_avr_t *c)
#define NATIONAL_NEG 0x2D
#if defined(HOST_WORDS_BIGENDIAN)
-#define BCD_DIG_BYTE(n) (15 - (n/2))
+#define BCD_DIG_BYTE(n) (15 - ((n) / 2))
#else
-#define BCD_DIG_BYTE(n) (n/2)
+#define BCD_DIG_BYTE(n) ((n) / 2)
#endif
static int bcd_get_sgn(ppc_avr_t *bcd)
@@ -2908,7 +2908,7 @@ uint32_t helper_bcdcfz(ppc_avr_t *r, ppc_avr_t *b, uint32_t ps)
}
for (i = 0; i < 16; i++) {
- zone_digit = (i * 2) ? b->u8[BCD_DIG_BYTE(i * 2)] >> 4 : zone_lead;
+ zone_digit = i ? b->u8[BCD_DIG_BYTE(i * 2)] >> 4 : zone_lead;
digit = b->u8[BCD_DIG_BYTE(i * 2)] & 0xF;
if (unlikely(zone_digit != zone_lead || digit > 0x9)) {
invalid = 1;
--
2.9.3
^ permalink raw reply related [flat|nested] 73+ messages in thread
* Re: [Qemu-devel] [PULL 00/67] ppc-for-2.9 queue 20170112
2017-01-12 2:02 [Qemu-devel] [PULL 00/67] ppc-for-2.9 queue 20170112 David Gibson
` (66 preceding siblings ...)
2017-01-12 2:03 ` [Qemu-devel] [PULL 67/67] ppc: Fix a warning in bcdcfz code and improve BCD_DIG_BYTE macro David Gibson
@ 2017-01-12 3:42 ` no-reply
2017-01-12 23:36 ` David Gibson
2017-01-13 10:54 ` Peter Maydell
68 siblings, 1 reply; 73+ messages in thread
From: no-reply @ 2017-01-12 3:42 UTC (permalink / raw)
To: david
Cc: famz, peter.maydell, lvivier, thuth, mdroth, aik, agraf,
qemu-devel, qemu-ppc
Hi,
Your series seems to have some coding style problems. See output below for
more information:
Message-id: 20170112020327.24882-1-david@gibson.dropbear.id.au
Subject: [Qemu-devel] [PULL 00/67] ppc-for-2.9 queue 20170112
Type: series
=== TEST SCRIPT BEGIN ===
#!/bin/bash
BASE=base
n=1
total=$(git log --oneline $BASE.. | wc -l)
failed=0
# Useful git options
git config --local diff.renamelimit 0
git config --local diff.renames True
commits="$(git log --format=%H --reverse $BASE..)"
for c in $commits; do
echo "Checking PATCH $n/$total: $(git log -n 1 --format=%s $c)..."
if ! git show $c --format=email | ./scripts/checkpatch.pl --mailback -; then
failed=1
echo
fi
n=$((n+1))
done
exit $failed
=== TEST SCRIPT END ===
Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
* [new tag] patchew/20170112020327.24882-1-david@gibson.dropbear.id.au -> patchew/20170112020327.24882-1-david@gibson.dropbear.id.au
Switched to a new branch 'test'
72585bd ppc: Fix a warning in bcdcfz code and improve BCD_DIG_BYTE macro
2db2c7b ppc: Prevent inifnite loop in decrementer auto-reload.
620e113 target-ppc: Add xscvqpdp instruction
092a884 target-ppc: Add xscvdpqp instruction
ff57624 target-ppc: Add xsaddqp instructions
27c5216 ppc: Add ppc_set_compat_all()
1481a0b pseries: Rewrite CAS PVR compatibility logic
e2a29af pxb: Restrict to x86
4b3013a target-ppc: Add xsxsigqp instructions
9fdc3d2 target-ppc: Add xsxsigdp instruction
f43d3fc target-ppc: Add xsxexpqp instruction
a239c30 target-ppc: Add xsxexpdp instruction
c29777c target-ppc: Use correct precision for FPRF setting
6ae9a4d target-ppc: Add xscvdphp, xscvhpdp
72d1eef target-ppc: Rename helper_compute_fprf to helper_compute_fprf_float64
748d789 target-ppc: Replace isden by float64_is_zero_or_denormal
82a197b target-ppc: Use float64 arg in helper_compute_fprf()
7156ebc prep: add IBM RS/6000 7020 (40p) machine emulation
afcb4bf prep: add IBM RS/6000 7020 (40p) memory controller
2fbd7b6 prep: add PReP System I/O
93cbe64 target-ppc: Add xxinsertw instruction
d70075c target-ppc: Add xxextractuw instruction
6290487 hw/ppc: QOM'ify spapr_vio.c
33ef5a9 hw/ppc: QOM'ify ppce500_spin.c
3fd3d44 hw/ppc: QOM'ify e500.c
239e417 hw/gpio: QOM'ify mpc8xxx.c
fbb187d qtest: add ivshmem-test for ppc64
15bb7c6 qtest: convert ivshmem-test to use libqos
40c9b58 libqos: fix spapr qpci_map()
b9b8246 qtest: add display-vga-test to ppc64
27bc180 qtest: add netfilter tests for ppc64
1ecf0e2 ppc: Validate compatibility modes when setting
2beabb6 ppc: Rewrite ppc_get_compat_smt_threads()
1f92c8b ppc: Rewrite ppc_set_compat()
7d7782d pseries: Add pseries-2.9 machine type
e905225 prep: do not use global variable to access nvram
f6ae8b9 hw/ppc/spapr: Fix boot path of usb-host storage devices
c2b60cf target-ppc: implement stxvll instructions
bd2f88a target-ppc: implement stxvl instruction
48a6ca2 target-ppc: implement lxvll instruction
3e7c1ff target-ppc: implement lxvl instruction
8c54325 target-ppc: Add xxperm and xxpermr instructions
70967fc target-ppc: implement xscpsgnqp instruction
89c0d8a target-ppc: implement xsnegqp instruction
fa5d29c target-ppc: Implement bcd_is_valid function
8c85203 target-ppc: implement xsabsqp/xsnabsqp instruction
823dce4 target-ppc: implement stop instruction
9d6502e target-ppc: move ppc_vsr_t to common header
ca7c6dc ppc/spapr: implement H_SIGNAL_SYS_RESET
d603b4e ppc: Rename cpu_version to compat_pvr
1873da5 ppc: Clean up and QOMify hypercall emulation
8183386 pseries: Make cpu_update during CAS unconditional
4cea010 pseries: Always use core objects for CPU construction
67a7a7d target-ppc: add vextu[bhw][lr]x instructions
d44501d target-ppc: Implement bcdsetsgn. instruction
fd0ab44 target-ppc: Implement bcdcpsgn. instruction
661615a target-ppc: Implement bcdctsq. instruction
f5eb3b3 target-ppc: Implement bcdcfsq. instruction
66ee361 target-ppc: implement lxv/lxvx and stxv/stxvx
c1a9d68 target-ppc: implement stxsd and stxssp
de3a632 target-ppc: implement lxsd and lxssp instructions
6aebf4c target-ppc: Add xscmpoqp and xscmpuqp instructions
53a4ac8 target-ppc: Add xscmpexp[dp, qp] instructions
b6e5abb target-ppc: Fix xscmpodp and xscmpudp instructions
fa4be48 target-ppc: rename CRF_* defines as CRF_*_BIT
8b01963 target-ppc: Consolidate instruction decode helpers
340c202 disas/ppc: Fix indefinite articles in comments
=== OUTPUT BEGIN ===
Checking PATCH 1/67: disas/ppc: Fix indefinite articles in comments...
Checking PATCH 2/67: target-ppc: Consolidate instruction decode helpers...
Checking PATCH 3/67: target-ppc: rename CRF_* defines as CRF_*_BIT...
Checking PATCH 4/67: target-ppc: Fix xscmpodp and xscmpudp instructions...
Checking PATCH 5/67: target-ppc: Add xscmpexp[dp, qp] instructions...
Checking PATCH 6/67: target-ppc: Add xscmpoqp and xscmpuqp instructions...
Checking PATCH 7/67: target-ppc: implement lxsd and lxssp instructions...
Checking PATCH 8/67: target-ppc: implement stxsd and stxssp...
Checking PATCH 9/67: target-ppc: implement lxv/lxvx and stxv/stxvx...
Checking PATCH 10/67: target-ppc: Implement bcdcfsq. instruction...
Checking PATCH 11/67: target-ppc: Implement bcdctsq. instruction...
Checking PATCH 12/67: target-ppc: Implement bcdcpsgn. instruction...
Checking PATCH 13/67: target-ppc: Implement bcdsetsgn. instruction...
Checking PATCH 14/67: target-ppc: add vextu[bhw][lr]x instructions...
Checking PATCH 15/67: pseries: Always use core objects for CPU construction...
Checking PATCH 16/67: pseries: Make cpu_update during CAS unconditional...
Checking PATCH 17/67: ppc: Clean up and QOMify hypercall emulation...
Checking PATCH 18/67: ppc: Rename cpu_version to compat_pvr...
Checking PATCH 19/67: ppc/spapr: implement H_SIGNAL_SYS_RESET...
Checking PATCH 20/67: target-ppc: move ppc_vsr_t to common header...
Checking PATCH 21/67: target-ppc: implement stop instruction...
Checking PATCH 22/67: target-ppc: implement xsabsqp/xsnabsqp instruction...
Checking PATCH 23/67: target-ppc: Implement bcd_is_valid function...
Checking PATCH 24/67: target-ppc: implement xsnegqp instruction...
Checking PATCH 25/67: target-ppc: implement xscpsgnqp instruction...
Checking PATCH 26/67: target-ppc: Add xxperm and xxpermr instructions...
Checking PATCH 27/67: target-ppc: implement lxvl instruction...
Checking PATCH 28/67: target-ppc: implement lxvll instruction...
Checking PATCH 29/67: target-ppc: implement stxvl instruction...
Checking PATCH 30/67: target-ppc: implement stxvll instructions...
Checking PATCH 31/67: hw/ppc/spapr: Fix boot path of usb-host storage devices...
Checking PATCH 32/67: prep: do not use global variable to access nvram...
Checking PATCH 33/67: pseries: Add pseries-2.9 machine type...
Checking PATCH 34/67: ppc: Rewrite ppc_set_compat()...
Checking PATCH 35/67: ppc: Rewrite ppc_get_compat_smt_threads()...
Checking PATCH 36/67: ppc: Validate compatibility modes when setting...
Checking PATCH 37/67: qtest: add netfilter tests for ppc64...
Checking PATCH 38/67: qtest: add display-vga-test to ppc64...
Checking PATCH 39/67: libqos: fix spapr qpci_map()...
Checking PATCH 40/67: qtest: convert ivshmem-test to use libqos...
Checking PATCH 41/67: qtest: add ivshmem-test for ppc64...
Checking PATCH 42/67: hw/gpio: QOM'ify mpc8xxx.c...
Checking PATCH 43/67: hw/ppc: QOM'ify e500.c...
Checking PATCH 44/67: hw/ppc: QOM'ify ppce500_spin.c...
Checking PATCH 45/67: hw/ppc: QOM'ify spapr_vio.c...
Checking PATCH 46/67: target-ppc: Add xxextractuw instruction...
ERROR: Macros with complex values should be enclosed in parenthesis
#110: FILE: target/ppc/translate/vsx-ops.inc.c:52:
+#define GEN_XX2FORM_EXT(name, opc2, opc3, fl2) \
+GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0, opc3, 0x00100000, PPC_NONE, fl2), \
+GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 1, opc3, 0x00100000, PPC_NONE, fl2)
total: 1 errors, 0 warnings, 92 lines checked
Your patch has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
Checking PATCH 47/67: target-ppc: Add xxinsertw instruction...
Checking PATCH 48/67: prep: add PReP System I/O...
Checking PATCH 49/67: prep: add IBM RS/6000 7020 (40p) memory controller...
Checking PATCH 50/67: prep: add IBM RS/6000 7020 (40p) machine emulation...
Checking PATCH 51/67: target-ppc: Use float64 arg in helper_compute_fprf()...
Checking PATCH 52/67: target-ppc: Replace isden by float64_is_zero_or_denormal...
Checking PATCH 53/67: target-ppc: Rename helper_compute_fprf to helper_compute_fprf_float64...
Checking PATCH 54/67: target-ppc: Add xscvdphp, xscvhpdp...
Checking PATCH 55/67: target-ppc: Use correct precision for FPRF setting...
Checking PATCH 56/67: target-ppc: Add xsxexpdp instruction...
Checking PATCH 57/67: target-ppc: Add xsxexpqp instruction...
Checking PATCH 58/67: target-ppc: Add xsxsigdp instruction...
Checking PATCH 59/67: target-ppc: Add xsxsigqp instructions...
Checking PATCH 60/67: pxb: Restrict to x86...
Checking PATCH 61/67: pseries: Rewrite CAS PVR compatibility logic...
Checking PATCH 62/67: ppc: Add ppc_set_compat_all()...
Checking PATCH 63/67: target-ppc: Add xsaddqp instructions...
Checking PATCH 64/67: target-ppc: Add xscvdpqp instruction...
Checking PATCH 65/67: target-ppc: Add xscvqpdp instruction...
Checking PATCH 66/67: ppc: Prevent inifnite loop in decrementer auto-reload....
Checking PATCH 67/67: ppc: Fix a warning in bcdcfz code and improve BCD_DIG_BYTE macro...
=== OUTPUT END ===
Test command exited with code: 1
---
Email generated automatically by Patchew [http://patchew.org/].
Please send your feedback to patchew-devel@freelists.org
^ permalink raw reply [flat|nested] 73+ messages in thread
* Re: [Qemu-devel] [PULL 00/67] ppc-for-2.9 queue 20170112
2017-01-12 3:42 ` [Qemu-devel] [PULL 00/67] ppc-for-2.9 queue 20170112 no-reply
@ 2017-01-12 23:36 ` David Gibson
0 siblings, 0 replies; 73+ messages in thread
From: David Gibson @ 2017-01-12 23:36 UTC (permalink / raw)
To: qemu-devel
Cc: famz, peter.maydell, lvivier, thuth, mdroth, aik, agraf, qemu-ppc
[-- Attachment #1: Type: text/plain, Size: 1305 bytes --]
On Wed, Jan 11, 2017 at 07:42:04PM -0800, no-reply@patchew.org wrote:
> Hi,
>
> Your series seems to have some coding style problems. See output below for
> more information:
I don't think this is a real problem:
> Checking PATCH 46/67: target-ppc: Add xxextractuw instruction...
> ERROR: Macros with complex values should be enclosed in parenthesis
> #110: FILE: target/ppc/translate/vsx-ops.inc.c:52:
> +#define GEN_XX2FORM_EXT(name, opc2, opc3, fl2) \
> +GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0, opc3, 0x00100000, PPC_NONE, fl2), \
> +GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 1, opc3, 0x00100000, PPC_NONE, fl2)
>
> total: 1 errors, 0 warnings, 92 lines checked
>
> Your patch has style problems, please review. If any of these errors
> are false positives report them to the maintainer, see
> CHECKPATCH in MAINTAINERS.
This is the standard problem with checkpatch getting confused by the
ugly, ugly macros in the instruction decode stuff. Maybe we'll fix
that one day, but it's not a priority, and it's definitely out of
scope for this patch.
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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^ permalink raw reply [flat|nested] 73+ messages in thread
* Re: [Qemu-devel] [PULL 00/67] ppc-for-2.9 queue 20170112
2017-01-12 2:02 [Qemu-devel] [PULL 00/67] ppc-for-2.9 queue 20170112 David Gibson
` (67 preceding siblings ...)
2017-01-12 3:42 ` [Qemu-devel] [PULL 00/67] ppc-for-2.9 queue 20170112 no-reply
@ 2017-01-13 10:54 ` Peter Maydell
2017-01-13 11:09 ` Laurent Vivier
2017-01-16 21:33 ` David Gibson
68 siblings, 2 replies; 73+ messages in thread
From: Peter Maydell @ 2017-01-13 10:54 UTC (permalink / raw)
To: David Gibson
Cc: Alexander Graf, qemu-ppc, QEMU Developers, Thomas Huth,
Laurent Vivier, Alexey Kardashevskiy, Michael Roth
On 12 January 2017 at 02:02, David Gibson <david@gibson.dropbear.id.au> wrote:
> The following changes since commit b44486dfb9447c88e4b216e730adcc780190852c:
>
> Merge remote-tracking branch 'remotes/kraxel/tags/pull-ui-20170110-1' into staging (2017-01-10 14:52:34 +0000)
>
> are available in the git repository at:
>
> git://github.com/dgibson/qemu.git tags/ppc-for-2.9-20170112
>
> for you to fetch changes up to 229b5b6b56db9c3e6b8f44b4b55a62fa32979f47:
>
> ppc: Fix a warning in bcdcfz code and improve BCD_DIG_BYTE macro (2017-01-12 10:21:49 +1100)
>
> ----------------------------------------------------------------
> ppc patch queue 2017-01-12
>
> This is the first ppc pull request for qemu-2.9. It's been a while
> coming, partly due to dealing with some problems running my usual set
> of tests. So, there's quite a lot in here.
>
> * More POWER9 instruction implementations for TCG
> * The simpler parts of my CPU compatibility mode cleanup
> * This changes behaviour to prefer compatibility modes over
> "raW" mode for new machine type versions
> * New "40p" machine type which is essentially a modernized and
> cleaned up "prep". The intention is that it will replace "prep"
> once it has some more testing and polish.
> * Add pseries-2.9 machine type
> * Implement H_SIGNAL_SYS_RESET hypercall
> * Consolidate the two alternate CPU init paths in pseries by
> making it always go through CPU core objects to initialize CPU
> * A handful of bugfixes and cleanups
>
> There are also some changes not strictly related to ppc code, but for
> its benefit:
>
> * Limit the pxi-expander-bridge (PXB) device to x86 guests only
> (it's essentially a hack to work around historical x86
> limitations)
> * Revise a number of qtests and enable them for ppc
Hi -- this fails "make check" on OSX host:
GTESTER check-qtest-ppc64
qemu-system-ppc64: -object
memory-backend-file,id=mb1,size=1M,share,mem-path=/dev/shm/qtest-68237-4247260626:
invalid object type: memory-backend-file
Broken pipe
GTester: last random seed: R02Sc13bf53b8b3055a3c30552f67d7c263b
**
ERROR:/Users/pm215/src/qemu-for-merges/tests/libqos/pci.c:412:void
qpci_plug_device_test(const char *, const char *, uint8_t, const char
*): assertion failed: (!qdict_haskey(response, "error"))
GTester: last random seed: R02Sf3594a21c711ec941d5f4c89724ce12d
qemu-system-ppc64: -device ivshmem-plain,memdev=mb1: 'ivshmem-plain'
is not a valid device model name
Broken pipe
It looks like you've enabled the ivshmem test unconditionally,
but it should only be turned on if CONFIG_EVENTFD is true, see
how we do this for x86:
check-qtest-pci-$(CONFIG_EVENTFD) += tests/ivshmem-test$(EXESUF)
gcov-files-pci-y += hw/misc/ivshmem.c
Q: can we just enable these tests for PCI with
check-qtest-ppc64-y += $(check-qtest-pci-y)
gcov-files-ppc64-y += $(gcov-files-pci-y)
the way we do for i386/x86_64 ? Or is that doing too much
unwanted extra testing?
thanks
-- PMM
^ permalink raw reply [flat|nested] 73+ messages in thread
* Re: [Qemu-devel] [PULL 00/67] ppc-for-2.9 queue 20170112
2017-01-13 10:54 ` Peter Maydell
@ 2017-01-13 11:09 ` Laurent Vivier
2017-01-16 21:33 ` David Gibson
1 sibling, 0 replies; 73+ messages in thread
From: Laurent Vivier @ 2017-01-13 11:09 UTC (permalink / raw)
To: Peter Maydell, David Gibson
Cc: Alexander Graf, qemu-ppc, QEMU Developers, Thomas Huth,
Alexey Kardashevskiy, Michael Roth
On 13/01/2017 11:54, Peter Maydell wrote:
> Q: can we just enable these tests for PCI with
> check-qtest-ppc64-y += $(check-qtest-pci-y)
> gcov-files-ppc64-y += $(gcov-files-pci-y)
>
> the way we do for i386/x86_64 ? Or is that doing too much
> unwanted extra testing?
For most of the devices tested in check-qtest-pci-y, the test has not
been ported to ppc64 and fails (or hangs).
This is why we don't add the full list in check-qtest-ppc64-y.
Laurent
^ permalink raw reply [flat|nested] 73+ messages in thread
* Re: [Qemu-devel] [PULL 00/67] ppc-for-2.9 queue 20170112
2017-01-13 10:54 ` Peter Maydell
2017-01-13 11:09 ` Laurent Vivier
@ 2017-01-16 21:33 ` David Gibson
1 sibling, 0 replies; 73+ messages in thread
From: David Gibson @ 2017-01-16 21:33 UTC (permalink / raw)
To: Peter Maydell
Cc: Alexander Graf, qemu-ppc, QEMU Developers, Thomas Huth,
Laurent Vivier, Alexey Kardashevskiy, Michael Roth
[-- Attachment #1: Type: text/plain, Size: 3923 bytes --]
On Fri, Jan 13, 2017 at 10:54:33AM +0000, Peter Maydell wrote:
> On 12 January 2017 at 02:02, David Gibson <david@gibson.dropbear.id.au> wrote:
> > The following changes since commit b44486dfb9447c88e4b216e730adcc780190852c:
> >
> > Merge remote-tracking branch 'remotes/kraxel/tags/pull-ui-20170110-1' into staging (2017-01-10 14:52:34 +0000)
> >
> > are available in the git repository at:
> >
> > git://github.com/dgibson/qemu.git tags/ppc-for-2.9-20170112
> >
> > for you to fetch changes up to 229b5b6b56db9c3e6b8f44b4b55a62fa32979f47:
> >
> > ppc: Fix a warning in bcdcfz code and improve BCD_DIG_BYTE macro (2017-01-12 10:21:49 +1100)
> >
> > ----------------------------------------------------------------
> > ppc patch queue 2017-01-12
> >
> > This is the first ppc pull request for qemu-2.9. It's been a while
> > coming, partly due to dealing with some problems running my usual set
> > of tests. So, there's quite a lot in here.
> >
> > * More POWER9 instruction implementations for TCG
> > * The simpler parts of my CPU compatibility mode cleanup
> > * This changes behaviour to prefer compatibility modes over
> > "raW" mode for new machine type versions
> > * New "40p" machine type which is essentially a modernized and
> > cleaned up "prep". The intention is that it will replace "prep"
> > once it has some more testing and polish.
> > * Add pseries-2.9 machine type
> > * Implement H_SIGNAL_SYS_RESET hypercall
> > * Consolidate the two alternate CPU init paths in pseries by
> > making it always go through CPU core objects to initialize CPU
> > * A handful of bugfixes and cleanups
> >
> > There are also some changes not strictly related to ppc code, but for
> > its benefit:
> >
> > * Limit the pxi-expander-bridge (PXB) device to x86 guests only
> > (it's essentially a hack to work around historical x86
> > limitations)
> > * Revise a number of qtests and enable them for ppc
>
> Hi -- this fails "make check" on OSX host:
Bother. I saw the failure on Travis, but I was misled by all the SASL
warnings, and assumed it was an upstream / library problem, not
something with my patches.
> GTESTER check-qtest-ppc64
> qemu-system-ppc64: -object
> memory-backend-file,id=mb1,size=1M,share,mem-path=/dev/shm/qtest-68237-4247260626:
> invalid object type: memory-backend-file
> Broken pipe
> GTester: last random seed: R02Sc13bf53b8b3055a3c30552f67d7c263b
> **
> ERROR:/Users/pm215/src/qemu-for-merges/tests/libqos/pci.c:412:void
> qpci_plug_device_test(const char *, const char *, uint8_t, const char
> *): assertion failed: (!qdict_haskey(response, "error"))
> GTester: last random seed: R02Sf3594a21c711ec941d5f4c89724ce12d
> qemu-system-ppc64: -device ivshmem-plain,memdev=mb1: 'ivshmem-plain'
> is not a valid device model name
> Broken pipe
>
> It looks like you've enabled the ivshmem test unconditionally,
> but it should only be turned on if CONFIG_EVENTFD is true, see
> how we do this for x86:
>
> check-qtest-pci-$(CONFIG_EVENTFD) += tests/ivshmem-test$(EXESUF)
> gcov-files-pci-y += hw/misc/ivshmem.c
Ah, right, thanks.
> Q: can we just enable these tests for PCI with
> check-qtest-ppc64-y += $(check-qtest-pci-y)
> gcov-files-ppc64-y += $(gcov-files-pci-y)
>
> the way we do for i386/x86_64 ? Or is that doing too much
> unwanted extra testing?
As Laurent says, that doesn't quite work, but we can still put the
test on CONFIG_EVENTFD in. I've put a draft fix into my tree, but I
probably won't get a chance to properly test and resend until after
I'm back from LCA and holidays, around the end of Jan.
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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^ permalink raw reply [flat|nested] 73+ messages in thread
end of thread, other threads:[~2017-01-16 23:31 UTC | newest]
Thread overview: 73+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2017-01-12 2:02 [Qemu-devel] [PULL 00/67] ppc-for-2.9 queue 20170112 David Gibson
2017-01-12 2:02 ` [Qemu-devel] [PULL 01/67] disas/ppc: Fix indefinite articles in comments David Gibson
2017-01-12 2:02 ` [Qemu-devel] [PULL 02/67] target-ppc: Consolidate instruction decode helpers David Gibson
2017-01-12 2:02 ` [Qemu-devel] [PULL 03/67] target-ppc: rename CRF_* defines as CRF_*_BIT David Gibson
2017-01-12 2:02 ` [Qemu-devel] [PULL 04/67] target-ppc: Fix xscmpodp and xscmpudp instructions David Gibson
2017-01-12 2:02 ` [Qemu-devel] [PULL 05/67] target-ppc: Add xscmpexp[dp, qp] instructions David Gibson
2017-01-12 2:02 ` [Qemu-devel] [PULL 06/67] target-ppc: Add xscmpoqp and xscmpuqp instructions David Gibson
2017-01-12 2:02 ` [Qemu-devel] [PULL 07/67] target-ppc: implement lxsd and lxssp instructions David Gibson
2017-01-12 2:02 ` [Qemu-devel] [PULL 08/67] target-ppc: implement stxsd and stxssp David Gibson
2017-01-12 2:02 ` [Qemu-devel] [PULL 09/67] target-ppc: implement lxv/lxvx and stxv/stxvx David Gibson
2017-01-12 2:02 ` [Qemu-devel] [PULL 10/67] target-ppc: Implement bcdcfsq. instruction David Gibson
2017-01-12 2:02 ` [Qemu-devel] [PULL 11/67] target-ppc: Implement bcdctsq. instruction David Gibson
2017-01-12 2:02 ` [Qemu-devel] [PULL 12/67] target-ppc: Implement bcdcpsgn. instruction David Gibson
2017-01-12 2:02 ` [Qemu-devel] [PULL 13/67] target-ppc: Implement bcdsetsgn. instruction David Gibson
2017-01-12 2:02 ` [Qemu-devel] [PULL 14/67] target-ppc: add vextu[bhw][lr]x instructions David Gibson
2017-01-12 2:02 ` [Qemu-devel] [PULL 15/67] pseries: Always use core objects for CPU construction David Gibson
2017-01-12 2:02 ` [Qemu-devel] [PULL 16/67] pseries: Make cpu_update during CAS unconditional David Gibson
2017-01-12 2:02 ` [Qemu-devel] [PULL 17/67] ppc: Clean up and QOMify hypercall emulation David Gibson
2017-01-12 2:02 ` [Qemu-devel] [PULL 18/67] ppc: Rename cpu_version to compat_pvr David Gibson
2017-01-12 2:02 ` [Qemu-devel] [PULL 19/67] ppc/spapr: implement H_SIGNAL_SYS_RESET David Gibson
2017-01-12 2:02 ` [Qemu-devel] [PULL 20/67] target-ppc: move ppc_vsr_t to common header David Gibson
2017-01-12 2:02 ` [Qemu-devel] [PULL 21/67] target-ppc: implement stop instruction David Gibson
2017-01-12 2:02 ` [Qemu-devel] [PULL 22/67] target-ppc: implement xsabsqp/xsnabsqp instruction David Gibson
2017-01-12 2:02 ` [Qemu-devel] [PULL 23/67] target-ppc: Implement bcd_is_valid function David Gibson
2017-01-12 2:02 ` [Qemu-devel] [PULL 24/67] target-ppc: implement xsnegqp instruction David Gibson
2017-01-12 2:02 ` [Qemu-devel] [PULL 25/67] target-ppc: implement xscpsgnqp instruction David Gibson
2017-01-12 2:02 ` [Qemu-devel] [PULL 26/67] target-ppc: Add xxperm and xxpermr instructions David Gibson
2017-01-12 2:02 ` [Qemu-devel] [PULL 27/67] target-ppc: implement lxvl instruction David Gibson
2017-01-12 2:02 ` [Qemu-devel] [PULL 28/67] target-ppc: implement lxvll instruction David Gibson
2017-01-12 2:02 ` [Qemu-devel] [PULL 29/67] target-ppc: implement stxvl instruction David Gibson
2017-01-12 2:02 ` [Qemu-devel] [PULL 30/67] target-ppc: implement stxvll instructions David Gibson
2017-01-12 2:02 ` [Qemu-devel] [PULL 31/67] hw/ppc/spapr: Fix boot path of usb-host storage devices David Gibson
2017-01-12 2:02 ` [Qemu-devel] [PULL 32/67] prep: do not use global variable to access nvram David Gibson
2017-01-12 2:02 ` [Qemu-devel] [PULL 33/67] pseries: Add pseries-2.9 machine type David Gibson
2017-01-12 2:02 ` [Qemu-devel] [PULL 34/67] ppc: Rewrite ppc_set_compat() David Gibson
2017-01-12 2:02 ` [Qemu-devel] [PULL 35/67] ppc: Rewrite ppc_get_compat_smt_threads() David Gibson
2017-01-12 2:02 ` [Qemu-devel] [PULL 36/67] ppc: Validate compatibility modes when setting David Gibson
2017-01-12 2:02 ` [Qemu-devel] [PULL 37/67] qtest: add netfilter tests for ppc64 David Gibson
2017-01-12 2:02 ` [Qemu-devel] [PULL 38/67] qtest: add display-vga-test to ppc64 David Gibson
2017-01-12 2:02 ` [Qemu-devel] [PULL 39/67] libqos: fix spapr qpci_map() David Gibson
2017-01-12 2:03 ` [Qemu-devel] [PULL 40/67] qtest: convert ivshmem-test to use libqos David Gibson
2017-01-12 2:03 ` [Qemu-devel] [PULL 41/67] qtest: add ivshmem-test for ppc64 David Gibson
2017-01-12 2:03 ` [Qemu-devel] [PULL 42/67] hw/gpio: QOM'ify mpc8xxx.c David Gibson
2017-01-12 2:03 ` [Qemu-devel] [PULL 43/67] hw/ppc: QOM'ify e500.c David Gibson
2017-01-12 2:03 ` [Qemu-devel] [PULL 44/67] hw/ppc: QOM'ify ppce500_spin.c David Gibson
2017-01-12 2:03 ` [Qemu-devel] [PULL 45/67] hw/ppc: QOM'ify spapr_vio.c David Gibson
2017-01-12 2:03 ` [Qemu-devel] [PULL 46/67] target-ppc: Add xxextractuw instruction David Gibson
2017-01-12 2:03 ` [Qemu-devel] [PULL 47/67] target-ppc: Add xxinsertw instruction David Gibson
2017-01-12 2:03 ` [Qemu-devel] [PULL 48/67] prep: add PReP System I/O David Gibson
2017-01-12 2:03 ` [Qemu-devel] [PULL 49/67] prep: add IBM RS/6000 7020 (40p) memory controller David Gibson
2017-01-12 2:03 ` [Qemu-devel] [PULL 50/67] prep: add IBM RS/6000 7020 (40p) machine emulation David Gibson
2017-01-12 2:03 ` [Qemu-devel] [PULL 51/67] target-ppc: Use float64 arg in helper_compute_fprf() David Gibson
2017-01-12 2:03 ` [Qemu-devel] [PULL 52/67] target-ppc: Replace isden by float64_is_zero_or_denormal David Gibson
2017-01-12 2:03 ` [Qemu-devel] [PULL 53/67] target-ppc: Rename helper_compute_fprf to helper_compute_fprf_float64 David Gibson
2017-01-12 2:03 ` [Qemu-devel] [PULL 54/67] target-ppc: Add xscvdphp, xscvhpdp David Gibson
2017-01-12 2:03 ` [Qemu-devel] [PULL 55/67] target-ppc: Use correct precision for FPRF setting David Gibson
2017-01-12 2:03 ` [Qemu-devel] [PULL 56/67] target-ppc: Add xsxexpdp instruction David Gibson
2017-01-12 2:03 ` [Qemu-devel] [PULL 57/67] target-ppc: Add xsxexpqp instruction David Gibson
2017-01-12 2:03 ` [Qemu-devel] [PULL 58/67] target-ppc: Add xsxsigdp instruction David Gibson
2017-01-12 2:03 ` [Qemu-devel] [PULL 59/67] target-ppc: Add xsxsigqp instructions David Gibson
2017-01-12 2:03 ` [Qemu-devel] [PULL 60/67] pxb: Restrict to x86 David Gibson
2017-01-12 2:03 ` [Qemu-devel] [PULL 61/67] pseries: Rewrite CAS PVR compatibility logic David Gibson
2017-01-12 2:03 ` [Qemu-devel] [PULL 62/67] ppc: Add ppc_set_compat_all() David Gibson
2017-01-12 2:03 ` [Qemu-devel] [PULL 63/67] target-ppc: Add xsaddqp instructions David Gibson
2017-01-12 2:03 ` [Qemu-devel] [PULL 64/67] target-ppc: Add xscvdpqp instruction David Gibson
2017-01-12 2:03 ` [Qemu-devel] [PULL 65/67] target-ppc: Add xscvqpdp instruction David Gibson
2017-01-12 2:03 ` [Qemu-devel] [PULL 66/67] ppc: Prevent inifnite loop in decrementer auto-reload David Gibson
2017-01-12 2:03 ` [Qemu-devel] [PULL 67/67] ppc: Fix a warning in bcdcfz code and improve BCD_DIG_BYTE macro David Gibson
2017-01-12 3:42 ` [Qemu-devel] [PULL 00/67] ppc-for-2.9 queue 20170112 no-reply
2017-01-12 23:36 ` David Gibson
2017-01-13 10:54 ` Peter Maydell
2017-01-13 11:09 ` Laurent Vivier
2017-01-16 21:33 ` David Gibson
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