[PATCH 0/2] MediaTek eMMC inline encryption support

[PATCH 0/2] MediaTek eMMC inline encryption support

[Mengqi Zhang]

Hello,

Mediatek eMMC hardware IP has Inline Crypto Engine (ICE), we support inline encryption now.

This patchset supports Mediatek eMMC inline encryption which meets the upcoming version of the eMMC specification such as v5.1 or v5.2.

Patch 1, add crypto clock control flow in mtk-sd driver, patch 2, document the device tree description about crypto clock.


Mengqi Zhang (2):
  mmc: mtk-sd: add Inline Crypto Engine support
  dt-bingdings: mmc: Mediatek: add ICE clock

 Documentation/devicetree/bindings/mmc/mtk-sd.yaml |  4 ++++
 drivers/mmc/host/mtk-sd.c                         | 12 ++++++++++++
 2 files changed, 16 insertions(+)

[PATCH 0/2] MediaTek eMMC inline encryption support

[Mengqi Zhang]

Hello,

Mediatek eMMC hardware IP has Inline Crypto Engine (ICE), we support inline encryption now.

This patchset supports Mediatek eMMC inline encryption which meets the upcoming version of the eMMC specification such as v5.1 or v5.2.

Patch 1, add crypto clock control flow in mtk-sd driver, patch 2, document the device tree description about crypto clock.


Mengqi Zhang (2):
  mmc: mtk-sd: add Inline Crypto Engine support
  dt-bingdings: mmc: Mediatek: add ICE clock

 Documentation/devicetree/bindings/mmc/mtk-sd.yaml |  4 ++++
 drivers/mmc/host/mtk-sd.c                         | 12 ++++++++++++
 2 files changed, 16 insertions(+)



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[PATCH 1/2] mmc: mtk-sd: add Inline Crypto Engine support

[Mengqi Zhang]

add crypto clock control and ungate it before CQHCI init.

Signed-off-by: Mengqi Zhang <mengqi.zhang@mediatek.com>
---
 drivers/mmc/host/mtk-sd.c | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/drivers/mmc/host/mtk-sd.c b/drivers/mmc/host/mtk-sd.c
index 69d78604d1fc..8b6ef8691e5b 100644
--- a/drivers/mmc/host/mtk-sd.c
+++ b/drivers/mmc/host/mtk-sd.c
@@ -452,6 +452,7 @@ struct msdc_host {
 	struct clk *bus_clk;	/* bus clock which used to access register */
 	struct clk *src_clk_cg; /* msdc source clock control gate */
 	struct clk *sys_clk_cg;	/* msdc subsys clock control gate */
+	struct clk *crypto_clk; /* msdc crypto clock control gate */
 	struct clk_bulk_data bulk_clks[MSDC_NR_CLOCKS];
 	u32 mclk;		/* mmc subsystem clock frequency */
 	u32 src_clk_freq;	/* source clock frequency */
@@ -811,6 +812,7 @@ static void msdc_set_busy_timeout(struct msdc_host *host, u64 ns, u64 clks)
 static void msdc_gate_clock(struct msdc_host *host)
 {
 	clk_bulk_disable_unprepare(MSDC_NR_CLOCKS, host->bulk_clks);
+	clk_disable_unprepare(host->crypto_clk);
 	clk_disable_unprepare(host->src_clk_cg);
 	clk_disable_unprepare(host->src_clk);
 	clk_disable_unprepare(host->bus_clk);
@@ -826,6 +828,7 @@ static int msdc_ungate_clock(struct msdc_host *host)
 	clk_prepare_enable(host->bus_clk);
 	clk_prepare_enable(host->src_clk);
 	clk_prepare_enable(host->src_clk_cg);
+	clk_prepare_enable(host->crypto_clk);
 	ret = clk_bulk_prepare_enable(MSDC_NR_CLOCKS, host->bulk_clks);
 	if (ret) {
 		dev_err(host->dev, "Cannot enable pclk/axi/ahb clock gates\n");
@@ -2643,6 +2646,15 @@ static int msdc_drv_probe(struct platform_device *pdev)
 		goto host_free;
 	}
 
+	/* only eMMC has crypto property */
+	if (!(mmc->caps2 & MMC_CAP2_NO_MMC)) {
+		host->crypto_clk = devm_clk_get_optional(&pdev->dev, "crypto");
+		if (IS_ERR(host->crypto_clk))
+			host->crypto_clk = NULL;
+		else
+			mmc->caps2 |= MMC_CAP2_CRYPTO;
+	}
+
 	host->irq = platform_get_irq(pdev, 0);
 	if (host->irq < 0) {
 		ret = -EINVAL;
-- 
2.25.1

[PATCH 1/2] mmc: mtk-sd: add Inline Crypto Engine support

[Mengqi Zhang]

add crypto clock control and ungate it before CQHCI init.

Signed-off-by: Mengqi Zhang <mengqi.zhang@mediatek.com>
---
 drivers/mmc/host/mtk-sd.c | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/drivers/mmc/host/mtk-sd.c b/drivers/mmc/host/mtk-sd.c
index 69d78604d1fc..8b6ef8691e5b 100644
--- a/drivers/mmc/host/mtk-sd.c
+++ b/drivers/mmc/host/mtk-sd.c
@@ -452,6 +452,7 @@ struct msdc_host {
 	struct clk *bus_clk;	/* bus clock which used to access register */
 	struct clk *src_clk_cg; /* msdc source clock control gate */
 	struct clk *sys_clk_cg;	/* msdc subsys clock control gate */
+	struct clk *crypto_clk; /* msdc crypto clock control gate */
 	struct clk_bulk_data bulk_clks[MSDC_NR_CLOCKS];
 	u32 mclk;		/* mmc subsystem clock frequency */
 	u32 src_clk_freq;	/* source clock frequency */
@@ -811,6 +812,7 @@ static void msdc_set_busy_timeout(struct msdc_host *host, u64 ns, u64 clks)
 static void msdc_gate_clock(struct msdc_host *host)
 {
 	clk_bulk_disable_unprepare(MSDC_NR_CLOCKS, host->bulk_clks);
+	clk_disable_unprepare(host->crypto_clk);
 	clk_disable_unprepare(host->src_clk_cg);
 	clk_disable_unprepare(host->src_clk);
 	clk_disable_unprepare(host->bus_clk);
@@ -826,6 +828,7 @@ static int msdc_ungate_clock(struct msdc_host *host)
 	clk_prepare_enable(host->bus_clk);
 	clk_prepare_enable(host->src_clk);
 	clk_prepare_enable(host->src_clk_cg);
+	clk_prepare_enable(host->crypto_clk);
 	ret = clk_bulk_prepare_enable(MSDC_NR_CLOCKS, host->bulk_clks);
 	if (ret) {
 		dev_err(host->dev, "Cannot enable pclk/axi/ahb clock gates\n");
@@ -2643,6 +2646,15 @@ static int msdc_drv_probe(struct platform_device *pdev)
 		goto host_free;
 	}
 
+	/* only eMMC has crypto property */
+	if (!(mmc->caps2 & MMC_CAP2_NO_MMC)) {
+		host->crypto_clk = devm_clk_get_optional(&pdev->dev, "crypto");
+		if (IS_ERR(host->crypto_clk))
+			host->crypto_clk = NULL;
+		else
+			mmc->caps2 |= MMC_CAP2_CRYPTO;
+	}
+
 	host->irq = platform_get_irq(pdev, 0);
 	if (host->irq < 0) {
 		ret = -EINVAL;
-- 
2.25.1


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[PATCH 2/2] dt-bingdings: mmc: Mediatek: add ICE clock

[Mengqi Zhang]

Document the binding for crypto clock of the Inline Crypto Engine
of Mediatek SoCs.

Signed-off-by: Mengqi Zhang <mengqi.zhang@mediatek.com>
---
 Documentation/devicetree/bindings/mmc/mtk-sd.yaml | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/Documentation/devicetree/bindings/mmc/mtk-sd.yaml b/Documentation/devicetree/bindings/mmc/mtk-sd.yaml
index d8e1e2e9adf2..f93d686e2911 100644
--- a/Documentation/devicetree/bindings/mmc/mtk-sd.yaml
+++ b/Documentation/devicetree/bindings/mmc/mtk-sd.yaml
@@ -57,6 +57,7 @@ properties:
       - description: peripheral bus clock gate (required for MT8192).
       - description: AXI bus clock gate (required for MT8192).
       - description: AHB bus clock gate (required for MT8192).
+      - description: crypto clock used for data encrypt/decrypt (optional).
 
   clock-names:
     minItems: 2
@@ -69,6 +70,7 @@ properties:
       - const: pclk_cg
       - const: axi_cg
       - const: ahb_cg
+      - const: crypto
 
   interrupts:
     description:
-- 
2.25.1

[PATCH 2/2] dt-bingdings: mmc: Mediatek: add ICE clock

[Mengqi Zhang]

Document the binding for crypto clock of the Inline Crypto Engine
of Mediatek SoCs.

Signed-off-by: Mengqi Zhang <mengqi.zhang@mediatek.com>
---
 Documentation/devicetree/bindings/mmc/mtk-sd.yaml | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/Documentation/devicetree/bindings/mmc/mtk-sd.yaml b/Documentation/devicetree/bindings/mmc/mtk-sd.yaml
index d8e1e2e9adf2..f93d686e2911 100644
--- a/Documentation/devicetree/bindings/mmc/mtk-sd.yaml
+++ b/Documentation/devicetree/bindings/mmc/mtk-sd.yaml
@@ -57,6 +57,7 @@ properties:
       - description: peripheral bus clock gate (required for MT8192).
       - description: AXI bus clock gate (required for MT8192).
       - description: AHB bus clock gate (required for MT8192).
+      - description: crypto clock used for data encrypt/decrypt (optional).
 
   clock-names:
     minItems: 2
@@ -69,6 +70,7 @@ properties:
       - const: pclk_cg
       - const: axi_cg
       - const: ahb_cg
+      - const: crypto
 
   interrupts:
     description:
-- 
2.25.1


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Re: [PATCH 1/2] mmc: mtk-sd: add Inline Crypto Engine support

[AngeloGioacchino Del Regno]

Il 17/10/22 16:20, Mengqi Zhang ha scritto:
> add crypto clock control and ungate it before CQHCI init.
> 
> Signed-off-by: Mengqi Zhang <mengqi.zhang@mediatek.com>

Hello Mengqi,
I'm a bit surprised that enabling ICE only requires enabling a clock as
on downstream code I see some SMC calls to MTK_SIP_KERNEL_HW_FDE_MSDC_CTL.

Can you please explain why SMC calls are not needed here?

Thanks,
Angelo

Re: [PATCH 1/2] mmc: mtk-sd: add Inline Crypto Engine support

[AngeloGioacchino Del Regno]

Il 17/10/22 16:20, Mengqi Zhang ha scritto:
> add crypto clock control and ungate it before CQHCI init.
> 
> Signed-off-by: Mengqi Zhang <mengqi.zhang@mediatek.com>

Hello Mengqi,
I'm a bit surprised that enabling ICE only requires enabling a clock as
on downstream code I see some SMC calls to MTK_SIP_KERNEL_HW_FDE_MSDC_CTL.

Can you please explain why SMC calls are not needed here?

Thanks,
Angelo


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Re: [PATCH 2/2] dt-bingdings: mmc: Mediatek: add ICE clock

[AngeloGioacchino Del Regno]

Il 17/10/22 16:20, Mengqi Zhang ha scritto:
> Document the binding for crypto clock of the Inline Crypto Engine
> of Mediatek SoCs.
> 
> Signed-off-by: Mengqi Zhang <mengqi.zhang@mediatek.com>

Looks good, but please fix the typo in the commit title.

Regards,
Angelo

Re: [PATCH 2/2] dt-bingdings: mmc: Mediatek: add ICE clock

[AngeloGioacchino Del Regno]

Il 17/10/22 16:20, Mengqi Zhang ha scritto:
> Document the binding for crypto clock of the Inline Crypto Engine
> of Mediatek SoCs.
> 
> Signed-off-by: Mengqi Zhang <mengqi.zhang@mediatek.com>

Looks good, but please fix the typo in the commit title.

Regards,
Angelo


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Re: [PATCH 2/2] dt-bingdings: mmc: Mediatek: add ICE clock

[Krzysztof Kozlowski]

On 17/10/2022 10:20, Mengqi Zhang wrote:
> Document the binding for crypto clock of the Inline Crypto Engine
> of Mediatek SoCs.

This does not match the patch contents at all.

> 
> Signed-off-by: Mengqi Zhang <mengqi.zhang@mediatek.com>
> ---
>  Documentation/devicetree/bindings/mmc/mtk-sd.yaml | 2 ++
>  1 file changed, 2 insertions(+)

Best regards,
Krzysztof

Re: [PATCH 2/2] dt-bingdings: mmc: Mediatek: add ICE clock

[Krzysztof Kozlowski]

On 17/10/2022 10:20, Mengqi Zhang wrote:
> Document the binding for crypto clock of the Inline Crypto Engine
> of Mediatek SoCs.

This does not match the patch contents at all.

> 
> Signed-off-by: Mengqi Zhang <mengqi.zhang@mediatek.com>
> ---
>  Documentation/devicetree/bindings/mmc/mtk-sd.yaml | 2 ++
>  1 file changed, 2 insertions(+)

Best regards,
Krzysztof


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Re: [PATCH 2/2] dt-bingdings: mmc: Mediatek: add ICE clock

[Krzysztof Kozlowski]

On 18/10/2022 14:29, Krzysztof Kozlowski wrote:
> On 17/10/2022 10:20, Mengqi Zhang wrote:
>> Document the binding for crypto clock of the Inline Crypto Engine
>> of Mediatek SoCs.
> > This does not match the patch contents at all.

Ah, my bad, I read "crypto block", not clock, so it matches. :)

However you are not documenting a binding for it. You are adding
optional clock.

> 
>>
>> Signed-off-by: Mengqi Zhang <mengqi.zhang@mediatek.com>
>> ---
>>  Documentation/devicetree/bindings/mmc/mtk-sd.yaml | 2 ++
>>  1 file changed, 2 insertions(+)
> 
> Best regards,
> Krzysztof
> 

Best regards,
Krzysztof

Re: [PATCH 2/2] dt-bingdings: mmc: Mediatek: add ICE clock

[Krzysztof Kozlowski]

On 18/10/2022 14:29, Krzysztof Kozlowski wrote:
> On 17/10/2022 10:20, Mengqi Zhang wrote:
>> Document the binding for crypto clock of the Inline Crypto Engine
>> of Mediatek SoCs.
> > This does not match the patch contents at all.

Ah, my bad, I read "crypto block", not clock, so it matches. :)

However you are not documenting a binding for it. You are adding
optional clock.

> 
>>
>> Signed-off-by: Mengqi Zhang <mengqi.zhang@mediatek.com>
>> ---
>>  Documentation/devicetree/bindings/mmc/mtk-sd.yaml | 2 ++
>>  1 file changed, 2 insertions(+)
> 
> Best regards,
> Krzysztof
> 

Best regards,
Krzysztof


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Re: [PATCH 1/2] mmc: mtk-sd: add Inline Crypto Engine support

[Mengqi Zhang (张梦琦)]

On Tue, 2022-10-18 at 11:50 +0200, AngeloGioacchino Del Regno wrote:
> Il 17/10/22 16:20, Mengqi Zhang ha scritto:
> > add crypto clock control and ungate it before CQHCI init.
> > 
> > Signed-off-by: Mengqi Zhang <mengqi.zhang@mediatek.com>
> 
> Hello Mengqi,
> I'm a bit surprised that enabling ICE only requires enabling a clock
> as
> on downstream code I see some SMC calls to
> MTK_SIP_KERNEL_HW_FDE_MSDC_CTL.
> 
> Can you please explain why SMC calls are not needed here?
> 
> Thanks,
> Angelo

> Hi Angelo,
> 
> In some MTK SoCs, we need set a encrypto enable bit
> MTK_SIP_KERNEL_HW_FDE_MSDC_CTL in secure world, so we use SMC call to
> finish it.
> But not every MTK SoC need to set this bit in secure world. This
> patch is for these SoCs.
> As for SMC call, we haven't found a proper way to deal with it, we'll
> do it later.
> 
> Thanks,
> Mengqi.Zhang
> 

Re: [PATCH 1/2] mmc: mtk-sd: add Inline Crypto Engine support

[Mengqi Zhang (张梦琦)]

On Tue, 2022-10-18 at 11:50 +0200, AngeloGioacchino Del Regno wrote:
> Il 17/10/22 16:20, Mengqi Zhang ha scritto:
> > add crypto clock control and ungate it before CQHCI init.
> > 
> > Signed-off-by: Mengqi Zhang <mengqi.zhang@mediatek.com>
> 
> Hello Mengqi,
> I'm a bit surprised that enabling ICE only requires enabling a clock
> as
> on downstream code I see some SMC calls to
> MTK_SIP_KERNEL_HW_FDE_MSDC_CTL.
> 
> Can you please explain why SMC calls are not needed here?
> 
> Thanks,
> Angelo

> Hi Angelo,
> 
> In some MTK SoCs, we need set a encrypto enable bit
> MTK_SIP_KERNEL_HW_FDE_MSDC_CTL in secure world, so we use SMC call to
> finish it.
> But not every MTK SoC need to set this bit in secure world. This
> patch is for these SoCs.
> As for SMC call, we haven't found a proper way to deal with it, we'll
> do it later.
> 
> Thanks,
> Mengqi.Zhang
> 
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Re: [PATCH 1/2] mmc: mtk-sd: add Inline Crypto Engine support

[Mengqi Zhang (张梦琦)]

On Tue, 2022-10-18 at 11:50 +0200, AngeloGioacchino Del Regno wrote:
> Il 17/10/22 16:20, Mengqi Zhang ha scritto:
> > add crypto clock control and ungate it before CQHCI init.
> > 
> > Signed-off-by: Mengqi Zhang <mengqi.zhang@mediatek.com>
> 
> Hello Mengqi,
> I'm a bit surprised that enabling ICE only requires enabling a clock
> as
> on downstream code I see some SMC calls to
> MTK_SIP_KERNEL_HW_FDE_MSDC_CTL.
> 
> Can you please explain why SMC calls are not needed here?
> 
> Thanks,
> Angelo
> 

Hi Angelo,

There are many wrong quotes in previous reply, let me fix it here.

In some MTK SoC, we need set a encrypto enable bit
MTK_SIP_KERNEL_HW_FDE_MSDC_CTL in secure world, so we use SMC call to
finish it.
But not every MTK SoC need to set this bit in secure world. This patch
is for these SoCs.
As for SMC call, we haven't found a proper way to deal with it, we'll
do it later.

Thanks,
Mengqi.Zhang

Re: [PATCH 1/2] mmc: mtk-sd: add Inline Crypto Engine support

[Mengqi Zhang (张梦琦)]

On Tue, 2022-10-18 at 11:50 +0200, AngeloGioacchino Del Regno wrote:
> Il 17/10/22 16:20, Mengqi Zhang ha scritto:
> > add crypto clock control and ungate it before CQHCI init.
> > 
> > Signed-off-by: Mengqi Zhang <mengqi.zhang@mediatek.com>
> 
> Hello Mengqi,
> I'm a bit surprised that enabling ICE only requires enabling a clock
> as
> on downstream code I see some SMC calls to
> MTK_SIP_KERNEL_HW_FDE_MSDC_CTL.
> 
> Can you please explain why SMC calls are not needed here?
> 
> Thanks,
> Angelo
> 

Hi Angelo,

There are many wrong quotes in previous reply, let me fix it here.

In some MTK SoC, we need set a encrypto enable bit
MTK_SIP_KERNEL_HW_FDE_MSDC_CTL in secure world, so we use SMC call to
finish it.
But not every MTK SoC need to set this bit in secure world. This patch
is for these SoCs.
As for SMC call, we haven't found a proper way to deal with it, we'll
do it later.

Thanks,
Mengqi.Zhang
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Re: [PATCH 1/2] mmc: mtk-sd: add Inline Crypto Engine support

[AngeloGioacchino Del Regno]

Il 31/10/22 10:50, Mengqi Zhang (张梦琦) ha scritto:
> On Tue, 2022-10-18 at 11:50 +0200, AngeloGioacchino Del Regno wrote:
>> Il 17/10/22 16:20, Mengqi Zhang ha scritto:
>>> add crypto clock control and ungate it before CQHCI init.
>>>
>>> Signed-off-by: Mengqi Zhang <mengqi.zhang@mediatek.com>
>>
>> Hello Mengqi,
>> I'm a bit surprised that enabling ICE only requires enabling a clock
>> as
>> on downstream code I see some SMC calls to
>> MTK_SIP_KERNEL_HW_FDE_MSDC_CTL.
>>
>> Can you please explain why SMC calls are not needed here?
>>
>> Thanks,
>> Angelo
>>
> 
> Hi Angelo,
> 
> There are many wrong quotes in previous reply, let me fix it here.
> 
> In some MTK SoC, we need set a encrypto enable bit
> MTK_SIP_KERNEL_HW_FDE_MSDC_CTL in secure world, so we use SMC call to
> finish it.
> But not every MTK SoC need to set this bit in secure world. This patch
> is for these SoCs.
> As for SMC call, we haven't found a proper way to deal with it, we'll
> do it later.
> 

Thanks for clarifying.
In that case, I'm a little worried about people trying to enable ICE on SoCs
that do require calling into TZ and getting a crash... but it's anyway out of
scope for this series, so:

Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

Re: [PATCH 1/2] mmc: mtk-sd: add Inline Crypto Engine support

[AngeloGioacchino Del Regno]

Il 31/10/22 10:50, Mengqi Zhang (张梦琦) ha scritto:
> On Tue, 2022-10-18 at 11:50 +0200, AngeloGioacchino Del Regno wrote:
>> Il 17/10/22 16:20, Mengqi Zhang ha scritto:
>>> add crypto clock control and ungate it before CQHCI init.
>>>
>>> Signed-off-by: Mengqi Zhang <mengqi.zhang@mediatek.com>
>>
>> Hello Mengqi,
>> I'm a bit surprised that enabling ICE only requires enabling a clock
>> as
>> on downstream code I see some SMC calls to
>> MTK_SIP_KERNEL_HW_FDE_MSDC_CTL.
>>
>> Can you please explain why SMC calls are not needed here?
>>
>> Thanks,
>> Angelo
>>
> 
> Hi Angelo,
> 
> There are many wrong quotes in previous reply, let me fix it here.
> 
> In some MTK SoC, we need set a encrypto enable bit
> MTK_SIP_KERNEL_HW_FDE_MSDC_CTL in secure world, so we use SMC call to
> finish it.
> But not every MTK SoC need to set this bit in secure world. This patch
> is for these SoCs.
> As for SMC call, we haven't found a proper way to deal with it, we'll
> do it later.
> 

Thanks for clarifying.
In that case, I'm a little worried about people trying to enable ICE on SoCs
that do require calling into TZ and getting a crash... but it's anyway out of
scope for this series, so:

Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>



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Re: [PATCH 2/2] dt-bingdings: mmc: Mediatek: add ICE clock

[Ulf Hansson]

On Mon, 17 Oct 2022 at 16:20, Mengqi Zhang <mengqi.zhang@mediatek.com> wrote:
>
> Document the binding for crypto clock of the Inline Crypto Engine
> of Mediatek SoCs.
>
> Signed-off-by: Mengqi Zhang <mengqi.zhang@mediatek.com>
> ---
>  Documentation/devicetree/bindings/mmc/mtk-sd.yaml | 2 ++
>  1 file changed, 2 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/mmc/mtk-sd.yaml b/Documentation/devicetree/bindings/mmc/mtk-sd.yaml
> index d8e1e2e9adf2..f93d686e2911 100644
> --- a/Documentation/devicetree/bindings/mmc/mtk-sd.yaml
> +++ b/Documentation/devicetree/bindings/mmc/mtk-sd.yaml
> @@ -57,6 +57,7 @@ properties:
>        - description: peripheral bus clock gate (required for MT8192).
>        - description: AXI bus clock gate (required for MT8192).
>        - description: AHB bus clock gate (required for MT8192).
> +      - description: crypto clock used for data encrypt/decrypt (optional).
>
>    clock-names:
>      minItems: 2
> @@ -69,6 +70,7 @@ properties:
>        - const: pclk_cg
>        - const: axi_cg
>        - const: ahb_cg
> +      - const: crypto

Looks like minItems/maxItems for clocks needs to be updated too.

>
>    interrupts:
>      description:
> --
> 2.25.1
>

Kind regards
Uffe

Re: [PATCH 2/2] dt-bingdings: mmc: Mediatek: add ICE clock

[Ulf Hansson]

On Mon, 17 Oct 2022 at 16:20, Mengqi Zhang <mengqi.zhang@mediatek.com> wrote:
>
> Document the binding for crypto clock of the Inline Crypto Engine
> of Mediatek SoCs.
>
> Signed-off-by: Mengqi Zhang <mengqi.zhang@mediatek.com>
> ---
>  Documentation/devicetree/bindings/mmc/mtk-sd.yaml | 2 ++
>  1 file changed, 2 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/mmc/mtk-sd.yaml b/Documentation/devicetree/bindings/mmc/mtk-sd.yaml
> index d8e1e2e9adf2..f93d686e2911 100644
> --- a/Documentation/devicetree/bindings/mmc/mtk-sd.yaml
> +++ b/Documentation/devicetree/bindings/mmc/mtk-sd.yaml
> @@ -57,6 +57,7 @@ properties:
>        - description: peripheral bus clock gate (required for MT8192).
>        - description: AXI bus clock gate (required for MT8192).
>        - description: AHB bus clock gate (required for MT8192).
> +      - description: crypto clock used for data encrypt/decrypt (optional).
>
>    clock-names:
>      minItems: 2
> @@ -69,6 +70,7 @@ properties:
>        - const: pclk_cg
>        - const: axi_cg
>        - const: ahb_cg
> +      - const: crypto

Looks like minItems/maxItems for clocks needs to be updated too.

>
>    interrupts:
>      description:
> --
> 2.25.1
>

Kind regards
Uffe

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Re: [PATCH 2/2] dt-bingdings: mmc: Mediatek: add ICE clock

[Mengqi Zhang (张梦琦)]

On Tue, 2022-10-18 at 11:50 +0200, AngeloGioacchino Del Regno wrote:
> Il 17/10/22 16:20, Mengqi Zhang ha scritto:
> > Document the binding for crypto clock of the Inline Crypto Engine
> > of Mediatek SoCs.
> > 
> > Signed-off-by: Mengqi Zhang <mengqi.zhang@mediatek.com>
> 
> Looks good, but please fix the typo in the commit title.
> 
> Regards,
> Angelo
> 

Hi Angelo,
I have re-sent my patch base on new code base.

https://lore.kernel.org/linux-mmc/20221106033924.9854-3-mengqi.zhang@mediatek.com/
Please help to review.
Thanks!

Regards,
Mengqi

Re: [PATCH 2/2] dt-bingdings: mmc: Mediatek: add ICE clock

[Mengqi Zhang (张梦琦)]

On Tue, 2022-10-18 at 11:50 +0200, AngeloGioacchino Del Regno wrote:
> Il 17/10/22 16:20, Mengqi Zhang ha scritto:
> > Document the binding for crypto clock of the Inline Crypto Engine
> > of Mediatek SoCs.
> > 
> > Signed-off-by: Mengqi Zhang <mengqi.zhang@mediatek.com>
> 
> Looks good, but please fix the typo in the commit title.
> 
> Regards,
> Angelo
> 

Hi Angelo,
I have re-sent my patch base on new code base.

https://lore.kernel.org/linux-mmc/20221106033924.9854-3-mengqi.zhang@mediatek.com/
Please help to review.
Thanks!

Regards,
Mengqi
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

Re: [PATCH 2/2] dt-bingdings: mmc: Mediatek: add ICE clock

[Mengqi Zhang (张梦琦)]

On Wed, 2022-11-02 at 16:13 +0100, Ulf Hansson wrote:
> On Mon, 17 Oct 2022 at 16:20, Mengqi Zhang <mengqi.zhang@mediatek.com
> > wrote:
> > 
> > Document the binding for crypto clock of the Inline Crypto Engine
> > of Mediatek SoCs.
> > 
> > Signed-off-by: Mengqi Zhang <mengqi.zhang@mediatek.com>
> > ---
> >  Documentation/devicetree/bindings/mmc/mtk-sd.yaml | 2 ++
> >  1 file changed, 2 insertions(+)
> > 
> > diff --git a/Documentation/devicetree/bindings/mmc/mtk-sd.yaml
> > b/Documentation/devicetree/bindings/mmc/mtk-sd.yaml
> > index d8e1e2e9adf2..f93d686e2911 100644
> > --- a/Documentation/devicetree/bindings/mmc/mtk-sd.yaml
> > +++ b/Documentation/devicetree/bindings/mmc/mtk-sd.yaml
> > @@ -57,6 +57,7 @@ properties:
> >        - description: peripheral bus clock gate (required for
> > MT8192).
> >        - description: AXI bus clock gate (required for MT8192).
> >        - description: AHB bus clock gate (required for MT8192).
> > +      - description: crypto clock used for data encrypt/decrypt
> > (optional).
> > 
> >    clock-names:
> >      minItems: 2
> > @@ -69,6 +70,7 @@ properties:
> >        - const: pclk_cg
> >        - const: axi_cg
> >        - const: ahb_cg
> > +      - const: crypto
> 
> Looks like minItems/maxItems for clocks needs to be updated too.
> 
> > 
> >    interrupts:
> >      description:
> > --
> > 2.25.1
> > 
> 
> Kind regards
> Uffe

Hi Uffe,

I just add crypto clock to mt8186/mt8188/mt8195, does not exceed the
minItems/maxItems.

I have re-sent my patch,

https://lore.kernel.org/linux-mmc/20221106033924.9854-3-mengqi.zhang@mediatek.com/
Please help to review it.
Thanks!

Regards,
Mengqi

Re: [PATCH 2/2] dt-bingdings: mmc: Mediatek: add ICE clock

[Mengqi Zhang (张梦琦)]

On Wed, 2022-11-02 at 16:13 +0100, Ulf Hansson wrote:
> On Mon, 17 Oct 2022 at 16:20, Mengqi Zhang <mengqi.zhang@mediatek.com
> > wrote:
> > 
> > Document the binding for crypto clock of the Inline Crypto Engine
> > of Mediatek SoCs.
> > 
> > Signed-off-by: Mengqi Zhang <mengqi.zhang@mediatek.com>
> > ---
> >  Documentation/devicetree/bindings/mmc/mtk-sd.yaml | 2 ++
> >  1 file changed, 2 insertions(+)
> > 
> > diff --git a/Documentation/devicetree/bindings/mmc/mtk-sd.yaml
> > b/Documentation/devicetree/bindings/mmc/mtk-sd.yaml
> > index d8e1e2e9adf2..f93d686e2911 100644
> > --- a/Documentation/devicetree/bindings/mmc/mtk-sd.yaml
> > +++ b/Documentation/devicetree/bindings/mmc/mtk-sd.yaml
> > @@ -57,6 +57,7 @@ properties:
> >        - description: peripheral bus clock gate (required for
> > MT8192).
> >        - description: AXI bus clock gate (required for MT8192).
> >        - description: AHB bus clock gate (required for MT8192).
> > +      - description: crypto clock used for data encrypt/decrypt
> > (optional).
> > 
> >    clock-names:
> >      minItems: 2
> > @@ -69,6 +70,7 @@ properties:
> >        - const: pclk_cg
> >        - const: axi_cg
> >        - const: ahb_cg
> > +      - const: crypto
> 
> Looks like minItems/maxItems for clocks needs to be updated too.
> 
> > 
> >    interrupts:
> >      description:
> > --
> > 2.25.1
> > 
> 
> Kind regards
> Uffe

Hi Uffe,

I just add crypto clock to mt8186/mt8188/mt8195, does not exceed the
minItems/maxItems.

I have re-sent my patch,

https://lore.kernel.org/linux-mmc/20221106033924.9854-3-mengqi.zhang@mediatek.com/
Please help to review it.
Thanks!

Regards,
Mengqi
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linux-arm-kernel@lists.infradead.org
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