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From: Olliver Schinagl <oliver@schinagl.nl>
To: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Cc: Sander Vanheule <sander@svanheule.net>,
	linux-mips@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH] mips: Realtek RTL: select NO_EXCEPT_FILL
Date: Sun, 19 Feb 2023 17:07:34 +0100	[thread overview]
Message-ID: <8bc77a68-ec04-863e-0c46-1ea442e392ee@schinagl.nl> (raw)
In-Reply-To: <20230219103112.GA4095@alpha.franken.de>

Hey Thomas,

On 19-02-2023 11:31, Thomas Bogendoerfer wrote:
> On Sun, Feb 19, 2023 at 10:27:17AM +0100, Olliver Schinagl wrote:
>> It's still odd though; as we do not have _anything_ PCI, but it
>> SWAP_IO_SPACE causes the crash.
> 
> but something uses readX/write() calls. If you aren't using any driver
> existing driver but only newly written dedicated for that SOC
> you could use raw_read/raw_writeX() instead. These type of functions
> are always using native endianess.

Ok that is valueable information. I think currently the only driver 
(that I can think of right now) that we use 'off the shelf' is the uart 
driver, so I hope that's written cleanly :)

As for readX/writeX, for sure that is being used, and I intended to 
refactor that while going to proper and clean drivers (the realtek 
support in openwrt is a big mess right now).

So you say raw_readX, but what about ioread32 which I thought was preferred?

I'll meanwhile read into what readX vs raw_readX to learn more with 
regards to endianess.

Thank you so mcuh so far!

> 
>> What makes SWAP_IO_SPACE generic then? :)
> 
> als long as hardware presents memory used with readX/writeX is
> seen as little endian independant from CPU endianess it's generic.

'little endian independent'? What does that mean, that the register maps 
follow the CPU endianess?

> 
> Thomas.
> 

  reply	other threads:[~2023-02-19 16:07 UTC|newest]

Thread overview: 12+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-01-15 12:19 [PATCH] mips: Realtek RTL: select NO_EXCEPT_FILL Sander Vanheule
2023-01-27 16:27 ` Thomas Bogendoerfer
2023-01-28 14:39   ` Olliver Schinagl
2023-02-05 16:19     ` Thomas Bogendoerfer
2023-02-05 18:33       ` Olliver Schinagl
2023-02-17 17:37         ` Thomas Bogendoerfer
2023-02-17 19:27           ` Olliver Schinagl
2023-02-19  9:02             ` Thomas Bogendoerfer
2023-02-19  9:27               ` Olliver Schinagl
2023-02-19 10:31                 ` Thomas Bogendoerfer
2023-02-19 16:07                   ` Olliver Schinagl [this message]
2023-02-22 15:23                     ` Olliver Schinagl

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