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* [PATCH] drm/radeon: ERROR: that open brace { should be on the previous line
       [not found] <tencent_996261255FBE1BF185353D65C90BFB5FDF0A@qq.com>
@ 2023-07-14  3:54   ` shijie001
  0 siblings, 0 replies; 7+ messages in thread
From: shijie001 @ 2023-07-14  3:54 UTC (permalink / raw)
  To: alexander.deucher, christian.koenig, Xinhui.Pan, airlied, daniel
  Cc: amd-gfx, dri-devel, linux-kernel

Fix eight occurrences of the checkpatch.pl error:
ERROR: that open brace { should be on the previous line
ERROR: space prohibited before that close parenthesis ')'
ERROR: spaces required around that '?' (ctx:VxW)

Signed-off-by: Jie Shi <shijie001@208suo.com>
---
  drivers/gpu/drm/radeon/sumo_dpm.c | 18 ++++++++----------
  1 file changed, 8 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/radeon/sumo_dpm.c 
b/drivers/gpu/drm/radeon/sumo_dpm.c
index f74f381af05f..8af793c89fd1 100644
--- a/drivers/gpu/drm/radeon/sumo_dpm.c
+++ b/drivers/gpu/drm/radeon/sumo_dpm.c
@@ -33,8 +33,7 @@
  #define SUMO_MINIMUM_ENGINE_CLOCK 800
  #define BOOST_DPM_LEVEL 7

-static const u32 sumo_utc[SUMO_PM_NUMBER_OF_TC] =
-{
+static const u32 sumo_utc[SUMO_PM_NUMBER_OF_TC] = {
      SUMO_UTC_DFLT_00,
      SUMO_UTC_DFLT_01,
      SUMO_UTC_DFLT_02,
@@ -52,8 +51,7 @@ static const u32 sumo_utc[SUMO_PM_NUMBER_OF_TC] =
      SUMO_UTC_DFLT_14,
  };

-static const u32 sumo_dtc[SUMO_PM_NUMBER_OF_TC] =
-{
+static const u32 sumo_dtc[SUMO_PM_NUMBER_OF_TC] = {
      SUMO_DTC_DFLT_00,
      SUMO_DTC_DFLT_01,
      SUMO_DTC_DFLT_02,
@@ -109,11 +107,11 @@ static void sumo_mg_clockgating_enable(struct 
radeon_device *rdev, bool enable)
      local1 = RREG32(CG_CGTT_LOCAL_1);

      if (enable) {
-        WREG32(CG_CGTT_LOCAL_0, (0 & CGCG_CGTT_LOCAL0_MASK) | (local0 & 
~CGCG_CGTT_LOCAL0_MASK) );
-        WREG32(CG_CGTT_LOCAL_1, (0 & CGCG_CGTT_LOCAL1_MASK) | (local1 & 
~CGCG_CGTT_LOCAL1_MASK) );
+        WREG32(CG_CGTT_LOCAL_0, (0 & CGCG_CGTT_LOCAL0_MASK) | (local0 & 
~CGCG_CGTT_LOCAL0_MASK));
+        WREG32(CG_CGTT_LOCAL_1, (0 & CGCG_CGTT_LOCAL1_MASK) | (local1 & 
~CGCG_CGTT_LOCAL1_MASK));
      } else {
-        WREG32(CG_CGTT_LOCAL_0, (0xFFFFFFFF & CGCG_CGTT_LOCAL0_MASK) | 
(local0 & ~CGCG_CGTT_LOCAL0_MASK) );
-        WREG32(CG_CGTT_LOCAL_1, (0xFFFFCFFF & CGCG_CGTT_LOCAL1_MASK) | 
(local1 & ~CGCG_CGTT_LOCAL1_MASK) );
+        WREG32(CG_CGTT_LOCAL_0, (0xFFFFFFFF & CGCG_CGTT_LOCAL0_MASK) | 
(local0 & ~CGCG_CGTT_LOCAL0_MASK));
+        WREG32(CG_CGTT_LOCAL_1, (0xFFFFCFFF & CGCG_CGTT_LOCAL1_MASK) | 
(local1 & ~CGCG_CGTT_LOCAL1_MASK));
      }
  }

@@ -702,9 +700,9 @@ static void sumo_post_notify_alt_vddnb_change(struct 
radeon_device *rdev,
      u32 nbps1_new = 0;

      if (old_ps != NULL)
-        nbps1_old = (old_ps->flags & 
SUMO_POWERSTATE_FLAGS_FORCE_NBPS1_STATE)? 1 : 0;
+        nbps1_old = (old_ps->flags & 
SUMO_POWERSTATE_FLAGS_FORCE_NBPS1_STATE) ? 1 : 0;

-    nbps1_new = (new_ps->flags & 
SUMO_POWERSTATE_FLAGS_FORCE_NBPS1_STATE)? 1 : 0;
+    nbps1_new = (new_ps->flags & 
SUMO_POWERSTATE_FLAGS_FORCE_NBPS1_STATE) ? 1 : 0;

      if (nbps1_old == 0 && nbps1_new == 1)
          sumo_smu_notify_alt_vddnb_change(rdev, 1, 1);

^ permalink raw reply related	[flat|nested] 7+ messages in thread

* [PATCH] drm/radeon: ERROR: that open brace { should be on the previous line
@ 2023-07-14  3:54   ` shijie001
  0 siblings, 0 replies; 7+ messages in thread
From: shijie001 @ 2023-07-14  3:54 UTC (permalink / raw)
  To: alexander.deucher, christian.koenig, Xinhui.Pan, airlied, daniel
  Cc: dri-devel, amd-gfx, linux-kernel

Fix eight occurrences of the checkpatch.pl error:
ERROR: that open brace { should be on the previous line
ERROR: space prohibited before that close parenthesis ')'
ERROR: spaces required around that '?' (ctx:VxW)

Signed-off-by: Jie Shi <shijie001@208suo.com>
---
  drivers/gpu/drm/radeon/sumo_dpm.c | 18 ++++++++----------
  1 file changed, 8 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/radeon/sumo_dpm.c 
b/drivers/gpu/drm/radeon/sumo_dpm.c
index f74f381af05f..8af793c89fd1 100644
--- a/drivers/gpu/drm/radeon/sumo_dpm.c
+++ b/drivers/gpu/drm/radeon/sumo_dpm.c
@@ -33,8 +33,7 @@
  #define SUMO_MINIMUM_ENGINE_CLOCK 800
  #define BOOST_DPM_LEVEL 7

-static const u32 sumo_utc[SUMO_PM_NUMBER_OF_TC] =
-{
+static const u32 sumo_utc[SUMO_PM_NUMBER_OF_TC] = {
      SUMO_UTC_DFLT_00,
      SUMO_UTC_DFLT_01,
      SUMO_UTC_DFLT_02,
@@ -52,8 +51,7 @@ static const u32 sumo_utc[SUMO_PM_NUMBER_OF_TC] =
      SUMO_UTC_DFLT_14,
  };

-static const u32 sumo_dtc[SUMO_PM_NUMBER_OF_TC] =
-{
+static const u32 sumo_dtc[SUMO_PM_NUMBER_OF_TC] = {
      SUMO_DTC_DFLT_00,
      SUMO_DTC_DFLT_01,
      SUMO_DTC_DFLT_02,
@@ -109,11 +107,11 @@ static void sumo_mg_clockgating_enable(struct 
radeon_device *rdev, bool enable)
      local1 = RREG32(CG_CGTT_LOCAL_1);

      if (enable) {
-        WREG32(CG_CGTT_LOCAL_0, (0 & CGCG_CGTT_LOCAL0_MASK) | (local0 & 
~CGCG_CGTT_LOCAL0_MASK) );
-        WREG32(CG_CGTT_LOCAL_1, (0 & CGCG_CGTT_LOCAL1_MASK) | (local1 & 
~CGCG_CGTT_LOCAL1_MASK) );
+        WREG32(CG_CGTT_LOCAL_0, (0 & CGCG_CGTT_LOCAL0_MASK) | (local0 & 
~CGCG_CGTT_LOCAL0_MASK));
+        WREG32(CG_CGTT_LOCAL_1, (0 & CGCG_CGTT_LOCAL1_MASK) | (local1 & 
~CGCG_CGTT_LOCAL1_MASK));
      } else {
-        WREG32(CG_CGTT_LOCAL_0, (0xFFFFFFFF & CGCG_CGTT_LOCAL0_MASK) | 
(local0 & ~CGCG_CGTT_LOCAL0_MASK) );
-        WREG32(CG_CGTT_LOCAL_1, (0xFFFFCFFF & CGCG_CGTT_LOCAL1_MASK) | 
(local1 & ~CGCG_CGTT_LOCAL1_MASK) );
+        WREG32(CG_CGTT_LOCAL_0, (0xFFFFFFFF & CGCG_CGTT_LOCAL0_MASK) | 
(local0 & ~CGCG_CGTT_LOCAL0_MASK));
+        WREG32(CG_CGTT_LOCAL_1, (0xFFFFCFFF & CGCG_CGTT_LOCAL1_MASK) | 
(local1 & ~CGCG_CGTT_LOCAL1_MASK));
      }
  }

@@ -702,9 +700,9 @@ static void sumo_post_notify_alt_vddnb_change(struct 
radeon_device *rdev,
      u32 nbps1_new = 0;

      if (old_ps != NULL)
-        nbps1_old = (old_ps->flags & 
SUMO_POWERSTATE_FLAGS_FORCE_NBPS1_STATE)? 1 : 0;
+        nbps1_old = (old_ps->flags & 
SUMO_POWERSTATE_FLAGS_FORCE_NBPS1_STATE) ? 1 : 0;

-    nbps1_new = (new_ps->flags & 
SUMO_POWERSTATE_FLAGS_FORCE_NBPS1_STATE)? 1 : 0;
+    nbps1_new = (new_ps->flags & 
SUMO_POWERSTATE_FLAGS_FORCE_NBPS1_STATE) ? 1 : 0;

      if (nbps1_old == 0 && nbps1_new == 1)
          sumo_smu_notify_alt_vddnb_change(rdev, 1, 1);

^ permalink raw reply related	[flat|nested] 7+ messages in thread

* Re: [PATCH] drm/radeon: ERROR: that open brace { should be on the previous line
  2023-07-10  9:05   ` sunran001
  (?)
@ 2023-07-10 17:28     ` Alex Deucher
  -1 siblings, 0 replies; 7+ messages in thread
From: Alex Deucher @ 2023-07-10 17:28 UTC (permalink / raw)
  To: sunran001; +Cc: airlied, daniel, dri-devel, amd-gfx, linux-kernel

Applied.  Thanks!

On Mon, Jul 10, 2023 at 5:06 AM <sunran001@208suo.com> wrote:
>
> Fix eleven occurrences of the checkpatch.pl error:
> ERROR: that open brace { should be on the previous line
>
> Signed-off-by: Ran Sun <sunran001@208suo.com>
> ---
>   drivers/gpu/drm/radeon/rv770.c | 22 +++++++++++-----------
>   1 file changed, 11 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/gpu/drm/radeon/rv770.c
> b/drivers/gpu/drm/radeon/rv770.c
> index a5ce59d4a485..9ce12fa3c356 100644
> --- a/drivers/gpu/drm/radeon/rv770.c
> +++ b/drivers/gpu/drm/radeon/rv770.c
> @@ -136,7 +136,7 @@ int rv770_set_uvd_clocks(struct radeon_device *rdev,
> u32 vclk, u32 dclk)
>       return 0;
>   }
>
> -static const u32 r7xx_golden_registers[] ={
> +static const u32 r7xx_golden_registers[] = {
>       0x8d00, 0xffffffff, 0x0e0e0074,
>       0x8d04, 0xffffffff, 0x013a2b34,
>       0x9508, 0xffffffff, 0x00000002,
> @@ -151,7 +151,7 @@ static const u32 r7xx_golden_registers[] ={
>       0x7300, 0xffffffff, 0x001000f0
>   };
>
> -static const u32 r7xx_golden_dyn_gpr_registers[] ={
> +static const u32 r7xx_golden_dyn_gpr_registers[] = {
>       0x8db0, 0xffffffff, 0x98989898,
>       0x8db4, 0xffffffff, 0x98989898,
>       0x8db8, 0xffffffff, 0x98989898,
> @@ -163,7 +163,7 @@ static const u32 r7xx_golden_dyn_gpr_registers[] ={
>       0x88c4, 0xffffffff, 0x00000082
>   };
>
> -static const u32 rv770_golden_registers[] ={
> +static const u32 rv770_golden_registers[] = {
>       0x562c, 0xffffffff, 0,
>       0x3f90, 0xffffffff, 0,
>       0x9148, 0xffffffff, 0,
> @@ -172,7 +172,7 @@ static const u32 rv770_golden_registers[] ={
>       0x9698, 0x18000000, 0x18000000
>   };
>
> -static const u32 rv770ce_golden_registers[] ={
> +static const u32 rv770ce_golden_registers[] = {
>       0x562c, 0xffffffff, 0,
>       0x3f90, 0xffffffff, 0x00cc0000,
>       0x9148, 0xffffffff, 0x00cc0000,
> @@ -183,7 +183,7 @@ static const u32 rv770ce_golden_registers[] ={
>       0x9698, 0x18000000, 0x18000000
>   };
>
> -static const u32 rv770_mgcg_init[] ={
> +static const u32 rv770_mgcg_init[] = {
>       0x8bcc, 0xffffffff, 0x130300f9,
>       0x5448, 0xffffffff, 0x100,
>       0x55e4, 0xffffffff, 0x100,
> @@ -340,7 +340,7 @@ static const u32 rv770_mgcg_init[] ={
>       0x92a4, 0xffffffff, 0x00080007
>   };
>
> -static const u32 rv710_golden_registers[] ={
> +static const u32 rv710_golden_registers[] = {
>       0x3f90, 0x00ff0000, 0x00fc0000,
>       0x9148, 0x00ff0000, 0x00fc0000,
>       0x3f94, 0x00ff0000, 0x00fc0000,
> @@ -349,7 +349,7 @@ static const u32 rv710_golden_registers[] ={
>       0xa180, 0xffffffff, 0x00003f3f
>   };
>
> -static const u32 rv710_mgcg_init[] ={
> +static const u32 rv710_mgcg_init[] = {
>       0x8bcc, 0xffffffff, 0x13030040,
>       0x5448, 0xffffffff, 0x100,
>       0x55e4, 0xffffffff, 0x100,
> @@ -407,7 +407,7 @@ static const u32 rv710_mgcg_init[] ={
>       0x9150, 0xffffffff, 0x4d940000
>   };
>
> -static const u32 rv730_golden_registers[] ={
> +static const u32 rv730_golden_registers[] = {
>       0x3f90, 0x00ff0000, 0x00f00000,
>       0x9148, 0x00ff0000, 0x00f00000,
>       0x3f94, 0x00ff0000, 0x00f00000,
> @@ -417,7 +417,7 @@ static const u32 rv730_golden_registers[] ={
>       0xa180, 0xffffffff, 0x00003f3f
>   };
>
> -static const u32 rv730_mgcg_init[] ={
> +static const u32 rv730_mgcg_init[] = {
>       0x8bcc, 0xffffffff, 0x130300f9,
>       0x5448, 0xffffffff, 0x100,
>       0x55e4, 0xffffffff, 0x100,
> @@ -538,7 +538,7 @@ static const u32 rv730_mgcg_init[] ={
>       0x92a4, 0xffffffff, 0x00000005
>   };
>
> -static const u32 rv740_golden_registers[] ={
> +static const u32 rv740_golden_registers[] = {
>       0x88c4, 0xffffffff, 0x00000082,
>       0x28a50, 0xfffffffc, 0x00000004,
>       0x2650, 0x00040000, 0,
> @@ -574,7 +574,7 @@ static const u32 rv740_golden_registers[] ={
>       0x9698, 0x18000000, 0x18000000
>   };
>
> -static const u32 rv740_mgcg_init[] ={
> +static const u32 rv740_mgcg_init[] = {
>       0x8bcc, 0xffffffff, 0x13030100,
>       0x5448, 0xffffffff, 0x100,
>       0x55e4, 0xffffffff, 0x100,

^ permalink raw reply	[flat|nested] 7+ messages in thread

* Re: [PATCH] drm/radeon: ERROR: that open brace { should be on the previous line
@ 2023-07-10 17:28     ` Alex Deucher
  0 siblings, 0 replies; 7+ messages in thread
From: Alex Deucher @ 2023-07-10 17:28 UTC (permalink / raw)
  To: sunran001; +Cc: amd-gfx, dri-devel, linux-kernel

Applied.  Thanks!

On Mon, Jul 10, 2023 at 5:06 AM <sunran001@208suo.com> wrote:
>
> Fix eleven occurrences of the checkpatch.pl error:
> ERROR: that open brace { should be on the previous line
>
> Signed-off-by: Ran Sun <sunran001@208suo.com>
> ---
>   drivers/gpu/drm/radeon/rv770.c | 22 +++++++++++-----------
>   1 file changed, 11 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/gpu/drm/radeon/rv770.c
> b/drivers/gpu/drm/radeon/rv770.c
> index a5ce59d4a485..9ce12fa3c356 100644
> --- a/drivers/gpu/drm/radeon/rv770.c
> +++ b/drivers/gpu/drm/radeon/rv770.c
> @@ -136,7 +136,7 @@ int rv770_set_uvd_clocks(struct radeon_device *rdev,
> u32 vclk, u32 dclk)
>       return 0;
>   }
>
> -static const u32 r7xx_golden_registers[] ={
> +static const u32 r7xx_golden_registers[] = {
>       0x8d00, 0xffffffff, 0x0e0e0074,
>       0x8d04, 0xffffffff, 0x013a2b34,
>       0x9508, 0xffffffff, 0x00000002,
> @@ -151,7 +151,7 @@ static const u32 r7xx_golden_registers[] ={
>       0x7300, 0xffffffff, 0x001000f0
>   };
>
> -static const u32 r7xx_golden_dyn_gpr_registers[] ={
> +static const u32 r7xx_golden_dyn_gpr_registers[] = {
>       0x8db0, 0xffffffff, 0x98989898,
>       0x8db4, 0xffffffff, 0x98989898,
>       0x8db8, 0xffffffff, 0x98989898,
> @@ -163,7 +163,7 @@ static const u32 r7xx_golden_dyn_gpr_registers[] ={
>       0x88c4, 0xffffffff, 0x00000082
>   };
>
> -static const u32 rv770_golden_registers[] ={
> +static const u32 rv770_golden_registers[] = {
>       0x562c, 0xffffffff, 0,
>       0x3f90, 0xffffffff, 0,
>       0x9148, 0xffffffff, 0,
> @@ -172,7 +172,7 @@ static const u32 rv770_golden_registers[] ={
>       0x9698, 0x18000000, 0x18000000
>   };
>
> -static const u32 rv770ce_golden_registers[] ={
> +static const u32 rv770ce_golden_registers[] = {
>       0x562c, 0xffffffff, 0,
>       0x3f90, 0xffffffff, 0x00cc0000,
>       0x9148, 0xffffffff, 0x00cc0000,
> @@ -183,7 +183,7 @@ static const u32 rv770ce_golden_registers[] ={
>       0x9698, 0x18000000, 0x18000000
>   };
>
> -static const u32 rv770_mgcg_init[] ={
> +static const u32 rv770_mgcg_init[] = {
>       0x8bcc, 0xffffffff, 0x130300f9,
>       0x5448, 0xffffffff, 0x100,
>       0x55e4, 0xffffffff, 0x100,
> @@ -340,7 +340,7 @@ static const u32 rv770_mgcg_init[] ={
>       0x92a4, 0xffffffff, 0x00080007
>   };
>
> -static const u32 rv710_golden_registers[] ={
> +static const u32 rv710_golden_registers[] = {
>       0x3f90, 0x00ff0000, 0x00fc0000,
>       0x9148, 0x00ff0000, 0x00fc0000,
>       0x3f94, 0x00ff0000, 0x00fc0000,
> @@ -349,7 +349,7 @@ static const u32 rv710_golden_registers[] ={
>       0xa180, 0xffffffff, 0x00003f3f
>   };
>
> -static const u32 rv710_mgcg_init[] ={
> +static const u32 rv710_mgcg_init[] = {
>       0x8bcc, 0xffffffff, 0x13030040,
>       0x5448, 0xffffffff, 0x100,
>       0x55e4, 0xffffffff, 0x100,
> @@ -407,7 +407,7 @@ static const u32 rv710_mgcg_init[] ={
>       0x9150, 0xffffffff, 0x4d940000
>   };
>
> -static const u32 rv730_golden_registers[] ={
> +static const u32 rv730_golden_registers[] = {
>       0x3f90, 0x00ff0000, 0x00f00000,
>       0x9148, 0x00ff0000, 0x00f00000,
>       0x3f94, 0x00ff0000, 0x00f00000,
> @@ -417,7 +417,7 @@ static const u32 rv730_golden_registers[] ={
>       0xa180, 0xffffffff, 0x00003f3f
>   };
>
> -static const u32 rv730_mgcg_init[] ={
> +static const u32 rv730_mgcg_init[] = {
>       0x8bcc, 0xffffffff, 0x130300f9,
>       0x5448, 0xffffffff, 0x100,
>       0x55e4, 0xffffffff, 0x100,
> @@ -538,7 +538,7 @@ static const u32 rv730_mgcg_init[] ={
>       0x92a4, 0xffffffff, 0x00000005
>   };
>
> -static const u32 rv740_golden_registers[] ={
> +static const u32 rv740_golden_registers[] = {
>       0x88c4, 0xffffffff, 0x00000082,
>       0x28a50, 0xfffffffc, 0x00000004,
>       0x2650, 0x00040000, 0,
> @@ -574,7 +574,7 @@ static const u32 rv740_golden_registers[] ={
>       0x9698, 0x18000000, 0x18000000
>   };
>
> -static const u32 rv740_mgcg_init[] ={
> +static const u32 rv740_mgcg_init[] = {
>       0x8bcc, 0xffffffff, 0x13030100,
>       0x5448, 0xffffffff, 0x100,
>       0x55e4, 0xffffffff, 0x100,

^ permalink raw reply	[flat|nested] 7+ messages in thread

* Re: [PATCH] drm/radeon: ERROR: that open brace { should be on the previous line
@ 2023-07-10 17:28     ` Alex Deucher
  0 siblings, 0 replies; 7+ messages in thread
From: Alex Deucher @ 2023-07-10 17:28 UTC (permalink / raw)
  To: sunran001; +Cc: amd-gfx, airlied, dri-devel, daniel, linux-kernel

Applied.  Thanks!

On Mon, Jul 10, 2023 at 5:06 AM <sunran001@208suo.com> wrote:
>
> Fix eleven occurrences of the checkpatch.pl error:
> ERROR: that open brace { should be on the previous line
>
> Signed-off-by: Ran Sun <sunran001@208suo.com>
> ---
>   drivers/gpu/drm/radeon/rv770.c | 22 +++++++++++-----------
>   1 file changed, 11 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/gpu/drm/radeon/rv770.c
> b/drivers/gpu/drm/radeon/rv770.c
> index a5ce59d4a485..9ce12fa3c356 100644
> --- a/drivers/gpu/drm/radeon/rv770.c
> +++ b/drivers/gpu/drm/radeon/rv770.c
> @@ -136,7 +136,7 @@ int rv770_set_uvd_clocks(struct radeon_device *rdev,
> u32 vclk, u32 dclk)
>       return 0;
>   }
>
> -static const u32 r7xx_golden_registers[] ={
> +static const u32 r7xx_golden_registers[] = {
>       0x8d00, 0xffffffff, 0x0e0e0074,
>       0x8d04, 0xffffffff, 0x013a2b34,
>       0x9508, 0xffffffff, 0x00000002,
> @@ -151,7 +151,7 @@ static const u32 r7xx_golden_registers[] ={
>       0x7300, 0xffffffff, 0x001000f0
>   };
>
> -static const u32 r7xx_golden_dyn_gpr_registers[] ={
> +static const u32 r7xx_golden_dyn_gpr_registers[] = {
>       0x8db0, 0xffffffff, 0x98989898,
>       0x8db4, 0xffffffff, 0x98989898,
>       0x8db8, 0xffffffff, 0x98989898,
> @@ -163,7 +163,7 @@ static const u32 r7xx_golden_dyn_gpr_registers[] ={
>       0x88c4, 0xffffffff, 0x00000082
>   };
>
> -static const u32 rv770_golden_registers[] ={
> +static const u32 rv770_golden_registers[] = {
>       0x562c, 0xffffffff, 0,
>       0x3f90, 0xffffffff, 0,
>       0x9148, 0xffffffff, 0,
> @@ -172,7 +172,7 @@ static const u32 rv770_golden_registers[] ={
>       0x9698, 0x18000000, 0x18000000
>   };
>
> -static const u32 rv770ce_golden_registers[] ={
> +static const u32 rv770ce_golden_registers[] = {
>       0x562c, 0xffffffff, 0,
>       0x3f90, 0xffffffff, 0x00cc0000,
>       0x9148, 0xffffffff, 0x00cc0000,
> @@ -183,7 +183,7 @@ static const u32 rv770ce_golden_registers[] ={
>       0x9698, 0x18000000, 0x18000000
>   };
>
> -static const u32 rv770_mgcg_init[] ={
> +static const u32 rv770_mgcg_init[] = {
>       0x8bcc, 0xffffffff, 0x130300f9,
>       0x5448, 0xffffffff, 0x100,
>       0x55e4, 0xffffffff, 0x100,
> @@ -340,7 +340,7 @@ static const u32 rv770_mgcg_init[] ={
>       0x92a4, 0xffffffff, 0x00080007
>   };
>
> -static const u32 rv710_golden_registers[] ={
> +static const u32 rv710_golden_registers[] = {
>       0x3f90, 0x00ff0000, 0x00fc0000,
>       0x9148, 0x00ff0000, 0x00fc0000,
>       0x3f94, 0x00ff0000, 0x00fc0000,
> @@ -349,7 +349,7 @@ static const u32 rv710_golden_registers[] ={
>       0xa180, 0xffffffff, 0x00003f3f
>   };
>
> -static const u32 rv710_mgcg_init[] ={
> +static const u32 rv710_mgcg_init[] = {
>       0x8bcc, 0xffffffff, 0x13030040,
>       0x5448, 0xffffffff, 0x100,
>       0x55e4, 0xffffffff, 0x100,
> @@ -407,7 +407,7 @@ static const u32 rv710_mgcg_init[] ={
>       0x9150, 0xffffffff, 0x4d940000
>   };
>
> -static const u32 rv730_golden_registers[] ={
> +static const u32 rv730_golden_registers[] = {
>       0x3f90, 0x00ff0000, 0x00f00000,
>       0x9148, 0x00ff0000, 0x00f00000,
>       0x3f94, 0x00ff0000, 0x00f00000,
> @@ -417,7 +417,7 @@ static const u32 rv730_golden_registers[] ={
>       0xa180, 0xffffffff, 0x00003f3f
>   };
>
> -static const u32 rv730_mgcg_init[] ={
> +static const u32 rv730_mgcg_init[] = {
>       0x8bcc, 0xffffffff, 0x130300f9,
>       0x5448, 0xffffffff, 0x100,
>       0x55e4, 0xffffffff, 0x100,
> @@ -538,7 +538,7 @@ static const u32 rv730_mgcg_init[] ={
>       0x92a4, 0xffffffff, 0x00000005
>   };
>
> -static const u32 rv740_golden_registers[] ={
> +static const u32 rv740_golden_registers[] = {
>       0x88c4, 0xffffffff, 0x00000082,
>       0x28a50, 0xfffffffc, 0x00000004,
>       0x2650, 0x00040000, 0,
> @@ -574,7 +574,7 @@ static const u32 rv740_golden_registers[] ={
>       0x9698, 0x18000000, 0x18000000
>   };
>
> -static const u32 rv740_mgcg_init[] ={
> +static const u32 rv740_mgcg_init[] = {
>       0x8bcc, 0xffffffff, 0x13030100,
>       0x5448, 0xffffffff, 0x100,
>       0x55e4, 0xffffffff, 0x100,

^ permalink raw reply	[flat|nested] 7+ messages in thread

* [PATCH] drm/radeon: ERROR: that open brace { should be on the previous line
       [not found] <20230710090421.61623-1-xujianghui@cdjrlc.com>
@ 2023-07-10  9:05   ` sunran001
  0 siblings, 0 replies; 7+ messages in thread
From: sunran001 @ 2023-07-10  9:05 UTC (permalink / raw)
  To: airlied, daniel; +Cc: amd-gfx, dri-devel, linux-kernel

Fix eleven occurrences of the checkpatch.pl error:
ERROR: that open brace { should be on the previous line

Signed-off-by: Ran Sun <sunran001@208suo.com>
---
  drivers/gpu/drm/radeon/rv770.c | 22 +++++++++++-----------
  1 file changed, 11 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/radeon/rv770.c 
b/drivers/gpu/drm/radeon/rv770.c
index a5ce59d4a485..9ce12fa3c356 100644
--- a/drivers/gpu/drm/radeon/rv770.c
+++ b/drivers/gpu/drm/radeon/rv770.c
@@ -136,7 +136,7 @@ int rv770_set_uvd_clocks(struct radeon_device *rdev, 
u32 vclk, u32 dclk)
      return 0;
  }

-static const u32 r7xx_golden_registers[] ={
+static const u32 r7xx_golden_registers[] = {
      0x8d00, 0xffffffff, 0x0e0e0074,
      0x8d04, 0xffffffff, 0x013a2b34,
      0x9508, 0xffffffff, 0x00000002,
@@ -151,7 +151,7 @@ static const u32 r7xx_golden_registers[] ={
      0x7300, 0xffffffff, 0x001000f0
  };

-static const u32 r7xx_golden_dyn_gpr_registers[] ={
+static const u32 r7xx_golden_dyn_gpr_registers[] = {
      0x8db0, 0xffffffff, 0x98989898,
      0x8db4, 0xffffffff, 0x98989898,
      0x8db8, 0xffffffff, 0x98989898,
@@ -163,7 +163,7 @@ static const u32 r7xx_golden_dyn_gpr_registers[] ={
      0x88c4, 0xffffffff, 0x00000082
  };

-static const u32 rv770_golden_registers[] ={
+static const u32 rv770_golden_registers[] = {
      0x562c, 0xffffffff, 0,
      0x3f90, 0xffffffff, 0,
      0x9148, 0xffffffff, 0,
@@ -172,7 +172,7 @@ static const u32 rv770_golden_registers[] ={
      0x9698, 0x18000000, 0x18000000
  };

-static const u32 rv770ce_golden_registers[] ={
+static const u32 rv770ce_golden_registers[] = {
      0x562c, 0xffffffff, 0,
      0x3f90, 0xffffffff, 0x00cc0000,
      0x9148, 0xffffffff, 0x00cc0000,
@@ -183,7 +183,7 @@ static const u32 rv770ce_golden_registers[] ={
      0x9698, 0x18000000, 0x18000000
  };

-static const u32 rv770_mgcg_init[] ={
+static const u32 rv770_mgcg_init[] = {
      0x8bcc, 0xffffffff, 0x130300f9,
      0x5448, 0xffffffff, 0x100,
      0x55e4, 0xffffffff, 0x100,
@@ -340,7 +340,7 @@ static const u32 rv770_mgcg_init[] ={
      0x92a4, 0xffffffff, 0x00080007
  };

-static const u32 rv710_golden_registers[] ={
+static const u32 rv710_golden_registers[] = {
      0x3f90, 0x00ff0000, 0x00fc0000,
      0x9148, 0x00ff0000, 0x00fc0000,
      0x3f94, 0x00ff0000, 0x00fc0000,
@@ -349,7 +349,7 @@ static const u32 rv710_golden_registers[] ={
      0xa180, 0xffffffff, 0x00003f3f
  };

-static const u32 rv710_mgcg_init[] ={
+static const u32 rv710_mgcg_init[] = {
      0x8bcc, 0xffffffff, 0x13030040,
      0x5448, 0xffffffff, 0x100,
      0x55e4, 0xffffffff, 0x100,
@@ -407,7 +407,7 @@ static const u32 rv710_mgcg_init[] ={
      0x9150, 0xffffffff, 0x4d940000
  };

-static const u32 rv730_golden_registers[] ={
+static const u32 rv730_golden_registers[] = {
      0x3f90, 0x00ff0000, 0x00f00000,
      0x9148, 0x00ff0000, 0x00f00000,
      0x3f94, 0x00ff0000, 0x00f00000,
@@ -417,7 +417,7 @@ static const u32 rv730_golden_registers[] ={
      0xa180, 0xffffffff, 0x00003f3f
  };

-static const u32 rv730_mgcg_init[] ={
+static const u32 rv730_mgcg_init[] = {
      0x8bcc, 0xffffffff, 0x130300f9,
      0x5448, 0xffffffff, 0x100,
      0x55e4, 0xffffffff, 0x100,
@@ -538,7 +538,7 @@ static const u32 rv730_mgcg_init[] ={
      0x92a4, 0xffffffff, 0x00000005
  };

-static const u32 rv740_golden_registers[] ={
+static const u32 rv740_golden_registers[] = {
      0x88c4, 0xffffffff, 0x00000082,
      0x28a50, 0xfffffffc, 0x00000004,
      0x2650, 0x00040000, 0,
@@ -574,7 +574,7 @@ static const u32 rv740_golden_registers[] ={
      0x9698, 0x18000000, 0x18000000
  };

-static const u32 rv740_mgcg_init[] ={
+static const u32 rv740_mgcg_init[] = {
      0x8bcc, 0xffffffff, 0x13030100,
      0x5448, 0xffffffff, 0x100,
      0x55e4, 0xffffffff, 0x100,

^ permalink raw reply related	[flat|nested] 7+ messages in thread

* [PATCH] drm/radeon: ERROR: that open brace { should be on the previous line
@ 2023-07-10  9:05   ` sunran001
  0 siblings, 0 replies; 7+ messages in thread
From: sunran001 @ 2023-07-10  9:05 UTC (permalink / raw)
  To: airlied, daniel; +Cc: dri-devel, amd-gfx, linux-kernel

Fix eleven occurrences of the checkpatch.pl error:
ERROR: that open brace { should be on the previous line

Signed-off-by: Ran Sun <sunran001@208suo.com>
---
  drivers/gpu/drm/radeon/rv770.c | 22 +++++++++++-----------
  1 file changed, 11 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/radeon/rv770.c 
b/drivers/gpu/drm/radeon/rv770.c
index a5ce59d4a485..9ce12fa3c356 100644
--- a/drivers/gpu/drm/radeon/rv770.c
+++ b/drivers/gpu/drm/radeon/rv770.c
@@ -136,7 +136,7 @@ int rv770_set_uvd_clocks(struct radeon_device *rdev, 
u32 vclk, u32 dclk)
      return 0;
  }

-static const u32 r7xx_golden_registers[] ={
+static const u32 r7xx_golden_registers[] = {
      0x8d00, 0xffffffff, 0x0e0e0074,
      0x8d04, 0xffffffff, 0x013a2b34,
      0x9508, 0xffffffff, 0x00000002,
@@ -151,7 +151,7 @@ static const u32 r7xx_golden_registers[] ={
      0x7300, 0xffffffff, 0x001000f0
  };

-static const u32 r7xx_golden_dyn_gpr_registers[] ={
+static const u32 r7xx_golden_dyn_gpr_registers[] = {
      0x8db0, 0xffffffff, 0x98989898,
      0x8db4, 0xffffffff, 0x98989898,
      0x8db8, 0xffffffff, 0x98989898,
@@ -163,7 +163,7 @@ static const u32 r7xx_golden_dyn_gpr_registers[] ={
      0x88c4, 0xffffffff, 0x00000082
  };

-static const u32 rv770_golden_registers[] ={
+static const u32 rv770_golden_registers[] = {
      0x562c, 0xffffffff, 0,
      0x3f90, 0xffffffff, 0,
      0x9148, 0xffffffff, 0,
@@ -172,7 +172,7 @@ static const u32 rv770_golden_registers[] ={
      0x9698, 0x18000000, 0x18000000
  };

-static const u32 rv770ce_golden_registers[] ={
+static const u32 rv770ce_golden_registers[] = {
      0x562c, 0xffffffff, 0,
      0x3f90, 0xffffffff, 0x00cc0000,
      0x9148, 0xffffffff, 0x00cc0000,
@@ -183,7 +183,7 @@ static const u32 rv770ce_golden_registers[] ={
      0x9698, 0x18000000, 0x18000000
  };

-static const u32 rv770_mgcg_init[] ={
+static const u32 rv770_mgcg_init[] = {
      0x8bcc, 0xffffffff, 0x130300f9,
      0x5448, 0xffffffff, 0x100,
      0x55e4, 0xffffffff, 0x100,
@@ -340,7 +340,7 @@ static const u32 rv770_mgcg_init[] ={
      0x92a4, 0xffffffff, 0x00080007
  };

-static const u32 rv710_golden_registers[] ={
+static const u32 rv710_golden_registers[] = {
      0x3f90, 0x00ff0000, 0x00fc0000,
      0x9148, 0x00ff0000, 0x00fc0000,
      0x3f94, 0x00ff0000, 0x00fc0000,
@@ -349,7 +349,7 @@ static const u32 rv710_golden_registers[] ={
      0xa180, 0xffffffff, 0x00003f3f
  };

-static const u32 rv710_mgcg_init[] ={
+static const u32 rv710_mgcg_init[] = {
      0x8bcc, 0xffffffff, 0x13030040,
      0x5448, 0xffffffff, 0x100,
      0x55e4, 0xffffffff, 0x100,
@@ -407,7 +407,7 @@ static const u32 rv710_mgcg_init[] ={
      0x9150, 0xffffffff, 0x4d940000
  };

-static const u32 rv730_golden_registers[] ={
+static const u32 rv730_golden_registers[] = {
      0x3f90, 0x00ff0000, 0x00f00000,
      0x9148, 0x00ff0000, 0x00f00000,
      0x3f94, 0x00ff0000, 0x00f00000,
@@ -417,7 +417,7 @@ static const u32 rv730_golden_registers[] ={
      0xa180, 0xffffffff, 0x00003f3f
  };

-static const u32 rv730_mgcg_init[] ={
+static const u32 rv730_mgcg_init[] = {
      0x8bcc, 0xffffffff, 0x130300f9,
      0x5448, 0xffffffff, 0x100,
      0x55e4, 0xffffffff, 0x100,
@@ -538,7 +538,7 @@ static const u32 rv730_mgcg_init[] ={
      0x92a4, 0xffffffff, 0x00000005
  };

-static const u32 rv740_golden_registers[] ={
+static const u32 rv740_golden_registers[] = {
      0x88c4, 0xffffffff, 0x00000082,
      0x28a50, 0xfffffffc, 0x00000004,
      0x2650, 0x00040000, 0,
@@ -574,7 +574,7 @@ static const u32 rv740_golden_registers[] ={
      0x9698, 0x18000000, 0x18000000
  };

-static const u32 rv740_mgcg_init[] ={
+static const u32 rv740_mgcg_init[] = {
      0x8bcc, 0xffffffff, 0x13030100,
      0x5448, 0xffffffff, 0x100,
      0x55e4, 0xffffffff, 0x100,

^ permalink raw reply related	[flat|nested] 7+ messages in thread

end of thread, other threads:[~2023-07-14  7:15 UTC | newest]

Thread overview: 7+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
     [not found] <tencent_996261255FBE1BF185353D65C90BFB5FDF0A@qq.com>
2023-07-14  3:54 ` [PATCH] drm/radeon: ERROR: that open brace { should be on the previous line shijie001
2023-07-14  3:54   ` shijie001
     [not found] <20230710090421.61623-1-xujianghui@cdjrlc.com>
2023-07-10  9:05 ` sunran001
2023-07-10  9:05   ` sunran001
2023-07-10 17:28   ` Alex Deucher
2023-07-10 17:28     ` Alex Deucher
2023-07-10 17:28     ` Alex Deucher

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