[U-Boot] [PATCH V3 1/5] mmc: uniphier-sd: Factor out register IO

[U-Boot] [PATCH V3 1/5] mmc: uniphier-sd: Factor out register IO

[Marek Vasut]

This patch prepares the driver to support controller(s) with registers
at locations shifted by constant. Pull out the readl()/writel() from
the driver into separate functions, where the adjustment of the register
offset can be easily contained.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
---
V2: Use unsigned int for the reg argument
V3: Remove const ...
---
 drivers/mmc/uniphier-sd.c | 115 +++++++++++++++++++++++++---------------------
 1 file changed, 63 insertions(+), 52 deletions(-)

diff --git a/drivers/mmc/uniphier-sd.c b/drivers/mmc/uniphier-sd.c
index e272b14153..cb53b28737 100644
--- a/drivers/mmc/uniphier-sd.c
+++ b/drivers/mmc/uniphier-sd.c
@@ -134,6 +134,17 @@ struct uniphier_sd_priv {
 #define UNIPHIER_SD_CAP_DIV1024		BIT(2)	/* divisor 1024 is available */
 };
 
+static u32 uniphier_sd_readl(struct uniphier_sd_priv *priv, unsigned int reg)
+{
+	return readl(priv->regbase + reg);
+}
+
+static void uniphier_sd_writel(struct uniphier_sd_priv *priv,
+			       u32 val, unsigned int reg)
+{
+	writel(val, priv->regbase + reg);
+}
+
 static dma_addr_t __dma_map_single(void *ptr, size_t size,
 				   enum dma_data_direction dir)
 {
@@ -157,7 +168,7 @@ static void __dma_unmap_single(dma_addr_t addr, size_t size,
 static int uniphier_sd_check_error(struct udevice *dev)
 {
 	struct uniphier_sd_priv *priv = dev_get_priv(dev);
-	u32 info2 = readl(priv->regbase + UNIPHIER_SD_INFO2);
+	u32 info2 = uniphier_sd_readl(priv, UNIPHIER_SD_INFO2);
 
 	if (info2 & UNIPHIER_SD_INFO2_ERR_RTO) {
 		/*
@@ -195,7 +206,7 @@ static int uniphier_sd_wait_for_irq(struct udevice *dev, unsigned int reg,
 	long wait = 1000000;
 	int ret;
 
-	while (!(readl(priv->regbase + reg) & flag)) {
+	while (!(uniphier_sd_readl(priv, reg) & flag)) {
 		if (wait-- < 0) {
 			dev_err(dev, "timeout\n");
 			return -ETIMEDOUT;
@@ -227,14 +238,14 @@ static int uniphier_sd_pio_read_one_block(struct udevice *dev, u32 **pbuf,
 	 * Clear the status flag _before_ read the buffer out because
 	 * UNIPHIER_SD_INFO2_BRE is edge-triggered, not level-triggered.
 	 */
-	writel(0, priv->regbase + UNIPHIER_SD_INFO2);
+	uniphier_sd_writel(priv, 0, UNIPHIER_SD_INFO2);
 
 	if (likely(IS_ALIGNED((unsigned long)*pbuf, 4))) {
 		for (i = 0; i < blocksize / 4; i++)
-			*(*pbuf)++ = readl(priv->regbase + UNIPHIER_SD_BUF);
+			*(*pbuf)++ = uniphier_sd_readl(priv, UNIPHIER_SD_BUF);
 	} else {
 		for (i = 0; i < blocksize / 4; i++)
-			put_unaligned(readl(priv->regbase + UNIPHIER_SD_BUF),
+			put_unaligned(uniphier_sd_readl(priv, UNIPHIER_SD_BUF),
 				      (*pbuf)++);
 	}
 
@@ -253,15 +264,15 @@ static int uniphier_sd_pio_write_one_block(struct udevice *dev,
 	if (ret)
 		return ret;
 
-	writel(0, priv->regbase + UNIPHIER_SD_INFO2);
+	uniphier_sd_writel(priv, 0, UNIPHIER_SD_INFO2);
 
 	if (likely(IS_ALIGNED((unsigned long)*pbuf, 4))) {
 		for (i = 0; i < blocksize / 4; i++)
-			writel(*(*pbuf)++, priv->regbase + UNIPHIER_SD_BUF);
+			uniphier_sd_writel(priv, *(*pbuf)++, UNIPHIER_SD_BUF);
 	} else {
 		for (i = 0; i < blocksize / 4; i++)
-			writel(get_unaligned((*pbuf)++),
-			       priv->regbase + UNIPHIER_SD_BUF);
+			uniphier_sd_writel(priv, get_unaligned((*pbuf)++),
+					   UNIPHIER_SD_BUF);
 	}
 
 	return 0;
@@ -292,22 +303,22 @@ static void uniphier_sd_dma_start(struct uniphier_sd_priv *priv,
 {
 	u32 tmp;
 
-	writel(0, priv->regbase + UNIPHIER_SD_DMA_INFO1);
-	writel(0, priv->regbase + UNIPHIER_SD_DMA_INFO2);
+	uniphier_sd_writel(priv, 0, UNIPHIER_SD_DMA_INFO1);
+	uniphier_sd_writel(priv, 0, UNIPHIER_SD_DMA_INFO2);
 
 	/* enable DMA */
-	tmp = readl(priv->regbase + UNIPHIER_SD_EXTMODE);
+	tmp = uniphier_sd_readl(priv, UNIPHIER_SD_EXTMODE);
 	tmp |= UNIPHIER_SD_EXTMODE_DMA_EN;
-	writel(tmp, priv->regbase + UNIPHIER_SD_EXTMODE);
+	uniphier_sd_writel(priv, tmp, UNIPHIER_SD_EXTMODE);
 
-	writel(dma_addr & U32_MAX, priv->regbase + UNIPHIER_SD_DMA_ADDR_L);
+	uniphier_sd_writel(priv, dma_addr & U32_MAX, UNIPHIER_SD_DMA_ADDR_L);
 
 	/* suppress the warning "right shift count >= width of type" */
 	dma_addr >>= min_t(int, 32, 8 * sizeof(dma_addr));
 
-	writel(dma_addr & U32_MAX, priv->regbase + UNIPHIER_SD_DMA_ADDR_H);
+	uniphier_sd_writel(priv, dma_addr & U32_MAX, UNIPHIER_SD_DMA_ADDR_H);
 
-	writel(UNIPHIER_SD_DMA_CTL_START, priv->regbase + UNIPHIER_SD_DMA_CTL);
+	uniphier_sd_writel(priv, UNIPHIER_SD_DMA_CTL_START, UNIPHIER_SD_DMA_CTL);
 }
 
 static int uniphier_sd_dma_wait_for_irq(struct udevice *dev, u32 flag,
@@ -316,7 +327,7 @@ static int uniphier_sd_dma_wait_for_irq(struct udevice *dev, u32 flag,
 	struct uniphier_sd_priv *priv = dev_get_priv(dev);
 	long wait = 1000000 + 10 * blocks;
 
-	while (!(readl(priv->regbase + UNIPHIER_SD_DMA_INFO1) & flag)) {
+	while (!(uniphier_sd_readl(priv, UNIPHIER_SD_DMA_INFO1) & flag)) {
 		if (wait-- < 0) {
 			dev_err(dev, "timeout during DMA\n");
 			return -ETIMEDOUT;
@@ -325,7 +336,7 @@ static int uniphier_sd_dma_wait_for_irq(struct udevice *dev, u32 flag,
 		udelay(10);
 	}
 
-	if (readl(priv->regbase + UNIPHIER_SD_DMA_INFO2)) {
+	if (uniphier_sd_readl(priv, UNIPHIER_SD_DMA_INFO2)) {
 		dev_err(dev, "error during DMA\n");
 		return -EIO;
 	}
@@ -343,7 +354,7 @@ static int uniphier_sd_dma_xfer(struct udevice *dev, struct mmc_data *data)
 	u32 poll_flag, tmp;
 	int ret;
 
-	tmp = readl(priv->regbase + UNIPHIER_SD_DMA_MODE);
+	tmp = uniphier_sd_readl(priv, UNIPHIER_SD_DMA_MODE);
 
 	if (data->flags & MMC_DATA_READ) {
 		buf = data->dest;
@@ -357,7 +368,7 @@ static int uniphier_sd_dma_xfer(struct udevice *dev, struct mmc_data *data)
 		tmp &= ~UNIPHIER_SD_DMA_MODE_DIR_RD;
 	}
 
-	writel(tmp, priv->regbase + UNIPHIER_SD_DMA_MODE);
+	uniphier_sd_writel(priv, tmp, UNIPHIER_SD_DMA_MODE);
 
 	dma_addr = __dma_map_single(buf, len, dir);
 
@@ -396,27 +407,27 @@ static int uniphier_sd_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
 	int ret;
 	u32 tmp;
 
-	if (readl(priv->regbase + UNIPHIER_SD_INFO2) & UNIPHIER_SD_INFO2_CBSY) {
+	if (uniphier_sd_readl(priv, UNIPHIER_SD_INFO2) & UNIPHIER_SD_INFO2_CBSY) {
 		dev_err(dev, "command busy\n");
 		return -EBUSY;
 	}
 
 	/* clear all status flags */
-	writel(0, priv->regbase + UNIPHIER_SD_INFO1);
-	writel(0, priv->regbase + UNIPHIER_SD_INFO2);
+	uniphier_sd_writel(priv, 0, UNIPHIER_SD_INFO1);
+	uniphier_sd_writel(priv, 0, UNIPHIER_SD_INFO2);
 
 	/* disable DMA once */
-	tmp = readl(priv->regbase + UNIPHIER_SD_EXTMODE);
+	tmp = uniphier_sd_readl(priv, UNIPHIER_SD_EXTMODE);
 	tmp &= ~UNIPHIER_SD_EXTMODE_DMA_EN;
-	writel(tmp, priv->regbase + UNIPHIER_SD_EXTMODE);
+	uniphier_sd_writel(priv, tmp, UNIPHIER_SD_EXTMODE);
 
-	writel(cmd->cmdarg, priv->regbase + UNIPHIER_SD_ARG);
+	uniphier_sd_writel(priv, cmd->cmdarg, UNIPHIER_SD_ARG);
 
 	tmp = cmd->cmdidx;
 
 	if (data) {
-		writel(data->blocksize, priv->regbase + UNIPHIER_SD_SIZE);
-		writel(data->blocks, priv->regbase + UNIPHIER_SD_SECCNT);
+		uniphier_sd_writel(priv, data->blocksize, UNIPHIER_SD_SIZE);
+		uniphier_sd_writel(priv, data->blocks, UNIPHIER_SD_SECCNT);
 
 		/* Do not send CMD12 automatically */
 		tmp |= UNIPHIER_SD_CMD_NOSTOP | UNIPHIER_SD_CMD_DATA;
@@ -457,7 +468,7 @@ static int uniphier_sd_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
 
 	dev_dbg(dev, "sending CMD%d (SD_CMD=%08x, SD_ARG=%08x)\n",
 		cmd->cmdidx, tmp, cmd->cmdarg);
-	writel(tmp, priv->regbase + UNIPHIER_SD_CMD);
+	uniphier_sd_writel(priv, tmp, UNIPHIER_SD_CMD);
 
 	ret = uniphier_sd_wait_for_irq(dev, UNIPHIER_SD_INFO1,
 				       UNIPHIER_SD_INFO1_RSP);
@@ -465,10 +476,10 @@ static int uniphier_sd_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
 		return ret;
 
 	if (cmd->resp_type & MMC_RSP_136) {
-		u32 rsp_127_104 = readl(priv->regbase + UNIPHIER_SD_RSP76);
-		u32 rsp_103_72 = readl(priv->regbase + UNIPHIER_SD_RSP54);
-		u32 rsp_71_40 = readl(priv->regbase + UNIPHIER_SD_RSP32);
-		u32 rsp_39_8 = readl(priv->regbase + UNIPHIER_SD_RSP10);
+		u32 rsp_127_104 = uniphier_sd_readl(priv, UNIPHIER_SD_RSP76);
+		u32 rsp_103_72 = uniphier_sd_readl(priv, UNIPHIER_SD_RSP54);
+		u32 rsp_71_40 = uniphier_sd_readl(priv, UNIPHIER_SD_RSP32);
+		u32 rsp_39_8 = uniphier_sd_readl(priv, UNIPHIER_SD_RSP10);
 
 		cmd->response[0] = ((rsp_127_104 & 0x00ffffff) << 8) |
 				   ((rsp_103_72  & 0xff000000) >> 24);
@@ -479,7 +490,7 @@ static int uniphier_sd_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
 		cmd->response[3] = (rsp_39_8     & 0xffffff)   << 8;
 	} else {
 		/* bit 39-8 */
-		cmd->response[0] = readl(priv->regbase + UNIPHIER_SD_RSP10);
+		cmd->response[0] = uniphier_sd_readl(priv, UNIPHIER_SD_RSP10);
 	}
 
 	if (data) {
@@ -518,10 +529,10 @@ static int uniphier_sd_set_bus_width(struct uniphier_sd_priv *priv,
 		return -EINVAL;
 	}
 
-	tmp = readl(priv->regbase + UNIPHIER_SD_OPTION);
+	tmp = uniphier_sd_readl(priv, UNIPHIER_SD_OPTION);
 	tmp &= ~UNIPHIER_SD_OPTION_WIDTH_MASK;
 	tmp |= val;
-	writel(tmp, priv->regbase + UNIPHIER_SD_OPTION);
+	uniphier_sd_writel(priv, tmp, UNIPHIER_SD_OPTION);
 
 	return 0;
 }
@@ -531,12 +542,12 @@ static void uniphier_sd_set_ddr_mode(struct uniphier_sd_priv *priv,
 {
 	u32 tmp;
 
-	tmp = readl(priv->regbase + UNIPHIER_SD_IF_MODE);
+	tmp = uniphier_sd_readl(priv, UNIPHIER_SD_IF_MODE);
 	if (mmc->ddr_mode)
 		tmp |= UNIPHIER_SD_IF_MODE_DDR;
 	else
 		tmp &= ~UNIPHIER_SD_IF_MODE_DDR;
-	writel(tmp, priv->regbase + UNIPHIER_SD_IF_MODE);
+	uniphier_sd_writel(priv, tmp, UNIPHIER_SD_IF_MODE);
 }
 
 static void uniphier_sd_set_clk_rate(struct uniphier_sd_priv *priv,
@@ -573,21 +584,21 @@ static void uniphier_sd_set_clk_rate(struct uniphier_sd_priv *priv,
 	else
 		val = UNIPHIER_SD_CLKCTL_DIV1024;
 
-	tmp = readl(priv->regbase + UNIPHIER_SD_CLKCTL);
+	tmp = uniphier_sd_readl(priv, UNIPHIER_SD_CLKCTL);
 	if (tmp & UNIPHIER_SD_CLKCTL_SCLKEN &&
 	    (tmp & UNIPHIER_SD_CLKCTL_DIV_MASK) == val)
 		return;
 
 	/* stop the clock before changing its rate to avoid a glitch signal */
 	tmp &= ~UNIPHIER_SD_CLKCTL_SCLKEN;
-	writel(tmp, priv->regbase + UNIPHIER_SD_CLKCTL);
+	uniphier_sd_writel(priv, tmp, UNIPHIER_SD_CLKCTL);
 
 	tmp &= ~UNIPHIER_SD_CLKCTL_DIV_MASK;
 	tmp |= val | UNIPHIER_SD_CLKCTL_OFFEN;
-	writel(tmp, priv->regbase + UNIPHIER_SD_CLKCTL);
+	uniphier_sd_writel(priv, tmp, UNIPHIER_SD_CLKCTL);
 
 	tmp |= UNIPHIER_SD_CLKCTL_SCLKEN;
-	writel(tmp, priv->regbase + UNIPHIER_SD_CLKCTL);
+	uniphier_sd_writel(priv, tmp, UNIPHIER_SD_CLKCTL);
 
 	udelay(1000);
 }
@@ -617,7 +628,7 @@ static int uniphier_sd_get_cd(struct udevice *dev)
 	if (priv->caps & UNIPHIER_SD_CAP_NONREMOVABLE)
 		return 1;
 
-	return !!(readl(priv->regbase + UNIPHIER_SD_INFO1) &
+	return !!(uniphier_sd_readl(priv, UNIPHIER_SD_INFO1) &
 		  UNIPHIER_SD_INFO1_CD);
 }
 
@@ -632,28 +643,28 @@ static void uniphier_sd_host_init(struct uniphier_sd_priv *priv)
 	u32 tmp;
 
 	/* soft reset of the host */
-	tmp = readl(priv->regbase + UNIPHIER_SD_SOFT_RST);
+	tmp = uniphier_sd_readl(priv, UNIPHIER_SD_SOFT_RST);
 	tmp &= ~UNIPHIER_SD_SOFT_RST_RSTX;
-	writel(tmp, priv->regbase + UNIPHIER_SD_SOFT_RST);
+	uniphier_sd_writel(priv, tmp, UNIPHIER_SD_SOFT_RST);
 	tmp |= UNIPHIER_SD_SOFT_RST_RSTX;
-	writel(tmp, priv->regbase + UNIPHIER_SD_SOFT_RST);
+	uniphier_sd_writel(priv, tmp, UNIPHIER_SD_SOFT_RST);
 
 	/* FIXME: implement eMMC hw_reset */
 
-	writel(UNIPHIER_SD_STOP_SEC, priv->regbase + UNIPHIER_SD_STOP);
+	uniphier_sd_writel(priv, UNIPHIER_SD_STOP_SEC, UNIPHIER_SD_STOP);
 
 	/*
 	 * Connected to 32bit AXI.
 	 * This register dropped backward compatibility at version 0x10.
 	 * Write an appropriate value depending on the IP version.
 	 */
-	writel(priv->version >= 0x10 ? 0x00000101 : 0x00000000,
-	       priv->regbase + UNIPHIER_SD_HOST_MODE);
+	uniphier_sd_writel(priv, priv->version >= 0x10 ? 0x00000101 : 0x00000000,
+			   UNIPHIER_SD_HOST_MODE);
 
 	if (priv->caps & UNIPHIER_SD_CAP_DMA_INTERNAL) {
-		tmp = readl(priv->regbase + UNIPHIER_SD_DMA_MODE);
+		tmp = uniphier_sd_readl(priv, UNIPHIER_SD_DMA_MODE);
 		tmp |= UNIPHIER_SD_DMA_MODE_ADDR_INC;
-		writel(tmp, priv->regbase + UNIPHIER_SD_DMA_MODE);
+		uniphier_sd_writel(priv, tmp, UNIPHIER_SD_DMA_MODE);
 	}
 }
 
@@ -724,7 +735,7 @@ static int uniphier_sd_probe(struct udevice *dev)
 			     NULL))
 		priv->caps |= UNIPHIER_SD_CAP_NONREMOVABLE;
 
-	priv->version = readl(priv->regbase + UNIPHIER_SD_VERSION) &
+	priv->version = uniphier_sd_readl(priv, UNIPHIER_SD_VERSION) &
 							UNIPHIER_SD_VERSION_IP;
 	dev_dbg(dev, "version %x\n", priv->version);
 	if (priv->version >= 0x10) {
-- 
2.11.0

[U-Boot] [PATCH 2/5] mmc: uniphier-sd: Add support for 64bit controller

[Marek Vasut]

The Renesas RCar Gen3 contains the same controller, originally
Matsushita, yet the register addresses are shifted by 1 to the
left. The whole controller is also 64bit, including the data
FIFOs and RSP registers. This patch adds support for handling
the register IO by shifting the register offset by 1 in the IO
accessor functions.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
---
 drivers/mmc/uniphier-sd.c | 11 +++++++++--
 1 file changed, 9 insertions(+), 2 deletions(-)

diff --git a/drivers/mmc/uniphier-sd.c b/drivers/mmc/uniphier-sd.c
index cb53b28737..bb9b2c4e04 100644
--- a/drivers/mmc/uniphier-sd.c
+++ b/drivers/mmc/uniphier-sd.c
@@ -132,17 +132,24 @@ struct uniphier_sd_priv {
 #define UNIPHIER_SD_CAP_NONREMOVABLE	BIT(0)	/* Nonremovable e.g. eMMC */
 #define UNIPHIER_SD_CAP_DMA_INTERNAL	BIT(1)	/* have internal DMA engine */
 #define UNIPHIER_SD_CAP_DIV1024		BIT(2)	/* divisor 1024 is available */
+#define UNIPHIER_SD_CAP_64BIT		BIT(3)	/* Controller is 64bit */
 };
 
 static u32 uniphier_sd_readl(struct uniphier_sd_priv *priv, unsigned int reg)
 {
-	return readl(priv->regbase + reg);
+	if (priv->caps & UNIPHIER_SD_CAP_64BIT)
+		return readl(priv->regbase + (reg << 1));
+	else
+		return readl(priv->regbase + reg);
 }
 
 static void uniphier_sd_writel(struct uniphier_sd_priv *priv,
 			       u32 val, unsigned int reg)
 {
-	writel(val, priv->regbase + reg);
+	if (priv->caps & UNIPHIER_SD_CAP_64BIT)
+		writel(val, priv->regbase + (reg << 1));
+	else
+		writel(val, priv->regbase + reg);
 }
 
 static dma_addr_t __dma_map_single(void *ptr, size_t size,
-- 
2.11.0

[U-Boot] [PATCH V3 3/5] mmc: uniphier-sd: Add support for 64bit FIFO

[Marek Vasut]

The Renesas RCar Gen3 contains the same controller, originally
Matsushita. This patch adds support for handling of the 64bit
FIFO on this controller.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
---
V2: - Use unsigned int for the reg argument of IO accessors
    - Rework the handling of aligned and unaligned data
V3: Remove const ...
---
 drivers/mmc/uniphier-sd.c | 101 +++++++++++++++++++++++++++++++++++++---------
 1 file changed, 83 insertions(+), 18 deletions(-)

diff --git a/drivers/mmc/uniphier-sd.c b/drivers/mmc/uniphier-sd.c
index bb9b2c4e04..0b594a0c90 100644
--- a/drivers/mmc/uniphier-sd.c
+++ b/drivers/mmc/uniphier-sd.c
@@ -135,6 +135,23 @@ struct uniphier_sd_priv {
 #define UNIPHIER_SD_CAP_64BIT		BIT(3)	/* Controller is 64bit */
 };
 
+static u64 uniphier_sd_readq(struct uniphier_sd_priv *priv, unsigned int reg)
+{
+	if (priv->caps & UNIPHIER_SD_CAP_64BIT)
+		return readq(priv->regbase + (reg << 1));
+	else
+		return readq(priv->regbase + reg);
+}
+
+static void uniphier_sd_writeq(struct uniphier_sd_priv *priv,
+			       u64 val, unsigned int reg)
+{
+	if (priv->caps & UNIPHIER_SD_CAP_64BIT)
+		writeq(val, priv->regbase + (reg << 1));
+	else
+		writeq(val, priv->regbase + reg);
+}
+
 static u32 uniphier_sd_readl(struct uniphier_sd_priv *priv, unsigned int reg)
 {
 	if (priv->caps & UNIPHIER_SD_CAP_64BIT)
@@ -229,7 +246,7 @@ static int uniphier_sd_wait_for_irq(struct udevice *dev, unsigned int reg,
 	return 0;
 }
 
-static int uniphier_sd_pio_read_one_block(struct udevice *dev, u32 **pbuf,
+static int uniphier_sd_pio_read_one_block(struct udevice *dev, char *pbuf,
 					  uint blocksize)
 {
 	struct uniphier_sd_priv *priv = dev_get_priv(dev);
@@ -247,20 +264,42 @@ static int uniphier_sd_pio_read_one_block(struct udevice *dev, u32 **pbuf,
 	 */
 	uniphier_sd_writel(priv, 0, UNIPHIER_SD_INFO2);
 
-	if (likely(IS_ALIGNED((unsigned long)*pbuf, 4))) {
-		for (i = 0; i < blocksize / 4; i++)
-			*(*pbuf)++ = uniphier_sd_readl(priv, UNIPHIER_SD_BUF);
+	if (priv->caps & UNIPHIER_SD_CAP_64BIT) {
+		u64 *buf = (u64 *)pbuf;
+		if (likely(IS_ALIGNED((uintptr_t)buf, 8))) {
+			for (i = 0; i < blocksize / 8; i++) {
+				*buf++ = uniphier_sd_readq(priv,
+							   UNIPHIER_SD_BUF);
+			}
+		} else {
+			for (i = 0; i < blocksize / 8; i++) {
+				u64 data;
+				data = uniphier_sd_readq(priv,
+							 UNIPHIER_SD_BUF);
+				put_unaligned(data, buf++);
+			}
+		}
 	} else {
-		for (i = 0; i < blocksize / 4; i++)
-			put_unaligned(uniphier_sd_readl(priv, UNIPHIER_SD_BUF),
-				      (*pbuf)++);
+		u32 *buf = (u32 *)pbuf;
+		if (likely(IS_ALIGNED((uintptr_t)buf, 4))) {
+			for (i = 0; i < blocksize / 4; i++) {
+				*buf++ = uniphier_sd_readl(priv,
+							   UNIPHIER_SD_BUF);
+			}
+		} else {
+			for (i = 0; i < blocksize / 4; i++) {
+				u32 data;
+				data = uniphier_sd_readl(priv, UNIPHIER_SD_BUF);
+				put_unaligned(data, buf++);
+			}
+		}
 	}
 
 	return 0;
 }
 
 static int uniphier_sd_pio_write_one_block(struct udevice *dev,
-					   const u32 **pbuf, uint blocksize)
+					   const char *pbuf, uint blocksize)
 {
 	struct uniphier_sd_priv *priv = dev_get_priv(dev);
 	int i, ret;
@@ -273,13 +312,34 @@ static int uniphier_sd_pio_write_one_block(struct udevice *dev,
 
 	uniphier_sd_writel(priv, 0, UNIPHIER_SD_INFO2);
 
-	if (likely(IS_ALIGNED((unsigned long)*pbuf, 4))) {
-		for (i = 0; i < blocksize / 4; i++)
-			uniphier_sd_writel(priv, *(*pbuf)++, UNIPHIER_SD_BUF);
+	if (priv->caps & UNIPHIER_SD_CAP_64BIT) {
+		const u64 *buf = (const u64 *)pbuf;
+		if (likely(IS_ALIGNED((uintptr_t)buf, 8))) {
+			for (i = 0; i < blocksize / 8; i++) {
+				uniphier_sd_writeq(priv, *buf++,
+						   UNIPHIER_SD_BUF);
+			}
+		} else {
+			for (i = 0; i < blocksize / 8; i++) {
+				u64 data = get_unaligned(buf++);
+				uniphier_sd_writeq(priv, data,
+						   UNIPHIER_SD_BUF);
+			}
+		}
 	} else {
-		for (i = 0; i < blocksize / 4; i++)
-			uniphier_sd_writel(priv, get_unaligned((*pbuf)++),
-					   UNIPHIER_SD_BUF);
+		const u32 *buf = (const u32 *)pbuf;
+		if (likely(IS_ALIGNED((uintptr_t)buf, 4))) {
+			for (i = 0; i < blocksize / 4; i++) {
+				uniphier_sd_writel(priv, *buf++,
+						   UNIPHIER_SD_BUF);
+			}
+		} else {
+			for (i = 0; i < blocksize / 4; i++) {
+				u32 data = get_unaligned(buf++);
+				uniphier_sd_writel(priv, data,
+						   UNIPHIER_SD_BUF);
+			}
+		}
 	}
 
 	return 0;
@@ -287,19 +347,24 @@ static int uniphier_sd_pio_write_one_block(struct udevice *dev,
 
 static int uniphier_sd_pio_xfer(struct udevice *dev, struct mmc_data *data)
 {
-	u32 *dest = (u32 *)data->dest;
-	const u32 *src = (const u32 *)data->src;
+	const char *src = data->src;
+	char *dest = data->dest;
 	int i, ret;
 
 	for (i = 0; i < data->blocks; i++) {
 		if (data->flags & MMC_DATA_READ)
-			ret = uniphier_sd_pio_read_one_block(dev, &dest,
+			ret = uniphier_sd_pio_read_one_block(dev, dest,
 							     data->blocksize);
 		else
-			ret = uniphier_sd_pio_write_one_block(dev, &src,
+			ret = uniphier_sd_pio_write_one_block(dev, src,
 							      data->blocksize);
 		if (ret)
 			return ret;
+
+		if (data->flags & MMC_DATA_READ)
+			dest += data->blocksize;
+		else
+			src += data->blocksize;
 	}
 
 	return 0;
-- 
2.11.0

[U-Boot] [PATCH 4/5] mmc: uniphier-sd: Add support for quirks

[Marek Vasut]

Check if the OF match has any associated data and if so, use those
data as the controller quirks, otherwise fallback to the old method
of reading the controller version register to figure out the quirks.
This allows us to supply controller quirks on controllers which ie.
do not have version register.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
---
 drivers/mmc/uniphier-sd.c | 23 ++++++++++++++---------
 1 file changed, 14 insertions(+), 9 deletions(-)

diff --git a/drivers/mmc/uniphier-sd.c b/drivers/mmc/uniphier-sd.c
index 0b594a0c90..77a6d60c5c 100644
--- a/drivers/mmc/uniphier-sd.c
+++ b/drivers/mmc/uniphier-sd.c
@@ -752,6 +752,7 @@ static int uniphier_sd_probe(struct udevice *dev)
 	struct uniphier_sd_plat *plat = dev_get_platdata(dev);
 	struct uniphier_sd_priv *priv = dev_get_priv(dev);
 	struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
+	const u32 quirks = dev_get_driver_data(dev);
 	fdt_addr_t base;
 	struct clk clk;
 	int ret;
@@ -803,18 +804,22 @@ static int uniphier_sd_probe(struct udevice *dev)
 		return -EINVAL;
 	}
 
+	if (quirks) {
+		priv->caps = quirks;
+	} else {
+		priv->version = uniphier_sd_readl(priv, UNIPHIER_SD_VERSION) &
+							UNIPHIER_SD_VERSION_IP;
+		dev_dbg(dev, "version %x\n", priv->version);
+		if (priv->version >= 0x10) {
+			priv->caps |= UNIPHIER_SD_CAP_DMA_INTERNAL;
+			priv->caps |= UNIPHIER_SD_CAP_DIV1024;
+		}
+	}
+
 	if (fdt_get_property(gd->fdt_blob, dev_of_offset(dev), "non-removable",
 			     NULL))
 		priv->caps |= UNIPHIER_SD_CAP_NONREMOVABLE;
 
-	priv->version = uniphier_sd_readl(priv, UNIPHIER_SD_VERSION) &
-							UNIPHIER_SD_VERSION_IP;
-	dev_dbg(dev, "version %x\n", priv->version);
-	if (priv->version >= 0x10) {
-		priv->caps |= UNIPHIER_SD_CAP_DMA_INTERNAL;
-		priv->caps |= UNIPHIER_SD_CAP_DIV1024;
-	}
-
 	uniphier_sd_host_init(priv);
 
 	plat->cfg.voltages = MMC_VDD_165_195 | MMC_VDD_32_33 | MMC_VDD_33_34;
@@ -829,7 +834,7 @@ static int uniphier_sd_probe(struct udevice *dev)
 }
 
 static const struct udevice_id uniphier_sd_match[] = {
-	{ .compatible = "socionext,uniphier-sdhc" },
+	{ .compatible = "socionext,uniphier-sdhc", .data = 0 },
 	{ /* sentinel */ }
 };
 
-- 
2.11.0

[U-Boot] [PATCH 5/5] mmc: uniphier-sd: Add support for R8A7795 and R7A7796

[Marek Vasut]

Add OF match entries and quirks for Renesas RCar Gen3 controllers
into the driver. The IP this driver handles is in fact Matsushita
one and in used both in Socionext and Renesas chips.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
---
 drivers/mmc/Kconfig       | 7 ++++---
 drivers/mmc/uniphier-sd.c | 2 ++
 2 files changed, 6 insertions(+), 3 deletions(-)

diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig
index 56c352e72a..892437ed91 100644
--- a/drivers/mmc/Kconfig
+++ b/drivers/mmc/Kconfig
@@ -162,12 +162,13 @@ config SH_SDHI
 	  Support for the on-chip SDHI host controller on SuperH/Renesas ARM SoCs platform
 
 config MMC_UNIPHIER
-	bool "UniPhier SD/MMC Host Controller support"
-	depends on ARCH_UNIPHIER
+	bool "UniPhier/RCar SD/MMC Host Controller support"
+	depends on ARCH_UNIPHIER || ARCH_RMOBILE
 	depends on BLK && DM_MMC
 	depends on OF_CONTROL
 	help
-	  This selects support for the SD/MMC Host Controller on UniPhier SoCs.
+	  This selects support for the Matsushita SD/MMC Host Controller on
+	  SocioNext UniPhier and Renesas RCar SoCs.
 
 config MMC_SANDBOX
 	bool "Sandbox MMC support"
diff --git a/drivers/mmc/uniphier-sd.c b/drivers/mmc/uniphier-sd.c
index 77a6d60c5c..5c16f88d9c 100644
--- a/drivers/mmc/uniphier-sd.c
+++ b/drivers/mmc/uniphier-sd.c
@@ -834,6 +834,8 @@ static int uniphier_sd_probe(struct udevice *dev)
 }
 
 static const struct udevice_id uniphier_sd_match[] = {
+	{ .compatible = "renesas,sdhi-r8a7795", .data = UNIPHIER_SD_CAP_64BIT },
+	{ .compatible = "renesas,sdhi-r8a7796", .data = UNIPHIER_SD_CAP_64BIT },
 	{ .compatible = "socionext,uniphier-sdhc", .data = 0 },
 	{ /* sentinel */ }
 };
-- 
2.11.0

[U-Boot] [PATCH V3 1/5] mmc: uniphier-sd: Factor out register IO

[Masahiro Yamada]

2017-08-21 0:11 GMT+09:00 Marek Vasut <marek.vasut@gmail.com>:
> This patch prepares the driver to support controller(s) with registers
> at locations shifted by constant. Pull out the readl()/writel() from
> the driver into separate functions, where the adjustment of the register
> offset can be easily contained.
>
> Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
> Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
> Cc: Jaehoon Chung <jh80.chung@samsung.com>
> ---
> V2: Use unsigned int for the reg argument
> V3: Remove const ...
> ---

Thanks!

Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com>



-- 
Best Regards
Masahiro Yamada

[U-Boot] [PATCH 2/5] mmc: uniphier-sd: Add support for 64bit controller

[Masahiro Yamada]

2017-08-21 0:11 GMT+09:00 Marek Vasut <marek.vasut@gmail.com>:
> The Renesas RCar Gen3 contains the same controller, originally
> Matsushita, yet the register addresses are shifted by 1 to the
> left. The whole controller is also 64bit, including the data
> FIFOs and RSP registers. This patch adds support for handling
> the register IO by shifting the register offset by 1 in the IO
> accessor functions.
>
> Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
> Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
> Cc: Jaehoon Chung <jh80.chung@samsung.com>


Thanks!

Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com>

-- 
Best Regards
Masahiro Yamada

[U-Boot] [PATCH V3 3/5] mmc: uniphier-sd: Add support for 64bit FIFO

[Masahiro Yamada]

2017-08-21 0:11 GMT+09:00 Marek Vasut <marek.vasut@gmail.com>:
> The Renesas RCar Gen3 contains the same controller, originally
> Matsushita. This patch adds support for handling of the 64bit
> FIFO on this controller.
>
> Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
> Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
> Cc: Jaehoon Chung <jh80.chung@samsung.com>
> ---
> V2: - Use unsigned int for the reg argument of IO accessors
>     - Rework the handling of aligned and unaligned data
> V3: Remove const ...

Thanks!

Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com>


-- 
Best Regards
Masahiro Yamada

[U-Boot] [PATCH 4/5] mmc: uniphier-sd: Add support for quirks

[Masahiro Yamada]

2017-08-21 0:11 GMT+09:00 Marek Vasut <marek.vasut@gmail.com>:
> Check if the OF match has any associated data and if so, use those
> data as the controller quirks, otherwise fallback to the old method
> of reading the controller version register to figure out the quirks.
> This allows us to supply controller quirks on controllers which ie.
> do not have version register.
>
> Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
> Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
> Cc: Jaehoon Chung <jh80.chung@samsung.com>

Thanks!

Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com>


-- 
Best Regards
Masahiro Yamada

[U-Boot] [PATCH 5/5] mmc: uniphier-sd: Add support for R8A7795 and R7A7796

[Masahiro Yamada]

2017-08-21 0:11 GMT+09:00 Marek Vasut <marek.vasut@gmail.com>:
> Add OF match entries and quirks for Renesas RCar Gen3 controllers
> into the driver. The IP this driver handles is in fact Matsushita
> one and in used both in Socionext and Renesas chips.
>
> Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
> Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
> Cc: Jaehoon Chung <jh80.chung@samsung.com>

Thanks!

Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com>



-- 
Best Regards
Masahiro Yamada

[U-Boot] [PATCH V3 1/5] mmc: uniphier-sd: Factor out register IO

[Marek Vasut]

On 08/20/2017 05:11 PM, Marek Vasut wrote:
> This patch prepares the driver to support controller(s) with registers
> at locations shifted by constant. Pull out the readl()/writel() from
> the driver into separate functions, where the adjustment of the register
> offset can be easily contained.
> 
> Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
> Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
> Cc: Jaehoon Chung <jh80.chung@samsung.com>

Hello Jaehoon,

just a reminder that this missed previous MW, so it would be nice if it
made it into this one.

Thanks

> ---
> V2: Use unsigned int for the reg argument
> V3: Remove const ...
[...]

-- 
Best regards,
Marek Vasut

[U-Boot] [PATCH V3 1/5] mmc: uniphier-sd: Factor out register IO

[Marek Vasut]

On 09/12/2017 07:04 PM, Marek Vasut wrote:
> On 08/20/2017 05:11 PM, Marek Vasut wrote:
>> This patch prepares the driver to support controller(s) with registers
>> at locations shifted by constant. Pull out the readl()/writel() from
>> the driver into separate functions, where the adjustment of the register
>> offset can be easily contained.
>>
>> Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
>> Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
>> Cc: Jaehoon Chung <jh80.chung@samsung.com>
> 
> Hello Jaehoon,
> 
> just a reminder that this missed previous MW, so it would be nice if it
> made it into this one.

Another week has passed and no response. It has been a month since these
patches were posted and ACKed, but they are still not in the tree, what
is going on ?!

> Thanks
> 
>> ---
>> V2: Use unsigned int for the reg argument
>> V3: Remove const ...
> [...]
> 


-- 
Best regards,
Marek Vasut

[U-Boot] [PATCH V3 1/5] mmc: uniphier-sd: Factor out register IO

[Jaehoon Chung]

On 08/21/2017 12:11 AM, Marek Vasut wrote:
> This patch prepares the driver to support controller(s) with registers
> at locations shifted by constant. Pull out the readl()/writel() from
> the driver into separate functions, where the adjustment of the register
> offset can be easily contained.

Sorry for late. Applied to u-boot-mmc about [PATCH 1/5~5/5].
(After fixing some conflict - i did.)

Best Regards,
Jaehoon Chung

> 
> Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
> Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
> Cc: Jaehoon Chung <jh80.chung@samsung.com>
> ---
> V2: Use unsigned int for the reg argument
> V3: Remove const ...
> ---
>  drivers/mmc/uniphier-sd.c | 115 +++++++++++++++++++++++++---------------------
>  1 file changed, 63 insertions(+), 52 deletions(-)
> 
> diff --git a/drivers/mmc/uniphier-sd.c b/drivers/mmc/uniphier-sd.c
> index e272b14153..cb53b28737 100644
> --- a/drivers/mmc/uniphier-sd.c
> +++ b/drivers/mmc/uniphier-sd.c
> @@ -134,6 +134,17 @@ struct uniphier_sd_priv {
>  #define UNIPHIER_SD_CAP_DIV1024		BIT(2)	/* divisor 1024 is available */
>  };
>  
> +static u32 uniphier_sd_readl(struct uniphier_sd_priv *priv, unsigned int reg)
> +{
> +	return readl(priv->regbase + reg);
> +}
> +
> +static void uniphier_sd_writel(struct uniphier_sd_priv *priv,
> +			       u32 val, unsigned int reg)
> +{
> +	writel(val, priv->regbase + reg);
> +}
> +
>  static dma_addr_t __dma_map_single(void *ptr, size_t size,
>  				   enum dma_data_direction dir)
>  {
> @@ -157,7 +168,7 @@ static void __dma_unmap_single(dma_addr_t addr, size_t size,
>  static int uniphier_sd_check_error(struct udevice *dev)
>  {
>  	struct uniphier_sd_priv *priv = dev_get_priv(dev);
> -	u32 info2 = readl(priv->regbase + UNIPHIER_SD_INFO2);
> +	u32 info2 = uniphier_sd_readl(priv, UNIPHIER_SD_INFO2);
>  
>  	if (info2 & UNIPHIER_SD_INFO2_ERR_RTO) {
>  		/*
> @@ -195,7 +206,7 @@ static int uniphier_sd_wait_for_irq(struct udevice *dev, unsigned int reg,
>  	long wait = 1000000;
>  	int ret;
>  
> -	while (!(readl(priv->regbase + reg) & flag)) {
> +	while (!(uniphier_sd_readl(priv, reg) & flag)) {
>  		if (wait-- < 0) {
>  			dev_err(dev, "timeout\n");
>  			return -ETIMEDOUT;
> @@ -227,14 +238,14 @@ static int uniphier_sd_pio_read_one_block(struct udevice *dev, u32 **pbuf,
>  	 * Clear the status flag _before_ read the buffer out because
>  	 * UNIPHIER_SD_INFO2_BRE is edge-triggered, not level-triggered.
>  	 */
> -	writel(0, priv->regbase + UNIPHIER_SD_INFO2);
> +	uniphier_sd_writel(priv, 0, UNIPHIER_SD_INFO2);
>  
>  	if (likely(IS_ALIGNED((unsigned long)*pbuf, 4))) {
>  		for (i = 0; i < blocksize / 4; i++)
> -			*(*pbuf)++ = readl(priv->regbase + UNIPHIER_SD_BUF);
> +			*(*pbuf)++ = uniphier_sd_readl(priv, UNIPHIER_SD_BUF);
>  	} else {
>  		for (i = 0; i < blocksize / 4; i++)
> -			put_unaligned(readl(priv->regbase + UNIPHIER_SD_BUF),
> +			put_unaligned(uniphier_sd_readl(priv, UNIPHIER_SD_BUF),
>  				      (*pbuf)++);
>  	}
>  
> @@ -253,15 +264,15 @@ static int uniphier_sd_pio_write_one_block(struct udevice *dev,
>  	if (ret)
>  		return ret;
>  
> -	writel(0, priv->regbase + UNIPHIER_SD_INFO2);
> +	uniphier_sd_writel(priv, 0, UNIPHIER_SD_INFO2);
>  
>  	if (likely(IS_ALIGNED((unsigned long)*pbuf, 4))) {
>  		for (i = 0; i < blocksize / 4; i++)
> -			writel(*(*pbuf)++, priv->regbase + UNIPHIER_SD_BUF);
> +			uniphier_sd_writel(priv, *(*pbuf)++, UNIPHIER_SD_BUF);
>  	} else {
>  		for (i = 0; i < blocksize / 4; i++)
> -			writel(get_unaligned((*pbuf)++),
> -			       priv->regbase + UNIPHIER_SD_BUF);
> +			uniphier_sd_writel(priv, get_unaligned((*pbuf)++),
> +					   UNIPHIER_SD_BUF);
>  	}
>  
>  	return 0;
> @@ -292,22 +303,22 @@ static void uniphier_sd_dma_start(struct uniphier_sd_priv *priv,
>  {
>  	u32 tmp;
>  
> -	writel(0, priv->regbase + UNIPHIER_SD_DMA_INFO1);
> -	writel(0, priv->regbase + UNIPHIER_SD_DMA_INFO2);
> +	uniphier_sd_writel(priv, 0, UNIPHIER_SD_DMA_INFO1);
> +	uniphier_sd_writel(priv, 0, UNIPHIER_SD_DMA_INFO2);
>  
>  	/* enable DMA */
> -	tmp = readl(priv->regbase + UNIPHIER_SD_EXTMODE);
> +	tmp = uniphier_sd_readl(priv, UNIPHIER_SD_EXTMODE);
>  	tmp |= UNIPHIER_SD_EXTMODE_DMA_EN;
> -	writel(tmp, priv->regbase + UNIPHIER_SD_EXTMODE);
> +	uniphier_sd_writel(priv, tmp, UNIPHIER_SD_EXTMODE);
>  
> -	writel(dma_addr & U32_MAX, priv->regbase + UNIPHIER_SD_DMA_ADDR_L);
> +	uniphier_sd_writel(priv, dma_addr & U32_MAX, UNIPHIER_SD_DMA_ADDR_L);
>  
>  	/* suppress the warning "right shift count >= width of type" */
>  	dma_addr >>= min_t(int, 32, 8 * sizeof(dma_addr));
>  
> -	writel(dma_addr & U32_MAX, priv->regbase + UNIPHIER_SD_DMA_ADDR_H);
> +	uniphier_sd_writel(priv, dma_addr & U32_MAX, UNIPHIER_SD_DMA_ADDR_H);
>  
> -	writel(UNIPHIER_SD_DMA_CTL_START, priv->regbase + UNIPHIER_SD_DMA_CTL);
> +	uniphier_sd_writel(priv, UNIPHIER_SD_DMA_CTL_START, UNIPHIER_SD_DMA_CTL);
>  }
>  
>  static int uniphier_sd_dma_wait_for_irq(struct udevice *dev, u32 flag,
> @@ -316,7 +327,7 @@ static int uniphier_sd_dma_wait_for_irq(struct udevice *dev, u32 flag,
>  	struct uniphier_sd_priv *priv = dev_get_priv(dev);
>  	long wait = 1000000 + 10 * blocks;
>  
> -	while (!(readl(priv->regbase + UNIPHIER_SD_DMA_INFO1) & flag)) {
> +	while (!(uniphier_sd_readl(priv, UNIPHIER_SD_DMA_INFO1) & flag)) {
>  		if (wait-- < 0) {
>  			dev_err(dev, "timeout during DMA\n");
>  			return -ETIMEDOUT;
> @@ -325,7 +336,7 @@ static int uniphier_sd_dma_wait_for_irq(struct udevice *dev, u32 flag,
>  		udelay(10);
>  	}
>  
> -	if (readl(priv->regbase + UNIPHIER_SD_DMA_INFO2)) {
> +	if (uniphier_sd_readl(priv, UNIPHIER_SD_DMA_INFO2)) {
>  		dev_err(dev, "error during DMA\n");
>  		return -EIO;
>  	}
> @@ -343,7 +354,7 @@ static int uniphier_sd_dma_xfer(struct udevice *dev, struct mmc_data *data)
>  	u32 poll_flag, tmp;
>  	int ret;
>  
> -	tmp = readl(priv->regbase + UNIPHIER_SD_DMA_MODE);
> +	tmp = uniphier_sd_readl(priv, UNIPHIER_SD_DMA_MODE);
>  
>  	if (data->flags & MMC_DATA_READ) {
>  		buf = data->dest;
> @@ -357,7 +368,7 @@ static int uniphier_sd_dma_xfer(struct udevice *dev, struct mmc_data *data)
>  		tmp &= ~UNIPHIER_SD_DMA_MODE_DIR_RD;
>  	}
>  
> -	writel(tmp, priv->regbase + UNIPHIER_SD_DMA_MODE);
> +	uniphier_sd_writel(priv, tmp, UNIPHIER_SD_DMA_MODE);
>  
>  	dma_addr = __dma_map_single(buf, len, dir);
>  
> @@ -396,27 +407,27 @@ static int uniphier_sd_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
>  	int ret;
>  	u32 tmp;
>  
> -	if (readl(priv->regbase + UNIPHIER_SD_INFO2) & UNIPHIER_SD_INFO2_CBSY) {
> +	if (uniphier_sd_readl(priv, UNIPHIER_SD_INFO2) & UNIPHIER_SD_INFO2_CBSY) {
>  		dev_err(dev, "command busy\n");
>  		return -EBUSY;
>  	}
>  
>  	/* clear all status flags */
> -	writel(0, priv->regbase + UNIPHIER_SD_INFO1);
> -	writel(0, priv->regbase + UNIPHIER_SD_INFO2);
> +	uniphier_sd_writel(priv, 0, UNIPHIER_SD_INFO1);
> +	uniphier_sd_writel(priv, 0, UNIPHIER_SD_INFO2);
>  
>  	/* disable DMA once */
> -	tmp = readl(priv->regbase + UNIPHIER_SD_EXTMODE);
> +	tmp = uniphier_sd_readl(priv, UNIPHIER_SD_EXTMODE);
>  	tmp &= ~UNIPHIER_SD_EXTMODE_DMA_EN;
> -	writel(tmp, priv->regbase + UNIPHIER_SD_EXTMODE);
> +	uniphier_sd_writel(priv, tmp, UNIPHIER_SD_EXTMODE);
>  
> -	writel(cmd->cmdarg, priv->regbase + UNIPHIER_SD_ARG);
> +	uniphier_sd_writel(priv, cmd->cmdarg, UNIPHIER_SD_ARG);
>  
>  	tmp = cmd->cmdidx;
>  
>  	if (data) {
> -		writel(data->blocksize, priv->regbase + UNIPHIER_SD_SIZE);
> -		writel(data->blocks, priv->regbase + UNIPHIER_SD_SECCNT);
> +		uniphier_sd_writel(priv, data->blocksize, UNIPHIER_SD_SIZE);
> +		uniphier_sd_writel(priv, data->blocks, UNIPHIER_SD_SECCNT);
>  
>  		/* Do not send CMD12 automatically */
>  		tmp |= UNIPHIER_SD_CMD_NOSTOP | UNIPHIER_SD_CMD_DATA;
> @@ -457,7 +468,7 @@ static int uniphier_sd_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
>  
>  	dev_dbg(dev, "sending CMD%d (SD_CMD=%08x, SD_ARG=%08x)\n",
>  		cmd->cmdidx, tmp, cmd->cmdarg);
> -	writel(tmp, priv->regbase + UNIPHIER_SD_CMD);
> +	uniphier_sd_writel(priv, tmp, UNIPHIER_SD_CMD);
>  
>  	ret = uniphier_sd_wait_for_irq(dev, UNIPHIER_SD_INFO1,
>  				       UNIPHIER_SD_INFO1_RSP);
> @@ -465,10 +476,10 @@ static int uniphier_sd_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
>  		return ret;
>  
>  	if (cmd->resp_type & MMC_RSP_136) {
> -		u32 rsp_127_104 = readl(priv->regbase + UNIPHIER_SD_RSP76);
> -		u32 rsp_103_72 = readl(priv->regbase + UNIPHIER_SD_RSP54);
> -		u32 rsp_71_40 = readl(priv->regbase + UNIPHIER_SD_RSP32);
> -		u32 rsp_39_8 = readl(priv->regbase + UNIPHIER_SD_RSP10);
> +		u32 rsp_127_104 = uniphier_sd_readl(priv, UNIPHIER_SD_RSP76);
> +		u32 rsp_103_72 = uniphier_sd_readl(priv, UNIPHIER_SD_RSP54);
> +		u32 rsp_71_40 = uniphier_sd_readl(priv, UNIPHIER_SD_RSP32);
> +		u32 rsp_39_8 = uniphier_sd_readl(priv, UNIPHIER_SD_RSP10);
>  
>  		cmd->response[0] = ((rsp_127_104 & 0x00ffffff) << 8) |
>  				   ((rsp_103_72  & 0xff000000) >> 24);
> @@ -479,7 +490,7 @@ static int uniphier_sd_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
>  		cmd->response[3] = (rsp_39_8     & 0xffffff)   << 8;
>  	} else {
>  		/* bit 39-8 */
> -		cmd->response[0] = readl(priv->regbase + UNIPHIER_SD_RSP10);
> +		cmd->response[0] = uniphier_sd_readl(priv, UNIPHIER_SD_RSP10);
>  	}
>  
>  	if (data) {
> @@ -518,10 +529,10 @@ static int uniphier_sd_set_bus_width(struct uniphier_sd_priv *priv,
>  		return -EINVAL;
>  	}
>  
> -	tmp = readl(priv->regbase + UNIPHIER_SD_OPTION);
> +	tmp = uniphier_sd_readl(priv, UNIPHIER_SD_OPTION);
>  	tmp &= ~UNIPHIER_SD_OPTION_WIDTH_MASK;
>  	tmp |= val;
> -	writel(tmp, priv->regbase + UNIPHIER_SD_OPTION);
> +	uniphier_sd_writel(priv, tmp, UNIPHIER_SD_OPTION);
>  
>  	return 0;
>  }
> @@ -531,12 +542,12 @@ static void uniphier_sd_set_ddr_mode(struct uniphier_sd_priv *priv,
>  {
>  	u32 tmp;
>  
> -	tmp = readl(priv->regbase + UNIPHIER_SD_IF_MODE);
> +	tmp = uniphier_sd_readl(priv, UNIPHIER_SD_IF_MODE);
>  	if (mmc->ddr_mode)
>  		tmp |= UNIPHIER_SD_IF_MODE_DDR;
>  	else
>  		tmp &= ~UNIPHIER_SD_IF_MODE_DDR;
> -	writel(tmp, priv->regbase + UNIPHIER_SD_IF_MODE);
> +	uniphier_sd_writel(priv, tmp, UNIPHIER_SD_IF_MODE);
>  }
>  
>  static void uniphier_sd_set_clk_rate(struct uniphier_sd_priv *priv,
> @@ -573,21 +584,21 @@ static void uniphier_sd_set_clk_rate(struct uniphier_sd_priv *priv,
>  	else
>  		val = UNIPHIER_SD_CLKCTL_DIV1024;
>  
> -	tmp = readl(priv->regbase + UNIPHIER_SD_CLKCTL);
> +	tmp = uniphier_sd_readl(priv, UNIPHIER_SD_CLKCTL);
>  	if (tmp & UNIPHIER_SD_CLKCTL_SCLKEN &&
>  	    (tmp & UNIPHIER_SD_CLKCTL_DIV_MASK) == val)
>  		return;
>  
>  	/* stop the clock before changing its rate to avoid a glitch signal */
>  	tmp &= ~UNIPHIER_SD_CLKCTL_SCLKEN;
> -	writel(tmp, priv->regbase + UNIPHIER_SD_CLKCTL);
> +	uniphier_sd_writel(priv, tmp, UNIPHIER_SD_CLKCTL);
>  
>  	tmp &= ~UNIPHIER_SD_CLKCTL_DIV_MASK;
>  	tmp |= val | UNIPHIER_SD_CLKCTL_OFFEN;
> -	writel(tmp, priv->regbase + UNIPHIER_SD_CLKCTL);
> +	uniphier_sd_writel(priv, tmp, UNIPHIER_SD_CLKCTL);
>  
>  	tmp |= UNIPHIER_SD_CLKCTL_SCLKEN;
> -	writel(tmp, priv->regbase + UNIPHIER_SD_CLKCTL);
> +	uniphier_sd_writel(priv, tmp, UNIPHIER_SD_CLKCTL);
>  
>  	udelay(1000);
>  }
> @@ -617,7 +628,7 @@ static int uniphier_sd_get_cd(struct udevice *dev)
>  	if (priv->caps & UNIPHIER_SD_CAP_NONREMOVABLE)
>  		return 1;
>  
> -	return !!(readl(priv->regbase + UNIPHIER_SD_INFO1) &
> +	return !!(uniphier_sd_readl(priv, UNIPHIER_SD_INFO1) &
>  		  UNIPHIER_SD_INFO1_CD);
>  }
>  
> @@ -632,28 +643,28 @@ static void uniphier_sd_host_init(struct uniphier_sd_priv *priv)
>  	u32 tmp;
>  
>  	/* soft reset of the host */
> -	tmp = readl(priv->regbase + UNIPHIER_SD_SOFT_RST);
> +	tmp = uniphier_sd_readl(priv, UNIPHIER_SD_SOFT_RST);
>  	tmp &= ~UNIPHIER_SD_SOFT_RST_RSTX;
> -	writel(tmp, priv->regbase + UNIPHIER_SD_SOFT_RST);
> +	uniphier_sd_writel(priv, tmp, UNIPHIER_SD_SOFT_RST);
>  	tmp |= UNIPHIER_SD_SOFT_RST_RSTX;
> -	writel(tmp, priv->regbase + UNIPHIER_SD_SOFT_RST);
> +	uniphier_sd_writel(priv, tmp, UNIPHIER_SD_SOFT_RST);
>  
>  	/* FIXME: implement eMMC hw_reset */
>  
> -	writel(UNIPHIER_SD_STOP_SEC, priv->regbase + UNIPHIER_SD_STOP);
> +	uniphier_sd_writel(priv, UNIPHIER_SD_STOP_SEC, UNIPHIER_SD_STOP);
>  
>  	/*
>  	 * Connected to 32bit AXI.
>  	 * This register dropped backward compatibility at version 0x10.
>  	 * Write an appropriate value depending on the IP version.
>  	 */
> -	writel(priv->version >= 0x10 ? 0x00000101 : 0x00000000,
> -	       priv->regbase + UNIPHIER_SD_HOST_MODE);
> +	uniphier_sd_writel(priv, priv->version >= 0x10 ? 0x00000101 : 0x00000000,
> +			   UNIPHIER_SD_HOST_MODE);
>  
>  	if (priv->caps & UNIPHIER_SD_CAP_DMA_INTERNAL) {
> -		tmp = readl(priv->regbase + UNIPHIER_SD_DMA_MODE);
> +		tmp = uniphier_sd_readl(priv, UNIPHIER_SD_DMA_MODE);
>  		tmp |= UNIPHIER_SD_DMA_MODE_ADDR_INC;
> -		writel(tmp, priv->regbase + UNIPHIER_SD_DMA_MODE);
> +		uniphier_sd_writel(priv, tmp, UNIPHIER_SD_DMA_MODE);
>  	}
>  }
>  
> @@ -724,7 +735,7 @@ static int uniphier_sd_probe(struct udevice *dev)
>  			     NULL))
>  		priv->caps |= UNIPHIER_SD_CAP_NONREMOVABLE;
>  
> -	priv->version = readl(priv->regbase + UNIPHIER_SD_VERSION) &
> +	priv->version = uniphier_sd_readl(priv, UNIPHIER_SD_VERSION) &
>  							UNIPHIER_SD_VERSION_IP;
>  	dev_dbg(dev, "version %x\n", priv->version);
>  	if (priv->version >= 0x10) {
> 

[U-Boot] [PATCH V3 1/5] mmc: uniphier-sd: Factor out register IO

[Masahiro Yamada]

2017-09-22 22:54 GMT+09:00 Jaehoon Chung <jh80.chung@samsung.com>:
> On 08/21/2017 12:11 AM, Marek Vasut wrote:
>> This patch prepares the driver to support controller(s) with registers
>> at locations shifted by constant. Pull out the readl()/writel() from
>> the driver into separate functions, where the adjustment of the register
>> offset can be easily contained.
>
> Sorry for late. Applied to u-boot-mmc about [PATCH 1/5~5/5].
> (After fixing some conflict - i did.)


What is worse, Jaehoon picked up wrong ones.
(seems v1)




-- 
Best Regards
Masahiro Yamada