* Re: [PATCH 000/100] Add Vega10 Support
@ 2017-03-20 21:36 Jan Ziak
[not found] ` <CAODFU0pW=uyAa9Bdjbzv63cFaBMoF34+rW9xWDorAuMKHFsRUQ-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
0 siblings, 1 reply; 16+ messages in thread
From: Jan Ziak @ 2017-03-20 21:36 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW, Alex Deucher
[-- Attachment #1.1: Type: text/plain, Size: 483 bytes --]
Hi
https://cgit.freedesktop.org/~agd5f/linux/plain/drivers/gpu/drm/amd/include/asic_reg/vega10/NBIO/nbio_6_1_sh_mask.h?h=amd-staging-4.9&id=9555ef0ba926df25d9a637d0ea21bc0d231c21d2
The file nbio_6_1_sh_mask.h is uncompressed. It consists from 133884 lines.
Only generated C/C++ code will be able to utilize the content of such a
file efficiently. All hand-written codes combined will be able to utilize
about 1% of the file.
Is there a reason why nbio_6_1_sh_mask.h is huge?
Jan
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^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH 000/100] Add Vega10 Support
[not found] ` <CAODFU0pW=uyAa9Bdjbzv63cFaBMoF34+rW9xWDorAuMKHFsRUQ-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
@ 2017-03-20 21:41 ` Alex Deucher
[not found] ` <CADnq5_ONBTDeGQC_3ApDBv+xa88r5ZvA0RHiZHbohYBZ48=F5g-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
0 siblings, 1 reply; 16+ messages in thread
From: Alex Deucher @ 2017-03-20 21:41 UTC (permalink / raw)
To: Jan Ziak; +Cc: amd-gfx list
On Mon, Mar 20, 2017 at 5:36 PM, Jan Ziak <0xe2.0x9a.0x9b@gmail.com> wrote:
> Hi
>
> https://cgit.freedesktop.org/~agd5f/linux/plain/drivers/gpu/drm/amd/include/asic_reg/vega10/NBIO/nbio_6_1_sh_mask.h?h=amd-staging-4.9&id=9555ef0ba926df25d9a637d0ea21bc0d231c21d2
>
> The file nbio_6_1_sh_mask.h is uncompressed. It consists from 133884 lines.
> Only generated C/C++ code will be able to utilize the content of such a file
> efficiently. All hand-written codes combined will be able to utilize about
> 1% of the file.
>
> Is there a reason why nbio_6_1_sh_mask.h is huge?
That IP block contains a lot of registers. The idea is to open source
as much IP as possible to facilitate debugging, new features, etc.
Alex
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^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH 000/100] Add Vega10 Support
[not found] ` <CADnq5_ONBTDeGQC_3ApDBv+xa88r5ZvA0RHiZHbohYBZ48=F5g-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
@ 2017-03-20 22:34 ` Jan Ziak
[not found] ` <CAODFU0q8C=yW-rBhf-Tj7AT=OijGfRViajMQH59WVYzHmPU9LA-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
0 siblings, 1 reply; 16+ messages in thread
From: Jan Ziak @ 2017-03-20 22:34 UTC (permalink / raw)
To: Alex Deucher; +Cc: amd-gfx list
[-- Attachment #1.1: Type: text/plain, Size: 4104 bytes --]
On Mon, Mar 20, 2017 at 10:41 PM, Alex Deucher <alexdeucher-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
wrote:
> On Mon, Mar 20, 2017 at 5:36 PM, Jan Ziak <0xe2.0x9a.0x9b-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
> wrote:
> > Hi
> >
> > https://cgit.freedesktop.org/~agd5f/linux/plain/drivers/gpu/
> drm/amd/include/asic_reg/vega10/NBIO/nbio_6_1_sh_mask.
> h?h=amd-staging-4.9&id=9555ef0ba926df25d9a637d0ea21bc0d231c21d2
> >
> > The file nbio_6_1_sh_mask.h is uncompressed. It consists from 133884
> lines.
> > Only generated C/C++ code will be able to utilize the content of such a
> file
> > efficiently. All hand-written codes combined will be able to utilize
> about
> > 1% of the file.
> >
> > Is there a reason why nbio_6_1_sh_mask.h is huge?
>
> That IP block contains a lot of registers. The idea is to open source
> as much IP as possible to facilitate debugging, new features, etc.
>
> Alex
>
[This email contains long/wide lines and should be viewed on a sufficiently
wide screen]
For example if I open the file in vim and go to line 66952:
#define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT
0x9
Then abstracting away some of the digits used in the defined identifier and
using egrep:
$ egrep
"\<DWC_E12MP_PHY_X._NS_X._._LANE._DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_.__DTB_SEL__SHIFT\>"
nbio_6_1_sh_mask.h
#define
DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT
0x9
#define
DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT
0x9
#define
DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT
0x9
#define
DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT
0x9
#define
DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT
0x9
#define
DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT
0x9
#define
DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT
0x9
#define
DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT
0x9
#define
DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT
0x9
#define
DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT
0x9
#define
DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT
0x9
#define
DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT
0x9
#define
DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT
0x9
#define
DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT
0x9
#define
DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT
0x9
#define
DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT
0x9
#define
DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT
0x9
#define
DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT
0x9
#define
DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT
0x9
#define
DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT
0x9
The egrep command produced 20 lines.
Instead of the many #define directives, it is a possibility to define
functions such as:
int
DWC_E12MP_PHY_Xa_NS_Xb_c_LANEd_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_e__DTB_SEL__SHIFT(int
a, int b, int c, int d, int e) __attribute__((pure));
I suppose the file nbio_6_1_sh_mask.h is the output of a tool (it is a
generated file). It is an option to modify the tool to output C functions
with proper input guards instead of #define directives.
Jan
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH 000/100] Add Vega10 Support
[not found] ` <CAODFU0q8C=yW-rBhf-Tj7AT=OijGfRViajMQH59WVYzHmPU9LA-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
@ 2017-03-20 23:38 ` Tom St Denis
[not found] ` <d1dc991e-8ae7-eae9-65bf-97c6319e8d17-5C7GfCeVMHo@public.gmane.org>
0 siblings, 1 reply; 16+ messages in thread
From: Tom St Denis @ 2017-03-20 23:38 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
On 03/20/2017 06:34 PM, Jan Ziak wrote:
> On Mon, Mar 20, 2017 at 10:41 PM, Alex Deucher <alexdeucher@gmail.com
> <mailto:alexdeucher@gmail.com>> wrote:
>
> On Mon, Mar 20, 2017 at 5:36 PM, Jan Ziak <0xe2.0x9a.0x9b@gmail.com
> <mailto:0xe2.0x9a.0x9b@gmail.com>> wrote:
> > Hi
> >
> > https://cgit.freedesktop.org/~agd5f/linux/plain/drivers/gpu/drm/amd/include/asic_reg/vega10/NBIO/nbio_6_1_sh_mask.h?h=amd-staging-4.9&id=9555ef0ba926df25d9a637d0ea21bc0d231c21d2
> <https://cgit.freedesktop.org/~agd5f/linux/plain/drivers/gpu/drm/amd/include/asic_reg/vega10/NBIO/nbio_6_1_sh_mask.h?h=amd-staging-4.9&id=9555ef0ba926df25d9a637d0ea21bc0d231c21d2>
> >
> > The file nbio_6_1_sh_mask.h is uncompressed. It consists from 133884 lines.
> > Only generated C/C++ code will be able to utilize the content of such a file
> > efficiently. All hand-written codes combined will be able to utilize about
> > 1% of the file.
> >
> > Is there a reason why nbio_6_1_sh_mask.h is huge?
>
> That IP block contains a lot of registers. The idea is to open source
> as much IP as possible to facilitate debugging, new features, etc.
>
> Alex
>
>
> [This email contains long/wide lines and should be viewed on a
> sufficiently wide screen]
>
> For example if I open the file in vim and go to line 66952:
>
> #define DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT
> 0x9
>
> Then abstracting away some of the digits used in the defined identifier
> and using egrep:
>
> $ egrep
> "\<DWC_E12MP_PHY_X._NS_X._._LANE._DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_.__DTB_SEL__SHIFT\>"
> nbio_6_1_sh_mask.h
> #define
> DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT
> 0x9
> #define
> DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT
> 0x9
> #define
> DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT
> 0x9
> #define
> DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT
> 0x9
> #define
> DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT
> 0x9
> #define
> DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT
> 0x9
> #define
> DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT
> 0x9
> #define
> DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT
> 0x9
> #define
> DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT
> 0x9
> #define
> DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT
> 0x9
> #define
> DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT
> 0x9
> #define
> DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT
> 0x9
> #define
> DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT
> 0x9
> #define
> DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT
> 0x9
> #define
> DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT
> 0x9
> #define
> DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT
> 0x9
> #define
> DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT
> 0x9
> #define
> DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT
> 0x9
> #define
> DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT
> 0x9
> #define
> DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT
> 0x9
>
> The egrep command produced 20 lines.
>
> Instead of the many #define directives, it is a possibility to define
> functions such as:
>
> int
> DWC_E12MP_PHY_Xa_NS_Xb_c_LANEd_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_e__DTB_SEL__SHIFT(int
> a, int b, int c, int d, int e) __attribute__((pure));
>
> I suppose the file nbio_6_1_sh_mask.h is the output of a tool (it is a
> generated file). It is an option to modify the tool to output C
> functions with proper input guards instead of #define directives.
The registers are generated by the HW team and then filtered down to
become what we release publicly. It is machine generated very likely
from the RTL that specifies the hardware itself.
Generally speaking if a class of registers share masks/offsets the
lowest (zero'th) is used in programming and offsets are used when
selecting the correct MMIO address to use specific instances.
Having these enumerated though is handy for tools like UMR which would
decode to the correct instance of the register (you could even see that
by watching the logscan via umr). So we make use of them fairly
efficiently. UMR reads the headers to create the arrays of
registers/bitfields which if they were computed at runtime (via helper
functions) would be harder to parse (and could amount to the halting
problem...).
What is in the NBIO header today is what was IP cleared but in theory it
could be filtered down more simply to reduce the unused LOCs in future
kernels.
They don't make for good bedtime reading but imho you'd rather have more
headers not less :-)
Tom
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^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH 000/100] Add Vega10 Support
[not found] ` <d1dc991e-8ae7-eae9-65bf-97c6319e8d17-5C7GfCeVMHo@public.gmane.org>
@ 2017-03-21 6:36 ` Christian König
[not found] ` <608e9c51-6610-bf11-a22a-a1f07e5cf4a9-5C7GfCeVMHo@public.gmane.org>
0 siblings, 1 reply; 16+ messages in thread
From: Christian König @ 2017-03-21 6:36 UTC (permalink / raw)
To: Tom St Denis, amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Am 21.03.2017 um 00:38 schrieb Tom St Denis:
> On 03/20/2017 06:34 PM, Jan Ziak wrote:
>> On Mon, Mar 20, 2017 at 10:41 PM, Alex Deucher <alexdeucher@gmail.com
>> <mailto:alexdeucher@gmail.com>> wrote:
>>
>> On Mon, Mar 20, 2017 at 5:36 PM, Jan Ziak <0xe2.0x9a.0x9b@gmail.com
>> <mailto:0xe2.0x9a.0x9b@gmail.com>> wrote:
>> > Hi
>> >
>> >
>> https://cgit.freedesktop.org/~agd5f/linux/plain/drivers/gpu/drm/amd/include/asic_reg/vega10/NBIO/nbio_6_1_sh_mask.h?h=amd-staging-4.9&id=9555ef0ba926df25d9a637d0ea21bc0d231c21d2
>> <https://cgit.freedesktop.org/~agd5f/linux/plain/drivers/gpu/drm/amd/include/asic_reg/vega10/NBIO/nbio_6_1_sh_mask.h?h=amd-staging-4.9&id=9555ef0ba926df25d9a637d0ea21bc0d231c21d2>
>> >
>> > The file nbio_6_1_sh_mask.h is uncompressed. It consists from
>> 133884 lines.
>> > Only generated C/C++ code will be able to utilize the content
>> of such a file
>> > efficiently. All hand-written codes combined will be able to
>> utilize about
>> > 1% of the file.
>> >
>> > Is there a reason why nbio_6_1_sh_mask.h is huge?
>>
>> That IP block contains a lot of registers. The idea is to open
>> source
>> as much IP as possible to facilitate debugging, new features, etc.
>>
>> Alex
>>
>>
>> [This email contains long/wide lines and should be viewed on a
>> sufficiently wide screen]
>>
>> For example if I open the file in vim and go to line 66952:
>>
>> #define
>> DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT
>> 0x9
>>
>> Then abstracting away some of the digits used in the defined identifier
>> and using egrep:
>>
>> $ egrep
>> "\<DWC_E12MP_PHY_X._NS_X._._LANE._DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_.__DTB_SEL__SHIFT\>"
>>
>> nbio_6_1_sh_mask.h
>> #define
>> DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT
>>
>> 0x9
>> #define
>> DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT
>>
>> 0x9
>> #define
>> DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT
>>
>> 0x9
>> #define
>> DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT
>>
>> 0x9
>> #define
>> DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT
>>
>> 0x9
>> #define
>> DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT
>>
>> 0x9
>> #define
>> DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT
>>
>> 0x9
>> #define
>> DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT
>>
>> 0x9
>> #define
>> DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT
>>
>> 0x9
>> #define
>> DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT
>>
>> 0x9
>> #define
>> DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT
>>
>> 0x9
>> #define
>> DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT
>>
>> 0x9
>> #define
>> DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT
>>
>> 0x9
>> #define
>> DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT
>>
>> 0x9
>> #define
>> DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT
>>
>> 0x9
>> #define
>> DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT
>>
>> 0x9
>> #define
>> DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT
>>
>> 0x9
>> #define
>> DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT
>>
>> 0x9
>> #define
>> DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT
>>
>> 0x9
>> #define
>> DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT
>>
>> 0x9
>>
>> The egrep command produced 20 lines.
>>
>> Instead of the many #define directives, it is a possibility to define
>> functions such as:
>>
>> int
>> DWC_E12MP_PHY_Xa_NS_Xb_c_LANEd_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_e__DTB_SEL__SHIFT(int
>>
>> a, int b, int c, int d, int e) __attribute__((pure));
>>
>> I suppose the file nbio_6_1_sh_mask.h is the output of a tool (it is a
>> generated file). It is an option to modify the tool to output C
>> functions with proper input guards instead of #define directives.
>
> The registers are generated by the HW team and then filtered down to
> become what we release publicly. It is machine generated very likely
> from the RTL that specifies the hardware itself.
Yes, exactly that. And it was actually quite some work to get to this point.
> Generally speaking if a class of registers share masks/offsets the
> lowest (zero'th) is used in programming and offsets are used when
> selecting the correct MMIO address to use specific instances.
The problem is that the files we get from the HW team describe the
register block already broken down to the memory mappings. E.g. when an
RTL block is instantiated N times you get N times the same definition.
>
> Having these enumerated though is handy for tools like UMR which would
> decode to the correct instance of the register (you could even see
> that by watching the logscan via umr). So we make use of them fairly
> efficiently. UMR reads the headers to create the arrays of
> registers/bitfields which if they were computed at runtime (via helper
> functions) would be harder to parse (and could amount to the halting
> problem...).
>
> What is in the NBIO header today is what was IP cleared but in theory
> it could be filtered down more simply to reduce the unused LOCs in
> future kernels.
>
> They don't make for good bedtime reading but imho you'd rather have
> more headers not less :-)
Manually merging that back into single definitions is not really an
option, but what we could do is releasing the full blown headers
somewhere and only limit what we push into the linux kernel to actually
used ones.
Christian.
>
> Tom
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH 000/100] Add Vega10 Support
[not found] ` <608e9c51-6610-bf11-a22a-a1f07e5cf4a9-5C7GfCeVMHo@public.gmane.org>
@ 2017-03-21 8:45 ` Edward O'Callaghan
[not found] ` <37027c02-1f10-858e-ca22-a6fc7cad330a-dczkZgxz+BNUPWh3PAxdjQ@public.gmane.org>
0 siblings, 1 reply; 16+ messages in thread
From: Edward O'Callaghan @ 2017-03-21 8:45 UTC (permalink / raw)
To: Christian König, Tom St Denis,
amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
[-- Attachment #1.1.1: Type: text/plain, Size: 7962 bytes --]
On 03/21/2017 05:36 PM, Christian König wrote:
> Am 21.03.2017 um 00:38 schrieb Tom St Denis:
>> On 03/20/2017 06:34 PM, Jan Ziak wrote:
>>> On Mon, Mar 20, 2017 at 10:41 PM, Alex Deucher <alexdeucher-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org
>>> <mailto:alexdeucher-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>> wrote:
>>>
>>> On Mon, Mar 20, 2017 at 5:36 PM, Jan Ziak <0xe2.0x9a.0x9b@gmail.com
>>> <mailto:0xe2.0x9a.0x9b-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>> wrote:
>>> > Hi
>>> >
>>> >
>>> https://cgit.freedesktop.org/~agd5f/linux/plain/drivers/gpu/drm/amd/include/asic_reg/vega10/NBIO/nbio_6_1_sh_mask.h?h=amd-staging-4.9&id=9555ef0ba926df25d9a637d0ea21bc0d231c21d2
>>>
>>> <https://cgit.freedesktop.org/~agd5f/linux/plain/drivers/gpu/drm/amd/include/asic_reg/vega10/NBIO/nbio_6_1_sh_mask.h?h=amd-staging-4.9&id=9555ef0ba926df25d9a637d0ea21bc0d231c21d2>
>>>
>>> >
>>> > The file nbio_6_1_sh_mask.h is uncompressed. It consists from
>>> 133884 lines.
>>> > Only generated C/C++ code will be able to utilize the content
>>> of such a file
>>> > efficiently. All hand-written codes combined will be able to
>>> utilize about
>>> > 1% of the file.
>>> >
>>> > Is there a reason why nbio_6_1_sh_mask.h is huge?
>>>
>>> That IP block contains a lot of registers. The idea is to open
>>> source
>>> as much IP as possible to facilitate debugging, new features, etc.
>>>
>>> Alex
>>>
>>>
>>> [This email contains long/wide lines and should be viewed on a
>>> sufficiently wide screen]
>>>
>>> For example if I open the file in vim and go to line 66952:
>>>
>>> #define
>>> DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT
>>>
>>> 0x9
>>>
>>> Then abstracting away some of the digits used in the defined identifier
>>> and using egrep:
>>>
>>> $ egrep
>>> "\<DWC_E12MP_PHY_X._NS_X._._LANE._DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_.__DTB_SEL__SHIFT\>"
>>>
>>> nbio_6_1_sh_mask.h
>>> #define
>>> DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT
>>>
>>> 0x9
>>> #define
>>> DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT
>>>
>>> 0x9
>>> #define
>>> DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT
>>>
>>> 0x9
>>> #define
>>> DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT
>>>
>>> 0x9
>>> #define
>>> DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT
>>>
>>> 0x9
>>> #define
>>> DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT
>>>
>>> 0x9
>>> #define
>>> DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT
>>>
>>> 0x9
>>> #define
>>> DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT
>>>
>>> 0x9
>>> #define
>>> DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT
>>>
>>> 0x9
>>> #define
>>> DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT
>>>
>>> 0x9
>>> #define
>>> DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT
>>>
>>> 0x9
>>> #define
>>> DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT
>>>
>>> 0x9
>>> #define
>>> DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT
>>>
>>> 0x9
>>> #define
>>> DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT
>>>
>>> 0x9
>>> #define
>>> DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT
>>>
>>> 0x9
>>> #define
>>> DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT
>>>
>>> 0x9
>>> #define
>>> DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT
>>>
>>> 0x9
>>> #define
>>> DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT
>>>
>>> 0x9
>>> #define
>>> DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT
>>>
>>> 0x9
>>> #define
>>> DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT
>>>
>>> 0x9
>>>
>>> The egrep command produced 20 lines.
>>>
>>> Instead of the many #define directives, it is a possibility to define
>>> functions such as:
>>>
>>> int
>>> DWC_E12MP_PHY_Xa_NS_Xb_c_LANEd_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_e__DTB_SEL__SHIFT(int
>>>
>>> a, int b, int c, int d, int e) __attribute__((pure));
>>>
>>> I suppose the file nbio_6_1_sh_mask.h is the output of a tool (it is a
>>> generated file). It is an option to modify the tool to output C
>>> functions with proper input guards instead of #define directives.
>>
>> The registers are generated by the HW team and then filtered down to
>> become what we release publicly. It is machine generated very likely
>> from the RTL that specifies the hardware itself.
>
> Yes, exactly that. And it was actually quite some work to get to this
> point.
>
>> Generally speaking if a class of registers share masks/offsets the
>> lowest (zero'th) is used in programming and offsets are used when
>> selecting the correct MMIO address to use specific instances.
>
> The problem is that the files we get from the HW team describe the
> register block already broken down to the memory mappings. E.g. when an
> RTL block is instantiated N times you get N times the same definition.
>
>>
>> Having these enumerated though is handy for tools like UMR which would
>> decode to the correct instance of the register (you could even see
>> that by watching the logscan via umr). So we make use of them fairly
>> efficiently. UMR reads the headers to create the arrays of
>> registers/bitfields which if they were computed at runtime (via helper
>> functions) would be harder to parse (and could amount to the halting
>> problem...).
>>
>> What is in the NBIO header today is what was IP cleared but in theory
>> it could be filtered down more simply to reduce the unused LOCs in
>> future kernels.
>>
>> They don't make for good bedtime reading but imho you'd rather have
>> more headers not less :-)
>
> Manually merging that back into single definitions is not really an
> option, but what we could do is releasing the full blown headers
> somewhere and only limit what we push into the linux kernel to actually
> used ones.
Hi Christian,
I have to say I prefer your idea here and perhaps they could even become
part of the UMR repo, not sure? May I suggest the reduction to some like
a `kernel-native-dialect` could be automated with a clang plugin. It
seems like heaps of work however maybe not really, clang provides a API
to grammatically do some AST transformers and auto-rewrite large chunks
of code given some rules.
I also agree with Tom, its certainly nice to have them regardless, just
perhaps the kernel mainline repo is the wrong place for the kitchen sink.
Just my thoughts,
Kind Regards,
Edward.
>
> Christian.
>
>
>>
>> Tom
>> _______________________________________________
>> amd-gfx mailing list
>> amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
>> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
>
>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[-- Attachment #1.2: OpenPGP digital signature --]
[-- Type: application/pgp-signature, Size: 819 bytes --]
[-- Attachment #2: Type: text/plain, Size: 154 bytes --]
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH 000/100] Add Vega10 Support
[not found] ` <37027c02-1f10-858e-ca22-a6fc7cad330a-dczkZgxz+BNUPWh3PAxdjQ@public.gmane.org>
@ 2017-03-21 9:01 ` Christian König
[not found] ` <94df79ba-c393-71a8-a825-7ab14f39a967-5C7GfCeVMHo@public.gmane.org>
2017-03-21 12:12 ` Marek Olšák
1 sibling, 1 reply; 16+ messages in thread
From: Christian König @ 2017-03-21 9:01 UTC (permalink / raw)
To: Edward O'Callaghan, Tom St Denis,
amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Am 21.03.2017 um 09:45 schrieb Edward O'Callaghan:
>
> On 03/21/2017 05:36 PM, Christian König wrote:
>> Am 21.03.2017 um 00:38 schrieb Tom St Denis:
>>> On 03/20/2017 06:34 PM, Jan Ziak wrote:
>>>> On Mon, Mar 20, 2017 at 10:41 PM, Alex Deucher <alexdeucher@gmail.com
>>>> <mailto:alexdeucher@gmail.com>> wrote:
>>>>
>>>> On Mon, Mar 20, 2017 at 5:36 PM, Jan Ziak <0xe2.0x9a.0x9b@gmail.com
>>>> <mailto:0xe2.0x9a.0x9b@gmail.com>> wrote:
>>>> > Hi
>>>> >
>>>> >
>>>> https://cgit.freedesktop.org/~agd5f/linux/plain/drivers/gpu/drm/amd/include/asic_reg/vega10/NBIO/nbio_6_1_sh_mask.h?h=amd-staging-4.9&id=9555ef0ba926df25d9a637d0ea21bc0d231c21d2
>>>>
>>>> <https://cgit.freedesktop.org/~agd5f/linux/plain/drivers/gpu/drm/amd/include/asic_reg/vega10/NBIO/nbio_6_1_sh_mask.h?h=amd-staging-4.9&id=9555ef0ba926df25d9a637d0ea21bc0d231c21d2>
>>>>
>>>> >
>>>> > The file nbio_6_1_sh_mask.h is uncompressed. It consists from
>>>> 133884 lines.
>>>> > Only generated C/C++ code will be able to utilize the content
>>>> of such a file
>>>> > efficiently. All hand-written codes combined will be able to
>>>> utilize about
>>>> > 1% of the file.
>>>> >
>>>> > Is there a reason why nbio_6_1_sh_mask.h is huge?
>>>>
>>>> That IP block contains a lot of registers. The idea is to open
>>>> source
>>>> as much IP as possible to facilitate debugging, new features, etc.
>>>>
>>>> Alex
>>>>
>>>>
>>>> [This email contains long/wide lines and should be viewed on a
>>>> sufficiently wide screen]
>>>>
>>>> For example if I open the file in vim and go to line 66952:
>>>>
>>>> #define
>>>> DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT
>>>>
>>>> 0x9
>>>>
>>>> Then abstracting away some of the digits used in the defined identifier
>>>> and using egrep:
>>>>
>>>> $ egrep
>>>> "\<DWC_E12MP_PHY_X._NS_X._._LANE._DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_.__DTB_SEL__SHIFT\>"
>>>>
>>>> nbio_6_1_sh_mask.h
>>>> #define
>>>> DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT
>>>>
>>>> 0x9
>>>> #define
>>>> DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT
>>>>
>>>> 0x9
>>>> #define
>>>> DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT
>>>>
>>>> 0x9
>>>> #define
>>>> DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT
>>>>
>>>> 0x9
>>>> #define
>>>> DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT
>>>>
>>>> 0x9
>>>> #define
>>>> DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT
>>>>
>>>> 0x9
>>>> #define
>>>> DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT
>>>>
>>>> 0x9
>>>> #define
>>>> DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT
>>>>
>>>> 0x9
>>>> #define
>>>> DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT
>>>>
>>>> 0x9
>>>> #define
>>>> DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT
>>>>
>>>> 0x9
>>>> #define
>>>> DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT
>>>>
>>>> 0x9
>>>> #define
>>>> DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT
>>>>
>>>> 0x9
>>>> #define
>>>> DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT
>>>>
>>>> 0x9
>>>> #define
>>>> DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT
>>>>
>>>> 0x9
>>>> #define
>>>> DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT
>>>>
>>>> 0x9
>>>> #define
>>>> DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT
>>>>
>>>> 0x9
>>>> #define
>>>> DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT
>>>>
>>>> 0x9
>>>> #define
>>>> DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT
>>>>
>>>> 0x9
>>>> #define
>>>> DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT
>>>>
>>>> 0x9
>>>> #define
>>>> DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1__DTB_SEL__SHIFT
>>>>
>>>> 0x9
>>>>
>>>> The egrep command produced 20 lines.
>>>>
>>>> Instead of the many #define directives, it is a possibility to define
>>>> functions such as:
>>>>
>>>> int
>>>> DWC_E12MP_PHY_Xa_NS_Xb_c_LANEd_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_e__DTB_SEL__SHIFT(int
>>>>
>>>> a, int b, int c, int d, int e) __attribute__((pure));
>>>>
>>>> I suppose the file nbio_6_1_sh_mask.h is the output of a tool (it is a
>>>> generated file). It is an option to modify the tool to output C
>>>> functions with proper input guards instead of #define directives.
>>> The registers are generated by the HW team and then filtered down to
>>> become what we release publicly. It is machine generated very likely
>>> from the RTL that specifies the hardware itself.
>> Yes, exactly that. And it was actually quite some work to get to this
>> point.
>>
>>> Generally speaking if a class of registers share masks/offsets the
>>> lowest (zero'th) is used in programming and offsets are used when
>>> selecting the correct MMIO address to use specific instances.
>> The problem is that the files we get from the HW team describe the
>> register block already broken down to the memory mappings. E.g. when an
>> RTL block is instantiated N times you get N times the same definition.
>>
>>> Having these enumerated though is handy for tools like UMR which would
>>> decode to the correct instance of the register (you could even see
>>> that by watching the logscan via umr). So we make use of them fairly
>>> efficiently. UMR reads the headers to create the arrays of
>>> registers/bitfields which if they were computed at runtime (via helper
>>> functions) would be harder to parse (and could amount to the halting
>>> problem...).
>>>
>>> What is in the NBIO header today is what was IP cleared but in theory
>>> it could be filtered down more simply to reduce the unused LOCs in
>>> future kernels.
>>>
>>> They don't make for good bedtime reading but imho you'd rather have
>>> more headers not less :-)
>> Manually merging that back into single definitions is not really an
>> option, but what we could do is releasing the full blown headers
>> somewhere and only limit what we push into the linux kernel to actually
>> used ones.
> Hi Christian,
>
> I have to say I prefer your idea here and perhaps they could even become
> part of the UMR repo, not sure? May I suggest the reduction to some like
> a `kernel-native-dialect` could be automated with a clang plugin. It
> seems like heaps of work however maybe not really, clang provides a API
> to grammatically do some AST transformers and auto-rewrite large chunks
> of code given some rules.
Using clang sounds like overkill to me, but we could write an
awk/sed/perl script to do the job.
Another problem is that we internally doesn't necessary want this during
bringup, so the question is when to apply it.
> I also agree with Tom, its certainly nice to have them regardless, just
> perhaps the kernel mainline repo is the wrong place for the kitchen sink.
It's not only nice to have, but a must have to publish the headers.
We have put a lot of work into changing the workflow at AMD from
"releasing only what we have to" toward "releasing everything we can".
Loosing that is NOT an option, but I clearly agree that the kernel
mainline repo is not necessary the best place for it.
Using UMR for this is actually a quite nifty idea if you ask me.
Regards,
Christian.
> Just my thoughts,
> Kind Regards,
> Edward.
>
>> Christian.
>>
>>
>>> Tom
>>> _______________________________________________
>>> amd-gfx mailing list
>>> amd-gfx@lists.freedesktop.org
>>> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
>>
>> _______________________________________________
>> amd-gfx mailing list
>> amd-gfx@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH 000/100] Add Vega10 Support
[not found] ` <37027c02-1f10-858e-ca22-a6fc7cad330a-dczkZgxz+BNUPWh3PAxdjQ@public.gmane.org>
2017-03-21 9:01 ` Christian König
@ 2017-03-21 12:12 ` Marek Olšák
1 sibling, 0 replies; 16+ messages in thread
From: Marek Olšák @ 2017-03-21 12:12 UTC (permalink / raw)
To: Edward O'Callaghan
Cc: Tom St Denis, Christian König, amd-gfx mailing list
[-- Attachment #1.1: Type: text/plain, Size: 8997 bytes --]
It would be better to keep the headers as-is, because changing them
wouldn't fix anybody's problems, but it would take time from us that we
don't have.
Marek
On Mar 21, 2017 9:46 AM, "Edward O'Callaghan" <funfunctor-dczkZgxz+BNUPWh3PAxdjQ@public.gmane.org>
wrote:
>
>
> On 03/21/2017 05:36 PM, Christian König wrote:
> > Am 21.03.2017 um 00:38 schrieb Tom St Denis:
> >> On 03/20/2017 06:34 PM, Jan Ziak wrote:
> >>> On Mon, Mar 20, 2017 at 10:41 PM, Alex Deucher <alexdeucher-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org
> >>> <mailto:alexdeucher-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>> wrote:
> >>>
> >>> On Mon, Mar 20, 2017 at 5:36 PM, Jan Ziak <
> 0xe2.0x9a.0x9b-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org
> >>> <mailto:0xe2.0x9a.0x9b-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>> wrote:
> >>> > Hi
> >>> >
> >>> >
> >>> https://cgit.freedesktop.org/~agd5f/linux/plain/drivers/gpu/
> drm/amd/include/asic_reg/vega10/NBIO/nbio_6_1_sh_mask.
> h?h=amd-staging-4.9&id=9555ef0ba926df25d9a637d0ea21bc0d231c21d2
> >>>
> >>> <https://cgit.freedesktop.org/~agd5f/linux/plain/drivers/
> gpu/drm/amd/include/asic_reg/vega10/NBIO/nbio_6_1_sh_mask.
> h?h=amd-staging-4.9&id=9555ef0ba926df25d9a637d0ea21bc0d231c21d2>
> >>>
> >>> >
> >>> > The file nbio_6_1_sh_mask.h is uncompressed. It consists from
> >>> 133884 lines.
> >>> > Only generated C/C++ code will be able to utilize the content
> >>> of such a file
> >>> > efficiently. All hand-written codes combined will be able to
> >>> utilize about
> >>> > 1% of the file.
> >>> >
> >>> > Is there a reason why nbio_6_1_sh_mask.h is huge?
> >>>
> >>> That IP block contains a lot of registers. The idea is to open
> >>> source
> >>> as much IP as possible to facilitate debugging, new features, etc.
> >>>
> >>> Alex
> >>>
> >>>
> >>> [This email contains long/wide lines and should be viewed on a
> >>> sufficiently wide screen]
> >>>
> >>> For example if I open the file in vim and go to line 66952:
> >>>
> >>> #define
> >>> DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_
> CAL_CTRL_1__DTB_SEL__SHIFT
> >>>
> >>> 0x9
> >>>
> >>> Then abstracting away some of the digits used in the defined identifier
> >>> and using egrep:
> >>>
> >>> $ egrep
> >>> "\<DWC_E12MP_PHY_X._NS_X._._LANE._DIG_RX_VCOCAL_RX_VCO_
> CAL_CTRL_.__DTB_SEL__SHIFT\>"
> >>>
> >>> nbio_6_1_sh_mask.h
> >>> #define
> >>> DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_
> CAL_CTRL_1__DTB_SEL__SHIFT
> >>>
> >>> 0x9
> >>> #define
> >>> DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_
> CAL_CTRL_1__DTB_SEL__SHIFT
> >>>
> >>> 0x9
> >>> #define
> >>> DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_
> CAL_CTRL_1__DTB_SEL__SHIFT
> >>>
> >>> 0x9
> >>> #define
> >>> DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_
> CAL_CTRL_1__DTB_SEL__SHIFT
> >>>
> >>> 0x9
> >>> #define
> >>> DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_
> CAL_CTRL_1__DTB_SEL__SHIFT
> >>>
> >>> 0x9
> >>> #define
> >>> DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_
> CAL_CTRL_1__DTB_SEL__SHIFT
> >>>
> >>> 0x9
> >>> #define
> >>> DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_
> CAL_CTRL_1__DTB_SEL__SHIFT
> >>>
> >>> 0x9
> >>> #define
> >>> DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_
> CAL_CTRL_1__DTB_SEL__SHIFT
> >>>
> >>> 0x9
> >>> #define
> >>> DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_
> CAL_CTRL_1__DTB_SEL__SHIFT
> >>>
> >>> 0x9
> >>> #define
> >>> DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_
> CAL_CTRL_1__DTB_SEL__SHIFT
> >>>
> >>> 0x9
> >>> #define
> >>> DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_
> CAL_CTRL_1__DTB_SEL__SHIFT
> >>>
> >>> 0x9
> >>> #define
> >>> DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_
> CAL_CTRL_1__DTB_SEL__SHIFT
> >>>
> >>> 0x9
> >>> #define
> >>> DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_
> CAL_CTRL_1__DTB_SEL__SHIFT
> >>>
> >>> 0x9
> >>> #define
> >>> DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_
> CAL_CTRL_1__DTB_SEL__SHIFT
> >>>
> >>> 0x9
> >>> #define
> >>> DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_
> CAL_CTRL_1__DTB_SEL__SHIFT
> >>>
> >>> 0x9
> >>> #define
> >>> DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_
> CAL_CTRL_1__DTB_SEL__SHIFT
> >>>
> >>> 0x9
> >>> #define
> >>> DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_
> CAL_CTRL_1__DTB_SEL__SHIFT
> >>>
> >>> 0x9
> >>> #define
> >>> DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_
> CAL_CTRL_1__DTB_SEL__SHIFT
> >>>
> >>> 0x9
> >>> #define
> >>> DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_
> CAL_CTRL_1__DTB_SEL__SHIFT
> >>>
> >>> 0x9
> >>> #define
> >>> DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_
> CAL_CTRL_1__DTB_SEL__SHIFT
> >>>
> >>> 0x9
> >>>
> >>> The egrep command produced 20 lines.
> >>>
> >>> Instead of the many #define directives, it is a possibility to define
> >>> functions such as:
> >>>
> >>> int
> >>> DWC_E12MP_PHY_Xa_NS_Xb_c_LANEd_DIG_RX_VCOCAL_RX_VCO_
> CAL_CTRL_e__DTB_SEL__SHIFT(int
> >>>
> >>> a, int b, int c, int d, int e) __attribute__((pure));
> >>>
> >>> I suppose the file nbio_6_1_sh_mask.h is the output of a tool (it is a
> >>> generated file). It is an option to modify the tool to output C
> >>> functions with proper input guards instead of #define directives.
> >>
> >> The registers are generated by the HW team and then filtered down to
> >> become what we release publicly. It is machine generated very likely
> >> from the RTL that specifies the hardware itself.
> >
> > Yes, exactly that. And it was actually quite some work to get to this
> > point.
> >
> >> Generally speaking if a class of registers share masks/offsets the
> >> lowest (zero'th) is used in programming and offsets are used when
> >> selecting the correct MMIO address to use specific instances.
> >
> > The problem is that the files we get from the HW team describe the
> > register block already broken down to the memory mappings. E.g. when an
> > RTL block is instantiated N times you get N times the same definition.
> >
> >>
> >> Having these enumerated though is handy for tools like UMR which would
> >> decode to the correct instance of the register (you could even see
> >> that by watching the logscan via umr). So we make use of them fairly
> >> efficiently. UMR reads the headers to create the arrays of
> >> registers/bitfields which if they were computed at runtime (via helper
> >> functions) would be harder to parse (and could amount to the halting
> >> problem...).
> >>
> >> What is in the NBIO header today is what was IP cleared but in theory
> >> it could be filtered down more simply to reduce the unused LOCs in
> >> future kernels.
> >>
> >> They don't make for good bedtime reading but imho you'd rather have
> >> more headers not less :-)
> >
> > Manually merging that back into single definitions is not really an
> > option, but what we could do is releasing the full blown headers
> > somewhere and only limit what we push into the linux kernel to actually
> > used ones.
>
> Hi Christian,
>
> I have to say I prefer your idea here and perhaps they could even become
> part of the UMR repo, not sure? May I suggest the reduction to some like
> a `kernel-native-dialect` could be automated with a clang plugin. It
> seems like heaps of work however maybe not really, clang provides a API
> to grammatically do some AST transformers and auto-rewrite large chunks
> of code given some rules.
>
> I also agree with Tom, its certainly nice to have them regardless, just
> perhaps the kernel mainline repo is the wrong place for the kitchen sink.
>
> Just my thoughts,
> Kind Regards,
> Edward.
>
> >
> > Christian.
> >
> >
> >>
> >> Tom
> >> _______________________________________________
> >> amd-gfx mailing list
> >> amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
> >> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
> >
> >
> > _______________________________________________
> > amd-gfx mailing list
> > amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
> > https://lists.freedesktop.org/mailman/listinfo/amd-gfx
>
>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
>
>
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[-- Attachment #2: Type: text/plain, Size: 154 bytes --]
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 16+ messages in thread
* RE: [PATCH 000/100] Add Vega10 Support
[not found] ` <94df79ba-c393-71a8-a825-7ab14f39a967-5C7GfCeVMHo@public.gmane.org>
@ 2017-03-21 15:14 ` Deucher, Alexander
[not found] ` <BN6PR12MB16526C8CA934A46308790AC0F73D0-/b2+HYfkarQqUD6E6FAiowdYzm3356FpvxpqHgZTriW3zl9H0oFU5g@public.gmane.org>
0 siblings, 1 reply; 16+ messages in thread
From: Deucher, Alexander @ 2017-03-21 15:14 UTC (permalink / raw)
To: Koenig, Christian, Edward O'Callaghan, StDenis, Tom,
amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
> -----Original Message-----
> From: amd-gfx [mailto:amd-gfx-bounces@lists.freedesktop.org] On Behalf
> Of Christian König
> Sent: Tuesday, March 21, 2017 5:01 AM
> To: Edward O'Callaghan; StDenis, Tom; amd-gfx@lists.freedesktop.org
> Subject: Re: [PATCH 000/100] Add Vega10 Support
>
> Am 21.03.2017 um 09:45 schrieb Edward O'Callaghan:
> >
> > On 03/21/2017 05:36 PM, Christian König wrote:
> >> Am 21.03.2017 um 00:38 schrieb Tom St Denis:
> >>> On 03/20/2017 06:34 PM, Jan Ziak wrote:
> >>>> On Mon, Mar 20, 2017 at 10:41 PM, Alex Deucher
> <alexdeucher@gmail.com
> >>>> <mailto:alexdeucher@gmail.com>> wrote:
> >>>>
> >>>> On Mon, Mar 20, 2017 at 5:36 PM, Jan Ziak
> <0xe2.0x9a.0x9b@gmail.com
> >>>> <mailto:0xe2.0x9a.0x9b@gmail.com>> wrote:
> >>>> > Hi
> >>>> >
> >>>> >
> >>>>
> https://cgit.freedesktop.org/~agd5f/linux/plain/drivers/gpu/drm/amd/inclu
> de/asic_reg/vega10/NBIO/nbio_6_1_sh_mask.h?h=amd-staging-
> 4.9&id=9555ef0ba926df25d9a637d0ea21bc0d231c21d2
> >>>>
> >>>>
> <https://cgit.freedesktop.org/~agd5f/linux/plain/drivers/gpu/drm/amd/incl
> ude/asic_reg/vega10/NBIO/nbio_6_1_sh_mask.h?h=amd-staging-
> 4.9&id=9555ef0ba926df25d9a637d0ea21bc0d231c21d2>
> >>>>
> >>>> >
> >>>> > The file nbio_6_1_sh_mask.h is uncompressed. It consists from
> >>>> 133884 lines.
> >>>> > Only generated C/C++ code will be able to utilize the content
> >>>> of such a file
> >>>> > efficiently. All hand-written codes combined will be able to
> >>>> utilize about
> >>>> > 1% of the file.
> >>>> >
> >>>> > Is there a reason why nbio_6_1_sh_mask.h is huge?
> >>>>
> >>>> That IP block contains a lot of registers. The idea is to open
> >>>> source
> >>>> as much IP as possible to facilitate debugging, new features, etc.
> >>>>
> >>>> Alex
> >>>>
> >>>>
> >>>> [This email contains long/wide lines and should be viewed on a
> >>>> sufficiently wide screen]
> >>>>
> >>>> For example if I open the file in vim and go to line 66952:
> >>>>
> >>>> #define
> >>>>
> DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_C
> TRL_1__DTB_SEL__SHIFT
> >>>>
> >>>> 0x9
> >>>>
> >>>> Then abstracting away some of the digits used in the defined identifier
> >>>> and using egrep:
> >>>>
> >>>> $ egrep
> >>>>
> "\<DWC_E12MP_PHY_X._NS_X._._LANE._DIG_RX_VCOCAL_RX_VCO_CAL_
> CTRL_.__DTB_SEL__SHIFT\>"
> >>>>
> >>>> nbio_6_1_sh_mask.h
> >>>> #define
> >>>>
> DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_C
> TRL_1__DTB_SEL__SHIFT
> >>>>
> >>>> 0x9
> >>>> #define
> >>>>
> DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_C
> TRL_1__DTB_SEL__SHIFT
> >>>>
> >>>> 0x9
> >>>> #define
> >>>>
> DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_C
> TRL_1__DTB_SEL__SHIFT
> >>>>
> >>>> 0x9
> >>>> #define
> >>>>
> DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_C
> TRL_1__DTB_SEL__SHIFT
> >>>>
> >>>> 0x9
> >>>> #define
> >>>>
> DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_C
> TRL_1__DTB_SEL__SHIFT
> >>>>
> >>>> 0x9
> >>>> #define
> >>>>
> DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_C
> TRL_1__DTB_SEL__SHIFT
> >>>>
> >>>> 0x9
> >>>> #define
> >>>>
> DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_C
> TRL_1__DTB_SEL__SHIFT
> >>>>
> >>>> 0x9
> >>>> #define
> >>>>
> DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_C
> TRL_1__DTB_SEL__SHIFT
> >>>>
> >>>> 0x9
> >>>> #define
> >>>>
> DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_C
> TRL_1__DTB_SEL__SHIFT
> >>>>
> >>>> 0x9
> >>>> #define
> >>>>
> DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_C
> TRL_1__DTB_SEL__SHIFT
> >>>>
> >>>> 0x9
> >>>> #define
> >>>>
> DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_C
> TRL_1__DTB_SEL__SHIFT
> >>>>
> >>>> 0x9
> >>>> #define
> >>>>
> DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_C
> TRL_1__DTB_SEL__SHIFT
> >>>>
> >>>> 0x9
> >>>> #define
> >>>>
> DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_C
> TRL_1__DTB_SEL__SHIFT
> >>>>
> >>>> 0x9
> >>>> #define
> >>>>
> DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_C
> TRL_1__DTB_SEL__SHIFT
> >>>>
> >>>> 0x9
> >>>> #define
> >>>>
> DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_C
> TRL_1__DTB_SEL__SHIFT
> >>>>
> >>>> 0x9
> >>>> #define
> >>>>
> DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_C
> TRL_1__DTB_SEL__SHIFT
> >>>>
> >>>> 0x9
> >>>> #define
> >>>>
> DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_C
> TRL_1__DTB_SEL__SHIFT
> >>>>
> >>>> 0x9
> >>>> #define
> >>>>
> DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_C
> TRL_1__DTB_SEL__SHIFT
> >>>>
> >>>> 0x9
> >>>> #define
> >>>>
> DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_C
> TRL_1__DTB_SEL__SHIFT
> >>>>
> >>>> 0x9
> >>>> #define
> >>>>
> DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_C
> TRL_1__DTB_SEL__SHIFT
> >>>>
> >>>> 0x9
> >>>>
> >>>> The egrep command produced 20 lines.
> >>>>
> >>>> Instead of the many #define directives, it is a possibility to define
> >>>> functions such as:
> >>>>
> >>>> int
> >>>>
> DWC_E12MP_PHY_Xa_NS_Xb_c_LANEd_DIG_RX_VCOCAL_RX_VCO_CAL_C
> TRL_e__DTB_SEL__SHIFT(int
> >>>>
> >>>> a, int b, int c, int d, int e) __attribute__((pure));
> >>>>
> >>>> I suppose the file nbio_6_1_sh_mask.h is the output of a tool (it is a
> >>>> generated file). It is an option to modify the tool to output C
> >>>> functions with proper input guards instead of #define directives.
> >>> The registers are generated by the HW team and then filtered down to
> >>> become what we release publicly. It is machine generated very likely
> >>> from the RTL that specifies the hardware itself.
> >> Yes, exactly that. And it was actually quite some work to get to this
> >> point.
> >>
> >>> Generally speaking if a class of registers share masks/offsets the
> >>> lowest (zero'th) is used in programming and offsets are used when
> >>> selecting the correct MMIO address to use specific instances.
> >> The problem is that the files we get from the HW team describe the
> >> register block already broken down to the memory mappings. E.g. when
> an
> >> RTL block is instantiated N times you get N times the same definition.
> >>
> >>> Having these enumerated though is handy for tools like UMR which
> would
> >>> decode to the correct instance of the register (you could even see
> >>> that by watching the logscan via umr). So we make use of them fairly
> >>> efficiently. UMR reads the headers to create the arrays of
> >>> registers/bitfields which if they were computed at runtime (via helper
> >>> functions) would be harder to parse (and could amount to the halting
> >>> problem...).
> >>>
> >>> What is in the NBIO header today is what was IP cleared but in theory
> >>> it could be filtered down more simply to reduce the unused LOCs in
> >>> future kernels.
> >>>
> >>> They don't make for good bedtime reading but imho you'd rather have
> >>> more headers not less :-)
> >> Manually merging that back into single definitions is not really an
> >> option, but what we could do is releasing the full blown headers
> >> somewhere and only limit what we push into the linux kernel to actually
> >> used ones.
> > Hi Christian,
> >
> > I have to say I prefer your idea here and perhaps they could even become
> > part of the UMR repo, not sure? May I suggest the reduction to some like
> > a `kernel-native-dialect` could be automated with a clang plugin. It
> > seems like heaps of work however maybe not really, clang provides a API
> > to grammatically do some AST transformers and auto-rewrite large chunks
> > of code given some rules.
>
> Using clang sounds like overkill to me, but we could write an
> awk/sed/perl script to do the job.
>
> Another problem is that we internally doesn't necessary want this during
> bringup, so the question is when to apply it.
>
> > I also agree with Tom, its certainly nice to have them regardless, just
> > perhaps the kernel mainline repo is the wrong place for the kitchen sink.
>
> It's not only nice to have, but a must have to publish the headers.
>
> We have put a lot of work into changing the workflow at AMD from
> "releasing only what we have to" toward "releasing everything we can".
>
> Loosing that is NOT an option, but I clearly agree that the kernel
> mainline repo is not necessary the best place for it.
One advantage to having it in the kernel, is that for debugging you don’t have to worry about adding a bunch of register defines if you need to print some registers or hack in a quick test. Another advantage is that when it comes to new developers working on the code, if a register define is not there, that is a good signal that the register is restricted for some reason and the patch needs further internal review and approval before release because it exposes new IP. If the headers are there, if the code compiles, it's safe from an IP perspective. It's also nice to have a unified source for the hardware and how to program it.
Alex
>
> Using UMR for this is actually a quite nifty idea if you ask me.
>
> Regards,
> Christian.
>
> > Just my thoughts,
> > Kind Regards,
> > Edward.
> >
> >> Christian.
> >>
> >>
> >>> Tom
> >>> _______________________________________________
> >>> amd-gfx mailing list
> >>> amd-gfx@lists.freedesktop.org
> >>> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
> >>
> >> _______________________________________________
> >> amd-gfx mailing list
> >> amd-gfx@lists.freedesktop.org
> >> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
>
>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH 000/100] Add Vega10 Support
[not found] ` <BN6PR12MB16526C8CA934A46308790AC0F73D0-/b2+HYfkarQqUD6E6FAiowdYzm3356FpvxpqHgZTriW3zl9H0oFU5g@public.gmane.org>
@ 2017-03-21 19:43 ` Andres Rodriguez
0 siblings, 0 replies; 16+ messages in thread
From: Andres Rodriguez @ 2017-03-21 19:43 UTC (permalink / raw)
To: Deucher, Alexander, Koenig, Christian, Edward O'Callaghan,
StDenis, Tom, amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
On 2017-03-21 11:14 AM, Deucher, Alexander wrote:
>> -----Original Message-----
>> From: amd-gfx [mailto:amd-gfx-bounces@lists.freedesktop.org] On Behalf
>> Of Christian König
>> Sent: Tuesday, March 21, 2017 5:01 AM
>> To: Edward O'Callaghan; StDenis, Tom; amd-gfx@lists.freedesktop.org
>> Subject: Re: [PATCH 000/100] Add Vega10 Support
>>
>> Am 21.03.2017 um 09:45 schrieb Edward O'Callaghan:
>>>
>>> On 03/21/2017 05:36 PM, Christian König wrote:
>>>> Am 21.03.2017 um 00:38 schrieb Tom St Denis:
>>>>> On 03/20/2017 06:34 PM, Jan Ziak wrote:
>>>>>> On Mon, Mar 20, 2017 at 10:41 PM, Alex Deucher
>> <alexdeucher@gmail.com
>>>>>> <mailto:alexdeucher@gmail.com>> wrote:
>>>>>>
>>>>>> On Mon, Mar 20, 2017 at 5:36 PM, Jan Ziak
>> <0xe2.0x9a.0x9b@gmail.com
>>>>>> <mailto:0xe2.0x9a.0x9b@gmail.com>> wrote:
>>>>>> > Hi
>>>>>> >
>>>>>> >
>>>>>>
>> https://cgit.freedesktop.org/~agd5f/linux/plain/drivers/gpu/drm/amd/inclu
>> de/asic_reg/vega10/NBIO/nbio_6_1_sh_mask.h?h=amd-staging-
>> 4.9&id=9555ef0ba926df25d9a637d0ea21bc0d231c21d2
>>>>>>
>>>>>>
>> <https://cgit.freedesktop.org/~agd5f/linux/plain/drivers/gpu/drm/amd/incl
>> ude/asic_reg/vega10/NBIO/nbio_6_1_sh_mask.h?h=amd-staging-
>> 4.9&id=9555ef0ba926df25d9a637d0ea21bc0d231c21d2>
>>>>>>
>>>>>> >
>>>>>> > The file nbio_6_1_sh_mask.h is uncompressed. It consists from
>>>>>> 133884 lines.
>>>>>> > Only generated C/C++ code will be able to utilize the content
>>>>>> of such a file
>>>>>> > efficiently. All hand-written codes combined will be able to
>>>>>> utilize about
>>>>>> > 1% of the file.
>>>>>> >
>>>>>> > Is there a reason why nbio_6_1_sh_mask.h is huge?
>>>>>>
>>>>>> That IP block contains a lot of registers. The idea is to open
>>>>>> source
>>>>>> as much IP as possible to facilitate debugging, new features, etc.
>>>>>>
>>>>>> Alex
>>>>>>
>>>>>>
>>>>>> [This email contains long/wide lines and should be viewed on a
>>>>>> sufficiently wide screen]
>>>>>>
>>>>>> For example if I open the file in vim and go to line 66952:
>>>>>>
>>>>>> #define
>>>>>>
>> DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_C
>> TRL_1__DTB_SEL__SHIFT
>>>>>>
>>>>>> 0x9
>>>>>>
>>>>>> Then abstracting away some of the digits used in the defined identifier
>>>>>> and using egrep:
>>>>>>
>>>>>> $ egrep
>>>>>>
>> "\<DWC_E12MP_PHY_X._NS_X._._LANE._DIG_RX_VCOCAL_RX_VCO_CAL_
>> CTRL_.__DTB_SEL__SHIFT\>"
>>>>>>
>>>>>> nbio_6_1_sh_mask.h
>>>>>> #define
>>>>>>
>> DWC_E12MP_PHY_X4_NS_X4_0_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_C
>> TRL_1__DTB_SEL__SHIFT
>>>>>>
>>>>>> 0x9
>>>>>> #define
>>>>>>
>> DWC_E12MP_PHY_X4_NS_X4_0_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_C
>> TRL_1__DTB_SEL__SHIFT
>>>>>>
>>>>>> 0x9
>>>>>> #define
>>>>>>
>> DWC_E12MP_PHY_X4_NS_X4_0_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_C
>> TRL_1__DTB_SEL__SHIFT
>>>>>>
>>>>>> 0x9
>>>>>> #define
>>>>>>
>> DWC_E12MP_PHY_X4_NS_X4_0_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_C
>> TRL_1__DTB_SEL__SHIFT
>>>>>>
>>>>>> 0x9
>>>>>> #define
>>>>>>
>> DWC_E12MP_PHY_X4_NS_X4_0_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_C
>> TRL_1__DTB_SEL__SHIFT
>>>>>>
>>>>>> 0x9
>>>>>> #define
>>>>>>
>> DWC_E12MP_PHY_X4_NS_X4_1_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_C
>> TRL_1__DTB_SEL__SHIFT
>>>>>>
>>>>>> 0x9
>>>>>> #define
>>>>>>
>> DWC_E12MP_PHY_X4_NS_X4_1_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_C
>> TRL_1__DTB_SEL__SHIFT
>>>>>>
>>>>>> 0x9
>>>>>> #define
>>>>>>
>> DWC_E12MP_PHY_X4_NS_X4_1_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_C
>> TRL_1__DTB_SEL__SHIFT
>>>>>>
>>>>>> 0x9
>>>>>> #define
>>>>>>
>> DWC_E12MP_PHY_X4_NS_X4_1_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_C
>> TRL_1__DTB_SEL__SHIFT
>>>>>>
>>>>>> 0x9
>>>>>> #define
>>>>>>
>> DWC_E12MP_PHY_X4_NS_X4_1_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_C
>> TRL_1__DTB_SEL__SHIFT
>>>>>>
>>>>>> 0x9
>>>>>> #define
>>>>>>
>> DWC_E12MP_PHY_X4_NS_X4_2_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_C
>> TRL_1__DTB_SEL__SHIFT
>>>>>>
>>>>>> 0x9
>>>>>> #define
>>>>>>
>> DWC_E12MP_PHY_X4_NS_X4_2_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_C
>> TRL_1__DTB_SEL__SHIFT
>>>>>>
>>>>>> 0x9
>>>>>> #define
>>>>>>
>> DWC_E12MP_PHY_X4_NS_X4_2_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_C
>> TRL_1__DTB_SEL__SHIFT
>>>>>>
>>>>>> 0x9
>>>>>> #define
>>>>>>
>> DWC_E12MP_PHY_X4_NS_X4_2_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_C
>> TRL_1__DTB_SEL__SHIFT
>>>>>>
>>>>>> 0x9
>>>>>> #define
>>>>>>
>> DWC_E12MP_PHY_X4_NS_X4_2_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_C
>> TRL_1__DTB_SEL__SHIFT
>>>>>>
>>>>>> 0x9
>>>>>> #define
>>>>>>
>> DWC_E12MP_PHY_X4_NS_X4_3_LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_C
>> TRL_1__DTB_SEL__SHIFT
>>>>>>
>>>>>> 0x9
>>>>>> #define
>>>>>>
>> DWC_E12MP_PHY_X4_NS_X4_3_LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_C
>> TRL_1__DTB_SEL__SHIFT
>>>>>>
>>>>>> 0x9
>>>>>> #define
>>>>>>
>> DWC_E12MP_PHY_X4_NS_X4_3_LANE2_DIG_RX_VCOCAL_RX_VCO_CAL_C
>> TRL_1__DTB_SEL__SHIFT
>>>>>>
>>>>>> 0x9
>>>>>> #define
>>>>>>
>> DWC_E12MP_PHY_X4_NS_X4_3_LANE3_DIG_RX_VCOCAL_RX_VCO_CAL_C
>> TRL_1__DTB_SEL__SHIFT
>>>>>>
>>>>>> 0x9
>>>>>> #define
>>>>>>
>> DWC_E12MP_PHY_X4_NS_X4_3_LANEX_DIG_RX_VCOCAL_RX_VCO_CAL_C
>> TRL_1__DTB_SEL__SHIFT
>>>>>>
>>>>>> 0x9
>>>>>>
>>>>>> The egrep command produced 20 lines.
>>>>>>
>>>>>> Instead of the many #define directives, it is a possibility to define
>>>>>> functions such as:
>>>>>>
>>>>>> int
>>>>>>
>> DWC_E12MP_PHY_Xa_NS_Xb_c_LANEd_DIG_RX_VCOCAL_RX_VCO_CAL_C
>> TRL_e__DTB_SEL__SHIFT(int
>>>>>>
>>>>>> a, int b, int c, int d, int e) __attribute__((pure));
>>>>>>
>>>>>> I suppose the file nbio_6_1_sh_mask.h is the output of a tool (it is a
>>>>>> generated file). It is an option to modify the tool to output C
>>>>>> functions with proper input guards instead of #define directives.
>>>>> The registers are generated by the HW team and then filtered down to
>>>>> become what we release publicly. It is machine generated very likely
>>>>> from the RTL that specifies the hardware itself.
>>>> Yes, exactly that. And it was actually quite some work to get to this
>>>> point.
>>>>
>>>>> Generally speaking if a class of registers share masks/offsets the
>>>>> lowest (zero'th) is used in programming and offsets are used when
>>>>> selecting the correct MMIO address to use specific instances.
>>>> The problem is that the files we get from the HW team describe the
>>>> register block already broken down to the memory mappings. E.g. when
>> an
>>>> RTL block is instantiated N times you get N times the same definition.
>>>>
>>>>> Having these enumerated though is handy for tools like UMR which
>> would
>>>>> decode to the correct instance of the register (you could even see
>>>>> that by watching the logscan via umr). So we make use of them fairly
>>>>> efficiently. UMR reads the headers to create the arrays of
>>>>> registers/bitfields which if they were computed at runtime (via helper
>>>>> functions) would be harder to parse (and could amount to the halting
>>>>> problem...).
>>>>>
>>>>> What is in the NBIO header today is what was IP cleared but in theory
>>>>> it could be filtered down more simply to reduce the unused LOCs in
>>>>> future kernels.
>>>>>
>>>>> They don't make for good bedtime reading but imho you'd rather have
>>>>> more headers not less :-)
>>>> Manually merging that back into single definitions is not really an
>>>> option, but what we could do is releasing the full blown headers
>>>> somewhere and only limit what we push into the linux kernel to actually
>>>> used ones.
>>> Hi Christian,
>>>
>>> I have to say I prefer your idea here and perhaps they could even become
>>> part of the UMR repo, not sure? May I suggest the reduction to some like
>>> a `kernel-native-dialect` could be automated with a clang plugin. It
>>> seems like heaps of work however maybe not really, clang provides a API
>>> to grammatically do some AST transformers and auto-rewrite large chunks
>>> of code given some rules.
>>
>> Using clang sounds like overkill to me, but we could write an
>> awk/sed/perl script to do the job.
>>
>> Another problem is that we internally doesn't necessary want this during
>> bringup, so the question is when to apply it.
>>
>>> I also agree with Tom, its certainly nice to have them regardless, just
>>> perhaps the kernel mainline repo is the wrong place for the kitchen sink.
>>
>> It's not only nice to have, but a must have to publish the headers.
>>
>> We have put a lot of work into changing the workflow at AMD from
>> "releasing only what we have to" toward "releasing everything we can".
>>
>> Loosing that is NOT an option, but I clearly agree that the kernel
>> mainline repo is not necessary the best place for it.
>
> One advantage to having it in the kernel, is that for debugging you don’t have to worry about adding a bunch of register defines if you need to print some registers or hack in a quick test. Another advantage is that when it comes to new developers working on the code, if a register define is not there, that is a good signal that the register is restricted for some reason and the patch needs further internal review and approval before release because it exposes new IP. If the headers are there, if the code compiles, it's safe from an IP perspective. It's also nice to have a unified source for the hardware and how to program it.
>
> Alex
>
>
I agree completely here. The register headers also function as the best
document of how the HW is supposed to behave.
I don't really see any advantage to splitting this into a separate
repository. As far as I can see, it would create a lot of extra busywork
with moving things from one place to another, in exchange of a few MB of
space. That is not a good trade-off.
One of the nicest things that the AMD team has been able to accomplish
in recent years is getting more and more of their registers open
publicly. I think moving them to a different repository would be a step
backwards.
Regards,
Andres
>>
>> Using UMR for this is actually a quite nifty idea if you ask me.
>>
>> Regards,
>> Christian.
>>
>>> Just my thoughts,
>>> Kind Regards,
>>> Edward.
>>>
>>>> Christian.
>>>>
>>>>
>>>>> Tom
>>>>> _______________________________________________
>>>>> amd-gfx mailing list
>>>>> amd-gfx@lists.freedesktop.org
>>>>> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
>>>>
>>>> _______________________________________________
>>>> amd-gfx mailing list
>>>> amd-gfx@lists.freedesktop.org
>>>> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
>>
>>
>> _______________________________________________
>> amd-gfx mailing list
>> amd-gfx@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
>
_______________________________________________
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^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH 000/100] Add Vega10 Support
[not found] ` <50d03274-5a6e-fb77-9741-b6700a9949bd-ANTagKRnAhcb1SvskN2V4Q@public.gmane.org>
2017-03-21 11:51 ` Christian König
@ 2017-03-21 22:00 ` Alex Deucher
1 sibling, 0 replies; 16+ messages in thread
From: Alex Deucher @ 2017-03-21 22:00 UTC (permalink / raw)
To: Christian König; +Cc: Alex Deucher, amd-gfx list
On Tue, Mar 21, 2017 at 3:42 AM, Christian König
<deathsimple@vodafone.de> wrote:
> Patches #1 - #5, #21, #23, #25, #27, #28, #31, #35-#38, #40, #41, #45 are
> Acked-by: Christian König.
>
> Patches #6-#20, #22, #24, #32, #39, #42 didn't made it to the list (probably
> to large).
>
> Patches #43, #44 are Reviewed-by: Christian König
> <christian.koenig@amd.com>.
>
> Patch #26: That stuff actually belongs into vega10 specifc code, doesn't it?
It's common to all soc15 parts for the foreseeable future.
>
> Patch #29: We shouldn't use typedefs for enums.
The existing doorbell assignments use a typedef as well. Should
probably fix both up.
>
> Going to take a look at the rest later today,
> Christian.
>
>
> Am 20.03.2017 um 21:29 schrieb Alex Deucher:
>>
>> This patch set adds support for vega10. Major changes and supported
>> features:
>> - new vbios interface
>> - Lots of new hw IPs
>> - Support for video decode using UVD
>> - Support for video encode using VCE
>> - Support for 3D via radeonsi
>> - Power management
>> - Full display support via DC
>> - Support for SR-IOV
>>
>> I did not send out the register headers since they are huge. You can find
>> them
>> along with all the other patches in this series here:
>> https://cgit.freedesktop.org/~agd5f/linux/log/?h=amd-staging-4.9
>>
>> Please review.
>>
>> Thanks,
>>
>> Alex
>>
>> Alex Deucher (29):
>> drm/amdgpu: add the new atomfirmware interface header
>> amdgpu: detect if we are using atomfirm or atombios for vbios (v2)
>> drm/amdgpu: move atom scratch setup into amdgpu_atombios.c
>> drm/amdgpu: add basic support for atomfirmware.h (v3)
>> drm/amdgpu: add soc15ip.h
>> drm/amdgpu: add vega10_enum.h
>> drm/amdgpu: Add ATHUB 1.0 register headers
>> drm/amdgpu: Add the DCE 12.0 register headers
>> drm/amdgpu: add the GC 9.0 register headers
>> drm/amdgpu: add the HDP 4.0 register headers
>> drm/amdgpu: add the MMHUB 1.0 register headers
>> drm/amdgpu: add MP 9.0 register headers
>> drm/amdgpu: add NBIF 6.1 register headers
>> drm/amdgpu: add NBIO 6.1 register headers
>> drm/amdgpu: add OSSSYS 4.0 register headers
>> drm/amdgpu: add SDMA 4.0 register headers
>> drm/amdgpu: add SMUIO 9.0 register headers
>> drm/amdgpu: add THM 9.0 register headers
>> drm/amdgpu: add the UVD 7.0 register headers
>> drm/amdgpu: add the VCE 4.0 register headers
>> drm/amdgpu: add gfx9 clearstate header
>> drm/amdgpu: add SDMA 4.0 packet header
>> drm/amdgpu: use atomfirmware interfaces for scratch reg save/restore
>> drm/amdgpu: update IH IV ring entry for soc-15
>> drm/amdgpu: add PTE defines for MTYPE
>> drm/amdgpu: add NGG parameters
>> drm/amdgpu: Add asic family for vega10
>> drm/amdgpu: add tiling flags for GFX9
>> drm/amdgpu: gart fixes for vega10
>>
>> Alex Xie (4):
>> drm/amdgpu: Add MTYPE flags to GPU VM IOCTL interface
>> drm/amdgpu: handle PTE EXEC in amdgpu_vm_bo_split_mapping
>> drm/amdgpu: handle PTE MTYPE in amdgpu_vm_bo_split_mapping
>> drm/amdgpu: Add GMC 9.0 support
>>
>> Andrey Grodzovsky (1):
>> drm/amdgpu: gb_addr_config struct
>>
>> Charlene Liu (1):
>> drm/amd/display: need to handle DCE_Info table ver4.2
>>
>> Christian König (1):
>> drm/amdgpu: add IV trace point
>>
>> Eric Huang (7):
>> drm/amd/powerplay: add smu9 header files for Vega10
>> drm/amd/powerplay: add new Vega10's ppsmc header file
>> drm/amdgpu: add new atomfirmware based helpers for powerplay
>> drm/amd/powerplay: add some new structures for Vega10
>> drm/amd: add structures for display/powerplay interface
>> drm/amd/powerplay: add some display/powerplay interfaces
>> drm/amd/powerplay: add Vega10 powerplay support
>>
>> Felix Kuehling (1):
>> drm/amd: Add MQD structs for GFX V9
>>
>> Harry Wentland (6):
>> drm/amd/display: Add DCE12 bios parser support
>> drm/amd/display: Add DCE12 gpio support
>> drm/amd/display: Add DCE12 i2c/aux support
>> drm/amd/display: Add DCE12 irq support
>> drm/amd/display: Add DCE12 core support
>> drm/amd/display: Enable DCE12 support
>>
>> Huang Rui (6):
>> drm/amdgpu: use new flag to handle different firmware loading method
>> drm/amdgpu: rework common ucode handling for vega10
>> drm/amdgpu: add psp firmware header info
>> drm/amdgpu: add PSP driver for vega10
>> drm/amdgpu: add psp firmware info into info query and debugfs
>> drm/amdgpu: add SMC firmware into global ucode list for psp loading
>>
>> Jordan Lazare (1):
>> drm/amd/display: Less log spam
>>
>> Junwei Zhang (2):
>> drm/amdgpu: add NBIO 6.1 driver
>> drm/amdgpu: add Vega10 Device IDs
>>
>> Ken Wang (8):
>> drm/amdgpu: add common soc15 headers
>> drm/amdgpu: add vega10 chip name
>> drm/amdgpu: add 64bit doorbell assignments
>> drm/amdgpu: add SDMA v4.0 implementation
>> drm/amdgpu: implement GFX 9.0 support
>> drm/amdgpu: add vega10 interrupt handler
>> drm/amdgpu: soc15 enable (v2)
>> drm/amdgpu: Set the IP blocks for vega10
>>
>> Leo Liu (2):
>> drm/amdgpu: add initial uvd 7.0 support for vega10
>> drm/amdgpu: add initial vce 4.0 support for vega10
>>
>> Marek Olšák (1):
>> drm/amdgpu: don't validate TILE_SPLIT on GFX9
>>
>> Monk Liu (5):
>> drm/amdgpu/gfx9: programing wptr_poll_addr register
>> drm/amdgpu:impl gfx9 cond_exec
>> drm/amdgpu:bypass RLC init for SRIOV
>> drm/amdgpu/sdma4:re-org SDMA initial steps for sriov
>> drm/amdgpu/vega10:fix DOORBELL64 scheme
>>
>> Rex Zhu (2):
>> drm/amdgpu: get display info from DC when DC enabled.
>> drm/amd/powerplay: add global PowerPlay mutex.
>>
>> Xiangliang Yu (22):
>> drm/amdgpu: impl sriov detection for vega10
>> drm/amdgpu: add kiq ring for gfx9
>> drm/amdgpu/gfx9: fullfill kiq funcs
>> drm/amdgpu/gfx9: fullfill kiq irq funcs
>> drm/amdgpu: init kiq and kcq for vega10
>> drm/amdgpu/gfx9: impl gfx9 meta data emit
>> drm/amdgpu/soc15: bypass PSP for VF
>> drm/amdgpu/gmc9: no need use kiq in vega10 tlb flush
>> drm/amdgpu/dce_virtual: bypass DPM for vf
>> drm/amdgpu/virt: impl mailbox for ai
>> drm/amdgpu/soc15: init virt ops for vf
>> drm/amdgpu/soc15: enable virtual dce for vf
>> drm/amdgpu: Don't touch PG&CG for SRIOV MM
>> drm/amdgpu/vce4: enable doorbell for SRIOV
>> drm/amdgpu: disable uvd for sriov
>> drm/amdgpu/soc15: bypass pp block for vf
>> drm/amdgpu/virt: add structure for MM table
>> drm/amdgpu/vce4: alloc mm table for MM sriov
>> drm/amdgpu/vce4: Ignore vce ring/ib test temporarily
>> drm/amdgpu: add mmsch structures
>> drm/amdgpu/vce4: impl vce & mmsch sriov start
>> drm/amdgpu/gfx9: correct wptr pointer value
>>
>> ken (1):
>> drm/amdgpu: add clinetid definition for vega10
>>
>> drivers/gpu/drm/amd/amdgpu/Makefile | 27 +-
>> drivers/gpu/drm/amd/amdgpu/amdgpu.h | 172 +-
>> drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c | 28 +
>> drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.h | 3 +
>> drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c | 112 +
>> drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.h | 33 +
>> drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c | 30 +-
>> drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c | 73 +-
>> drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 73 +-
>> drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 36 +-
>> drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c | 3 +-
>> drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 2 +-
>> drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h | 47 +-
>> drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c | 3 +
>> drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 32 +
>> drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 5 +-
>> drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c | 5 +-
>> drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 473 +
>> drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h | 127 +
>> drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h | 37 +
>> drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c | 113 +-
>> drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h | 17 +
>> drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c | 58 +-
>> drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c | 21 +
>> drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h | 7 +
>> drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 34 +-
>> drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h | 4 +
>> drivers/gpu/drm/amd/amdgpu/atom.c | 26 -
>> drivers/gpu/drm/amd/amdgpu/atom.h | 1 -
>> drivers/gpu/drm/amd/amdgpu/cik.c | 2 +
>> drivers/gpu/drm/amd/amdgpu/clearstate_gfx9.h | 941 +
>> drivers/gpu/drm/amd/amdgpu/dce_virtual.c | 3 +
>> drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 6 +-
>> drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 4075 +
>> drivers/gpu/drm/amd/amdgpu/gfx_v9_0.h | 35 +
>> drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c | 447 +
>> drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.h | 35 +
>> drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 826 +
>> drivers/gpu/drm/amd/amdgpu/gmc_v9_0.h | 30 +
>> drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c | 585 +
>> drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.h | 35 +
>> drivers/gpu/drm/amd/amdgpu/mmsch_v1_0.h | 87 +
>> drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c | 207 +
>> drivers/gpu/drm/amd/amdgpu/mxgpu_ai.h | 47 +
>> drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c | 251 +
>> drivers/gpu/drm/amd/amdgpu/nbio_v6_1.h | 53 +
>> drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h | 269 +
>> drivers/gpu/drm/amd/amdgpu/psp_v3_1.c | 507 +
>> drivers/gpu/drm/amd/amdgpu/psp_v3_1.h | 50 +
>> drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c | 4 +-
>> drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 4 +-
>> drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 1573 +
>> drivers/gpu/drm/amd/amdgpu/sdma_v4_0.h | 30 +
>> drivers/gpu/drm/amd/amdgpu/soc15.c | 825 +
>> drivers/gpu/drm/amd/amdgpu/soc15.h | 35 +
>> drivers/gpu/drm/amd/amdgpu/soc15_common.h | 57 +
>> drivers/gpu/drm/amd/amdgpu/soc15d.h | 287 +
>> drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c | 1543 +
>> drivers/gpu/drm/amd/amdgpu/uvd_v7_0.h | 29 +
>> drivers/gpu/drm/amd/amdgpu/vce_v4_0.c | 1141 +
>> drivers/gpu/drm/amd/amdgpu/vce_v4_0.h | 29 +
>> drivers/gpu/drm/amd/amdgpu/vega10_ih.c | 424 +
>> drivers/gpu/drm/amd/amdgpu/vega10_ih.h | 30 +
>> drivers/gpu/drm/amd/amdgpu/vega10_sdma_pkt_open.h | 3335 +
>> drivers/gpu/drm/amd/amdgpu/vi.c | 4 +-
>> drivers/gpu/drm/amd/display/Kconfig | 7 +
>> drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 145 +-
>> .../drm/amd/display/amdgpu_dm/amdgpu_dm_services.c | 10 +
>> .../drm/amd/display/amdgpu_dm/amdgpu_dm_types.c | 20 +-
>> drivers/gpu/drm/amd/display/dc/Makefile | 4 +
>> drivers/gpu/drm/amd/display/dc/bios/Makefile | 8 +
>> drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c | 2162 +
>> drivers/gpu/drm/amd/display/dc/bios/bios_parser2.h | 33 +
>> .../amd/display/dc/bios/bios_parser_interface.c | 14 +
>> .../display/dc/bios/bios_parser_types_internal2.h | 74 +
>> .../gpu/drm/amd/display/dc/bios/command_table2.c | 813 +
>> .../gpu/drm/amd/display/dc/bios/command_table2.h | 105 +
>> .../amd/display/dc/bios/command_table_helper2.c | 260 +
>> .../amd/display/dc/bios/command_table_helper2.h | 82 +
>> .../dc/bios/dce112/command_table_helper2_dce112.c | 418 +
>> .../dc/bios/dce112/command_table_helper2_dce112.h | 34 +
>> drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c | 117 +
>> drivers/gpu/drm/amd/display/dc/core/dc.c | 29 +
>> drivers/gpu/drm/amd/display/dc/core/dc_debug.c | 11 +
>> drivers/gpu/drm/amd/display/dc/core/dc_link.c | 19 +
>> drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 14 +
>> drivers/gpu/drm/amd/display/dc/dc.h | 27 +
>> drivers/gpu/drm/amd/display/dc/dc_hw_types.h | 46 +
>> .../gpu/drm/amd/display/dc/dce/dce_clock_source.c | 6 +
>> drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c | 149 +
>> drivers/gpu/drm/amd/display/dc/dce/dce_clocks.h | 20 +
>> drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h | 8 +
>> .../gpu/drm/amd/display/dc/dce/dce_link_encoder.h | 14 +
>> drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c | 35 +
>> drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h | 34 +
>> drivers/gpu/drm/amd/display/dc/dce/dce_opp.h | 72 +
>> .../drm/amd/display/dc/dce/dce_stream_encoder.h | 100 +
>> drivers/gpu/drm/amd/display/dc/dce/dce_transform.h | 68 +
>> .../amd/display/dc/dce110/dce110_hw_sequencer.c | 53 +-
>> .../drm/amd/display/dc/dce110/dce110_mem_input.c | 3 +
>> .../display/dc/dce110/dce110_timing_generator.h | 3 +
>> drivers/gpu/drm/amd/display/dc/dce120/Makefile | 12 +
>> .../amd/display/dc/dce120/dce120_hw_sequencer.c | 197 +
>> .../amd/display/dc/dce120/dce120_hw_sequencer.h | 36 +
>> drivers/gpu/drm/amd/display/dc/dce120/dce120_ipp.c | 58 +
>> drivers/gpu/drm/amd/display/dc/dce120/dce120_ipp.h | 62 +
>> .../drm/amd/display/dc/dce120/dce120_ipp_cursor.c | 202 +
>> .../drm/amd/display/dc/dce120/dce120_ipp_gamma.c | 167 +
>> .../drm/amd/display/dc/dce120/dce120_mem_input.c | 340 +
>> .../drm/amd/display/dc/dce120/dce120_mem_input.h | 37 +
>> .../drm/amd/display/dc/dce120/dce120_resource.c | 1099 +
>> .../drm/amd/display/dc/dce120/dce120_resource.h | 39 +
>> .../display/dc/dce120/dce120_timing_generator.c | 1109 +
>> .../display/dc/dce120/dce120_timing_generator.h | 41 +
>> .../gpu/drm/amd/display/dc/dce80/dce80_mem_input.c | 3 +
>> drivers/gpu/drm/amd/display/dc/dm_services.h | 89 +
>> drivers/gpu/drm/amd/display/dc/dm_services_types.h | 27 +
>> drivers/gpu/drm/amd/display/dc/gpio/Makefile | 11 +
>> .../amd/display/dc/gpio/dce120/hw_factory_dce120.c | 197 +
>> .../amd/display/dc/gpio/dce120/hw_factory_dce120.h | 32 +
>> .../display/dc/gpio/dce120/hw_translate_dce120.c | 408 +
>> .../display/dc/gpio/dce120/hw_translate_dce120.h | 34 +
>> drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c | 9 +
>> drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c | 9 +-
>> drivers/gpu/drm/amd/display/dc/i2caux/Makefile | 11 +
>> .../amd/display/dc/i2caux/dce120/i2caux_dce120.c | 125 +
>> .../amd/display/dc/i2caux/dce120/i2caux_dce120.h | 32 +
>> drivers/gpu/drm/amd/display/dc/i2caux/i2caux.c | 8 +
>> .../gpu/drm/amd/display/dc/inc/bandwidth_calcs.h | 3 +
>> .../gpu/drm/amd/display/dc/inc/hw/display_clock.h | 23 +
>> drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h | 4 +
>> drivers/gpu/drm/amd/display/dc/irq/Makefile | 12 +
>> .../amd/display/dc/irq/dce120/irq_service_dce120.c | 293 +
>> .../amd/display/dc/irq/dce120/irq_service_dce120.h | 34 +
>> drivers/gpu/drm/amd/display/dc/irq/irq_service.c | 3 +
>> drivers/gpu/drm/amd/display/include/dal_asic_id.h | 4 +
>> drivers/gpu/drm/amd/display/include/dal_types.h | 3 +
>> drivers/gpu/drm/amd/include/amd_shared.h | 4 +
>> .../asic_reg/vega10/ATHUB/athub_1_0_default.h | 241 +
>> .../asic_reg/vega10/ATHUB/athub_1_0_offset.h | 453 +
>> .../asic_reg/vega10/ATHUB/athub_1_0_sh_mask.h | 2045 +
>> .../include/asic_reg/vega10/DC/dce_12_0_default.h | 9868 ++
>> .../include/asic_reg/vega10/DC/dce_12_0_offset.h | 18193 +++
>> .../include/asic_reg/vega10/DC/dce_12_0_sh_mask.h | 64636 +++++++++
>> .../include/asic_reg/vega10/GC/gc_9_0_default.h | 3873 +
>> .../amd/include/asic_reg/vega10/GC/gc_9_0_offset.h | 7230 +
>> .../include/asic_reg/vega10/GC/gc_9_0_sh_mask.h | 29868 ++++
>> .../include/asic_reg/vega10/HDP/hdp_4_0_default.h | 117 +
>> .../include/asic_reg/vega10/HDP/hdp_4_0_offset.h | 209 +
>> .../include/asic_reg/vega10/HDP/hdp_4_0_sh_mask.h | 601 +
>> .../asic_reg/vega10/MMHUB/mmhub_1_0_default.h | 1011 +
>> .../asic_reg/vega10/MMHUB/mmhub_1_0_offset.h | 1967 +
>> .../asic_reg/vega10/MMHUB/mmhub_1_0_sh_mask.h | 10127 ++
>> .../include/asic_reg/vega10/MP/mp_9_0_default.h | 342 +
>> .../amd/include/asic_reg/vega10/MP/mp_9_0_offset.h | 375 +
>> .../include/asic_reg/vega10/MP/mp_9_0_sh_mask.h | 1463 +
>> .../asic_reg/vega10/NBIF/nbif_6_1_default.h | 1271 +
>> .../include/asic_reg/vega10/NBIF/nbif_6_1_offset.h | 1688 +
>> .../asic_reg/vega10/NBIF/nbif_6_1_sh_mask.h | 10281 ++
>> .../asic_reg/vega10/NBIO/nbio_6_1_default.h | 22340 +++
>> .../include/asic_reg/vega10/NBIO/nbio_6_1_offset.h | 3649 +
>> .../asic_reg/vega10/NBIO/nbio_6_1_sh_mask.h | 133884
>> ++++++++++++++++++
>> .../asic_reg/vega10/OSSSYS/osssys_4_0_default.h | 176 +
>> .../asic_reg/vega10/OSSSYS/osssys_4_0_offset.h | 327 +
>> .../asic_reg/vega10/OSSSYS/osssys_4_0_sh_mask.h | 1196 +
>> .../asic_reg/vega10/SDMA0/sdma0_4_0_default.h | 286 +
>> .../asic_reg/vega10/SDMA0/sdma0_4_0_offset.h | 547 +
>> .../asic_reg/vega10/SDMA0/sdma0_4_0_sh_mask.h | 1852 +
>> .../asic_reg/vega10/SDMA1/sdma1_4_0_default.h | 282 +
>> .../asic_reg/vega10/SDMA1/sdma1_4_0_offset.h | 539 +
>> .../asic_reg/vega10/SDMA1/sdma1_4_0_sh_mask.h | 1810 +
>> .../asic_reg/vega10/SMUIO/smuio_9_0_default.h | 100 +
>> .../asic_reg/vega10/SMUIO/smuio_9_0_offset.h | 175 +
>> .../asic_reg/vega10/SMUIO/smuio_9_0_sh_mask.h | 258 +
>> .../include/asic_reg/vega10/THM/thm_9_0_default.h | 194 +
>> .../include/asic_reg/vega10/THM/thm_9_0_offset.h | 363 +
>> .../include/asic_reg/vega10/THM/thm_9_0_sh_mask.h | 1314 +
>> .../include/asic_reg/vega10/UVD/uvd_7_0_default.h | 127 +
>> .../include/asic_reg/vega10/UVD/uvd_7_0_offset.h | 222 +
>> .../include/asic_reg/vega10/UVD/uvd_7_0_sh_mask.h | 811 +
>> .../include/asic_reg/vega10/VCE/vce_4_0_default.h | 122 +
>> .../include/asic_reg/vega10/VCE/vce_4_0_offset.h | 208 +
>> .../include/asic_reg/vega10/VCE/vce_4_0_sh_mask.h | 488 +
>> .../gpu/drm/amd/include/asic_reg/vega10/soc15ip.h | 1343 +
>> .../drm/amd/include/asic_reg/vega10/vega10_enum.h | 22531 +++
>> drivers/gpu/drm/amd/include/atomfirmware.h | 2385 +
>> drivers/gpu/drm/amd/include/atomfirmwareid.h | 86 +
>> drivers/gpu/drm/amd/include/displayobject.h | 249 +
>> drivers/gpu/drm/amd/include/dm_pp_interface.h | 83 +
>> drivers/gpu/drm/amd/include/v9_structs.h | 743 +
>> drivers/gpu/drm/amd/powerplay/amd_powerplay.c | 284 +-
>> drivers/gpu/drm/amd/powerplay/hwmgr/Makefile | 6 +-
>> .../gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c | 49 +
>> drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c | 9 +
>> drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr_ppt.h | 16 +-
>> drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.c | 396 +
>> drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.h | 140 +
>> drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c | 4378 +
>> drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h | 434 +
>> drivers/gpu/drm/amd/powerplay/hwmgr/vega10_inc.h | 44 +
>> .../gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c | 137 +
>> .../gpu/drm/amd/powerplay/hwmgr/vega10_powertune.h | 65 +
>> .../gpu/drm/amd/powerplay/hwmgr/vega10_pptable.h | 331 +
>> .../amd/powerplay/hwmgr/vega10_processpptables.c | 1056 +
>> .../amd/powerplay/hwmgr/vega10_processpptables.h | 34 +
>> .../gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c | 761 +
>> .../gpu/drm/amd/powerplay/hwmgr/vega10_thermal.h | 83 +
>> drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h | 28 +-
>> .../gpu/drm/amd/powerplay/inc/hardwaremanager.h | 43 +
>> drivers/gpu/drm/amd/powerplay/inc/hwmgr.h | 125 +-
>> drivers/gpu/drm/amd/powerplay/inc/pp_instance.h | 1 +
>> drivers/gpu/drm/amd/powerplay/inc/pp_soc15.h | 48 +
>> drivers/gpu/drm/amd/powerplay/inc/smu9.h | 147 +
>> drivers/gpu/drm/amd/powerplay/inc/smu9_driver_if.h | 418 +
>> drivers/gpu/drm/amd/powerplay/inc/smumgr.h | 3 +
>> drivers/gpu/drm/amd/powerplay/inc/vega10_ppsmc.h | 131 +
>> drivers/gpu/drm/amd/powerplay/smumgr/Makefile | 2 +-
>> drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c | 9 +
>> .../gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c | 564 +
>> .../gpu/drm/amd/powerplay/smumgr/vega10_smumgr.h | 70 +
>> include/uapi/drm/amdgpu_drm.h | 29 +
>> 221 files changed, 403408 insertions(+), 219 deletions(-)
>> create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c
>> create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.h
>> create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
>> create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
>> create mode 100644 drivers/gpu/drm/amd/amdgpu/clearstate_gfx9.h
>> create mode 100644 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
>> create mode 100644 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.h
>> create mode 100644 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
>> create mode 100644 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.h
>> create mode 100644 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
>> create mode 100644 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.h
>> create mode 100644 drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
>> create mode 100644 drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.h
>> create mode 100644 drivers/gpu/drm/amd/amdgpu/mmsch_v1_0.h
>> create mode 100644 drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c
>> create mode 100644 drivers/gpu/drm/amd/amdgpu/mxgpu_ai.h
>> create mode 100644 drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c
>> create mode 100644 drivers/gpu/drm/amd/amdgpu/nbio_v6_1.h
>> create mode 100644 drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h
>> create mode 100644 drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
>> create mode 100644 drivers/gpu/drm/amd/amdgpu/psp_v3_1.h
>> create mode 100644 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
>> create mode 100644 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.h
>> create mode 100644 drivers/gpu/drm/amd/amdgpu/soc15.c
>> create mode 100644 drivers/gpu/drm/amd/amdgpu/soc15.h
>> create mode 100644 drivers/gpu/drm/amd/amdgpu/soc15_common.h
>> create mode 100644 drivers/gpu/drm/amd/amdgpu/soc15d.h
>> create mode 100644 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
>> create mode 100644 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.h
>> create mode 100644 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
>> create mode 100644 drivers/gpu/drm/amd/amdgpu/vce_v4_0.h
>> create mode 100644 drivers/gpu/drm/amd/amdgpu/vega10_ih.c
>> create mode 100644 drivers/gpu/drm/amd/amdgpu/vega10_ih.h
>> create mode 100644 drivers/gpu/drm/amd/amdgpu/vega10_sdma_pkt_open.h
>> create mode 100644 drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
>> create mode 100644 drivers/gpu/drm/amd/display/dc/bios/bios_parser2.h
>> create mode 100644
>> drivers/gpu/drm/amd/display/dc/bios/bios_parser_types_internal2.h
>> create mode 100644 drivers/gpu/drm/amd/display/dc/bios/command_table2.c
>> create mode 100644 drivers/gpu/drm/amd/display/dc/bios/command_table2.h
>> create mode 100644
>> drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c
>> create mode 100644
>> drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.h
>> create mode 100644
>> drivers/gpu/drm/amd/display/dc/bios/dce112/command_table_helper2_dce112.c
>> create mode 100644
>> drivers/gpu/drm/amd/display/dc/bios/dce112/command_table_helper2_dce112.h
>> create mode 100644 drivers/gpu/drm/amd/display/dc/dce120/Makefile
>> create mode 100644
>> drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.c
>> create mode 100644
>> drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.h
>> create mode 100644 drivers/gpu/drm/amd/display/dc/dce120/dce120_ipp.c
>> create mode 100644 drivers/gpu/drm/amd/display/dc/dce120/dce120_ipp.h
>> create mode 100644
>> drivers/gpu/drm/amd/display/dc/dce120/dce120_ipp_cursor.c
>> create mode 100644
>> drivers/gpu/drm/amd/display/dc/dce120/dce120_ipp_gamma.c
>> create mode 100644
>> drivers/gpu/drm/amd/display/dc/dce120/dce120_mem_input.c
>> create mode 100644
>> drivers/gpu/drm/amd/display/dc/dce120/dce120_mem_input.h
>> create mode 100644
>> drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c
>> create mode 100644
>> drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.h
>> create mode 100644
>> drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c
>> create mode 100644
>> drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.h
>> create mode 100644
>> drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_factory_dce120.c
>> create mode 100644
>> drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_factory_dce120.h
>> create mode 100644
>> drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c
>> create mode 100644
>> drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.h
>> create mode 100644
>> drivers/gpu/drm/amd/display/dc/i2caux/dce120/i2caux_dce120.c
>> create mode 100644
>> drivers/gpu/drm/amd/display/dc/i2caux/dce120/i2caux_dce120.h
>> create mode 100644
>> drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c
>> create mode 100644
>> drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.h
>> create mode 100644
>> drivers/gpu/drm/amd/include/asic_reg/vega10/ATHUB/athub_1_0_default.h
>> create mode 100644
>> drivers/gpu/drm/amd/include/asic_reg/vega10/ATHUB/athub_1_0_offset.h
>> create mode 100644
>> drivers/gpu/drm/amd/include/asic_reg/vega10/ATHUB/athub_1_0_sh_mask.h
>> create mode 100644
>> drivers/gpu/drm/amd/include/asic_reg/vega10/DC/dce_12_0_default.h
>> create mode 100644
>> drivers/gpu/drm/amd/include/asic_reg/vega10/DC/dce_12_0_offset.h
>> create mode 100644
>> drivers/gpu/drm/amd/include/asic_reg/vega10/DC/dce_12_0_sh_mask.h
>> create mode 100644
>> drivers/gpu/drm/amd/include/asic_reg/vega10/GC/gc_9_0_default.h
>> create mode 100644
>> drivers/gpu/drm/amd/include/asic_reg/vega10/GC/gc_9_0_offset.h
>> create mode 100644
>> drivers/gpu/drm/amd/include/asic_reg/vega10/GC/gc_9_0_sh_mask.h
>> create mode 100644
>> drivers/gpu/drm/amd/include/asic_reg/vega10/HDP/hdp_4_0_default.h
>> create mode 100644
>> drivers/gpu/drm/amd/include/asic_reg/vega10/HDP/hdp_4_0_offset.h
>> create mode 100644
>> drivers/gpu/drm/amd/include/asic_reg/vega10/HDP/hdp_4_0_sh_mask.h
>> create mode 100644
>> drivers/gpu/drm/amd/include/asic_reg/vega10/MMHUB/mmhub_1_0_default.h
>> create mode 100644
>> drivers/gpu/drm/amd/include/asic_reg/vega10/MMHUB/mmhub_1_0_offset.h
>> create mode 100644
>> drivers/gpu/drm/amd/include/asic_reg/vega10/MMHUB/mmhub_1_0_sh_mask.h
>> create mode 100644
>> drivers/gpu/drm/amd/include/asic_reg/vega10/MP/mp_9_0_default.h
>> create mode 100644
>> drivers/gpu/drm/amd/include/asic_reg/vega10/MP/mp_9_0_offset.h
>> create mode 100644
>> drivers/gpu/drm/amd/include/asic_reg/vega10/MP/mp_9_0_sh_mask.h
>> create mode 100644
>> drivers/gpu/drm/amd/include/asic_reg/vega10/NBIF/nbif_6_1_default.h
>> create mode 100644
>> drivers/gpu/drm/amd/include/asic_reg/vega10/NBIF/nbif_6_1_offset.h
>> create mode 100644
>> drivers/gpu/drm/amd/include/asic_reg/vega10/NBIF/nbif_6_1_sh_mask.h
>> create mode 100644
>> drivers/gpu/drm/amd/include/asic_reg/vega10/NBIO/nbio_6_1_default.h
>> create mode 100644
>> drivers/gpu/drm/amd/include/asic_reg/vega10/NBIO/nbio_6_1_offset.h
>> create mode 100644
>> drivers/gpu/drm/amd/include/asic_reg/vega10/NBIO/nbio_6_1_sh_mask.h
>> create mode 100644
>> drivers/gpu/drm/amd/include/asic_reg/vega10/OSSSYS/osssys_4_0_default.h
>> create mode 100644
>> drivers/gpu/drm/amd/include/asic_reg/vega10/OSSSYS/osssys_4_0_offset.h
>> create mode 100644
>> drivers/gpu/drm/amd/include/asic_reg/vega10/OSSSYS/osssys_4_0_sh_mask.h
>> create mode 100644
>> drivers/gpu/drm/amd/include/asic_reg/vega10/SDMA0/sdma0_4_0_default.h
>> create mode 100644
>> drivers/gpu/drm/amd/include/asic_reg/vega10/SDMA0/sdma0_4_0_offset.h
>> create mode 100644
>> drivers/gpu/drm/amd/include/asic_reg/vega10/SDMA0/sdma0_4_0_sh_mask.h
>> create mode 100644
>> drivers/gpu/drm/amd/include/asic_reg/vega10/SDMA1/sdma1_4_0_default.h
>> create mode 100644
>> drivers/gpu/drm/amd/include/asic_reg/vega10/SDMA1/sdma1_4_0_offset.h
>> create mode 100644
>> drivers/gpu/drm/amd/include/asic_reg/vega10/SDMA1/sdma1_4_0_sh_mask.h
>> create mode 100644
>> drivers/gpu/drm/amd/include/asic_reg/vega10/SMUIO/smuio_9_0_default.h
>> create mode 100644
>> drivers/gpu/drm/amd/include/asic_reg/vega10/SMUIO/smuio_9_0_offset.h
>> create mode 100644
>> drivers/gpu/drm/amd/include/asic_reg/vega10/SMUIO/smuio_9_0_sh_mask.h
>> create mode 100644
>> drivers/gpu/drm/amd/include/asic_reg/vega10/THM/thm_9_0_default.h
>> create mode 100644
>> drivers/gpu/drm/amd/include/asic_reg/vega10/THM/thm_9_0_offset.h
>> create mode 100644
>> drivers/gpu/drm/amd/include/asic_reg/vega10/THM/thm_9_0_sh_mask.h
>> create mode 100644
>> drivers/gpu/drm/amd/include/asic_reg/vega10/UVD/uvd_7_0_default.h
>> create mode 100644
>> drivers/gpu/drm/amd/include/asic_reg/vega10/UVD/uvd_7_0_offset.h
>> create mode 100644
>> drivers/gpu/drm/amd/include/asic_reg/vega10/UVD/uvd_7_0_sh_mask.h
>> create mode 100644
>> drivers/gpu/drm/amd/include/asic_reg/vega10/VCE/vce_4_0_default.h
>> create mode 100644
>> drivers/gpu/drm/amd/include/asic_reg/vega10/VCE/vce_4_0_offset.h
>> create mode 100644
>> drivers/gpu/drm/amd/include/asic_reg/vega10/VCE/vce_4_0_sh_mask.h
>> create mode 100644 drivers/gpu/drm/amd/include/asic_reg/vega10/soc15ip.h
>> create mode 100644
>> drivers/gpu/drm/amd/include/asic_reg/vega10/vega10_enum.h
>> create mode 100644 drivers/gpu/drm/amd/include/atomfirmware.h
>> create mode 100644 drivers/gpu/drm/amd/include/atomfirmwareid.h
>> create mode 100644 drivers/gpu/drm/amd/include/displayobject.h
>> create mode 100644 drivers/gpu/drm/amd/include/dm_pp_interface.h
>> create mode 100644 drivers/gpu/drm/amd/include/v9_structs.h
>> create mode 100644 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.c
>> create mode 100644 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.h
>> create mode 100644 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
>> create mode 100644 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h
>> create mode 100644 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_inc.h
>> create mode 100644
>> drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c
>> create mode 100644
>> drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.h
>> create mode 100644 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_pptable.h
>> create mode 100644
>> drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c
>> create mode 100644
>> drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.h
>> create mode 100644 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c
>> create mode 100644 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.h
>> create mode 100644 drivers/gpu/drm/amd/powerplay/inc/pp_soc15.h
>> create mode 100644 drivers/gpu/drm/amd/powerplay/inc/smu9.h
>> create mode 100644 drivers/gpu/drm/amd/powerplay/inc/smu9_driver_if.h
>> create mode 100644 drivers/gpu/drm/amd/powerplay/inc/vega10_ppsmc.h
>> create mode 100644 drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c
>> create mode 100644 drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.h
>>
>
_______________________________________________
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^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH 000/100] Add Vega10 Support
[not found] ` <15b7d1b4-8ac7-d14b-40f6-aba529b301ea-ANTagKRnAhcb1SvskN2V4Q@public.gmane.org>
@ 2017-03-21 15:54 ` Alex Deucher
0 siblings, 0 replies; 16+ messages in thread
From: Alex Deucher @ 2017-03-21 15:54 UTC (permalink / raw)
To: Christian König; +Cc: Alex Deucher, amd-gfx list
On Tue, Mar 21, 2017 at 8:18 AM, Christian König
<deathsimple@vodafone.de> wrote:
> In my Spam folder I've found:
>
> Patches #22, #24, #39, #50, #64, #69, #75, #78 which are Acked-by: Christian
> König <christian.koenig@amd.com>.
>
> Patches #32, #42 which are Reviewed-by: Christian König
> <christian.koenig@amd.com>.
>
> And patches #80, #85, #89, #90, #91, #100 which already had either my rb or
> ackb.
>
> So still missing are #6-#20 which are probably just to large for the list.
As I mentioned below, 6-20 are the register headers which I didn't
send because they are too big.
Alex
>
> Regards,
> Christian.
>
>
> Am 21.03.2017 um 12:51 schrieb Christian König:
>>
>> Patches #48, #49, #52-#63, #65-#68, #70-#72, #74, #76, #77, #79, #81-#84
>> are Acked-by: Christian König <christian.koenig@amd.com>.
>>
>> Patches #50, #64, #69, #75, #78, #80, #85, #89-#91, #100 didn't made it to
>> the list.
>>
>> Patch #73 probably needs to be moved to the end of the set or at least
>> after the wptr_poll fix.
>>
>> Apart from those everything should already have my reviewed-by or
>> acked-by.
>>
>> What worries me a bit are the ones who didn't made it to the list. Going
>> to check my spam folder, but that is a bit disturbing.
>>
>> Regards,
>> Christian.
>>
>> Am 21.03.2017 um 08:42 schrieb Christian König:
>>>
>>> Patches #1 - #5, #21, #23, #25, #27, #28, #31, #35-#38, #40, #41, #45 are
>>> Acked-by: Christian König.
>>>
>>> Patches #6-#20, #22, #24, #32, #39, #42 didn't made it to the list
>>> (probably to large).
>>>
>>> Patches #43, #44 are Reviewed-by: Christian König
>>> <christian.koenig@amd.com>.
>>>
>>> Patch #26: That stuff actually belongs into vega10 specifc code, doesn't
>>> it?
>>>
>>> Patch #29: We shouldn't use typedefs for enums.
>>>
>>> Going to take a look at the rest later today,
>>> Christian.
>>>
>>> Am 20.03.2017 um 21:29 schrieb Alex Deucher:
>>>>
>>>> This patch set adds support for vega10. Major changes and supported
>>>> features:
>>>> - new vbios interface
>>>> - Lots of new hw IPs
>>>> - Support for video decode using UVD
>>>> - Support for video encode using VCE
>>>> - Support for 3D via radeonsi
>>>> - Power management
>>>> - Full display support via DC
>>>> - Support for SR-IOV
>>>>
>>>> I did not send out the register headers since they are huge. You can
>>>> find them
>>>> along with all the other patches in this series here:
>>>> https://cgit.freedesktop.org/~agd5f/linux/log/?h=amd-staging-4.9
>>>>
>>>> Please review.
>>>>
>>>> Thanks,
>>>>
>>>> Alex
>>>>
>>>> Alex Deucher (29):
>>>> drm/amdgpu: add the new atomfirmware interface header
>>>> amdgpu: detect if we are using atomfirm or atombios for vbios (v2)
>>>> drm/amdgpu: move atom scratch setup into amdgpu_atombios.c
>>>> drm/amdgpu: add basic support for atomfirmware.h (v3)
>>>> drm/amdgpu: add soc15ip.h
>>>> drm/amdgpu: add vega10_enum.h
>>>> drm/amdgpu: Add ATHUB 1.0 register headers
>>>> drm/amdgpu: Add the DCE 12.0 register headers
>>>> drm/amdgpu: add the GC 9.0 register headers
>>>> drm/amdgpu: add the HDP 4.0 register headers
>>>> drm/amdgpu: add the MMHUB 1.0 register headers
>>>> drm/amdgpu: add MP 9.0 register headers
>>>> drm/amdgpu: add NBIF 6.1 register headers
>>>> drm/amdgpu: add NBIO 6.1 register headers
>>>> drm/amdgpu: add OSSSYS 4.0 register headers
>>>> drm/amdgpu: add SDMA 4.0 register headers
>>>> drm/amdgpu: add SMUIO 9.0 register headers
>>>> drm/amdgpu: add THM 9.0 register headers
>>>> drm/amdgpu: add the UVD 7.0 register headers
>>>> drm/amdgpu: add the VCE 4.0 register headers
>>>> drm/amdgpu: add gfx9 clearstate header
>>>> drm/amdgpu: add SDMA 4.0 packet header
>>>> drm/amdgpu: use atomfirmware interfaces for scratch reg save/restore
>>>> drm/amdgpu: update IH IV ring entry for soc-15
>>>> drm/amdgpu: add PTE defines for MTYPE
>>>> drm/amdgpu: add NGG parameters
>>>> drm/amdgpu: Add asic family for vega10
>>>> drm/amdgpu: add tiling flags for GFX9
>>>> drm/amdgpu: gart fixes for vega10
>>>>
>>>> Alex Xie (4):
>>>> drm/amdgpu: Add MTYPE flags to GPU VM IOCTL interface
>>>> drm/amdgpu: handle PTE EXEC in amdgpu_vm_bo_split_mapping
>>>> drm/amdgpu: handle PTE MTYPE in amdgpu_vm_bo_split_mapping
>>>> drm/amdgpu: Add GMC 9.0 support
>>>>
>>>> Andrey Grodzovsky (1):
>>>> drm/amdgpu: gb_addr_config struct
>>>>
>>>> Charlene Liu (1):
>>>> drm/amd/display: need to handle DCE_Info table ver4.2
>>>>
>>>> Christian König (1):
>>>> drm/amdgpu: add IV trace point
>>>>
>>>> Eric Huang (7):
>>>> drm/amd/powerplay: add smu9 header files for Vega10
>>>> drm/amd/powerplay: add new Vega10's ppsmc header file
>>>> drm/amdgpu: add new atomfirmware based helpers for powerplay
>>>> drm/amd/powerplay: add some new structures for Vega10
>>>> drm/amd: add structures for display/powerplay interface
>>>> drm/amd/powerplay: add some display/powerplay interfaces
>>>> drm/amd/powerplay: add Vega10 powerplay support
>>>>
>>>> Felix Kuehling (1):
>>>> drm/amd: Add MQD structs for GFX V9
>>>>
>>>> Harry Wentland (6):
>>>> drm/amd/display: Add DCE12 bios parser support
>>>> drm/amd/display: Add DCE12 gpio support
>>>> drm/amd/display: Add DCE12 i2c/aux support
>>>> drm/amd/display: Add DCE12 irq support
>>>> drm/amd/display: Add DCE12 core support
>>>> drm/amd/display: Enable DCE12 support
>>>>
>>>> Huang Rui (6):
>>>> drm/amdgpu: use new flag to handle different firmware loading method
>>>> drm/amdgpu: rework common ucode handling for vega10
>>>> drm/amdgpu: add psp firmware header info
>>>> drm/amdgpu: add PSP driver for vega10
>>>> drm/amdgpu: add psp firmware info into info query and debugfs
>>>> drm/amdgpu: add SMC firmware into global ucode list for psp loading
>>>>
>>>> Jordan Lazare (1):
>>>> drm/amd/display: Less log spam
>>>>
>>>> Junwei Zhang (2):
>>>> drm/amdgpu: add NBIO 6.1 driver
>>>> drm/amdgpu: add Vega10 Device IDs
>>>>
>>>> Ken Wang (8):
>>>> drm/amdgpu: add common soc15 headers
>>>> drm/amdgpu: add vega10 chip name
>>>> drm/amdgpu: add 64bit doorbell assignments
>>>> drm/amdgpu: add SDMA v4.0 implementation
>>>> drm/amdgpu: implement GFX 9.0 support
>>>> drm/amdgpu: add vega10 interrupt handler
>>>> drm/amdgpu: soc15 enable (v2)
>>>> drm/amdgpu: Set the IP blocks for vega10
>>>>
>>>> Leo Liu (2):
>>>> drm/amdgpu: add initial uvd 7.0 support for vega10
>>>> drm/amdgpu: add initial vce 4.0 support for vega10
>>>>
>>>> Marek Olšák (1):
>>>> drm/amdgpu: don't validate TILE_SPLIT on GFX9
>>>>
>>>> Monk Liu (5):
>>>> drm/amdgpu/gfx9: programing wptr_poll_addr register
>>>> drm/amdgpu:impl gfx9 cond_exec
>>>> drm/amdgpu:bypass RLC init for SRIOV
>>>> drm/amdgpu/sdma4:re-org SDMA initial steps for sriov
>>>> drm/amdgpu/vega10:fix DOORBELL64 scheme
>>>>
>>>> Rex Zhu (2):
>>>> drm/amdgpu: get display info from DC when DC enabled.
>>>> drm/amd/powerplay: add global PowerPlay mutex.
>>>>
>>>> Xiangliang Yu (22):
>>>> drm/amdgpu: impl sriov detection for vega10
>>>> drm/amdgpu: add kiq ring for gfx9
>>>> drm/amdgpu/gfx9: fullfill kiq funcs
>>>> drm/amdgpu/gfx9: fullfill kiq irq funcs
>>>> drm/amdgpu: init kiq and kcq for vega10
>>>> drm/amdgpu/gfx9: impl gfx9 meta data emit
>>>> drm/amdgpu/soc15: bypass PSP for VF
>>>> drm/amdgpu/gmc9: no need use kiq in vega10 tlb flush
>>>> drm/amdgpu/dce_virtual: bypass DPM for vf
>>>> drm/amdgpu/virt: impl mailbox for ai
>>>> drm/amdgpu/soc15: init virt ops for vf
>>>> drm/amdgpu/soc15: enable virtual dce for vf
>>>> drm/amdgpu: Don't touch PG&CG for SRIOV MM
>>>> drm/amdgpu/vce4: enable doorbell for SRIOV
>>>> drm/amdgpu: disable uvd for sriov
>>>> drm/amdgpu/soc15: bypass pp block for vf
>>>> drm/amdgpu/virt: add structure for MM table
>>>> drm/amdgpu/vce4: alloc mm table for MM sriov
>>>> drm/amdgpu/vce4: Ignore vce ring/ib test temporarily
>>>> drm/amdgpu: add mmsch structures
>>>> drm/amdgpu/vce4: impl vce & mmsch sriov start
>>>> drm/amdgpu/gfx9: correct wptr pointer value
>>>>
>>>> ken (1):
>>>> drm/amdgpu: add clinetid definition for vega10
>>>>
>>>> drivers/gpu/drm/amd/amdgpu/Makefile | 27 +-
>>>> drivers/gpu/drm/amd/amdgpu/amdgpu.h | 172 +-
>>>> drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c | 28 +
>>>> drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.h | 3 +
>>>> drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c | 112 +
>>>> drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.h | 33 +
>>>> drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c | 30 +-
>>>> drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c | 73 +-
>>>> drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 73 +-
>>>> drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 36 +-
>>>> drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c | 3 +-
>>>> drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 2 +-
>>>> drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h | 47 +-
>>>> drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c | 3 +
>>>> drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 32 +
>>>> drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 5 +-
>>>> drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c | 5 +-
>>>> drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 473 +
>>>> drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h | 127 +
>>>> drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h | 37 +
>>>> drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c | 113 +-
>>>> drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h | 17 +
>>>> drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c | 58 +-
>>>> drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c | 21 +
>>>> drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h | 7 +
>>>> drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 34 +-
>>>> drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h | 4 +
>>>> drivers/gpu/drm/amd/amdgpu/atom.c | 26 -
>>>> drivers/gpu/drm/amd/amdgpu/atom.h | 1 -
>>>> drivers/gpu/drm/amd/amdgpu/cik.c | 2 +
>>>> drivers/gpu/drm/amd/amdgpu/clearstate_gfx9.h | 941 +
>>>> drivers/gpu/drm/amd/amdgpu/dce_virtual.c | 3 +
>>>> drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 6 +-
>>>> drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 4075 +
>>>> drivers/gpu/drm/amd/amdgpu/gfx_v9_0.h | 35 +
>>>> drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c | 447 +
>>>> drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.h | 35 +
>>>> drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 826 +
>>>> drivers/gpu/drm/amd/amdgpu/gmc_v9_0.h | 30 +
>>>> drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c | 585 +
>>>> drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.h | 35 +
>>>> drivers/gpu/drm/amd/amdgpu/mmsch_v1_0.h | 87 +
>>>> drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c | 207 +
>>>> drivers/gpu/drm/amd/amdgpu/mxgpu_ai.h | 47 +
>>>> drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c | 251 +
>>>> drivers/gpu/drm/amd/amdgpu/nbio_v6_1.h | 53 +
>>>> drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h | 269 +
>>>> drivers/gpu/drm/amd/amdgpu/psp_v3_1.c | 507 +
>>>> drivers/gpu/drm/amd/amdgpu/psp_v3_1.h | 50 +
>>>> drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c | 4 +-
>>>> drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 4 +-
>>>> drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 1573 +
>>>> drivers/gpu/drm/amd/amdgpu/sdma_v4_0.h | 30 +
>>>> drivers/gpu/drm/amd/amdgpu/soc15.c | 825 +
>>>> drivers/gpu/drm/amd/amdgpu/soc15.h | 35 +
>>>> drivers/gpu/drm/amd/amdgpu/soc15_common.h | 57 +
>>>> drivers/gpu/drm/amd/amdgpu/soc15d.h | 287 +
>>>> drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c | 1543 +
>>>> drivers/gpu/drm/amd/amdgpu/uvd_v7_0.h | 29 +
>>>> drivers/gpu/drm/amd/amdgpu/vce_v4_0.c | 1141 +
>>>> drivers/gpu/drm/amd/amdgpu/vce_v4_0.h | 29 +
>>>> drivers/gpu/drm/amd/amdgpu/vega10_ih.c | 424 +
>>>> drivers/gpu/drm/amd/amdgpu/vega10_ih.h | 30 +
>>>> drivers/gpu/drm/amd/amdgpu/vega10_sdma_pkt_open.h | 3335 +
>>>> drivers/gpu/drm/amd/amdgpu/vi.c | 4 +-
>>>> drivers/gpu/drm/amd/display/Kconfig | 7 +
>>>> drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 145 +-
>>>> .../drm/amd/display/amdgpu_dm/amdgpu_dm_services.c | 10 +
>>>> .../drm/amd/display/amdgpu_dm/amdgpu_dm_types.c | 20 +-
>>>> drivers/gpu/drm/amd/display/dc/Makefile | 4 +
>>>> drivers/gpu/drm/amd/display/dc/bios/Makefile | 8 +
>>>> drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c | 2162 +
>>>> drivers/gpu/drm/amd/display/dc/bios/bios_parser2.h | 33 +
>>>> .../amd/display/dc/bios/bios_parser_interface.c | 14 +
>>>> .../display/dc/bios/bios_parser_types_internal2.h | 74 +
>>>> .../gpu/drm/amd/display/dc/bios/command_table2.c | 813 +
>>>> .../gpu/drm/amd/display/dc/bios/command_table2.h | 105 +
>>>> .../amd/display/dc/bios/command_table_helper2.c | 260 +
>>>> .../amd/display/dc/bios/command_table_helper2.h | 82 +
>>>> .../dc/bios/dce112/command_table_helper2_dce112.c | 418 +
>>>> .../dc/bios/dce112/command_table_helper2_dce112.h | 34 +
>>>> drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c | 117 +
>>>> drivers/gpu/drm/amd/display/dc/core/dc.c | 29 +
>>>> drivers/gpu/drm/amd/display/dc/core/dc_debug.c | 11 +
>>>> drivers/gpu/drm/amd/display/dc/core/dc_link.c | 19 +
>>>> drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 14 +
>>>> drivers/gpu/drm/amd/display/dc/dc.h | 27 +
>>>> drivers/gpu/drm/amd/display/dc/dc_hw_types.h | 46 +
>>>> .../gpu/drm/amd/display/dc/dce/dce_clock_source.c | 6 +
>>>> drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c | 149 +
>>>> drivers/gpu/drm/amd/display/dc/dce/dce_clocks.h | 20 +
>>>> drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h | 8 +
>>>> .../gpu/drm/amd/display/dc/dce/dce_link_encoder.h | 14 +
>>>> drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c | 35 +
>>>> drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h | 34 +
>>>> drivers/gpu/drm/amd/display/dc/dce/dce_opp.h | 72 +
>>>> .../drm/amd/display/dc/dce/dce_stream_encoder.h | 100 +
>>>> drivers/gpu/drm/amd/display/dc/dce/dce_transform.h | 68 +
>>>> .../amd/display/dc/dce110/dce110_hw_sequencer.c | 53 +-
>>>> .../drm/amd/display/dc/dce110/dce110_mem_input.c | 3 +
>>>> .../display/dc/dce110/dce110_timing_generator.h | 3 +
>>>> drivers/gpu/drm/amd/display/dc/dce120/Makefile | 12 +
>>>> .../amd/display/dc/dce120/dce120_hw_sequencer.c | 197 +
>>>> .../amd/display/dc/dce120/dce120_hw_sequencer.h | 36 +
>>>> drivers/gpu/drm/amd/display/dc/dce120/dce120_ipp.c | 58 +
>>>> drivers/gpu/drm/amd/display/dc/dce120/dce120_ipp.h | 62 +
>>>> .../drm/amd/display/dc/dce120/dce120_ipp_cursor.c | 202 +
>>>> .../drm/amd/display/dc/dce120/dce120_ipp_gamma.c | 167 +
>>>> .../drm/amd/display/dc/dce120/dce120_mem_input.c | 340 +
>>>> .../drm/amd/display/dc/dce120/dce120_mem_input.h | 37 +
>>>> .../drm/amd/display/dc/dce120/dce120_resource.c | 1099 +
>>>> .../drm/amd/display/dc/dce120/dce120_resource.h | 39 +
>>>> .../display/dc/dce120/dce120_timing_generator.c | 1109 +
>>>> .../display/dc/dce120/dce120_timing_generator.h | 41 +
>>>> .../gpu/drm/amd/display/dc/dce80/dce80_mem_input.c | 3 +
>>>> drivers/gpu/drm/amd/display/dc/dm_services.h | 89 +
>>>> drivers/gpu/drm/amd/display/dc/dm_services_types.h | 27 +
>>>> drivers/gpu/drm/amd/display/dc/gpio/Makefile | 11 +
>>>> .../amd/display/dc/gpio/dce120/hw_factory_dce120.c | 197 +
>>>> .../amd/display/dc/gpio/dce120/hw_factory_dce120.h | 32 +
>>>> .../display/dc/gpio/dce120/hw_translate_dce120.c | 408 +
>>>> .../display/dc/gpio/dce120/hw_translate_dce120.h | 34 +
>>>> drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c | 9 +
>>>> drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c | 9 +-
>>>> drivers/gpu/drm/amd/display/dc/i2caux/Makefile | 11 +
>>>> .../amd/display/dc/i2caux/dce120/i2caux_dce120.c | 125 +
>>>> .../amd/display/dc/i2caux/dce120/i2caux_dce120.h | 32 +
>>>> drivers/gpu/drm/amd/display/dc/i2caux/i2caux.c | 8 +
>>>> .../gpu/drm/amd/display/dc/inc/bandwidth_calcs.h | 3 +
>>>> .../gpu/drm/amd/display/dc/inc/hw/display_clock.h | 23 +
>>>> drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h | 4 +
>>>> drivers/gpu/drm/amd/display/dc/irq/Makefile | 12 +
>>>> .../amd/display/dc/irq/dce120/irq_service_dce120.c | 293 +
>>>> .../amd/display/dc/irq/dce120/irq_service_dce120.h | 34 +
>>>> drivers/gpu/drm/amd/display/dc/irq/irq_service.c | 3 +
>>>> drivers/gpu/drm/amd/display/include/dal_asic_id.h | 4 +
>>>> drivers/gpu/drm/amd/display/include/dal_types.h | 3 +
>>>> drivers/gpu/drm/amd/include/amd_shared.h | 4 +
>>>> .../asic_reg/vega10/ATHUB/athub_1_0_default.h | 241 +
>>>> .../asic_reg/vega10/ATHUB/athub_1_0_offset.h | 453 +
>>>> .../asic_reg/vega10/ATHUB/athub_1_0_sh_mask.h | 2045 +
>>>> .../include/asic_reg/vega10/DC/dce_12_0_default.h | 9868 ++
>>>> .../include/asic_reg/vega10/DC/dce_12_0_offset.h | 18193 +++
>>>> .../include/asic_reg/vega10/DC/dce_12_0_sh_mask.h | 64636 +++++++++
>>>> .../include/asic_reg/vega10/GC/gc_9_0_default.h | 3873 +
>>>> .../amd/include/asic_reg/vega10/GC/gc_9_0_offset.h | 7230 +
>>>> .../include/asic_reg/vega10/GC/gc_9_0_sh_mask.h | 29868 ++++
>>>> .../include/asic_reg/vega10/HDP/hdp_4_0_default.h | 117 +
>>>> .../include/asic_reg/vega10/HDP/hdp_4_0_offset.h | 209 +
>>>> .../include/asic_reg/vega10/HDP/hdp_4_0_sh_mask.h | 601 +
>>>> .../asic_reg/vega10/MMHUB/mmhub_1_0_default.h | 1011 +
>>>> .../asic_reg/vega10/MMHUB/mmhub_1_0_offset.h | 1967 +
>>>> .../asic_reg/vega10/MMHUB/mmhub_1_0_sh_mask.h | 10127 ++
>>>> .../include/asic_reg/vega10/MP/mp_9_0_default.h | 342 +
>>>> .../amd/include/asic_reg/vega10/MP/mp_9_0_offset.h | 375 +
>>>> .../include/asic_reg/vega10/MP/mp_9_0_sh_mask.h | 1463 +
>>>> .../asic_reg/vega10/NBIF/nbif_6_1_default.h | 1271 +
>>>> .../include/asic_reg/vega10/NBIF/nbif_6_1_offset.h | 1688 +
>>>> .../asic_reg/vega10/NBIF/nbif_6_1_sh_mask.h | 10281 ++
>>>> .../asic_reg/vega10/NBIO/nbio_6_1_default.h | 22340 +++
>>>> .../include/asic_reg/vega10/NBIO/nbio_6_1_offset.h | 3649 +
>>>> .../asic_reg/vega10/NBIO/nbio_6_1_sh_mask.h | 133884
>>>> ++++++++++++++++++
>>>> .../asic_reg/vega10/OSSSYS/osssys_4_0_default.h | 176 +
>>>> .../asic_reg/vega10/OSSSYS/osssys_4_0_offset.h | 327 +
>>>> .../asic_reg/vega10/OSSSYS/osssys_4_0_sh_mask.h | 1196 +
>>>> .../asic_reg/vega10/SDMA0/sdma0_4_0_default.h | 286 +
>>>> .../asic_reg/vega10/SDMA0/sdma0_4_0_offset.h | 547 +
>>>> .../asic_reg/vega10/SDMA0/sdma0_4_0_sh_mask.h | 1852 +
>>>> .../asic_reg/vega10/SDMA1/sdma1_4_0_default.h | 282 +
>>>> .../asic_reg/vega10/SDMA1/sdma1_4_0_offset.h | 539 +
>>>> .../asic_reg/vega10/SDMA1/sdma1_4_0_sh_mask.h | 1810 +
>>>> .../asic_reg/vega10/SMUIO/smuio_9_0_default.h | 100 +
>>>> .../asic_reg/vega10/SMUIO/smuio_9_0_offset.h | 175 +
>>>> .../asic_reg/vega10/SMUIO/smuio_9_0_sh_mask.h | 258 +
>>>> .../include/asic_reg/vega10/THM/thm_9_0_default.h | 194 +
>>>> .../include/asic_reg/vega10/THM/thm_9_0_offset.h | 363 +
>>>> .../include/asic_reg/vega10/THM/thm_9_0_sh_mask.h | 1314 +
>>>> .../include/asic_reg/vega10/UVD/uvd_7_0_default.h | 127 +
>>>> .../include/asic_reg/vega10/UVD/uvd_7_0_offset.h | 222 +
>>>> .../include/asic_reg/vega10/UVD/uvd_7_0_sh_mask.h | 811 +
>>>> .../include/asic_reg/vega10/VCE/vce_4_0_default.h | 122 +
>>>> .../include/asic_reg/vega10/VCE/vce_4_0_offset.h | 208 +
>>>> .../include/asic_reg/vega10/VCE/vce_4_0_sh_mask.h | 488 +
>>>> .../gpu/drm/amd/include/asic_reg/vega10/soc15ip.h | 1343 +
>>>> .../drm/amd/include/asic_reg/vega10/vega10_enum.h | 22531 +++
>>>> drivers/gpu/drm/amd/include/atomfirmware.h | 2385 +
>>>> drivers/gpu/drm/amd/include/atomfirmwareid.h | 86 +
>>>> drivers/gpu/drm/amd/include/displayobject.h | 249 +
>>>> drivers/gpu/drm/amd/include/dm_pp_interface.h | 83 +
>>>> drivers/gpu/drm/amd/include/v9_structs.h | 743 +
>>>> drivers/gpu/drm/amd/powerplay/amd_powerplay.c | 284 +-
>>>> drivers/gpu/drm/amd/powerplay/hwmgr/Makefile | 6 +-
>>>> .../gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c | 49 +
>>>> drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c | 9 +
>>>> drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr_ppt.h | 16 +-
>>>> drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.c | 396 +
>>>> drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.h | 140 +
>>>> drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c | 4378 +
>>>> drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h | 434 +
>>>> drivers/gpu/drm/amd/powerplay/hwmgr/vega10_inc.h | 44 +
>>>> .../gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c | 137 +
>>>> .../gpu/drm/amd/powerplay/hwmgr/vega10_powertune.h | 65 +
>>>> .../gpu/drm/amd/powerplay/hwmgr/vega10_pptable.h | 331 +
>>>> .../amd/powerplay/hwmgr/vega10_processpptables.c | 1056 +
>>>> .../amd/powerplay/hwmgr/vega10_processpptables.h | 34 +
>>>> .../gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c | 761 +
>>>> .../gpu/drm/amd/powerplay/hwmgr/vega10_thermal.h | 83 +
>>>> drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h | 28 +-
>>>> .../gpu/drm/amd/powerplay/inc/hardwaremanager.h | 43 +
>>>> drivers/gpu/drm/amd/powerplay/inc/hwmgr.h | 125 +-
>>>> drivers/gpu/drm/amd/powerplay/inc/pp_instance.h | 1 +
>>>> drivers/gpu/drm/amd/powerplay/inc/pp_soc15.h | 48 +
>>>> drivers/gpu/drm/amd/powerplay/inc/smu9.h | 147 +
>>>> drivers/gpu/drm/amd/powerplay/inc/smu9_driver_if.h | 418 +
>>>> drivers/gpu/drm/amd/powerplay/inc/smumgr.h | 3 +
>>>> drivers/gpu/drm/amd/powerplay/inc/vega10_ppsmc.h | 131 +
>>>> drivers/gpu/drm/amd/powerplay/smumgr/Makefile | 2 +-
>>>> drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c | 9 +
>>>> .../gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c | 564 +
>>>> .../gpu/drm/amd/powerplay/smumgr/vega10_smumgr.h | 70 +
>>>> include/uapi/drm/amdgpu_drm.h | 29 +
>>>> 221 files changed, 403408 insertions(+), 219 deletions(-)
>>>> create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c
>>>> create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.h
>>>> create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
>>>> create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
>>>> create mode 100644 drivers/gpu/drm/amd/amdgpu/clearstate_gfx9.h
>>>> create mode 100644 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
>>>> create mode 100644 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.h
>>>> create mode 100644 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
>>>> create mode 100644 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.h
>>>> create mode 100644 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
>>>> create mode 100644 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.h
>>>> create mode 100644 drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
>>>> create mode 100644 drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.h
>>>> create mode 100644 drivers/gpu/drm/amd/amdgpu/mmsch_v1_0.h
>>>> create mode 100644 drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c
>>>> create mode 100644 drivers/gpu/drm/amd/amdgpu/mxgpu_ai.h
>>>> create mode 100644 drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c
>>>> create mode 100644 drivers/gpu/drm/amd/amdgpu/nbio_v6_1.h
>>>> create mode 100644 drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h
>>>> create mode 100644 drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
>>>> create mode 100644 drivers/gpu/drm/amd/amdgpu/psp_v3_1.h
>>>> create mode 100644 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
>>>> create mode 100644 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.h
>>>> create mode 100644 drivers/gpu/drm/amd/amdgpu/soc15.c
>>>> create mode 100644 drivers/gpu/drm/amd/amdgpu/soc15.h
>>>> create mode 100644 drivers/gpu/drm/amd/amdgpu/soc15_common.h
>>>> create mode 100644 drivers/gpu/drm/amd/amdgpu/soc15d.h
>>>> create mode 100644 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
>>>> create mode 100644 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.h
>>>> create mode 100644 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
>>>> create mode 100644 drivers/gpu/drm/amd/amdgpu/vce_v4_0.h
>>>> create mode 100644 drivers/gpu/drm/amd/amdgpu/vega10_ih.c
>>>> create mode 100644 drivers/gpu/drm/amd/amdgpu/vega10_ih.h
>>>> create mode 100644 drivers/gpu/drm/amd/amdgpu/vega10_sdma_pkt_open.h
>>>> create mode 100644 drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
>>>> create mode 100644 drivers/gpu/drm/amd/display/dc/bios/bios_parser2.h
>>>> create mode 100644
>>>> drivers/gpu/drm/amd/display/dc/bios/bios_parser_types_internal2.h
>>>> create mode 100644
>>>> drivers/gpu/drm/amd/display/dc/bios/command_table2.c
>>>> create mode 100644
>>>> drivers/gpu/drm/amd/display/dc/bios/command_table2.h
>>>> create mode 100644
>>>> drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c
>>>> create mode 100644
>>>> drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.h
>>>> create mode 100644
>>>> drivers/gpu/drm/amd/display/dc/bios/dce112/command_table_helper2_dce112.c
>>>> create mode 100644
>>>> drivers/gpu/drm/amd/display/dc/bios/dce112/command_table_helper2_dce112.h
>>>> create mode 100644 drivers/gpu/drm/amd/display/dc/dce120/Makefile
>>>> create mode 100644
>>>> drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.c
>>>> create mode 100644
>>>> drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.h
>>>> create mode 100644 drivers/gpu/drm/amd/display/dc/dce120/dce120_ipp.c
>>>> create mode 100644 drivers/gpu/drm/amd/display/dc/dce120/dce120_ipp.h
>>>> create mode 100644
>>>> drivers/gpu/drm/amd/display/dc/dce120/dce120_ipp_cursor.c
>>>> create mode 100644
>>>> drivers/gpu/drm/amd/display/dc/dce120/dce120_ipp_gamma.c
>>>> create mode 100644
>>>> drivers/gpu/drm/amd/display/dc/dce120/dce120_mem_input.c
>>>> create mode 100644
>>>> drivers/gpu/drm/amd/display/dc/dce120/dce120_mem_input.h
>>>> create mode 100644
>>>> drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c
>>>> create mode 100644
>>>> drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.h
>>>> create mode 100644
>>>> drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c
>>>> create mode 100644
>>>> drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.h
>>>> create mode 100644
>>>> drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_factory_dce120.c
>>>> create mode 100644
>>>> drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_factory_dce120.h
>>>> create mode 100644
>>>> drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c
>>>> create mode 100644
>>>> drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.h
>>>> create mode 100644
>>>> drivers/gpu/drm/amd/display/dc/i2caux/dce120/i2caux_dce120.c
>>>> create mode 100644
>>>> drivers/gpu/drm/amd/display/dc/i2caux/dce120/i2caux_dce120.h
>>>> create mode 100644
>>>> drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c
>>>> create mode 100644
>>>> drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.h
>>>> create mode 100644
>>>> drivers/gpu/drm/amd/include/asic_reg/vega10/ATHUB/athub_1_0_default.h
>>>> create mode 100644
>>>> drivers/gpu/drm/amd/include/asic_reg/vega10/ATHUB/athub_1_0_offset.h
>>>> create mode 100644
>>>> drivers/gpu/drm/amd/include/asic_reg/vega10/ATHUB/athub_1_0_sh_mask.h
>>>> create mode 100644
>>>> drivers/gpu/drm/amd/include/asic_reg/vega10/DC/dce_12_0_default.h
>>>> create mode 100644
>>>> drivers/gpu/drm/amd/include/asic_reg/vega10/DC/dce_12_0_offset.h
>>>> create mode 100644
>>>> drivers/gpu/drm/amd/include/asic_reg/vega10/DC/dce_12_0_sh_mask.h
>>>> create mode 100644
>>>> drivers/gpu/drm/amd/include/asic_reg/vega10/GC/gc_9_0_default.h
>>>> create mode 100644
>>>> drivers/gpu/drm/amd/include/asic_reg/vega10/GC/gc_9_0_offset.h
>>>> create mode 100644
>>>> drivers/gpu/drm/amd/include/asic_reg/vega10/GC/gc_9_0_sh_mask.h
>>>> create mode 100644
>>>> drivers/gpu/drm/amd/include/asic_reg/vega10/HDP/hdp_4_0_default.h
>>>> create mode 100644
>>>> drivers/gpu/drm/amd/include/asic_reg/vega10/HDP/hdp_4_0_offset.h
>>>> create mode 100644
>>>> drivers/gpu/drm/amd/include/asic_reg/vega10/HDP/hdp_4_0_sh_mask.h
>>>> create mode 100644
>>>> drivers/gpu/drm/amd/include/asic_reg/vega10/MMHUB/mmhub_1_0_default.h
>>>> create mode 100644
>>>> drivers/gpu/drm/amd/include/asic_reg/vega10/MMHUB/mmhub_1_0_offset.h
>>>> create mode 100644
>>>> drivers/gpu/drm/amd/include/asic_reg/vega10/MMHUB/mmhub_1_0_sh_mask.h
>>>> create mode 100644
>>>> drivers/gpu/drm/amd/include/asic_reg/vega10/MP/mp_9_0_default.h
>>>> create mode 100644
>>>> drivers/gpu/drm/amd/include/asic_reg/vega10/MP/mp_9_0_offset.h
>>>> create mode 100644
>>>> drivers/gpu/drm/amd/include/asic_reg/vega10/MP/mp_9_0_sh_mask.h
>>>> create mode 100644
>>>> drivers/gpu/drm/amd/include/asic_reg/vega10/NBIF/nbif_6_1_default.h
>>>> create mode 100644
>>>> drivers/gpu/drm/amd/include/asic_reg/vega10/NBIF/nbif_6_1_offset.h
>>>> create mode 100644
>>>> drivers/gpu/drm/amd/include/asic_reg/vega10/NBIF/nbif_6_1_sh_mask.h
>>>> create mode 100644
>>>> drivers/gpu/drm/amd/include/asic_reg/vega10/NBIO/nbio_6_1_default.h
>>>> create mode 100644
>>>> drivers/gpu/drm/amd/include/asic_reg/vega10/NBIO/nbio_6_1_offset.h
>>>> create mode 100644
>>>> drivers/gpu/drm/amd/include/asic_reg/vega10/NBIO/nbio_6_1_sh_mask.h
>>>> create mode 100644
>>>> drivers/gpu/drm/amd/include/asic_reg/vega10/OSSSYS/osssys_4_0_default.h
>>>> create mode 100644
>>>> drivers/gpu/drm/amd/include/asic_reg/vega10/OSSSYS/osssys_4_0_offset.h
>>>> create mode 100644
>>>> drivers/gpu/drm/amd/include/asic_reg/vega10/OSSSYS/osssys_4_0_sh_mask.h
>>>> create mode 100644
>>>> drivers/gpu/drm/amd/include/asic_reg/vega10/SDMA0/sdma0_4_0_default.h
>>>> create mode 100644
>>>> drivers/gpu/drm/amd/include/asic_reg/vega10/SDMA0/sdma0_4_0_offset.h
>>>> create mode 100644
>>>> drivers/gpu/drm/amd/include/asic_reg/vega10/SDMA0/sdma0_4_0_sh_mask.h
>>>> create mode 100644
>>>> drivers/gpu/drm/amd/include/asic_reg/vega10/SDMA1/sdma1_4_0_default.h
>>>> create mode 100644
>>>> drivers/gpu/drm/amd/include/asic_reg/vega10/SDMA1/sdma1_4_0_offset.h
>>>> create mode 100644
>>>> drivers/gpu/drm/amd/include/asic_reg/vega10/SDMA1/sdma1_4_0_sh_mask.h
>>>> create mode 100644
>>>> drivers/gpu/drm/amd/include/asic_reg/vega10/SMUIO/smuio_9_0_default.h
>>>> create mode 100644
>>>> drivers/gpu/drm/amd/include/asic_reg/vega10/SMUIO/smuio_9_0_offset.h
>>>> create mode 100644
>>>> drivers/gpu/drm/amd/include/asic_reg/vega10/SMUIO/smuio_9_0_sh_mask.h
>>>> create mode 100644
>>>> drivers/gpu/drm/amd/include/asic_reg/vega10/THM/thm_9_0_default.h
>>>> create mode 100644
>>>> drivers/gpu/drm/amd/include/asic_reg/vega10/THM/thm_9_0_offset.h
>>>> create mode 100644
>>>> drivers/gpu/drm/amd/include/asic_reg/vega10/THM/thm_9_0_sh_mask.h
>>>> create mode 100644
>>>> drivers/gpu/drm/amd/include/asic_reg/vega10/UVD/uvd_7_0_default.h
>>>> create mode 100644
>>>> drivers/gpu/drm/amd/include/asic_reg/vega10/UVD/uvd_7_0_offset.h
>>>> create mode 100644
>>>> drivers/gpu/drm/amd/include/asic_reg/vega10/UVD/uvd_7_0_sh_mask.h
>>>> create mode 100644
>>>> drivers/gpu/drm/amd/include/asic_reg/vega10/VCE/vce_4_0_default.h
>>>> create mode 100644
>>>> drivers/gpu/drm/amd/include/asic_reg/vega10/VCE/vce_4_0_offset.h
>>>> create mode 100644
>>>> drivers/gpu/drm/amd/include/asic_reg/vega10/VCE/vce_4_0_sh_mask.h
>>>> create mode 100644
>>>> drivers/gpu/drm/amd/include/asic_reg/vega10/soc15ip.h
>>>> create mode 100644
>>>> drivers/gpu/drm/amd/include/asic_reg/vega10/vega10_enum.h
>>>> create mode 100644 drivers/gpu/drm/amd/include/atomfirmware.h
>>>> create mode 100644 drivers/gpu/drm/amd/include/atomfirmwareid.h
>>>> create mode 100644 drivers/gpu/drm/amd/include/displayobject.h
>>>> create mode 100644 drivers/gpu/drm/amd/include/dm_pp_interface.h
>>>> create mode 100644 drivers/gpu/drm/amd/include/v9_structs.h
>>>> create mode 100644 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.c
>>>> create mode 100644 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.h
>>>> create mode 100644 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
>>>> create mode 100644 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h
>>>> create mode 100644 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_inc.h
>>>> create mode 100644
>>>> drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c
>>>> create mode 100644
>>>> drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.h
>>>> create mode 100644
>>>> drivers/gpu/drm/amd/powerplay/hwmgr/vega10_pptable.h
>>>> create mode 100644
>>>> drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c
>>>> create mode 100644
>>>> drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.h
>>>> create mode 100644
>>>> drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c
>>>> create mode 100644
>>>> drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.h
>>>> create mode 100644 drivers/gpu/drm/amd/powerplay/inc/pp_soc15.h
>>>> create mode 100644 drivers/gpu/drm/amd/powerplay/inc/smu9.h
>>>> create mode 100644 drivers/gpu/drm/amd/powerplay/inc/smu9_driver_if.h
>>>> create mode 100644 drivers/gpu/drm/amd/powerplay/inc/vega10_ppsmc.h
>>>> create mode 100644
>>>> drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c
>>>> create mode 100644
>>>> drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.h
>>>>
>>>
>>> _______________________________________________
>>> amd-gfx mailing list
>>> amd-gfx@lists.freedesktop.org
>>> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
>>
>>
>>
>> _______________________________________________
>> amd-gfx mailing list
>> amd-gfx@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
>
>
>
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH 000/100] Add Vega10 Support
[not found] ` <b717602f-7573-6c20-ca68-491e3fe847c0-ANTagKRnAhcb1SvskN2V4Q@public.gmane.org>
@ 2017-03-21 12:18 ` Christian König
[not found] ` <15b7d1b4-8ac7-d14b-40f6-aba529b301ea-ANTagKRnAhcb1SvskN2V4Q@public.gmane.org>
0 siblings, 1 reply; 16+ messages in thread
From: Christian König @ 2017-03-21 12:18 UTC (permalink / raw)
To: Alex Deucher, amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Alex Deucher
In my Spam folder I've found:
Patches #22, #24, #39, #50, #64, #69, #75, #78 which are Acked-by:
Christian König <christian.koenig@amd.com>.
Patches #32, #42 which are Reviewed-by: Christian König
<christian.koenig@amd.com>.
And patches #80, #85, #89, #90, #91, #100 which already had either my rb
or ackb.
So still missing are #6-#20 which are probably just to large for the list.
Regards,
Christian.
Am 21.03.2017 um 12:51 schrieb Christian König:
> Patches #48, #49, #52-#63, #65-#68, #70-#72, #74, #76, #77, #79,
> #81-#84 are Acked-by: Christian König <christian.koenig@amd.com>.
>
> Patches #50, #64, #69, #75, #78, #80, #85, #89-#91, #100 didn't made
> it to the list.
>
> Patch #73 probably needs to be moved to the end of the set or at least
> after the wptr_poll fix.
>
> Apart from those everything should already have my reviewed-by or
> acked-by.
>
> What worries me a bit are the ones who didn't made it to the list.
> Going to check my spam folder, but that is a bit disturbing.
>
> Regards,
> Christian.
>
> Am 21.03.2017 um 08:42 schrieb Christian König:
>> Patches #1 - #5, #21, #23, #25, #27, #28, #31, #35-#38, #40, #41, #45
>> are Acked-by: Christian König.
>>
>> Patches #6-#20, #22, #24, #32, #39, #42 didn't made it to the list
>> (probably to large).
>>
>> Patches #43, #44 are Reviewed-by: Christian König
>> <christian.koenig@amd.com>.
>>
>> Patch #26: That stuff actually belongs into vega10 specifc code,
>> doesn't it?
>>
>> Patch #29: We shouldn't use typedefs for enums.
>>
>> Going to take a look at the rest later today,
>> Christian.
>>
>> Am 20.03.2017 um 21:29 schrieb Alex Deucher:
>>> This patch set adds support for vega10. Major changes and supported
>>> features:
>>> - new vbios interface
>>> - Lots of new hw IPs
>>> - Support for video decode using UVD
>>> - Support for video encode using VCE
>>> - Support for 3D via radeonsi
>>> - Power management
>>> - Full display support via DC
>>> - Support for SR-IOV
>>>
>>> I did not send out the register headers since they are huge. You can
>>> find them
>>> along with all the other patches in this series here:
>>> https://cgit.freedesktop.org/~agd5f/linux/log/?h=amd-staging-4.9
>>>
>>> Please review.
>>>
>>> Thanks,
>>>
>>> Alex
>>>
>>> Alex Deucher (29):
>>> drm/amdgpu: add the new atomfirmware interface header
>>> amdgpu: detect if we are using atomfirm or atombios for vbios (v2)
>>> drm/amdgpu: move atom scratch setup into amdgpu_atombios.c
>>> drm/amdgpu: add basic support for atomfirmware.h (v3)
>>> drm/amdgpu: add soc15ip.h
>>> drm/amdgpu: add vega10_enum.h
>>> drm/amdgpu: Add ATHUB 1.0 register headers
>>> drm/amdgpu: Add the DCE 12.0 register headers
>>> drm/amdgpu: add the GC 9.0 register headers
>>> drm/amdgpu: add the HDP 4.0 register headers
>>> drm/amdgpu: add the MMHUB 1.0 register headers
>>> drm/amdgpu: add MP 9.0 register headers
>>> drm/amdgpu: add NBIF 6.1 register headers
>>> drm/amdgpu: add NBIO 6.1 register headers
>>> drm/amdgpu: add OSSSYS 4.0 register headers
>>> drm/amdgpu: add SDMA 4.0 register headers
>>> drm/amdgpu: add SMUIO 9.0 register headers
>>> drm/amdgpu: add THM 9.0 register headers
>>> drm/amdgpu: add the UVD 7.0 register headers
>>> drm/amdgpu: add the VCE 4.0 register headers
>>> drm/amdgpu: add gfx9 clearstate header
>>> drm/amdgpu: add SDMA 4.0 packet header
>>> drm/amdgpu: use atomfirmware interfaces for scratch reg save/restore
>>> drm/amdgpu: update IH IV ring entry for soc-15
>>> drm/amdgpu: add PTE defines for MTYPE
>>> drm/amdgpu: add NGG parameters
>>> drm/amdgpu: Add asic family for vega10
>>> drm/amdgpu: add tiling flags for GFX9
>>> drm/amdgpu: gart fixes for vega10
>>>
>>> Alex Xie (4):
>>> drm/amdgpu: Add MTYPE flags to GPU VM IOCTL interface
>>> drm/amdgpu: handle PTE EXEC in amdgpu_vm_bo_split_mapping
>>> drm/amdgpu: handle PTE MTYPE in amdgpu_vm_bo_split_mapping
>>> drm/amdgpu: Add GMC 9.0 support
>>>
>>> Andrey Grodzovsky (1):
>>> drm/amdgpu: gb_addr_config struct
>>>
>>> Charlene Liu (1):
>>> drm/amd/display: need to handle DCE_Info table ver4.2
>>>
>>> Christian König (1):
>>> drm/amdgpu: add IV trace point
>>>
>>> Eric Huang (7):
>>> drm/amd/powerplay: add smu9 header files for Vega10
>>> drm/amd/powerplay: add new Vega10's ppsmc header file
>>> drm/amdgpu: add new atomfirmware based helpers for powerplay
>>> drm/amd/powerplay: add some new structures for Vega10
>>> drm/amd: add structures for display/powerplay interface
>>> drm/amd/powerplay: add some display/powerplay interfaces
>>> drm/amd/powerplay: add Vega10 powerplay support
>>>
>>> Felix Kuehling (1):
>>> drm/amd: Add MQD structs for GFX V9
>>>
>>> Harry Wentland (6):
>>> drm/amd/display: Add DCE12 bios parser support
>>> drm/amd/display: Add DCE12 gpio support
>>> drm/amd/display: Add DCE12 i2c/aux support
>>> drm/amd/display: Add DCE12 irq support
>>> drm/amd/display: Add DCE12 core support
>>> drm/amd/display: Enable DCE12 support
>>>
>>> Huang Rui (6):
>>> drm/amdgpu: use new flag to handle different firmware loading method
>>> drm/amdgpu: rework common ucode handling for vega10
>>> drm/amdgpu: add psp firmware header info
>>> drm/amdgpu: add PSP driver for vega10
>>> drm/amdgpu: add psp firmware info into info query and debugfs
>>> drm/amdgpu: add SMC firmware into global ucode list for psp loading
>>>
>>> Jordan Lazare (1):
>>> drm/amd/display: Less log spam
>>>
>>> Junwei Zhang (2):
>>> drm/amdgpu: add NBIO 6.1 driver
>>> drm/amdgpu: add Vega10 Device IDs
>>>
>>> Ken Wang (8):
>>> drm/amdgpu: add common soc15 headers
>>> drm/amdgpu: add vega10 chip name
>>> drm/amdgpu: add 64bit doorbell assignments
>>> drm/amdgpu: add SDMA v4.0 implementation
>>> drm/amdgpu: implement GFX 9.0 support
>>> drm/amdgpu: add vega10 interrupt handler
>>> drm/amdgpu: soc15 enable (v2)
>>> drm/amdgpu: Set the IP blocks for vega10
>>>
>>> Leo Liu (2):
>>> drm/amdgpu: add initial uvd 7.0 support for vega10
>>> drm/amdgpu: add initial vce 4.0 support for vega10
>>>
>>> Marek Olšák (1):
>>> drm/amdgpu: don't validate TILE_SPLIT on GFX9
>>>
>>> Monk Liu (5):
>>> drm/amdgpu/gfx9: programing wptr_poll_addr register
>>> drm/amdgpu:impl gfx9 cond_exec
>>> drm/amdgpu:bypass RLC init for SRIOV
>>> drm/amdgpu/sdma4:re-org SDMA initial steps for sriov
>>> drm/amdgpu/vega10:fix DOORBELL64 scheme
>>>
>>> Rex Zhu (2):
>>> drm/amdgpu: get display info from DC when DC enabled.
>>> drm/amd/powerplay: add global PowerPlay mutex.
>>>
>>> Xiangliang Yu (22):
>>> drm/amdgpu: impl sriov detection for vega10
>>> drm/amdgpu: add kiq ring for gfx9
>>> drm/amdgpu/gfx9: fullfill kiq funcs
>>> drm/amdgpu/gfx9: fullfill kiq irq funcs
>>> drm/amdgpu: init kiq and kcq for vega10
>>> drm/amdgpu/gfx9: impl gfx9 meta data emit
>>> drm/amdgpu/soc15: bypass PSP for VF
>>> drm/amdgpu/gmc9: no need use kiq in vega10 tlb flush
>>> drm/amdgpu/dce_virtual: bypass DPM for vf
>>> drm/amdgpu/virt: impl mailbox for ai
>>> drm/amdgpu/soc15: init virt ops for vf
>>> drm/amdgpu/soc15: enable virtual dce for vf
>>> drm/amdgpu: Don't touch PG&CG for SRIOV MM
>>> drm/amdgpu/vce4: enable doorbell for SRIOV
>>> drm/amdgpu: disable uvd for sriov
>>> drm/amdgpu/soc15: bypass pp block for vf
>>> drm/amdgpu/virt: add structure for MM table
>>> drm/amdgpu/vce4: alloc mm table for MM sriov
>>> drm/amdgpu/vce4: Ignore vce ring/ib test temporarily
>>> drm/amdgpu: add mmsch structures
>>> drm/amdgpu/vce4: impl vce & mmsch sriov start
>>> drm/amdgpu/gfx9: correct wptr pointer value
>>>
>>> ken (1):
>>> drm/amdgpu: add clinetid definition for vega10
>>>
>>> drivers/gpu/drm/amd/amdgpu/Makefile | 27 +-
>>> drivers/gpu/drm/amd/amdgpu/amdgpu.h | 172 +-
>>> drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c | 28 +
>>> drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.h | 3 +
>>> drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c | 112 +
>>> drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.h | 33 +
>>> drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c | 30 +-
>>> drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c | 73 +-
>>> drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 73 +-
>>> drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 36 +-
>>> drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c | 3 +-
>>> drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 2 +-
>>> drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h | 47 +-
>>> drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c | 3 +
>>> drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 32 +
>>> drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 5 +-
>>> drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c | 5 +-
>>> drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 473 +
>>> drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h | 127 +
>>> drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h | 37 +
>>> drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c | 113 +-
>>> drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h | 17 +
>>> drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c | 58 +-
>>> drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c | 21 +
>>> drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h | 7 +
>>> drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 34 +-
>>> drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h | 4 +
>>> drivers/gpu/drm/amd/amdgpu/atom.c | 26 -
>>> drivers/gpu/drm/amd/amdgpu/atom.h | 1 -
>>> drivers/gpu/drm/amd/amdgpu/cik.c | 2 +
>>> drivers/gpu/drm/amd/amdgpu/clearstate_gfx9.h | 941 +
>>> drivers/gpu/drm/amd/amdgpu/dce_virtual.c | 3 +
>>> drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 6 +-
>>> drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 4075 +
>>> drivers/gpu/drm/amd/amdgpu/gfx_v9_0.h | 35 +
>>> drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c | 447 +
>>> drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.h | 35 +
>>> drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 826 +
>>> drivers/gpu/drm/amd/amdgpu/gmc_v9_0.h | 30 +
>>> drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c | 585 +
>>> drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.h | 35 +
>>> drivers/gpu/drm/amd/amdgpu/mmsch_v1_0.h | 87 +
>>> drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c | 207 +
>>> drivers/gpu/drm/amd/amdgpu/mxgpu_ai.h | 47 +
>>> drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c | 251 +
>>> drivers/gpu/drm/amd/amdgpu/nbio_v6_1.h | 53 +
>>> drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h | 269 +
>>> drivers/gpu/drm/amd/amdgpu/psp_v3_1.c | 507 +
>>> drivers/gpu/drm/amd/amdgpu/psp_v3_1.h | 50 +
>>> drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c | 4 +-
>>> drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 4 +-
>>> drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 1573 +
>>> drivers/gpu/drm/amd/amdgpu/sdma_v4_0.h | 30 +
>>> drivers/gpu/drm/amd/amdgpu/soc15.c | 825 +
>>> drivers/gpu/drm/amd/amdgpu/soc15.h | 35 +
>>> drivers/gpu/drm/amd/amdgpu/soc15_common.h | 57 +
>>> drivers/gpu/drm/amd/amdgpu/soc15d.h | 287 +
>>> drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c | 1543 +
>>> drivers/gpu/drm/amd/amdgpu/uvd_v7_0.h | 29 +
>>> drivers/gpu/drm/amd/amdgpu/vce_v4_0.c | 1141 +
>>> drivers/gpu/drm/amd/amdgpu/vce_v4_0.h | 29 +
>>> drivers/gpu/drm/amd/amdgpu/vega10_ih.c | 424 +
>>> drivers/gpu/drm/amd/amdgpu/vega10_ih.h | 30 +
>>> drivers/gpu/drm/amd/amdgpu/vega10_sdma_pkt_open.h | 3335 +
>>> drivers/gpu/drm/amd/amdgpu/vi.c | 4 +-
>>> drivers/gpu/drm/amd/display/Kconfig | 7 +
>>> drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 145 +-
>>> .../drm/amd/display/amdgpu_dm/amdgpu_dm_services.c | 10 +
>>> .../drm/amd/display/amdgpu_dm/amdgpu_dm_types.c | 20 +-
>>> drivers/gpu/drm/amd/display/dc/Makefile | 4 +
>>> drivers/gpu/drm/amd/display/dc/bios/Makefile | 8 +
>>> drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c | 2162 +
>>> drivers/gpu/drm/amd/display/dc/bios/bios_parser2.h | 33 +
>>> .../amd/display/dc/bios/bios_parser_interface.c | 14 +
>>> .../display/dc/bios/bios_parser_types_internal2.h | 74 +
>>> .../gpu/drm/amd/display/dc/bios/command_table2.c | 813 +
>>> .../gpu/drm/amd/display/dc/bios/command_table2.h | 105 +
>>> .../amd/display/dc/bios/command_table_helper2.c | 260 +
>>> .../amd/display/dc/bios/command_table_helper2.h | 82 +
>>> .../dc/bios/dce112/command_table_helper2_dce112.c | 418 +
>>> .../dc/bios/dce112/command_table_helper2_dce112.h | 34 +
>>> drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c | 117 +
>>> drivers/gpu/drm/amd/display/dc/core/dc.c | 29 +
>>> drivers/gpu/drm/amd/display/dc/core/dc_debug.c | 11 +
>>> drivers/gpu/drm/amd/display/dc/core/dc_link.c | 19 +
>>> drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 14 +
>>> drivers/gpu/drm/amd/display/dc/dc.h | 27 +
>>> drivers/gpu/drm/amd/display/dc/dc_hw_types.h | 46 +
>>> .../gpu/drm/amd/display/dc/dce/dce_clock_source.c | 6 +
>>> drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c | 149 +
>>> drivers/gpu/drm/amd/display/dc/dce/dce_clocks.h | 20 +
>>> drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h | 8 +
>>> .../gpu/drm/amd/display/dc/dce/dce_link_encoder.h | 14 +
>>> drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c | 35 +
>>> drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h | 34 +
>>> drivers/gpu/drm/amd/display/dc/dce/dce_opp.h | 72 +
>>> .../drm/amd/display/dc/dce/dce_stream_encoder.h | 100 +
>>> drivers/gpu/drm/amd/display/dc/dce/dce_transform.h | 68 +
>>> .../amd/display/dc/dce110/dce110_hw_sequencer.c | 53 +-
>>> .../drm/amd/display/dc/dce110/dce110_mem_input.c | 3 +
>>> .../display/dc/dce110/dce110_timing_generator.h | 3 +
>>> drivers/gpu/drm/amd/display/dc/dce120/Makefile | 12 +
>>> .../amd/display/dc/dce120/dce120_hw_sequencer.c | 197 +
>>> .../amd/display/dc/dce120/dce120_hw_sequencer.h | 36 +
>>> drivers/gpu/drm/amd/display/dc/dce120/dce120_ipp.c | 58 +
>>> drivers/gpu/drm/amd/display/dc/dce120/dce120_ipp.h | 62 +
>>> .../drm/amd/display/dc/dce120/dce120_ipp_cursor.c | 202 +
>>> .../drm/amd/display/dc/dce120/dce120_ipp_gamma.c | 167 +
>>> .../drm/amd/display/dc/dce120/dce120_mem_input.c | 340 +
>>> .../drm/amd/display/dc/dce120/dce120_mem_input.h | 37 +
>>> .../drm/amd/display/dc/dce120/dce120_resource.c | 1099 +
>>> .../drm/amd/display/dc/dce120/dce120_resource.h | 39 +
>>> .../display/dc/dce120/dce120_timing_generator.c | 1109 +
>>> .../display/dc/dce120/dce120_timing_generator.h | 41 +
>>> .../gpu/drm/amd/display/dc/dce80/dce80_mem_input.c | 3 +
>>> drivers/gpu/drm/amd/display/dc/dm_services.h | 89 +
>>> drivers/gpu/drm/amd/display/dc/dm_services_types.h | 27 +
>>> drivers/gpu/drm/amd/display/dc/gpio/Makefile | 11 +
>>> .../amd/display/dc/gpio/dce120/hw_factory_dce120.c | 197 +
>>> .../amd/display/dc/gpio/dce120/hw_factory_dce120.h | 32 +
>>> .../display/dc/gpio/dce120/hw_translate_dce120.c | 408 +
>>> .../display/dc/gpio/dce120/hw_translate_dce120.h | 34 +
>>> drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c | 9 +
>>> drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c | 9 +-
>>> drivers/gpu/drm/amd/display/dc/i2caux/Makefile | 11 +
>>> .../amd/display/dc/i2caux/dce120/i2caux_dce120.c | 125 +
>>> .../amd/display/dc/i2caux/dce120/i2caux_dce120.h | 32 +
>>> drivers/gpu/drm/amd/display/dc/i2caux/i2caux.c | 8 +
>>> .../gpu/drm/amd/display/dc/inc/bandwidth_calcs.h | 3 +
>>> .../gpu/drm/amd/display/dc/inc/hw/display_clock.h | 23 +
>>> drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h | 4 +
>>> drivers/gpu/drm/amd/display/dc/irq/Makefile | 12 +
>>> .../amd/display/dc/irq/dce120/irq_service_dce120.c | 293 +
>>> .../amd/display/dc/irq/dce120/irq_service_dce120.h | 34 +
>>> drivers/gpu/drm/amd/display/dc/irq/irq_service.c | 3 +
>>> drivers/gpu/drm/amd/display/include/dal_asic_id.h | 4 +
>>> drivers/gpu/drm/amd/display/include/dal_types.h | 3 +
>>> drivers/gpu/drm/amd/include/amd_shared.h | 4 +
>>> .../asic_reg/vega10/ATHUB/athub_1_0_default.h | 241 +
>>> .../asic_reg/vega10/ATHUB/athub_1_0_offset.h | 453 +
>>> .../asic_reg/vega10/ATHUB/athub_1_0_sh_mask.h | 2045 +
>>> .../include/asic_reg/vega10/DC/dce_12_0_default.h | 9868 ++
>>> .../include/asic_reg/vega10/DC/dce_12_0_offset.h | 18193 +++
>>> .../include/asic_reg/vega10/DC/dce_12_0_sh_mask.h | 64636 +++++++++
>>> .../include/asic_reg/vega10/GC/gc_9_0_default.h | 3873 +
>>> .../amd/include/asic_reg/vega10/GC/gc_9_0_offset.h | 7230 +
>>> .../include/asic_reg/vega10/GC/gc_9_0_sh_mask.h | 29868 ++++
>>> .../include/asic_reg/vega10/HDP/hdp_4_0_default.h | 117 +
>>> .../include/asic_reg/vega10/HDP/hdp_4_0_offset.h | 209 +
>>> .../include/asic_reg/vega10/HDP/hdp_4_0_sh_mask.h | 601 +
>>> .../asic_reg/vega10/MMHUB/mmhub_1_0_default.h | 1011 +
>>> .../asic_reg/vega10/MMHUB/mmhub_1_0_offset.h | 1967 +
>>> .../asic_reg/vega10/MMHUB/mmhub_1_0_sh_mask.h | 10127 ++
>>> .../include/asic_reg/vega10/MP/mp_9_0_default.h | 342 +
>>> .../amd/include/asic_reg/vega10/MP/mp_9_0_offset.h | 375 +
>>> .../include/asic_reg/vega10/MP/mp_9_0_sh_mask.h | 1463 +
>>> .../asic_reg/vega10/NBIF/nbif_6_1_default.h | 1271 +
>>> .../include/asic_reg/vega10/NBIF/nbif_6_1_offset.h | 1688 +
>>> .../asic_reg/vega10/NBIF/nbif_6_1_sh_mask.h | 10281 ++
>>> .../asic_reg/vega10/NBIO/nbio_6_1_default.h | 22340 +++
>>> .../include/asic_reg/vega10/NBIO/nbio_6_1_offset.h | 3649 +
>>> .../asic_reg/vega10/NBIO/nbio_6_1_sh_mask.h | 133884
>>> ++++++++++++++++++
>>> .../asic_reg/vega10/OSSSYS/osssys_4_0_default.h | 176 +
>>> .../asic_reg/vega10/OSSSYS/osssys_4_0_offset.h | 327 +
>>> .../asic_reg/vega10/OSSSYS/osssys_4_0_sh_mask.h | 1196 +
>>> .../asic_reg/vega10/SDMA0/sdma0_4_0_default.h | 286 +
>>> .../asic_reg/vega10/SDMA0/sdma0_4_0_offset.h | 547 +
>>> .../asic_reg/vega10/SDMA0/sdma0_4_0_sh_mask.h | 1852 +
>>> .../asic_reg/vega10/SDMA1/sdma1_4_0_default.h | 282 +
>>> .../asic_reg/vega10/SDMA1/sdma1_4_0_offset.h | 539 +
>>> .../asic_reg/vega10/SDMA1/sdma1_4_0_sh_mask.h | 1810 +
>>> .../asic_reg/vega10/SMUIO/smuio_9_0_default.h | 100 +
>>> .../asic_reg/vega10/SMUIO/smuio_9_0_offset.h | 175 +
>>> .../asic_reg/vega10/SMUIO/smuio_9_0_sh_mask.h | 258 +
>>> .../include/asic_reg/vega10/THM/thm_9_0_default.h | 194 +
>>> .../include/asic_reg/vega10/THM/thm_9_0_offset.h | 363 +
>>> .../include/asic_reg/vega10/THM/thm_9_0_sh_mask.h | 1314 +
>>> .../include/asic_reg/vega10/UVD/uvd_7_0_default.h | 127 +
>>> .../include/asic_reg/vega10/UVD/uvd_7_0_offset.h | 222 +
>>> .../include/asic_reg/vega10/UVD/uvd_7_0_sh_mask.h | 811 +
>>> .../include/asic_reg/vega10/VCE/vce_4_0_default.h | 122 +
>>> .../include/asic_reg/vega10/VCE/vce_4_0_offset.h | 208 +
>>> .../include/asic_reg/vega10/VCE/vce_4_0_sh_mask.h | 488 +
>>> .../gpu/drm/amd/include/asic_reg/vega10/soc15ip.h | 1343 +
>>> .../drm/amd/include/asic_reg/vega10/vega10_enum.h | 22531 +++
>>> drivers/gpu/drm/amd/include/atomfirmware.h | 2385 +
>>> drivers/gpu/drm/amd/include/atomfirmwareid.h | 86 +
>>> drivers/gpu/drm/amd/include/displayobject.h | 249 +
>>> drivers/gpu/drm/amd/include/dm_pp_interface.h | 83 +
>>> drivers/gpu/drm/amd/include/v9_structs.h | 743 +
>>> drivers/gpu/drm/amd/powerplay/amd_powerplay.c | 284 +-
>>> drivers/gpu/drm/amd/powerplay/hwmgr/Makefile | 6 +-
>>> .../gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c | 49 +
>>> drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c | 9 +
>>> drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr_ppt.h | 16 +-
>>> drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.c | 396 +
>>> drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.h | 140 +
>>> drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c | 4378 +
>>> drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h | 434 +
>>> drivers/gpu/drm/amd/powerplay/hwmgr/vega10_inc.h | 44 +
>>> .../gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c | 137 +
>>> .../gpu/drm/amd/powerplay/hwmgr/vega10_powertune.h | 65 +
>>> .../gpu/drm/amd/powerplay/hwmgr/vega10_pptable.h | 331 +
>>> .../amd/powerplay/hwmgr/vega10_processpptables.c | 1056 +
>>> .../amd/powerplay/hwmgr/vega10_processpptables.h | 34 +
>>> .../gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c | 761 +
>>> .../gpu/drm/amd/powerplay/hwmgr/vega10_thermal.h | 83 +
>>> drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h | 28 +-
>>> .../gpu/drm/amd/powerplay/inc/hardwaremanager.h | 43 +
>>> drivers/gpu/drm/amd/powerplay/inc/hwmgr.h | 125 +-
>>> drivers/gpu/drm/amd/powerplay/inc/pp_instance.h | 1 +
>>> drivers/gpu/drm/amd/powerplay/inc/pp_soc15.h | 48 +
>>> drivers/gpu/drm/amd/powerplay/inc/smu9.h | 147 +
>>> drivers/gpu/drm/amd/powerplay/inc/smu9_driver_if.h | 418 +
>>> drivers/gpu/drm/amd/powerplay/inc/smumgr.h | 3 +
>>> drivers/gpu/drm/amd/powerplay/inc/vega10_ppsmc.h | 131 +
>>> drivers/gpu/drm/amd/powerplay/smumgr/Makefile | 2 +-
>>> drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c | 9 +
>>> .../gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c | 564 +
>>> .../gpu/drm/amd/powerplay/smumgr/vega10_smumgr.h | 70 +
>>> include/uapi/drm/amdgpu_drm.h | 29 +
>>> 221 files changed, 403408 insertions(+), 219 deletions(-)
>>> create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c
>>> create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.h
>>> create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
>>> create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
>>> create mode 100644 drivers/gpu/drm/amd/amdgpu/clearstate_gfx9.h
>>> create mode 100644 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
>>> create mode 100644 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.h
>>> create mode 100644 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
>>> create mode 100644 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.h
>>> create mode 100644 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
>>> create mode 100644 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.h
>>> create mode 100644 drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
>>> create mode 100644 drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.h
>>> create mode 100644 drivers/gpu/drm/amd/amdgpu/mmsch_v1_0.h
>>> create mode 100644 drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c
>>> create mode 100644 drivers/gpu/drm/amd/amdgpu/mxgpu_ai.h
>>> create mode 100644 drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c
>>> create mode 100644 drivers/gpu/drm/amd/amdgpu/nbio_v6_1.h
>>> create mode 100644 drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h
>>> create mode 100644 drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
>>> create mode 100644 drivers/gpu/drm/amd/amdgpu/psp_v3_1.h
>>> create mode 100644 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
>>> create mode 100644 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.h
>>> create mode 100644 drivers/gpu/drm/amd/amdgpu/soc15.c
>>> create mode 100644 drivers/gpu/drm/amd/amdgpu/soc15.h
>>> create mode 100644 drivers/gpu/drm/amd/amdgpu/soc15_common.h
>>> create mode 100644 drivers/gpu/drm/amd/amdgpu/soc15d.h
>>> create mode 100644 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
>>> create mode 100644 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.h
>>> create mode 100644 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
>>> create mode 100644 drivers/gpu/drm/amd/amdgpu/vce_v4_0.h
>>> create mode 100644 drivers/gpu/drm/amd/amdgpu/vega10_ih.c
>>> create mode 100644 drivers/gpu/drm/amd/amdgpu/vega10_ih.h
>>> create mode 100644 drivers/gpu/drm/amd/amdgpu/vega10_sdma_pkt_open.h
>>> create mode 100644 drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
>>> create mode 100644 drivers/gpu/drm/amd/display/dc/bios/bios_parser2.h
>>> create mode 100644
>>> drivers/gpu/drm/amd/display/dc/bios/bios_parser_types_internal2.h
>>> create mode 100644
>>> drivers/gpu/drm/amd/display/dc/bios/command_table2.c
>>> create mode 100644
>>> drivers/gpu/drm/amd/display/dc/bios/command_table2.h
>>> create mode 100644
>>> drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c
>>> create mode 100644
>>> drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.h
>>> create mode 100644
>>> drivers/gpu/drm/amd/display/dc/bios/dce112/command_table_helper2_dce112.c
>>> create mode 100644
>>> drivers/gpu/drm/amd/display/dc/bios/dce112/command_table_helper2_dce112.h
>>> create mode 100644 drivers/gpu/drm/amd/display/dc/dce120/Makefile
>>> create mode 100644
>>> drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.c
>>> create mode 100644
>>> drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.h
>>> create mode 100644 drivers/gpu/drm/amd/display/dc/dce120/dce120_ipp.c
>>> create mode 100644 drivers/gpu/drm/amd/display/dc/dce120/dce120_ipp.h
>>> create mode 100644
>>> drivers/gpu/drm/amd/display/dc/dce120/dce120_ipp_cursor.c
>>> create mode 100644
>>> drivers/gpu/drm/amd/display/dc/dce120/dce120_ipp_gamma.c
>>> create mode 100644
>>> drivers/gpu/drm/amd/display/dc/dce120/dce120_mem_input.c
>>> create mode 100644
>>> drivers/gpu/drm/amd/display/dc/dce120/dce120_mem_input.h
>>> create mode 100644
>>> drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c
>>> create mode 100644
>>> drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.h
>>> create mode 100644
>>> drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c
>>> create mode 100644
>>> drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.h
>>> create mode 100644
>>> drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_factory_dce120.c
>>> create mode 100644
>>> drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_factory_dce120.h
>>> create mode 100644
>>> drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c
>>> create mode 100644
>>> drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.h
>>> create mode 100644
>>> drivers/gpu/drm/amd/display/dc/i2caux/dce120/i2caux_dce120.c
>>> create mode 100644
>>> drivers/gpu/drm/amd/display/dc/i2caux/dce120/i2caux_dce120.h
>>> create mode 100644
>>> drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c
>>> create mode 100644
>>> drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.h
>>> create mode 100644
>>> drivers/gpu/drm/amd/include/asic_reg/vega10/ATHUB/athub_1_0_default.h
>>> create mode 100644
>>> drivers/gpu/drm/amd/include/asic_reg/vega10/ATHUB/athub_1_0_offset.h
>>> create mode 100644
>>> drivers/gpu/drm/amd/include/asic_reg/vega10/ATHUB/athub_1_0_sh_mask.h
>>> create mode 100644
>>> drivers/gpu/drm/amd/include/asic_reg/vega10/DC/dce_12_0_default.h
>>> create mode 100644
>>> drivers/gpu/drm/amd/include/asic_reg/vega10/DC/dce_12_0_offset.h
>>> create mode 100644
>>> drivers/gpu/drm/amd/include/asic_reg/vega10/DC/dce_12_0_sh_mask.h
>>> create mode 100644
>>> drivers/gpu/drm/amd/include/asic_reg/vega10/GC/gc_9_0_default.h
>>> create mode 100644
>>> drivers/gpu/drm/amd/include/asic_reg/vega10/GC/gc_9_0_offset.h
>>> create mode 100644
>>> drivers/gpu/drm/amd/include/asic_reg/vega10/GC/gc_9_0_sh_mask.h
>>> create mode 100644
>>> drivers/gpu/drm/amd/include/asic_reg/vega10/HDP/hdp_4_0_default.h
>>> create mode 100644
>>> drivers/gpu/drm/amd/include/asic_reg/vega10/HDP/hdp_4_0_offset.h
>>> create mode 100644
>>> drivers/gpu/drm/amd/include/asic_reg/vega10/HDP/hdp_4_0_sh_mask.h
>>> create mode 100644
>>> drivers/gpu/drm/amd/include/asic_reg/vega10/MMHUB/mmhub_1_0_default.h
>>> create mode 100644
>>> drivers/gpu/drm/amd/include/asic_reg/vega10/MMHUB/mmhub_1_0_offset.h
>>> create mode 100644
>>> drivers/gpu/drm/amd/include/asic_reg/vega10/MMHUB/mmhub_1_0_sh_mask.h
>>> create mode 100644
>>> drivers/gpu/drm/amd/include/asic_reg/vega10/MP/mp_9_0_default.h
>>> create mode 100644
>>> drivers/gpu/drm/amd/include/asic_reg/vega10/MP/mp_9_0_offset.h
>>> create mode 100644
>>> drivers/gpu/drm/amd/include/asic_reg/vega10/MP/mp_9_0_sh_mask.h
>>> create mode 100644
>>> drivers/gpu/drm/amd/include/asic_reg/vega10/NBIF/nbif_6_1_default.h
>>> create mode 100644
>>> drivers/gpu/drm/amd/include/asic_reg/vega10/NBIF/nbif_6_1_offset.h
>>> create mode 100644
>>> drivers/gpu/drm/amd/include/asic_reg/vega10/NBIF/nbif_6_1_sh_mask.h
>>> create mode 100644
>>> drivers/gpu/drm/amd/include/asic_reg/vega10/NBIO/nbio_6_1_default.h
>>> create mode 100644
>>> drivers/gpu/drm/amd/include/asic_reg/vega10/NBIO/nbio_6_1_offset.h
>>> create mode 100644
>>> drivers/gpu/drm/amd/include/asic_reg/vega10/NBIO/nbio_6_1_sh_mask.h
>>> create mode 100644
>>> drivers/gpu/drm/amd/include/asic_reg/vega10/OSSSYS/osssys_4_0_default.h
>>> create mode 100644
>>> drivers/gpu/drm/amd/include/asic_reg/vega10/OSSSYS/osssys_4_0_offset.h
>>> create mode 100644
>>> drivers/gpu/drm/amd/include/asic_reg/vega10/OSSSYS/osssys_4_0_sh_mask.h
>>> create mode 100644
>>> drivers/gpu/drm/amd/include/asic_reg/vega10/SDMA0/sdma0_4_0_default.h
>>> create mode 100644
>>> drivers/gpu/drm/amd/include/asic_reg/vega10/SDMA0/sdma0_4_0_offset.h
>>> create mode 100644
>>> drivers/gpu/drm/amd/include/asic_reg/vega10/SDMA0/sdma0_4_0_sh_mask.h
>>> create mode 100644
>>> drivers/gpu/drm/amd/include/asic_reg/vega10/SDMA1/sdma1_4_0_default.h
>>> create mode 100644
>>> drivers/gpu/drm/amd/include/asic_reg/vega10/SDMA1/sdma1_4_0_offset.h
>>> create mode 100644
>>> drivers/gpu/drm/amd/include/asic_reg/vega10/SDMA1/sdma1_4_0_sh_mask.h
>>> create mode 100644
>>> drivers/gpu/drm/amd/include/asic_reg/vega10/SMUIO/smuio_9_0_default.h
>>> create mode 100644
>>> drivers/gpu/drm/amd/include/asic_reg/vega10/SMUIO/smuio_9_0_offset.h
>>> create mode 100644
>>> drivers/gpu/drm/amd/include/asic_reg/vega10/SMUIO/smuio_9_0_sh_mask.h
>>> create mode 100644
>>> drivers/gpu/drm/amd/include/asic_reg/vega10/THM/thm_9_0_default.h
>>> create mode 100644
>>> drivers/gpu/drm/amd/include/asic_reg/vega10/THM/thm_9_0_offset.h
>>> create mode 100644
>>> drivers/gpu/drm/amd/include/asic_reg/vega10/THM/thm_9_0_sh_mask.h
>>> create mode 100644
>>> drivers/gpu/drm/amd/include/asic_reg/vega10/UVD/uvd_7_0_default.h
>>> create mode 100644
>>> drivers/gpu/drm/amd/include/asic_reg/vega10/UVD/uvd_7_0_offset.h
>>> create mode 100644
>>> drivers/gpu/drm/amd/include/asic_reg/vega10/UVD/uvd_7_0_sh_mask.h
>>> create mode 100644
>>> drivers/gpu/drm/amd/include/asic_reg/vega10/VCE/vce_4_0_default.h
>>> create mode 100644
>>> drivers/gpu/drm/amd/include/asic_reg/vega10/VCE/vce_4_0_offset.h
>>> create mode 100644
>>> drivers/gpu/drm/amd/include/asic_reg/vega10/VCE/vce_4_0_sh_mask.h
>>> create mode 100644
>>> drivers/gpu/drm/amd/include/asic_reg/vega10/soc15ip.h
>>> create mode 100644
>>> drivers/gpu/drm/amd/include/asic_reg/vega10/vega10_enum.h
>>> create mode 100644 drivers/gpu/drm/amd/include/atomfirmware.h
>>> create mode 100644 drivers/gpu/drm/amd/include/atomfirmwareid.h
>>> create mode 100644 drivers/gpu/drm/amd/include/displayobject.h
>>> create mode 100644 drivers/gpu/drm/amd/include/dm_pp_interface.h
>>> create mode 100644 drivers/gpu/drm/amd/include/v9_structs.h
>>> create mode 100644 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.c
>>> create mode 100644 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.h
>>> create mode 100644 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
>>> create mode 100644 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h
>>> create mode 100644 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_inc.h
>>> create mode 100644
>>> drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c
>>> create mode 100644
>>> drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.h
>>> create mode 100644
>>> drivers/gpu/drm/amd/powerplay/hwmgr/vega10_pptable.h
>>> create mode 100644
>>> drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c
>>> create mode 100644
>>> drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.h
>>> create mode 100644
>>> drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c
>>> create mode 100644
>>> drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.h
>>> create mode 100644 drivers/gpu/drm/amd/powerplay/inc/pp_soc15.h
>>> create mode 100644 drivers/gpu/drm/amd/powerplay/inc/smu9.h
>>> create mode 100644 drivers/gpu/drm/amd/powerplay/inc/smu9_driver_if.h
>>> create mode 100644 drivers/gpu/drm/amd/powerplay/inc/vega10_ppsmc.h
>>> create mode 100644
>>> drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c
>>> create mode 100644
>>> drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.h
>>>
>>
>> _______________________________________________
>> amd-gfx mailing list
>> amd-gfx@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
>
>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH 000/100] Add Vega10 Support
[not found] ` <50d03274-5a6e-fb77-9741-b6700a9949bd-ANTagKRnAhcb1SvskN2V4Q@public.gmane.org>
@ 2017-03-21 11:51 ` Christian König
[not found] ` <b717602f-7573-6c20-ca68-491e3fe847c0-ANTagKRnAhcb1SvskN2V4Q@public.gmane.org>
2017-03-21 22:00 ` Alex Deucher
1 sibling, 1 reply; 16+ messages in thread
From: Christian König @ 2017-03-21 11:51 UTC (permalink / raw)
To: Alex Deucher, amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Alex Deucher
Patches #48, #49, #52-#63, #65-#68, #70-#72, #74, #76, #77, #79, #81-#84
are Acked-by: Christian König <christian.koenig@amd.com>.
Patches #50, #64, #69, #75, #78, #80, #85, #89-#91, #100 didn't made it
to the list.
Patch #73 probably needs to be moved to the end of the set or at least
after the wptr_poll fix.
Apart from those everything should already have my reviewed-by or acked-by.
What worries me a bit are the ones who didn't made it to the list. Going
to check my spam folder, but that is a bit disturbing.
Regards,
Christian.
Am 21.03.2017 um 08:42 schrieb Christian König:
> Patches #1 - #5, #21, #23, #25, #27, #28, #31, #35-#38, #40, #41, #45
> are Acked-by: Christian König.
>
> Patches #6-#20, #22, #24, #32, #39, #42 didn't made it to the list
> (probably to large).
>
> Patches #43, #44 are Reviewed-by: Christian König
> <christian.koenig@amd.com>.
>
> Patch #26: That stuff actually belongs into vega10 specifc code,
> doesn't it?
>
> Patch #29: We shouldn't use typedefs for enums.
>
> Going to take a look at the rest later today,
> Christian.
>
> Am 20.03.2017 um 21:29 schrieb Alex Deucher:
>> This patch set adds support for vega10. Major changes and supported
>> features:
>> - new vbios interface
>> - Lots of new hw IPs
>> - Support for video decode using UVD
>> - Support for video encode using VCE
>> - Support for 3D via radeonsi
>> - Power management
>> - Full display support via DC
>> - Support for SR-IOV
>>
>> I did not send out the register headers since they are huge. You can
>> find them
>> along with all the other patches in this series here:
>> https://cgit.freedesktop.org/~agd5f/linux/log/?h=amd-staging-4.9
>>
>> Please review.
>>
>> Thanks,
>>
>> Alex
>>
>> Alex Deucher (29):
>> drm/amdgpu: add the new atomfirmware interface header
>> amdgpu: detect if we are using atomfirm or atombios for vbios (v2)
>> drm/amdgpu: move atom scratch setup into amdgpu_atombios.c
>> drm/amdgpu: add basic support for atomfirmware.h (v3)
>> drm/amdgpu: add soc15ip.h
>> drm/amdgpu: add vega10_enum.h
>> drm/amdgpu: Add ATHUB 1.0 register headers
>> drm/amdgpu: Add the DCE 12.0 register headers
>> drm/amdgpu: add the GC 9.0 register headers
>> drm/amdgpu: add the HDP 4.0 register headers
>> drm/amdgpu: add the MMHUB 1.0 register headers
>> drm/amdgpu: add MP 9.0 register headers
>> drm/amdgpu: add NBIF 6.1 register headers
>> drm/amdgpu: add NBIO 6.1 register headers
>> drm/amdgpu: add OSSSYS 4.0 register headers
>> drm/amdgpu: add SDMA 4.0 register headers
>> drm/amdgpu: add SMUIO 9.0 register headers
>> drm/amdgpu: add THM 9.0 register headers
>> drm/amdgpu: add the UVD 7.0 register headers
>> drm/amdgpu: add the VCE 4.0 register headers
>> drm/amdgpu: add gfx9 clearstate header
>> drm/amdgpu: add SDMA 4.0 packet header
>> drm/amdgpu: use atomfirmware interfaces for scratch reg save/restore
>> drm/amdgpu: update IH IV ring entry for soc-15
>> drm/amdgpu: add PTE defines for MTYPE
>> drm/amdgpu: add NGG parameters
>> drm/amdgpu: Add asic family for vega10
>> drm/amdgpu: add tiling flags for GFX9
>> drm/amdgpu: gart fixes for vega10
>>
>> Alex Xie (4):
>> drm/amdgpu: Add MTYPE flags to GPU VM IOCTL interface
>> drm/amdgpu: handle PTE EXEC in amdgpu_vm_bo_split_mapping
>> drm/amdgpu: handle PTE MTYPE in amdgpu_vm_bo_split_mapping
>> drm/amdgpu: Add GMC 9.0 support
>>
>> Andrey Grodzovsky (1):
>> drm/amdgpu: gb_addr_config struct
>>
>> Charlene Liu (1):
>> drm/amd/display: need to handle DCE_Info table ver4.2
>>
>> Christian König (1):
>> drm/amdgpu: add IV trace point
>>
>> Eric Huang (7):
>> drm/amd/powerplay: add smu9 header files for Vega10
>> drm/amd/powerplay: add new Vega10's ppsmc header file
>> drm/amdgpu: add new atomfirmware based helpers for powerplay
>> drm/amd/powerplay: add some new structures for Vega10
>> drm/amd: add structures for display/powerplay interface
>> drm/amd/powerplay: add some display/powerplay interfaces
>> drm/amd/powerplay: add Vega10 powerplay support
>>
>> Felix Kuehling (1):
>> drm/amd: Add MQD structs for GFX V9
>>
>> Harry Wentland (6):
>> drm/amd/display: Add DCE12 bios parser support
>> drm/amd/display: Add DCE12 gpio support
>> drm/amd/display: Add DCE12 i2c/aux support
>> drm/amd/display: Add DCE12 irq support
>> drm/amd/display: Add DCE12 core support
>> drm/amd/display: Enable DCE12 support
>>
>> Huang Rui (6):
>> drm/amdgpu: use new flag to handle different firmware loading method
>> drm/amdgpu: rework common ucode handling for vega10
>> drm/amdgpu: add psp firmware header info
>> drm/amdgpu: add PSP driver for vega10
>> drm/amdgpu: add psp firmware info into info query and debugfs
>> drm/amdgpu: add SMC firmware into global ucode list for psp loading
>>
>> Jordan Lazare (1):
>> drm/amd/display: Less log spam
>>
>> Junwei Zhang (2):
>> drm/amdgpu: add NBIO 6.1 driver
>> drm/amdgpu: add Vega10 Device IDs
>>
>> Ken Wang (8):
>> drm/amdgpu: add common soc15 headers
>> drm/amdgpu: add vega10 chip name
>> drm/amdgpu: add 64bit doorbell assignments
>> drm/amdgpu: add SDMA v4.0 implementation
>> drm/amdgpu: implement GFX 9.0 support
>> drm/amdgpu: add vega10 interrupt handler
>> drm/amdgpu: soc15 enable (v2)
>> drm/amdgpu: Set the IP blocks for vega10
>>
>> Leo Liu (2):
>> drm/amdgpu: add initial uvd 7.0 support for vega10
>> drm/amdgpu: add initial vce 4.0 support for vega10
>>
>> Marek Olšák (1):
>> drm/amdgpu: don't validate TILE_SPLIT on GFX9
>>
>> Monk Liu (5):
>> drm/amdgpu/gfx9: programing wptr_poll_addr register
>> drm/amdgpu:impl gfx9 cond_exec
>> drm/amdgpu:bypass RLC init for SRIOV
>> drm/amdgpu/sdma4:re-org SDMA initial steps for sriov
>> drm/amdgpu/vega10:fix DOORBELL64 scheme
>>
>> Rex Zhu (2):
>> drm/amdgpu: get display info from DC when DC enabled.
>> drm/amd/powerplay: add global PowerPlay mutex.
>>
>> Xiangliang Yu (22):
>> drm/amdgpu: impl sriov detection for vega10
>> drm/amdgpu: add kiq ring for gfx9
>> drm/amdgpu/gfx9: fullfill kiq funcs
>> drm/amdgpu/gfx9: fullfill kiq irq funcs
>> drm/amdgpu: init kiq and kcq for vega10
>> drm/amdgpu/gfx9: impl gfx9 meta data emit
>> drm/amdgpu/soc15: bypass PSP for VF
>> drm/amdgpu/gmc9: no need use kiq in vega10 tlb flush
>> drm/amdgpu/dce_virtual: bypass DPM for vf
>> drm/amdgpu/virt: impl mailbox for ai
>> drm/amdgpu/soc15: init virt ops for vf
>> drm/amdgpu/soc15: enable virtual dce for vf
>> drm/amdgpu: Don't touch PG&CG for SRIOV MM
>> drm/amdgpu/vce4: enable doorbell for SRIOV
>> drm/amdgpu: disable uvd for sriov
>> drm/amdgpu/soc15: bypass pp block for vf
>> drm/amdgpu/virt: add structure for MM table
>> drm/amdgpu/vce4: alloc mm table for MM sriov
>> drm/amdgpu/vce4: Ignore vce ring/ib test temporarily
>> drm/amdgpu: add mmsch structures
>> drm/amdgpu/vce4: impl vce & mmsch sriov start
>> drm/amdgpu/gfx9: correct wptr pointer value
>>
>> ken (1):
>> drm/amdgpu: add clinetid definition for vega10
>>
>> drivers/gpu/drm/amd/amdgpu/Makefile | 27 +-
>> drivers/gpu/drm/amd/amdgpu/amdgpu.h | 172 +-
>> drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c | 28 +
>> drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.h | 3 +
>> drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c | 112 +
>> drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.h | 33 +
>> drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c | 30 +-
>> drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c | 73 +-
>> drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 73 +-
>> drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 36 +-
>> drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c | 3 +-
>> drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 2 +-
>> drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h | 47 +-
>> drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c | 3 +
>> drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 32 +
>> drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 5 +-
>> drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c | 5 +-
>> drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 473 +
>> drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h | 127 +
>> drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h | 37 +
>> drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c | 113 +-
>> drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h | 17 +
>> drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c | 58 +-
>> drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c | 21 +
>> drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h | 7 +
>> drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 34 +-
>> drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h | 4 +
>> drivers/gpu/drm/amd/amdgpu/atom.c | 26 -
>> drivers/gpu/drm/amd/amdgpu/atom.h | 1 -
>> drivers/gpu/drm/amd/amdgpu/cik.c | 2 +
>> drivers/gpu/drm/amd/amdgpu/clearstate_gfx9.h | 941 +
>> drivers/gpu/drm/amd/amdgpu/dce_virtual.c | 3 +
>> drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 6 +-
>> drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 4075 +
>> drivers/gpu/drm/amd/amdgpu/gfx_v9_0.h | 35 +
>> drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c | 447 +
>> drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.h | 35 +
>> drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 826 +
>> drivers/gpu/drm/amd/amdgpu/gmc_v9_0.h | 30 +
>> drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c | 585 +
>> drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.h | 35 +
>> drivers/gpu/drm/amd/amdgpu/mmsch_v1_0.h | 87 +
>> drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c | 207 +
>> drivers/gpu/drm/amd/amdgpu/mxgpu_ai.h | 47 +
>> drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c | 251 +
>> drivers/gpu/drm/amd/amdgpu/nbio_v6_1.h | 53 +
>> drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h | 269 +
>> drivers/gpu/drm/amd/amdgpu/psp_v3_1.c | 507 +
>> drivers/gpu/drm/amd/amdgpu/psp_v3_1.h | 50 +
>> drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c | 4 +-
>> drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 4 +-
>> drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 1573 +
>> drivers/gpu/drm/amd/amdgpu/sdma_v4_0.h | 30 +
>> drivers/gpu/drm/amd/amdgpu/soc15.c | 825 +
>> drivers/gpu/drm/amd/amdgpu/soc15.h | 35 +
>> drivers/gpu/drm/amd/amdgpu/soc15_common.h | 57 +
>> drivers/gpu/drm/amd/amdgpu/soc15d.h | 287 +
>> drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c | 1543 +
>> drivers/gpu/drm/amd/amdgpu/uvd_v7_0.h | 29 +
>> drivers/gpu/drm/amd/amdgpu/vce_v4_0.c | 1141 +
>> drivers/gpu/drm/amd/amdgpu/vce_v4_0.h | 29 +
>> drivers/gpu/drm/amd/amdgpu/vega10_ih.c | 424 +
>> drivers/gpu/drm/amd/amdgpu/vega10_ih.h | 30 +
>> drivers/gpu/drm/amd/amdgpu/vega10_sdma_pkt_open.h | 3335 +
>> drivers/gpu/drm/amd/amdgpu/vi.c | 4 +-
>> drivers/gpu/drm/amd/display/Kconfig | 7 +
>> drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 145 +-
>> .../drm/amd/display/amdgpu_dm/amdgpu_dm_services.c | 10 +
>> .../drm/amd/display/amdgpu_dm/amdgpu_dm_types.c | 20 +-
>> drivers/gpu/drm/amd/display/dc/Makefile | 4 +
>> drivers/gpu/drm/amd/display/dc/bios/Makefile | 8 +
>> drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c | 2162 +
>> drivers/gpu/drm/amd/display/dc/bios/bios_parser2.h | 33 +
>> .../amd/display/dc/bios/bios_parser_interface.c | 14 +
>> .../display/dc/bios/bios_parser_types_internal2.h | 74 +
>> .../gpu/drm/amd/display/dc/bios/command_table2.c | 813 +
>> .../gpu/drm/amd/display/dc/bios/command_table2.h | 105 +
>> .../amd/display/dc/bios/command_table_helper2.c | 260 +
>> .../amd/display/dc/bios/command_table_helper2.h | 82 +
>> .../dc/bios/dce112/command_table_helper2_dce112.c | 418 +
>> .../dc/bios/dce112/command_table_helper2_dce112.h | 34 +
>> drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c | 117 +
>> drivers/gpu/drm/amd/display/dc/core/dc.c | 29 +
>> drivers/gpu/drm/amd/display/dc/core/dc_debug.c | 11 +
>> drivers/gpu/drm/amd/display/dc/core/dc_link.c | 19 +
>> drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 14 +
>> drivers/gpu/drm/amd/display/dc/dc.h | 27 +
>> drivers/gpu/drm/amd/display/dc/dc_hw_types.h | 46 +
>> .../gpu/drm/amd/display/dc/dce/dce_clock_source.c | 6 +
>> drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c | 149 +
>> drivers/gpu/drm/amd/display/dc/dce/dce_clocks.h | 20 +
>> drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h | 8 +
>> .../gpu/drm/amd/display/dc/dce/dce_link_encoder.h | 14 +
>> drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c | 35 +
>> drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h | 34 +
>> drivers/gpu/drm/amd/display/dc/dce/dce_opp.h | 72 +
>> .../drm/amd/display/dc/dce/dce_stream_encoder.h | 100 +
>> drivers/gpu/drm/amd/display/dc/dce/dce_transform.h | 68 +
>> .../amd/display/dc/dce110/dce110_hw_sequencer.c | 53 +-
>> .../drm/amd/display/dc/dce110/dce110_mem_input.c | 3 +
>> .../display/dc/dce110/dce110_timing_generator.h | 3 +
>> drivers/gpu/drm/amd/display/dc/dce120/Makefile | 12 +
>> .../amd/display/dc/dce120/dce120_hw_sequencer.c | 197 +
>> .../amd/display/dc/dce120/dce120_hw_sequencer.h | 36 +
>> drivers/gpu/drm/amd/display/dc/dce120/dce120_ipp.c | 58 +
>> drivers/gpu/drm/amd/display/dc/dce120/dce120_ipp.h | 62 +
>> .../drm/amd/display/dc/dce120/dce120_ipp_cursor.c | 202 +
>> .../drm/amd/display/dc/dce120/dce120_ipp_gamma.c | 167 +
>> .../drm/amd/display/dc/dce120/dce120_mem_input.c | 340 +
>> .../drm/amd/display/dc/dce120/dce120_mem_input.h | 37 +
>> .../drm/amd/display/dc/dce120/dce120_resource.c | 1099 +
>> .../drm/amd/display/dc/dce120/dce120_resource.h | 39 +
>> .../display/dc/dce120/dce120_timing_generator.c | 1109 +
>> .../display/dc/dce120/dce120_timing_generator.h | 41 +
>> .../gpu/drm/amd/display/dc/dce80/dce80_mem_input.c | 3 +
>> drivers/gpu/drm/amd/display/dc/dm_services.h | 89 +
>> drivers/gpu/drm/amd/display/dc/dm_services_types.h | 27 +
>> drivers/gpu/drm/amd/display/dc/gpio/Makefile | 11 +
>> .../amd/display/dc/gpio/dce120/hw_factory_dce120.c | 197 +
>> .../amd/display/dc/gpio/dce120/hw_factory_dce120.h | 32 +
>> .../display/dc/gpio/dce120/hw_translate_dce120.c | 408 +
>> .../display/dc/gpio/dce120/hw_translate_dce120.h | 34 +
>> drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c | 9 +
>> drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c | 9 +-
>> drivers/gpu/drm/amd/display/dc/i2caux/Makefile | 11 +
>> .../amd/display/dc/i2caux/dce120/i2caux_dce120.c | 125 +
>> .../amd/display/dc/i2caux/dce120/i2caux_dce120.h | 32 +
>> drivers/gpu/drm/amd/display/dc/i2caux/i2caux.c | 8 +
>> .../gpu/drm/amd/display/dc/inc/bandwidth_calcs.h | 3 +
>> .../gpu/drm/amd/display/dc/inc/hw/display_clock.h | 23 +
>> drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h | 4 +
>> drivers/gpu/drm/amd/display/dc/irq/Makefile | 12 +
>> .../amd/display/dc/irq/dce120/irq_service_dce120.c | 293 +
>> .../amd/display/dc/irq/dce120/irq_service_dce120.h | 34 +
>> drivers/gpu/drm/amd/display/dc/irq/irq_service.c | 3 +
>> drivers/gpu/drm/amd/display/include/dal_asic_id.h | 4 +
>> drivers/gpu/drm/amd/display/include/dal_types.h | 3 +
>> drivers/gpu/drm/amd/include/amd_shared.h | 4 +
>> .../asic_reg/vega10/ATHUB/athub_1_0_default.h | 241 +
>> .../asic_reg/vega10/ATHUB/athub_1_0_offset.h | 453 +
>> .../asic_reg/vega10/ATHUB/athub_1_0_sh_mask.h | 2045 +
>> .../include/asic_reg/vega10/DC/dce_12_0_default.h | 9868 ++
>> .../include/asic_reg/vega10/DC/dce_12_0_offset.h | 18193 +++
>> .../include/asic_reg/vega10/DC/dce_12_0_sh_mask.h | 64636 +++++++++
>> .../include/asic_reg/vega10/GC/gc_9_0_default.h | 3873 +
>> .../amd/include/asic_reg/vega10/GC/gc_9_0_offset.h | 7230 +
>> .../include/asic_reg/vega10/GC/gc_9_0_sh_mask.h | 29868 ++++
>> .../include/asic_reg/vega10/HDP/hdp_4_0_default.h | 117 +
>> .../include/asic_reg/vega10/HDP/hdp_4_0_offset.h | 209 +
>> .../include/asic_reg/vega10/HDP/hdp_4_0_sh_mask.h | 601 +
>> .../asic_reg/vega10/MMHUB/mmhub_1_0_default.h | 1011 +
>> .../asic_reg/vega10/MMHUB/mmhub_1_0_offset.h | 1967 +
>> .../asic_reg/vega10/MMHUB/mmhub_1_0_sh_mask.h | 10127 ++
>> .../include/asic_reg/vega10/MP/mp_9_0_default.h | 342 +
>> .../amd/include/asic_reg/vega10/MP/mp_9_0_offset.h | 375 +
>> .../include/asic_reg/vega10/MP/mp_9_0_sh_mask.h | 1463 +
>> .../asic_reg/vega10/NBIF/nbif_6_1_default.h | 1271 +
>> .../include/asic_reg/vega10/NBIF/nbif_6_1_offset.h | 1688 +
>> .../asic_reg/vega10/NBIF/nbif_6_1_sh_mask.h | 10281 ++
>> .../asic_reg/vega10/NBIO/nbio_6_1_default.h | 22340 +++
>> .../include/asic_reg/vega10/NBIO/nbio_6_1_offset.h | 3649 +
>> .../asic_reg/vega10/NBIO/nbio_6_1_sh_mask.h | 133884
>> ++++++++++++++++++
>> .../asic_reg/vega10/OSSSYS/osssys_4_0_default.h | 176 +
>> .../asic_reg/vega10/OSSSYS/osssys_4_0_offset.h | 327 +
>> .../asic_reg/vega10/OSSSYS/osssys_4_0_sh_mask.h | 1196 +
>> .../asic_reg/vega10/SDMA0/sdma0_4_0_default.h | 286 +
>> .../asic_reg/vega10/SDMA0/sdma0_4_0_offset.h | 547 +
>> .../asic_reg/vega10/SDMA0/sdma0_4_0_sh_mask.h | 1852 +
>> .../asic_reg/vega10/SDMA1/sdma1_4_0_default.h | 282 +
>> .../asic_reg/vega10/SDMA1/sdma1_4_0_offset.h | 539 +
>> .../asic_reg/vega10/SDMA1/sdma1_4_0_sh_mask.h | 1810 +
>> .../asic_reg/vega10/SMUIO/smuio_9_0_default.h | 100 +
>> .../asic_reg/vega10/SMUIO/smuio_9_0_offset.h | 175 +
>> .../asic_reg/vega10/SMUIO/smuio_9_0_sh_mask.h | 258 +
>> .../include/asic_reg/vega10/THM/thm_9_0_default.h | 194 +
>> .../include/asic_reg/vega10/THM/thm_9_0_offset.h | 363 +
>> .../include/asic_reg/vega10/THM/thm_9_0_sh_mask.h | 1314 +
>> .../include/asic_reg/vega10/UVD/uvd_7_0_default.h | 127 +
>> .../include/asic_reg/vega10/UVD/uvd_7_0_offset.h | 222 +
>> .../include/asic_reg/vega10/UVD/uvd_7_0_sh_mask.h | 811 +
>> .../include/asic_reg/vega10/VCE/vce_4_0_default.h | 122 +
>> .../include/asic_reg/vega10/VCE/vce_4_0_offset.h | 208 +
>> .../include/asic_reg/vega10/VCE/vce_4_0_sh_mask.h | 488 +
>> .../gpu/drm/amd/include/asic_reg/vega10/soc15ip.h | 1343 +
>> .../drm/amd/include/asic_reg/vega10/vega10_enum.h | 22531 +++
>> drivers/gpu/drm/amd/include/atomfirmware.h | 2385 +
>> drivers/gpu/drm/amd/include/atomfirmwareid.h | 86 +
>> drivers/gpu/drm/amd/include/displayobject.h | 249 +
>> drivers/gpu/drm/amd/include/dm_pp_interface.h | 83 +
>> drivers/gpu/drm/amd/include/v9_structs.h | 743 +
>> drivers/gpu/drm/amd/powerplay/amd_powerplay.c | 284 +-
>> drivers/gpu/drm/amd/powerplay/hwmgr/Makefile | 6 +-
>> .../gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c | 49 +
>> drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c | 9 +
>> drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr_ppt.h | 16 +-
>> drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.c | 396 +
>> drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.h | 140 +
>> drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c | 4378 +
>> drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h | 434 +
>> drivers/gpu/drm/amd/powerplay/hwmgr/vega10_inc.h | 44 +
>> .../gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c | 137 +
>> .../gpu/drm/amd/powerplay/hwmgr/vega10_powertune.h | 65 +
>> .../gpu/drm/amd/powerplay/hwmgr/vega10_pptable.h | 331 +
>> .../amd/powerplay/hwmgr/vega10_processpptables.c | 1056 +
>> .../amd/powerplay/hwmgr/vega10_processpptables.h | 34 +
>> .../gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c | 761 +
>> .../gpu/drm/amd/powerplay/hwmgr/vega10_thermal.h | 83 +
>> drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h | 28 +-
>> .../gpu/drm/amd/powerplay/inc/hardwaremanager.h | 43 +
>> drivers/gpu/drm/amd/powerplay/inc/hwmgr.h | 125 +-
>> drivers/gpu/drm/amd/powerplay/inc/pp_instance.h | 1 +
>> drivers/gpu/drm/amd/powerplay/inc/pp_soc15.h | 48 +
>> drivers/gpu/drm/amd/powerplay/inc/smu9.h | 147 +
>> drivers/gpu/drm/amd/powerplay/inc/smu9_driver_if.h | 418 +
>> drivers/gpu/drm/amd/powerplay/inc/smumgr.h | 3 +
>> drivers/gpu/drm/amd/powerplay/inc/vega10_ppsmc.h | 131 +
>> drivers/gpu/drm/amd/powerplay/smumgr/Makefile | 2 +-
>> drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c | 9 +
>> .../gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c | 564 +
>> .../gpu/drm/amd/powerplay/smumgr/vega10_smumgr.h | 70 +
>> include/uapi/drm/amdgpu_drm.h | 29 +
>> 221 files changed, 403408 insertions(+), 219 deletions(-)
>> create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c
>> create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.h
>> create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
>> create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
>> create mode 100644 drivers/gpu/drm/amd/amdgpu/clearstate_gfx9.h
>> create mode 100644 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
>> create mode 100644 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.h
>> create mode 100644 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
>> create mode 100644 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.h
>> create mode 100644 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
>> create mode 100644 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.h
>> create mode 100644 drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
>> create mode 100644 drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.h
>> create mode 100644 drivers/gpu/drm/amd/amdgpu/mmsch_v1_0.h
>> create mode 100644 drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c
>> create mode 100644 drivers/gpu/drm/amd/amdgpu/mxgpu_ai.h
>> create mode 100644 drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c
>> create mode 100644 drivers/gpu/drm/amd/amdgpu/nbio_v6_1.h
>> create mode 100644 drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h
>> create mode 100644 drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
>> create mode 100644 drivers/gpu/drm/amd/amdgpu/psp_v3_1.h
>> create mode 100644 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
>> create mode 100644 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.h
>> create mode 100644 drivers/gpu/drm/amd/amdgpu/soc15.c
>> create mode 100644 drivers/gpu/drm/amd/amdgpu/soc15.h
>> create mode 100644 drivers/gpu/drm/amd/amdgpu/soc15_common.h
>> create mode 100644 drivers/gpu/drm/amd/amdgpu/soc15d.h
>> create mode 100644 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
>> create mode 100644 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.h
>> create mode 100644 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
>> create mode 100644 drivers/gpu/drm/amd/amdgpu/vce_v4_0.h
>> create mode 100644 drivers/gpu/drm/amd/amdgpu/vega10_ih.c
>> create mode 100644 drivers/gpu/drm/amd/amdgpu/vega10_ih.h
>> create mode 100644 drivers/gpu/drm/amd/amdgpu/vega10_sdma_pkt_open.h
>> create mode 100644 drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
>> create mode 100644 drivers/gpu/drm/amd/display/dc/bios/bios_parser2.h
>> create mode 100644
>> drivers/gpu/drm/amd/display/dc/bios/bios_parser_types_internal2.h
>> create mode 100644
>> drivers/gpu/drm/amd/display/dc/bios/command_table2.c
>> create mode 100644
>> drivers/gpu/drm/amd/display/dc/bios/command_table2.h
>> create mode 100644
>> drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c
>> create mode 100644
>> drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.h
>> create mode 100644
>> drivers/gpu/drm/amd/display/dc/bios/dce112/command_table_helper2_dce112.c
>> create mode 100644
>> drivers/gpu/drm/amd/display/dc/bios/dce112/command_table_helper2_dce112.h
>> create mode 100644 drivers/gpu/drm/amd/display/dc/dce120/Makefile
>> create mode 100644
>> drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.c
>> create mode 100644
>> drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.h
>> create mode 100644 drivers/gpu/drm/amd/display/dc/dce120/dce120_ipp.c
>> create mode 100644 drivers/gpu/drm/amd/display/dc/dce120/dce120_ipp.h
>> create mode 100644
>> drivers/gpu/drm/amd/display/dc/dce120/dce120_ipp_cursor.c
>> create mode 100644
>> drivers/gpu/drm/amd/display/dc/dce120/dce120_ipp_gamma.c
>> create mode 100644
>> drivers/gpu/drm/amd/display/dc/dce120/dce120_mem_input.c
>> create mode 100644
>> drivers/gpu/drm/amd/display/dc/dce120/dce120_mem_input.h
>> create mode 100644
>> drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c
>> create mode 100644
>> drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.h
>> create mode 100644
>> drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c
>> create mode 100644
>> drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.h
>> create mode 100644
>> drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_factory_dce120.c
>> create mode 100644
>> drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_factory_dce120.h
>> create mode 100644
>> drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c
>> create mode 100644
>> drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.h
>> create mode 100644
>> drivers/gpu/drm/amd/display/dc/i2caux/dce120/i2caux_dce120.c
>> create mode 100644
>> drivers/gpu/drm/amd/display/dc/i2caux/dce120/i2caux_dce120.h
>> create mode 100644
>> drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c
>> create mode 100644
>> drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.h
>> create mode 100644
>> drivers/gpu/drm/amd/include/asic_reg/vega10/ATHUB/athub_1_0_default.h
>> create mode 100644
>> drivers/gpu/drm/amd/include/asic_reg/vega10/ATHUB/athub_1_0_offset.h
>> create mode 100644
>> drivers/gpu/drm/amd/include/asic_reg/vega10/ATHUB/athub_1_0_sh_mask.h
>> create mode 100644
>> drivers/gpu/drm/amd/include/asic_reg/vega10/DC/dce_12_0_default.h
>> create mode 100644
>> drivers/gpu/drm/amd/include/asic_reg/vega10/DC/dce_12_0_offset.h
>> create mode 100644
>> drivers/gpu/drm/amd/include/asic_reg/vega10/DC/dce_12_0_sh_mask.h
>> create mode 100644
>> drivers/gpu/drm/amd/include/asic_reg/vega10/GC/gc_9_0_default.h
>> create mode 100644
>> drivers/gpu/drm/amd/include/asic_reg/vega10/GC/gc_9_0_offset.h
>> create mode 100644
>> drivers/gpu/drm/amd/include/asic_reg/vega10/GC/gc_9_0_sh_mask.h
>> create mode 100644
>> drivers/gpu/drm/amd/include/asic_reg/vega10/HDP/hdp_4_0_default.h
>> create mode 100644
>> drivers/gpu/drm/amd/include/asic_reg/vega10/HDP/hdp_4_0_offset.h
>> create mode 100644
>> drivers/gpu/drm/amd/include/asic_reg/vega10/HDP/hdp_4_0_sh_mask.h
>> create mode 100644
>> drivers/gpu/drm/amd/include/asic_reg/vega10/MMHUB/mmhub_1_0_default.h
>> create mode 100644
>> drivers/gpu/drm/amd/include/asic_reg/vega10/MMHUB/mmhub_1_0_offset.h
>> create mode 100644
>> drivers/gpu/drm/amd/include/asic_reg/vega10/MMHUB/mmhub_1_0_sh_mask.h
>> create mode 100644
>> drivers/gpu/drm/amd/include/asic_reg/vega10/MP/mp_9_0_default.h
>> create mode 100644
>> drivers/gpu/drm/amd/include/asic_reg/vega10/MP/mp_9_0_offset.h
>> create mode 100644
>> drivers/gpu/drm/amd/include/asic_reg/vega10/MP/mp_9_0_sh_mask.h
>> create mode 100644
>> drivers/gpu/drm/amd/include/asic_reg/vega10/NBIF/nbif_6_1_default.h
>> create mode 100644
>> drivers/gpu/drm/amd/include/asic_reg/vega10/NBIF/nbif_6_1_offset.h
>> create mode 100644
>> drivers/gpu/drm/amd/include/asic_reg/vega10/NBIF/nbif_6_1_sh_mask.h
>> create mode 100644
>> drivers/gpu/drm/amd/include/asic_reg/vega10/NBIO/nbio_6_1_default.h
>> create mode 100644
>> drivers/gpu/drm/amd/include/asic_reg/vega10/NBIO/nbio_6_1_offset.h
>> create mode 100644
>> drivers/gpu/drm/amd/include/asic_reg/vega10/NBIO/nbio_6_1_sh_mask.h
>> create mode 100644
>> drivers/gpu/drm/amd/include/asic_reg/vega10/OSSSYS/osssys_4_0_default.h
>> create mode 100644
>> drivers/gpu/drm/amd/include/asic_reg/vega10/OSSSYS/osssys_4_0_offset.h
>> create mode 100644
>> drivers/gpu/drm/amd/include/asic_reg/vega10/OSSSYS/osssys_4_0_sh_mask.h
>> create mode 100644
>> drivers/gpu/drm/amd/include/asic_reg/vega10/SDMA0/sdma0_4_0_default.h
>> create mode 100644
>> drivers/gpu/drm/amd/include/asic_reg/vega10/SDMA0/sdma0_4_0_offset.h
>> create mode 100644
>> drivers/gpu/drm/amd/include/asic_reg/vega10/SDMA0/sdma0_4_0_sh_mask.h
>> create mode 100644
>> drivers/gpu/drm/amd/include/asic_reg/vega10/SDMA1/sdma1_4_0_default.h
>> create mode 100644
>> drivers/gpu/drm/amd/include/asic_reg/vega10/SDMA1/sdma1_4_0_offset.h
>> create mode 100644
>> drivers/gpu/drm/amd/include/asic_reg/vega10/SDMA1/sdma1_4_0_sh_mask.h
>> create mode 100644
>> drivers/gpu/drm/amd/include/asic_reg/vega10/SMUIO/smuio_9_0_default.h
>> create mode 100644
>> drivers/gpu/drm/amd/include/asic_reg/vega10/SMUIO/smuio_9_0_offset.h
>> create mode 100644
>> drivers/gpu/drm/amd/include/asic_reg/vega10/SMUIO/smuio_9_0_sh_mask.h
>> create mode 100644
>> drivers/gpu/drm/amd/include/asic_reg/vega10/THM/thm_9_0_default.h
>> create mode 100644
>> drivers/gpu/drm/amd/include/asic_reg/vega10/THM/thm_9_0_offset.h
>> create mode 100644
>> drivers/gpu/drm/amd/include/asic_reg/vega10/THM/thm_9_0_sh_mask.h
>> create mode 100644
>> drivers/gpu/drm/amd/include/asic_reg/vega10/UVD/uvd_7_0_default.h
>> create mode 100644
>> drivers/gpu/drm/amd/include/asic_reg/vega10/UVD/uvd_7_0_offset.h
>> create mode 100644
>> drivers/gpu/drm/amd/include/asic_reg/vega10/UVD/uvd_7_0_sh_mask.h
>> create mode 100644
>> drivers/gpu/drm/amd/include/asic_reg/vega10/VCE/vce_4_0_default.h
>> create mode 100644
>> drivers/gpu/drm/amd/include/asic_reg/vega10/VCE/vce_4_0_offset.h
>> create mode 100644
>> drivers/gpu/drm/amd/include/asic_reg/vega10/VCE/vce_4_0_sh_mask.h
>> create mode 100644
>> drivers/gpu/drm/amd/include/asic_reg/vega10/soc15ip.h
>> create mode 100644
>> drivers/gpu/drm/amd/include/asic_reg/vega10/vega10_enum.h
>> create mode 100644 drivers/gpu/drm/amd/include/atomfirmware.h
>> create mode 100644 drivers/gpu/drm/amd/include/atomfirmwareid.h
>> create mode 100644 drivers/gpu/drm/amd/include/displayobject.h
>> create mode 100644 drivers/gpu/drm/amd/include/dm_pp_interface.h
>> create mode 100644 drivers/gpu/drm/amd/include/v9_structs.h
>> create mode 100644 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.c
>> create mode 100644 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.h
>> create mode 100644 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
>> create mode 100644 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h
>> create mode 100644 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_inc.h
>> create mode 100644
>> drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c
>> create mode 100644
>> drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.h
>> create mode 100644
>> drivers/gpu/drm/amd/powerplay/hwmgr/vega10_pptable.h
>> create mode 100644
>> drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c
>> create mode 100644
>> drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.h
>> create mode 100644
>> drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c
>> create mode 100644
>> drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.h
>> create mode 100644 drivers/gpu/drm/amd/powerplay/inc/pp_soc15.h
>> create mode 100644 drivers/gpu/drm/amd/powerplay/inc/smu9.h
>> create mode 100644 drivers/gpu/drm/amd/powerplay/inc/smu9_driver_if.h
>> create mode 100644 drivers/gpu/drm/amd/powerplay/inc/vega10_ppsmc.h
>> create mode 100644
>> drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c
>> create mode 100644
>> drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.h
>>
>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
_______________________________________________
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^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH 000/100] Add Vega10 Support
[not found] ` <1490041835-11255-1-git-send-email-alexander.deucher-5C7GfCeVMHo@public.gmane.org>
@ 2017-03-21 7:42 ` Christian König
[not found] ` <50d03274-5a6e-fb77-9741-b6700a9949bd-ANTagKRnAhcb1SvskN2V4Q@public.gmane.org>
0 siblings, 1 reply; 16+ messages in thread
From: Christian König @ 2017-03-21 7:42 UTC (permalink / raw)
To: Alex Deucher, amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Alex Deucher
Patches #1 - #5, #21, #23, #25, #27, #28, #31, #35-#38, #40, #41, #45
are Acked-by: Christian König.
Patches #6-#20, #22, #24, #32, #39, #42 didn't made it to the list
(probably to large).
Patches #43, #44 are Reviewed-by: Christian König
<christian.koenig@amd.com>.
Patch #26: That stuff actually belongs into vega10 specifc code, doesn't it?
Patch #29: We shouldn't use typedefs for enums.
Going to take a look at the rest later today,
Christian.
Am 20.03.2017 um 21:29 schrieb Alex Deucher:
> This patch set adds support for vega10. Major changes and supported
> features:
> - new vbios interface
> - Lots of new hw IPs
> - Support for video decode using UVD
> - Support for video encode using VCE
> - Support for 3D via radeonsi
> - Power management
> - Full display support via DC
> - Support for SR-IOV
>
> I did not send out the register headers since they are huge. You can find them
> along with all the other patches in this series here:
> https://cgit.freedesktop.org/~agd5f/linux/log/?h=amd-staging-4.9
>
> Please review.
>
> Thanks,
>
> Alex
>
> Alex Deucher (29):
> drm/amdgpu: add the new atomfirmware interface header
> amdgpu: detect if we are using atomfirm or atombios for vbios (v2)
> drm/amdgpu: move atom scratch setup into amdgpu_atombios.c
> drm/amdgpu: add basic support for atomfirmware.h (v3)
> drm/amdgpu: add soc15ip.h
> drm/amdgpu: add vega10_enum.h
> drm/amdgpu: Add ATHUB 1.0 register headers
> drm/amdgpu: Add the DCE 12.0 register headers
> drm/amdgpu: add the GC 9.0 register headers
> drm/amdgpu: add the HDP 4.0 register headers
> drm/amdgpu: add the MMHUB 1.0 register headers
> drm/amdgpu: add MP 9.0 register headers
> drm/amdgpu: add NBIF 6.1 register headers
> drm/amdgpu: add NBIO 6.1 register headers
> drm/amdgpu: add OSSSYS 4.0 register headers
> drm/amdgpu: add SDMA 4.0 register headers
> drm/amdgpu: add SMUIO 9.0 register headers
> drm/amdgpu: add THM 9.0 register headers
> drm/amdgpu: add the UVD 7.0 register headers
> drm/amdgpu: add the VCE 4.0 register headers
> drm/amdgpu: add gfx9 clearstate header
> drm/amdgpu: add SDMA 4.0 packet header
> drm/amdgpu: use atomfirmware interfaces for scratch reg save/restore
> drm/amdgpu: update IH IV ring entry for soc-15
> drm/amdgpu: add PTE defines for MTYPE
> drm/amdgpu: add NGG parameters
> drm/amdgpu: Add asic family for vega10
> drm/amdgpu: add tiling flags for GFX9
> drm/amdgpu: gart fixes for vega10
>
> Alex Xie (4):
> drm/amdgpu: Add MTYPE flags to GPU VM IOCTL interface
> drm/amdgpu: handle PTE EXEC in amdgpu_vm_bo_split_mapping
> drm/amdgpu: handle PTE MTYPE in amdgpu_vm_bo_split_mapping
> drm/amdgpu: Add GMC 9.0 support
>
> Andrey Grodzovsky (1):
> drm/amdgpu: gb_addr_config struct
>
> Charlene Liu (1):
> drm/amd/display: need to handle DCE_Info table ver4.2
>
> Christian König (1):
> drm/amdgpu: add IV trace point
>
> Eric Huang (7):
> drm/amd/powerplay: add smu9 header files for Vega10
> drm/amd/powerplay: add new Vega10's ppsmc header file
> drm/amdgpu: add new atomfirmware based helpers for powerplay
> drm/amd/powerplay: add some new structures for Vega10
> drm/amd: add structures for display/powerplay interface
> drm/amd/powerplay: add some display/powerplay interfaces
> drm/amd/powerplay: add Vega10 powerplay support
>
> Felix Kuehling (1):
> drm/amd: Add MQD structs for GFX V9
>
> Harry Wentland (6):
> drm/amd/display: Add DCE12 bios parser support
> drm/amd/display: Add DCE12 gpio support
> drm/amd/display: Add DCE12 i2c/aux support
> drm/amd/display: Add DCE12 irq support
> drm/amd/display: Add DCE12 core support
> drm/amd/display: Enable DCE12 support
>
> Huang Rui (6):
> drm/amdgpu: use new flag to handle different firmware loading method
> drm/amdgpu: rework common ucode handling for vega10
> drm/amdgpu: add psp firmware header info
> drm/amdgpu: add PSP driver for vega10
> drm/amdgpu: add psp firmware info into info query and debugfs
> drm/amdgpu: add SMC firmware into global ucode list for psp loading
>
> Jordan Lazare (1):
> drm/amd/display: Less log spam
>
> Junwei Zhang (2):
> drm/amdgpu: add NBIO 6.1 driver
> drm/amdgpu: add Vega10 Device IDs
>
> Ken Wang (8):
> drm/amdgpu: add common soc15 headers
> drm/amdgpu: add vega10 chip name
> drm/amdgpu: add 64bit doorbell assignments
> drm/amdgpu: add SDMA v4.0 implementation
> drm/amdgpu: implement GFX 9.0 support
> drm/amdgpu: add vega10 interrupt handler
> drm/amdgpu: soc15 enable (v2)
> drm/amdgpu: Set the IP blocks for vega10
>
> Leo Liu (2):
> drm/amdgpu: add initial uvd 7.0 support for vega10
> drm/amdgpu: add initial vce 4.0 support for vega10
>
> Marek Olšák (1):
> drm/amdgpu: don't validate TILE_SPLIT on GFX9
>
> Monk Liu (5):
> drm/amdgpu/gfx9: programing wptr_poll_addr register
> drm/amdgpu:impl gfx9 cond_exec
> drm/amdgpu:bypass RLC init for SRIOV
> drm/amdgpu/sdma4:re-org SDMA initial steps for sriov
> drm/amdgpu/vega10:fix DOORBELL64 scheme
>
> Rex Zhu (2):
> drm/amdgpu: get display info from DC when DC enabled.
> drm/amd/powerplay: add global PowerPlay mutex.
>
> Xiangliang Yu (22):
> drm/amdgpu: impl sriov detection for vega10
> drm/amdgpu: add kiq ring for gfx9
> drm/amdgpu/gfx9: fullfill kiq funcs
> drm/amdgpu/gfx9: fullfill kiq irq funcs
> drm/amdgpu: init kiq and kcq for vega10
> drm/amdgpu/gfx9: impl gfx9 meta data emit
> drm/amdgpu/soc15: bypass PSP for VF
> drm/amdgpu/gmc9: no need use kiq in vega10 tlb flush
> drm/amdgpu/dce_virtual: bypass DPM for vf
> drm/amdgpu/virt: impl mailbox for ai
> drm/amdgpu/soc15: init virt ops for vf
> drm/amdgpu/soc15: enable virtual dce for vf
> drm/amdgpu: Don't touch PG&CG for SRIOV MM
> drm/amdgpu/vce4: enable doorbell for SRIOV
> drm/amdgpu: disable uvd for sriov
> drm/amdgpu/soc15: bypass pp block for vf
> drm/amdgpu/virt: add structure for MM table
> drm/amdgpu/vce4: alloc mm table for MM sriov
> drm/amdgpu/vce4: Ignore vce ring/ib test temporarily
> drm/amdgpu: add mmsch structures
> drm/amdgpu/vce4: impl vce & mmsch sriov start
> drm/amdgpu/gfx9: correct wptr pointer value
>
> ken (1):
> drm/amdgpu: add clinetid definition for vega10
>
> drivers/gpu/drm/amd/amdgpu/Makefile | 27 +-
> drivers/gpu/drm/amd/amdgpu/amdgpu.h | 172 +-
> drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c | 28 +
> drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.h | 3 +
> drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c | 112 +
> drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.h | 33 +
> drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c | 30 +-
> drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c | 73 +-
> drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 73 +-
> drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 36 +-
> drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c | 3 +-
> drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 2 +-
> drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h | 47 +-
> drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c | 3 +
> drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 32 +
> drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 5 +-
> drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c | 5 +-
> drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 473 +
> drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h | 127 +
> drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h | 37 +
> drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c | 113 +-
> drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h | 17 +
> drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c | 58 +-
> drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c | 21 +
> drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h | 7 +
> drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 34 +-
> drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h | 4 +
> drivers/gpu/drm/amd/amdgpu/atom.c | 26 -
> drivers/gpu/drm/amd/amdgpu/atom.h | 1 -
> drivers/gpu/drm/amd/amdgpu/cik.c | 2 +
> drivers/gpu/drm/amd/amdgpu/clearstate_gfx9.h | 941 +
> drivers/gpu/drm/amd/amdgpu/dce_virtual.c | 3 +
> drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 6 +-
> drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 4075 +
> drivers/gpu/drm/amd/amdgpu/gfx_v9_0.h | 35 +
> drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c | 447 +
> drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.h | 35 +
> drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 826 +
> drivers/gpu/drm/amd/amdgpu/gmc_v9_0.h | 30 +
> drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c | 585 +
> drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.h | 35 +
> drivers/gpu/drm/amd/amdgpu/mmsch_v1_0.h | 87 +
> drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c | 207 +
> drivers/gpu/drm/amd/amdgpu/mxgpu_ai.h | 47 +
> drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c | 251 +
> drivers/gpu/drm/amd/amdgpu/nbio_v6_1.h | 53 +
> drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h | 269 +
> drivers/gpu/drm/amd/amdgpu/psp_v3_1.c | 507 +
> drivers/gpu/drm/amd/amdgpu/psp_v3_1.h | 50 +
> drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c | 4 +-
> drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 4 +-
> drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 1573 +
> drivers/gpu/drm/amd/amdgpu/sdma_v4_0.h | 30 +
> drivers/gpu/drm/amd/amdgpu/soc15.c | 825 +
> drivers/gpu/drm/amd/amdgpu/soc15.h | 35 +
> drivers/gpu/drm/amd/amdgpu/soc15_common.h | 57 +
> drivers/gpu/drm/amd/amdgpu/soc15d.h | 287 +
> drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c | 1543 +
> drivers/gpu/drm/amd/amdgpu/uvd_v7_0.h | 29 +
> drivers/gpu/drm/amd/amdgpu/vce_v4_0.c | 1141 +
> drivers/gpu/drm/amd/amdgpu/vce_v4_0.h | 29 +
> drivers/gpu/drm/amd/amdgpu/vega10_ih.c | 424 +
> drivers/gpu/drm/amd/amdgpu/vega10_ih.h | 30 +
> drivers/gpu/drm/amd/amdgpu/vega10_sdma_pkt_open.h | 3335 +
> drivers/gpu/drm/amd/amdgpu/vi.c | 4 +-
> drivers/gpu/drm/amd/display/Kconfig | 7 +
> drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 145 +-
> .../drm/amd/display/amdgpu_dm/amdgpu_dm_services.c | 10 +
> .../drm/amd/display/amdgpu_dm/amdgpu_dm_types.c | 20 +-
> drivers/gpu/drm/amd/display/dc/Makefile | 4 +
> drivers/gpu/drm/amd/display/dc/bios/Makefile | 8 +
> drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c | 2162 +
> drivers/gpu/drm/amd/display/dc/bios/bios_parser2.h | 33 +
> .../amd/display/dc/bios/bios_parser_interface.c | 14 +
> .../display/dc/bios/bios_parser_types_internal2.h | 74 +
> .../gpu/drm/amd/display/dc/bios/command_table2.c | 813 +
> .../gpu/drm/amd/display/dc/bios/command_table2.h | 105 +
> .../amd/display/dc/bios/command_table_helper2.c | 260 +
> .../amd/display/dc/bios/command_table_helper2.h | 82 +
> .../dc/bios/dce112/command_table_helper2_dce112.c | 418 +
> .../dc/bios/dce112/command_table_helper2_dce112.h | 34 +
> drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c | 117 +
> drivers/gpu/drm/amd/display/dc/core/dc.c | 29 +
> drivers/gpu/drm/amd/display/dc/core/dc_debug.c | 11 +
> drivers/gpu/drm/amd/display/dc/core/dc_link.c | 19 +
> drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 14 +
> drivers/gpu/drm/amd/display/dc/dc.h | 27 +
> drivers/gpu/drm/amd/display/dc/dc_hw_types.h | 46 +
> .../gpu/drm/amd/display/dc/dce/dce_clock_source.c | 6 +
> drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c | 149 +
> drivers/gpu/drm/amd/display/dc/dce/dce_clocks.h | 20 +
> drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h | 8 +
> .../gpu/drm/amd/display/dc/dce/dce_link_encoder.h | 14 +
> drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c | 35 +
> drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h | 34 +
> drivers/gpu/drm/amd/display/dc/dce/dce_opp.h | 72 +
> .../drm/amd/display/dc/dce/dce_stream_encoder.h | 100 +
> drivers/gpu/drm/amd/display/dc/dce/dce_transform.h | 68 +
> .../amd/display/dc/dce110/dce110_hw_sequencer.c | 53 +-
> .../drm/amd/display/dc/dce110/dce110_mem_input.c | 3 +
> .../display/dc/dce110/dce110_timing_generator.h | 3 +
> drivers/gpu/drm/amd/display/dc/dce120/Makefile | 12 +
> .../amd/display/dc/dce120/dce120_hw_sequencer.c | 197 +
> .../amd/display/dc/dce120/dce120_hw_sequencer.h | 36 +
> drivers/gpu/drm/amd/display/dc/dce120/dce120_ipp.c | 58 +
> drivers/gpu/drm/amd/display/dc/dce120/dce120_ipp.h | 62 +
> .../drm/amd/display/dc/dce120/dce120_ipp_cursor.c | 202 +
> .../drm/amd/display/dc/dce120/dce120_ipp_gamma.c | 167 +
> .../drm/amd/display/dc/dce120/dce120_mem_input.c | 340 +
> .../drm/amd/display/dc/dce120/dce120_mem_input.h | 37 +
> .../drm/amd/display/dc/dce120/dce120_resource.c | 1099 +
> .../drm/amd/display/dc/dce120/dce120_resource.h | 39 +
> .../display/dc/dce120/dce120_timing_generator.c | 1109 +
> .../display/dc/dce120/dce120_timing_generator.h | 41 +
> .../gpu/drm/amd/display/dc/dce80/dce80_mem_input.c | 3 +
> drivers/gpu/drm/amd/display/dc/dm_services.h | 89 +
> drivers/gpu/drm/amd/display/dc/dm_services_types.h | 27 +
> drivers/gpu/drm/amd/display/dc/gpio/Makefile | 11 +
> .../amd/display/dc/gpio/dce120/hw_factory_dce120.c | 197 +
> .../amd/display/dc/gpio/dce120/hw_factory_dce120.h | 32 +
> .../display/dc/gpio/dce120/hw_translate_dce120.c | 408 +
> .../display/dc/gpio/dce120/hw_translate_dce120.h | 34 +
> drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c | 9 +
> drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c | 9 +-
> drivers/gpu/drm/amd/display/dc/i2caux/Makefile | 11 +
> .../amd/display/dc/i2caux/dce120/i2caux_dce120.c | 125 +
> .../amd/display/dc/i2caux/dce120/i2caux_dce120.h | 32 +
> drivers/gpu/drm/amd/display/dc/i2caux/i2caux.c | 8 +
> .../gpu/drm/amd/display/dc/inc/bandwidth_calcs.h | 3 +
> .../gpu/drm/amd/display/dc/inc/hw/display_clock.h | 23 +
> drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h | 4 +
> drivers/gpu/drm/amd/display/dc/irq/Makefile | 12 +
> .../amd/display/dc/irq/dce120/irq_service_dce120.c | 293 +
> .../amd/display/dc/irq/dce120/irq_service_dce120.h | 34 +
> drivers/gpu/drm/amd/display/dc/irq/irq_service.c | 3 +
> drivers/gpu/drm/amd/display/include/dal_asic_id.h | 4 +
> drivers/gpu/drm/amd/display/include/dal_types.h | 3 +
> drivers/gpu/drm/amd/include/amd_shared.h | 4 +
> .../asic_reg/vega10/ATHUB/athub_1_0_default.h | 241 +
> .../asic_reg/vega10/ATHUB/athub_1_0_offset.h | 453 +
> .../asic_reg/vega10/ATHUB/athub_1_0_sh_mask.h | 2045 +
> .../include/asic_reg/vega10/DC/dce_12_0_default.h | 9868 ++
> .../include/asic_reg/vega10/DC/dce_12_0_offset.h | 18193 +++
> .../include/asic_reg/vega10/DC/dce_12_0_sh_mask.h | 64636 +++++++++
> .../include/asic_reg/vega10/GC/gc_9_0_default.h | 3873 +
> .../amd/include/asic_reg/vega10/GC/gc_9_0_offset.h | 7230 +
> .../include/asic_reg/vega10/GC/gc_9_0_sh_mask.h | 29868 ++++
> .../include/asic_reg/vega10/HDP/hdp_4_0_default.h | 117 +
> .../include/asic_reg/vega10/HDP/hdp_4_0_offset.h | 209 +
> .../include/asic_reg/vega10/HDP/hdp_4_0_sh_mask.h | 601 +
> .../asic_reg/vega10/MMHUB/mmhub_1_0_default.h | 1011 +
> .../asic_reg/vega10/MMHUB/mmhub_1_0_offset.h | 1967 +
> .../asic_reg/vega10/MMHUB/mmhub_1_0_sh_mask.h | 10127 ++
> .../include/asic_reg/vega10/MP/mp_9_0_default.h | 342 +
> .../amd/include/asic_reg/vega10/MP/mp_9_0_offset.h | 375 +
> .../include/asic_reg/vega10/MP/mp_9_0_sh_mask.h | 1463 +
> .../asic_reg/vega10/NBIF/nbif_6_1_default.h | 1271 +
> .../include/asic_reg/vega10/NBIF/nbif_6_1_offset.h | 1688 +
> .../asic_reg/vega10/NBIF/nbif_6_1_sh_mask.h | 10281 ++
> .../asic_reg/vega10/NBIO/nbio_6_1_default.h | 22340 +++
> .../include/asic_reg/vega10/NBIO/nbio_6_1_offset.h | 3649 +
> .../asic_reg/vega10/NBIO/nbio_6_1_sh_mask.h | 133884 ++++++++++++++++++
> .../asic_reg/vega10/OSSSYS/osssys_4_0_default.h | 176 +
> .../asic_reg/vega10/OSSSYS/osssys_4_0_offset.h | 327 +
> .../asic_reg/vega10/OSSSYS/osssys_4_0_sh_mask.h | 1196 +
> .../asic_reg/vega10/SDMA0/sdma0_4_0_default.h | 286 +
> .../asic_reg/vega10/SDMA0/sdma0_4_0_offset.h | 547 +
> .../asic_reg/vega10/SDMA0/sdma0_4_0_sh_mask.h | 1852 +
> .../asic_reg/vega10/SDMA1/sdma1_4_0_default.h | 282 +
> .../asic_reg/vega10/SDMA1/sdma1_4_0_offset.h | 539 +
> .../asic_reg/vega10/SDMA1/sdma1_4_0_sh_mask.h | 1810 +
> .../asic_reg/vega10/SMUIO/smuio_9_0_default.h | 100 +
> .../asic_reg/vega10/SMUIO/smuio_9_0_offset.h | 175 +
> .../asic_reg/vega10/SMUIO/smuio_9_0_sh_mask.h | 258 +
> .../include/asic_reg/vega10/THM/thm_9_0_default.h | 194 +
> .../include/asic_reg/vega10/THM/thm_9_0_offset.h | 363 +
> .../include/asic_reg/vega10/THM/thm_9_0_sh_mask.h | 1314 +
> .../include/asic_reg/vega10/UVD/uvd_7_0_default.h | 127 +
> .../include/asic_reg/vega10/UVD/uvd_7_0_offset.h | 222 +
> .../include/asic_reg/vega10/UVD/uvd_7_0_sh_mask.h | 811 +
> .../include/asic_reg/vega10/VCE/vce_4_0_default.h | 122 +
> .../include/asic_reg/vega10/VCE/vce_4_0_offset.h | 208 +
> .../include/asic_reg/vega10/VCE/vce_4_0_sh_mask.h | 488 +
> .../gpu/drm/amd/include/asic_reg/vega10/soc15ip.h | 1343 +
> .../drm/amd/include/asic_reg/vega10/vega10_enum.h | 22531 +++
> drivers/gpu/drm/amd/include/atomfirmware.h | 2385 +
> drivers/gpu/drm/amd/include/atomfirmwareid.h | 86 +
> drivers/gpu/drm/amd/include/displayobject.h | 249 +
> drivers/gpu/drm/amd/include/dm_pp_interface.h | 83 +
> drivers/gpu/drm/amd/include/v9_structs.h | 743 +
> drivers/gpu/drm/amd/powerplay/amd_powerplay.c | 284 +-
> drivers/gpu/drm/amd/powerplay/hwmgr/Makefile | 6 +-
> .../gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c | 49 +
> drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c | 9 +
> drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr_ppt.h | 16 +-
> drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.c | 396 +
> drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.h | 140 +
> drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c | 4378 +
> drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h | 434 +
> drivers/gpu/drm/amd/powerplay/hwmgr/vega10_inc.h | 44 +
> .../gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c | 137 +
> .../gpu/drm/amd/powerplay/hwmgr/vega10_powertune.h | 65 +
> .../gpu/drm/amd/powerplay/hwmgr/vega10_pptable.h | 331 +
> .../amd/powerplay/hwmgr/vega10_processpptables.c | 1056 +
> .../amd/powerplay/hwmgr/vega10_processpptables.h | 34 +
> .../gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c | 761 +
> .../gpu/drm/amd/powerplay/hwmgr/vega10_thermal.h | 83 +
> drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h | 28 +-
> .../gpu/drm/amd/powerplay/inc/hardwaremanager.h | 43 +
> drivers/gpu/drm/amd/powerplay/inc/hwmgr.h | 125 +-
> drivers/gpu/drm/amd/powerplay/inc/pp_instance.h | 1 +
> drivers/gpu/drm/amd/powerplay/inc/pp_soc15.h | 48 +
> drivers/gpu/drm/amd/powerplay/inc/smu9.h | 147 +
> drivers/gpu/drm/amd/powerplay/inc/smu9_driver_if.h | 418 +
> drivers/gpu/drm/amd/powerplay/inc/smumgr.h | 3 +
> drivers/gpu/drm/amd/powerplay/inc/vega10_ppsmc.h | 131 +
> drivers/gpu/drm/amd/powerplay/smumgr/Makefile | 2 +-
> drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c | 9 +
> .../gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c | 564 +
> .../gpu/drm/amd/powerplay/smumgr/vega10_smumgr.h | 70 +
> include/uapi/drm/amdgpu_drm.h | 29 +
> 221 files changed, 403408 insertions(+), 219 deletions(-)
> create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c
> create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.h
> create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
> create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
> create mode 100644 drivers/gpu/drm/amd/amdgpu/clearstate_gfx9.h
> create mode 100644 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> create mode 100644 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.h
> create mode 100644 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
> create mode 100644 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.h
> create mode 100644 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> create mode 100644 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.h
> create mode 100644 drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
> create mode 100644 drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.h
> create mode 100644 drivers/gpu/drm/amd/amdgpu/mmsch_v1_0.h
> create mode 100644 drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c
> create mode 100644 drivers/gpu/drm/amd/amdgpu/mxgpu_ai.h
> create mode 100644 drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c
> create mode 100644 drivers/gpu/drm/amd/amdgpu/nbio_v6_1.h
> create mode 100644 drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h
> create mode 100644 drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
> create mode 100644 drivers/gpu/drm/amd/amdgpu/psp_v3_1.h
> create mode 100644 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
> create mode 100644 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.h
> create mode 100644 drivers/gpu/drm/amd/amdgpu/soc15.c
> create mode 100644 drivers/gpu/drm/amd/amdgpu/soc15.h
> create mode 100644 drivers/gpu/drm/amd/amdgpu/soc15_common.h
> create mode 100644 drivers/gpu/drm/amd/amdgpu/soc15d.h
> create mode 100644 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
> create mode 100644 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.h
> create mode 100644 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
> create mode 100644 drivers/gpu/drm/amd/amdgpu/vce_v4_0.h
> create mode 100644 drivers/gpu/drm/amd/amdgpu/vega10_ih.c
> create mode 100644 drivers/gpu/drm/amd/amdgpu/vega10_ih.h
> create mode 100644 drivers/gpu/drm/amd/amdgpu/vega10_sdma_pkt_open.h
> create mode 100644 drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
> create mode 100644 drivers/gpu/drm/amd/display/dc/bios/bios_parser2.h
> create mode 100644 drivers/gpu/drm/amd/display/dc/bios/bios_parser_types_internal2.h
> create mode 100644 drivers/gpu/drm/amd/display/dc/bios/command_table2.c
> create mode 100644 drivers/gpu/drm/amd/display/dc/bios/command_table2.h
> create mode 100644 drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c
> create mode 100644 drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.h
> create mode 100644 drivers/gpu/drm/amd/display/dc/bios/dce112/command_table_helper2_dce112.c
> create mode 100644 drivers/gpu/drm/amd/display/dc/bios/dce112/command_table_helper2_dce112.h
> create mode 100644 drivers/gpu/drm/amd/display/dc/dce120/Makefile
> create mode 100644 drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.c
> create mode 100644 drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.h
> create mode 100644 drivers/gpu/drm/amd/display/dc/dce120/dce120_ipp.c
> create mode 100644 drivers/gpu/drm/amd/display/dc/dce120/dce120_ipp.h
> create mode 100644 drivers/gpu/drm/amd/display/dc/dce120/dce120_ipp_cursor.c
> create mode 100644 drivers/gpu/drm/amd/display/dc/dce120/dce120_ipp_gamma.c
> create mode 100644 drivers/gpu/drm/amd/display/dc/dce120/dce120_mem_input.c
> create mode 100644 drivers/gpu/drm/amd/display/dc/dce120/dce120_mem_input.h
> create mode 100644 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c
> create mode 100644 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.h
> create mode 100644 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c
> create mode 100644 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.h
> create mode 100644 drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_factory_dce120.c
> create mode 100644 drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_factory_dce120.h
> create mode 100644 drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c
> create mode 100644 drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.h
> create mode 100644 drivers/gpu/drm/amd/display/dc/i2caux/dce120/i2caux_dce120.c
> create mode 100644 drivers/gpu/drm/amd/display/dc/i2caux/dce120/i2caux_dce120.h
> create mode 100644 drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c
> create mode 100644 drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.h
> create mode 100644 drivers/gpu/drm/amd/include/asic_reg/vega10/ATHUB/athub_1_0_default.h
> create mode 100644 drivers/gpu/drm/amd/include/asic_reg/vega10/ATHUB/athub_1_0_offset.h
> create mode 100644 drivers/gpu/drm/amd/include/asic_reg/vega10/ATHUB/athub_1_0_sh_mask.h
> create mode 100644 drivers/gpu/drm/amd/include/asic_reg/vega10/DC/dce_12_0_default.h
> create mode 100644 drivers/gpu/drm/amd/include/asic_reg/vega10/DC/dce_12_0_offset.h
> create mode 100644 drivers/gpu/drm/amd/include/asic_reg/vega10/DC/dce_12_0_sh_mask.h
> create mode 100644 drivers/gpu/drm/amd/include/asic_reg/vega10/GC/gc_9_0_default.h
> create mode 100644 drivers/gpu/drm/amd/include/asic_reg/vega10/GC/gc_9_0_offset.h
> create mode 100644 drivers/gpu/drm/amd/include/asic_reg/vega10/GC/gc_9_0_sh_mask.h
> create mode 100644 drivers/gpu/drm/amd/include/asic_reg/vega10/HDP/hdp_4_0_default.h
> create mode 100644 drivers/gpu/drm/amd/include/asic_reg/vega10/HDP/hdp_4_0_offset.h
> create mode 100644 drivers/gpu/drm/amd/include/asic_reg/vega10/HDP/hdp_4_0_sh_mask.h
> create mode 100644 drivers/gpu/drm/amd/include/asic_reg/vega10/MMHUB/mmhub_1_0_default.h
> create mode 100644 drivers/gpu/drm/amd/include/asic_reg/vega10/MMHUB/mmhub_1_0_offset.h
> create mode 100644 drivers/gpu/drm/amd/include/asic_reg/vega10/MMHUB/mmhub_1_0_sh_mask.h
> create mode 100644 drivers/gpu/drm/amd/include/asic_reg/vega10/MP/mp_9_0_default.h
> create mode 100644 drivers/gpu/drm/amd/include/asic_reg/vega10/MP/mp_9_0_offset.h
> create mode 100644 drivers/gpu/drm/amd/include/asic_reg/vega10/MP/mp_9_0_sh_mask.h
> create mode 100644 drivers/gpu/drm/amd/include/asic_reg/vega10/NBIF/nbif_6_1_default.h
> create mode 100644 drivers/gpu/drm/amd/include/asic_reg/vega10/NBIF/nbif_6_1_offset.h
> create mode 100644 drivers/gpu/drm/amd/include/asic_reg/vega10/NBIF/nbif_6_1_sh_mask.h
> create mode 100644 drivers/gpu/drm/amd/include/asic_reg/vega10/NBIO/nbio_6_1_default.h
> create mode 100644 drivers/gpu/drm/amd/include/asic_reg/vega10/NBIO/nbio_6_1_offset.h
> create mode 100644 drivers/gpu/drm/amd/include/asic_reg/vega10/NBIO/nbio_6_1_sh_mask.h
> create mode 100644 drivers/gpu/drm/amd/include/asic_reg/vega10/OSSSYS/osssys_4_0_default.h
> create mode 100644 drivers/gpu/drm/amd/include/asic_reg/vega10/OSSSYS/osssys_4_0_offset.h
> create mode 100644 drivers/gpu/drm/amd/include/asic_reg/vega10/OSSSYS/osssys_4_0_sh_mask.h
> create mode 100644 drivers/gpu/drm/amd/include/asic_reg/vega10/SDMA0/sdma0_4_0_default.h
> create mode 100644 drivers/gpu/drm/amd/include/asic_reg/vega10/SDMA0/sdma0_4_0_offset.h
> create mode 100644 drivers/gpu/drm/amd/include/asic_reg/vega10/SDMA0/sdma0_4_0_sh_mask.h
> create mode 100644 drivers/gpu/drm/amd/include/asic_reg/vega10/SDMA1/sdma1_4_0_default.h
> create mode 100644 drivers/gpu/drm/amd/include/asic_reg/vega10/SDMA1/sdma1_4_0_offset.h
> create mode 100644 drivers/gpu/drm/amd/include/asic_reg/vega10/SDMA1/sdma1_4_0_sh_mask.h
> create mode 100644 drivers/gpu/drm/amd/include/asic_reg/vega10/SMUIO/smuio_9_0_default.h
> create mode 100644 drivers/gpu/drm/amd/include/asic_reg/vega10/SMUIO/smuio_9_0_offset.h
> create mode 100644 drivers/gpu/drm/amd/include/asic_reg/vega10/SMUIO/smuio_9_0_sh_mask.h
> create mode 100644 drivers/gpu/drm/amd/include/asic_reg/vega10/THM/thm_9_0_default.h
> create mode 100644 drivers/gpu/drm/amd/include/asic_reg/vega10/THM/thm_9_0_offset.h
> create mode 100644 drivers/gpu/drm/amd/include/asic_reg/vega10/THM/thm_9_0_sh_mask.h
> create mode 100644 drivers/gpu/drm/amd/include/asic_reg/vega10/UVD/uvd_7_0_default.h
> create mode 100644 drivers/gpu/drm/amd/include/asic_reg/vega10/UVD/uvd_7_0_offset.h
> create mode 100644 drivers/gpu/drm/amd/include/asic_reg/vega10/UVD/uvd_7_0_sh_mask.h
> create mode 100644 drivers/gpu/drm/amd/include/asic_reg/vega10/VCE/vce_4_0_default.h
> create mode 100644 drivers/gpu/drm/amd/include/asic_reg/vega10/VCE/vce_4_0_offset.h
> create mode 100644 drivers/gpu/drm/amd/include/asic_reg/vega10/VCE/vce_4_0_sh_mask.h
> create mode 100644 drivers/gpu/drm/amd/include/asic_reg/vega10/soc15ip.h
> create mode 100644 drivers/gpu/drm/amd/include/asic_reg/vega10/vega10_enum.h
> create mode 100644 drivers/gpu/drm/amd/include/atomfirmware.h
> create mode 100644 drivers/gpu/drm/amd/include/atomfirmwareid.h
> create mode 100644 drivers/gpu/drm/amd/include/displayobject.h
> create mode 100644 drivers/gpu/drm/amd/include/dm_pp_interface.h
> create mode 100644 drivers/gpu/drm/amd/include/v9_structs.h
> create mode 100644 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.c
> create mode 100644 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.h
> create mode 100644 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
> create mode 100644 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h
> create mode 100644 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_inc.h
> create mode 100644 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c
> create mode 100644 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.h
> create mode 100644 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_pptable.h
> create mode 100644 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c
> create mode 100644 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.h
> create mode 100644 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c
> create mode 100644 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.h
> create mode 100644 drivers/gpu/drm/amd/powerplay/inc/pp_soc15.h
> create mode 100644 drivers/gpu/drm/amd/powerplay/inc/smu9.h
> create mode 100644 drivers/gpu/drm/amd/powerplay/inc/smu9_driver_if.h
> create mode 100644 drivers/gpu/drm/amd/powerplay/inc/vega10_ppsmc.h
> create mode 100644 drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c
> create mode 100644 drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.h
>
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amd-gfx@lists.freedesktop.org
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^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH 000/100] Add Vega10 Support
@ 2017-03-20 20:29 Alex Deucher
[not found] ` <1490041835-11255-1-git-send-email-alexander.deucher-5C7GfCeVMHo@public.gmane.org>
0 siblings, 1 reply; 16+ messages in thread
From: Alex Deucher @ 2017-03-20 20:29 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Alex Deucher
This patch set adds support for vega10. Major changes and supported
features:
- new vbios interface
- Lots of new hw IPs
- Support for video decode using UVD
- Support for video encode using VCE
- Support for 3D via radeonsi
- Power management
- Full display support via DC
- Support for SR-IOV
I did not send out the register headers since they are huge. You can find them
along with all the other patches in this series here:
https://cgit.freedesktop.org/~agd5f/linux/log/?h=amd-staging-4.9
Please review.
Thanks,
Alex
Alex Deucher (29):
drm/amdgpu: add the new atomfirmware interface header
amdgpu: detect if we are using atomfirm or atombios for vbios (v2)
drm/amdgpu: move atom scratch setup into amdgpu_atombios.c
drm/amdgpu: add basic support for atomfirmware.h (v3)
drm/amdgpu: add soc15ip.h
drm/amdgpu: add vega10_enum.h
drm/amdgpu: Add ATHUB 1.0 register headers
drm/amdgpu: Add the DCE 12.0 register headers
drm/amdgpu: add the GC 9.0 register headers
drm/amdgpu: add the HDP 4.0 register headers
drm/amdgpu: add the MMHUB 1.0 register headers
drm/amdgpu: add MP 9.0 register headers
drm/amdgpu: add NBIF 6.1 register headers
drm/amdgpu: add NBIO 6.1 register headers
drm/amdgpu: add OSSSYS 4.0 register headers
drm/amdgpu: add SDMA 4.0 register headers
drm/amdgpu: add SMUIO 9.0 register headers
drm/amdgpu: add THM 9.0 register headers
drm/amdgpu: add the UVD 7.0 register headers
drm/amdgpu: add the VCE 4.0 register headers
drm/amdgpu: add gfx9 clearstate header
drm/amdgpu: add SDMA 4.0 packet header
drm/amdgpu: use atomfirmware interfaces for scratch reg save/restore
drm/amdgpu: update IH IV ring entry for soc-15
drm/amdgpu: add PTE defines for MTYPE
drm/amdgpu: add NGG parameters
drm/amdgpu: Add asic family for vega10
drm/amdgpu: add tiling flags for GFX9
drm/amdgpu: gart fixes for vega10
Alex Xie (4):
drm/amdgpu: Add MTYPE flags to GPU VM IOCTL interface
drm/amdgpu: handle PTE EXEC in amdgpu_vm_bo_split_mapping
drm/amdgpu: handle PTE MTYPE in amdgpu_vm_bo_split_mapping
drm/amdgpu: Add GMC 9.0 support
Andrey Grodzovsky (1):
drm/amdgpu: gb_addr_config struct
Charlene Liu (1):
drm/amd/display: need to handle DCE_Info table ver4.2
Christian König (1):
drm/amdgpu: add IV trace point
Eric Huang (7):
drm/amd/powerplay: add smu9 header files for Vega10
drm/amd/powerplay: add new Vega10's ppsmc header file
drm/amdgpu: add new atomfirmware based helpers for powerplay
drm/amd/powerplay: add some new structures for Vega10
drm/amd: add structures for display/powerplay interface
drm/amd/powerplay: add some display/powerplay interfaces
drm/amd/powerplay: add Vega10 powerplay support
Felix Kuehling (1):
drm/amd: Add MQD structs for GFX V9
Harry Wentland (6):
drm/amd/display: Add DCE12 bios parser support
drm/amd/display: Add DCE12 gpio support
drm/amd/display: Add DCE12 i2c/aux support
drm/amd/display: Add DCE12 irq support
drm/amd/display: Add DCE12 core support
drm/amd/display: Enable DCE12 support
Huang Rui (6):
drm/amdgpu: use new flag to handle different firmware loading method
drm/amdgpu: rework common ucode handling for vega10
drm/amdgpu: add psp firmware header info
drm/amdgpu: add PSP driver for vega10
drm/amdgpu: add psp firmware info into info query and debugfs
drm/amdgpu: add SMC firmware into global ucode list for psp loading
Jordan Lazare (1):
drm/amd/display: Less log spam
Junwei Zhang (2):
drm/amdgpu: add NBIO 6.1 driver
drm/amdgpu: add Vega10 Device IDs
Ken Wang (8):
drm/amdgpu: add common soc15 headers
drm/amdgpu: add vega10 chip name
drm/amdgpu: add 64bit doorbell assignments
drm/amdgpu: add SDMA v4.0 implementation
drm/amdgpu: implement GFX 9.0 support
drm/amdgpu: add vega10 interrupt handler
drm/amdgpu: soc15 enable (v2)
drm/amdgpu: Set the IP blocks for vega10
Leo Liu (2):
drm/amdgpu: add initial uvd 7.0 support for vega10
drm/amdgpu: add initial vce 4.0 support for vega10
Marek Olšák (1):
drm/amdgpu: don't validate TILE_SPLIT on GFX9
Monk Liu (5):
drm/amdgpu/gfx9: programing wptr_poll_addr register
drm/amdgpu:impl gfx9 cond_exec
drm/amdgpu:bypass RLC init for SRIOV
drm/amdgpu/sdma4:re-org SDMA initial steps for sriov
drm/amdgpu/vega10:fix DOORBELL64 scheme
Rex Zhu (2):
drm/amdgpu: get display info from DC when DC enabled.
drm/amd/powerplay: add global PowerPlay mutex.
Xiangliang Yu (22):
drm/amdgpu: impl sriov detection for vega10
drm/amdgpu: add kiq ring for gfx9
drm/amdgpu/gfx9: fullfill kiq funcs
drm/amdgpu/gfx9: fullfill kiq irq funcs
drm/amdgpu: init kiq and kcq for vega10
drm/amdgpu/gfx9: impl gfx9 meta data emit
drm/amdgpu/soc15: bypass PSP for VF
drm/amdgpu/gmc9: no need use kiq in vega10 tlb flush
drm/amdgpu/dce_virtual: bypass DPM for vf
drm/amdgpu/virt: impl mailbox for ai
drm/amdgpu/soc15: init virt ops for vf
drm/amdgpu/soc15: enable virtual dce for vf
drm/amdgpu: Don't touch PG&CG for SRIOV MM
drm/amdgpu/vce4: enable doorbell for SRIOV
drm/amdgpu: disable uvd for sriov
drm/amdgpu/soc15: bypass pp block for vf
drm/amdgpu/virt: add structure for MM table
drm/amdgpu/vce4: alloc mm table for MM sriov
drm/amdgpu/vce4: Ignore vce ring/ib test temporarily
drm/amdgpu: add mmsch structures
drm/amdgpu/vce4: impl vce & mmsch sriov start
drm/amdgpu/gfx9: correct wptr pointer value
ken (1):
drm/amdgpu: add clinetid definition for vega10
drivers/gpu/drm/amd/amdgpu/Makefile | 27 +-
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 172 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c | 28 +
drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.h | 3 +
drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c | 112 +
drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.h | 33 +
drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c | 30 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c | 73 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 73 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 36 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c | 3 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 2 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h | 47 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c | 3 +
drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 32 +
drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 5 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c | 5 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 473 +
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h | 127 +
drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h | 37 +
drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c | 113 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h | 17 +
drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c | 58 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c | 21 +
drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h | 7 +
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 34 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h | 4 +
drivers/gpu/drm/amd/amdgpu/atom.c | 26 -
drivers/gpu/drm/amd/amdgpu/atom.h | 1 -
drivers/gpu/drm/amd/amdgpu/cik.c | 2 +
drivers/gpu/drm/amd/amdgpu/clearstate_gfx9.h | 941 +
drivers/gpu/drm/amd/amdgpu/dce_virtual.c | 3 +
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 6 +-
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 4075 +
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.h | 35 +
drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c | 447 +
drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.h | 35 +
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 826 +
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.h | 30 +
drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c | 585 +
drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.h | 35 +
drivers/gpu/drm/amd/amdgpu/mmsch_v1_0.h | 87 +
drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c | 207 +
drivers/gpu/drm/amd/amdgpu/mxgpu_ai.h | 47 +
drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c | 251 +
drivers/gpu/drm/amd/amdgpu/nbio_v6_1.h | 53 +
drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h | 269 +
drivers/gpu/drm/amd/amdgpu/psp_v3_1.c | 507 +
drivers/gpu/drm/amd/amdgpu/psp_v3_1.h | 50 +
drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c | 4 +-
drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 4 +-
drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 1573 +
drivers/gpu/drm/amd/amdgpu/sdma_v4_0.h | 30 +
drivers/gpu/drm/amd/amdgpu/soc15.c | 825 +
drivers/gpu/drm/amd/amdgpu/soc15.h | 35 +
drivers/gpu/drm/amd/amdgpu/soc15_common.h | 57 +
drivers/gpu/drm/amd/amdgpu/soc15d.h | 287 +
drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c | 1543 +
drivers/gpu/drm/amd/amdgpu/uvd_v7_0.h | 29 +
drivers/gpu/drm/amd/amdgpu/vce_v4_0.c | 1141 +
drivers/gpu/drm/amd/amdgpu/vce_v4_0.h | 29 +
drivers/gpu/drm/amd/amdgpu/vega10_ih.c | 424 +
drivers/gpu/drm/amd/amdgpu/vega10_ih.h | 30 +
drivers/gpu/drm/amd/amdgpu/vega10_sdma_pkt_open.h | 3335 +
drivers/gpu/drm/amd/amdgpu/vi.c | 4 +-
drivers/gpu/drm/amd/display/Kconfig | 7 +
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 145 +-
.../drm/amd/display/amdgpu_dm/amdgpu_dm_services.c | 10 +
.../drm/amd/display/amdgpu_dm/amdgpu_dm_types.c | 20 +-
drivers/gpu/drm/amd/display/dc/Makefile | 4 +
drivers/gpu/drm/amd/display/dc/bios/Makefile | 8 +
drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c | 2162 +
drivers/gpu/drm/amd/display/dc/bios/bios_parser2.h | 33 +
.../amd/display/dc/bios/bios_parser_interface.c | 14 +
.../display/dc/bios/bios_parser_types_internal2.h | 74 +
.../gpu/drm/amd/display/dc/bios/command_table2.c | 813 +
.../gpu/drm/amd/display/dc/bios/command_table2.h | 105 +
.../amd/display/dc/bios/command_table_helper2.c | 260 +
.../amd/display/dc/bios/command_table_helper2.h | 82 +
.../dc/bios/dce112/command_table_helper2_dce112.c | 418 +
.../dc/bios/dce112/command_table_helper2_dce112.h | 34 +
drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c | 117 +
drivers/gpu/drm/amd/display/dc/core/dc.c | 29 +
drivers/gpu/drm/amd/display/dc/core/dc_debug.c | 11 +
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 19 +
drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 14 +
drivers/gpu/drm/amd/display/dc/dc.h | 27 +
drivers/gpu/drm/amd/display/dc/dc_hw_types.h | 46 +
.../gpu/drm/amd/display/dc/dce/dce_clock_source.c | 6 +
drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c | 149 +
drivers/gpu/drm/amd/display/dc/dce/dce_clocks.h | 20 +
drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h | 8 +
.../gpu/drm/amd/display/dc/dce/dce_link_encoder.h | 14 +
drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c | 35 +
drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h | 34 +
drivers/gpu/drm/amd/display/dc/dce/dce_opp.h | 72 +
.../drm/amd/display/dc/dce/dce_stream_encoder.h | 100 +
drivers/gpu/drm/amd/display/dc/dce/dce_transform.h | 68 +
.../amd/display/dc/dce110/dce110_hw_sequencer.c | 53 +-
.../drm/amd/display/dc/dce110/dce110_mem_input.c | 3 +
.../display/dc/dce110/dce110_timing_generator.h | 3 +
drivers/gpu/drm/amd/display/dc/dce120/Makefile | 12 +
.../amd/display/dc/dce120/dce120_hw_sequencer.c | 197 +
.../amd/display/dc/dce120/dce120_hw_sequencer.h | 36 +
drivers/gpu/drm/amd/display/dc/dce120/dce120_ipp.c | 58 +
drivers/gpu/drm/amd/display/dc/dce120/dce120_ipp.h | 62 +
.../drm/amd/display/dc/dce120/dce120_ipp_cursor.c | 202 +
.../drm/amd/display/dc/dce120/dce120_ipp_gamma.c | 167 +
.../drm/amd/display/dc/dce120/dce120_mem_input.c | 340 +
.../drm/amd/display/dc/dce120/dce120_mem_input.h | 37 +
.../drm/amd/display/dc/dce120/dce120_resource.c | 1099 +
.../drm/amd/display/dc/dce120/dce120_resource.h | 39 +
.../display/dc/dce120/dce120_timing_generator.c | 1109 +
.../display/dc/dce120/dce120_timing_generator.h | 41 +
.../gpu/drm/amd/display/dc/dce80/dce80_mem_input.c | 3 +
drivers/gpu/drm/amd/display/dc/dm_services.h | 89 +
drivers/gpu/drm/amd/display/dc/dm_services_types.h | 27 +
drivers/gpu/drm/amd/display/dc/gpio/Makefile | 11 +
.../amd/display/dc/gpio/dce120/hw_factory_dce120.c | 197 +
.../amd/display/dc/gpio/dce120/hw_factory_dce120.h | 32 +
.../display/dc/gpio/dce120/hw_translate_dce120.c | 408 +
.../display/dc/gpio/dce120/hw_translate_dce120.h | 34 +
drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c | 9 +
drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c | 9 +-
drivers/gpu/drm/amd/display/dc/i2caux/Makefile | 11 +
.../amd/display/dc/i2caux/dce120/i2caux_dce120.c | 125 +
.../amd/display/dc/i2caux/dce120/i2caux_dce120.h | 32 +
drivers/gpu/drm/amd/display/dc/i2caux/i2caux.c | 8 +
.../gpu/drm/amd/display/dc/inc/bandwidth_calcs.h | 3 +
.../gpu/drm/amd/display/dc/inc/hw/display_clock.h | 23 +
drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h | 4 +
drivers/gpu/drm/amd/display/dc/irq/Makefile | 12 +
.../amd/display/dc/irq/dce120/irq_service_dce120.c | 293 +
.../amd/display/dc/irq/dce120/irq_service_dce120.h | 34 +
drivers/gpu/drm/amd/display/dc/irq/irq_service.c | 3 +
drivers/gpu/drm/amd/display/include/dal_asic_id.h | 4 +
drivers/gpu/drm/amd/display/include/dal_types.h | 3 +
drivers/gpu/drm/amd/include/amd_shared.h | 4 +
.../asic_reg/vega10/ATHUB/athub_1_0_default.h | 241 +
.../asic_reg/vega10/ATHUB/athub_1_0_offset.h | 453 +
.../asic_reg/vega10/ATHUB/athub_1_0_sh_mask.h | 2045 +
.../include/asic_reg/vega10/DC/dce_12_0_default.h | 9868 ++
.../include/asic_reg/vega10/DC/dce_12_0_offset.h | 18193 +++
.../include/asic_reg/vega10/DC/dce_12_0_sh_mask.h | 64636 +++++++++
.../include/asic_reg/vega10/GC/gc_9_0_default.h | 3873 +
.../amd/include/asic_reg/vega10/GC/gc_9_0_offset.h | 7230 +
.../include/asic_reg/vega10/GC/gc_9_0_sh_mask.h | 29868 ++++
.../include/asic_reg/vega10/HDP/hdp_4_0_default.h | 117 +
.../include/asic_reg/vega10/HDP/hdp_4_0_offset.h | 209 +
.../include/asic_reg/vega10/HDP/hdp_4_0_sh_mask.h | 601 +
.../asic_reg/vega10/MMHUB/mmhub_1_0_default.h | 1011 +
.../asic_reg/vega10/MMHUB/mmhub_1_0_offset.h | 1967 +
.../asic_reg/vega10/MMHUB/mmhub_1_0_sh_mask.h | 10127 ++
.../include/asic_reg/vega10/MP/mp_9_0_default.h | 342 +
.../amd/include/asic_reg/vega10/MP/mp_9_0_offset.h | 375 +
.../include/asic_reg/vega10/MP/mp_9_0_sh_mask.h | 1463 +
.../asic_reg/vega10/NBIF/nbif_6_1_default.h | 1271 +
.../include/asic_reg/vega10/NBIF/nbif_6_1_offset.h | 1688 +
.../asic_reg/vega10/NBIF/nbif_6_1_sh_mask.h | 10281 ++
.../asic_reg/vega10/NBIO/nbio_6_1_default.h | 22340 +++
.../include/asic_reg/vega10/NBIO/nbio_6_1_offset.h | 3649 +
.../asic_reg/vega10/NBIO/nbio_6_1_sh_mask.h | 133884 ++++++++++++++++++
.../asic_reg/vega10/OSSSYS/osssys_4_0_default.h | 176 +
.../asic_reg/vega10/OSSSYS/osssys_4_0_offset.h | 327 +
.../asic_reg/vega10/OSSSYS/osssys_4_0_sh_mask.h | 1196 +
.../asic_reg/vega10/SDMA0/sdma0_4_0_default.h | 286 +
.../asic_reg/vega10/SDMA0/sdma0_4_0_offset.h | 547 +
.../asic_reg/vega10/SDMA0/sdma0_4_0_sh_mask.h | 1852 +
.../asic_reg/vega10/SDMA1/sdma1_4_0_default.h | 282 +
.../asic_reg/vega10/SDMA1/sdma1_4_0_offset.h | 539 +
.../asic_reg/vega10/SDMA1/sdma1_4_0_sh_mask.h | 1810 +
.../asic_reg/vega10/SMUIO/smuio_9_0_default.h | 100 +
.../asic_reg/vega10/SMUIO/smuio_9_0_offset.h | 175 +
.../asic_reg/vega10/SMUIO/smuio_9_0_sh_mask.h | 258 +
.../include/asic_reg/vega10/THM/thm_9_0_default.h | 194 +
.../include/asic_reg/vega10/THM/thm_9_0_offset.h | 363 +
.../include/asic_reg/vega10/THM/thm_9_0_sh_mask.h | 1314 +
.../include/asic_reg/vega10/UVD/uvd_7_0_default.h | 127 +
.../include/asic_reg/vega10/UVD/uvd_7_0_offset.h | 222 +
.../include/asic_reg/vega10/UVD/uvd_7_0_sh_mask.h | 811 +
.../include/asic_reg/vega10/VCE/vce_4_0_default.h | 122 +
.../include/asic_reg/vega10/VCE/vce_4_0_offset.h | 208 +
.../include/asic_reg/vega10/VCE/vce_4_0_sh_mask.h | 488 +
.../gpu/drm/amd/include/asic_reg/vega10/soc15ip.h | 1343 +
.../drm/amd/include/asic_reg/vega10/vega10_enum.h | 22531 +++
drivers/gpu/drm/amd/include/atomfirmware.h | 2385 +
drivers/gpu/drm/amd/include/atomfirmwareid.h | 86 +
drivers/gpu/drm/amd/include/displayobject.h | 249 +
drivers/gpu/drm/amd/include/dm_pp_interface.h | 83 +
drivers/gpu/drm/amd/include/v9_structs.h | 743 +
drivers/gpu/drm/amd/powerplay/amd_powerplay.c | 284 +-
drivers/gpu/drm/amd/powerplay/hwmgr/Makefile | 6 +-
.../gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c | 49 +
drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c | 9 +
drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr_ppt.h | 16 +-
drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.c | 396 +
drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.h | 140 +
drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c | 4378 +
drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h | 434 +
drivers/gpu/drm/amd/powerplay/hwmgr/vega10_inc.h | 44 +
.../gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c | 137 +
.../gpu/drm/amd/powerplay/hwmgr/vega10_powertune.h | 65 +
.../gpu/drm/amd/powerplay/hwmgr/vega10_pptable.h | 331 +
.../amd/powerplay/hwmgr/vega10_processpptables.c | 1056 +
.../amd/powerplay/hwmgr/vega10_processpptables.h | 34 +
.../gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c | 761 +
.../gpu/drm/amd/powerplay/hwmgr/vega10_thermal.h | 83 +
drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h | 28 +-
.../gpu/drm/amd/powerplay/inc/hardwaremanager.h | 43 +
drivers/gpu/drm/amd/powerplay/inc/hwmgr.h | 125 +-
drivers/gpu/drm/amd/powerplay/inc/pp_instance.h | 1 +
drivers/gpu/drm/amd/powerplay/inc/pp_soc15.h | 48 +
drivers/gpu/drm/amd/powerplay/inc/smu9.h | 147 +
drivers/gpu/drm/amd/powerplay/inc/smu9_driver_if.h | 418 +
drivers/gpu/drm/amd/powerplay/inc/smumgr.h | 3 +
drivers/gpu/drm/amd/powerplay/inc/vega10_ppsmc.h | 131 +
drivers/gpu/drm/amd/powerplay/smumgr/Makefile | 2 +-
drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c | 9 +
.../gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c | 564 +
.../gpu/drm/amd/powerplay/smumgr/vega10_smumgr.h | 70 +
include/uapi/drm/amdgpu_drm.h | 29 +
221 files changed, 403408 insertions(+), 219 deletions(-)
create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c
create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.h
create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
create mode 100644 drivers/gpu/drm/amd/amdgpu/clearstate_gfx9.h
create mode 100644 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
create mode 100644 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.h
create mode 100644 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
create mode 100644 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.h
create mode 100644 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
create mode 100644 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.h
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create mode 100644 drivers/gpu/drm/amd/include/asic_reg/vega10/OSSSYS/osssys_4_0_default.h
create mode 100644 drivers/gpu/drm/amd/include/asic_reg/vega10/OSSSYS/osssys_4_0_offset.h
create mode 100644 drivers/gpu/drm/amd/include/asic_reg/vega10/OSSSYS/osssys_4_0_sh_mask.h
create mode 100644 drivers/gpu/drm/amd/include/asic_reg/vega10/SDMA0/sdma0_4_0_default.h
create mode 100644 drivers/gpu/drm/amd/include/asic_reg/vega10/SDMA0/sdma0_4_0_offset.h
create mode 100644 drivers/gpu/drm/amd/include/asic_reg/vega10/SDMA0/sdma0_4_0_sh_mask.h
create mode 100644 drivers/gpu/drm/amd/include/asic_reg/vega10/SDMA1/sdma1_4_0_default.h
create mode 100644 drivers/gpu/drm/amd/include/asic_reg/vega10/SDMA1/sdma1_4_0_offset.h
create mode 100644 drivers/gpu/drm/amd/include/asic_reg/vega10/SDMA1/sdma1_4_0_sh_mask.h
create mode 100644 drivers/gpu/drm/amd/include/asic_reg/vega10/SMUIO/smuio_9_0_default.h
create mode 100644 drivers/gpu/drm/amd/include/asic_reg/vega10/SMUIO/smuio_9_0_offset.h
create mode 100644 drivers/gpu/drm/amd/include/asic_reg/vega10/SMUIO/smuio_9_0_sh_mask.h
create mode 100644 drivers/gpu/drm/amd/include/asic_reg/vega10/THM/thm_9_0_default.h
create mode 100644 drivers/gpu/drm/amd/include/asic_reg/vega10/THM/thm_9_0_offset.h
create mode 100644 drivers/gpu/drm/amd/include/asic_reg/vega10/THM/thm_9_0_sh_mask.h
create mode 100644 drivers/gpu/drm/amd/include/asic_reg/vega10/UVD/uvd_7_0_default.h
create mode 100644 drivers/gpu/drm/amd/include/asic_reg/vega10/UVD/uvd_7_0_offset.h
create mode 100644 drivers/gpu/drm/amd/include/asic_reg/vega10/UVD/uvd_7_0_sh_mask.h
create mode 100644 drivers/gpu/drm/amd/include/asic_reg/vega10/VCE/vce_4_0_default.h
create mode 100644 drivers/gpu/drm/amd/include/asic_reg/vega10/VCE/vce_4_0_offset.h
create mode 100644 drivers/gpu/drm/amd/include/asic_reg/vega10/VCE/vce_4_0_sh_mask.h
create mode 100644 drivers/gpu/drm/amd/include/asic_reg/vega10/soc15ip.h
create mode 100644 drivers/gpu/drm/amd/include/asic_reg/vega10/vega10_enum.h
create mode 100644 drivers/gpu/drm/amd/include/atomfirmware.h
create mode 100644 drivers/gpu/drm/amd/include/atomfirmwareid.h
create mode 100644 drivers/gpu/drm/amd/include/displayobject.h
create mode 100644 drivers/gpu/drm/amd/include/dm_pp_interface.h
create mode 100644 drivers/gpu/drm/amd/include/v9_structs.h
create mode 100644 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.c
create mode 100644 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.h
create mode 100644 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
create mode 100644 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h
create mode 100644 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_inc.h
create mode 100644 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c
create mode 100644 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_powertune.h
create mode 100644 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_pptable.h
create mode 100644 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c
create mode 100644 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.h
create mode 100644 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.c
create mode 100644 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_thermal.h
create mode 100644 drivers/gpu/drm/amd/powerplay/inc/pp_soc15.h
create mode 100644 drivers/gpu/drm/amd/powerplay/inc/smu9.h
create mode 100644 drivers/gpu/drm/amd/powerplay/inc/smu9_driver_if.h
create mode 100644 drivers/gpu/drm/amd/powerplay/inc/vega10_ppsmc.h
create mode 100644 drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c
create mode 100644 drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.h
--
2.5.5
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^ permalink raw reply [flat|nested] 16+ messages in thread
end of thread, other threads:[~2017-03-21 22:00 UTC | newest]
Thread overview: 16+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2017-03-20 21:36 [PATCH 000/100] Add Vega10 Support Jan Ziak
[not found] ` <CAODFU0pW=uyAa9Bdjbzv63cFaBMoF34+rW9xWDorAuMKHFsRUQ-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2017-03-20 21:41 ` Alex Deucher
[not found] ` <CADnq5_ONBTDeGQC_3ApDBv+xa88r5ZvA0RHiZHbohYBZ48=F5g-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2017-03-20 22:34 ` Jan Ziak
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2017-03-20 23:38 ` Tom St Denis
[not found] ` <d1dc991e-8ae7-eae9-65bf-97c6319e8d17-5C7GfCeVMHo@public.gmane.org>
2017-03-21 6:36 ` Christian König
[not found] ` <608e9c51-6610-bf11-a22a-a1f07e5cf4a9-5C7GfCeVMHo@public.gmane.org>
2017-03-21 8:45 ` Edward O'Callaghan
[not found] ` <37027c02-1f10-858e-ca22-a6fc7cad330a-dczkZgxz+BNUPWh3PAxdjQ@public.gmane.org>
2017-03-21 9:01 ` Christian König
[not found] ` <94df79ba-c393-71a8-a825-7ab14f39a967-5C7GfCeVMHo@public.gmane.org>
2017-03-21 15:14 ` Deucher, Alexander
[not found] ` <BN6PR12MB16526C8CA934A46308790AC0F73D0-/b2+HYfkarQqUD6E6FAiowdYzm3356FpvxpqHgZTriW3zl9H0oFU5g@public.gmane.org>
2017-03-21 19:43 ` Andres Rodriguez
2017-03-21 12:12 ` Marek Olšák
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2017-03-20 20:29 Alex Deucher
[not found] ` <1490041835-11255-1-git-send-email-alexander.deucher-5C7GfCeVMHo@public.gmane.org>
2017-03-21 7:42 ` Christian König
[not found] ` <50d03274-5a6e-fb77-9741-b6700a9949bd-ANTagKRnAhcb1SvskN2V4Q@public.gmane.org>
2017-03-21 11:51 ` Christian König
[not found] ` <b717602f-7573-6c20-ca68-491e3fe847c0-ANTagKRnAhcb1SvskN2V4Q@public.gmane.org>
2017-03-21 12:18 ` Christian König
[not found] ` <15b7d1b4-8ac7-d14b-40f6-aba529b301ea-ANTagKRnAhcb1SvskN2V4Q@public.gmane.org>
2017-03-21 15:54 ` Alex Deucher
2017-03-21 22:00 ` Alex Deucher
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