From: Parthiban <parthiban@linumiz.com>
To: Marco Felsch <m.felsch@pengutronix.de>
Cc: robh+dt@kernel.org, shawnguo@kernel.org, s.hauer@pengutronix.de,
kernel@pengutronix.de, festevam@gmail.com, linux-imx@nxp.com,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
Parthiban <parthiban@linumiz.com>
Subject: Re: [PATCH] ARM: dts: imx6ull: add MYiR MYS-6ULX SBC
Date: Mon, 1 Jun 2020 16:55:08 +0200 [thread overview]
Message-ID: <9077f6b0-66ac-8854-75fe-5bebb8314fc2@linumiz.com> (raw)
In-Reply-To: <20200427061844.i5hb2xatq2ntdqbe@pengutronix.de>
On 4/27/20 8:18 AM, Marco Felsch wrote:
> Hi Parthiban,
>
> a few more minor comments..
>
> On 20-04-08 20:43, Parthiban Nallathambi wrote:
>
> ...
>
>> diff --git a/arch/arm/boot/dts/imx6ull-myir-mys-6ulx.dtsi b/arch/arm/boot/dts/imx6ull-myir-mys-6ulx.dtsi
>> new file mode 100644
>> index 000000000000..f0a514187c21
>> --- /dev/null
>> +++ b/arch/arm/boot/dts/imx6ull-myir-mys-6ulx.dtsi
>> @@ -0,0 +1,247 @@
>> +// SPDX-License-Identifier: GPL-2.0
>> +/*
>> + * Copyright (C) 2020 Linumiz
>> + * Author: Parthiban Nallathambi <parthiban@linumiz.com>
>> + */
>> +
>> +#include <dt-bindings/gpio/gpio.h>
>> +#include <dt-bindings/interrupt-controller/irq.h>
>> +#include <dt-bindings/pwm/pwm.h>
>> +
>> +/ {
>> + model = "MYiR MYS-6ULX Single Board Computer";
>> + compatible = "myir,imx6ull-mys-6ulx", "fsl,imx6ull";
>> +
>> + chosen {
>> + stdout-path = &uart1;
>> + };
>> +
>> + regulators: regulators {
>> + compatible = "simple-bus";
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + vdd_5v: regulator@0 {
>> + compatible = "regulator-fixed";
>> + regulator-name = "VDD_5V";
>> + regulator-min-microvolt = <5000000>;
>> + regulator-max-microvolt = <5000000>;
>> + regulator-always-on;
>> + regulator-boot-on;
>> + };
>> +
>> + vdd_3v3: regulator@1 {
>> + compatible = "regulator-fixed";
>> + regulator-name = "VDD_3V3";
>> + regulator-min-microvolt = <3300000>;
>> + regulator-max-microvolt = <3300000>;
>> + regulator-always-on;
>> + vin-supply = <&vdd_5v>;
>> + };
>> + };
>> +};
>> +
>> +&fec1 {
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&pinctrl_enet1>;
>> + phy-mode = "rmii";
>> + phy-handle = <ðphy0>;
>> + phy-supply = <&vdd_3v3>;
>> + status = "okay";
>> +
>> + mdio: mdio {
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + ethphy0: ethernet-phy@0 {
>> + reg = <0>;
>> + compatible = "ethernet-phy-ieee802.3-c22";
>> + interrupt-parent = <&gpio5>;
>> + interrupts = <5 IRQ_TYPE_LEVEL_LOW>;
>> + clocks = <&clks IMX6UL_CLK_ENET_REF>;
>> + clock-names = "rmii-ref";
>> + status = "okay";
>
> Status not needed here.
Thanks, removed it.
>
>> + };
>> + };
>> +};
>> +
>> +&gpmi {
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&pinctrl_gpmi_nand>;
>> + nand-on-flash-bbt;
>> + status = "disabled";
>> +};
>> +
>> +&uart1 {
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&pinctrl_uart1>;
>> + status = "okay";
>> +};
>> +
>> +&usbotg1 {
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&pinctrl_usb_otg1_id>;
>> + dr_mode = "otg";
>> + status = "okay";
>> +};
>> +
>> +&usbotg2 {
>> + dr_mode = "host";
>> + disable-over-current;
>> + status = "okay";
>> +};
>> +
>> +&usdhc1 {
>> + pinctrl-names = "default", "state_100mhz", "state_200mhz";
>> + pinctrl-0 = <&pinctrl_usdhc1>;
>> + pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
>> + pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
>> + cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
>> + no-1-8-v;
>> + keep-power-in-suspend;
>> + wakeup-source;
>> + vmmc-supply = <&vdd_3v3>;
>> + status = "okay";
>> +};
>> +
>> +&usdhc2 {
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&pinctrl_usdhc2>;
>> + pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
>> + pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
>> + bus-width = <8>;
>> + non-removable;
>> + keep-power-in-suspend;
>> + vmmc-supply = <&vdd_3v3>;
>> + status = "disabled";
>
> Status not needed here.
Removed, thanks.
>
> Regards,
> Marco
>
>> +};
>> +
>> +&iomuxc {
>> + pinctrl_enet1: enet1grp {
>> + fsl,pins = <
>> + MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x1b0b0
>> + MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x1b0b0
>> + MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0
>> + MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0
>> + MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0
>> + MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0
>> + MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0
>> + MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0
>> + MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0
>> + MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031
>> + MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x1b0b0
>> + >;
>> + };
>> +
>> + pinctrl_gpmi_nand: gpminandgrp {
>> + fsl,pins = <
>> + MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0x0b0b1
>> + MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0x0b0b1
>> + MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B 0x0b0b1
>> + MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0x0b000
>> + MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0x0b0b1
>> + MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0x0b0b1
>> + MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0x0b0b1
>> + MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0x0b0b1
>> + MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0x0b0b1
>> + MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0x0b0b1
>> + MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0x0b0b1
>> + MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0x0b0b1
>> + MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0x0b0b1
>> + MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0x0b0b1
>> + MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0x0b0b1
>> + >;
>> + };
>> +
>> + pinctrl_uart1: uart1grp {
>> + fsl,pins = <
>> + MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
>> + MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1
>> + >;
>> + };
>> +
>> + pinctrl_usb_otg1_id: usbotg1idgrp {
>> + fsl,pins = <
>> + MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x17059
>> + >;
>> + };
>> +
>> + pinctrl_usdhc1: usdhc1grp {
>> + fsl,pins = <
>> + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059
>> + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059
>> + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059
>> + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059
>> + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059
>> + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
>> + MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x17059
>> + >;
>> + };
>> +
>> + pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
>> + fsl,pins = <
>> + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9
>> + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9
>> + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9
>> + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9
>> + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9
>> + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9
>> + >;
>> + };
>> +
>> + pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
>> + fsl,pins = <
>> + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9
>> + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9
>> + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9
>> + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9
>> + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9
>> + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9
>> + >;
>> + };
>> +
>> + pinctrl_usdhc2: usdhc2grp {
>> + fsl,pins = <
>> + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10069
>> + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059
>> + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059
>> + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059
>> + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059
>> + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059
>> + MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x17059
>> + MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x17059
>> + MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x17059
>> + MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x17059
>> + >;
>> + };
>> +
>> + pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
>> + fsl,pins = <
>> + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100b9
>> + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170b9
>> + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170b9
>> + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170b9
>> + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170b9
>> + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170b9
>> + MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170b9
>> + MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170b9
>> + MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170b9
>> + MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170b9
>> + >;
>> + };
>> +
>> + pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
>> + fsl,pins = <
>> + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100f9
>> + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170f9
>> + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170f9
>> + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170f9
>> + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170f9
>> + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170f9
>> + MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170f9
>> + MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170f9
>> + MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170f9
>> + MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170f9
>> + >;
>> + };
>> +};
>> --
>> 2.11.0
>>
--
Thanks,
Parthiban N
+4915163761545
WARNING: multiple messages have this Message-ID (diff)
From: Parthiban <parthiban@linumiz.com>
To: Marco Felsch <m.felsch@pengutronix.de>
Cc: devicetree@vger.kernel.org, Parthiban <parthiban@linumiz.com>,
shawnguo@kernel.org, s.hauer@pengutronix.de,
linux-kernel@vger.kernel.org, robh+dt@kernel.org,
linux-imx@nxp.com, kernel@pengutronix.de, festevam@gmail.com,
linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH] ARM: dts: imx6ull: add MYiR MYS-6ULX SBC
Date: Mon, 1 Jun 2020 16:55:08 +0200 [thread overview]
Message-ID: <9077f6b0-66ac-8854-75fe-5bebb8314fc2@linumiz.com> (raw)
In-Reply-To: <20200427061844.i5hb2xatq2ntdqbe@pengutronix.de>
On 4/27/20 8:18 AM, Marco Felsch wrote:
> Hi Parthiban,
>
> a few more minor comments..
>
> On 20-04-08 20:43, Parthiban Nallathambi wrote:
>
> ...
>
>> diff --git a/arch/arm/boot/dts/imx6ull-myir-mys-6ulx.dtsi b/arch/arm/boot/dts/imx6ull-myir-mys-6ulx.dtsi
>> new file mode 100644
>> index 000000000000..f0a514187c21
>> --- /dev/null
>> +++ b/arch/arm/boot/dts/imx6ull-myir-mys-6ulx.dtsi
>> @@ -0,0 +1,247 @@
>> +// SPDX-License-Identifier: GPL-2.0
>> +/*
>> + * Copyright (C) 2020 Linumiz
>> + * Author: Parthiban Nallathambi <parthiban@linumiz.com>
>> + */
>> +
>> +#include <dt-bindings/gpio/gpio.h>
>> +#include <dt-bindings/interrupt-controller/irq.h>
>> +#include <dt-bindings/pwm/pwm.h>
>> +
>> +/ {
>> + model = "MYiR MYS-6ULX Single Board Computer";
>> + compatible = "myir,imx6ull-mys-6ulx", "fsl,imx6ull";
>> +
>> + chosen {
>> + stdout-path = &uart1;
>> + };
>> +
>> + regulators: regulators {
>> + compatible = "simple-bus";
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + vdd_5v: regulator@0 {
>> + compatible = "regulator-fixed";
>> + regulator-name = "VDD_5V";
>> + regulator-min-microvolt = <5000000>;
>> + regulator-max-microvolt = <5000000>;
>> + regulator-always-on;
>> + regulator-boot-on;
>> + };
>> +
>> + vdd_3v3: regulator@1 {
>> + compatible = "regulator-fixed";
>> + regulator-name = "VDD_3V3";
>> + regulator-min-microvolt = <3300000>;
>> + regulator-max-microvolt = <3300000>;
>> + regulator-always-on;
>> + vin-supply = <&vdd_5v>;
>> + };
>> + };
>> +};
>> +
>> +&fec1 {
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&pinctrl_enet1>;
>> + phy-mode = "rmii";
>> + phy-handle = <ðphy0>;
>> + phy-supply = <&vdd_3v3>;
>> + status = "okay";
>> +
>> + mdio: mdio {
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + ethphy0: ethernet-phy@0 {
>> + reg = <0>;
>> + compatible = "ethernet-phy-ieee802.3-c22";
>> + interrupt-parent = <&gpio5>;
>> + interrupts = <5 IRQ_TYPE_LEVEL_LOW>;
>> + clocks = <&clks IMX6UL_CLK_ENET_REF>;
>> + clock-names = "rmii-ref";
>> + status = "okay";
>
> Status not needed here.
Thanks, removed it.
>
>> + };
>> + };
>> +};
>> +
>> +&gpmi {
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&pinctrl_gpmi_nand>;
>> + nand-on-flash-bbt;
>> + status = "disabled";
>> +};
>> +
>> +&uart1 {
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&pinctrl_uart1>;
>> + status = "okay";
>> +};
>> +
>> +&usbotg1 {
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&pinctrl_usb_otg1_id>;
>> + dr_mode = "otg";
>> + status = "okay";
>> +};
>> +
>> +&usbotg2 {
>> + dr_mode = "host";
>> + disable-over-current;
>> + status = "okay";
>> +};
>> +
>> +&usdhc1 {
>> + pinctrl-names = "default", "state_100mhz", "state_200mhz";
>> + pinctrl-0 = <&pinctrl_usdhc1>;
>> + pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
>> + pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
>> + cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
>> + no-1-8-v;
>> + keep-power-in-suspend;
>> + wakeup-source;
>> + vmmc-supply = <&vdd_3v3>;
>> + status = "okay";
>> +};
>> +
>> +&usdhc2 {
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&pinctrl_usdhc2>;
>> + pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
>> + pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
>> + bus-width = <8>;
>> + non-removable;
>> + keep-power-in-suspend;
>> + vmmc-supply = <&vdd_3v3>;
>> + status = "disabled";
>
> Status not needed here.
Removed, thanks.
>
> Regards,
> Marco
>
>> +};
>> +
>> +&iomuxc {
>> + pinctrl_enet1: enet1grp {
>> + fsl,pins = <
>> + MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x1b0b0
>> + MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x1b0b0
>> + MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0
>> + MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0
>> + MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0
>> + MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0
>> + MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0
>> + MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0
>> + MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0
>> + MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031
>> + MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x1b0b0
>> + >;
>> + };
>> +
>> + pinctrl_gpmi_nand: gpminandgrp {
>> + fsl,pins = <
>> + MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0x0b0b1
>> + MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0x0b0b1
>> + MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B 0x0b0b1
>> + MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0x0b000
>> + MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0x0b0b1
>> + MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0x0b0b1
>> + MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0x0b0b1
>> + MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0x0b0b1
>> + MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0x0b0b1
>> + MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0x0b0b1
>> + MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0x0b0b1
>> + MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0x0b0b1
>> + MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0x0b0b1
>> + MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0x0b0b1
>> + MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0x0b0b1
>> + >;
>> + };
>> +
>> + pinctrl_uart1: uart1grp {
>> + fsl,pins = <
>> + MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
>> + MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1
>> + >;
>> + };
>> +
>> + pinctrl_usb_otg1_id: usbotg1idgrp {
>> + fsl,pins = <
>> + MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x17059
>> + >;
>> + };
>> +
>> + pinctrl_usdhc1: usdhc1grp {
>> + fsl,pins = <
>> + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059
>> + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059
>> + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059
>> + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059
>> + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059
>> + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
>> + MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x17059
>> + >;
>> + };
>> +
>> + pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
>> + fsl,pins = <
>> + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9
>> + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9
>> + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9
>> + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9
>> + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9
>> + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9
>> + >;
>> + };
>> +
>> + pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
>> + fsl,pins = <
>> + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9
>> + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9
>> + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9
>> + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9
>> + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9
>> + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9
>> + >;
>> + };
>> +
>> + pinctrl_usdhc2: usdhc2grp {
>> + fsl,pins = <
>> + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10069
>> + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059
>> + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059
>> + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059
>> + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059
>> + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059
>> + MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x17059
>> + MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x17059
>> + MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x17059
>> + MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x17059
>> + >;
>> + };
>> +
>> + pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
>> + fsl,pins = <
>> + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100b9
>> + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170b9
>> + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170b9
>> + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170b9
>> + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170b9
>> + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170b9
>> + MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170b9
>> + MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170b9
>> + MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170b9
>> + MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170b9
>> + >;
>> + };
>> +
>> + pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
>> + fsl,pins = <
>> + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100f9
>> + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170f9
>> + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170f9
>> + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170f9
>> + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170f9
>> + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170f9
>> + MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170f9
>> + MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170f9
>> + MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170f9
>> + MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170f9
>> + >;
>> + };
>> +};
>> --
>> 2.11.0
>>
--
Thanks,
Parthiban N
+4915163761545
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next prev parent reply other threads:[~2020-06-01 15:16 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-04-08 18:43 [PATCH] ARM: dts: imx6ull: add MYiR MYS-6ULX SBC Parthiban Nallathambi
2020-04-08 18:43 ` Parthiban Nallathambi
2020-04-26 13:33 ` Shawn Guo
2020-04-26 13:33 ` Shawn Guo
2020-06-01 14:54 ` Parthiban
2020-06-01 14:54 ` Parthiban
2020-04-27 6:18 ` Marco Felsch
2020-04-27 6:18 ` Marco Felsch
2020-06-01 14:55 ` Parthiban [this message]
2020-06-01 14:55 ` Parthiban
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