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From: Dilip Kota <eswara.kota@linux.intel.com>
To: gustavo.pimentel@synopsys.com, lorenzo.pieralisi@arm.com,
	andrew.murray@arm.com, helgaas@kernel.org, jingoohan1@gmail.com,
	robh@kernel.org, martin.blumenstingl@googlemail.com,
	linux-pci@vger.kernel.org, devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org, andriy.shevchenko@intel.com,
	cheol.yong.kim@intel.com, chuanhua.lei@linux.intel.com,
	qi-ming.wu@intel.com, Dilip Kota <eswara.kota@linux.intel.com>
Subject: [PATCH v5 3/3] PCI: artpec6: Configure FTS with dwc helper function
Date: Wed,  6 Nov 2019 11:44:03 +0800	[thread overview]
Message-ID: <90a64d72a32dbc75c03a58a1813f50e547170ff4.1572950559.git.eswara.kota@linux.intel.com> (raw)
In-Reply-To: <cover.1572950559.git.eswara.kota@linux.intel.com>
In-Reply-To: <cover.1572950559.git.eswara.kota@linux.intel.com>

Utilize DesugnWare helper functions to configure Fast Training
Sequence. Drop the respective code in the driver.

Signed-off-by: Dilip Kota <eswara.kota@linux.intel.com>
---
 drivers/pci/controller/dwc/pcie-artpec6.c | 8 +-------
 1 file changed, 1 insertion(+), 7 deletions(-)

diff --git a/drivers/pci/controller/dwc/pcie-artpec6.c b/drivers/pci/controller/dwc/pcie-artpec6.c
index d00252bd8fae..02d93b8c7942 100644
--- a/drivers/pci/controller/dwc/pcie-artpec6.c
+++ b/drivers/pci/controller/dwc/pcie-artpec6.c
@@ -51,9 +51,6 @@ static const struct of_device_id artpec6_pcie_of_match[];
 #define ACK_N_FTS_MASK			GENMASK(15, 8)
 #define ACK_N_FTS(x)			(((x) << 8) & ACK_N_FTS_MASK)
 
-#define FAST_TRAINING_SEQ_MASK		GENMASK(7, 0)
-#define FAST_TRAINING_SEQ(x)		(((x) << 0) & FAST_TRAINING_SEQ_MASK)
-
 /* ARTPEC-6 specific registers */
 #define PCIECFG				0x18
 #define  PCIECFG_DBG_OEN		BIT(24)
@@ -313,10 +310,7 @@ static void artpec6_pcie_set_nfts(struct artpec6_pcie *artpec6_pcie)
 	 * Set the Number of Fast Training Sequences that the core
 	 * advertises as its N_FTS during Gen2 or Gen3 link training.
 	 */
-	val = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL);
-	val &= ~FAST_TRAINING_SEQ_MASK;
-	val |= FAST_TRAINING_SEQ(180);
-	dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, val);
+	dw_pcie_link_set_n_fts(pci, 180);
 }
 
 static void artpec6_pcie_assert_core_reset(struct artpec6_pcie *artpec6_pcie)
-- 
2.11.0


  parent reply	other threads:[~2019-11-06  3:44 UTC|newest]

Thread overview: 17+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-11-06  3:44 [PATCH v5 0/3] PCI: Add Intel PCIe Driver and respective dt-binding yaml file Dilip Kota
2019-11-06  3:44 ` [PATCH v5 1/3] dt-bindings: PCI: intel: Add YAML schemas for the PCIe RC controller Dilip Kota
2019-11-12 19:17   ` Rob Herring
2019-11-13  2:39     ` Dilip Kota
2019-11-06  3:44 ` [PATCH v5 2/3] dwc: PCI: intel: PCIe RC controller driver Dilip Kota
2019-11-06 12:24   ` Andy Shevchenko
2019-11-11  8:08     ` Dilip Kota
2019-11-12  7:18       ` Dilip Kota
2019-11-08 10:42   ` Andrew Murray
2019-11-11  8:09     ` Dilip Kota
2019-11-06  3:44 ` Dilip Kota [this message]
2019-11-06  9:43   ` [PATCH v5 3/3] PCI: artpec6: Configure FTS with dwc helper function Gustavo Pimentel
2019-11-11  6:24     ` Dilip Kota
2019-11-07 21:03   ` Jingoo Han
2019-11-08 10:43     ` Andrew Murray
2019-11-11  8:10       ` Dilip Kota
2019-11-11  8:09     ` Dilip Kota

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