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From: David Laight <David.Laight@ACULAB.COM>
To: 'Guo Ren' <guoren@kernel.org>, Mark Rutland <mark.rutland@arm.com>
Cc: Evgenii Shatokhin <e.shatokhin@yadro.com>,
	"suagrfillet@gmail.com" <suagrfillet@gmail.com>,
	"andy.chiu@sifive.com" <andy.chiu@sifive.com>,
	"linux-riscv@lists.infradead.org"
	<linux-riscv@lists.infradead.org>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
	Guo Ren <guoren@linux.alibaba.com>,
	"anup@brainfault.org" <anup@brainfault.org>,
	"paul.walmsley@sifive.com" <paul.walmsley@sifive.com>,
	"palmer@dabbelt.com" <palmer@dabbelt.com>,
	"conor.dooley@microchip.com" <conor.dooley@microchip.com>,
	"heiko@sntech.de" <heiko@sntech.de>,
	"rostedt@goodmis.org" <rostedt@goodmis.org>,
	"mhiramat@kernel.org" <mhiramat@kernel.org>,
	"jolsa@redhat.com" <jolsa@redhat.com>, "bp@suse.de" <bp@suse.de>,
	"jpoimboe@kernel.org" <jpoimboe@kernel.org>,
	"linux@yadro.com" <linux@yadro.com>
Subject: RE: [PATCH -next V7 0/7] riscv: Optimize function trace
Date: Thu, 9 Feb 2023 22:46:53 +0000	[thread overview]
Message-ID: <90ad3009049e4d39a952b6e4c170740b@AcuMS.aculab.com> (raw)
In-Reply-To: <CAJF2gTT_aMBx3mPnzWWqj6uGM75yT_62x+_wZ4HkWd7BqEzvug@mail.gmail.com>

From: Guo Ren
> Sent: 09 February 2023 01:31
...
> > I'm a bit confused there; I thought that the `symbol(reg)` addressing mode was
> > generating additional bits that the AUPIC didn't -- have I got that wrong?
> >
> > What specifies which register the JALR will write the link address to?
>
> According to the spec, auipc t1,0x0 should write PC + 0x0<<12 (which
> is equal to PC) to t1 and then jalr t0, (t0)0 jumps to the address
> stored in t0 + 0x0 and stores the return address to t0.
> 
> That means auipc defines xxx << 12 bits, jalr defines lowest 12 bits.

...
> What I want to point out:
> If we keep "auipc (addr+00)" fixed, we could use the different
> trampolines at "jalr (addr+0x4)" (All of them must be in one 2k
> aligned area).

I looked up auipc:
"AUIPC is used to build PC-relative addresses and uses the U-type format.
AUIPC forms a 32-bit offset from the U-immediate, filling in the lowest
12 bits with zeros, adds this offset to the address of the AUIPC instruction,
then places the result in rd."

So it generates 'pc + (val << 12)'.
And the jalr then adds in a 12bit offset.

I think that means that if you have two trampolines you might need
to change both instructions even if the two trampolines are actually
adjacent instructions.
It is the distance from the call site that mustn't cross a 2k
boundary - not the absolute address of the trampoline itself.

	David

-
Registered Address Lakeside, Bramley Road, Mount Farm, Milton Keynes, MK1 1PT, UK
Registration No: 1397386 (Wales)

WARNING: multiple messages have this Message-ID (diff)
From: David Laight <David.Laight@ACULAB.COM>
To: 'Guo Ren' <guoren@kernel.org>, Mark Rutland <mark.rutland@arm.com>
Cc: Evgenii Shatokhin <e.shatokhin@yadro.com>,
	"suagrfillet@gmail.com" <suagrfillet@gmail.com>,
	"andy.chiu@sifive.com" <andy.chiu@sifive.com>,
	"linux-riscv@lists.infradead.org"
	<linux-riscv@lists.infradead.org>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
	Guo Ren <guoren@linux.alibaba.com>,
	"anup@brainfault.org" <anup@brainfault.org>,
	"paul.walmsley@sifive.com" <paul.walmsley@sifive.com>,
	"palmer@dabbelt.com" <palmer@dabbelt.com>,
	"conor.dooley@microchip.com" <conor.dooley@microchip.com>,
	"heiko@sntech.de" <heiko@sntech.de>,
	"rostedt@goodmis.org" <rostedt@goodmis.org>,
	"mhiramat@kernel.org" <mhiramat@kernel.org>,
	"jolsa@redhat.com" <jolsa@redhat.com>, "bp@suse.de" <bp@suse.de>,
	"jpoimboe@kernel.org" <jpoimboe@kernel.org>,
	"linux@yadro.com" <linux@yadro.com>
Subject: RE: [PATCH -next V7 0/7] riscv: Optimize function trace
Date: Thu, 9 Feb 2023 22:46:53 +0000	[thread overview]
Message-ID: <90ad3009049e4d39a952b6e4c170740b@AcuMS.aculab.com> (raw)
In-Reply-To: <CAJF2gTT_aMBx3mPnzWWqj6uGM75yT_62x+_wZ4HkWd7BqEzvug@mail.gmail.com>

From: Guo Ren
> Sent: 09 February 2023 01:31
...
> > I'm a bit confused there; I thought that the `symbol(reg)` addressing mode was
> > generating additional bits that the AUPIC didn't -- have I got that wrong?
> >
> > What specifies which register the JALR will write the link address to?
>
> According to the spec, auipc t1,0x0 should write PC + 0x0<<12 (which
> is equal to PC) to t1 and then jalr t0, (t0)0 jumps to the address
> stored in t0 + 0x0 and stores the return address to t0.
> 
> That means auipc defines xxx << 12 bits, jalr defines lowest 12 bits.

...
> What I want to point out:
> If we keep "auipc (addr+00)" fixed, we could use the different
> trampolines at "jalr (addr+0x4)" (All of them must be in one 2k
> aligned area).

I looked up auipc:
"AUIPC is used to build PC-relative addresses and uses the U-type format.
AUIPC forms a 32-bit offset from the U-immediate, filling in the lowest
12 bits with zeros, adds this offset to the address of the AUIPC instruction,
then places the result in rd."

So it generates 'pc + (val << 12)'.
And the jalr then adds in a 12bit offset.

I think that means that if you have two trampolines you might need
to change both instructions even if the two trampolines are actually
adjacent instructions.
It is the distance from the call site that mustn't cross a 2k
boundary - not the absolute address of the trampoline itself.

	David

-
Registered Address Lakeside, Bramley Road, Mount Farm, Milton Keynes, MK1 1PT, UK
Registration No: 1397386 (Wales)
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

  reply	other threads:[~2023-02-09 22:47 UTC|newest]

Thread overview: 88+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-01-12  9:05 [PATCH -next V7 0/7] riscv: Optimize function trace guoren
2023-01-12  9:05 ` guoren
2023-01-12  9:05 ` [PATCH -next V7 1/7] riscv: ftrace: Fixup panic by disabling preemption guoren
2023-01-12  9:05   ` guoren
2023-01-12 12:16   ` Mark Rutland
2023-01-12 12:16     ` Mark Rutland
2023-01-12 12:57     ` Mark Rutland
2023-01-12 12:57       ` Mark Rutland
2023-01-28  9:45       ` Guo Ren
2023-01-28  9:45         ` Guo Ren
2023-01-28  9:37     ` Guo Ren
2023-01-28  9:37       ` Guo Ren
2023-01-30 10:54       ` Mark Rutland
2023-01-30 10:54         ` Mark Rutland
2023-02-04  1:19         ` Guo Ren
2023-02-04  1:19           ` Guo Ren
2023-01-12  9:05 ` [PATCH -next V7 2/7] riscv: ftrace: Remove wasted nops for !RISCV_ISA_C guoren
2023-01-12  9:05   ` guoren
2023-01-12  9:05 ` [PATCH -next V7 3/7] riscv: ftrace: Reduce the detour code size to half guoren
2023-01-12  9:05   ` guoren
2023-01-16 14:11   ` Evgenii Shatokhin
2023-01-16 14:11     ` Evgenii Shatokhin
2023-01-12  9:06 ` [PATCH -next V7 4/7] riscv: ftrace: Add ftrace_graph_func guoren
2023-01-12  9:06   ` guoren
2023-01-12  9:06 ` [PATCH -next V7 5/7] riscv: ftrace: Add DYNAMIC_FTRACE_WITH_DIRECT_CALLS support guoren
2023-01-12  9:06   ` guoren
2023-01-12  9:06 ` [PATCH -next V7 6/7] samples: ftrace: Add riscv support for SAMPLE_FTRACE_DIRECT[_MULTI] guoren
2023-01-12  9:06   ` guoren
2023-01-16 14:30   ` Evgenii Shatokhin
2023-01-16 14:30     ` Evgenii Shatokhin
2023-01-17  9:32     ` Song Shuai
2023-01-17  9:32       ` Song Shuai
2023-01-17 13:16       ` Evgenii Shatokhin
2023-01-17 13:16         ` Evgenii Shatokhin
2023-01-17 16:22         ` Evgenii Shatokhin
2023-01-17 16:22           ` Evgenii Shatokhin
2023-01-18  2:37           ` Song Shuai
2023-01-18  2:37             ` Song Shuai
2023-01-18 15:19             ` Evgenii Shatokhin
2023-01-18 15:19               ` Evgenii Shatokhin
2023-01-19  6:05               ` Guo Ren
2023-01-19  6:05                 ` Guo Ren
2023-02-18 21:30                 ` Palmer Dabbelt
2023-02-18 21:30                   ` Palmer Dabbelt
2023-02-20  2:46                   ` Song Shuai
2023-02-20  2:46                     ` Song Shuai
2023-02-21  3:56                     ` Guo Ren
2023-02-21  3:56                       ` Guo Ren
2023-02-21  4:02                   ` Guo Ren
2023-02-21  4:02                     ` Guo Ren
2023-01-12  9:06 ` [PATCH -next V7 7/7] riscv : select FTRACE_MCOUNT_USE_PATCHABLE_FUNCTION_ENTRY guoren
2023-01-12  9:06   ` guoren
2023-01-16 15:02 ` [PATCH -next V7 0/7] riscv: Optimize function trace Evgenii Shatokhin
2023-01-16 15:02   ` Evgenii Shatokhin
2023-02-04  6:40   ` Guo Ren
2023-02-04  6:40     ` Guo Ren
2023-02-06  9:56     ` Mark Rutland
2023-02-06  9:56       ` Mark Rutland
2023-02-07  3:57       ` Guo Ren
2023-02-07  3:57         ` Guo Ren
2023-02-07  9:16         ` Mark Rutland
2023-02-07  9:16           ` Mark Rutland
2023-02-08  2:30           ` Guo Ren
2023-02-08  2:30             ` Guo Ren
2023-02-08 14:46             ` Mark Rutland
2023-02-08 14:46               ` Mark Rutland
2023-02-09  1:31               ` Guo Ren
2023-02-09  1:31                 ` Guo Ren
2023-02-09 22:46                 ` David Laight [this message]
2023-02-09 22:46                   ` David Laight
2023-02-10  2:18                   ` Guo Ren
2023-02-10  2:18                     ` Guo Ren
2023-02-08 22:29             ` David Laight
2023-02-08 22:29               ` David Laight
2023-02-09  1:51               ` Guo Ren
2023-02-09  1:51                 ` Guo Ren
2023-02-09  1:59                 ` Guo Ren
2023-02-09  1:59                   ` Guo Ren
2023-02-09  9:54                   ` Mark Rutland
2023-02-09  9:54                     ` Mark Rutland
2023-02-10  2:21                     ` Guo Ren
2023-02-10  2:21                       ` Guo Ren
2023-02-09  9:00                 ` David Laight
2023-02-09  9:00                   ` David Laight
2023-02-09  9:11                   ` Guo Ren
2023-02-09  9:11                     ` Guo Ren
2023-02-18 21:42 ` patchwork-bot+linux-riscv
2023-02-18 21:42   ` patchwork-bot+linux-riscv

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