* your patch "intel_idle: add 'preferred_cstates' module argument"
@ 2022-04-25 15:47 Jan Beulich
2022-04-25 15:54 ` Artem Bityutskiy
0 siblings, 1 reply; 3+ messages in thread
From: Jan Beulich @ 2022-04-25 15:47 UTC (permalink / raw)
To: Artem Bityutskiy; +Cc: linux-pm
Artem,
while porting this change of yours to our clone of the driver in
Xen, I've gained the impression that the respective MSR write
wouldn't happen on all CPUs / cores. Was that an oversight, or am
I overlooking something?
Jan
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: your patch "intel_idle: add 'preferred_cstates' module argument"
2022-04-25 15:47 your patch "intel_idle: add 'preferred_cstates' module argument" Jan Beulich
@ 2022-04-25 15:54 ` Artem Bityutskiy
2022-04-25 16:05 ` Jan Beulich
0 siblings, 1 reply; 3+ messages in thread
From: Artem Bityutskiy @ 2022-04-25 15:54 UTC (permalink / raw)
To: Jan Beulich; +Cc: linux-pm
On Mon, 2022-04-25 at 17:47 +0200, Jan Beulich wrote:
> Artem,
>
> while porting this change of yours to our clone of the driver in
> Xen, I've gained the impression that the respective MSR write
> wouldn't happen on all CPUs / cores. Was that an oversight, or am
> I overlooking something?
Hi,
on SPR the C1E promotion bit is "global". So any CPU can change it, and the
change should be visible to all CPUs.
But I can see that this is subtle and deserves at least a comment. Let me look
into this.
Artem.
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: your patch "intel_idle: add 'preferred_cstates' module argument"
2022-04-25 15:54 ` Artem Bityutskiy
@ 2022-04-25 16:05 ` Jan Beulich
0 siblings, 0 replies; 3+ messages in thread
From: Jan Beulich @ 2022-04-25 16:05 UTC (permalink / raw)
To: Artem Bityutskiy; +Cc: linux-pm
On 25.04.2022 17:54, Artem Bityutskiy wrote:
> On Mon, 2022-04-25 at 17:47 +0200, Jan Beulich wrote:
>> Artem,
>>
>> while porting this change of yours to our clone of the driver in
>> Xen, I've gained the impression that the respective MSR write
>> wouldn't happen on all CPUs / cores. Was that an oversight, or am
>> I overlooking something?
>
> on SPR the C1E promotion bit is "global". So any CPU can change it, and the
> change should be visible to all CPUs.
But perhaps no more global than extending to an entire socket? Or even
across sockets?
> But I can see that this is subtle and deserves at least a comment. Let me look
> into this.
Indeed, with the MSR itself documented as per-core.
Jan
^ permalink raw reply [flat|nested] 3+ messages in thread
end of thread, other threads:[~2022-04-25 16:06 UTC | newest]
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2022-04-25 15:47 your patch "intel_idle: add 'preferred_cstates' module argument" Jan Beulich
2022-04-25 15:54 ` Artem Bityutskiy
2022-04-25 16:05 ` Jan Beulich
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