* [PATCH v2 0/7] Make GEN macros more similar
@ 2018-11-06 21:51 Lucas De Marchi
2018-11-06 21:51 ` [PATCH v2 1/7] Revert "drm/i915: Kill GEN_FOREVER" Lucas De Marchi
` (11 more replies)
0 siblings, 12 replies; 38+ messages in thread
From: Lucas De Marchi @ 2018-11-06 21:51 UTC (permalink / raw)
To: intel-gfx; +Cc: Rodrigo Vivi
This is the second version of the series trying to make GEN checks
more similar. These or roughly the changes from v1:
- We don't have a single macro receiving 2 or 3 parameters. Now there
is GT_GEN_RANGE(), and GT_GEN(). The firs is the conversion from
IS_GEN() while the second is the conversion from IS_GEN<N>()
- Bring GEN_FOREVER back to be used with above macros
- Patch converting <, <=, ==, >, >= checks using INTEL_GEN() to
use the macros above was added
- INTEL_GEN() is removed to avoid it being used when we should prefer
the new macros
The idea of the names is to pave the way for checks of the display version,
which would be named DISPLAY_GEN(), DISPLAY_GEN_RANGE().
In the commit messages we have the scripts to regenerate the patch to make
it easier to apply after the discussions and also to be able to convert
inflight patches.
Sorry in advance for the noise this causes in the codebase, but hopefully
it is for the greater good.
Lucas De Marchi (6):
Revert "drm/i915: Kill GEN_FOREVER"
drm/i915: replace IS_GEN<N> with GT_GEN(..., N)
drm/i915: rename IS_GEN9_* to GT_GEN9_*
drm/i915: replace gen checks using operators by GT_GEN/GT_GEN_RANGE
drm/i915: merge gen checks to use range
drm/i915: remove INTEL_GEN macro
Rodrigo Vivi (1):
drm/i915: Rename IS_GEN to GT_RANGE
drivers/gpu/drm/i915/gvt/gtt.c | 4 +-
drivers/gpu/drm/i915/gvt/handlers.c | 2 +-
drivers/gpu/drm/i915/gvt/vgpu.c | 4 +-
drivers/gpu/drm/i915/i915_cmd_parser.c | 2 +-
drivers/gpu/drm/i915/i915_debugfs.c | 145 +++++----
drivers/gpu/drm/i915/i915_drv.c | 50 +--
drivers/gpu/drm/i915/i915_drv.h | 67 ++--
drivers/gpu/drm/i915/i915_gem.c | 30 +-
drivers/gpu/drm/i915/i915_gem_context.c | 4 +-
drivers/gpu/drm/i915/i915_gem_execbuffer.c | 10 +-
drivers/gpu/drm/i915/i915_gem_fence_reg.c | 16 +-
drivers/gpu/drm/i915/i915_gem_gtt.c | 36 +-
drivers/gpu/drm/i915/i915_gem_render_state.c | 2 +-
drivers/gpu/drm/i915/i915_gem_stolen.c | 15 +-
drivers/gpu/drm/i915/i915_gem_tiling.c | 12 +-
drivers/gpu/drm/i915/i915_gpu_error.c | 62 ++--
drivers/gpu/drm/i915/i915_irq.c | 120 +++----
drivers/gpu/drm/i915/i915_perf.c | 14 +-
drivers/gpu/drm/i915/i915_pmu.c | 6 +-
drivers/gpu/drm/i915/i915_reg.h | 8 +-
drivers/gpu/drm/i915/i915_suspend.c | 24 +-
drivers/gpu/drm/i915/i915_sysfs.c | 2 +-
drivers/gpu/drm/i915/intel_atomic.c | 4 +-
drivers/gpu/drm/i915/intel_audio.c | 4 +-
drivers/gpu/drm/i915/intel_bios.c | 12 +-
drivers/gpu/drm/i915/intel_cdclk.c | 28 +-
drivers/gpu/drm/i915/intel_color.c | 6 +-
drivers/gpu/drm/i915/intel_crt.c | 12 +-
drivers/gpu/drm/i915/intel_csr.c | 2 +-
drivers/gpu/drm/i915/intel_ddi.c | 58 ++--
drivers/gpu/drm/i915/intel_device_info.c | 46 +--
drivers/gpu/drm/i915/intel_display.c | 308 +++++++++---------
drivers/gpu/drm/i915/intel_dp.c | 82 ++---
drivers/gpu/drm/i915/intel_dp_mst.c | 2 +-
drivers/gpu/drm/i915/intel_dpll_mgr.c | 10 +-
drivers/gpu/drm/i915/intel_drv.h | 2 +-
drivers/gpu/drm/i915/intel_engine_cs.c | 44 +--
drivers/gpu/drm/i915/intel_fbc.c | 52 +--
drivers/gpu/drm/i915/intel_fifo_underrun.c | 8 +-
drivers/gpu/drm/i915/intel_guc_fw.c | 4 +-
drivers/gpu/drm/i915/intel_hangcheck.c | 6 +-
drivers/gpu/drm/i915/intel_hdcp.c | 2 +-
drivers/gpu/drm/i915/intel_hdmi.c | 18 +-
drivers/gpu/drm/i915/intel_i2c.c | 14 +-
drivers/gpu/drm/i915/intel_lrc.c | 32 +-
drivers/gpu/drm/i915/intel_lvds.c | 14 +-
drivers/gpu/drm/i915/intel_mocs.c | 8 +-
drivers/gpu/drm/i915/intel_overlay.c | 12 +-
drivers/gpu/drm/i915/intel_panel.c | 20 +-
drivers/gpu/drm/i915/intel_pipe_crc.c | 12 +-
drivers/gpu/drm/i915/intel_pm.c | 196 +++++------
drivers/gpu/drm/i915/intel_psr.c | 26 +-
drivers/gpu/drm/i915/intel_ringbuffer.c | 68 ++--
drivers/gpu/drm/i915/intel_ringbuffer.h | 4 +-
drivers/gpu/drm/i915/intel_runtime_pm.c | 32 +-
drivers/gpu/drm/i915/intel_sdvo.c | 14 +-
drivers/gpu/drm/i915/intel_sprite.c | 34 +-
drivers/gpu/drm/i915/intel_tv.c | 2 +-
drivers/gpu/drm/i915/intel_uc.c | 4 +-
drivers/gpu/drm/i915/intel_uncore.c | 60 ++--
drivers/gpu/drm/i915/intel_wopcm.c | 8 +-
drivers/gpu/drm/i915/intel_workarounds.c | 20 +-
drivers/gpu/drm/i915/selftests/huge_pages.c | 2 +-
.../drm/i915/selftests/i915_gem_coherency.c | 4 +-
.../gpu/drm/i915/selftests/i915_gem_context.c | 10 +-
.../gpu/drm/i915/selftests/i915_gem_object.c | 12 +-
drivers/gpu/drm/i915/selftests/i915_request.c | 2 +-
.../gpu/drm/i915/selftests/intel_hangcheck.c | 8 +-
drivers/gpu/drm/i915/selftests/intel_lrc.c | 2 +-
drivers/gpu/drm/i915/selftests/intel_uncore.c | 2 +-
.../drm/i915/selftests/intel_workarounds.c | 2 +-
drivers/gpu/drm/i915/vlv_dsi.c | 40 +--
72 files changed, 1003 insertions(+), 1006 deletions(-)
--
2.19.1.1.g56c4683e68
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^ permalink raw reply [flat|nested] 38+ messages in thread* [PATCH v2 1/7] Revert "drm/i915: Kill GEN_FOREVER" 2018-11-06 21:51 [PATCH v2 0/7] Make GEN macros more similar Lucas De Marchi @ 2018-11-06 21:51 ` Lucas De Marchi 2018-11-21 22:22 ` Rodrigo Vivi 2018-11-06 21:51 ` [PATCH v2 2/7] drm/i915: Rename IS_GEN to GT_RANGE Lucas De Marchi ` (10 subsequent siblings) 11 siblings, 1 reply; 38+ messages in thread From: Lucas De Marchi @ 2018-11-06 21:51 UTC (permalink / raw) To: intel-gfx; +Cc: Rodrigo Vivi This reverts commit 5bc0e89ff1bee1566bd2fbd1142dce001c068aeb. The macro was added and then never used so it was removed. However after removal it was noticed that it was actually something that should indeed be useful to out gen check macros to make use of. Let's get the define back and start using it in follow up changes. Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> --- drivers/gpu/drm/i915/i915_drv.h | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 2a88a7eb871b..8839a34f7648 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -2360,12 +2360,20 @@ intel_info(const struct drm_i915_private *dev_priv) #define REVID_FOREVER 0xff #define INTEL_REVID(dev_priv) ((dev_priv)->drm.pdev->revision) +#define GEN_FOREVER (0) + #define INTEL_GEN_MASK(s, e) ( \ BUILD_BUG_ON_ZERO(!__builtin_constant_p(s)) + \ BUILD_BUG_ON_ZERO(!__builtin_constant_p(e)) + \ - GENMASK((e) - 1, (s) - 1)) + GENMASK((e) != GEN_FOREVER ? (e) - 1 : BITS_PER_LONG - 1, \ + (s) != GEN_FOREVER ? (s) - 1 : 0) \ +) -/* Returns true if Gen is in inclusive range [Start, End] */ +/* + * Returns true if Gen is in inclusive range [Start, End]. + * + * Use GEN_FOREVER for unbound start and or end. + */ #define IS_GEN(dev_priv, s, e) \ (!!((dev_priv)->info.gen_mask & INTEL_GEN_MASK((s), (e)))) -- 2.19.1.1.g56c4683e68 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 38+ messages in thread
* Re: [PATCH v2 1/7] Revert "drm/i915: Kill GEN_FOREVER" 2018-11-06 21:51 ` [PATCH v2 1/7] Revert "drm/i915: Kill GEN_FOREVER" Lucas De Marchi @ 2018-11-21 22:22 ` Rodrigo Vivi 0 siblings, 0 replies; 38+ messages in thread From: Rodrigo Vivi @ 2018-11-21 22:22 UTC (permalink / raw) To: Lucas De Marchi; +Cc: intel-gfx On Tue, Nov 06, 2018 at 01:51:17PM -0800, Lucas De Marchi wrote: > This reverts commit 5bc0e89ff1bee1566bd2fbd1142dce001c068aeb. > > The macro was added and then never used so it was removed. However > after removal it was noticed that it was actually something that should > indeed be useful to out gen check macros to make use of. > > Let's get the define back and start using it in follow up changes. > > Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> > --- > drivers/gpu/drm/i915/i915_drv.h | 12 ++++++++++-- > 1 file changed, 10 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h > index 2a88a7eb871b..8839a34f7648 100644 > --- a/drivers/gpu/drm/i915/i915_drv.h > +++ b/drivers/gpu/drm/i915/i915_drv.h > @@ -2360,12 +2360,20 @@ intel_info(const struct drm_i915_private *dev_priv) > #define REVID_FOREVER 0xff > #define INTEL_REVID(dev_priv) ((dev_priv)->drm.pdev->revision) > > +#define GEN_FOREVER (0) > + > #define INTEL_GEN_MASK(s, e) ( \ > BUILD_BUG_ON_ZERO(!__builtin_constant_p(s)) + \ > BUILD_BUG_ON_ZERO(!__builtin_constant_p(e)) + \ > - GENMASK((e) - 1, (s) - 1)) > + GENMASK((e) != GEN_FOREVER ? (e) - 1 : BITS_PER_LONG - 1, \ > + (s) != GEN_FOREVER ? (s) - 1 : 0) \ As I mentioned before I don't like the forever as start, but this could be removed later so this can be a pure revert?! Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> > +) > > -/* Returns true if Gen is in inclusive range [Start, End] */ > +/* > + * Returns true if Gen is in inclusive range [Start, End]. > + * > + * Use GEN_FOREVER for unbound start and or end. > + */ > #define IS_GEN(dev_priv, s, e) \ > (!!((dev_priv)->info.gen_mask & INTEL_GEN_MASK((s), (e)))) > > -- > 2.19.1.1.g56c4683e68 > _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 38+ messages in thread
* [PATCH v2 2/7] drm/i915: Rename IS_GEN to GT_RANGE 2018-11-06 21:51 [PATCH v2 0/7] Make GEN macros more similar Lucas De Marchi 2018-11-06 21:51 ` [PATCH v2 1/7] Revert "drm/i915: Kill GEN_FOREVER" Lucas De Marchi @ 2018-11-06 21:51 ` Lucas De Marchi 2018-11-28 8:02 ` Jani Nikula 2018-11-06 21:51 ` [PATCH v2 3/7] drm/i915: replace IS_GEN<N> with GT_GEN(..., N) Lucas De Marchi ` (9 subsequent siblings) 11 siblings, 1 reply; 38+ messages in thread From: Lucas De Marchi @ 2018-11-06 21:51 UTC (permalink / raw) To: intel-gfx; +Cc: Rodrigo Vivi From: Rodrigo Vivi <rodrigo.vivi@intel.com> RANGE makes it longer, but clear. We are also going to add a check for the display part, so make rename to GT. Diff generated with: sed 's/IS_GEN(/GT_GEN_RANGE(/g' drivers/gpu/drm/i915/*.{c,h} -i Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> --- drivers/gpu/drm/i915/i915_drv.h | 2 +- drivers/gpu/drm/i915/i915_perf.c | 4 ++-- drivers/gpu/drm/i915/intel_bios.c | 2 +- drivers/gpu/drm/i915/intel_engine_cs.c | 2 +- drivers/gpu/drm/i915/intel_fbc.c | 2 +- drivers/gpu/drm/i915/intel_hangcheck.c | 2 +- drivers/gpu/drm/i915/intel_ringbuffer.c | 8 ++++---- drivers/gpu/drm/i915/intel_uncore.c | 12 ++++++------ 8 files changed, 17 insertions(+), 17 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 8839a34f7648..e4749e93a1f9 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -2374,7 +2374,7 @@ intel_info(const struct drm_i915_private *dev_priv) * * Use GEN_FOREVER for unbound start and or end. */ -#define IS_GEN(dev_priv, s, e) \ +#define GT_GEN_RANGE(dev_priv, s, e) \ (!!((dev_priv)->info.gen_mask & INTEL_GEN_MASK((s), (e)))) /* diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c index 2c2b63be7a6c..acc3502403b3 100644 --- a/drivers/gpu/drm/i915/i915_perf.c +++ b/drivers/gpu/drm/i915/i915_perf.c @@ -1796,7 +1796,7 @@ static int gen8_enable_metric_set(struct i915_perf_stream *stream) * be read back from automatically triggered reports, as part of the * RPT_ID field. */ - if (IS_GEN(dev_priv, 9, 11)) { + if (GT_GEN_RANGE(dev_priv, 9, 11)) { I915_WRITE(GEN8_OA_DEBUG, _MASKED_BIT_ENABLE(GEN9_OA_DEBUG_DISABLE_CLK_RATIO_REPORTS | GEN9_OA_DEBUG_INCLUDE_CLK_RATIO)); @@ -3476,7 +3476,7 @@ void i915_perf_init(struct drm_i915_private *dev_priv) dev_priv->perf.oa.gen8_valid_ctx_bit = (1<<16); } - } else if (IS_GEN(dev_priv, 10, 11)) { + } else if (GT_GEN_RANGE(dev_priv, 10, 11)) { dev_priv->perf.oa.ops.is_valid_b_counter_reg = gen7_is_valid_b_counter_addr; dev_priv->perf.oa.ops.is_valid_mux_reg = diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c index 0ad2304457ab..fb918e942e9a 100644 --- a/drivers/gpu/drm/i915/intel_bios.c +++ b/drivers/gpu/drm/i915/intel_bios.c @@ -446,7 +446,7 @@ parse_sdvo_device_mapping(struct drm_i915_private *dev_priv, u8 bdb_version) * Only parse SDVO mappings on gens that could have SDVO. This isn't * accurate and doesn't have to be, as long as it's not too strict. */ - if (!IS_GEN(dev_priv, 3, 7)) { + if (!GT_GEN_RANGE(dev_priv, 3, 7)) { DRM_DEBUG_KMS("Skipping SDVO device mapping\n"); return; } diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c index bc147d9e6c92..4f7b654614e9 100644 --- a/drivers/gpu/drm/i915/intel_engine_cs.c +++ b/drivers/gpu/drm/i915/intel_engine_cs.c @@ -1286,7 +1286,7 @@ static void intel_engine_print_registers(const struct intel_engine_cs *engine, &engine->execlists; u64 addr; - if (engine->id == RCS && IS_GEN(dev_priv, 4, 7)) + if (engine->id == RCS && GT_GEN_RANGE(dev_priv, 4, 7)) drm_printf(m, "\tCCID: 0x%08x\n", I915_READ(CCID)); drm_printf(m, "\tRING_START: 0x%08x\n", I915_READ(RING_START(engine->mmio_base))); diff --git a/drivers/gpu/drm/i915/intel_fbc.c b/drivers/gpu/drm/i915/intel_fbc.c index 14cbaf4a0e93..9f41779988e5 100644 --- a/drivers/gpu/drm/i915/intel_fbc.c +++ b/drivers/gpu/drm/i915/intel_fbc.c @@ -784,7 +784,7 @@ static bool intel_fbc_can_activate(struct intel_crtc *crtc) * having a Y offset that isn't divisible by 4 causes FIFO underrun * and screen flicker. */ - if (IS_GEN(dev_priv, 9, 10) && + if (GT_GEN_RANGE(dev_priv, 9, 10) && (fbc->state_cache.plane.adjusted_y & 3)) { fbc->no_fbc_reason = "plane Y offset is misaligned"; return false; diff --git a/drivers/gpu/drm/i915/intel_hangcheck.c b/drivers/gpu/drm/i915/intel_hangcheck.c index e26d05a46451..9b15ed1409ae 100644 --- a/drivers/gpu/drm/i915/intel_hangcheck.c +++ b/drivers/gpu/drm/i915/intel_hangcheck.c @@ -252,7 +252,7 @@ engine_stuck(struct intel_engine_cs *engine, u64 acthd) return ENGINE_WAIT_KICK; } - if (IS_GEN(dev_priv, 6, 7) && tmp & RING_WAIT_SEMAPHORE) { + if (GT_GEN_RANGE(dev_priv, 6, 7) && tmp & RING_WAIT_SEMAPHORE) { switch (semaphore_passed(engine)) { default: return ENGINE_DEAD; diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index b8a7a014d46d..0e5f49c45298 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c @@ -407,7 +407,7 @@ static void intel_ring_setup_status_page(struct intel_engine_cs *engine) POSTING_READ(mmio); /* Flush the TLB for this page */ - if (IS_GEN(dev_priv, 6, 7)) { + if (GT_GEN_RANGE(dev_priv, 6, 7)) { i915_reg_t reg = RING_INSTPM(engine->mmio_base); /* ring should be idle before issuing a sync flush*/ @@ -629,7 +629,7 @@ static int init_render_ring(struct intel_engine_cs *engine) intel_whitelist_workarounds_apply(engine); /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */ - if (IS_GEN(dev_priv, 4, 6)) + if (GT_GEN_RANGE(dev_priv, 4, 6)) I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH)); /* We need to disable the AsyncFlip performance optimisations in order @@ -638,7 +638,7 @@ static int init_render_ring(struct intel_engine_cs *engine) * * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv */ - if (IS_GEN(dev_priv, 6, 7)) + if (GT_GEN_RANGE(dev_priv, 6, 7)) I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE)); /* Required for the hardware to program scanline values for waiting */ @@ -663,7 +663,7 @@ static int init_render_ring(struct intel_engine_cs *engine) _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB)); } - if (IS_GEN(dev_priv, 6, 7)) + if (GT_GEN_RANGE(dev_priv, 6, 7)) I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING)); if (INTEL_GEN(dev_priv) >= 6) diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c index 9289515108c3..4ffe26cc3c3f 100644 --- a/drivers/gpu/drm/i915/intel_uncore.c +++ b/drivers/gpu/drm/i915/intel_uncore.c @@ -1567,13 +1567,13 @@ void intel_uncore_init(struct drm_i915_private *dev_priv) dev_priv->uncore.pmic_bus_access_nb.notifier_call = i915_pmic_bus_access_notifier; - if (IS_GEN(dev_priv, 2, 4) || intel_vgpu_active(dev_priv)) { + if (GT_GEN_RANGE(dev_priv, 2, 4) || intel_vgpu_active(dev_priv)) { ASSIGN_WRITE_MMIO_VFUNCS(dev_priv, gen2); ASSIGN_READ_MMIO_VFUNCS(dev_priv, gen2); } else if (IS_GEN5(dev_priv)) { ASSIGN_WRITE_MMIO_VFUNCS(dev_priv, gen5); ASSIGN_READ_MMIO_VFUNCS(dev_priv, gen5); - } else if (IS_GEN(dev_priv, 6, 7)) { + } else if (GT_GEN_RANGE(dev_priv, 6, 7)) { ASSIGN_WRITE_MMIO_VFUNCS(dev_priv, gen6); if (IS_VALLEYVIEW(dev_priv)) { @@ -1592,7 +1592,7 @@ void intel_uncore_init(struct drm_i915_private *dev_priv) ASSIGN_WRITE_MMIO_VFUNCS(dev_priv, gen8); ASSIGN_READ_MMIO_VFUNCS(dev_priv, gen6); } - } else if (IS_GEN(dev_priv, 9, 10)) { + } else if (GT_GEN_RANGE(dev_priv, 9, 10)) { ASSIGN_FW_DOMAINS_TABLE(__gen9_fw_ranges); ASSIGN_WRITE_MMIO_VFUNCS(dev_priv, fwtable); ASSIGN_READ_MMIO_VFUNCS(dev_priv, fwtable); @@ -2321,7 +2321,7 @@ intel_uncore_forcewake_for_read(struct drm_i915_private *dev_priv, } else if (INTEL_GEN(dev_priv) >= 6) { fw_domains = __gen6_reg_read_fw_domains(offset); } else { - WARN_ON(!IS_GEN(dev_priv, 2, 5)); + WARN_ON(!GT_GEN_RANGE(dev_priv, 2, 5)); fw_domains = 0; } @@ -2343,10 +2343,10 @@ intel_uncore_forcewake_for_write(struct drm_i915_private *dev_priv, fw_domains = __fwtable_reg_write_fw_domains(offset); } else if (IS_GEN8(dev_priv)) { fw_domains = __gen8_reg_write_fw_domains(offset); - } else if (IS_GEN(dev_priv, 6, 7)) { + } else if (GT_GEN_RANGE(dev_priv, 6, 7)) { fw_domains = FORCEWAKE_RENDER; } else { - WARN_ON(!IS_GEN(dev_priv, 2, 5)); + WARN_ON(!GT_GEN_RANGE(dev_priv, 2, 5)); fw_domains = 0; } -- 2.19.1.1.g56c4683e68 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 38+ messages in thread
* Re: [PATCH v2 2/7] drm/i915: Rename IS_GEN to GT_RANGE 2018-11-06 21:51 ` [PATCH v2 2/7] drm/i915: Rename IS_GEN to GT_RANGE Lucas De Marchi @ 2018-11-28 8:02 ` Jani Nikula 2018-11-28 9:27 ` Joonas Lahtinen ` (2 more replies) 0 siblings, 3 replies; 38+ messages in thread From: Jani Nikula @ 2018-11-28 8:02 UTC (permalink / raw) To: Lucas De Marchi, intel-gfx; +Cc: Rodrigo Vivi On Tue, 06 Nov 2018, Lucas De Marchi <lucas.demarchi@intel.com> wrote: > From: Rodrigo Vivi <rodrigo.vivi@intel.com> > > RANGE makes it longer, but clear. We are also going to add a check for > the display part, so make rename to GT. I also still have my doubts about this patch I'm afraid. I've expressed the concern before, but here goes again. How much is the split of gen to GT gen and display gen going to help us in the long run? The only current platform that would benefit from this is GLK. However, not all IS_GEMINILAKE() can be replaced with IS_DISPLAY_GEN() >= 10 or similar. We also have VLV/CHV display that is better represented by HAS_GMCH_DISPLAY() and AFAICT can't usefully be replaced by a display gen check. My main fear is that the split adds a lot of confusion. (Where should I use GT gen, where should I use display gen, patches to change between one and the other. It's not 100% clear cut.) Here too I wonder if we're better off adding more has_feature flags that describe what gt or display features a platform has. BR, Jani. > > Diff generated with: > > sed 's/IS_GEN(/GT_GEN_RANGE(/g' drivers/gpu/drm/i915/*.{c,h} -i > > Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> > Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> > Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> > --- > drivers/gpu/drm/i915/i915_drv.h | 2 +- > drivers/gpu/drm/i915/i915_perf.c | 4 ++-- > drivers/gpu/drm/i915/intel_bios.c | 2 +- > drivers/gpu/drm/i915/intel_engine_cs.c | 2 +- > drivers/gpu/drm/i915/intel_fbc.c | 2 +- > drivers/gpu/drm/i915/intel_hangcheck.c | 2 +- > drivers/gpu/drm/i915/intel_ringbuffer.c | 8 ++++---- > drivers/gpu/drm/i915/intel_uncore.c | 12 ++++++------ > 8 files changed, 17 insertions(+), 17 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h > index 8839a34f7648..e4749e93a1f9 100644 > --- a/drivers/gpu/drm/i915/i915_drv.h > +++ b/drivers/gpu/drm/i915/i915_drv.h > @@ -2374,7 +2374,7 @@ intel_info(const struct drm_i915_private *dev_priv) > * > * Use GEN_FOREVER for unbound start and or end. > */ > -#define IS_GEN(dev_priv, s, e) \ > +#define GT_GEN_RANGE(dev_priv, s, e) \ > (!!((dev_priv)->info.gen_mask & INTEL_GEN_MASK((s), (e)))) > > /* > diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c > index 2c2b63be7a6c..acc3502403b3 100644 > --- a/drivers/gpu/drm/i915/i915_perf.c > +++ b/drivers/gpu/drm/i915/i915_perf.c > @@ -1796,7 +1796,7 @@ static int gen8_enable_metric_set(struct i915_perf_stream *stream) > * be read back from automatically triggered reports, as part of the > * RPT_ID field. > */ > - if (IS_GEN(dev_priv, 9, 11)) { > + if (GT_GEN_RANGE(dev_priv, 9, 11)) { > I915_WRITE(GEN8_OA_DEBUG, > _MASKED_BIT_ENABLE(GEN9_OA_DEBUG_DISABLE_CLK_RATIO_REPORTS | > GEN9_OA_DEBUG_INCLUDE_CLK_RATIO)); > @@ -3476,7 +3476,7 @@ void i915_perf_init(struct drm_i915_private *dev_priv) > > dev_priv->perf.oa.gen8_valid_ctx_bit = (1<<16); > } > - } else if (IS_GEN(dev_priv, 10, 11)) { > + } else if (GT_GEN_RANGE(dev_priv, 10, 11)) { > dev_priv->perf.oa.ops.is_valid_b_counter_reg = > gen7_is_valid_b_counter_addr; > dev_priv->perf.oa.ops.is_valid_mux_reg = > diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c > index 0ad2304457ab..fb918e942e9a 100644 > --- a/drivers/gpu/drm/i915/intel_bios.c > +++ b/drivers/gpu/drm/i915/intel_bios.c > @@ -446,7 +446,7 @@ parse_sdvo_device_mapping(struct drm_i915_private *dev_priv, u8 bdb_version) > * Only parse SDVO mappings on gens that could have SDVO. This isn't > * accurate and doesn't have to be, as long as it's not too strict. > */ > - if (!IS_GEN(dev_priv, 3, 7)) { > + if (!GT_GEN_RANGE(dev_priv, 3, 7)) { > DRM_DEBUG_KMS("Skipping SDVO device mapping\n"); > return; > } > diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c > index bc147d9e6c92..4f7b654614e9 100644 > --- a/drivers/gpu/drm/i915/intel_engine_cs.c > +++ b/drivers/gpu/drm/i915/intel_engine_cs.c > @@ -1286,7 +1286,7 @@ static void intel_engine_print_registers(const struct intel_engine_cs *engine, > &engine->execlists; > u64 addr; > > - if (engine->id == RCS && IS_GEN(dev_priv, 4, 7)) > + if (engine->id == RCS && GT_GEN_RANGE(dev_priv, 4, 7)) > drm_printf(m, "\tCCID: 0x%08x\n", I915_READ(CCID)); > drm_printf(m, "\tRING_START: 0x%08x\n", > I915_READ(RING_START(engine->mmio_base))); > diff --git a/drivers/gpu/drm/i915/intel_fbc.c b/drivers/gpu/drm/i915/intel_fbc.c > index 14cbaf4a0e93..9f41779988e5 100644 > --- a/drivers/gpu/drm/i915/intel_fbc.c > +++ b/drivers/gpu/drm/i915/intel_fbc.c > @@ -784,7 +784,7 @@ static bool intel_fbc_can_activate(struct intel_crtc *crtc) > * having a Y offset that isn't divisible by 4 causes FIFO underrun > * and screen flicker. > */ > - if (IS_GEN(dev_priv, 9, 10) && > + if (GT_GEN_RANGE(dev_priv, 9, 10) && > (fbc->state_cache.plane.adjusted_y & 3)) { > fbc->no_fbc_reason = "plane Y offset is misaligned"; > return false; > diff --git a/drivers/gpu/drm/i915/intel_hangcheck.c b/drivers/gpu/drm/i915/intel_hangcheck.c > index e26d05a46451..9b15ed1409ae 100644 > --- a/drivers/gpu/drm/i915/intel_hangcheck.c > +++ b/drivers/gpu/drm/i915/intel_hangcheck.c > @@ -252,7 +252,7 @@ engine_stuck(struct intel_engine_cs *engine, u64 acthd) > return ENGINE_WAIT_KICK; > } > > - if (IS_GEN(dev_priv, 6, 7) && tmp & RING_WAIT_SEMAPHORE) { > + if (GT_GEN_RANGE(dev_priv, 6, 7) && tmp & RING_WAIT_SEMAPHORE) { > switch (semaphore_passed(engine)) { > default: > return ENGINE_DEAD; > diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c > index b8a7a014d46d..0e5f49c45298 100644 > --- a/drivers/gpu/drm/i915/intel_ringbuffer.c > +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c > @@ -407,7 +407,7 @@ static void intel_ring_setup_status_page(struct intel_engine_cs *engine) > POSTING_READ(mmio); > > /* Flush the TLB for this page */ > - if (IS_GEN(dev_priv, 6, 7)) { > + if (GT_GEN_RANGE(dev_priv, 6, 7)) { > i915_reg_t reg = RING_INSTPM(engine->mmio_base); > > /* ring should be idle before issuing a sync flush*/ > @@ -629,7 +629,7 @@ static int init_render_ring(struct intel_engine_cs *engine) > intel_whitelist_workarounds_apply(engine); > > /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */ > - if (IS_GEN(dev_priv, 4, 6)) > + if (GT_GEN_RANGE(dev_priv, 4, 6)) > I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH)); > > /* We need to disable the AsyncFlip performance optimisations in order > @@ -638,7 +638,7 @@ static int init_render_ring(struct intel_engine_cs *engine) > * > * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv > */ > - if (IS_GEN(dev_priv, 6, 7)) > + if (GT_GEN_RANGE(dev_priv, 6, 7)) > I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE)); > > /* Required for the hardware to program scanline values for waiting */ > @@ -663,7 +663,7 @@ static int init_render_ring(struct intel_engine_cs *engine) > _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB)); > } > > - if (IS_GEN(dev_priv, 6, 7)) > + if (GT_GEN_RANGE(dev_priv, 6, 7)) > I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING)); > > if (INTEL_GEN(dev_priv) >= 6) > diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c > index 9289515108c3..4ffe26cc3c3f 100644 > --- a/drivers/gpu/drm/i915/intel_uncore.c > +++ b/drivers/gpu/drm/i915/intel_uncore.c > @@ -1567,13 +1567,13 @@ void intel_uncore_init(struct drm_i915_private *dev_priv) > dev_priv->uncore.pmic_bus_access_nb.notifier_call = > i915_pmic_bus_access_notifier; > > - if (IS_GEN(dev_priv, 2, 4) || intel_vgpu_active(dev_priv)) { > + if (GT_GEN_RANGE(dev_priv, 2, 4) || intel_vgpu_active(dev_priv)) { > ASSIGN_WRITE_MMIO_VFUNCS(dev_priv, gen2); > ASSIGN_READ_MMIO_VFUNCS(dev_priv, gen2); > } else if (IS_GEN5(dev_priv)) { > ASSIGN_WRITE_MMIO_VFUNCS(dev_priv, gen5); > ASSIGN_READ_MMIO_VFUNCS(dev_priv, gen5); > - } else if (IS_GEN(dev_priv, 6, 7)) { > + } else if (GT_GEN_RANGE(dev_priv, 6, 7)) { > ASSIGN_WRITE_MMIO_VFUNCS(dev_priv, gen6); > > if (IS_VALLEYVIEW(dev_priv)) { > @@ -1592,7 +1592,7 @@ void intel_uncore_init(struct drm_i915_private *dev_priv) > ASSIGN_WRITE_MMIO_VFUNCS(dev_priv, gen8); > ASSIGN_READ_MMIO_VFUNCS(dev_priv, gen6); > } > - } else if (IS_GEN(dev_priv, 9, 10)) { > + } else if (GT_GEN_RANGE(dev_priv, 9, 10)) { > ASSIGN_FW_DOMAINS_TABLE(__gen9_fw_ranges); > ASSIGN_WRITE_MMIO_VFUNCS(dev_priv, fwtable); > ASSIGN_READ_MMIO_VFUNCS(dev_priv, fwtable); > @@ -2321,7 +2321,7 @@ intel_uncore_forcewake_for_read(struct drm_i915_private *dev_priv, > } else if (INTEL_GEN(dev_priv) >= 6) { > fw_domains = __gen6_reg_read_fw_domains(offset); > } else { > - WARN_ON(!IS_GEN(dev_priv, 2, 5)); > + WARN_ON(!GT_GEN_RANGE(dev_priv, 2, 5)); > fw_domains = 0; > } > > @@ -2343,10 +2343,10 @@ intel_uncore_forcewake_for_write(struct drm_i915_private *dev_priv, > fw_domains = __fwtable_reg_write_fw_domains(offset); > } else if (IS_GEN8(dev_priv)) { > fw_domains = __gen8_reg_write_fw_domains(offset); > - } else if (IS_GEN(dev_priv, 6, 7)) { > + } else if (GT_GEN_RANGE(dev_priv, 6, 7)) { > fw_domains = FORCEWAKE_RENDER; > } else { > - WARN_ON(!IS_GEN(dev_priv, 2, 5)); > + WARN_ON(!GT_GEN_RANGE(dev_priv, 2, 5)); > fw_domains = 0; > } -- Jani Nikula, Intel Open Source Graphics Center _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [PATCH v2 2/7] drm/i915: Rename IS_GEN to GT_RANGE 2018-11-28 8:02 ` Jani Nikula @ 2018-11-28 9:27 ` Joonas Lahtinen 2018-11-28 17:04 ` Rodrigo Vivi 2018-11-28 17:34 ` Lucas De Marchi 2 siblings, 0 replies; 38+ messages in thread From: Joonas Lahtinen @ 2018-11-28 9:27 UTC (permalink / raw) To: Jani Nikula, Lucas De Marchi, intel-gfx; +Cc: Rodrigo Vivi Quoting Jani Nikula (2018-11-28 10:02:22) > On Tue, 06 Nov 2018, Lucas De Marchi <lucas.demarchi@intel.com> wrote: > > From: Rodrigo Vivi <rodrigo.vivi@intel.com> > > > > RANGE makes it longer, but clear. We are also going to add a check for > > the display part, so make rename to GT. > > I also still have my doubts about this patch I'm afraid. I've expressed > the concern before, but here goes again. > > How much is the split of gen to GT gen and display gen going to help us > in the long run? The only current platform that would benefit from this > is GLK. However, not all IS_GEMINILAKE() can be replaced with > IS_DISPLAY_GEN() >= 10 or similar. We also have VLV/CHV display that is > better represented by HAS_GMCH_DISPLAY() and AFAICT can't usefully be > replaced by a display gen check. > > My main fear is that the split adds a lot of confusion. (Where should I > use GT gen, where should I use display gen, patches to change between > one and the other. It's not 100% clear cut.) > > Here too I wonder if we're better off adding more has_feature flags that > describe what gt or display features a platform has. Count my vote on the has_feature flags. Regards, Joonas > > BR, > Jani. > > > > > > Diff generated with: > > > > sed 's/IS_GEN(/GT_GEN_RANGE(/g' drivers/gpu/drm/i915/*.{c,h} -i > > > > Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> > > Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> > > Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> > > --- > > drivers/gpu/drm/i915/i915_drv.h | 2 +- > > drivers/gpu/drm/i915/i915_perf.c | 4 ++-- > > drivers/gpu/drm/i915/intel_bios.c | 2 +- > > drivers/gpu/drm/i915/intel_engine_cs.c | 2 +- > > drivers/gpu/drm/i915/intel_fbc.c | 2 +- > > drivers/gpu/drm/i915/intel_hangcheck.c | 2 +- > > drivers/gpu/drm/i915/intel_ringbuffer.c | 8 ++++---- > > drivers/gpu/drm/i915/intel_uncore.c | 12 ++++++------ > > 8 files changed, 17 insertions(+), 17 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h > > index 8839a34f7648..e4749e93a1f9 100644 > > --- a/drivers/gpu/drm/i915/i915_drv.h > > +++ b/drivers/gpu/drm/i915/i915_drv.h > > @@ -2374,7 +2374,7 @@ intel_info(const struct drm_i915_private *dev_priv) > > * > > * Use GEN_FOREVER for unbound start and or end. > > */ > > -#define IS_GEN(dev_priv, s, e) \ > > +#define GT_GEN_RANGE(dev_priv, s, e) \ > > (!!((dev_priv)->info.gen_mask & INTEL_GEN_MASK((s), (e)))) > > > > /* > > diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c > > index 2c2b63be7a6c..acc3502403b3 100644 > > --- a/drivers/gpu/drm/i915/i915_perf.c > > +++ b/drivers/gpu/drm/i915/i915_perf.c > > @@ -1796,7 +1796,7 @@ static int gen8_enable_metric_set(struct i915_perf_stream *stream) > > * be read back from automatically triggered reports, as part of the > > * RPT_ID field. > > */ > > - if (IS_GEN(dev_priv, 9, 11)) { > > + if (GT_GEN_RANGE(dev_priv, 9, 11)) { > > I915_WRITE(GEN8_OA_DEBUG, > > _MASKED_BIT_ENABLE(GEN9_OA_DEBUG_DISABLE_CLK_RATIO_REPORTS | > > GEN9_OA_DEBUG_INCLUDE_CLK_RATIO)); > > @@ -3476,7 +3476,7 @@ void i915_perf_init(struct drm_i915_private *dev_priv) > > > > dev_priv->perf.oa.gen8_valid_ctx_bit = (1<<16); > > } > > - } else if (IS_GEN(dev_priv, 10, 11)) { > > + } else if (GT_GEN_RANGE(dev_priv, 10, 11)) { > > dev_priv->perf.oa.ops.is_valid_b_counter_reg = > > gen7_is_valid_b_counter_addr; > > dev_priv->perf.oa.ops.is_valid_mux_reg = > > diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c > > index 0ad2304457ab..fb918e942e9a 100644 > > --- a/drivers/gpu/drm/i915/intel_bios.c > > +++ b/drivers/gpu/drm/i915/intel_bios.c > > @@ -446,7 +446,7 @@ parse_sdvo_device_mapping(struct drm_i915_private *dev_priv, u8 bdb_version) > > * Only parse SDVO mappings on gens that could have SDVO. This isn't > > * accurate and doesn't have to be, as long as it's not too strict. > > */ > > - if (!IS_GEN(dev_priv, 3, 7)) { > > + if (!GT_GEN_RANGE(dev_priv, 3, 7)) { > > DRM_DEBUG_KMS("Skipping SDVO device mapping\n"); > > return; > > } > > diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c > > index bc147d9e6c92..4f7b654614e9 100644 > > --- a/drivers/gpu/drm/i915/intel_engine_cs.c > > +++ b/drivers/gpu/drm/i915/intel_engine_cs.c > > @@ -1286,7 +1286,7 @@ static void intel_engine_print_registers(const struct intel_engine_cs *engine, > > &engine->execlists; > > u64 addr; > > > > - if (engine->id == RCS && IS_GEN(dev_priv, 4, 7)) > > + if (engine->id == RCS && GT_GEN_RANGE(dev_priv, 4, 7)) > > drm_printf(m, "\tCCID: 0x%08x\n", I915_READ(CCID)); > > drm_printf(m, "\tRING_START: 0x%08x\n", > > I915_READ(RING_START(engine->mmio_base))); > > diff --git a/drivers/gpu/drm/i915/intel_fbc.c b/drivers/gpu/drm/i915/intel_fbc.c > > index 14cbaf4a0e93..9f41779988e5 100644 > > --- a/drivers/gpu/drm/i915/intel_fbc.c > > +++ b/drivers/gpu/drm/i915/intel_fbc.c > > @@ -784,7 +784,7 @@ static bool intel_fbc_can_activate(struct intel_crtc *crtc) > > * having a Y offset that isn't divisible by 4 causes FIFO underrun > > * and screen flicker. > > */ > > - if (IS_GEN(dev_priv, 9, 10) && > > + if (GT_GEN_RANGE(dev_priv, 9, 10) && > > (fbc->state_cache.plane.adjusted_y & 3)) { > > fbc->no_fbc_reason = "plane Y offset is misaligned"; > > return false; > > diff --git a/drivers/gpu/drm/i915/intel_hangcheck.c b/drivers/gpu/drm/i915/intel_hangcheck.c > > index e26d05a46451..9b15ed1409ae 100644 > > --- a/drivers/gpu/drm/i915/intel_hangcheck.c > > +++ b/drivers/gpu/drm/i915/intel_hangcheck.c > > @@ -252,7 +252,7 @@ engine_stuck(struct intel_engine_cs *engine, u64 acthd) > > return ENGINE_WAIT_KICK; > > } > > > > - if (IS_GEN(dev_priv, 6, 7) && tmp & RING_WAIT_SEMAPHORE) { > > + if (GT_GEN_RANGE(dev_priv, 6, 7) && tmp & RING_WAIT_SEMAPHORE) { > > switch (semaphore_passed(engine)) { > > default: > > return ENGINE_DEAD; > > diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c > > index b8a7a014d46d..0e5f49c45298 100644 > > --- a/drivers/gpu/drm/i915/intel_ringbuffer.c > > +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c > > @@ -407,7 +407,7 @@ static void intel_ring_setup_status_page(struct intel_engine_cs *engine) > > POSTING_READ(mmio); > > > > /* Flush the TLB for this page */ > > - if (IS_GEN(dev_priv, 6, 7)) { > > + if (GT_GEN_RANGE(dev_priv, 6, 7)) { > > i915_reg_t reg = RING_INSTPM(engine->mmio_base); > > > > /* ring should be idle before issuing a sync flush*/ > > @@ -629,7 +629,7 @@ static int init_render_ring(struct intel_engine_cs *engine) > > intel_whitelist_workarounds_apply(engine); > > > > /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */ > > - if (IS_GEN(dev_priv, 4, 6)) > > + if (GT_GEN_RANGE(dev_priv, 4, 6)) > > I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH)); > > > > /* We need to disable the AsyncFlip performance optimisations in order > > @@ -638,7 +638,7 @@ static int init_render_ring(struct intel_engine_cs *engine) > > * > > * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv > > */ > > - if (IS_GEN(dev_priv, 6, 7)) > > + if (GT_GEN_RANGE(dev_priv, 6, 7)) > > I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE)); > > > > /* Required for the hardware to program scanline values for waiting */ > > @@ -663,7 +663,7 @@ static int init_render_ring(struct intel_engine_cs *engine) > > _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB)); > > } > > > > - if (IS_GEN(dev_priv, 6, 7)) > > + if (GT_GEN_RANGE(dev_priv, 6, 7)) > > I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING)); > > > > if (INTEL_GEN(dev_priv) >= 6) > > diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c > > index 9289515108c3..4ffe26cc3c3f 100644 > > --- a/drivers/gpu/drm/i915/intel_uncore.c > > +++ b/drivers/gpu/drm/i915/intel_uncore.c > > @@ -1567,13 +1567,13 @@ void intel_uncore_init(struct drm_i915_private *dev_priv) > > dev_priv->uncore.pmic_bus_access_nb.notifier_call = > > i915_pmic_bus_access_notifier; > > > > - if (IS_GEN(dev_priv, 2, 4) || intel_vgpu_active(dev_priv)) { > > + if (GT_GEN_RANGE(dev_priv, 2, 4) || intel_vgpu_active(dev_priv)) { > > ASSIGN_WRITE_MMIO_VFUNCS(dev_priv, gen2); > > ASSIGN_READ_MMIO_VFUNCS(dev_priv, gen2); > > } else if (IS_GEN5(dev_priv)) { > > ASSIGN_WRITE_MMIO_VFUNCS(dev_priv, gen5); > > ASSIGN_READ_MMIO_VFUNCS(dev_priv, gen5); > > - } else if (IS_GEN(dev_priv, 6, 7)) { > > + } else if (GT_GEN_RANGE(dev_priv, 6, 7)) { > > ASSIGN_WRITE_MMIO_VFUNCS(dev_priv, gen6); > > > > if (IS_VALLEYVIEW(dev_priv)) { > > @@ -1592,7 +1592,7 @@ void intel_uncore_init(struct drm_i915_private *dev_priv) > > ASSIGN_WRITE_MMIO_VFUNCS(dev_priv, gen8); > > ASSIGN_READ_MMIO_VFUNCS(dev_priv, gen6); > > } > > - } else if (IS_GEN(dev_priv, 9, 10)) { > > + } else if (GT_GEN_RANGE(dev_priv, 9, 10)) { > > ASSIGN_FW_DOMAINS_TABLE(__gen9_fw_ranges); > > ASSIGN_WRITE_MMIO_VFUNCS(dev_priv, fwtable); > > ASSIGN_READ_MMIO_VFUNCS(dev_priv, fwtable); > > @@ -2321,7 +2321,7 @@ intel_uncore_forcewake_for_read(struct drm_i915_private *dev_priv, > > } else if (INTEL_GEN(dev_priv) >= 6) { > > fw_domains = __gen6_reg_read_fw_domains(offset); > > } else { > > - WARN_ON(!IS_GEN(dev_priv, 2, 5)); > > + WARN_ON(!GT_GEN_RANGE(dev_priv, 2, 5)); > > fw_domains = 0; > > } > > > > @@ -2343,10 +2343,10 @@ intel_uncore_forcewake_for_write(struct drm_i915_private *dev_priv, > > fw_domains = __fwtable_reg_write_fw_domains(offset); > > } else if (IS_GEN8(dev_priv)) { > > fw_domains = __gen8_reg_write_fw_domains(offset); > > - } else if (IS_GEN(dev_priv, 6, 7)) { > > + } else if (GT_GEN_RANGE(dev_priv, 6, 7)) { > > fw_domains = FORCEWAKE_RENDER; > > } else { > > - WARN_ON(!IS_GEN(dev_priv, 2, 5)); > > + WARN_ON(!GT_GEN_RANGE(dev_priv, 2, 5)); > > fw_domains = 0; > > } > > -- > Jani Nikula, Intel Open Source Graphics Center > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [PATCH v2 2/7] drm/i915: Rename IS_GEN to GT_RANGE 2018-11-28 8:02 ` Jani Nikula 2018-11-28 9:27 ` Joonas Lahtinen @ 2018-11-28 17:04 ` Rodrigo Vivi 2018-11-28 17:34 ` Lucas De Marchi 2 siblings, 0 replies; 38+ messages in thread From: Rodrigo Vivi @ 2018-11-28 17:04 UTC (permalink / raw) To: Jani Nikula; +Cc: intel-gfx, Lucas De Marchi On Wed, Nov 28, 2018 at 10:02:22AM +0200, Jani Nikula wrote: > On Tue, 06 Nov 2018, Lucas De Marchi <lucas.demarchi@intel.com> wrote: > > From: Rodrigo Vivi <rodrigo.vivi@intel.com> > > > > RANGE makes it longer, but clear. We are also going to add a check for > > the display part, so make rename to GT. > > I also still have my doubts about this patch I'm afraid. I've expressed > the concern before, but here goes again. > > How much is the split of gen to GT gen and display gen going to help us > in the long run? The only current platform that would benefit from this > is GLK. However, not all IS_GEMINILAKE() can be replaced with > IS_DISPLAY_GEN() >= 10 or similar. We also have VLV/CHV display that is > better represented by HAS_GMCH_DISPLAY() and AFAICT can't usefully be > replaced by a display gen check. Fair enough. I believe I have to prove that out with the other series that I'm planning to put on top. For this one for now maybe we should just rename IS_GEN() to GEN_RANGE() And latter on the series introducing the display_gen we could convert that to GT_GEN_RANGE DISPLAY_GEN_RANGE if that is acceptable. > > My main fear is that the split adds a lot of confusion. (Where should I > use GT gen, where should I use display gen, patches to change between > one and the other. It's not 100% clear cut.) Yes, this is a very good point. Specially around some gray areas like PM. So let's hold this discussion for the next series and first organize the current gen_range vs is_gen/intel_gen <= etc... > > Here too I wonder if we're better off adding more has_feature flags that > describe what gt or display features a platform has. This is another thing we should discuss separated of this thread. I believe that our platform definition and addition as a room for improve somehow... I just don't have good ideas :/ and I also believe this is discussion for another series and should not block the progress of this one. > > BR, > Jani. > > > > > > Diff generated with: > > > > sed 's/IS_GEN(/GT_GEN_RANGE(/g' drivers/gpu/drm/i915/*.{c,h} -i > > > > Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> > > Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> > > Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> > > --- > > drivers/gpu/drm/i915/i915_drv.h | 2 +- > > drivers/gpu/drm/i915/i915_perf.c | 4 ++-- > > drivers/gpu/drm/i915/intel_bios.c | 2 +- > > drivers/gpu/drm/i915/intel_engine_cs.c | 2 +- > > drivers/gpu/drm/i915/intel_fbc.c | 2 +- > > drivers/gpu/drm/i915/intel_hangcheck.c | 2 +- > > drivers/gpu/drm/i915/intel_ringbuffer.c | 8 ++++---- > > drivers/gpu/drm/i915/intel_uncore.c | 12 ++++++------ > > 8 files changed, 17 insertions(+), 17 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h > > index 8839a34f7648..e4749e93a1f9 100644 > > --- a/drivers/gpu/drm/i915/i915_drv.h > > +++ b/drivers/gpu/drm/i915/i915_drv.h > > @@ -2374,7 +2374,7 @@ intel_info(const struct drm_i915_private *dev_priv) > > * > > * Use GEN_FOREVER for unbound start and or end. > > */ > > -#define IS_GEN(dev_priv, s, e) \ > > +#define GT_GEN_RANGE(dev_priv, s, e) \ > > (!!((dev_priv)->info.gen_mask & INTEL_GEN_MASK((s), (e)))) > > > > /* > > diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c > > index 2c2b63be7a6c..acc3502403b3 100644 > > --- a/drivers/gpu/drm/i915/i915_perf.c > > +++ b/drivers/gpu/drm/i915/i915_perf.c > > @@ -1796,7 +1796,7 @@ static int gen8_enable_metric_set(struct i915_perf_stream *stream) > > * be read back from automatically triggered reports, as part of the > > * RPT_ID field. > > */ > > - if (IS_GEN(dev_priv, 9, 11)) { > > + if (GT_GEN_RANGE(dev_priv, 9, 11)) { > > I915_WRITE(GEN8_OA_DEBUG, > > _MASKED_BIT_ENABLE(GEN9_OA_DEBUG_DISABLE_CLK_RATIO_REPORTS | > > GEN9_OA_DEBUG_INCLUDE_CLK_RATIO)); > > @@ -3476,7 +3476,7 @@ void i915_perf_init(struct drm_i915_private *dev_priv) > > > > dev_priv->perf.oa.gen8_valid_ctx_bit = (1<<16); > > } > > - } else if (IS_GEN(dev_priv, 10, 11)) { > > + } else if (GT_GEN_RANGE(dev_priv, 10, 11)) { > > dev_priv->perf.oa.ops.is_valid_b_counter_reg = > > gen7_is_valid_b_counter_addr; > > dev_priv->perf.oa.ops.is_valid_mux_reg = > > diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c > > index 0ad2304457ab..fb918e942e9a 100644 > > --- a/drivers/gpu/drm/i915/intel_bios.c > > +++ b/drivers/gpu/drm/i915/intel_bios.c > > @@ -446,7 +446,7 @@ parse_sdvo_device_mapping(struct drm_i915_private *dev_priv, u8 bdb_version) > > * Only parse SDVO mappings on gens that could have SDVO. This isn't > > * accurate and doesn't have to be, as long as it's not too strict. > > */ > > - if (!IS_GEN(dev_priv, 3, 7)) { > > + if (!GT_GEN_RANGE(dev_priv, 3, 7)) { > > DRM_DEBUG_KMS("Skipping SDVO device mapping\n"); > > return; > > } > > diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c > > index bc147d9e6c92..4f7b654614e9 100644 > > --- a/drivers/gpu/drm/i915/intel_engine_cs.c > > +++ b/drivers/gpu/drm/i915/intel_engine_cs.c > > @@ -1286,7 +1286,7 @@ static void intel_engine_print_registers(const struct intel_engine_cs *engine, > > &engine->execlists; > > u64 addr; > > > > - if (engine->id == RCS && IS_GEN(dev_priv, 4, 7)) > > + if (engine->id == RCS && GT_GEN_RANGE(dev_priv, 4, 7)) > > drm_printf(m, "\tCCID: 0x%08x\n", I915_READ(CCID)); > > drm_printf(m, "\tRING_START: 0x%08x\n", > > I915_READ(RING_START(engine->mmio_base))); > > diff --git a/drivers/gpu/drm/i915/intel_fbc.c b/drivers/gpu/drm/i915/intel_fbc.c > > index 14cbaf4a0e93..9f41779988e5 100644 > > --- a/drivers/gpu/drm/i915/intel_fbc.c > > +++ b/drivers/gpu/drm/i915/intel_fbc.c > > @@ -784,7 +784,7 @@ static bool intel_fbc_can_activate(struct intel_crtc *crtc) > > * having a Y offset that isn't divisible by 4 causes FIFO underrun > > * and screen flicker. > > */ > > - if (IS_GEN(dev_priv, 9, 10) && > > + if (GT_GEN_RANGE(dev_priv, 9, 10) && > > (fbc->state_cache.plane.adjusted_y & 3)) { > > fbc->no_fbc_reason = "plane Y offset is misaligned"; > > return false; > > diff --git a/drivers/gpu/drm/i915/intel_hangcheck.c b/drivers/gpu/drm/i915/intel_hangcheck.c > > index e26d05a46451..9b15ed1409ae 100644 > > --- a/drivers/gpu/drm/i915/intel_hangcheck.c > > +++ b/drivers/gpu/drm/i915/intel_hangcheck.c > > @@ -252,7 +252,7 @@ engine_stuck(struct intel_engine_cs *engine, u64 acthd) > > return ENGINE_WAIT_KICK; > > } > > > > - if (IS_GEN(dev_priv, 6, 7) && tmp & RING_WAIT_SEMAPHORE) { > > + if (GT_GEN_RANGE(dev_priv, 6, 7) && tmp & RING_WAIT_SEMAPHORE) { > > switch (semaphore_passed(engine)) { > > default: > > return ENGINE_DEAD; > > diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c > > index b8a7a014d46d..0e5f49c45298 100644 > > --- a/drivers/gpu/drm/i915/intel_ringbuffer.c > > +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c > > @@ -407,7 +407,7 @@ static void intel_ring_setup_status_page(struct intel_engine_cs *engine) > > POSTING_READ(mmio); > > > > /* Flush the TLB for this page */ > > - if (IS_GEN(dev_priv, 6, 7)) { > > + if (GT_GEN_RANGE(dev_priv, 6, 7)) { > > i915_reg_t reg = RING_INSTPM(engine->mmio_base); > > > > /* ring should be idle before issuing a sync flush*/ > > @@ -629,7 +629,7 @@ static int init_render_ring(struct intel_engine_cs *engine) > > intel_whitelist_workarounds_apply(engine); > > > > /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */ > > - if (IS_GEN(dev_priv, 4, 6)) > > + if (GT_GEN_RANGE(dev_priv, 4, 6)) > > I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH)); > > > > /* We need to disable the AsyncFlip performance optimisations in order > > @@ -638,7 +638,7 @@ static int init_render_ring(struct intel_engine_cs *engine) > > * > > * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv > > */ > > - if (IS_GEN(dev_priv, 6, 7)) > > + if (GT_GEN_RANGE(dev_priv, 6, 7)) > > I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE)); > > > > /* Required for the hardware to program scanline values for waiting */ > > @@ -663,7 +663,7 @@ static int init_render_ring(struct intel_engine_cs *engine) > > _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB)); > > } > > > > - if (IS_GEN(dev_priv, 6, 7)) > > + if (GT_GEN_RANGE(dev_priv, 6, 7)) > > I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING)); > > > > if (INTEL_GEN(dev_priv) >= 6) > > diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c > > index 9289515108c3..4ffe26cc3c3f 100644 > > --- a/drivers/gpu/drm/i915/intel_uncore.c > > +++ b/drivers/gpu/drm/i915/intel_uncore.c > > @@ -1567,13 +1567,13 @@ void intel_uncore_init(struct drm_i915_private *dev_priv) > > dev_priv->uncore.pmic_bus_access_nb.notifier_call = > > i915_pmic_bus_access_notifier; > > > > - if (IS_GEN(dev_priv, 2, 4) || intel_vgpu_active(dev_priv)) { > > + if (GT_GEN_RANGE(dev_priv, 2, 4) || intel_vgpu_active(dev_priv)) { > > ASSIGN_WRITE_MMIO_VFUNCS(dev_priv, gen2); > > ASSIGN_READ_MMIO_VFUNCS(dev_priv, gen2); > > } else if (IS_GEN5(dev_priv)) { > > ASSIGN_WRITE_MMIO_VFUNCS(dev_priv, gen5); > > ASSIGN_READ_MMIO_VFUNCS(dev_priv, gen5); > > - } else if (IS_GEN(dev_priv, 6, 7)) { > > + } else if (GT_GEN_RANGE(dev_priv, 6, 7)) { > > ASSIGN_WRITE_MMIO_VFUNCS(dev_priv, gen6); > > > > if (IS_VALLEYVIEW(dev_priv)) { > > @@ -1592,7 +1592,7 @@ void intel_uncore_init(struct drm_i915_private *dev_priv) > > ASSIGN_WRITE_MMIO_VFUNCS(dev_priv, gen8); > > ASSIGN_READ_MMIO_VFUNCS(dev_priv, gen6); > > } > > - } else if (IS_GEN(dev_priv, 9, 10)) { > > + } else if (GT_GEN_RANGE(dev_priv, 9, 10)) { > > ASSIGN_FW_DOMAINS_TABLE(__gen9_fw_ranges); > > ASSIGN_WRITE_MMIO_VFUNCS(dev_priv, fwtable); > > ASSIGN_READ_MMIO_VFUNCS(dev_priv, fwtable); > > @@ -2321,7 +2321,7 @@ intel_uncore_forcewake_for_read(struct drm_i915_private *dev_priv, > > } else if (INTEL_GEN(dev_priv) >= 6) { > > fw_domains = __gen6_reg_read_fw_domains(offset); > > } else { > > - WARN_ON(!IS_GEN(dev_priv, 2, 5)); > > + WARN_ON(!GT_GEN_RANGE(dev_priv, 2, 5)); > > fw_domains = 0; > > } > > > > @@ -2343,10 +2343,10 @@ intel_uncore_forcewake_for_write(struct drm_i915_private *dev_priv, > > fw_domains = __fwtable_reg_write_fw_domains(offset); > > } else if (IS_GEN8(dev_priv)) { > > fw_domains = __gen8_reg_write_fw_domains(offset); > > - } else if (IS_GEN(dev_priv, 6, 7)) { > > + } else if (GT_GEN_RANGE(dev_priv, 6, 7)) { > > fw_domains = FORCEWAKE_RENDER; > > } else { > > - WARN_ON(!IS_GEN(dev_priv, 2, 5)); > > + WARN_ON(!GT_GEN_RANGE(dev_priv, 2, 5)); > > fw_domains = 0; > > } > > -- > Jani Nikula, Intel Open Source Graphics Center > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [PATCH v2 2/7] drm/i915: Rename IS_GEN to GT_RANGE 2018-11-28 8:02 ` Jani Nikula 2018-11-28 9:27 ` Joonas Lahtinen 2018-11-28 17:04 ` Rodrigo Vivi @ 2018-11-28 17:34 ` Lucas De Marchi 2 siblings, 0 replies; 38+ messages in thread From: Lucas De Marchi @ 2018-11-28 17:34 UTC (permalink / raw) To: Jani Nikula; +Cc: intel-gfx, Lucas De Marchi, Rodrigo Vivi On Wed, Nov 28, 2018 at 10:02:22AM +0200, Jani Nikula wrote: > On Tue, 06 Nov 2018, Lucas De Marchi <lucas.demarchi@intel.com> wrote: > > From: Rodrigo Vivi <rodrigo.vivi@intel.com> > > > > RANGE makes it longer, but clear. We are also going to add a check for > > the display part, so make rename to GT. > > I also still have my doubts about this patch I'm afraid. I've expressed > the concern before, but here goes again. > > How much is the split of gen to GT gen and display gen going to help us > in the long run? The only current platform that would benefit from this > is GLK. However, not all IS_GEMINILAKE() can be replaced with > IS_DISPLAY_GEN() >= 10 or similar. We also have VLV/CHV display that is > better represented by HAS_GMCH_DISPLAY() and AFAICT can't usefully be > replaced by a display gen check. > > My main fear is that the split adds a lot of confusion. (Where should I > use GT gen, where should I use display gen, patches to change between > one and the other. It's not 100% clear cut.) > > Here too I wonder if we're better off adding more has_feature flags that > describe what gt or display features a platform has. It will never be a clear cut. Adding more flags make perfect sense when there is such a feature to check for. Sometimes registers just change location based on what is the display gen. Having the display gen serves to group small differences together into a "single flag" if you will. And today what we do is to actually check for gen rather than display gen. Or a mix of platform names. Lucas De Marchi _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 38+ messages in thread
* [PATCH v2 3/7] drm/i915: replace IS_GEN<N> with GT_GEN(..., N) 2018-11-06 21:51 [PATCH v2 0/7] Make GEN macros more similar Lucas De Marchi 2018-11-06 21:51 ` [PATCH v2 1/7] Revert "drm/i915: Kill GEN_FOREVER" Lucas De Marchi 2018-11-06 21:51 ` [PATCH v2 2/7] drm/i915: Rename IS_GEN to GT_RANGE Lucas De Marchi @ 2018-11-06 21:51 ` Lucas De Marchi 2018-11-21 22:20 ` Rodrigo Vivi 2018-11-06 21:51 ` [PATCH v2 4/7] drm/i915: rename IS_GEN9_* to GT_GEN9_* Lucas De Marchi ` (8 subsequent siblings) 11 siblings, 1 reply; 38+ messages in thread From: Lucas De Marchi @ 2018-11-06 21:51 UTC (permalink / raw) To: intel-gfx; +Cc: Rodrigo Vivi Define GT_GEN() similarly to our GT_GEN_RANGE() and convert users of IS_GEN<N> to pss the gen as parameter. This prepares for the addition of display gen checks by renaming the IS_GENx() and using common code for all the n gens. The following spatch was used to convert the users of these macros: @@ expression e; @@ ( - IS_GEN2(e) + GT_GEN(e, 2) | - IS_GEN3(e) + GT_GEN(e, 3) | - IS_GEN4(e) + GT_GEN(e, 4) | - IS_GEN5(e) + GT_GEN(e, 5) | - IS_GEN6(e) + GT_GEN(e, 6) | - IS_GEN7(e) + GT_GEN(e, 7) | - IS_GEN8(e) + GT_GEN(e, 8) | - IS_GEN9(e) + GT_GEN(e, 9) | - IS_GEN10(e) + GT_GEN(e, 10) | - IS_GEN11(e) + GT_GEN(e, 11) ) Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> --- drivers/gpu/drm/i915/gvt/vgpu.c | 4 +- drivers/gpu/drm/i915/i915_cmd_parser.c | 2 +- drivers/gpu/drm/i915/i915_debugfs.c | 16 ++--- drivers/gpu/drm/i915/i915_drv.c | 18 +++--- drivers/gpu/drm/i915/i915_drv.h | 29 +++------ drivers/gpu/drm/i915/i915_gem.c | 12 ++-- drivers/gpu/drm/i915/i915_gem_context.c | 2 +- drivers/gpu/drm/i915/i915_gem_execbuffer.c | 4 +- drivers/gpu/drm/i915/i915_gem_fence_reg.c | 10 +-- drivers/gpu/drm/i915/i915_gem_gtt.c | 6 +- drivers/gpu/drm/i915/i915_gem_stolen.c | 7 +- drivers/gpu/drm/i915/i915_gem_tiling.c | 4 +- drivers/gpu/drm/i915/i915_gpu_error.c | 18 +++--- drivers/gpu/drm/i915/i915_irq.c | 24 +++---- drivers/gpu/drm/i915/i915_perf.c | 4 +- drivers/gpu/drm/i915/i915_suspend.c | 12 ++-- drivers/gpu/drm/i915/intel_atomic.c | 2 +- drivers/gpu/drm/i915/intel_audio.c | 2 +- drivers/gpu/drm/i915/intel_cdclk.c | 10 +-- drivers/gpu/drm/i915/intel_crt.c | 6 +- drivers/gpu/drm/i915/intel_device_info.c | 16 ++--- drivers/gpu/drm/i915/intel_display.c | 74 +++++++++++----------- drivers/gpu/drm/i915/intel_dp.c | 24 +++---- drivers/gpu/drm/i915/intel_engine_cs.c | 4 +- drivers/gpu/drm/i915/intel_fbc.c | 22 +++---- drivers/gpu/drm/i915/intel_fifo_underrun.c | 6 +- drivers/gpu/drm/i915/intel_guc_fw.c | 2 +- drivers/gpu/drm/i915/intel_hangcheck.c | 2 +- drivers/gpu/drm/i915/intel_lrc.c | 4 +- drivers/gpu/drm/i915/intel_lvds.c | 4 +- drivers/gpu/drm/i915/intel_mocs.c | 2 +- drivers/gpu/drm/i915/intel_overlay.c | 10 +-- drivers/gpu/drm/i915/intel_panel.c | 8 +-- drivers/gpu/drm/i915/intel_pipe_crc.c | 8 +-- drivers/gpu/drm/i915/intel_pm.c | 60 +++++++++--------- drivers/gpu/drm/i915/intel_psr.c | 4 +- drivers/gpu/drm/i915/intel_ringbuffer.c | 28 ++++---- drivers/gpu/drm/i915/intel_ringbuffer.h | 4 +- drivers/gpu/drm/i915/intel_runtime_pm.c | 2 +- drivers/gpu/drm/i915/intel_sprite.c | 6 +- drivers/gpu/drm/i915/intel_uc.c | 2 +- drivers/gpu/drm/i915/intel_uncore.c | 18 +++--- drivers/gpu/drm/i915/intel_wopcm.c | 4 +- 43 files changed, 247 insertions(+), 259 deletions(-) diff --git a/drivers/gpu/drm/i915/gvt/vgpu.c b/drivers/gpu/drm/i915/gvt/vgpu.c index c628be05fbfe..ea45b22814a1 100644 --- a/drivers/gpu/drm/i915/gvt/vgpu.c +++ b/drivers/gpu/drm/i915/gvt/vgpu.c @@ -148,10 +148,10 @@ int intel_gvt_init_vgpu_types(struct intel_gvt *gvt) gvt->types[i].avail_instance = min(low_avail / vgpu_types[i].low_mm, high_avail / vgpu_types[i].high_mm); - if (IS_GEN8(gvt->dev_priv)) + if (GT_GEN(gvt->dev_priv, 8)) sprintf(gvt->types[i].name, "GVTg_V4_%s", vgpu_types[i].name); - else if (IS_GEN9(gvt->dev_priv)) + else if (GT_GEN(gvt->dev_priv, 9)) sprintf(gvt->types[i].name, "GVTg_V5_%s", vgpu_types[i].name); diff --git a/drivers/gpu/drm/i915/i915_cmd_parser.c b/drivers/gpu/drm/i915/i915_cmd_parser.c index 95478db9998b..2be8c22641b6 100644 --- a/drivers/gpu/drm/i915/i915_cmd_parser.c +++ b/drivers/gpu/drm/i915/i915_cmd_parser.c @@ -865,7 +865,7 @@ void intel_engine_init_cmd_parser(struct intel_engine_cs *engine) int cmd_table_count; int ret; - if (!IS_GEN7(engine->i915)) + if (!GT_GEN(engine->i915, 7)) return; switch (engine->id) { diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index f60485906f7e..2514ec4d97d4 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -1064,7 +1064,7 @@ static int i915_frequency_info(struct seq_file *m, void *unused) intel_runtime_pm_get(dev_priv); - if (IS_GEN5(dev_priv)) { + if (GT_GEN(dev_priv, 5)) { u16 rgvswctl = I915_READ16(MEMSWCTL); u16 rgvstat = I915_READ16(MEMSTAT_ILK); @@ -1785,7 +1785,7 @@ static int i915_emon_status(struct seq_file *m, void *unused) unsigned long temp, chipset, gfx; int ret; - if (!IS_GEN5(dev_priv)) + if (!GT_GEN(dev_priv, 5)) return -ENODEV; ret = mutex_lock_interruptible(&dev->struct_mutex); @@ -2030,7 +2030,7 @@ static int i915_swizzle_info(struct seq_file *m, void *data) seq_printf(m, "bit6 swizzle for Y-tiling = %s\n", swizzle_string(dev_priv->mm.bit_6_swizzle_y)); - if (IS_GEN3(dev_priv) || IS_GEN4(dev_priv)) { + if (GT_GEN(dev_priv, 3) || GT_GEN(dev_priv, 4)) { seq_printf(m, "DDC = 0x%08x\n", I915_READ(DCC)); seq_printf(m, "DDC2 = 0x%08x\n", @@ -2115,12 +2115,12 @@ static void gen6_ppgtt_info(struct seq_file *m, struct intel_engine_cs *engine; enum intel_engine_id id; - if (IS_GEN6(dev_priv)) + if (GT_GEN(dev_priv, 6)) seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE)); for_each_engine(engine, dev_priv, id) { seq_printf(m, "%s\n", engine->name); - if (IS_GEN7(dev_priv)) + if (GT_GEN(dev_priv, 7)) seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(RING_MODE_GEN7(engine))); seq_printf(m, "PP_DIR_BASE: 0x%08x\n", @@ -4261,7 +4261,7 @@ i915_cache_sharing_get(void *data, u64 *val) struct drm_i915_private *dev_priv = data; u32 snpcr; - if (!(IS_GEN6(dev_priv) || IS_GEN7(dev_priv))) + if (!(GT_GEN(dev_priv, 6) || GT_GEN(dev_priv, 7))) return -ENODEV; intel_runtime_pm_get(dev_priv); @@ -4281,7 +4281,7 @@ i915_cache_sharing_set(void *data, u64 val) struct drm_i915_private *dev_priv = data; u32 snpcr; - if (!(IS_GEN6(dev_priv) || IS_GEN7(dev_priv))) + if (!(GT_GEN(dev_priv, 6) || GT_GEN(dev_priv, 7))) return -ENODEV; if (val > 3) @@ -4538,7 +4538,7 @@ static int i915_sseu_status(struct seq_file *m, void *unused) cherryview_sseu_device_status(dev_priv, &sseu); } else if (IS_BROADWELL(dev_priv)) { broadwell_sseu_device_status(dev_priv, &sseu); - } else if (IS_GEN9(dev_priv)) { + } else if (GT_GEN(dev_priv, 9)) { gen9_sseu_device_status(dev_priv, &sseu); } else if (INTEL_GEN(dev_priv) >= 10) { gen10_sseu_device_status(dev_priv, &sseu); diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index acb516308262..d2bdd7112c5d 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -131,15 +131,15 @@ intel_pch_type(const struct drm_i915_private *dev_priv, unsigned short id) switch (id) { case INTEL_PCH_IBX_DEVICE_ID_TYPE: DRM_DEBUG_KMS("Found Ibex Peak PCH\n"); - WARN_ON(!IS_GEN5(dev_priv)); + WARN_ON(!GT_GEN(dev_priv, 5)); return PCH_IBX; case INTEL_PCH_CPT_DEVICE_ID_TYPE: DRM_DEBUG_KMS("Found CougarPoint PCH\n"); - WARN_ON(!IS_GEN6(dev_priv) && !IS_IVYBRIDGE(dev_priv)); + WARN_ON(!GT_GEN(dev_priv, 6) && !IS_IVYBRIDGE(dev_priv)); return PCH_CPT; case INTEL_PCH_PPT_DEVICE_ID_TYPE: DRM_DEBUG_KMS("Found PantherPoint PCH\n"); - WARN_ON(!IS_GEN6(dev_priv) && !IS_IVYBRIDGE(dev_priv)); + WARN_ON(!GT_GEN(dev_priv, 6) && !IS_IVYBRIDGE(dev_priv)); /* PantherPoint is CPT compatible */ return PCH_CPT; case INTEL_PCH_LPT_DEVICE_ID_TYPE: @@ -216,9 +216,9 @@ intel_virt_detect_pch(const struct drm_i915_private *dev_priv) * make an educated guess as to which PCH is really there. */ - if (IS_GEN5(dev_priv)) + if (GT_GEN(dev_priv, 5)) id = INTEL_PCH_IBX_DEVICE_ID_TYPE; - else if (IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv)) + else if (GT_GEN(dev_priv, 6) || IS_IVYBRIDGE(dev_priv)) id = INTEL_PCH_CPT_DEVICE_ID_TYPE; else if (IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv)) id = INTEL_PCH_LPT_LP_DEVICE_ID_TYPE; @@ -955,7 +955,7 @@ static int i915_mmio_setup(struct drm_i915_private *dev_priv) int mmio_bar; int mmio_size; - mmio_bar = IS_GEN2(dev_priv) ? 1 : 0; + mmio_bar = GT_GEN(dev_priv, 2) ? 1 : 0; /* * Before gen4, the registers and the GTT are behind different BARs. * However, from gen4 onwards, the registers and the GTT are shared @@ -1330,7 +1330,7 @@ intel_get_dram_info(struct drm_i915_private *dev_priv) /* Need to calculate bandwidth only for Gen9 */ if (IS_BROXTON(dev_priv)) ret = bxt_get_dram_info(dev_priv); - else if (IS_GEN9(dev_priv)) + else if (GT_GEN(dev_priv, 9)) ret = skl_get_dram_info(dev_priv); else ret = skl_dram_get_channels_info(dev_priv); @@ -1411,7 +1411,7 @@ static int i915_driver_init_hw(struct drm_i915_private *dev_priv) pci_set_master(pdev); /* overlay on gen2 is broken and can't address above 1G */ - if (IS_GEN2(dev_priv)) { + if (GT_GEN(dev_priv, 2)) { ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(30)); if (ret) { DRM_ERROR("failed to set DMA mask\n"); @@ -1548,7 +1548,7 @@ static void i915_driver_register(struct drm_i915_private *dev_priv) acpi_video_register(); } - if (IS_GEN5(dev_priv)) + if (GT_GEN(dev_priv, 5)) intel_gpu_ips_init(dev_priv); intel_audio_init(dev_priv); diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index e4749e93a1f9..f11aad5cd7fb 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -2377,6 +2377,10 @@ intel_info(const struct drm_i915_private *dev_priv) #define GT_GEN_RANGE(dev_priv, s, e) \ (!!((dev_priv)->info.gen_mask & INTEL_GEN_MASK((s), (e)))) +#define GT_GEN(dev_priv, n) \ + (BUILD_BUG_ON_ZERO(!__builtin_constant_p(n)) + \ + (!!((dev_priv)->info.gen_mask & BIT((n) - 1)))) + /* * Return true if revision is in range [since,until] inclusive. * @@ -2528,26 +2532,9 @@ intel_info(const struct drm_i915_private *dev_priv) #define IS_ICL_REVID(p, since, until) \ (IS_ICELAKE(p) && IS_REVID(p, since, until)) -/* - * The genX designation typically refers to the render engine, so render - * capability related checks should use IS_GEN, while display and other checks - * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular - * chips, etc.). - */ -#define IS_GEN2(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(1))) -#define IS_GEN3(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(2))) -#define IS_GEN4(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(3))) -#define IS_GEN5(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(4))) -#define IS_GEN6(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(5))) -#define IS_GEN7(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(6))) -#define IS_GEN8(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(7))) -#define IS_GEN9(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(8))) -#define IS_GEN10(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(9))) -#define IS_GEN11(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(10))) - #define IS_LP(dev_priv) (INTEL_INFO(dev_priv)->is_lp) -#define IS_GEN9_LP(dev_priv) (IS_GEN9(dev_priv) && IS_LP(dev_priv)) -#define IS_GEN9_BC(dev_priv) (IS_GEN9(dev_priv) && !IS_LP(dev_priv)) +#define IS_GEN9_LP(dev_priv) (GT_GEN(dev_priv, 9) && IS_LP(dev_priv)) +#define IS_GEN9_BC(dev_priv) (GT_GEN(dev_priv, 9) && !IS_LP(dev_priv)) #define ENGINE_MASK(id) BIT(id) #define RENDER_RING ENGINE_MASK(RCS) @@ -2568,7 +2555,7 @@ intel_info(const struct drm_i915_private *dev_priv) #define HAS_BLT(dev_priv) HAS_ENGINE(dev_priv, BCS) #define HAS_VEBOX(dev_priv) HAS_ENGINE(dev_priv, VECS) -#define HAS_LEGACY_SEMAPHORES(dev_priv) IS_GEN7(dev_priv) +#define HAS_LEGACY_SEMAPHORES(dev_priv) GT_GEN(dev_priv, 7) #define HAS_LLC(dev_priv) ((dev_priv)->info.has_llc) #define HAS_SNOOP(dev_priv) ((dev_priv)->info.has_snoop) @@ -2620,7 +2607,7 @@ intel_info(const struct drm_i915_private *dev_priv) /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte * rows, which changed the alignment requirements and fence programming. */ -#define HAS_128_BYTE_Y_TILING(dev_priv) (!IS_GEN2(dev_priv) && \ +#define HAS_128_BYTE_Y_TILING(dev_priv) (!GT_GEN(dev_priv, 2) && \ !(IS_I915G(dev_priv) || \ IS_I915GM(dev_priv))) #define SUPPORTS_TV(dev_priv) ((dev_priv)->info.supports_tv) diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index a120112d0621..d50955f7fe3f 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -5223,15 +5223,15 @@ void i915_gem_init_swizzling(struct drm_i915_private *dev_priv) I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) | DISP_TILE_SURFACE_SWIZZLING); - if (IS_GEN5(dev_priv)) + if (GT_GEN(dev_priv, 5)) return; I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL); - if (IS_GEN6(dev_priv)) + if (GT_GEN(dev_priv, 6)) I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB)); - else if (IS_GEN7(dev_priv)) + else if (GT_GEN(dev_priv, 7)) I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB)); - else if (IS_GEN8(dev_priv)) + else if (GT_GEN(dev_priv, 8)) I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW)); else BUG(); @@ -5253,10 +5253,10 @@ static void init_unused_rings(struct drm_i915_private *dev_priv) init_unused_ring(dev_priv, SRB1_BASE); init_unused_ring(dev_priv, SRB2_BASE); init_unused_ring(dev_priv, SRB3_BASE); - } else if (IS_GEN2(dev_priv)) { + } else if (GT_GEN(dev_priv, 2)) { init_unused_ring(dev_priv, SRB0_BASE); init_unused_ring(dev_priv, SRB1_BASE); - } else if (IS_GEN3(dev_priv)) { + } else if (GT_GEN(dev_priv, 3)) { init_unused_ring(dev_priv, PRB1_BASE); init_unused_ring(dev_priv, PRB2_BASE); } diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c index b97963db0287..031a2a358f19 100644 --- a/drivers/gpu/drm/i915/i915_gem_context.c +++ b/drivers/gpu/drm/i915/i915_gem_context.c @@ -311,7 +311,7 @@ static u32 default_desc_template(const struct drm_i915_private *i915, address_mode = INTEL_LEGACY_64B_CONTEXT; desc |= address_mode << GEN8_CTX_ADDRESSING_MODE_SHIFT; - if (IS_GEN8(i915)) + if (GT_GEN(i915, 8)) desc |= GEN8_CTX_L3LLC_COHERENT; /* TODO: WaDisableLiteRestore when we start using semaphore diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c index 1a1c04db6c80..f1df4114305a 100644 --- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c +++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c @@ -1380,7 +1380,7 @@ eb_relocate_entry(struct i915_execbuffer *eb, * batchbuffers. */ if (reloc->write_domain == I915_GEM_DOMAIN_INSTRUCTION && - IS_GEN6(eb->i915)) { + GT_GEN(eb->i915, 6)) { err = i915_vma_bind(target, target->obj->cache_level, PIN_GLOBAL); if (WARN_ONCE(err, @@ -1893,7 +1893,7 @@ static int i915_reset_gen7_sol_offsets(struct i915_request *rq) u32 *cs; int i; - if (!IS_GEN7(rq->i915) || rq->engine->id != RCS) { + if (!GT_GEN(rq->i915, 7) || rq->engine->id != RCS) { DRM_DEBUG("sol reset is gen7/rcs only\n"); return -EINVAL; } diff --git a/drivers/gpu/drm/i915/i915_gem_fence_reg.c b/drivers/gpu/drm/i915/i915_gem_fence_reg.c index d548ac05ccd7..caafbf7e62a4 100644 --- a/drivers/gpu/drm/i915/i915_gem_fence_reg.c +++ b/drivers/gpu/drm/i915/i915_gem_fence_reg.c @@ -193,9 +193,9 @@ static void fence_write(struct drm_i915_fence_reg *fence, * and explicitly managed for internal users. */ - if (IS_GEN2(fence->i915)) + if (GT_GEN(fence->i915, 2)) i830_write_fence_reg(fence, vma); - else if (IS_GEN3(fence->i915)) + else if (GT_GEN(fence->i915, 3)) i915_write_fence_reg(fence, vma); else i965_write_fence_reg(fence, vma); @@ -596,13 +596,13 @@ i915_gem_detect_bit_6_swizzle(struct drm_i915_private *dev_priv) swizzle_y = I915_BIT_6_SWIZZLE_NONE; } } - } else if (IS_GEN5(dev_priv)) { + } else if (GT_GEN(dev_priv, 5)) { /* On Ironlake whatever DRAM config, GPU always do * same swizzling setup. */ swizzle_x = I915_BIT_6_SWIZZLE_9_10; swizzle_y = I915_BIT_6_SWIZZLE_9; - } else if (IS_GEN2(dev_priv)) { + } else if (GT_GEN(dev_priv, 2)) { /* As far as we know, the 865 doesn't have these bit 6 * swizzling issues. */ @@ -647,7 +647,7 @@ i915_gem_detect_bit_6_swizzle(struct drm_i915_private *dev_priv) } /* check for L-shaped memory aka modified enhanced addressing */ - if (IS_GEN4(dev_priv) && + if (GT_GEN(dev_priv, 4) && !(I915_READ(DCC2) & DCC2_MODIFIED_ENHANCED_DISABLE)) { swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN; swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN; diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c index a98c29147d5e..1723f374c5a8 100644 --- a/drivers/gpu/drm/i915/i915_gem_gtt.c +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c @@ -2195,9 +2195,9 @@ int i915_ppgtt_init_hw(struct drm_i915_private *dev_priv) { gtt_write_workarounds(dev_priv); - if (IS_GEN6(dev_priv)) + if (GT_GEN(dev_priv, 6)) gen6_ppgtt_enable(dev_priv); - else if (IS_GEN7(dev_priv)) + else if (GT_GEN(dev_priv, 7)) gen7_ppgtt_enable(dev_priv); return 0; @@ -2279,7 +2279,7 @@ static bool needs_idle_maps(struct drm_i915_private *dev_priv) /* Query intel_iommu to see if we need the workaround. Presumably that * was loaded first. */ - return IS_GEN5(dev_priv) && IS_MOBILE(dev_priv) && intel_vtd_active(); + return GT_GEN(dev_priv, 5) && IS_MOBILE(dev_priv) && intel_vtd_active(); } static void gen6_check_faults(struct drm_i915_private *dev_priv) diff --git a/drivers/gpu/drm/i915/i915_gem_stolen.c b/drivers/gpu/drm/i915/i915_gem_stolen.c index f29a7ff7c362..d01dea84ffae 100644 --- a/drivers/gpu/drm/i915/i915_gem_stolen.c +++ b/drivers/gpu/drm/i915/i915_gem_stolen.c @@ -102,7 +102,7 @@ static int i915_adjust_stolen(struct drm_i915_private *dev_priv, resource_size_t ggtt_start; ggtt_start = I915_READ(PGTBL_CTL); - if (IS_GEN4(dev_priv)) + if (GT_GEN(dev_priv, 4)) ggtt_start = (ggtt_start & PGTBL_ADDRESS_LO_MASK) | (ggtt_start & PGTBL_ADDRESS_HI_MASK) << 28; else @@ -156,7 +156,7 @@ static int i915_adjust_stolen(struct drm_i915_private *dev_priv, * GEN3 firmware likes to smash pci bridges into the stolen * range. Apparently this works. */ - if (r == NULL && !IS_GEN3(dev_priv)) { + if (r == NULL && !GT_GEN(dev_priv, 3)) { DRM_ERROR("conflict detected with stolen region: %pR\n", dsm); @@ -194,7 +194,8 @@ static void g4x_get_stolen_reserved(struct drm_i915_private *dev_priv, * Whether ILK really reuses the ELK register for this is unclear. * Let's see if we catch anyone with this supposedly enabled on ILK. */ - WARN(IS_GEN5(dev_priv), "ILK stolen reserved found? 0x%08x\n", reg_val); + WARN(GT_GEN(dev_priv, 5), "ILK stolen reserved found? 0x%08x\n", + reg_val); if (!(reg_val & G4X_STOLEN_RESERVED_ADDR2_MASK)) return; diff --git a/drivers/gpu/drm/i915/i915_gem_tiling.c b/drivers/gpu/drm/i915/i915_gem_tiling.c index d9dc9df523b5..8a1976c523b0 100644 --- a/drivers/gpu/drm/i915/i915_gem_tiling.c +++ b/drivers/gpu/drm/i915/i915_gem_tiling.c @@ -87,7 +87,7 @@ u32 i915_gem_fence_size(struct drm_i915_private *i915, } /* Previous chips need a power-of-two fence region when tiling */ - if (IS_GEN3(i915)) + if (GT_GEN(i915, 3)) ggtt_size = 1024*1024; else ggtt_size = 512*1024; @@ -162,7 +162,7 @@ i915_tiling_ok(struct drm_i915_gem_object *obj, return false; } - if (IS_GEN2(i915) || + if (GT_GEN(i915, 2) || (tiling == I915_TILING_Y && HAS_128_BYTE_Y_TILING(i915))) tile_width = 128; else diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c index c8d8f79688a8..c7b492b6cf4e 100644 --- a/drivers/gpu/drm/i915/i915_gpu_error.c +++ b/drivers/gpu/drm/i915/i915_gpu_error.c @@ -720,7 +720,7 @@ int i915_error_state_to_str(struct drm_i915_error_state_buf *m, err_printf(m, "DONE_REG: 0x%08x\n", error->done_reg); } - if (IS_GEN7(dev_priv)) + if (GT_GEN(dev_priv, 7)) err_printf(m, "ERR_INT: 0x%08x\n", error->err_int); for (i = 0; i < ARRAY_SIZE(error->engine); i++) { @@ -1234,7 +1234,7 @@ static void error_record_engine_registers(struct i915_gpu_state *error, if (!HWS_NEEDS_PHYSICAL(dev_priv)) { i915_reg_t mmio; - if (IS_GEN7(dev_priv)) { + if (GT_GEN(dev_priv, 7)) { switch (engine->id) { default: case RCS: @@ -1250,7 +1250,7 @@ static void error_record_engine_registers(struct i915_gpu_state *error, mmio = VEBOX_HWS_PGA_GEN7; break; } - } else if (IS_GEN6(engine->i915)) { + } else if (GT_GEN(engine->i915, 6)) { mmio = RING_HWS_PGA_GEN6(engine->mmio_base); } else { /* XXX: gen8 returns to sanity */ @@ -1272,10 +1272,10 @@ static void error_record_engine_registers(struct i915_gpu_state *error, ee->vm_info.gfx_mode = I915_READ(RING_MODE_GEN7(engine)); - if (IS_GEN6(dev_priv)) + if (GT_GEN(dev_priv, 6)) ee->vm_info.pp_dir_base = I915_READ(RING_PP_DIR_BASE_READ(engine)); - else if (IS_GEN7(dev_priv)) + else if (GT_GEN(dev_priv, 7)) ee->vm_info.pp_dir_base = I915_READ(RING_PP_DIR_BASE(engine)); else if (INTEL_GEN(dev_priv) >= 8) @@ -1645,7 +1645,7 @@ static void capture_reg_state(struct i915_gpu_state *error) error->forcewake = I915_READ_FW(FORCEWAKE_VLV); } - if (IS_GEN7(dev_priv)) + if (GT_GEN(dev_priv, 7)) error->err_int = I915_READ(GEN7_ERR_INT); if (INTEL_GEN(dev_priv) >= 8) { @@ -1653,7 +1653,7 @@ static void capture_reg_state(struct i915_gpu_state *error) error->fault_data1 = I915_READ(GEN8_FAULT_TLB_DATA1); } - if (IS_GEN6(dev_priv)) { + if (GT_GEN(dev_priv, 6)) { error->forcewake = I915_READ_FW(FORCEWAKE); error->gab_ctl = I915_READ(GAB_CTL); error->gfx_mode = I915_READ(GFX_MODE); @@ -1673,7 +1673,7 @@ static void capture_reg_state(struct i915_gpu_state *error) error->ccid = I915_READ(CCID); /* 3: Feature specific registers */ - if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv)) { + if (GT_GEN(dev_priv, 6) || GT_GEN(dev_priv, 7)) { error->gam_ecochk = I915_READ(GAM_ECOCHK); error->gac_eco = I915_READ(GAC_ECO_BITS); } @@ -1697,7 +1697,7 @@ static void capture_reg_state(struct i915_gpu_state *error) error->ier = I915_READ(DEIER); error->gtier[0] = I915_READ(GTIER); error->ngtier = 1; - } else if (IS_GEN2(dev_priv)) { + } else if (GT_GEN(dev_priv, 2)) { error->ier = I915_READ16(IER); } else if (!IS_VALLEYVIEW(dev_priv)) { error->ier = I915_READ(IER); diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index 5d1f53723388..3ed545c2d508 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -950,7 +950,7 @@ static int __intel_get_crtc_scanline(struct intel_crtc *crtc) if (mode->flags & DRM_MODE_FLAG_INTERLACE) vtotal /= 2; - if (IS_GEN2(dev_priv)) + if (GT_GEN(dev_priv, 2)) position = I915_READ_FW(PIPEDSL(pipe)) & DSL_LINEMASK_GEN2; else position = I915_READ_FW(PIPEDSL(pipe)) & DSL_LINEMASK_GEN3; @@ -1030,7 +1030,7 @@ static bool i915_get_crtc_scanoutpos(struct drm_device *dev, unsigned int pipe, if (stime) *stime = ktime_get(); - if (IS_GEN2(dev_priv) || IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5) { + if (GT_GEN(dev_priv, 2) || IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5) { /* No obvious pixelcount register. Only query vertical * scanout position from Display scan line register. */ @@ -1090,7 +1090,7 @@ static bool i915_get_crtc_scanoutpos(struct drm_device *dev, unsigned int pipe, else position += vtotal - vbl_end; - if (IS_GEN2(dev_priv) || IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5) { + if (GT_GEN(dev_priv, 2) || IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5) { *vpos = position; *hpos = 0; } else { @@ -2547,7 +2547,7 @@ static void ilk_display_irq_handler(struct drm_i915_private *dev_priv, I915_WRITE(SDEIIR, pch_iir); } - if (IS_GEN5(dev_priv) && de_iir & DE_PCU_EVENT) + if (GT_GEN(dev_priv, 5) && de_iir & DE_PCU_EVENT) ironlake_rps_change_irq_handler(dev_priv); } @@ -3243,7 +3243,7 @@ void i915_clear_error_registers(struct drm_i915_private *dev_priv) { u32 eir; - if (!IS_GEN2(dev_priv)) + if (!GT_GEN(dev_priv, 2)) I915_WRITE(PGTBL_ER, I915_READ(PGTBL_ER)); if (INTEL_GEN(dev_priv) < 4) @@ -3586,11 +3586,11 @@ static void ironlake_irq_reset(struct drm_device *dev) { struct drm_i915_private *dev_priv = to_i915(dev); - if (IS_GEN5(dev_priv)) + if (GT_GEN(dev_priv, 5)) I915_WRITE(HWSTAM, 0xffffffff); GEN3_IRQ_RESET(DE); - if (IS_GEN7(dev_priv)) + if (GT_GEN(dev_priv, 7)) I915_WRITE(GEN7_ERR_INT, 0xffffffff); if (IS_HASWELL(dev_priv)) { @@ -4042,7 +4042,7 @@ static void gen5_gt_irq_postinstall(struct drm_device *dev) } gt_irqs |= GT_RENDER_USER_INTERRUPT; - if (IS_GEN5(dev_priv)) { + if (GT_GEN(dev_priv, 5)) { gt_irqs |= ILK_BSD_USER_INTERRUPT; } else { gt_irqs |= GT_BLT_USER_INTERRUPT | GT_BSD_USER_INTERRUPT; @@ -4833,7 +4833,7 @@ void intel_irq_init(struct drm_i915_private *dev_priv) if (INTEL_GEN(dev_priv) >= 8) rps->pm_intrmsk_mbz |= GEN8_PMINTR_DISABLE_REDIRECT_TO_GUC; - if (IS_GEN2(dev_priv)) { + if (GT_GEN(dev_priv, 2)) { /* Gen2 doesn't have a hardware frame counter */ dev->max_vblank_count = 0; } else if (IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5) { @@ -4849,7 +4849,7 @@ void intel_irq_init(struct drm_i915_private *dev_priv) * Gen2 doesn't have a hardware frame counter and so depends on * vblank interrupts to produce sane vblank seuquence numbers. */ - if (!IS_GEN2(dev_priv)) + if (!GT_GEN(dev_priv, 2)) dev->vblank_disable_immediate = true; /* Most platforms treat the display irq block as an always-on @@ -4914,14 +4914,14 @@ void intel_irq_init(struct drm_i915_private *dev_priv) dev->driver->disable_vblank = ironlake_disable_vblank; dev_priv->display.hpd_irq_setup = ilk_hpd_irq_setup; } else { - if (IS_GEN2(dev_priv)) { + if (GT_GEN(dev_priv, 2)) { dev->driver->irq_preinstall = i8xx_irq_reset; dev->driver->irq_postinstall = i8xx_irq_postinstall; dev->driver->irq_handler = i8xx_irq_handler; dev->driver->irq_uninstall = i8xx_irq_reset; dev->driver->enable_vblank = i8xx_enable_vblank; dev->driver->disable_vblank = i8xx_disable_vblank; - } else if (IS_GEN3(dev_priv)) { + } else if (GT_GEN(dev_priv, 3)) { dev->driver->irq_preinstall = i915_irq_reset; dev->driver->irq_postinstall = i915_irq_postinstall; dev->driver->irq_uninstall = i915_irq_reset; diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c index acc3502403b3..afbccc144c66 100644 --- a/drivers/gpu/drm/i915/i915_perf.c +++ b/drivers/gpu/drm/i915/i915_perf.c @@ -3449,7 +3449,7 @@ void i915_perf_init(struct drm_i915_private *dev_priv) dev_priv->perf.oa.ops.read = gen8_oa_read; dev_priv->perf.oa.ops.oa_hw_tail_read = gen8_oa_hw_tail_read; - if (IS_GEN8(dev_priv) || IS_GEN9(dev_priv)) { + if (GT_GEN(dev_priv, 8) || GT_GEN(dev_priv, 9)) { dev_priv->perf.oa.ops.is_valid_b_counter_reg = gen7_is_valid_b_counter_addr; dev_priv->perf.oa.ops.is_valid_mux_reg = @@ -3465,7 +3465,7 @@ void i915_perf_init(struct drm_i915_private *dev_priv) dev_priv->perf.oa.ops.enable_metric_set = gen8_enable_metric_set; dev_priv->perf.oa.ops.disable_metric_set = gen8_disable_metric_set; - if (IS_GEN8(dev_priv)) { + if (GT_GEN(dev_priv, 8)) { dev_priv->perf.oa.ctx_oactxctrl_offset = 0x120; dev_priv->perf.oa.ctx_flexeu0_offset = 0x2ce; diff --git a/drivers/gpu/drm/i915/i915_suspend.c b/drivers/gpu/drm/i915/i915_suspend.c index 8f3aa4dc0c98..b47b822fa6d6 100644 --- a/drivers/gpu/drm/i915/i915_suspend.c +++ b/drivers/gpu/drm/i915/i915_suspend.c @@ -65,7 +65,7 @@ int i915_save_state(struct drm_i915_private *dev_priv) i915_save_display(dev_priv); - if (IS_GEN4(dev_priv)) + if (GT_GEN(dev_priv, 4)) pci_read_config_word(pdev, GCDGMBUS, &dev_priv->regfile.saveGCDGMBUS); @@ -77,14 +77,14 @@ int i915_save_state(struct drm_i915_private *dev_priv) dev_priv->regfile.saveMI_ARB_STATE = I915_READ(MI_ARB_STATE); /* Scratch space */ - if (IS_GEN2(dev_priv) && IS_MOBILE(dev_priv)) { + if (GT_GEN(dev_priv, 2) && IS_MOBILE(dev_priv)) { for (i = 0; i < 7; i++) { dev_priv->regfile.saveSWF0[i] = I915_READ(SWF0(i)); dev_priv->regfile.saveSWF1[i] = I915_READ(SWF1(i)); } for (i = 0; i < 3; i++) dev_priv->regfile.saveSWF3[i] = I915_READ(SWF3(i)); - } else if (IS_GEN2(dev_priv)) { + } else if (GT_GEN(dev_priv, 2)) { for (i = 0; i < 7; i++) dev_priv->regfile.saveSWF1[i] = I915_READ(SWF1(i)); } else if (HAS_GMCH_DISPLAY(dev_priv)) { @@ -108,7 +108,7 @@ int i915_restore_state(struct drm_i915_private *dev_priv) mutex_lock(&dev_priv->drm.struct_mutex); - if (IS_GEN4(dev_priv)) + if (GT_GEN(dev_priv, 4)) pci_write_config_word(pdev, GCDGMBUS, dev_priv->regfile.saveGCDGMBUS); i915_restore_display(dev_priv); @@ -122,14 +122,14 @@ int i915_restore_state(struct drm_i915_private *dev_priv) I915_WRITE(MI_ARB_STATE, dev_priv->regfile.saveMI_ARB_STATE | 0xffff0000); /* Scratch space */ - if (IS_GEN2(dev_priv) && IS_MOBILE(dev_priv)) { + if (GT_GEN(dev_priv, 2) && IS_MOBILE(dev_priv)) { for (i = 0; i < 7; i++) { I915_WRITE(SWF0(i), dev_priv->regfile.saveSWF0[i]); I915_WRITE(SWF1(i), dev_priv->regfile.saveSWF1[i]); } for (i = 0; i < 3; i++) I915_WRITE(SWF3(i), dev_priv->regfile.saveSWF3[i]); - } else if (IS_GEN2(dev_priv)) { + } else if (GT_GEN(dev_priv, 2)) { for (i = 0; i < 7; i++) I915_WRITE(SWF1(i), dev_priv->regfile.saveSWF1[i]); } else if (HAS_GMCH_DISPLAY(dev_priv)) { diff --git a/drivers/gpu/drm/i915/intel_atomic.c b/drivers/gpu/drm/i915/intel_atomic.c index a5a2c8fe58a7..74dc23f67151 100644 --- a/drivers/gpu/drm/i915/intel_atomic.c +++ b/drivers/gpu/drm/i915/intel_atomic.c @@ -232,7 +232,7 @@ static void intel_atomic_setup_scaler(struct intel_crtc_scaler_state *scaler_sta if (plane_state && plane_state->base.fb && plane_state->base.fb->format->is_yuv && plane_state->base.fb->format->num_planes > 1) { - if (IS_GEN9(dev_priv) && + if (GT_GEN(dev_priv, 9) && !IS_GEMINILAKE(dev_priv)) { mode = SKL_PS_SCALER_MODE_NV12; } else if (icl_is_hdr_plane(to_intel_plane(plane_state->base.plane))) { diff --git a/drivers/gpu/drm/i915/intel_audio.c b/drivers/gpu/drm/i915/intel_audio.c index ccd88da20a14..7f47bacbef20 100644 --- a/drivers/gpu/drm/i915/intel_audio.c +++ b/drivers/gpu/drm/i915/intel_audio.c @@ -758,7 +758,7 @@ static void i915_audio_component_codec_wake_override(struct device *kdev, struct drm_i915_private *dev_priv = kdev_to_i915(kdev); u32 tmp; - if (!IS_GEN9(dev_priv)) + if (!GT_GEN(dev_priv, 9)) return; i915_audio_component_get_power(kdev); diff --git a/drivers/gpu/drm/i915/intel_cdclk.c b/drivers/gpu/drm/i915/intel_cdclk.c index 8d74276029e6..db0edd01c973 100644 --- a/drivers/gpu/drm/i915/intel_cdclk.c +++ b/drivers/gpu/drm/i915/intel_cdclk.c @@ -2140,7 +2140,7 @@ static int intel_pixel_rate_to_cdclk(struct drm_i915_private *dev_priv, { if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) return DIV_ROUND_UP(pixel_rate, 2); - else if (IS_GEN9(dev_priv) || + else if (GT_GEN(dev_priv, 9) || IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) return pixel_rate; else if (IS_CHERRYVIEW(dev_priv)) @@ -2176,7 +2176,7 @@ int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state) if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv)) { /* Display WA #1145: glk,cnl */ min_cdclk = max(316800, min_cdclk); - } else if (IS_GEN9(dev_priv) || IS_BROADWELL(dev_priv)) { + } else if (GT_GEN(dev_priv, 9) || IS_BROADWELL(dev_priv)) { /* Display WA #1144: skl,bxt */ min_cdclk = max(432000, min_cdclk); } @@ -2537,7 +2537,7 @@ static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv) if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) return 2 * max_cdclk_freq; - else if (IS_GEN9(dev_priv) || + else if (GT_GEN(dev_priv, 9) || IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) return max_cdclk_freq; else if (IS_CHERRYVIEW(dev_priv)) @@ -2806,9 +2806,9 @@ void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv) dev_priv->display.get_cdclk = hsw_get_cdclk; else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) dev_priv->display.get_cdclk = vlv_get_cdclk; - else if (IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv)) + else if (GT_GEN(dev_priv, 6) || IS_IVYBRIDGE(dev_priv)) dev_priv->display.get_cdclk = fixed_400mhz_get_cdclk; - else if (IS_GEN5(dev_priv)) + else if (GT_GEN(dev_priv, 5)) dev_priv->display.get_cdclk = fixed_450mhz_get_cdclk; else if (IS_GM45(dev_priv)) dev_priv->display.get_cdclk = gm45_get_cdclk; diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c index 68f2fb89ece3..b37224227420 100644 --- a/drivers/gpu/drm/i915/intel_crt.c +++ b/drivers/gpu/drm/i915/intel_crt.c @@ -322,7 +322,7 @@ intel_crt_mode_valid(struct drm_connector *connector, * DAC limit supposedly 355 MHz. */ max_clock = 270000; - else if (IS_GEN3(dev_priv) || IS_GEN4(dev_priv)) + else if (GT_GEN(dev_priv, 3) || GT_GEN(dev_priv, 4)) max_clock = 400000; else max_clock = 350000; @@ -666,7 +666,7 @@ intel_crt_load_detect(struct intel_crt *crt, uint32_t pipe) /* Set the border color to purple. */ I915_WRITE(bclrpat_reg, 0x500050); - if (!IS_GEN2(dev_priv)) { + if (!GT_GEN(dev_priv, 2)) { uint32_t pipeconf = I915_READ(pipeconf_reg); I915_WRITE(pipeconf_reg, pipeconf | PIPECONF_FORCE_BORDER); POSTING_READ(pipeconf_reg); @@ -981,7 +981,7 @@ void intel_crt_init(struct drm_i915_private *dev_priv) else crt->base.crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); - if (IS_GEN2(dev_priv)) + if (GT_GEN(dev_priv, 2)) connector->interlace_allowed = 0; else connector->interlace_allowed = 1; diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c index 89ed3a84a4fa..7f712cd238fe 100644 --- a/drivers/gpu/drm/i915/intel_device_info.c +++ b/drivers/gpu/drm/i915/intel_device_info.c @@ -744,7 +744,7 @@ void intel_device_info_runtime_init(struct intel_device_info *info) if (INTEL_GEN(dev_priv) >= 10) { for_each_pipe(dev_priv, pipe) info->num_scalers[pipe] = 2; - } else if (IS_GEN9(dev_priv)) { + } else if (GT_GEN(dev_priv, 9)) { info->num_scalers[PIPE_A] = 2; info->num_scalers[PIPE_B] = 2; info->num_scalers[PIPE_C] = 1; @@ -752,10 +752,10 @@ void intel_device_info_runtime_init(struct intel_device_info *info) BUILD_BUG_ON(I915_NUM_ENGINES > BITS_PER_TYPE(intel_ring_mask_t)); - if (IS_GEN11(dev_priv)) + if (GT_GEN(dev_priv, 11)) for_each_pipe(dev_priv, pipe) info->num_sprites[pipe] = 6; - else if (IS_GEN10(dev_priv) || IS_GEMINILAKE(dev_priv)) + else if (GT_GEN(dev_priv, 10) || IS_GEMINILAKE(dev_priv)) for_each_pipe(dev_priv, pipe) info->num_sprites[pipe] = 3; else if (IS_BROXTON(dev_priv)) { @@ -783,7 +783,7 @@ void intel_device_info_runtime_init(struct intel_device_info *info) DRM_INFO("Display disabled (module parameter)\n"); info->num_pipes = 0; } else if (info->num_pipes > 0 && - (IS_GEN7(dev_priv) || IS_GEN8(dev_priv)) && + (GT_GEN(dev_priv, 7) || GT_GEN(dev_priv, 8)) && HAS_PCH_SPLIT(dev_priv)) { u32 fuse_strap = I915_READ(FUSE_STRAP); u32 sfuse_strap = I915_READ(SFUSE_STRAP); @@ -807,7 +807,7 @@ void intel_device_info_runtime_init(struct intel_device_info *info) DRM_INFO("PipeC fused off\n"); info->num_pipes -= 1; } - } else if (info->num_pipes > 0 && IS_GEN9(dev_priv)) { + } else if (info->num_pipes > 0 && GT_GEN(dev_priv, 9)) { u32 dfsm = I915_READ(SKL_DFSM); u8 disabled_mask = 0; bool invalid; @@ -847,14 +847,14 @@ void intel_device_info_runtime_init(struct intel_device_info *info) cherryview_sseu_info_init(dev_priv); else if (IS_BROADWELL(dev_priv)) broadwell_sseu_info_init(dev_priv); - else if (IS_GEN9(dev_priv)) + else if (GT_GEN(dev_priv, 9)) gen9_sseu_info_init(dev_priv); - else if (IS_GEN10(dev_priv)) + else if (GT_GEN(dev_priv, 10)) gen10_sseu_info_init(dev_priv); else if (INTEL_GEN(dev_priv) >= 11) gen11_sseu_info_init(dev_priv); - if (IS_GEN6(dev_priv) && intel_vtd_active()) { + if (GT_GEN(dev_priv, 6) && intel_vtd_active()) { DRM_INFO("Disabling ppGTT for VT-d support\n"); info->ppgtt = INTEL_PPGTT_NONE; } diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index bbf8ca21a7a2..904950a65c1b 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -984,7 +984,7 @@ static bool pipe_scanline_is_moving(struct drm_i915_private *dev_priv, u32 line1, line2; u32 line_mask; - if (IS_GEN2(dev_priv)) + if (GT_GEN(dev_priv, 2)) line_mask = DSL_LINEMASK_GEN2; else line_mask = DSL_LINEMASK_GEN3; @@ -1110,7 +1110,7 @@ static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv, u32 val; /* ILK FDI PLL is always enabled */ - if (IS_GEN5(dev_priv)) + if (GT_GEN(dev_priv, 5)) return; /* On Haswell, DDI ports are responsible for the FDI PLL setup */ @@ -1849,7 +1849,7 @@ static void intel_disable_pipe(const struct intel_crtc_state *old_crtc_state) static unsigned int intel_tile_size(const struct drm_i915_private *dev_priv) { - return IS_GEN2(dev_priv) ? 2048 : 4096; + return GT_GEN(dev_priv, 2) ? 2048 : 4096; } static unsigned int @@ -1862,7 +1862,7 @@ intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane) case DRM_FORMAT_MOD_LINEAR: return cpp; case I915_FORMAT_MOD_X_TILED: - if (IS_GEN2(dev_priv)) + if (GT_GEN(dev_priv, 2)) return 128; else return 512; @@ -1871,7 +1871,7 @@ intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane) return 128; /* fall through */ case I915_FORMAT_MOD_Y_TILED: - if (IS_GEN2(dev_priv) || HAS_128_BYTE_Y_TILING(dev_priv)) + if (GT_GEN(dev_priv, 2) || HAS_128_BYTE_Y_TILING(dev_priv)) return 128; else return 512; @@ -3175,8 +3175,8 @@ static u32 i9xx_plane_ctl(const struct intel_crtc_state *crtc_state, dspcntr = DISPLAY_PLANE_ENABLE | DISPPLANE_GAMMA_ENABLE; - if (IS_G4X(dev_priv) || IS_GEN5(dev_priv) || - IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv)) + if (IS_G4X(dev_priv) || GT_GEN(dev_priv, 5) || + GT_GEN(dev_priv, 6) || IS_IVYBRIDGE(dev_priv)) dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) @@ -4095,7 +4095,7 @@ static void gen6_fdi_link_train(struct intel_crtc *crtc, temp = I915_READ(reg); temp &= ~FDI_LINK_TRAIN_NONE; temp |= FDI_LINK_TRAIN_PATTERN_2; - if (IS_GEN6(dev_priv)) { + if (GT_GEN(dev_priv, 6)) { temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; /* SNB-B */ temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; @@ -4862,10 +4862,10 @@ skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach, /* range checks */ if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H || dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H || - (IS_GEN11(dev_priv) && + (GT_GEN(dev_priv, 11) && (src_w > ICL_MAX_SRC_W || src_h > ICL_MAX_SRC_H || dst_w > ICL_MAX_DST_W || dst_h > ICL_MAX_DST_H)) || - (!IS_GEN11(dev_priv) && + (!GT_GEN(dev_priv, 11) && (src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H || dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H))) { DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u " @@ -5149,7 +5149,7 @@ intel_post_enable_primary(struct drm_crtc *crtc, * FIXME: Need to fix the logic to work when we turn off all planes * but leave the pipe running. */ - if (IS_GEN2(dev_priv)) + if (GT_GEN(dev_priv, 2)) intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); /* Underruns don't always raise interrupts, so check manually. */ @@ -5170,7 +5170,7 @@ intel_pre_disable_primary_noatomic(struct drm_crtc *crtc) * Gen2 reports pipe underruns whenever all planes are disabled. * So disable underrun reporting before all the planes get disabled. */ - if (IS_GEN2(dev_priv)) + if (GT_GEN(dev_priv, 2)) intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); hsw_disable_ips(to_intel_crtc_state(crtc->state)); @@ -5228,7 +5228,7 @@ static bool needs_nv12_wa(struct drm_i915_private *dev_priv, return false; /* WA Display #0827: Gen9:all */ - if (IS_GEN9(dev_priv) && !IS_GEMINILAKE(dev_priv)) + if (GT_GEN(dev_priv, 9) && !IS_GEMINILAKE(dev_priv)) return true; return false; @@ -5301,7 +5301,7 @@ static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state, * Gen2 reports pipe underruns whenever all planes are disabled. * So disable underrun reporting before all the planes get disabled. */ - if (IS_GEN2(dev_priv) && old_primary_state->visible && + if (GT_GEN(dev_priv, 2) && old_primary_state->visible && (modeset || !new_primary_state->base.visible)) intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false); } @@ -6115,7 +6115,7 @@ static void i9xx_crtc_enable(struct intel_crtc_state *pipe_config, intel_crtc->active = true; - if (!IS_GEN2(dev_priv)) + if (!GT_GEN(dev_priv, 2)) intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); intel_encoders_pre_enable(crtc, pipe_config, old_state); @@ -6167,7 +6167,7 @@ static void i9xx_crtc_disable(struct intel_crtc_state *old_crtc_state, * On gen2 planes are double buffered but the pipe isn't, so we must * wait for planes to fully turn off before disabling the pipe. */ - if (IS_GEN2(dev_priv)) + if (GT_GEN(dev_priv, 2)) intel_wait_for_vblank(dev_priv, pipe); intel_encoders_disable(crtc, old_crtc_state, old_state); @@ -6192,7 +6192,7 @@ static void i9xx_crtc_disable(struct intel_crtc_state *old_crtc_state, intel_encoders_post_pll_disable(crtc, old_crtc_state, old_state); - if (!IS_GEN2(dev_priv)) + if (!GT_GEN(dev_priv, 2)) intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); if (!dev_priv->display.initial_watermarks) @@ -6796,7 +6796,7 @@ static bool transcoder_has_m2_n2(struct drm_i915_private *dev_priv, * Strictly speaking some registers are available before * gen7, but we only support DRRS on gen7+ */ - return IS_GEN7(dev_priv) || IS_CHERRYVIEW(dev_priv); + return GT_GEN(dev_priv, 7) || IS_CHERRYVIEW(dev_priv); } static void intel_cpu_transcoder_set_m_n(const struct intel_crtc_state *crtc_state, @@ -8903,7 +8903,7 @@ static void ironlake_get_pfit_config(struct intel_crtc *crtc, /* We currently do not free assignements of panel fitters on * ivb/hsw (since we don't use the higher upscaling modes which * differentiates them) so just WARN about this case for now. */ - if (IS_GEN7(dev_priv)) { + if (GT_GEN(dev_priv, 7)) { WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) != PF_PIPE_SEL_IVB(crtc->pipe)); } @@ -9865,7 +9865,7 @@ static u32 i9xx_cursor_ctl(const struct intel_crtc_state *crtc_state, struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); u32 cntl = 0; - if (IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv)) + if (GT_GEN(dev_priv, 6) || IS_IVYBRIDGE(dev_priv)) cntl |= MCURSOR_TRICKLE_FEED_DISABLE; if (INTEL_GEN(dev_priv) <= 10) { @@ -10335,7 +10335,7 @@ static int i9xx_pll_refclk(struct drm_device *dev, return dev_priv->vbt.lvds_ssc_freq; else if (HAS_PCH_SPLIT(dev_priv)) return 120000; - else if (!IS_GEN2(dev_priv)) + else if (!GT_GEN(dev_priv, 2)) return 96000; else return 48000; @@ -10368,7 +10368,7 @@ static void i9xx_crtc_clock_get(struct intel_crtc *crtc, clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT; } - if (!IS_GEN2(dev_priv)) { + if (!GT_GEN(dev_priv, 2)) { if (IS_PINEVIEW(dev_priv)) clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >> DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW); @@ -10684,7 +10684,7 @@ int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_crtc_stat * the w/a on all three platforms. */ if (plane->id == PLANE_SPRITE0 && - (IS_GEN5(dev_priv) || IS_GEN6(dev_priv) || + (GT_GEN(dev_priv, 5) || GT_GEN(dev_priv, 6) || IS_IVYBRIDGE(dev_priv)) && (turn_on || (!needs_scaling(old_plane_state) && needs_scaling(to_intel_plane_state(plane_state))))) @@ -12238,7 +12238,7 @@ static void update_scanline_offset(const struct intel_crtc_state *crtc_state) * However if queried just before the start of vblank we'll get an * answer that's slightly in the future. */ - if (IS_GEN2(dev_priv)) { + if (GT_GEN(dev_priv, 2)) { const struct drm_display_mode *adjusted_mode = &crtc_state->base.adjusted_mode; int vtotal; @@ -13437,7 +13437,7 @@ void intel_crtc_arm_fifo_underrun(struct intel_crtc *crtc, { struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); - if (!IS_GEN2(dev_priv)) + if (!GT_GEN(dev_priv, 2)) intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true); if (crtc_state->has_pch_encoder) { @@ -14044,7 +14044,7 @@ static bool has_edp_a(struct drm_i915_private *dev_priv) if ((I915_READ(DP_A) & DP_DETECTED) == 0) return false; - if (IS_GEN5(dev_priv) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE)) + if (GT_GEN(dev_priv, 5) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE)) return false; return true; @@ -14256,7 +14256,7 @@ static void intel_setup_outputs(struct drm_i915_private *dev_priv) } vlv_dsi_init(dev_priv); - } else if (!IS_GEN2(dev_priv) && !IS_PINEVIEW(dev_priv)) { + } else if (!GT_GEN(dev_priv, 2) && !IS_PINEVIEW(dev_priv)) { bool found = false; if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { @@ -14290,7 +14290,7 @@ static void intel_setup_outputs(struct drm_i915_private *dev_priv) if (IS_G4X(dev_priv) && (I915_READ(DP_D) & DP_DETECTED)) intel_dp_init(dev_priv, DP_D, PORT_D); - } else if (IS_GEN2(dev_priv)) + } else if (GT_GEN(dev_priv, 2)) intel_dvo_init(dev_priv); if (SUPPORTS_TV(dev_priv)) @@ -14577,7 +14577,7 @@ static int intel_framebuffer_init(struct intel_framebuffer *intel_fb, * require the entire fb to accommodate that to avoid * potential runtime errors at plane configuration time. */ - if (IS_GEN9(dev_priv) && i == 0 && fb->width > 3840 && + if (GT_GEN(dev_priv, 9) && i == 0 && fb->width > 3840 && is_ccs_modifier(fb->modifier)) stride_alignment *= 4; @@ -14782,7 +14782,7 @@ void intel_init_display_hooks(struct drm_i915_private *dev_priv) dev_priv->display.crtc_compute_clock = pnv_crtc_compute_clock; dev_priv->display.crtc_enable = i9xx_crtc_enable; dev_priv->display.crtc_disable = i9xx_crtc_disable; - } else if (!IS_GEN2(dev_priv)) { + } else if (!GT_GEN(dev_priv, 2)) { dev_priv->display.get_pipe_config = i9xx_get_pipe_config; dev_priv->display.get_initial_plane_config = i9xx_get_initial_plane_config; @@ -14798,9 +14798,9 @@ void intel_init_display_hooks(struct drm_i915_private *dev_priv) dev_priv->display.crtc_disable = i9xx_crtc_disable; } - if (IS_GEN5(dev_priv)) { + if (GT_GEN(dev_priv, 5)) { dev_priv->display.fdi_link_train = ironlake_fdi_link_train; - } else if (IS_GEN6(dev_priv)) { + } else if (GT_GEN(dev_priv, 6)) { dev_priv->display.fdi_link_train = gen6_fdi_link_train; } else if (IS_IVYBRIDGE(dev_priv)) { /* FIXME: detect B0+ stepping and use auto training */ @@ -14932,12 +14932,12 @@ static void sanitize_watermarks(struct drm_device *dev) static void intel_update_fdi_pll_freq(struct drm_i915_private *dev_priv) { - if (IS_GEN5(dev_priv)) { + if (GT_GEN(dev_priv, 5)) { u32 fdi_pll_clk = I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK; dev_priv->fdi_pll_freq = (fdi_pll_clk + 2) * 10000; - } else if (IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv)) { + } else if (GT_GEN(dev_priv, 6) || IS_IVYBRIDGE(dev_priv)) { dev_priv->fdi_pll_freq = 270000; } else { return; @@ -15043,10 +15043,10 @@ int intel_modeset_init(struct drm_device *dev) } /* maximum framebuffer dimensions */ - if (IS_GEN2(dev_priv)) { + if (GT_GEN(dev_priv, 2)) { dev->mode_config.max_width = 2048; dev->mode_config.max_height = 2048; - } else if (IS_GEN3(dev_priv)) { + } else if (GT_GEN(dev_priv, 3)) { dev->mode_config.max_width = 4096; dev->mode_config.max_height = 4096; } else { @@ -15057,7 +15057,7 @@ int intel_modeset_init(struct drm_device *dev) if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) { dev->mode_config.cursor_width = IS_I845G(dev_priv) ? 64 : 512; dev->mode_config.cursor_height = 1023; - } else if (IS_GEN2(dev_priv)) { + } else if (GT_GEN(dev_priv, 2)) { dev->mode_config.cursor_width = 64; dev->mode_config.cursor_height = 64; } else { diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index 5258c9d654f4..9e410b04f99d 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -342,7 +342,7 @@ intel_dp_set_source_rates(struct intel_dp *intel_dp) if (INTEL_GEN(dev_priv) >= 10) { source_rates = cnl_rates; size = ARRAY_SIZE(cnl_rates); - if (IS_GEN10(dev_priv)) + if (GT_GEN(dev_priv, 10)) max_rate = cnl_max_source_rate(intel_dp); else max_rate = icl_max_source_rate(intel_dp); @@ -1126,7 +1126,7 @@ static uint32_t g4x_get_aux_send_ctl(struct intel_dp *intel_dp, to_i915(intel_dig_port->base.base.dev); uint32_t precharge, timeout; - if (IS_GEN6(dev_priv)) + if (GT_GEN(dev_priv, 6)) precharge = 3; else precharge = 5; @@ -2412,7 +2412,7 @@ static void edp_panel_on(struct intel_dp *intel_dp) pp_ctrl_reg = _pp_ctrl_reg(intel_dp); pp = ironlake_get_pp_control(intel_dp); - if (IS_GEN5(dev_priv)) { + if (GT_GEN(dev_priv, 5)) { /* ILK workaround: disable reset around power sequence */ pp &= ~PANEL_POWER_RESET; I915_WRITE(pp_ctrl_reg, pp); @@ -2420,7 +2420,7 @@ static void edp_panel_on(struct intel_dp *intel_dp) } pp |= PANEL_POWER_ON; - if (!IS_GEN5(dev_priv)) + if (!GT_GEN(dev_priv, 5)) pp |= PANEL_POWER_RESET; I915_WRITE(pp_ctrl_reg, pp); @@ -2429,7 +2429,7 @@ static void edp_panel_on(struct intel_dp *intel_dp) wait_panel_on(intel_dp); intel_dp->last_power_on = jiffies; - if (IS_GEN5(dev_priv)) { + if (GT_GEN(dev_priv, 5)) { pp |= PANEL_POWER_RESET; /* restore panel reset bit */ I915_WRITE(pp_ctrl_reg, pp); POSTING_READ(pp_ctrl_reg); @@ -2658,7 +2658,7 @@ static void ironlake_edp_pll_on(struct intel_dp *intel_dp, * 1. Wait for the start of vertical blank on the enabled pipe going to FDI * 2. Program DP PLL enable */ - if (IS_GEN5(dev_priv)) + if (GT_GEN(dev_priv, 5)) intel_wait_for_vblank_if_active(dev_priv, !crtc->pipe); intel_dp->DP |= DP_PLL_ENABLE; @@ -3660,7 +3660,7 @@ intel_dp_set_signal_levels(struct intel_dp *intel_dp) } else if (IS_IVYBRIDGE(dev_priv) && port == PORT_A) { signal_levels = ivb_cpu_edp_signal_levels(train_set); mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB; - } else if (IS_GEN6(dev_priv) && port == PORT_A) { + } else if (GT_GEN(dev_priv, 6) && port == PORT_A) { signal_levels = snb_cpu_edp_signal_levels(train_set); mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB; } else { @@ -5026,17 +5026,17 @@ bool intel_digital_port_connected(struct intel_encoder *encoder) if (INTEL_GEN(dev_priv) >= 11) return icl_digital_port_connected(encoder); - else if (IS_GEN10(dev_priv) || IS_GEN9_BC(dev_priv)) + else if (GT_GEN(dev_priv, 10) || IS_GEN9_BC(dev_priv)) return spt_digital_port_connected(encoder); else if (IS_GEN9_LP(dev_priv)) return bxt_digital_port_connected(encoder); - else if (IS_GEN8(dev_priv)) + else if (GT_GEN(dev_priv, 8)) return bdw_digital_port_connected(encoder); - else if (IS_GEN7(dev_priv)) + else if (GT_GEN(dev_priv, 7)) return ivb_digital_port_connected(encoder); - else if (IS_GEN6(dev_priv)) + else if (GT_GEN(dev_priv, 6)) return snb_digital_port_connected(encoder); - else if (IS_GEN5(dev_priv)) + else if (GT_GEN(dev_priv, 5)) return ilk_digital_port_connected(encoder); MISSING_CASE(INTEL_GEN(dev_priv)); diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c index 4f7b654614e9..4032a635acb5 100644 --- a/drivers/gpu/drm/i915/intel_engine_cs.c +++ b/drivers/gpu/drm/i915/intel_engine_cs.c @@ -438,7 +438,7 @@ void intel_engine_init_global_seqno(struct intel_engine_cs *engine, u32 seqno) * the semaphore value, then when the seqno moves backwards all * future waits will complete instantly (causing rendering corruption). */ - if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv)) { + if (GT_GEN(dev_priv, 6) || GT_GEN(dev_priv, 7)) { I915_WRITE(RING_SYNC_0(engine->mmio_base), 0); I915_WRITE(RING_SYNC_1(engine->mmio_base), 0); if (HAS_VEBOX(dev_priv)) @@ -812,7 +812,7 @@ u32 intel_calculate_mcr_s_ss_select(struct drm_i915_private *dev_priv) u32 slice = fls(sseu->slice_mask); u32 subslice = fls(sseu->subslice_mask[slice]); - if (IS_GEN10(dev_priv)) + if (GT_GEN(dev_priv, 10)) mcr_s_ss_select = GEN8_MCR_SLICE(slice) | GEN8_MCR_SUBSLICE(subslice); else if (INTEL_GEN(dev_priv) >= 11) diff --git a/drivers/gpu/drm/i915/intel_fbc.c b/drivers/gpu/drm/i915/intel_fbc.c index 9f41779988e5..549e3dc0e457 100644 --- a/drivers/gpu/drm/i915/intel_fbc.c +++ b/drivers/gpu/drm/i915/intel_fbc.c @@ -84,7 +84,7 @@ static int intel_fbc_calculate_cfb_size(struct drm_i915_private *dev_priv, int lines; intel_fbc_get_plane_source_size(cache, NULL, &lines); - if (IS_GEN7(dev_priv)) + if (GT_GEN(dev_priv, 7)) lines = min(lines, 2048); else if (INTEL_GEN(dev_priv) >= 8) lines = min(lines, 2560); @@ -127,7 +127,7 @@ static void i8xx_fbc_activate(struct drm_i915_private *dev_priv) cfb_pitch = params->fb.stride; /* FBC_CTL wants 32B or 64B units */ - if (IS_GEN2(dev_priv)) + if (GT_GEN(dev_priv, 2)) cfb_pitch = (cfb_pitch / 32) - 1; else cfb_pitch = (cfb_pitch / 64) - 1; @@ -136,7 +136,7 @@ static void i8xx_fbc_activate(struct drm_i915_private *dev_priv) for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++) I915_WRITE(FBC_TAG(i), 0); - if (IS_GEN4(dev_priv)) { + if (GT_GEN(dev_priv, 4)) { u32 fbc_ctl2; /* Set it up... */ @@ -233,9 +233,9 @@ static void ilk_fbc_activate(struct drm_i915_private *dev_priv) if (params->flags & PLANE_HAS_FENCE) { dpfc_ctl |= DPFC_CTL_FENCE_EN; - if (IS_GEN5(dev_priv)) + if (GT_GEN(dev_priv, 5)) dpfc_ctl |= params->vma->fence->id; - if (IS_GEN6(dev_priv)) { + if (GT_GEN(dev_priv, 6)) { I915_WRITE(SNB_DPFC_CTL_SA, SNB_CPU_FENCE_ENABLE | params->vma->fence->id); @@ -243,7 +243,7 @@ static void ilk_fbc_activate(struct drm_i915_private *dev_priv) params->crtc.fence_y_offset); } } else { - if (IS_GEN6(dev_priv)) { + if (GT_GEN(dev_priv, 6)) { I915_WRITE(SNB_DPFC_CTL_SA, 0); I915_WRITE(DPFC_CPU_FENCE_OFFSET, 0); } @@ -282,7 +282,7 @@ static void gen7_fbc_activate(struct drm_i915_private *dev_priv) int threshold = dev_priv->fbc.threshold; /* Display WA #0529: skl, kbl, bxt. */ - if (IS_GEN9(dev_priv) && !IS_GEMINILAKE(dev_priv)) { + if (GT_GEN(dev_priv, 9) && !IS_GEMINILAKE(dev_priv)) { u32 val = I915_READ(CHICKEN_MISC_4); val &= ~(FBC_STRIDE_OVERRIDE | FBC_STRIDE_MASK); @@ -581,10 +581,10 @@ static bool stride_is_valid(struct drm_i915_private *dev_priv, if (stride < 512) return false; - if (IS_GEN2(dev_priv) || IS_GEN3(dev_priv)) + if (GT_GEN(dev_priv, 2) || GT_GEN(dev_priv, 3)) return stride == 4096 || stride == 8192; - if (IS_GEN4(dev_priv) && !IS_G4X(dev_priv) && stride < 2048) + if (GT_GEN(dev_priv, 4) && !IS_G4X(dev_priv) && stride < 2048) return false; if (stride > 16384) @@ -603,7 +603,7 @@ static bool pixel_format_is_valid(struct drm_i915_private *dev_priv, case DRM_FORMAT_XRGB1555: case DRM_FORMAT_RGB565: /* 16bpp not supported on gen2 */ - if (IS_GEN2(dev_priv)) + if (GT_GEN(dev_priv, 2)) return false; /* WaFbcOnly1to1Ratio:ctg */ if (IS_G4X(dev_priv)) @@ -839,7 +839,7 @@ static void intel_fbc_get_reg_params(struct intel_crtc *crtc, params->cfb_size = intel_fbc_calculate_cfb_size(dev_priv, cache); - if (IS_GEN9(dev_priv) && !IS_GEMINILAKE(dev_priv)) + if (GT_GEN(dev_priv, 9) && !IS_GEMINILAKE(dev_priv)) params->gen9_wa_cfb_stride = DIV_ROUND_UP(cache->plane.src_w, 32 * fbc->threshold) * 8; } diff --git a/drivers/gpu/drm/i915/intel_fifo_underrun.c b/drivers/gpu/drm/i915/intel_fifo_underrun.c index 77c123cc8817..06f69bca0ff4 100644 --- a/drivers/gpu/drm/i915/intel_fifo_underrun.c +++ b/drivers/gpu/drm/i915/intel_fifo_underrun.c @@ -260,9 +260,9 @@ static bool __intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev, if (HAS_GMCH_DISPLAY(dev_priv)) i9xx_set_fifo_underrun_reporting(dev, pipe, enable, old); - else if (IS_GEN5(dev_priv) || IS_GEN6(dev_priv)) + else if (GT_GEN(dev_priv, 5) || GT_GEN(dev_priv, 6)) ironlake_set_fifo_underrun_reporting(dev, pipe, enable); - else if (IS_GEN7(dev_priv)) + else if (GT_GEN(dev_priv, 7)) ivybridge_set_fifo_underrun_reporting(dev, pipe, enable, old); else if (INTEL_GEN(dev_priv) >= 8) broadwell_set_fifo_underrun_reporting(dev, pipe, enable); @@ -423,7 +423,7 @@ void intel_check_cpu_fifo_underruns(struct drm_i915_private *dev_priv) if (HAS_GMCH_DISPLAY(dev_priv)) i9xx_check_fifo_underruns(crtc); - else if (IS_GEN7(dev_priv)) + else if (GT_GEN(dev_priv, 7)) ivybridge_check_fifo_underruns(crtc); } diff --git a/drivers/gpu/drm/i915/intel_guc_fw.c b/drivers/gpu/drm/i915/intel_guc_fw.c index ae8e103a2c4d..9fdce47755e2 100644 --- a/drivers/gpu/drm/i915/intel_guc_fw.c +++ b/drivers/gpu/drm/i915/intel_guc_fw.c @@ -114,7 +114,7 @@ static void guc_prepare_xfer(struct intel_guc *guc) else I915_WRITE(GEN9_GT_PM_CONFIG, GT_DOORBELL_ENABLE); - if (IS_GEN9(dev_priv)) { + if (GT_GEN(dev_priv, 9)) { /* DOP Clock Gating Enable for GuC clocks */ I915_WRITE(GEN7_MISCCPCTL, (GEN8_DOP_CLOCK_GATE_GUC_ENABLE | I915_READ(GEN7_MISCCPCTL))); diff --git a/drivers/gpu/drm/i915/intel_hangcheck.c b/drivers/gpu/drm/i915/intel_hangcheck.c index 9b15ed1409ae..84867ca2cc0c 100644 --- a/drivers/gpu/drm/i915/intel_hangcheck.c +++ b/drivers/gpu/drm/i915/intel_hangcheck.c @@ -236,7 +236,7 @@ engine_stuck(struct intel_engine_cs *engine, u64 acthd) if (ha != ENGINE_DEAD) return ha; - if (IS_GEN2(dev_priv)) + if (GT_GEN(dev_priv, 2)) return ENGINE_DEAD; /* Is the chip hanging on a WAIT_FOR_EVENT? diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c index 22b57b8926fc..d8b53a0eac09 100644 --- a/drivers/gpu/drm/i915/intel_lrc.c +++ b/drivers/gpu/drm/i915/intel_lrc.c @@ -1990,7 +1990,7 @@ static int gen8_emit_flush_render(struct i915_request *request, * On GEN9: before VF_CACHE_INVALIDATE we need to emit a NULL * pipe control. */ - if (IS_GEN9(request->i915)) + if (GT_GEN(request->i915, 9)) vf_flush_wa = true; /* WaForGAMHang:kbl */ @@ -2368,7 +2368,7 @@ make_rpcs(struct drm_i915_private *dev_priv) * subslices are enabled, or a count between one and four on the first * slice. */ - if (IS_GEN11(dev_priv) && slices == 1 && subslices >= 4) { + if (GT_GEN(dev_priv, 11) && slices == 1 && subslices >= 4) { GEM_BUG_ON(subslices & 1); subslice_pg = false; diff --git a/drivers/gpu/drm/i915/intel_lvds.c b/drivers/gpu/drm/i915/intel_lvds.c index e6c5d985ea0a..79fa6b09a8db 100644 --- a/drivers/gpu/drm/i915/intel_lvds.c +++ b/drivers/gpu/drm/i915/intel_lvds.c @@ -279,7 +279,7 @@ static void intel_pre_enable_lvds(struct intel_encoder *encoder, * special lvds dither control bit on pch-split platforms, dithering is * only controlled through the PIPECONF reg. */ - if (IS_GEN4(dev_priv)) { + if (GT_GEN(dev_priv, 4)) { /* * Bspec wording suggests that LVDS port dithering only exists * for 18bpp panels. @@ -919,7 +919,7 @@ void intel_lvds_init(struct drm_i915_private *dev_priv) intel_encoder->cloneable = 0; if (HAS_PCH_SPLIT(dev_priv)) intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); - else if (IS_GEN4(dev_priv)) + else if (GT_GEN(dev_priv, 4)) intel_encoder->crtc_mask = (1 << 0) | (1 << 1); else intel_encoder->crtc_mask = (1 << 1); diff --git a/drivers/gpu/drm/i915/intel_mocs.c b/drivers/gpu/drm/i915/intel_mocs.c index 77e9871a8c9a..8201774c2c0f 100644 --- a/drivers/gpu/drm/i915/intel_mocs.c +++ b/drivers/gpu/drm/i915/intel_mocs.c @@ -193,7 +193,7 @@ static bool get_mocs_settings(struct drm_i915_private *dev_priv, } /* WaDisableSkipCaching:skl,bxt,kbl,glk */ - if (IS_GEN9(dev_priv)) { + if (GT_GEN(dev_priv, 9)) { int i; for (i = 0; i < table->size; i++) diff --git a/drivers/gpu/drm/i915/intel_overlay.c b/drivers/gpu/drm/i915/intel_overlay.c index 72eb7e48e8bc..c8eddf941762 100644 --- a/drivers/gpu/drm/i915/intel_overlay.c +++ b/drivers/gpu/drm/i915/intel_overlay.c @@ -541,7 +541,7 @@ static u32 calc_swidthsw(struct drm_i915_private *dev_priv, u32 offset, u32 widt { u32 sw; - if (IS_GEN2(dev_priv)) + if (GT_GEN(dev_priv, 2)) sw = ALIGN((offset & 31) + width, 32); else sw = ALIGN((offset & 63) + width, 64); @@ -778,7 +778,7 @@ static int intel_overlay_do_put_image(struct intel_overlay *overlay, u32 oconfig; oconfig = OCONF_CC_OUT_8BIT; - if (IS_GEN4(dev_priv)) + if (GT_GEN(dev_priv, 4)) oconfig |= OCONF_CSC_MODE_BT709; oconfig |= pipe == 0 ? OCONF_PIPE_A : OCONF_PIPE_B; @@ -1012,7 +1012,7 @@ static int check_overlay_src(struct drm_i915_private *dev_priv, if (rec->stride_Y & stride_mask || rec->stride_UV & stride_mask) return -EINVAL; - if (IS_GEN4(dev_priv) && rec->stride_Y < 512) + if (GT_GEN(dev_priv, 4) && rec->stride_Y < 512) return -EINVAL; tmp = (rec->flags & I915_OVERLAY_TYPE_MASK) == I915_OVERLAY_YUV_PLANAR ? @@ -1246,7 +1246,7 @@ int intel_overlay_attrs_ioctl(struct drm_device *dev, void *data, attrs->contrast = overlay->contrast; attrs->saturation = overlay->saturation; - if (!IS_GEN2(dev_priv)) { + if (!GT_GEN(dev_priv, 2)) { attrs->gamma0 = I915_READ(OGAMC0); attrs->gamma1 = I915_READ(OGAMC1); attrs->gamma2 = I915_READ(OGAMC2); @@ -1270,7 +1270,7 @@ int intel_overlay_attrs_ioctl(struct drm_device *dev, void *data, update_reg_attrs(overlay, overlay->regs); if (attrs->flags & I915_OVERLAY_UPDATE_GAMMA) { - if (IS_GEN2(dev_priv)) + if (GT_GEN(dev_priv, 2)) goto out_unlock; if (overlay->active) { diff --git a/drivers/gpu/drm/i915/intel_panel.c b/drivers/gpu/drm/i915/intel_panel.c index e6cd7b55c018..e658904c5576 100644 --- a/drivers/gpu/drm/i915/intel_panel.c +++ b/drivers/gpu/drm/i915/intel_panel.c @@ -563,7 +563,7 @@ static void i9xx_set_backlight(const struct drm_connector_state *conn_state, u32 pci_write_config_byte(dev_priv->drm.pdev, LBPC, lbpc); } - if (IS_GEN4(dev_priv)) { + if (GT_GEN(dev_priv, 4)) { mask = BACKLIGHT_DUTY_CYCLE_MASK; } else { level <<= 1; @@ -929,7 +929,7 @@ static void i9xx_enable_backlight(const struct intel_crtc_state *crtc_state, * 855gm only, but checking for gen2 is safe, as 855gm is the only gen2 * that has backlight. */ - if (IS_GEN2(dev_priv)) + if (GT_GEN(dev_priv, 2)) I915_WRITE(BLC_HIST_CTL, BLM_HISTOGRAM_ENABLE); } @@ -1557,7 +1557,7 @@ static int i9xx_setup_backlight(struct intel_connector *connector, enum pipe unu ctl = I915_READ(BLC_PWM_CTL); - if (IS_GEN2(dev_priv) || IS_I915GM(dev_priv) || IS_I945GM(dev_priv)) + if (GT_GEN(dev_priv, 2) || IS_I915GM(dev_priv) || IS_I945GM(dev_priv)) panel->backlight.combination_mode = ctl & BLM_LEGACY_MODE; if (IS_PINEVIEW(dev_priv)) @@ -1886,7 +1886,7 @@ intel_panel_init_backlight_funcs(struct intel_panel *panel) panel->backlight.get = vlv_get_backlight; panel->backlight.hz_to_pwm = vlv_hz_to_pwm; } - } else if (IS_GEN4(dev_priv)) { + } else if (GT_GEN(dev_priv, 4)) { panel->backlight.setup = i965_setup_backlight; panel->backlight.enable = i965_enable_backlight; panel->backlight.disable = i965_disable_backlight; diff --git a/drivers/gpu/drm/i915/intel_pipe_crc.c b/drivers/gpu/drm/i915/intel_pipe_crc.c index f3c9010e332a..a426978b233d 100644 --- a/drivers/gpu/drm/i915/intel_pipe_crc.c +++ b/drivers/gpu/drm/i915/intel_pipe_crc.c @@ -427,13 +427,13 @@ static int get_new_crc_ctl_reg(struct drm_i915_private *dev_priv, enum intel_pipe_crc_source *source, u32 *val, bool set_wa) { - if (IS_GEN2(dev_priv)) + if (GT_GEN(dev_priv, 2)) return i8xx_pipe_crc_ctl_reg(source, val); else if (INTEL_GEN(dev_priv) < 5) return i9xx_pipe_crc_ctl_reg(dev_priv, pipe, source, val); else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) return vlv_pipe_crc_ctl_reg(dev_priv, pipe, source, val); - else if (IS_GEN5(dev_priv) || IS_GEN6(dev_priv)) + else if (GT_GEN(dev_priv, 5) || GT_GEN(dev_priv, 6)) return ilk_pipe_crc_ctl_reg(source, val); else return ivb_pipe_crc_ctl_reg(dev_priv, pipe, source, val, set_wa); @@ -544,13 +544,13 @@ static int intel_is_valid_crc_source(struct drm_i915_private *dev_priv, const enum intel_pipe_crc_source source) { - if (IS_GEN2(dev_priv)) + if (GT_GEN(dev_priv, 2)) return i8xx_crc_source_valid(dev_priv, source); else if (INTEL_GEN(dev_priv) < 5) return i9xx_crc_source_valid(dev_priv, source); else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) return vlv_crc_source_valid(dev_priv, source); - else if (IS_GEN5(dev_priv) || IS_GEN6(dev_priv)) + else if (GT_GEN(dev_priv, 5) || GT_GEN(dev_priv, 6)) return ilk_crc_source_valid(dev_priv, source); else return ivb_crc_source_valid(dev_priv, source); diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 9da8ff263d36..74e14d8848f8 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -2273,7 +2273,7 @@ static void i9xx_update_wm(struct intel_crtc *unused_crtc) if (IS_I945GM(dev_priv)) wm_info = &i945_wm_info; - else if (!IS_GEN2(dev_priv)) + else if (!GT_GEN(dev_priv, 2)) wm_info = &i915_wm_info; else wm_info = &i830_a_wm_info; @@ -2287,7 +2287,7 @@ static void i9xx_update_wm(struct intel_crtc *unused_crtc) crtc->base.primary->state->fb; int cpp; - if (IS_GEN2(dev_priv)) + if (GT_GEN(dev_priv, 2)) cpp = 4; else cpp = fb->format->cpp[0]; @@ -2302,7 +2302,7 @@ static void i9xx_update_wm(struct intel_crtc *unused_crtc) planea_wm = wm_info->max_wm; } - if (IS_GEN2(dev_priv)) + if (GT_GEN(dev_priv, 2)) wm_info = &i830_bc_wm_info; fifo_size = dev_priv->display.get_fifo_size(dev_priv, PLANE_B); @@ -2314,7 +2314,7 @@ static void i9xx_update_wm(struct intel_crtc *unused_crtc) crtc->base.primary->state->fb; int cpp; - if (IS_GEN2(dev_priv)) + if (GT_GEN(dev_priv, 2)) cpp = 4; else cpp = fb->format->cpp[0]; @@ -2917,7 +2917,7 @@ static void intel_fixup_spr_wm_latency(struct drm_i915_private *dev_priv, uint16_t wm[5]) { /* ILK sprite LP0 latency is 1300 ns */ - if (IS_GEN5(dev_priv)) + if (GT_GEN(dev_priv, 5)) wm[0] = 13; } @@ -2925,7 +2925,7 @@ static void intel_fixup_cur_wm_latency(struct drm_i915_private *dev_priv, uint16_t wm[5]) { /* ILK cursor LP0 latency is 1300 ns */ - if (IS_GEN5(dev_priv)) + if (GT_GEN(dev_priv, 5)) wm[0] = 13; } @@ -3024,7 +3024,7 @@ static void ilk_setup_wm_latency(struct drm_i915_private *dev_priv) intel_print_wm_latency(dev_priv, "Sprite", dev_priv->wm.spr_latency); intel_print_wm_latency(dev_priv, "Cursor", dev_priv->wm.cur_latency); - if (IS_GEN6(dev_priv)) + if (GT_GEN(dev_priv, 6)) snb_wm_latency_quirk(dev_priv); } @@ -3278,7 +3278,7 @@ static void ilk_wm_merge(struct drm_device *dev, * What we should check here is whether FBC can be * enabled sometime later. */ - if (IS_GEN5(dev_priv) && !merged->fbc_wm_enabled && + if (GT_GEN(dev_priv, 5) && !merged->fbc_wm_enabled && intel_fbc_is_active(dev_priv)) { for (level = 2; level <= max_level; level++) { struct intel_wm_level *wm = &merged->wm[level]; @@ -3716,9 +3716,9 @@ bool intel_can_enable_sagv(struct drm_atomic_state *state) if (!intel_has_sagv(dev_priv)) return false; - if (IS_GEN9(dev_priv)) + if (GT_GEN(dev_priv, 9)) sagv_block_time_us = 30; - else if (IS_GEN10(dev_priv)) + else if (GT_GEN(dev_priv, 10)) sagv_block_time_us = 20; else sagv_block_time_us = 10; @@ -4666,7 +4666,7 @@ skl_compute_plane_wm_params(const struct drm_i915_private *dev_priv, wp->plane_blocks_per_line = div_fixed16(interm_pbpl, wp->y_min_scanlines); - } else if (wp->x_tiled && IS_GEN9(dev_priv)) { + } else if (wp->x_tiled && GT_GEN(dev_priv, 9)) { interm_pbpl = DIV_ROUND_UP(wp->plane_bytes_per_line, wp->dbuf_block_size); wp->plane_blocks_per_line = u32_to_fixed16(interm_pbpl); @@ -4734,13 +4734,13 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv, selected_result = method2; } else if (ddb_allocation >= fixed16_to_u32_round_up(wp->plane_blocks_per_line)) { - if (IS_GEN9(dev_priv) && + if (GT_GEN(dev_priv, 9) && !IS_GEMINILAKE(dev_priv)) selected_result = min_fixed16(method1, method2); else selected_result = method2; } else if (latency >= wp->linetime_us) { - if (IS_GEN9(dev_priv) && + if (GT_GEN(dev_priv, 9) && !IS_GEMINILAKE(dev_priv)) selected_result = min_fixed16(method1, method2); else @@ -6979,7 +6979,7 @@ static void gen9_enable_rps(struct drm_i915_private *dev_priv) intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); /* Program defaults and thresholds for RPS */ - if (IS_GEN9(dev_priv)) + if (GT_GEN(dev_priv, 9)) I915_WRITE(GEN6_RC_VIDEO_FREQ, GEN9_FREQUENCY(dev_priv->gt_pm.rps.rp1_freq)); @@ -7215,9 +7215,9 @@ static void gen6_enable_rc6(struct drm_i915_private *dev_priv) rc6vids = 0; ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids); - if (IS_GEN6(dev_priv) && ret) { + if (GT_GEN(dev_priv, 6) && ret) { DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n"); - } else if (IS_GEN6(dev_priv) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) { + } else if (GT_GEN(dev_priv, 6) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) { DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n", GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450); rc6vids &= 0xffff00; @@ -7917,7 +7917,7 @@ unsigned long i915_chipset_val(struct drm_i915_private *dev_priv) { unsigned long val; - if (!IS_GEN5(dev_priv)) + if (!GT_GEN(dev_priv, 5)) return 0; spin_lock_irq(&mchdev_lock); @@ -8001,7 +8001,7 @@ static void __i915_update_gfx_val(struct drm_i915_private *dev_priv) void i915_update_gfx_val(struct drm_i915_private *dev_priv) { - if (!IS_GEN5(dev_priv)) + if (!GT_GEN(dev_priv, 5)) return; spin_lock_irq(&mchdev_lock); @@ -8052,7 +8052,7 @@ unsigned long i915_gfx_val(struct drm_i915_private *dev_priv) { unsigned long val; - if (!IS_GEN5(dev_priv)) + if (!GT_GEN(dev_priv, 5)) return 0; spin_lock_irq(&mchdev_lock); @@ -8340,7 +8340,7 @@ void intel_init_gt_powersave(struct drm_i915_private *dev_priv) intel_freq_opcode(dev_priv, 450)); /* After setting max-softlimit, find the overclock max freq */ - if (IS_GEN6(dev_priv) || + if (GT_GEN(dev_priv, 6) || IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv)) { u32 params = 0; @@ -9410,9 +9410,9 @@ void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv) dev_priv->display.init_clock_gating = ivb_init_clock_gating; else if (IS_VALLEYVIEW(dev_priv)) dev_priv->display.init_clock_gating = vlv_init_clock_gating; - else if (IS_GEN6(dev_priv)) + else if (GT_GEN(dev_priv, 6)) dev_priv->display.init_clock_gating = gen6_init_clock_gating; - else if (IS_GEN5(dev_priv)) + else if (GT_GEN(dev_priv, 5)) dev_priv->display.init_clock_gating = ilk_init_clock_gating; else if (IS_G4X(dev_priv)) dev_priv->display.init_clock_gating = g4x_init_clock_gating; @@ -9420,11 +9420,11 @@ void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv) dev_priv->display.init_clock_gating = i965gm_init_clock_gating; else if (IS_I965G(dev_priv)) dev_priv->display.init_clock_gating = i965g_init_clock_gating; - else if (IS_GEN3(dev_priv)) + else if (GT_GEN(dev_priv, 3)) dev_priv->display.init_clock_gating = gen3_init_clock_gating; else if (IS_I85X(dev_priv) || IS_I865G(dev_priv)) dev_priv->display.init_clock_gating = i85x_init_clock_gating; - else if (IS_GEN2(dev_priv)) + else if (GT_GEN(dev_priv, 2)) dev_priv->display.init_clock_gating = i830_init_clock_gating; else { MISSING_CASE(INTEL_DEVID(dev_priv)); @@ -9440,7 +9440,7 @@ void intel_init_pm(struct drm_i915_private *dev_priv) /* For cxsr */ if (IS_PINEVIEW(dev_priv)) i915_pineview_get_mem_freq(dev_priv); - else if (IS_GEN5(dev_priv)) + else if (GT_GEN(dev_priv, 5)) i915_ironlake_get_mem_freq(dev_priv); /* For FIFO watermark updates */ @@ -9452,9 +9452,9 @@ void intel_init_pm(struct drm_i915_private *dev_priv) } else if (HAS_PCH_SPLIT(dev_priv)) { ilk_setup_wm_latency(dev_priv); - if ((IS_GEN5(dev_priv) && dev_priv->wm.pri_latency[1] && + if ((GT_GEN(dev_priv, 5) && dev_priv->wm.pri_latency[1] && dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) || - (!IS_GEN5(dev_priv) && dev_priv->wm.pri_latency[0] && + (!GT_GEN(dev_priv, 5) && dev_priv->wm.pri_latency[0] && dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) { dev_priv->display.compute_pipe_wm = ilk_compute_pipe_wm; dev_priv->display.compute_intermediate_wm = @@ -9495,12 +9495,12 @@ void intel_init_pm(struct drm_i915_private *dev_priv) dev_priv->display.update_wm = NULL; } else dev_priv->display.update_wm = pineview_update_wm; - } else if (IS_GEN4(dev_priv)) { + } else if (GT_GEN(dev_priv, 4)) { dev_priv->display.update_wm = i965_update_wm; - } else if (IS_GEN3(dev_priv)) { + } else if (GT_GEN(dev_priv, 3)) { dev_priv->display.update_wm = i9xx_update_wm; dev_priv->display.get_fifo_size = i9xx_get_fifo_size; - } else if (IS_GEN2(dev_priv)) { + } else if (GT_GEN(dev_priv, 2)) { if (INTEL_INFO(dev_priv)->num_pipes == 1) { dev_priv->display.update_wm = i845_update_wm; dev_priv->display.get_fifo_size = i845_get_fifo_size; diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c index bc2d88313ed0..cacd54cc00e6 100644 --- a/drivers/gpu/drm/i915/intel_psr.c +++ b/drivers/gpu/drm/i915/intel_psr.c @@ -466,7 +466,7 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp, if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) { psr_max_h = 4096; psr_max_v = 2304; - } else if (IS_GEN9(dev_priv)) { + } else if (GT_GEN(dev_priv, 9)) { psr_max_h = 3640; psr_max_v = 2304; } @@ -574,7 +574,7 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp, if (dev_priv->psr.psr2_enabled) { u32 chicken = I915_READ(CHICKEN_TRANS(cpu_transcoder)); - if (IS_GEN9(dev_priv) && !IS_GEMINILAKE(dev_priv)) + if (GT_GEN(dev_priv, 9) && !IS_GEMINILAKE(dev_priv)) chicken |= (PSR2_VSC_ENABLE_PROG_HEADER | PSR2_ADD_VERTICAL_LINE_COUNT); diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index 0e5f49c45298..e2907ae38b7f 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c @@ -123,7 +123,7 @@ gen4_render_ring_flush(struct i915_request *rq, u32 mode) cmd = MI_FLUSH; if (mode & EMIT_INVALIDATE) { cmd |= MI_EXE_FLUSH; - if (IS_G4X(rq->i915) || IS_GEN5(rq->i915)) + if (IS_G4X(rq->i915) || GT_GEN(rq->i915, 5)) cmd |= MI_INVALIDATE_ISP; } @@ -363,7 +363,7 @@ static void intel_ring_setup_status_page(struct intel_engine_cs *engine) /* The ring status page addresses are no longer next to the rest of * the ring registers as of gen7. */ - if (IS_GEN7(dev_priv)) { + if (GT_GEN(dev_priv, 7)) { switch (engine->id) { /* * No more rings exist on Gen7. Default case is only to shut up @@ -384,7 +384,7 @@ static void intel_ring_setup_status_page(struct intel_engine_cs *engine) mmio = VEBOX_HWS_PGA_GEN7; break; } - } else if (IS_GEN6(dev_priv)) { + } else if (GT_GEN(dev_priv, 6)) { mmio = RING_HWS_PGA_GEN6(engine->mmio_base); } else { mmio = RING_HWS_PGA(engine->mmio_base); @@ -643,17 +643,17 @@ static int init_render_ring(struct intel_engine_cs *engine) /* Required for the hardware to program scanline values for waiting */ /* WaEnableFlushTlbInvalidationMode:snb */ - if (IS_GEN6(dev_priv)) + if (GT_GEN(dev_priv, 6)) I915_WRITE(GFX_MODE, _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT)); /* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */ - if (IS_GEN7(dev_priv)) + if (GT_GEN(dev_priv, 7)) I915_WRITE(GFX_MODE_GEN7, _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT) | _MASKED_BIT_ENABLE(GFX_REPLAY_MODE)); - if (IS_GEN6(dev_priv)) { + if (GT_GEN(dev_priv, 6)) { /* From the Sandybridge PRM, volume 1 part 3, page 24: * "If this bit is set, STCunit will have LRA as replacement * policy. [...] This bit must be reset. LRA replacement @@ -1531,7 +1531,7 @@ static inline int mi_set_context(struct i915_request *rq, u32 flags) enum intel_engine_id id; const int num_rings = /* Use an extended w/a on gen7 if signalling from other rings */ - (HAS_LEGACY_SEMAPHORES(i915) && IS_GEN7(i915)) ? + (HAS_LEGACY_SEMAPHORES(i915) && GT_GEN(i915, 7)) ? INTEL_INFO(i915)->num_rings - 1 : 0; bool force_restore = false; @@ -1546,7 +1546,7 @@ static inline int mi_set_context(struct i915_request *rq, u32 flags) flags |= MI_SAVE_EXT_STATE_EN | MI_RESTORE_EXT_STATE_EN; len = 4; - if (IS_GEN7(i915)) + if (GT_GEN(i915, 7)) len += 2 + (num_rings ? 4*num_rings + 6 : 0); if (flags & MI_FORCE_RESTORE) { GEM_BUG_ON(flags & MI_RESTORE_INHIBIT); @@ -1560,7 +1560,7 @@ static inline int mi_set_context(struct i915_request *rq, u32 flags) return PTR_ERR(cs); /* WaProgramMiArbOnOffAroundMiSetContext:ivb,vlv,hsw,bdw,chv */ - if (IS_GEN7(i915)) { + if (GT_GEN(i915, 7)) { *cs++ = MI_ARB_ON_OFF | MI_ARB_DISABLE; if (num_rings) { struct intel_engine_cs *signaller; @@ -1607,7 +1607,7 @@ static inline int mi_set_context(struct i915_request *rq, u32 flags) */ *cs++ = MI_NOOP; - if (IS_GEN7(i915)) { + if (GT_GEN(i915, 7)) { if (num_rings) { struct intel_engine_cs *signaller; i915_reg_t last_reg = {}; /* keep gcc quiet */ @@ -2230,9 +2230,9 @@ int intel_init_render_ring_buffer(struct intel_engine_cs *engine) if (INTEL_GEN(dev_priv) >= 6) { engine->init_context = intel_rcs_ctx_init; engine->emit_flush = gen7_render_ring_flush; - if (IS_GEN6(dev_priv)) + if (GT_GEN(dev_priv, 6)) engine->emit_flush = gen6_render_ring_flush; - } else if (IS_GEN5(dev_priv)) { + } else if (GT_GEN(dev_priv, 5)) { engine->emit_flush = gen4_render_ring_flush; } else { if (INTEL_GEN(dev_priv) < 4) @@ -2262,13 +2262,13 @@ int intel_init_bsd_ring_buffer(struct intel_engine_cs *engine) if (INTEL_GEN(dev_priv) >= 6) { /* gen6 bsd needs a special wa for tail updates */ - if (IS_GEN6(dev_priv)) + if (GT_GEN(dev_priv, 6)) engine->set_default_submission = gen6_bsd_set_default_submission; engine->emit_flush = gen6_bsd_ring_flush; engine->irq_enable_mask = GT_BSD_USER_INTERRUPT; } else { engine->emit_flush = bsd_ring_flush; - if (IS_GEN5(dev_priv)) + if (GT_GEN(dev_priv, 5)) engine->irq_enable_mask = ILK_BSD_USER_INTERRUPT; else engine->irq_enable_mask = I915_BSD_USER_INTERRUPT; diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h index 8a2270b209b0..e6b24cbf3b04 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.h +++ b/drivers/gpu/drm/i915/intel_ringbuffer.h @@ -93,11 +93,11 @@ hangcheck_action_to_str(const enum intel_engine_hangcheck_action a) #define I915_MAX_SUBSLICES 8 #define instdone_slice_mask(dev_priv__) \ - (IS_GEN7(dev_priv__) ? \ + (GT_GEN(dev_priv__, 7) ? \ 1 : INTEL_INFO(dev_priv__)->sseu.slice_mask) #define instdone_subslice_mask(dev_priv__) \ - (IS_GEN7(dev_priv__) ? \ + (GT_GEN(dev_priv__, 7) ? \ 1 : INTEL_INFO(dev_priv__)->sseu.subslice_mask[0]) #define for_each_instdone_slice_subslice(dev_priv__, slice__, subslice__) \ diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c index 6c453366cd24..b164a2c4b058 100644 --- a/drivers/gpu/drm/i915/intel_runtime_pm.c +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c @@ -3027,7 +3027,7 @@ static uint32_t get_allowed_dc_mask(const struct drm_i915_private *dev_priv, * suspend/resume, so allow it unconditionally. */ mask = DC_STATE_EN_DC9; - } else if (IS_GEN10(dev_priv) || IS_GEN9_BC(dev_priv)) { + } else if (GT_GEN(dev_priv, 10) || IS_GEN9_BC(dev_priv)) { max_dc = 2; mask = 0; } else if (IS_GEN9_LP(dev_priv)) { diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c index f15b27983fbf..049e679e4145 100644 --- a/drivers/gpu/drm/i915/intel_sprite.c +++ b/drivers/gpu/drm/i915/intel_sprite.c @@ -1083,7 +1083,7 @@ static u32 g4x_sprite_ctl(const struct intel_crtc_state *crtc_state, dvscntr = DVS_ENABLE | DVS_GAMMA_ENABLE; - if (IS_GEN6(dev_priv)) + if (GT_GEN(dev_priv, 6)) dvscntr |= DVS_TRICKLE_FEED_DISABLE; switch (fb->format->format) { @@ -1979,7 +1979,7 @@ static bool skl_plane_has_planar(struct drm_i915_private *dev_priv, if (IS_SKYLAKE(dev_priv) || IS_BROXTON(dev_priv)) return false; - if (IS_GEN9(dev_priv) && !IS_GEMINILAKE(dev_priv) && pipe == PIPE_C) + if (GT_GEN(dev_priv, 9) && !IS_GEMINILAKE(dev_priv) && pipe == PIPE_C) return false; if (plane_id != PLANE_PRIMARY && plane_id != PLANE_SPRITE0) @@ -2188,7 +2188,7 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv, plane->check_plane = g4x_sprite_check; modifiers = i9xx_plane_format_modifiers; - if (IS_GEN6(dev_priv)) { + if (GT_GEN(dev_priv, 6)) { formats = snb_plane_formats; num_formats = ARRAY_SIZE(snb_plane_formats); diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c index b34c318b238d..9eca84e7baa5 100644 --- a/drivers/gpu/drm/i915/intel_uc.c +++ b/drivers/gpu/drm/i915/intel_uc.c @@ -354,7 +354,7 @@ int intel_uc_init_hw(struct drm_i915_private *i915) /* WaEnableuKernelHeaderValidFix:skl */ /* WaEnableGuCBootHashCheckNotSet:skl,bxt,kbl */ - if (IS_GEN9(i915)) + if (GT_GEN(i915, 9)) attempts = 3; else attempts = 1; diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c index 4ffe26cc3c3f..2e98416467a0 100644 --- a/drivers/gpu/drm/i915/intel_uncore.c +++ b/drivers/gpu/drm/i915/intel_uncore.c @@ -528,7 +528,7 @@ check_for_unclaimed_mmio(struct drm_i915_private *dev_priv) if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) ret |= vlv_check_for_unclaimed_mmio(dev_priv); - if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv)) + if (GT_GEN(dev_priv, 6) || GT_GEN(dev_priv, 7)) ret |= gen6_check_for_fifo_debug(dev_priv); return ret; @@ -556,7 +556,7 @@ static void __intel_uncore_early_sanitize(struct drm_i915_private *dev_priv, dev_priv->uncore.funcs.force_wake_get(dev_priv, restore_forcewake); - if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv)) + if (GT_GEN(dev_priv, 6) || GT_GEN(dev_priv, 7)) dev_priv->uncore.fifo_count = fifo_free_entries(dev_priv); spin_unlock_irq(&dev_priv->uncore.lock); @@ -1398,7 +1398,7 @@ static void intel_uncore_fw_domains_init(struct drm_i915_private *dev_priv) if (INTEL_GEN(dev_priv) <= 5 || intel_vgpu_active(dev_priv)) return; - if (IS_GEN6(dev_priv)) { + if (GT_GEN(dev_priv, 6)) { dev_priv->uncore.fw_reset = 0; dev_priv->uncore.fw_set = FORCEWAKE_KERNEL; dev_priv->uncore.fw_clear = 0; @@ -1437,7 +1437,7 @@ static void intel_uncore_fw_domains_init(struct drm_i915_private *dev_priv) FORCEWAKE_MEDIA_VEBOX_GEN11(i), FORCEWAKE_ACK_MEDIA_VEBOX_GEN11(i)); } - } else if (IS_GEN10(dev_priv) || IS_GEN9(dev_priv)) { + } else if (GT_GEN(dev_priv, 10) || GT_GEN(dev_priv, 9)) { dev_priv->uncore.funcs.force_wake_get = fw_domains_get_with_fallback; dev_priv->uncore.funcs.force_wake_put = fw_domains_put; @@ -1503,7 +1503,7 @@ static void intel_uncore_fw_domains_init(struct drm_i915_private *dev_priv) fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER, FORCEWAKE, FORCEWAKE_ACK); } - } else if (IS_GEN6(dev_priv)) { + } else if (GT_GEN(dev_priv, 6)) { dev_priv->uncore.funcs.force_wake_get = fw_domains_get_with_thread_status; dev_priv->uncore.funcs.force_wake_put = fw_domains_put; @@ -1570,7 +1570,7 @@ void intel_uncore_init(struct drm_i915_private *dev_priv) if (GT_GEN_RANGE(dev_priv, 2, 4) || intel_vgpu_active(dev_priv)) { ASSIGN_WRITE_MMIO_VFUNCS(dev_priv, gen2); ASSIGN_READ_MMIO_VFUNCS(dev_priv, gen2); - } else if (IS_GEN5(dev_priv)) { + } else if (GT_GEN(dev_priv, 5)) { ASSIGN_WRITE_MMIO_VFUNCS(dev_priv, gen5); ASSIGN_READ_MMIO_VFUNCS(dev_priv, gen5); } else if (GT_GEN_RANGE(dev_priv, 6, 7)) { @@ -1582,7 +1582,7 @@ void intel_uncore_init(struct drm_i915_private *dev_priv) } else { ASSIGN_READ_MMIO_VFUNCS(dev_priv, gen6); } - } else if (IS_GEN8(dev_priv)) { + } else if (GT_GEN(dev_priv, 8)) { if (IS_CHERRYVIEW(dev_priv)) { ASSIGN_FW_DOMAINS_TABLE(__chv_fw_ranges); ASSIGN_WRITE_MMIO_VFUNCS(dev_priv, fwtable); @@ -2173,7 +2173,7 @@ static reset_func intel_get_gpu_reset(struct drm_i915_private *dev_priv) return gen8_reset_engines; else if (INTEL_GEN(dev_priv) >= 6) return gen6_reset_engines; - else if (IS_GEN5(dev_priv)) + else if (GT_GEN(dev_priv, 5)) return ironlake_do_reset; else if (IS_G4X(dev_priv)) return g4x_do_reset; @@ -2341,7 +2341,7 @@ intel_uncore_forcewake_for_write(struct drm_i915_private *dev_priv, fw_domains = __gen11_fwtable_reg_write_fw_domains(offset); } else if (HAS_FWTABLE(dev_priv) && !IS_VALLEYVIEW(dev_priv)) { fw_domains = __fwtable_reg_write_fw_domains(offset); - } else if (IS_GEN8(dev_priv)) { + } else if (GT_GEN(dev_priv, 8)) { fw_domains = __gen8_reg_write_fw_domains(offset); } else if (GT_GEN_RANGE(dev_priv, 6, 7)) { fw_domains = FORCEWAKE_RENDER; diff --git a/drivers/gpu/drm/i915/intel_wopcm.c b/drivers/gpu/drm/i915/intel_wopcm.c index 92cb82dd0c07..3987207cddd0 100644 --- a/drivers/gpu/drm/i915/intel_wopcm.c +++ b/drivers/gpu/drm/i915/intel_wopcm.c @@ -130,11 +130,11 @@ static inline int check_hw_restriction(struct drm_i915_private *i915, { int err = 0; - if (IS_GEN9(i915)) + if (GT_GEN(i915, 9)) err = gen9_check_dword_gap(guc_wopcm_base, guc_wopcm_size); if (!err && - (IS_GEN9(i915) || IS_CNL_REVID(i915, CNL_REVID_A0, CNL_REVID_A0))) + (GT_GEN(i915, 9) || IS_CNL_REVID(i915, CNL_REVID_A0, CNL_REVID_A0))) err = gen9_check_huc_fw_fits(guc_wopcm_size, huc_fw_size); return err; -- 2.19.1.1.g56c4683e68 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 38+ messages in thread
* Re: [PATCH v2 3/7] drm/i915: replace IS_GEN<N> with GT_GEN(..., N) 2018-11-06 21:51 ` [PATCH v2 3/7] drm/i915: replace IS_GEN<N> with GT_GEN(..., N) Lucas De Marchi @ 2018-11-21 22:20 ` Rodrigo Vivi 2018-11-23 12:42 ` Jani Nikula 0 siblings, 1 reply; 38+ messages in thread From: Rodrigo Vivi @ 2018-11-21 22:20 UTC (permalink / raw) To: Lucas De Marchi; +Cc: intel-gfx On Tue, Nov 06, 2018 at 01:51:19PM -0800, Lucas De Marchi wrote: > Define GT_GEN() similarly to our GT_GEN_RANGE() and convert users of > IS_GEN<N> to pss the gen as parameter. This prepares for the addition > of display gen checks by renaming the IS_GENx() and using common code > for all the n gens. > > The following spatch was used to convert the users of these macros: > > @@ > expression e; > @@ > ( > - IS_GEN2(e) > + GT_GEN(e, 2) > | > - IS_GEN3(e) > + GT_GEN(e, 3) > | > - IS_GEN4(e) > + GT_GEN(e, 4) > | > - IS_GEN5(e) > + GT_GEN(e, 5) > | > - IS_GEN6(e) > + GT_GEN(e, 6) > | > - IS_GEN7(e) > + GT_GEN(e, 7) > | > - IS_GEN8(e) > + GT_GEN(e, 8) > | > - IS_GEN9(e) > + GT_GEN(e, 9) > | > - IS_GEN10(e) > + GT_GEN(e, 10) > | > - IS_GEN11(e) > + GT_GEN(e, 11) > ) > > Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> > --- > drivers/gpu/drm/i915/gvt/vgpu.c | 4 +- > drivers/gpu/drm/i915/i915_cmd_parser.c | 2 +- > drivers/gpu/drm/i915/i915_debugfs.c | 16 ++--- > drivers/gpu/drm/i915/i915_drv.c | 18 +++--- > drivers/gpu/drm/i915/i915_drv.h | 29 +++------ > drivers/gpu/drm/i915/i915_gem.c | 12 ++-- > drivers/gpu/drm/i915/i915_gem_context.c | 2 +- > drivers/gpu/drm/i915/i915_gem_execbuffer.c | 4 +- > drivers/gpu/drm/i915/i915_gem_fence_reg.c | 10 +-- > drivers/gpu/drm/i915/i915_gem_gtt.c | 6 +- > drivers/gpu/drm/i915/i915_gem_stolen.c | 7 +- > drivers/gpu/drm/i915/i915_gem_tiling.c | 4 +- > drivers/gpu/drm/i915/i915_gpu_error.c | 18 +++--- > drivers/gpu/drm/i915/i915_irq.c | 24 +++---- > drivers/gpu/drm/i915/i915_perf.c | 4 +- > drivers/gpu/drm/i915/i915_suspend.c | 12 ++-- > drivers/gpu/drm/i915/intel_atomic.c | 2 +- > drivers/gpu/drm/i915/intel_audio.c | 2 +- > drivers/gpu/drm/i915/intel_cdclk.c | 10 +-- > drivers/gpu/drm/i915/intel_crt.c | 6 +- > drivers/gpu/drm/i915/intel_device_info.c | 16 ++--- > drivers/gpu/drm/i915/intel_display.c | 74 +++++++++++----------- > drivers/gpu/drm/i915/intel_dp.c | 24 +++---- > drivers/gpu/drm/i915/intel_engine_cs.c | 4 +- > drivers/gpu/drm/i915/intel_fbc.c | 22 +++---- > drivers/gpu/drm/i915/intel_fifo_underrun.c | 6 +- > drivers/gpu/drm/i915/intel_guc_fw.c | 2 +- > drivers/gpu/drm/i915/intel_hangcheck.c | 2 +- > drivers/gpu/drm/i915/intel_lrc.c | 4 +- > drivers/gpu/drm/i915/intel_lvds.c | 4 +- > drivers/gpu/drm/i915/intel_mocs.c | 2 +- > drivers/gpu/drm/i915/intel_overlay.c | 10 +-- > drivers/gpu/drm/i915/intel_panel.c | 8 +-- > drivers/gpu/drm/i915/intel_pipe_crc.c | 8 +-- > drivers/gpu/drm/i915/intel_pm.c | 60 +++++++++--------- > drivers/gpu/drm/i915/intel_psr.c | 4 +- > drivers/gpu/drm/i915/intel_ringbuffer.c | 28 ++++---- > drivers/gpu/drm/i915/intel_ringbuffer.h | 4 +- > drivers/gpu/drm/i915/intel_runtime_pm.c | 2 +- > drivers/gpu/drm/i915/intel_sprite.c | 6 +- > drivers/gpu/drm/i915/intel_uc.c | 2 +- > drivers/gpu/drm/i915/intel_uncore.c | 18 +++--- > drivers/gpu/drm/i915/intel_wopcm.c | 4 +- > 43 files changed, 247 insertions(+), 259 deletions(-) > > diff --git a/drivers/gpu/drm/i915/gvt/vgpu.c b/drivers/gpu/drm/i915/gvt/vgpu.c > index c628be05fbfe..ea45b22814a1 100644 > --- a/drivers/gpu/drm/i915/gvt/vgpu.c > +++ b/drivers/gpu/drm/i915/gvt/vgpu.c > @@ -148,10 +148,10 @@ int intel_gvt_init_vgpu_types(struct intel_gvt *gvt) > gvt->types[i].avail_instance = min(low_avail / vgpu_types[i].low_mm, > high_avail / vgpu_types[i].high_mm); > > - if (IS_GEN8(gvt->dev_priv)) > + if (GT_GEN(gvt->dev_priv, 8)) > sprintf(gvt->types[i].name, "GVTg_V4_%s", > vgpu_types[i].name); > - else if (IS_GEN9(gvt->dev_priv)) > + else if (GT_GEN(gvt->dev_priv, 9)) > sprintf(gvt->types[i].name, "GVTg_V5_%s", > vgpu_types[i].name); > > diff --git a/drivers/gpu/drm/i915/i915_cmd_parser.c b/drivers/gpu/drm/i915/i915_cmd_parser.c > index 95478db9998b..2be8c22641b6 100644 > --- a/drivers/gpu/drm/i915/i915_cmd_parser.c > +++ b/drivers/gpu/drm/i915/i915_cmd_parser.c > @@ -865,7 +865,7 @@ void intel_engine_init_cmd_parser(struct intel_engine_cs *engine) > int cmd_table_count; > int ret; > > - if (!IS_GEN7(engine->i915)) > + if (!GT_GEN(engine->i915, 7)) > return; > > switch (engine->id) { > diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c > index f60485906f7e..2514ec4d97d4 100644 > --- a/drivers/gpu/drm/i915/i915_debugfs.c > +++ b/drivers/gpu/drm/i915/i915_debugfs.c > @@ -1064,7 +1064,7 @@ static int i915_frequency_info(struct seq_file *m, void *unused) > > intel_runtime_pm_get(dev_priv); > > - if (IS_GEN5(dev_priv)) { > + if (GT_GEN(dev_priv, 5)) { > u16 rgvswctl = I915_READ16(MEMSWCTL); > u16 rgvstat = I915_READ16(MEMSTAT_ILK); > > @@ -1785,7 +1785,7 @@ static int i915_emon_status(struct seq_file *m, void *unused) > unsigned long temp, chipset, gfx; > int ret; > > - if (!IS_GEN5(dev_priv)) > + if (!GT_GEN(dev_priv, 5)) > return -ENODEV; > > ret = mutex_lock_interruptible(&dev->struct_mutex); > @@ -2030,7 +2030,7 @@ static int i915_swizzle_info(struct seq_file *m, void *data) > seq_printf(m, "bit6 swizzle for Y-tiling = %s\n", > swizzle_string(dev_priv->mm.bit_6_swizzle_y)); > > - if (IS_GEN3(dev_priv) || IS_GEN4(dev_priv)) { > + if (GT_GEN(dev_priv, 3) || GT_GEN(dev_priv, 4)) { > seq_printf(m, "DDC = 0x%08x\n", > I915_READ(DCC)); > seq_printf(m, "DDC2 = 0x%08x\n", > @@ -2115,12 +2115,12 @@ static void gen6_ppgtt_info(struct seq_file *m, > struct intel_engine_cs *engine; > enum intel_engine_id id; > > - if (IS_GEN6(dev_priv)) > + if (GT_GEN(dev_priv, 6)) > seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE)); > > for_each_engine(engine, dev_priv, id) { > seq_printf(m, "%s\n", engine->name); > - if (IS_GEN7(dev_priv)) > + if (GT_GEN(dev_priv, 7)) > seq_printf(m, "GFX_MODE: 0x%08x\n", > I915_READ(RING_MODE_GEN7(engine))); > seq_printf(m, "PP_DIR_BASE: 0x%08x\n", > @@ -4261,7 +4261,7 @@ i915_cache_sharing_get(void *data, u64 *val) > struct drm_i915_private *dev_priv = data; > u32 snpcr; > > - if (!(IS_GEN6(dev_priv) || IS_GEN7(dev_priv))) > + if (!(GT_GEN(dev_priv, 6) || GT_GEN(dev_priv, 7))) > return -ENODEV; > > intel_runtime_pm_get(dev_priv); > @@ -4281,7 +4281,7 @@ i915_cache_sharing_set(void *data, u64 val) > struct drm_i915_private *dev_priv = data; > u32 snpcr; > > - if (!(IS_GEN6(dev_priv) || IS_GEN7(dev_priv))) > + if (!(GT_GEN(dev_priv, 6) || GT_GEN(dev_priv, 7))) > return -ENODEV; > > if (val > 3) > @@ -4538,7 +4538,7 @@ static int i915_sseu_status(struct seq_file *m, void *unused) > cherryview_sseu_device_status(dev_priv, &sseu); > } else if (IS_BROADWELL(dev_priv)) { > broadwell_sseu_device_status(dev_priv, &sseu); > - } else if (IS_GEN9(dev_priv)) { > + } else if (GT_GEN(dev_priv, 9)) { > gen9_sseu_device_status(dev_priv, &sseu); > } else if (INTEL_GEN(dev_priv) >= 10) { > gen10_sseu_device_status(dev_priv, &sseu); > diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c > index acb516308262..d2bdd7112c5d 100644 > --- a/drivers/gpu/drm/i915/i915_drv.c > +++ b/drivers/gpu/drm/i915/i915_drv.c > @@ -131,15 +131,15 @@ intel_pch_type(const struct drm_i915_private *dev_priv, unsigned short id) > switch (id) { > case INTEL_PCH_IBX_DEVICE_ID_TYPE: > DRM_DEBUG_KMS("Found Ibex Peak PCH\n"); > - WARN_ON(!IS_GEN5(dev_priv)); > + WARN_ON(!GT_GEN(dev_priv, 5)); > return PCH_IBX; > case INTEL_PCH_CPT_DEVICE_ID_TYPE: > DRM_DEBUG_KMS("Found CougarPoint PCH\n"); > - WARN_ON(!IS_GEN6(dev_priv) && !IS_IVYBRIDGE(dev_priv)); > + WARN_ON(!GT_GEN(dev_priv, 6) && !IS_IVYBRIDGE(dev_priv)); > return PCH_CPT; > case INTEL_PCH_PPT_DEVICE_ID_TYPE: > DRM_DEBUG_KMS("Found PantherPoint PCH\n"); > - WARN_ON(!IS_GEN6(dev_priv) && !IS_IVYBRIDGE(dev_priv)); > + WARN_ON(!GT_GEN(dev_priv, 6) && !IS_IVYBRIDGE(dev_priv)); > /* PantherPoint is CPT compatible */ > return PCH_CPT; > case INTEL_PCH_LPT_DEVICE_ID_TYPE: > @@ -216,9 +216,9 @@ intel_virt_detect_pch(const struct drm_i915_private *dev_priv) > * make an educated guess as to which PCH is really there. > */ > > - if (IS_GEN5(dev_priv)) > + if (GT_GEN(dev_priv, 5)) > id = INTEL_PCH_IBX_DEVICE_ID_TYPE; > - else if (IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv)) > + else if (GT_GEN(dev_priv, 6) || IS_IVYBRIDGE(dev_priv)) > id = INTEL_PCH_CPT_DEVICE_ID_TYPE; > else if (IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv)) > id = INTEL_PCH_LPT_LP_DEVICE_ID_TYPE; > @@ -955,7 +955,7 @@ static int i915_mmio_setup(struct drm_i915_private *dev_priv) > int mmio_bar; > int mmio_size; > > - mmio_bar = IS_GEN2(dev_priv) ? 1 : 0; > + mmio_bar = GT_GEN(dev_priv, 2) ? 1 : 0; > /* > * Before gen4, the registers and the GTT are behind different BARs. > * However, from gen4 onwards, the registers and the GTT are shared > @@ -1330,7 +1330,7 @@ intel_get_dram_info(struct drm_i915_private *dev_priv) > /* Need to calculate bandwidth only for Gen9 */ > if (IS_BROXTON(dev_priv)) > ret = bxt_get_dram_info(dev_priv); > - else if (IS_GEN9(dev_priv)) > + else if (GT_GEN(dev_priv, 9)) > ret = skl_get_dram_info(dev_priv); > else > ret = skl_dram_get_channels_info(dev_priv); > @@ -1411,7 +1411,7 @@ static int i915_driver_init_hw(struct drm_i915_private *dev_priv) > pci_set_master(pdev); > > /* overlay on gen2 is broken and can't address above 1G */ > - if (IS_GEN2(dev_priv)) { > + if (GT_GEN(dev_priv, 2)) { > ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(30)); > if (ret) { > DRM_ERROR("failed to set DMA mask\n"); > @@ -1548,7 +1548,7 @@ static void i915_driver_register(struct drm_i915_private *dev_priv) > acpi_video_register(); > } > > - if (IS_GEN5(dev_priv)) > + if (GT_GEN(dev_priv, 5)) > intel_gpu_ips_init(dev_priv); > > intel_audio_init(dev_priv); > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h > index e4749e93a1f9..f11aad5cd7fb 100644 > --- a/drivers/gpu/drm/i915/i915_drv.h > +++ b/drivers/gpu/drm/i915/i915_drv.h > @@ -2377,6 +2377,10 @@ intel_info(const struct drm_i915_private *dev_priv) > #define GT_GEN_RANGE(dev_priv, s, e) \ > (!!((dev_priv)->info.gen_mask & INTEL_GEN_MASK((s), (e)))) > > +#define GT_GEN(dev_priv, n) \ > + (BUILD_BUG_ON_ZERO(!__builtin_constant_p(n)) + \ > + (!!((dev_priv)->info.gen_mask & BIT((n) - 1)))) > + > /* > * Return true if revision is in range [since,until] inclusive. > * > @@ -2528,26 +2532,9 @@ intel_info(const struct drm_i915_private *dev_priv) > #define IS_ICL_REVID(p, since, until) \ > (IS_ICELAKE(p) && IS_REVID(p, since, until)) > > -/* > - * The genX designation typically refers to the render engine, so render > - * capability related checks should use IS_GEN, while display and other checks > - * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular > - * chips, etc.). > - */ > -#define IS_GEN2(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(1))) > -#define IS_GEN3(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(2))) > -#define IS_GEN4(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(3))) > -#define IS_GEN5(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(4))) > -#define IS_GEN6(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(5))) > -#define IS_GEN7(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(6))) > -#define IS_GEN8(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(7))) > -#define IS_GEN9(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(8))) > -#define IS_GEN10(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(9))) > -#define IS_GEN11(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(10))) > - > #define IS_LP(dev_priv) (INTEL_INFO(dev_priv)->is_lp) > -#define IS_GEN9_LP(dev_priv) (IS_GEN9(dev_priv) && IS_LP(dev_priv)) > -#define IS_GEN9_BC(dev_priv) (IS_GEN9(dev_priv) && !IS_LP(dev_priv)) > +#define IS_GEN9_LP(dev_priv) (GT_GEN(dev_priv, 9) && IS_LP(dev_priv)) > +#define IS_GEN9_BC(dev_priv) (GT_GEN(dev_priv, 9) && !IS_LP(dev_priv)) > > #define ENGINE_MASK(id) BIT(id) > #define RENDER_RING ENGINE_MASK(RCS) > @@ -2568,7 +2555,7 @@ intel_info(const struct drm_i915_private *dev_priv) > #define HAS_BLT(dev_priv) HAS_ENGINE(dev_priv, BCS) > #define HAS_VEBOX(dev_priv) HAS_ENGINE(dev_priv, VECS) > > -#define HAS_LEGACY_SEMAPHORES(dev_priv) IS_GEN7(dev_priv) > +#define HAS_LEGACY_SEMAPHORES(dev_priv) GT_GEN(dev_priv, 7) > > #define HAS_LLC(dev_priv) ((dev_priv)->info.has_llc) > #define HAS_SNOOP(dev_priv) ((dev_priv)->info.has_snoop) > @@ -2620,7 +2607,7 @@ intel_info(const struct drm_i915_private *dev_priv) > /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte > * rows, which changed the alignment requirements and fence programming. > */ > -#define HAS_128_BYTE_Y_TILING(dev_priv) (!IS_GEN2(dev_priv) && \ > +#define HAS_128_BYTE_Y_TILING(dev_priv) (!GT_GEN(dev_priv, 2) && \ > !(IS_I915G(dev_priv) || \ > IS_I915GM(dev_priv))) > #define SUPPORTS_TV(dev_priv) ((dev_priv)->info.supports_tv) > diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c > index a120112d0621..d50955f7fe3f 100644 > --- a/drivers/gpu/drm/i915/i915_gem.c > +++ b/drivers/gpu/drm/i915/i915_gem.c > @@ -5223,15 +5223,15 @@ void i915_gem_init_swizzling(struct drm_i915_private *dev_priv) > I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) | > DISP_TILE_SURFACE_SWIZZLING); > > - if (IS_GEN5(dev_priv)) > + if (GT_GEN(dev_priv, 5)) > return; > > I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL); > - if (IS_GEN6(dev_priv)) > + if (GT_GEN(dev_priv, 6)) > I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB)); > - else if (IS_GEN7(dev_priv)) > + else if (GT_GEN(dev_priv, 7)) > I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB)); > - else if (IS_GEN8(dev_priv)) > + else if (GT_GEN(dev_priv, 8)) > I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW)); > else > BUG(); > @@ -5253,10 +5253,10 @@ static void init_unused_rings(struct drm_i915_private *dev_priv) > init_unused_ring(dev_priv, SRB1_BASE); > init_unused_ring(dev_priv, SRB2_BASE); > init_unused_ring(dev_priv, SRB3_BASE); > - } else if (IS_GEN2(dev_priv)) { > + } else if (GT_GEN(dev_priv, 2)) { > init_unused_ring(dev_priv, SRB0_BASE); > init_unused_ring(dev_priv, SRB1_BASE); > - } else if (IS_GEN3(dev_priv)) { > + } else if (GT_GEN(dev_priv, 3)) { > init_unused_ring(dev_priv, PRB1_BASE); > init_unused_ring(dev_priv, PRB2_BASE); > } > diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c > index b97963db0287..031a2a358f19 100644 > --- a/drivers/gpu/drm/i915/i915_gem_context.c > +++ b/drivers/gpu/drm/i915/i915_gem_context.c > @@ -311,7 +311,7 @@ static u32 default_desc_template(const struct drm_i915_private *i915, > address_mode = INTEL_LEGACY_64B_CONTEXT; > desc |= address_mode << GEN8_CTX_ADDRESSING_MODE_SHIFT; > > - if (IS_GEN8(i915)) > + if (GT_GEN(i915, 8)) > desc |= GEN8_CTX_L3LLC_COHERENT; > > /* TODO: WaDisableLiteRestore when we start using semaphore > diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c > index 1a1c04db6c80..f1df4114305a 100644 > --- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c > +++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c > @@ -1380,7 +1380,7 @@ eb_relocate_entry(struct i915_execbuffer *eb, > * batchbuffers. > */ > if (reloc->write_domain == I915_GEM_DOMAIN_INSTRUCTION && > - IS_GEN6(eb->i915)) { > + GT_GEN(eb->i915, 6)) { > err = i915_vma_bind(target, target->obj->cache_level, > PIN_GLOBAL); > if (WARN_ONCE(err, > @@ -1893,7 +1893,7 @@ static int i915_reset_gen7_sol_offsets(struct i915_request *rq) > u32 *cs; > int i; > > - if (!IS_GEN7(rq->i915) || rq->engine->id != RCS) { > + if (!GT_GEN(rq->i915, 7) || rq->engine->id != RCS) { > DRM_DEBUG("sol reset is gen7/rcs only\n"); > return -EINVAL; > } > diff --git a/drivers/gpu/drm/i915/i915_gem_fence_reg.c b/drivers/gpu/drm/i915/i915_gem_fence_reg.c > index d548ac05ccd7..caafbf7e62a4 100644 > --- a/drivers/gpu/drm/i915/i915_gem_fence_reg.c > +++ b/drivers/gpu/drm/i915/i915_gem_fence_reg.c > @@ -193,9 +193,9 @@ static void fence_write(struct drm_i915_fence_reg *fence, > * and explicitly managed for internal users. > */ > > - if (IS_GEN2(fence->i915)) > + if (GT_GEN(fence->i915, 2)) > i830_write_fence_reg(fence, vma); > - else if (IS_GEN3(fence->i915)) > + else if (GT_GEN(fence->i915, 3)) > i915_write_fence_reg(fence, vma); > else > i965_write_fence_reg(fence, vma); > @@ -596,13 +596,13 @@ i915_gem_detect_bit_6_swizzle(struct drm_i915_private *dev_priv) > swizzle_y = I915_BIT_6_SWIZZLE_NONE; > } > } > - } else if (IS_GEN5(dev_priv)) { > + } else if (GT_GEN(dev_priv, 5)) { > /* On Ironlake whatever DRAM config, GPU always do > * same swizzling setup. > */ > swizzle_x = I915_BIT_6_SWIZZLE_9_10; > swizzle_y = I915_BIT_6_SWIZZLE_9; > - } else if (IS_GEN2(dev_priv)) { > + } else if (GT_GEN(dev_priv, 2)) { > /* As far as we know, the 865 doesn't have these bit 6 > * swizzling issues. > */ > @@ -647,7 +647,7 @@ i915_gem_detect_bit_6_swizzle(struct drm_i915_private *dev_priv) > } > > /* check for L-shaped memory aka modified enhanced addressing */ > - if (IS_GEN4(dev_priv) && > + if (GT_GEN(dev_priv, 4) && > !(I915_READ(DCC2) & DCC2_MODIFIED_ENHANCED_DISABLE)) { > swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN; > swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN; > diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c > index a98c29147d5e..1723f374c5a8 100644 > --- a/drivers/gpu/drm/i915/i915_gem_gtt.c > +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c > @@ -2195,9 +2195,9 @@ int i915_ppgtt_init_hw(struct drm_i915_private *dev_priv) > { > gtt_write_workarounds(dev_priv); > > - if (IS_GEN6(dev_priv)) > + if (GT_GEN(dev_priv, 6)) > gen6_ppgtt_enable(dev_priv); > - else if (IS_GEN7(dev_priv)) > + else if (GT_GEN(dev_priv, 7)) > gen7_ppgtt_enable(dev_priv); > > return 0; > @@ -2279,7 +2279,7 @@ static bool needs_idle_maps(struct drm_i915_private *dev_priv) > /* Query intel_iommu to see if we need the workaround. Presumably that > * was loaded first. > */ > - return IS_GEN5(dev_priv) && IS_MOBILE(dev_priv) && intel_vtd_active(); > + return GT_GEN(dev_priv, 5) && IS_MOBILE(dev_priv) && intel_vtd_active(); > } > > static void gen6_check_faults(struct drm_i915_private *dev_priv) > diff --git a/drivers/gpu/drm/i915/i915_gem_stolen.c b/drivers/gpu/drm/i915/i915_gem_stolen.c > index f29a7ff7c362..d01dea84ffae 100644 > --- a/drivers/gpu/drm/i915/i915_gem_stolen.c > +++ b/drivers/gpu/drm/i915/i915_gem_stolen.c > @@ -102,7 +102,7 @@ static int i915_adjust_stolen(struct drm_i915_private *dev_priv, > resource_size_t ggtt_start; > > ggtt_start = I915_READ(PGTBL_CTL); > - if (IS_GEN4(dev_priv)) > + if (GT_GEN(dev_priv, 4)) > ggtt_start = (ggtt_start & PGTBL_ADDRESS_LO_MASK) | > (ggtt_start & PGTBL_ADDRESS_HI_MASK) << 28; > else > @@ -156,7 +156,7 @@ static int i915_adjust_stolen(struct drm_i915_private *dev_priv, > * GEN3 firmware likes to smash pci bridges into the stolen > * range. Apparently this works. > */ > - if (r == NULL && !IS_GEN3(dev_priv)) { > + if (r == NULL && !GT_GEN(dev_priv, 3)) { > DRM_ERROR("conflict detected with stolen region: %pR\n", > dsm); > > @@ -194,7 +194,8 @@ static void g4x_get_stolen_reserved(struct drm_i915_private *dev_priv, > * Whether ILK really reuses the ELK register for this is unclear. > * Let's see if we catch anyone with this supposedly enabled on ILK. > */ > - WARN(IS_GEN5(dev_priv), "ILK stolen reserved found? 0x%08x\n", reg_val); > + WARN(GT_GEN(dev_priv, 5), "ILK stolen reserved found? 0x%08x\n", > + reg_val); > > if (!(reg_val & G4X_STOLEN_RESERVED_ADDR2_MASK)) > return; > diff --git a/drivers/gpu/drm/i915/i915_gem_tiling.c b/drivers/gpu/drm/i915/i915_gem_tiling.c > index d9dc9df523b5..8a1976c523b0 100644 > --- a/drivers/gpu/drm/i915/i915_gem_tiling.c > +++ b/drivers/gpu/drm/i915/i915_gem_tiling.c > @@ -87,7 +87,7 @@ u32 i915_gem_fence_size(struct drm_i915_private *i915, > } > > /* Previous chips need a power-of-two fence region when tiling */ > - if (IS_GEN3(i915)) > + if (GT_GEN(i915, 3)) > ggtt_size = 1024*1024; > else > ggtt_size = 512*1024; > @@ -162,7 +162,7 @@ i915_tiling_ok(struct drm_i915_gem_object *obj, > return false; > } > > - if (IS_GEN2(i915) || > + if (GT_GEN(i915, 2) || > (tiling == I915_TILING_Y && HAS_128_BYTE_Y_TILING(i915))) > tile_width = 128; > else > diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c > index c8d8f79688a8..c7b492b6cf4e 100644 > --- a/drivers/gpu/drm/i915/i915_gpu_error.c > +++ b/drivers/gpu/drm/i915/i915_gpu_error.c > @@ -720,7 +720,7 @@ int i915_error_state_to_str(struct drm_i915_error_state_buf *m, > err_printf(m, "DONE_REG: 0x%08x\n", error->done_reg); > } > > - if (IS_GEN7(dev_priv)) > + if (GT_GEN(dev_priv, 7)) > err_printf(m, "ERR_INT: 0x%08x\n", error->err_int); > > for (i = 0; i < ARRAY_SIZE(error->engine); i++) { > @@ -1234,7 +1234,7 @@ static void error_record_engine_registers(struct i915_gpu_state *error, > if (!HWS_NEEDS_PHYSICAL(dev_priv)) { > i915_reg_t mmio; > > - if (IS_GEN7(dev_priv)) { > + if (GT_GEN(dev_priv, 7)) { > switch (engine->id) { > default: > case RCS: > @@ -1250,7 +1250,7 @@ static void error_record_engine_registers(struct i915_gpu_state *error, > mmio = VEBOX_HWS_PGA_GEN7; > break; > } > - } else if (IS_GEN6(engine->i915)) { > + } else if (GT_GEN(engine->i915, 6)) { > mmio = RING_HWS_PGA_GEN6(engine->mmio_base); > } else { > /* XXX: gen8 returns to sanity */ > @@ -1272,10 +1272,10 @@ static void error_record_engine_registers(struct i915_gpu_state *error, > > ee->vm_info.gfx_mode = I915_READ(RING_MODE_GEN7(engine)); > > - if (IS_GEN6(dev_priv)) > + if (GT_GEN(dev_priv, 6)) > ee->vm_info.pp_dir_base = > I915_READ(RING_PP_DIR_BASE_READ(engine)); > - else if (IS_GEN7(dev_priv)) > + else if (GT_GEN(dev_priv, 7)) > ee->vm_info.pp_dir_base = > I915_READ(RING_PP_DIR_BASE(engine)); > else if (INTEL_GEN(dev_priv) >= 8) > @@ -1645,7 +1645,7 @@ static void capture_reg_state(struct i915_gpu_state *error) > error->forcewake = I915_READ_FW(FORCEWAKE_VLV); > } > > - if (IS_GEN7(dev_priv)) > + if (GT_GEN(dev_priv, 7)) > error->err_int = I915_READ(GEN7_ERR_INT); > > if (INTEL_GEN(dev_priv) >= 8) { > @@ -1653,7 +1653,7 @@ static void capture_reg_state(struct i915_gpu_state *error) > error->fault_data1 = I915_READ(GEN8_FAULT_TLB_DATA1); > } > > - if (IS_GEN6(dev_priv)) { > + if (GT_GEN(dev_priv, 6)) { > error->forcewake = I915_READ_FW(FORCEWAKE); > error->gab_ctl = I915_READ(GAB_CTL); > error->gfx_mode = I915_READ(GFX_MODE); > @@ -1673,7 +1673,7 @@ static void capture_reg_state(struct i915_gpu_state *error) > error->ccid = I915_READ(CCID); > > /* 3: Feature specific registers */ > - if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv)) { > + if (GT_GEN(dev_priv, 6) || GT_GEN(dev_priv, 7)) { > error->gam_ecochk = I915_READ(GAM_ECOCHK); > error->gac_eco = I915_READ(GAC_ECO_BITS); > } > @@ -1697,7 +1697,7 @@ static void capture_reg_state(struct i915_gpu_state *error) > error->ier = I915_READ(DEIER); > error->gtier[0] = I915_READ(GTIER); > error->ngtier = 1; > - } else if (IS_GEN2(dev_priv)) { > + } else if (GT_GEN(dev_priv, 2)) { > error->ier = I915_READ16(IER); > } else if (!IS_VALLEYVIEW(dev_priv)) { > error->ier = I915_READ(IER); > diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c > index 5d1f53723388..3ed545c2d508 100644 > --- a/drivers/gpu/drm/i915/i915_irq.c > +++ b/drivers/gpu/drm/i915/i915_irq.c > @@ -950,7 +950,7 @@ static int __intel_get_crtc_scanline(struct intel_crtc *crtc) > if (mode->flags & DRM_MODE_FLAG_INTERLACE) > vtotal /= 2; > > - if (IS_GEN2(dev_priv)) > + if (GT_GEN(dev_priv, 2)) > position = I915_READ_FW(PIPEDSL(pipe)) & DSL_LINEMASK_GEN2; > else > position = I915_READ_FW(PIPEDSL(pipe)) & DSL_LINEMASK_GEN3; > @@ -1030,7 +1030,7 @@ static bool i915_get_crtc_scanoutpos(struct drm_device *dev, unsigned int pipe, > if (stime) > *stime = ktime_get(); > > - if (IS_GEN2(dev_priv) || IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5) { > + if (GT_GEN(dev_priv, 2) || IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5) { > /* No obvious pixelcount register. Only query vertical > * scanout position from Display scan line register. > */ > @@ -1090,7 +1090,7 @@ static bool i915_get_crtc_scanoutpos(struct drm_device *dev, unsigned int pipe, > else > position += vtotal - vbl_end; > > - if (IS_GEN2(dev_priv) || IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5) { > + if (GT_GEN(dev_priv, 2) || IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5) { > *vpos = position; > *hpos = 0; > } else { > @@ -2547,7 +2547,7 @@ static void ilk_display_irq_handler(struct drm_i915_private *dev_priv, > I915_WRITE(SDEIIR, pch_iir); > } > > - if (IS_GEN5(dev_priv) && de_iir & DE_PCU_EVENT) > + if (GT_GEN(dev_priv, 5) && de_iir & DE_PCU_EVENT) > ironlake_rps_change_irq_handler(dev_priv); > } > > @@ -3243,7 +3243,7 @@ void i915_clear_error_registers(struct drm_i915_private *dev_priv) > { > u32 eir; > > - if (!IS_GEN2(dev_priv)) > + if (!GT_GEN(dev_priv, 2)) > I915_WRITE(PGTBL_ER, I915_READ(PGTBL_ER)); > > if (INTEL_GEN(dev_priv) < 4) > @@ -3586,11 +3586,11 @@ static void ironlake_irq_reset(struct drm_device *dev) > { > struct drm_i915_private *dev_priv = to_i915(dev); > > - if (IS_GEN5(dev_priv)) > + if (GT_GEN(dev_priv, 5)) > I915_WRITE(HWSTAM, 0xffffffff); > > GEN3_IRQ_RESET(DE); > - if (IS_GEN7(dev_priv)) > + if (GT_GEN(dev_priv, 7)) > I915_WRITE(GEN7_ERR_INT, 0xffffffff); > > if (IS_HASWELL(dev_priv)) { > @@ -4042,7 +4042,7 @@ static void gen5_gt_irq_postinstall(struct drm_device *dev) > } > > gt_irqs |= GT_RENDER_USER_INTERRUPT; > - if (IS_GEN5(dev_priv)) { > + if (GT_GEN(dev_priv, 5)) { > gt_irqs |= ILK_BSD_USER_INTERRUPT; > } else { > gt_irqs |= GT_BLT_USER_INTERRUPT | GT_BSD_USER_INTERRUPT; > @@ -4833,7 +4833,7 @@ void intel_irq_init(struct drm_i915_private *dev_priv) > if (INTEL_GEN(dev_priv) >= 8) > rps->pm_intrmsk_mbz |= GEN8_PMINTR_DISABLE_REDIRECT_TO_GUC; > > - if (IS_GEN2(dev_priv)) { > + if (GT_GEN(dev_priv, 2)) { > /* Gen2 doesn't have a hardware frame counter */ > dev->max_vblank_count = 0; > } else if (IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5) { > @@ -4849,7 +4849,7 @@ void intel_irq_init(struct drm_i915_private *dev_priv) > * Gen2 doesn't have a hardware frame counter and so depends on > * vblank interrupts to produce sane vblank seuquence numbers. > */ > - if (!IS_GEN2(dev_priv)) > + if (!GT_GEN(dev_priv, 2)) > dev->vblank_disable_immediate = true; > > /* Most platforms treat the display irq block as an always-on > @@ -4914,14 +4914,14 @@ void intel_irq_init(struct drm_i915_private *dev_priv) > dev->driver->disable_vblank = ironlake_disable_vblank; > dev_priv->display.hpd_irq_setup = ilk_hpd_irq_setup; > } else { > - if (IS_GEN2(dev_priv)) { > + if (GT_GEN(dev_priv, 2)) { > dev->driver->irq_preinstall = i8xx_irq_reset; > dev->driver->irq_postinstall = i8xx_irq_postinstall; > dev->driver->irq_handler = i8xx_irq_handler; > dev->driver->irq_uninstall = i8xx_irq_reset; > dev->driver->enable_vblank = i8xx_enable_vblank; > dev->driver->disable_vblank = i8xx_disable_vblank; > - } else if (IS_GEN3(dev_priv)) { > + } else if (GT_GEN(dev_priv, 3)) { > dev->driver->irq_preinstall = i915_irq_reset; > dev->driver->irq_postinstall = i915_irq_postinstall; > dev->driver->irq_uninstall = i915_irq_reset; > diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c > index acc3502403b3..afbccc144c66 100644 > --- a/drivers/gpu/drm/i915/i915_perf.c > +++ b/drivers/gpu/drm/i915/i915_perf.c > @@ -3449,7 +3449,7 @@ void i915_perf_init(struct drm_i915_private *dev_priv) > dev_priv->perf.oa.ops.read = gen8_oa_read; > dev_priv->perf.oa.ops.oa_hw_tail_read = gen8_oa_hw_tail_read; > > - if (IS_GEN8(dev_priv) || IS_GEN9(dev_priv)) { > + if (GT_GEN(dev_priv, 8) || GT_GEN(dev_priv, 9)) { > dev_priv->perf.oa.ops.is_valid_b_counter_reg = > gen7_is_valid_b_counter_addr; > dev_priv->perf.oa.ops.is_valid_mux_reg = > @@ -3465,7 +3465,7 @@ void i915_perf_init(struct drm_i915_private *dev_priv) > dev_priv->perf.oa.ops.enable_metric_set = gen8_enable_metric_set; > dev_priv->perf.oa.ops.disable_metric_set = gen8_disable_metric_set; > > - if (IS_GEN8(dev_priv)) { > + if (GT_GEN(dev_priv, 8)) { > dev_priv->perf.oa.ctx_oactxctrl_offset = 0x120; > dev_priv->perf.oa.ctx_flexeu0_offset = 0x2ce; > > diff --git a/drivers/gpu/drm/i915/i915_suspend.c b/drivers/gpu/drm/i915/i915_suspend.c > index 8f3aa4dc0c98..b47b822fa6d6 100644 > --- a/drivers/gpu/drm/i915/i915_suspend.c > +++ b/drivers/gpu/drm/i915/i915_suspend.c > @@ -65,7 +65,7 @@ int i915_save_state(struct drm_i915_private *dev_priv) > > i915_save_display(dev_priv); > > - if (IS_GEN4(dev_priv)) > + if (GT_GEN(dev_priv, 4)) > pci_read_config_word(pdev, GCDGMBUS, > &dev_priv->regfile.saveGCDGMBUS); > > @@ -77,14 +77,14 @@ int i915_save_state(struct drm_i915_private *dev_priv) > dev_priv->regfile.saveMI_ARB_STATE = I915_READ(MI_ARB_STATE); > > /* Scratch space */ > - if (IS_GEN2(dev_priv) && IS_MOBILE(dev_priv)) { > + if (GT_GEN(dev_priv, 2) && IS_MOBILE(dev_priv)) { > for (i = 0; i < 7; i++) { > dev_priv->regfile.saveSWF0[i] = I915_READ(SWF0(i)); > dev_priv->regfile.saveSWF1[i] = I915_READ(SWF1(i)); > } > for (i = 0; i < 3; i++) > dev_priv->regfile.saveSWF3[i] = I915_READ(SWF3(i)); > - } else if (IS_GEN2(dev_priv)) { > + } else if (GT_GEN(dev_priv, 2)) { > for (i = 0; i < 7; i++) > dev_priv->regfile.saveSWF1[i] = I915_READ(SWF1(i)); > } else if (HAS_GMCH_DISPLAY(dev_priv)) { > @@ -108,7 +108,7 @@ int i915_restore_state(struct drm_i915_private *dev_priv) > > mutex_lock(&dev_priv->drm.struct_mutex); > > - if (IS_GEN4(dev_priv)) > + if (GT_GEN(dev_priv, 4)) > pci_write_config_word(pdev, GCDGMBUS, > dev_priv->regfile.saveGCDGMBUS); > i915_restore_display(dev_priv); > @@ -122,14 +122,14 @@ int i915_restore_state(struct drm_i915_private *dev_priv) > I915_WRITE(MI_ARB_STATE, dev_priv->regfile.saveMI_ARB_STATE | 0xffff0000); > > /* Scratch space */ > - if (IS_GEN2(dev_priv) && IS_MOBILE(dev_priv)) { > + if (GT_GEN(dev_priv, 2) && IS_MOBILE(dev_priv)) { > for (i = 0; i < 7; i++) { > I915_WRITE(SWF0(i), dev_priv->regfile.saveSWF0[i]); > I915_WRITE(SWF1(i), dev_priv->regfile.saveSWF1[i]); > } > for (i = 0; i < 3; i++) > I915_WRITE(SWF3(i), dev_priv->regfile.saveSWF3[i]); > - } else if (IS_GEN2(dev_priv)) { > + } else if (GT_GEN(dev_priv, 2)) { > for (i = 0; i < 7; i++) > I915_WRITE(SWF1(i), dev_priv->regfile.saveSWF1[i]); > } else if (HAS_GMCH_DISPLAY(dev_priv)) { > diff --git a/drivers/gpu/drm/i915/intel_atomic.c b/drivers/gpu/drm/i915/intel_atomic.c > index a5a2c8fe58a7..74dc23f67151 100644 > --- a/drivers/gpu/drm/i915/intel_atomic.c > +++ b/drivers/gpu/drm/i915/intel_atomic.c > @@ -232,7 +232,7 @@ static void intel_atomic_setup_scaler(struct intel_crtc_scaler_state *scaler_sta > if (plane_state && plane_state->base.fb && > plane_state->base.fb->format->is_yuv && > plane_state->base.fb->format->num_planes > 1) { > - if (IS_GEN9(dev_priv) && > + if (GT_GEN(dev_priv, 9) && > !IS_GEMINILAKE(dev_priv)) { > mode = SKL_PS_SCALER_MODE_NV12; > } else if (icl_is_hdr_plane(to_intel_plane(plane_state->base.plane))) { > diff --git a/drivers/gpu/drm/i915/intel_audio.c b/drivers/gpu/drm/i915/intel_audio.c > index ccd88da20a14..7f47bacbef20 100644 > --- a/drivers/gpu/drm/i915/intel_audio.c > +++ b/drivers/gpu/drm/i915/intel_audio.c > @@ -758,7 +758,7 @@ static void i915_audio_component_codec_wake_override(struct device *kdev, > struct drm_i915_private *dev_priv = kdev_to_i915(kdev); > u32 tmp; > > - if (!IS_GEN9(dev_priv)) > + if (!GT_GEN(dev_priv, 9)) > return; > > i915_audio_component_get_power(kdev); > diff --git a/drivers/gpu/drm/i915/intel_cdclk.c b/drivers/gpu/drm/i915/intel_cdclk.c > index 8d74276029e6..db0edd01c973 100644 > --- a/drivers/gpu/drm/i915/intel_cdclk.c > +++ b/drivers/gpu/drm/i915/intel_cdclk.c > @@ -2140,7 +2140,7 @@ static int intel_pixel_rate_to_cdclk(struct drm_i915_private *dev_priv, > { > if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) > return DIV_ROUND_UP(pixel_rate, 2); > - else if (IS_GEN9(dev_priv) || > + else if (GT_GEN(dev_priv, 9) || > IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) > return pixel_rate; > else if (IS_CHERRYVIEW(dev_priv)) > @@ -2176,7 +2176,7 @@ int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state) > if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv)) { > /* Display WA #1145: glk,cnl */ > min_cdclk = max(316800, min_cdclk); > - } else if (IS_GEN9(dev_priv) || IS_BROADWELL(dev_priv)) { > + } else if (GT_GEN(dev_priv, 9) || IS_BROADWELL(dev_priv)) { > /* Display WA #1144: skl,bxt */ > min_cdclk = max(432000, min_cdclk); > } > @@ -2537,7 +2537,7 @@ static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv) > > if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) > return 2 * max_cdclk_freq; > - else if (IS_GEN9(dev_priv) || > + else if (GT_GEN(dev_priv, 9) || > IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) > return max_cdclk_freq; > else if (IS_CHERRYVIEW(dev_priv)) > @@ -2806,9 +2806,9 @@ void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv) > dev_priv->display.get_cdclk = hsw_get_cdclk; > else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) > dev_priv->display.get_cdclk = vlv_get_cdclk; > - else if (IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv)) > + else if (GT_GEN(dev_priv, 6) || IS_IVYBRIDGE(dev_priv)) > dev_priv->display.get_cdclk = fixed_400mhz_get_cdclk; > - else if (IS_GEN5(dev_priv)) > + else if (GT_GEN(dev_priv, 5)) > dev_priv->display.get_cdclk = fixed_450mhz_get_cdclk; > else if (IS_GM45(dev_priv)) > dev_priv->display.get_cdclk = gm45_get_cdclk; > diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c > index 68f2fb89ece3..b37224227420 100644 > --- a/drivers/gpu/drm/i915/intel_crt.c > +++ b/drivers/gpu/drm/i915/intel_crt.c > @@ -322,7 +322,7 @@ intel_crt_mode_valid(struct drm_connector *connector, > * DAC limit supposedly 355 MHz. > */ > max_clock = 270000; > - else if (IS_GEN3(dev_priv) || IS_GEN4(dev_priv)) > + else if (GT_GEN(dev_priv, 3) || GT_GEN(dev_priv, 4)) > max_clock = 400000; > else > max_clock = 350000; > @@ -666,7 +666,7 @@ intel_crt_load_detect(struct intel_crt *crt, uint32_t pipe) > /* Set the border color to purple. */ > I915_WRITE(bclrpat_reg, 0x500050); > > - if (!IS_GEN2(dev_priv)) { > + if (!GT_GEN(dev_priv, 2)) { > uint32_t pipeconf = I915_READ(pipeconf_reg); > I915_WRITE(pipeconf_reg, pipeconf | PIPECONF_FORCE_BORDER); > POSTING_READ(pipeconf_reg); > @@ -981,7 +981,7 @@ void intel_crt_init(struct drm_i915_private *dev_priv) > else > crt->base.crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); > > - if (IS_GEN2(dev_priv)) > + if (GT_GEN(dev_priv, 2)) > connector->interlace_allowed = 0; > else > connector->interlace_allowed = 1; > diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c > index 89ed3a84a4fa..7f712cd238fe 100644 > --- a/drivers/gpu/drm/i915/intel_device_info.c > +++ b/drivers/gpu/drm/i915/intel_device_info.c > @@ -744,7 +744,7 @@ void intel_device_info_runtime_init(struct intel_device_info *info) > if (INTEL_GEN(dev_priv) >= 10) { > for_each_pipe(dev_priv, pipe) > info->num_scalers[pipe] = 2; > - } else if (IS_GEN9(dev_priv)) { > + } else if (GT_GEN(dev_priv, 9)) { > info->num_scalers[PIPE_A] = 2; > info->num_scalers[PIPE_B] = 2; > info->num_scalers[PIPE_C] = 1; > @@ -752,10 +752,10 @@ void intel_device_info_runtime_init(struct intel_device_info *info) > > BUILD_BUG_ON(I915_NUM_ENGINES > BITS_PER_TYPE(intel_ring_mask_t)); > > - if (IS_GEN11(dev_priv)) > + if (GT_GEN(dev_priv, 11)) > for_each_pipe(dev_priv, pipe) > info->num_sprites[pipe] = 6; > - else if (IS_GEN10(dev_priv) || IS_GEMINILAKE(dev_priv)) > + else if (GT_GEN(dev_priv, 10) || IS_GEMINILAKE(dev_priv)) > for_each_pipe(dev_priv, pipe) > info->num_sprites[pipe] = 3; > else if (IS_BROXTON(dev_priv)) { > @@ -783,7 +783,7 @@ void intel_device_info_runtime_init(struct intel_device_info *info) > DRM_INFO("Display disabled (module parameter)\n"); > info->num_pipes = 0; > } else if (info->num_pipes > 0 && > - (IS_GEN7(dev_priv) || IS_GEN8(dev_priv)) && > + (GT_GEN(dev_priv, 7) || GT_GEN(dev_priv, 8)) && > HAS_PCH_SPLIT(dev_priv)) { > u32 fuse_strap = I915_READ(FUSE_STRAP); > u32 sfuse_strap = I915_READ(SFUSE_STRAP); > @@ -807,7 +807,7 @@ void intel_device_info_runtime_init(struct intel_device_info *info) > DRM_INFO("PipeC fused off\n"); > info->num_pipes -= 1; > } > - } else if (info->num_pipes > 0 && IS_GEN9(dev_priv)) { > + } else if (info->num_pipes > 0 && GT_GEN(dev_priv, 9)) { > u32 dfsm = I915_READ(SKL_DFSM); > u8 disabled_mask = 0; > bool invalid; > @@ -847,14 +847,14 @@ void intel_device_info_runtime_init(struct intel_device_info *info) > cherryview_sseu_info_init(dev_priv); > else if (IS_BROADWELL(dev_priv)) > broadwell_sseu_info_init(dev_priv); > - else if (IS_GEN9(dev_priv)) > + else if (GT_GEN(dev_priv, 9)) > gen9_sseu_info_init(dev_priv); > - else if (IS_GEN10(dev_priv)) > + else if (GT_GEN(dev_priv, 10)) > gen10_sseu_info_init(dev_priv); > else if (INTEL_GEN(dev_priv) >= 11) > gen11_sseu_info_init(dev_priv); > > - if (IS_GEN6(dev_priv) && intel_vtd_active()) { > + if (GT_GEN(dev_priv, 6) && intel_vtd_active()) { > DRM_INFO("Disabling ppGTT for VT-d support\n"); > info->ppgtt = INTEL_PPGTT_NONE; > } > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c > index bbf8ca21a7a2..904950a65c1b 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -984,7 +984,7 @@ static bool pipe_scanline_is_moving(struct drm_i915_private *dev_priv, > u32 line1, line2; > u32 line_mask; > > - if (IS_GEN2(dev_priv)) > + if (GT_GEN(dev_priv, 2)) > line_mask = DSL_LINEMASK_GEN2; > else > line_mask = DSL_LINEMASK_GEN3; > @@ -1110,7 +1110,7 @@ static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv, > u32 val; > > /* ILK FDI PLL is always enabled */ > - if (IS_GEN5(dev_priv)) > + if (GT_GEN(dev_priv, 5)) > return; > > /* On Haswell, DDI ports are responsible for the FDI PLL setup */ > @@ -1849,7 +1849,7 @@ static void intel_disable_pipe(const struct intel_crtc_state *old_crtc_state) > > static unsigned int intel_tile_size(const struct drm_i915_private *dev_priv) > { > - return IS_GEN2(dev_priv) ? 2048 : 4096; > + return GT_GEN(dev_priv, 2) ? 2048 : 4096; > } > > static unsigned int > @@ -1862,7 +1862,7 @@ intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane) > case DRM_FORMAT_MOD_LINEAR: > return cpp; > case I915_FORMAT_MOD_X_TILED: > - if (IS_GEN2(dev_priv)) > + if (GT_GEN(dev_priv, 2)) > return 128; > else > return 512; > @@ -1871,7 +1871,7 @@ intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane) > return 128; > /* fall through */ > case I915_FORMAT_MOD_Y_TILED: > - if (IS_GEN2(dev_priv) || HAS_128_BYTE_Y_TILING(dev_priv)) > + if (GT_GEN(dev_priv, 2) || HAS_128_BYTE_Y_TILING(dev_priv)) > return 128; > else > return 512; > @@ -3175,8 +3175,8 @@ static u32 i9xx_plane_ctl(const struct intel_crtc_state *crtc_state, > > dspcntr = DISPLAY_PLANE_ENABLE | DISPPLANE_GAMMA_ENABLE; > > - if (IS_G4X(dev_priv) || IS_GEN5(dev_priv) || > - IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv)) > + if (IS_G4X(dev_priv) || GT_GEN(dev_priv, 5) || > + GT_GEN(dev_priv, 6) || IS_IVYBRIDGE(dev_priv)) > dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; > > if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) > @@ -4095,7 +4095,7 @@ static void gen6_fdi_link_train(struct intel_crtc *crtc, > temp = I915_READ(reg); > temp &= ~FDI_LINK_TRAIN_NONE; > temp |= FDI_LINK_TRAIN_PATTERN_2; > - if (IS_GEN6(dev_priv)) { > + if (GT_GEN(dev_priv, 6)) { > temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; > /* SNB-B */ > temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; > @@ -4862,10 +4862,10 @@ skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach, > /* range checks */ > if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H || > dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H || > - (IS_GEN11(dev_priv) && > + (GT_GEN(dev_priv, 11) && > (src_w > ICL_MAX_SRC_W || src_h > ICL_MAX_SRC_H || > dst_w > ICL_MAX_DST_W || dst_h > ICL_MAX_DST_H)) || > - (!IS_GEN11(dev_priv) && > + (!GT_GEN(dev_priv, 11) && > (src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H || > dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H))) { > DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u " > @@ -5149,7 +5149,7 @@ intel_post_enable_primary(struct drm_crtc *crtc, > * FIXME: Need to fix the logic to work when we turn off all planes > * but leave the pipe running. > */ > - if (IS_GEN2(dev_priv)) > + if (GT_GEN(dev_priv, 2)) > intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); > > /* Underruns don't always raise interrupts, so check manually. */ > @@ -5170,7 +5170,7 @@ intel_pre_disable_primary_noatomic(struct drm_crtc *crtc) > * Gen2 reports pipe underruns whenever all planes are disabled. > * So disable underrun reporting before all the planes get disabled. > */ > - if (IS_GEN2(dev_priv)) > + if (GT_GEN(dev_priv, 2)) > intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); > > hsw_disable_ips(to_intel_crtc_state(crtc->state)); > @@ -5228,7 +5228,7 @@ static bool needs_nv12_wa(struct drm_i915_private *dev_priv, > return false; > > /* WA Display #0827: Gen9:all */ > - if (IS_GEN9(dev_priv) && !IS_GEMINILAKE(dev_priv)) > + if (GT_GEN(dev_priv, 9) && !IS_GEMINILAKE(dev_priv)) > return true; > > return false; > @@ -5301,7 +5301,7 @@ static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state, > * Gen2 reports pipe underruns whenever all planes are disabled. > * So disable underrun reporting before all the planes get disabled. > */ > - if (IS_GEN2(dev_priv) && old_primary_state->visible && > + if (GT_GEN(dev_priv, 2) && old_primary_state->visible && > (modeset || !new_primary_state->base.visible)) > intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false); > } > @@ -6115,7 +6115,7 @@ static void i9xx_crtc_enable(struct intel_crtc_state *pipe_config, > > intel_crtc->active = true; > > - if (!IS_GEN2(dev_priv)) > + if (!GT_GEN(dev_priv, 2)) > intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); > > intel_encoders_pre_enable(crtc, pipe_config, old_state); > @@ -6167,7 +6167,7 @@ static void i9xx_crtc_disable(struct intel_crtc_state *old_crtc_state, > * On gen2 planes are double buffered but the pipe isn't, so we must > * wait for planes to fully turn off before disabling the pipe. > */ > - if (IS_GEN2(dev_priv)) > + if (GT_GEN(dev_priv, 2)) > intel_wait_for_vblank(dev_priv, pipe); > > intel_encoders_disable(crtc, old_crtc_state, old_state); > @@ -6192,7 +6192,7 @@ static void i9xx_crtc_disable(struct intel_crtc_state *old_crtc_state, > > intel_encoders_post_pll_disable(crtc, old_crtc_state, old_state); > > - if (!IS_GEN2(dev_priv)) > + if (!GT_GEN(dev_priv, 2)) > intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); > > if (!dev_priv->display.initial_watermarks) > @@ -6796,7 +6796,7 @@ static bool transcoder_has_m2_n2(struct drm_i915_private *dev_priv, > * Strictly speaking some registers are available before > * gen7, but we only support DRRS on gen7+ > */ > - return IS_GEN7(dev_priv) || IS_CHERRYVIEW(dev_priv); > + return GT_GEN(dev_priv, 7) || IS_CHERRYVIEW(dev_priv); > } > > static void intel_cpu_transcoder_set_m_n(const struct intel_crtc_state *crtc_state, > @@ -8903,7 +8903,7 @@ static void ironlake_get_pfit_config(struct intel_crtc *crtc, > /* We currently do not free assignements of panel fitters on > * ivb/hsw (since we don't use the higher upscaling modes which > * differentiates them) so just WARN about this case for now. */ > - if (IS_GEN7(dev_priv)) { > + if (GT_GEN(dev_priv, 7)) { > WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) != > PF_PIPE_SEL_IVB(crtc->pipe)); > } > @@ -9865,7 +9865,7 @@ static u32 i9xx_cursor_ctl(const struct intel_crtc_state *crtc_state, > struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); > u32 cntl = 0; > > - if (IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv)) > + if (GT_GEN(dev_priv, 6) || IS_IVYBRIDGE(dev_priv)) > cntl |= MCURSOR_TRICKLE_FEED_DISABLE; > > if (INTEL_GEN(dev_priv) <= 10) { > @@ -10335,7 +10335,7 @@ static int i9xx_pll_refclk(struct drm_device *dev, > return dev_priv->vbt.lvds_ssc_freq; > else if (HAS_PCH_SPLIT(dev_priv)) > return 120000; > - else if (!IS_GEN2(dev_priv)) > + else if (!GT_GEN(dev_priv, 2)) > return 96000; > else > return 48000; > @@ -10368,7 +10368,7 @@ static void i9xx_crtc_clock_get(struct intel_crtc *crtc, > clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT; > } > > - if (!IS_GEN2(dev_priv)) { > + if (!GT_GEN(dev_priv, 2)) { > if (IS_PINEVIEW(dev_priv)) > clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >> > DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW); > @@ -10684,7 +10684,7 @@ int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_crtc_stat > * the w/a on all three platforms. > */ > if (plane->id == PLANE_SPRITE0 && > - (IS_GEN5(dev_priv) || IS_GEN6(dev_priv) || > + (GT_GEN(dev_priv, 5) || GT_GEN(dev_priv, 6) || > IS_IVYBRIDGE(dev_priv)) && > (turn_on || (!needs_scaling(old_plane_state) && > needs_scaling(to_intel_plane_state(plane_state))))) > @@ -12238,7 +12238,7 @@ static void update_scanline_offset(const struct intel_crtc_state *crtc_state) > * However if queried just before the start of vblank we'll get an > * answer that's slightly in the future. > */ > - if (IS_GEN2(dev_priv)) { > + if (GT_GEN(dev_priv, 2)) { > const struct drm_display_mode *adjusted_mode = &crtc_state->base.adjusted_mode; > int vtotal; > > @@ -13437,7 +13437,7 @@ void intel_crtc_arm_fifo_underrun(struct intel_crtc *crtc, > { > struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); > > - if (!IS_GEN2(dev_priv)) > + if (!GT_GEN(dev_priv, 2)) > intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true); > > if (crtc_state->has_pch_encoder) { > @@ -14044,7 +14044,7 @@ static bool has_edp_a(struct drm_i915_private *dev_priv) > if ((I915_READ(DP_A) & DP_DETECTED) == 0) > return false; > > - if (IS_GEN5(dev_priv) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE)) > + if (GT_GEN(dev_priv, 5) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE)) > return false; > > return true; > @@ -14256,7 +14256,7 @@ static void intel_setup_outputs(struct drm_i915_private *dev_priv) > } > > vlv_dsi_init(dev_priv); > - } else if (!IS_GEN2(dev_priv) && !IS_PINEVIEW(dev_priv)) { > + } else if (!GT_GEN(dev_priv, 2) && !IS_PINEVIEW(dev_priv)) { > bool found = false; > > if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { > @@ -14290,7 +14290,7 @@ static void intel_setup_outputs(struct drm_i915_private *dev_priv) > > if (IS_G4X(dev_priv) && (I915_READ(DP_D) & DP_DETECTED)) > intel_dp_init(dev_priv, DP_D, PORT_D); > - } else if (IS_GEN2(dev_priv)) > + } else if (GT_GEN(dev_priv, 2)) > intel_dvo_init(dev_priv); > > if (SUPPORTS_TV(dev_priv)) > @@ -14577,7 +14577,7 @@ static int intel_framebuffer_init(struct intel_framebuffer *intel_fb, > * require the entire fb to accommodate that to avoid > * potential runtime errors at plane configuration time. > */ > - if (IS_GEN9(dev_priv) && i == 0 && fb->width > 3840 && > + if (GT_GEN(dev_priv, 9) && i == 0 && fb->width > 3840 && > is_ccs_modifier(fb->modifier)) > stride_alignment *= 4; > > @@ -14782,7 +14782,7 @@ void intel_init_display_hooks(struct drm_i915_private *dev_priv) > dev_priv->display.crtc_compute_clock = pnv_crtc_compute_clock; > dev_priv->display.crtc_enable = i9xx_crtc_enable; > dev_priv->display.crtc_disable = i9xx_crtc_disable; > - } else if (!IS_GEN2(dev_priv)) { > + } else if (!GT_GEN(dev_priv, 2)) { > dev_priv->display.get_pipe_config = i9xx_get_pipe_config; > dev_priv->display.get_initial_plane_config = > i9xx_get_initial_plane_config; > @@ -14798,9 +14798,9 @@ void intel_init_display_hooks(struct drm_i915_private *dev_priv) > dev_priv->display.crtc_disable = i9xx_crtc_disable; > } > > - if (IS_GEN5(dev_priv)) { > + if (GT_GEN(dev_priv, 5)) { > dev_priv->display.fdi_link_train = ironlake_fdi_link_train; > - } else if (IS_GEN6(dev_priv)) { > + } else if (GT_GEN(dev_priv, 6)) { > dev_priv->display.fdi_link_train = gen6_fdi_link_train; > } else if (IS_IVYBRIDGE(dev_priv)) { > /* FIXME: detect B0+ stepping and use auto training */ > @@ -14932,12 +14932,12 @@ static void sanitize_watermarks(struct drm_device *dev) > > static void intel_update_fdi_pll_freq(struct drm_i915_private *dev_priv) > { > - if (IS_GEN5(dev_priv)) { > + if (GT_GEN(dev_priv, 5)) { > u32 fdi_pll_clk = > I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK; > > dev_priv->fdi_pll_freq = (fdi_pll_clk + 2) * 10000; > - } else if (IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv)) { > + } else if (GT_GEN(dev_priv, 6) || IS_IVYBRIDGE(dev_priv)) { > dev_priv->fdi_pll_freq = 270000; > } else { > return; > @@ -15043,10 +15043,10 @@ int intel_modeset_init(struct drm_device *dev) > } > > /* maximum framebuffer dimensions */ > - if (IS_GEN2(dev_priv)) { > + if (GT_GEN(dev_priv, 2)) { > dev->mode_config.max_width = 2048; > dev->mode_config.max_height = 2048; > - } else if (IS_GEN3(dev_priv)) { > + } else if (GT_GEN(dev_priv, 3)) { > dev->mode_config.max_width = 4096; > dev->mode_config.max_height = 4096; > } else { > @@ -15057,7 +15057,7 @@ int intel_modeset_init(struct drm_device *dev) > if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) { > dev->mode_config.cursor_width = IS_I845G(dev_priv) ? 64 : 512; > dev->mode_config.cursor_height = 1023; > - } else if (IS_GEN2(dev_priv)) { > + } else if (GT_GEN(dev_priv, 2)) { > dev->mode_config.cursor_width = 64; > dev->mode_config.cursor_height = 64; > } else { > diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c > index 5258c9d654f4..9e410b04f99d 100644 > --- a/drivers/gpu/drm/i915/intel_dp.c > +++ b/drivers/gpu/drm/i915/intel_dp.c > @@ -342,7 +342,7 @@ intel_dp_set_source_rates(struct intel_dp *intel_dp) > if (INTEL_GEN(dev_priv) >= 10) { > source_rates = cnl_rates; > size = ARRAY_SIZE(cnl_rates); > - if (IS_GEN10(dev_priv)) > + if (GT_GEN(dev_priv, 10)) > max_rate = cnl_max_source_rate(intel_dp); > else > max_rate = icl_max_source_rate(intel_dp); > @@ -1126,7 +1126,7 @@ static uint32_t g4x_get_aux_send_ctl(struct intel_dp *intel_dp, > to_i915(intel_dig_port->base.base.dev); > uint32_t precharge, timeout; > > - if (IS_GEN6(dev_priv)) > + if (GT_GEN(dev_priv, 6)) > precharge = 3; > else > precharge = 5; > @@ -2412,7 +2412,7 @@ static void edp_panel_on(struct intel_dp *intel_dp) > > pp_ctrl_reg = _pp_ctrl_reg(intel_dp); > pp = ironlake_get_pp_control(intel_dp); > - if (IS_GEN5(dev_priv)) { > + if (GT_GEN(dev_priv, 5)) { > /* ILK workaround: disable reset around power sequence */ > pp &= ~PANEL_POWER_RESET; > I915_WRITE(pp_ctrl_reg, pp); > @@ -2420,7 +2420,7 @@ static void edp_panel_on(struct intel_dp *intel_dp) > } > > pp |= PANEL_POWER_ON; > - if (!IS_GEN5(dev_priv)) > + if (!GT_GEN(dev_priv, 5)) > pp |= PANEL_POWER_RESET; > > I915_WRITE(pp_ctrl_reg, pp); > @@ -2429,7 +2429,7 @@ static void edp_panel_on(struct intel_dp *intel_dp) > wait_panel_on(intel_dp); > intel_dp->last_power_on = jiffies; > > - if (IS_GEN5(dev_priv)) { > + if (GT_GEN(dev_priv, 5)) { > pp |= PANEL_POWER_RESET; /* restore panel reset bit */ > I915_WRITE(pp_ctrl_reg, pp); > POSTING_READ(pp_ctrl_reg); > @@ -2658,7 +2658,7 @@ static void ironlake_edp_pll_on(struct intel_dp *intel_dp, > * 1. Wait for the start of vertical blank on the enabled pipe going to FDI > * 2. Program DP PLL enable > */ > - if (IS_GEN5(dev_priv)) > + if (GT_GEN(dev_priv, 5)) > intel_wait_for_vblank_if_active(dev_priv, !crtc->pipe); > > intel_dp->DP |= DP_PLL_ENABLE; > @@ -3660,7 +3660,7 @@ intel_dp_set_signal_levels(struct intel_dp *intel_dp) > } else if (IS_IVYBRIDGE(dev_priv) && port == PORT_A) { > signal_levels = ivb_cpu_edp_signal_levels(train_set); > mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB; > - } else if (IS_GEN6(dev_priv) && port == PORT_A) { > + } else if (GT_GEN(dev_priv, 6) && port == PORT_A) { > signal_levels = snb_cpu_edp_signal_levels(train_set); > mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB; > } else { > @@ -5026,17 +5026,17 @@ bool intel_digital_port_connected(struct intel_encoder *encoder) > > if (INTEL_GEN(dev_priv) >= 11) > return icl_digital_port_connected(encoder); > - else if (IS_GEN10(dev_priv) || IS_GEN9_BC(dev_priv)) > + else if (GT_GEN(dev_priv, 10) || IS_GEN9_BC(dev_priv)) > return spt_digital_port_connected(encoder); > else if (IS_GEN9_LP(dev_priv)) > return bxt_digital_port_connected(encoder); > - else if (IS_GEN8(dev_priv)) > + else if (GT_GEN(dev_priv, 8)) > return bdw_digital_port_connected(encoder); > - else if (IS_GEN7(dev_priv)) > + else if (GT_GEN(dev_priv, 7)) > return ivb_digital_port_connected(encoder); > - else if (IS_GEN6(dev_priv)) > + else if (GT_GEN(dev_priv, 6)) > return snb_digital_port_connected(encoder); > - else if (IS_GEN5(dev_priv)) > + else if (GT_GEN(dev_priv, 5)) > return ilk_digital_port_connected(encoder); > > MISSING_CASE(INTEL_GEN(dev_priv)); > diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c > index 4f7b654614e9..4032a635acb5 100644 > --- a/drivers/gpu/drm/i915/intel_engine_cs.c > +++ b/drivers/gpu/drm/i915/intel_engine_cs.c > @@ -438,7 +438,7 @@ void intel_engine_init_global_seqno(struct intel_engine_cs *engine, u32 seqno) > * the semaphore value, then when the seqno moves backwards all > * future waits will complete instantly (causing rendering corruption). > */ > - if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv)) { > + if (GT_GEN(dev_priv, 6) || GT_GEN(dev_priv, 7)) { > I915_WRITE(RING_SYNC_0(engine->mmio_base), 0); > I915_WRITE(RING_SYNC_1(engine->mmio_base), 0); > if (HAS_VEBOX(dev_priv)) > @@ -812,7 +812,7 @@ u32 intel_calculate_mcr_s_ss_select(struct drm_i915_private *dev_priv) > u32 slice = fls(sseu->slice_mask); > u32 subslice = fls(sseu->subslice_mask[slice]); > > - if (IS_GEN10(dev_priv)) > + if (GT_GEN(dev_priv, 10)) > mcr_s_ss_select = GEN8_MCR_SLICE(slice) | > GEN8_MCR_SUBSLICE(subslice); > else if (INTEL_GEN(dev_priv) >= 11) > diff --git a/drivers/gpu/drm/i915/intel_fbc.c b/drivers/gpu/drm/i915/intel_fbc.c > index 9f41779988e5..549e3dc0e457 100644 > --- a/drivers/gpu/drm/i915/intel_fbc.c > +++ b/drivers/gpu/drm/i915/intel_fbc.c > @@ -84,7 +84,7 @@ static int intel_fbc_calculate_cfb_size(struct drm_i915_private *dev_priv, > int lines; > > intel_fbc_get_plane_source_size(cache, NULL, &lines); > - if (IS_GEN7(dev_priv)) > + if (GT_GEN(dev_priv, 7)) > lines = min(lines, 2048); > else if (INTEL_GEN(dev_priv) >= 8) > lines = min(lines, 2560); > @@ -127,7 +127,7 @@ static void i8xx_fbc_activate(struct drm_i915_private *dev_priv) > cfb_pitch = params->fb.stride; > > /* FBC_CTL wants 32B or 64B units */ > - if (IS_GEN2(dev_priv)) > + if (GT_GEN(dev_priv, 2)) > cfb_pitch = (cfb_pitch / 32) - 1; > else > cfb_pitch = (cfb_pitch / 64) - 1; > @@ -136,7 +136,7 @@ static void i8xx_fbc_activate(struct drm_i915_private *dev_priv) > for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++) > I915_WRITE(FBC_TAG(i), 0); > > - if (IS_GEN4(dev_priv)) { > + if (GT_GEN(dev_priv, 4)) { > u32 fbc_ctl2; > > /* Set it up... */ > @@ -233,9 +233,9 @@ static void ilk_fbc_activate(struct drm_i915_private *dev_priv) > > if (params->flags & PLANE_HAS_FENCE) { > dpfc_ctl |= DPFC_CTL_FENCE_EN; > - if (IS_GEN5(dev_priv)) > + if (GT_GEN(dev_priv, 5)) > dpfc_ctl |= params->vma->fence->id; > - if (IS_GEN6(dev_priv)) { > + if (GT_GEN(dev_priv, 6)) { > I915_WRITE(SNB_DPFC_CTL_SA, > SNB_CPU_FENCE_ENABLE | > params->vma->fence->id); > @@ -243,7 +243,7 @@ static void ilk_fbc_activate(struct drm_i915_private *dev_priv) > params->crtc.fence_y_offset); > } > } else { > - if (IS_GEN6(dev_priv)) { > + if (GT_GEN(dev_priv, 6)) { > I915_WRITE(SNB_DPFC_CTL_SA, 0); > I915_WRITE(DPFC_CPU_FENCE_OFFSET, 0); > } > @@ -282,7 +282,7 @@ static void gen7_fbc_activate(struct drm_i915_private *dev_priv) > int threshold = dev_priv->fbc.threshold; > > /* Display WA #0529: skl, kbl, bxt. */ > - if (IS_GEN9(dev_priv) && !IS_GEMINILAKE(dev_priv)) { > + if (GT_GEN(dev_priv, 9) && !IS_GEMINILAKE(dev_priv)) { > u32 val = I915_READ(CHICKEN_MISC_4); > > val &= ~(FBC_STRIDE_OVERRIDE | FBC_STRIDE_MASK); > @@ -581,10 +581,10 @@ static bool stride_is_valid(struct drm_i915_private *dev_priv, > if (stride < 512) > return false; > > - if (IS_GEN2(dev_priv) || IS_GEN3(dev_priv)) > + if (GT_GEN(dev_priv, 2) || GT_GEN(dev_priv, 3)) > return stride == 4096 || stride == 8192; > > - if (IS_GEN4(dev_priv) && !IS_G4X(dev_priv) && stride < 2048) > + if (GT_GEN(dev_priv, 4) && !IS_G4X(dev_priv) && stride < 2048) > return false; > > if (stride > 16384) > @@ -603,7 +603,7 @@ static bool pixel_format_is_valid(struct drm_i915_private *dev_priv, > case DRM_FORMAT_XRGB1555: > case DRM_FORMAT_RGB565: > /* 16bpp not supported on gen2 */ > - if (IS_GEN2(dev_priv)) > + if (GT_GEN(dev_priv, 2)) > return false; > /* WaFbcOnly1to1Ratio:ctg */ > if (IS_G4X(dev_priv)) > @@ -839,7 +839,7 @@ static void intel_fbc_get_reg_params(struct intel_crtc *crtc, > > params->cfb_size = intel_fbc_calculate_cfb_size(dev_priv, cache); > > - if (IS_GEN9(dev_priv) && !IS_GEMINILAKE(dev_priv)) > + if (GT_GEN(dev_priv, 9) && !IS_GEMINILAKE(dev_priv)) > params->gen9_wa_cfb_stride = DIV_ROUND_UP(cache->plane.src_w, > 32 * fbc->threshold) * 8; > } > diff --git a/drivers/gpu/drm/i915/intel_fifo_underrun.c b/drivers/gpu/drm/i915/intel_fifo_underrun.c > index 77c123cc8817..06f69bca0ff4 100644 > --- a/drivers/gpu/drm/i915/intel_fifo_underrun.c > +++ b/drivers/gpu/drm/i915/intel_fifo_underrun.c > @@ -260,9 +260,9 @@ static bool __intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev, > > if (HAS_GMCH_DISPLAY(dev_priv)) > i9xx_set_fifo_underrun_reporting(dev, pipe, enable, old); > - else if (IS_GEN5(dev_priv) || IS_GEN6(dev_priv)) > + else if (GT_GEN(dev_priv, 5) || GT_GEN(dev_priv, 6)) > ironlake_set_fifo_underrun_reporting(dev, pipe, enable); > - else if (IS_GEN7(dev_priv)) > + else if (GT_GEN(dev_priv, 7)) > ivybridge_set_fifo_underrun_reporting(dev, pipe, enable, old); > else if (INTEL_GEN(dev_priv) >= 8) > broadwell_set_fifo_underrun_reporting(dev, pipe, enable); > @@ -423,7 +423,7 @@ void intel_check_cpu_fifo_underruns(struct drm_i915_private *dev_priv) > > if (HAS_GMCH_DISPLAY(dev_priv)) > i9xx_check_fifo_underruns(crtc); > - else if (IS_GEN7(dev_priv)) > + else if (GT_GEN(dev_priv, 7)) > ivybridge_check_fifo_underruns(crtc); > } > > diff --git a/drivers/gpu/drm/i915/intel_guc_fw.c b/drivers/gpu/drm/i915/intel_guc_fw.c > index ae8e103a2c4d..9fdce47755e2 100644 > --- a/drivers/gpu/drm/i915/intel_guc_fw.c > +++ b/drivers/gpu/drm/i915/intel_guc_fw.c > @@ -114,7 +114,7 @@ static void guc_prepare_xfer(struct intel_guc *guc) > else > I915_WRITE(GEN9_GT_PM_CONFIG, GT_DOORBELL_ENABLE); > > - if (IS_GEN9(dev_priv)) { > + if (GT_GEN(dev_priv, 9)) { > /* DOP Clock Gating Enable for GuC clocks */ > I915_WRITE(GEN7_MISCCPCTL, (GEN8_DOP_CLOCK_GATE_GUC_ENABLE | > I915_READ(GEN7_MISCCPCTL))); > diff --git a/drivers/gpu/drm/i915/intel_hangcheck.c b/drivers/gpu/drm/i915/intel_hangcheck.c > index 9b15ed1409ae..84867ca2cc0c 100644 > --- a/drivers/gpu/drm/i915/intel_hangcheck.c > +++ b/drivers/gpu/drm/i915/intel_hangcheck.c > @@ -236,7 +236,7 @@ engine_stuck(struct intel_engine_cs *engine, u64 acthd) > if (ha != ENGINE_DEAD) > return ha; > > - if (IS_GEN2(dev_priv)) > + if (GT_GEN(dev_priv, 2)) > return ENGINE_DEAD; > > /* Is the chip hanging on a WAIT_FOR_EVENT? > diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c > index 22b57b8926fc..d8b53a0eac09 100644 > --- a/drivers/gpu/drm/i915/intel_lrc.c > +++ b/drivers/gpu/drm/i915/intel_lrc.c > @@ -1990,7 +1990,7 @@ static int gen8_emit_flush_render(struct i915_request *request, > * On GEN9: before VF_CACHE_INVALIDATE we need to emit a NULL > * pipe control. > */ > - if (IS_GEN9(request->i915)) > + if (GT_GEN(request->i915, 9)) > vf_flush_wa = true; > > /* WaForGAMHang:kbl */ > @@ -2368,7 +2368,7 @@ make_rpcs(struct drm_i915_private *dev_priv) > * subslices are enabled, or a count between one and four on the first > * slice. > */ > - if (IS_GEN11(dev_priv) && slices == 1 && subslices >= 4) { > + if (GT_GEN(dev_priv, 11) && slices == 1 && subslices >= 4) { > GEM_BUG_ON(subslices & 1); > > subslice_pg = false; > diff --git a/drivers/gpu/drm/i915/intel_lvds.c b/drivers/gpu/drm/i915/intel_lvds.c > index e6c5d985ea0a..79fa6b09a8db 100644 > --- a/drivers/gpu/drm/i915/intel_lvds.c > +++ b/drivers/gpu/drm/i915/intel_lvds.c > @@ -279,7 +279,7 @@ static void intel_pre_enable_lvds(struct intel_encoder *encoder, > * special lvds dither control bit on pch-split platforms, dithering is > * only controlled through the PIPECONF reg. > */ > - if (IS_GEN4(dev_priv)) { > + if (GT_GEN(dev_priv, 4)) { > /* > * Bspec wording suggests that LVDS port dithering only exists > * for 18bpp panels. > @@ -919,7 +919,7 @@ void intel_lvds_init(struct drm_i915_private *dev_priv) > intel_encoder->cloneable = 0; > if (HAS_PCH_SPLIT(dev_priv)) > intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); > - else if (IS_GEN4(dev_priv)) > + else if (GT_GEN(dev_priv, 4)) > intel_encoder->crtc_mask = (1 << 0) | (1 << 1); > else > intel_encoder->crtc_mask = (1 << 1); > diff --git a/drivers/gpu/drm/i915/intel_mocs.c b/drivers/gpu/drm/i915/intel_mocs.c > index 77e9871a8c9a..8201774c2c0f 100644 > --- a/drivers/gpu/drm/i915/intel_mocs.c > +++ b/drivers/gpu/drm/i915/intel_mocs.c > @@ -193,7 +193,7 @@ static bool get_mocs_settings(struct drm_i915_private *dev_priv, > } > > /* WaDisableSkipCaching:skl,bxt,kbl,glk */ > - if (IS_GEN9(dev_priv)) { > + if (GT_GEN(dev_priv, 9)) { > int i; > > for (i = 0; i < table->size; i++) > diff --git a/drivers/gpu/drm/i915/intel_overlay.c b/drivers/gpu/drm/i915/intel_overlay.c > index 72eb7e48e8bc..c8eddf941762 100644 > --- a/drivers/gpu/drm/i915/intel_overlay.c > +++ b/drivers/gpu/drm/i915/intel_overlay.c > @@ -541,7 +541,7 @@ static u32 calc_swidthsw(struct drm_i915_private *dev_priv, u32 offset, u32 widt > { > u32 sw; > > - if (IS_GEN2(dev_priv)) > + if (GT_GEN(dev_priv, 2)) > sw = ALIGN((offset & 31) + width, 32); > else > sw = ALIGN((offset & 63) + width, 64); > @@ -778,7 +778,7 @@ static int intel_overlay_do_put_image(struct intel_overlay *overlay, > u32 oconfig; > > oconfig = OCONF_CC_OUT_8BIT; > - if (IS_GEN4(dev_priv)) > + if (GT_GEN(dev_priv, 4)) > oconfig |= OCONF_CSC_MODE_BT709; > oconfig |= pipe == 0 ? > OCONF_PIPE_A : OCONF_PIPE_B; > @@ -1012,7 +1012,7 @@ static int check_overlay_src(struct drm_i915_private *dev_priv, > > if (rec->stride_Y & stride_mask || rec->stride_UV & stride_mask) > return -EINVAL; > - if (IS_GEN4(dev_priv) && rec->stride_Y < 512) > + if (GT_GEN(dev_priv, 4) && rec->stride_Y < 512) > return -EINVAL; > > tmp = (rec->flags & I915_OVERLAY_TYPE_MASK) == I915_OVERLAY_YUV_PLANAR ? > @@ -1246,7 +1246,7 @@ int intel_overlay_attrs_ioctl(struct drm_device *dev, void *data, > attrs->contrast = overlay->contrast; > attrs->saturation = overlay->saturation; > > - if (!IS_GEN2(dev_priv)) { > + if (!GT_GEN(dev_priv, 2)) { > attrs->gamma0 = I915_READ(OGAMC0); > attrs->gamma1 = I915_READ(OGAMC1); > attrs->gamma2 = I915_READ(OGAMC2); > @@ -1270,7 +1270,7 @@ int intel_overlay_attrs_ioctl(struct drm_device *dev, void *data, > update_reg_attrs(overlay, overlay->regs); > > if (attrs->flags & I915_OVERLAY_UPDATE_GAMMA) { > - if (IS_GEN2(dev_priv)) > + if (GT_GEN(dev_priv, 2)) > goto out_unlock; > > if (overlay->active) { > diff --git a/drivers/gpu/drm/i915/intel_panel.c b/drivers/gpu/drm/i915/intel_panel.c > index e6cd7b55c018..e658904c5576 100644 > --- a/drivers/gpu/drm/i915/intel_panel.c > +++ b/drivers/gpu/drm/i915/intel_panel.c > @@ -563,7 +563,7 @@ static void i9xx_set_backlight(const struct drm_connector_state *conn_state, u32 > pci_write_config_byte(dev_priv->drm.pdev, LBPC, lbpc); > } > > - if (IS_GEN4(dev_priv)) { > + if (GT_GEN(dev_priv, 4)) { > mask = BACKLIGHT_DUTY_CYCLE_MASK; > } else { > level <<= 1; > @@ -929,7 +929,7 @@ static void i9xx_enable_backlight(const struct intel_crtc_state *crtc_state, > * 855gm only, but checking for gen2 is safe, as 855gm is the only gen2 > * that has backlight. > */ > - if (IS_GEN2(dev_priv)) > + if (GT_GEN(dev_priv, 2)) > I915_WRITE(BLC_HIST_CTL, BLM_HISTOGRAM_ENABLE); > } > > @@ -1557,7 +1557,7 @@ static int i9xx_setup_backlight(struct intel_connector *connector, enum pipe unu > > ctl = I915_READ(BLC_PWM_CTL); > > - if (IS_GEN2(dev_priv) || IS_I915GM(dev_priv) || IS_I945GM(dev_priv)) > + if (GT_GEN(dev_priv, 2) || IS_I915GM(dev_priv) || IS_I945GM(dev_priv)) > panel->backlight.combination_mode = ctl & BLM_LEGACY_MODE; > > if (IS_PINEVIEW(dev_priv)) > @@ -1886,7 +1886,7 @@ intel_panel_init_backlight_funcs(struct intel_panel *panel) > panel->backlight.get = vlv_get_backlight; > panel->backlight.hz_to_pwm = vlv_hz_to_pwm; > } > - } else if (IS_GEN4(dev_priv)) { > + } else if (GT_GEN(dev_priv, 4)) { > panel->backlight.setup = i965_setup_backlight; > panel->backlight.enable = i965_enable_backlight; > panel->backlight.disable = i965_disable_backlight; > diff --git a/drivers/gpu/drm/i915/intel_pipe_crc.c b/drivers/gpu/drm/i915/intel_pipe_crc.c > index f3c9010e332a..a426978b233d 100644 > --- a/drivers/gpu/drm/i915/intel_pipe_crc.c > +++ b/drivers/gpu/drm/i915/intel_pipe_crc.c > @@ -427,13 +427,13 @@ static int get_new_crc_ctl_reg(struct drm_i915_private *dev_priv, > enum intel_pipe_crc_source *source, u32 *val, > bool set_wa) > { > - if (IS_GEN2(dev_priv)) > + if (GT_GEN(dev_priv, 2)) > return i8xx_pipe_crc_ctl_reg(source, val); > else if (INTEL_GEN(dev_priv) < 5) > return i9xx_pipe_crc_ctl_reg(dev_priv, pipe, source, val); > else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) > return vlv_pipe_crc_ctl_reg(dev_priv, pipe, source, val); > - else if (IS_GEN5(dev_priv) || IS_GEN6(dev_priv)) > + else if (GT_GEN(dev_priv, 5) || GT_GEN(dev_priv, 6)) > return ilk_pipe_crc_ctl_reg(source, val); > else > return ivb_pipe_crc_ctl_reg(dev_priv, pipe, source, val, set_wa); > @@ -544,13 +544,13 @@ static int > intel_is_valid_crc_source(struct drm_i915_private *dev_priv, > const enum intel_pipe_crc_source source) > { > - if (IS_GEN2(dev_priv)) > + if (GT_GEN(dev_priv, 2)) > return i8xx_crc_source_valid(dev_priv, source); > else if (INTEL_GEN(dev_priv) < 5) > return i9xx_crc_source_valid(dev_priv, source); > else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) > return vlv_crc_source_valid(dev_priv, source); > - else if (IS_GEN5(dev_priv) || IS_GEN6(dev_priv)) > + else if (GT_GEN(dev_priv, 5) || GT_GEN(dev_priv, 6)) > return ilk_crc_source_valid(dev_priv, source); > else > return ivb_crc_source_valid(dev_priv, source); > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c > index 9da8ff263d36..74e14d8848f8 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -2273,7 +2273,7 @@ static void i9xx_update_wm(struct intel_crtc *unused_crtc) > > if (IS_I945GM(dev_priv)) > wm_info = &i945_wm_info; > - else if (!IS_GEN2(dev_priv)) > + else if (!GT_GEN(dev_priv, 2)) > wm_info = &i915_wm_info; > else > wm_info = &i830_a_wm_info; > @@ -2287,7 +2287,7 @@ static void i9xx_update_wm(struct intel_crtc *unused_crtc) > crtc->base.primary->state->fb; > int cpp; > > - if (IS_GEN2(dev_priv)) > + if (GT_GEN(dev_priv, 2)) > cpp = 4; > else > cpp = fb->format->cpp[0]; > @@ -2302,7 +2302,7 @@ static void i9xx_update_wm(struct intel_crtc *unused_crtc) > planea_wm = wm_info->max_wm; > } > > - if (IS_GEN2(dev_priv)) > + if (GT_GEN(dev_priv, 2)) > wm_info = &i830_bc_wm_info; > > fifo_size = dev_priv->display.get_fifo_size(dev_priv, PLANE_B); > @@ -2314,7 +2314,7 @@ static void i9xx_update_wm(struct intel_crtc *unused_crtc) > crtc->base.primary->state->fb; > int cpp; > > - if (IS_GEN2(dev_priv)) > + if (GT_GEN(dev_priv, 2)) > cpp = 4; > else > cpp = fb->format->cpp[0]; > @@ -2917,7 +2917,7 @@ static void intel_fixup_spr_wm_latency(struct drm_i915_private *dev_priv, > uint16_t wm[5]) > { > /* ILK sprite LP0 latency is 1300 ns */ > - if (IS_GEN5(dev_priv)) > + if (GT_GEN(dev_priv, 5)) > wm[0] = 13; > } > > @@ -2925,7 +2925,7 @@ static void intel_fixup_cur_wm_latency(struct drm_i915_private *dev_priv, > uint16_t wm[5]) > { > /* ILK cursor LP0 latency is 1300 ns */ > - if (IS_GEN5(dev_priv)) > + if (GT_GEN(dev_priv, 5)) > wm[0] = 13; > } > > @@ -3024,7 +3024,7 @@ static void ilk_setup_wm_latency(struct drm_i915_private *dev_priv) > intel_print_wm_latency(dev_priv, "Sprite", dev_priv->wm.spr_latency); > intel_print_wm_latency(dev_priv, "Cursor", dev_priv->wm.cur_latency); > > - if (IS_GEN6(dev_priv)) > + if (GT_GEN(dev_priv, 6)) > snb_wm_latency_quirk(dev_priv); > } > > @@ -3278,7 +3278,7 @@ static void ilk_wm_merge(struct drm_device *dev, > * What we should check here is whether FBC can be > * enabled sometime later. > */ > - if (IS_GEN5(dev_priv) && !merged->fbc_wm_enabled && > + if (GT_GEN(dev_priv, 5) && !merged->fbc_wm_enabled && > intel_fbc_is_active(dev_priv)) { > for (level = 2; level <= max_level; level++) { > struct intel_wm_level *wm = &merged->wm[level]; > @@ -3716,9 +3716,9 @@ bool intel_can_enable_sagv(struct drm_atomic_state *state) > if (!intel_has_sagv(dev_priv)) > return false; > > - if (IS_GEN9(dev_priv)) > + if (GT_GEN(dev_priv, 9)) > sagv_block_time_us = 30; > - else if (IS_GEN10(dev_priv)) > + else if (GT_GEN(dev_priv, 10)) > sagv_block_time_us = 20; > else > sagv_block_time_us = 10; > @@ -4666,7 +4666,7 @@ skl_compute_plane_wm_params(const struct drm_i915_private *dev_priv, > > wp->plane_blocks_per_line = div_fixed16(interm_pbpl, > wp->y_min_scanlines); > - } else if (wp->x_tiled && IS_GEN9(dev_priv)) { > + } else if (wp->x_tiled && GT_GEN(dev_priv, 9)) { > interm_pbpl = DIV_ROUND_UP(wp->plane_bytes_per_line, > wp->dbuf_block_size); > wp->plane_blocks_per_line = u32_to_fixed16(interm_pbpl); > @@ -4734,13 +4734,13 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv, > selected_result = method2; > } else if (ddb_allocation >= > fixed16_to_u32_round_up(wp->plane_blocks_per_line)) { > - if (IS_GEN9(dev_priv) && > + if (GT_GEN(dev_priv, 9) && > !IS_GEMINILAKE(dev_priv)) > selected_result = min_fixed16(method1, method2); > else > selected_result = method2; > } else if (latency >= wp->linetime_us) { > - if (IS_GEN9(dev_priv) && > + if (GT_GEN(dev_priv, 9) && > !IS_GEMINILAKE(dev_priv)) > selected_result = min_fixed16(method1, method2); > else > @@ -6979,7 +6979,7 @@ static void gen9_enable_rps(struct drm_i915_private *dev_priv) > intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); > > /* Program defaults and thresholds for RPS */ > - if (IS_GEN9(dev_priv)) > + if (GT_GEN(dev_priv, 9)) > I915_WRITE(GEN6_RC_VIDEO_FREQ, > GEN9_FREQUENCY(dev_priv->gt_pm.rps.rp1_freq)); > > @@ -7215,9 +7215,9 @@ static void gen6_enable_rc6(struct drm_i915_private *dev_priv) > > rc6vids = 0; > ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids); > - if (IS_GEN6(dev_priv) && ret) { > + if (GT_GEN(dev_priv, 6) && ret) { > DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n"); > - } else if (IS_GEN6(dev_priv) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) { > + } else if (GT_GEN(dev_priv, 6) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) { > DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n", > GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450); > rc6vids &= 0xffff00; > @@ -7917,7 +7917,7 @@ unsigned long i915_chipset_val(struct drm_i915_private *dev_priv) > { > unsigned long val; > > - if (!IS_GEN5(dev_priv)) > + if (!GT_GEN(dev_priv, 5)) > return 0; > > spin_lock_irq(&mchdev_lock); > @@ -8001,7 +8001,7 @@ static void __i915_update_gfx_val(struct drm_i915_private *dev_priv) > > void i915_update_gfx_val(struct drm_i915_private *dev_priv) > { > - if (!IS_GEN5(dev_priv)) > + if (!GT_GEN(dev_priv, 5)) > return; > > spin_lock_irq(&mchdev_lock); > @@ -8052,7 +8052,7 @@ unsigned long i915_gfx_val(struct drm_i915_private *dev_priv) > { > unsigned long val; > > - if (!IS_GEN5(dev_priv)) > + if (!GT_GEN(dev_priv, 5)) > return 0; > > spin_lock_irq(&mchdev_lock); > @@ -8340,7 +8340,7 @@ void intel_init_gt_powersave(struct drm_i915_private *dev_priv) > intel_freq_opcode(dev_priv, 450)); > > /* After setting max-softlimit, find the overclock max freq */ > - if (IS_GEN6(dev_priv) || > + if (GT_GEN(dev_priv, 6) || > IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv)) { > u32 params = 0; > > @@ -9410,9 +9410,9 @@ void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv) > dev_priv->display.init_clock_gating = ivb_init_clock_gating; > else if (IS_VALLEYVIEW(dev_priv)) > dev_priv->display.init_clock_gating = vlv_init_clock_gating; > - else if (IS_GEN6(dev_priv)) > + else if (GT_GEN(dev_priv, 6)) > dev_priv->display.init_clock_gating = gen6_init_clock_gating; > - else if (IS_GEN5(dev_priv)) > + else if (GT_GEN(dev_priv, 5)) > dev_priv->display.init_clock_gating = ilk_init_clock_gating; > else if (IS_G4X(dev_priv)) > dev_priv->display.init_clock_gating = g4x_init_clock_gating; > @@ -9420,11 +9420,11 @@ void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv) > dev_priv->display.init_clock_gating = i965gm_init_clock_gating; > else if (IS_I965G(dev_priv)) > dev_priv->display.init_clock_gating = i965g_init_clock_gating; > - else if (IS_GEN3(dev_priv)) > + else if (GT_GEN(dev_priv, 3)) > dev_priv->display.init_clock_gating = gen3_init_clock_gating; > else if (IS_I85X(dev_priv) || IS_I865G(dev_priv)) > dev_priv->display.init_clock_gating = i85x_init_clock_gating; > - else if (IS_GEN2(dev_priv)) > + else if (GT_GEN(dev_priv, 2)) > dev_priv->display.init_clock_gating = i830_init_clock_gating; > else { > MISSING_CASE(INTEL_DEVID(dev_priv)); > @@ -9440,7 +9440,7 @@ void intel_init_pm(struct drm_i915_private *dev_priv) > /* For cxsr */ > if (IS_PINEVIEW(dev_priv)) > i915_pineview_get_mem_freq(dev_priv); > - else if (IS_GEN5(dev_priv)) > + else if (GT_GEN(dev_priv, 5)) > i915_ironlake_get_mem_freq(dev_priv); > > /* For FIFO watermark updates */ > @@ -9452,9 +9452,9 @@ void intel_init_pm(struct drm_i915_private *dev_priv) > } else if (HAS_PCH_SPLIT(dev_priv)) { > ilk_setup_wm_latency(dev_priv); > > - if ((IS_GEN5(dev_priv) && dev_priv->wm.pri_latency[1] && > + if ((GT_GEN(dev_priv, 5) && dev_priv->wm.pri_latency[1] && > dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) || > - (!IS_GEN5(dev_priv) && dev_priv->wm.pri_latency[0] && > + (!GT_GEN(dev_priv, 5) && dev_priv->wm.pri_latency[0] && > dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) { > dev_priv->display.compute_pipe_wm = ilk_compute_pipe_wm; > dev_priv->display.compute_intermediate_wm = > @@ -9495,12 +9495,12 @@ void intel_init_pm(struct drm_i915_private *dev_priv) > dev_priv->display.update_wm = NULL; > } else > dev_priv->display.update_wm = pineview_update_wm; > - } else if (IS_GEN4(dev_priv)) { > + } else if (GT_GEN(dev_priv, 4)) { > dev_priv->display.update_wm = i965_update_wm; > - } else if (IS_GEN3(dev_priv)) { > + } else if (GT_GEN(dev_priv, 3)) { > dev_priv->display.update_wm = i9xx_update_wm; > dev_priv->display.get_fifo_size = i9xx_get_fifo_size; > - } else if (IS_GEN2(dev_priv)) { > + } else if (GT_GEN(dev_priv, 2)) { > if (INTEL_INFO(dev_priv)->num_pipes == 1) { > dev_priv->display.update_wm = i845_update_wm; > dev_priv->display.get_fifo_size = i845_get_fifo_size; > diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c > index bc2d88313ed0..cacd54cc00e6 100644 > --- a/drivers/gpu/drm/i915/intel_psr.c > +++ b/drivers/gpu/drm/i915/intel_psr.c > @@ -466,7 +466,7 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp, > if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) { > psr_max_h = 4096; > psr_max_v = 2304; > - } else if (IS_GEN9(dev_priv)) { > + } else if (GT_GEN(dev_priv, 9)) { > psr_max_h = 3640; > psr_max_v = 2304; > } > @@ -574,7 +574,7 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp, > if (dev_priv->psr.psr2_enabled) { > u32 chicken = I915_READ(CHICKEN_TRANS(cpu_transcoder)); > > - if (IS_GEN9(dev_priv) && !IS_GEMINILAKE(dev_priv)) > + if (GT_GEN(dev_priv, 9) && !IS_GEMINILAKE(dev_priv)) > chicken |= (PSR2_VSC_ENABLE_PROG_HEADER > | PSR2_ADD_VERTICAL_LINE_COUNT); > > diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c > index 0e5f49c45298..e2907ae38b7f 100644 > --- a/drivers/gpu/drm/i915/intel_ringbuffer.c > +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c > @@ -123,7 +123,7 @@ gen4_render_ring_flush(struct i915_request *rq, u32 mode) > cmd = MI_FLUSH; > if (mode & EMIT_INVALIDATE) { > cmd |= MI_EXE_FLUSH; > - if (IS_G4X(rq->i915) || IS_GEN5(rq->i915)) > + if (IS_G4X(rq->i915) || GT_GEN(rq->i915, 5)) > cmd |= MI_INVALIDATE_ISP; > } > > @@ -363,7 +363,7 @@ static void intel_ring_setup_status_page(struct intel_engine_cs *engine) > /* The ring status page addresses are no longer next to the rest of > * the ring registers as of gen7. > */ > - if (IS_GEN7(dev_priv)) { > + if (GT_GEN(dev_priv, 7)) { > switch (engine->id) { > /* > * No more rings exist on Gen7. Default case is only to shut up > @@ -384,7 +384,7 @@ static void intel_ring_setup_status_page(struct intel_engine_cs *engine) > mmio = VEBOX_HWS_PGA_GEN7; > break; > } > - } else if (IS_GEN6(dev_priv)) { > + } else if (GT_GEN(dev_priv, 6)) { > mmio = RING_HWS_PGA_GEN6(engine->mmio_base); > } else { > mmio = RING_HWS_PGA(engine->mmio_base); > @@ -643,17 +643,17 @@ static int init_render_ring(struct intel_engine_cs *engine) > > /* Required for the hardware to program scanline values for waiting */ > /* WaEnableFlushTlbInvalidationMode:snb */ > - if (IS_GEN6(dev_priv)) > + if (GT_GEN(dev_priv, 6)) > I915_WRITE(GFX_MODE, > _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT)); > > /* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */ > - if (IS_GEN7(dev_priv)) > + if (GT_GEN(dev_priv, 7)) > I915_WRITE(GFX_MODE_GEN7, > _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT) | > _MASKED_BIT_ENABLE(GFX_REPLAY_MODE)); > > - if (IS_GEN6(dev_priv)) { > + if (GT_GEN(dev_priv, 6)) { > /* From the Sandybridge PRM, volume 1 part 3, page 24: > * "If this bit is set, STCunit will have LRA as replacement > * policy. [...] This bit must be reset. LRA replacement > @@ -1531,7 +1531,7 @@ static inline int mi_set_context(struct i915_request *rq, u32 flags) > enum intel_engine_id id; > const int num_rings = > /* Use an extended w/a on gen7 if signalling from other rings */ > - (HAS_LEGACY_SEMAPHORES(i915) && IS_GEN7(i915)) ? > + (HAS_LEGACY_SEMAPHORES(i915) && GT_GEN(i915, 7)) ? > INTEL_INFO(i915)->num_rings - 1 : > 0; > bool force_restore = false; > @@ -1546,7 +1546,7 @@ static inline int mi_set_context(struct i915_request *rq, u32 flags) > flags |= MI_SAVE_EXT_STATE_EN | MI_RESTORE_EXT_STATE_EN; > > len = 4; > - if (IS_GEN7(i915)) > + if (GT_GEN(i915, 7)) > len += 2 + (num_rings ? 4*num_rings + 6 : 0); > if (flags & MI_FORCE_RESTORE) { > GEM_BUG_ON(flags & MI_RESTORE_INHIBIT); > @@ -1560,7 +1560,7 @@ static inline int mi_set_context(struct i915_request *rq, u32 flags) > return PTR_ERR(cs); > > /* WaProgramMiArbOnOffAroundMiSetContext:ivb,vlv,hsw,bdw,chv */ > - if (IS_GEN7(i915)) { > + if (GT_GEN(i915, 7)) { > *cs++ = MI_ARB_ON_OFF | MI_ARB_DISABLE; > if (num_rings) { > struct intel_engine_cs *signaller; > @@ -1607,7 +1607,7 @@ static inline int mi_set_context(struct i915_request *rq, u32 flags) > */ > *cs++ = MI_NOOP; > > - if (IS_GEN7(i915)) { > + if (GT_GEN(i915, 7)) { > if (num_rings) { > struct intel_engine_cs *signaller; > i915_reg_t last_reg = {}; /* keep gcc quiet */ > @@ -2230,9 +2230,9 @@ int intel_init_render_ring_buffer(struct intel_engine_cs *engine) > if (INTEL_GEN(dev_priv) >= 6) { > engine->init_context = intel_rcs_ctx_init; > engine->emit_flush = gen7_render_ring_flush; > - if (IS_GEN6(dev_priv)) > + if (GT_GEN(dev_priv, 6)) > engine->emit_flush = gen6_render_ring_flush; > - } else if (IS_GEN5(dev_priv)) { > + } else if (GT_GEN(dev_priv, 5)) { > engine->emit_flush = gen4_render_ring_flush; > } else { > if (INTEL_GEN(dev_priv) < 4) > @@ -2262,13 +2262,13 @@ int intel_init_bsd_ring_buffer(struct intel_engine_cs *engine) > > if (INTEL_GEN(dev_priv) >= 6) { > /* gen6 bsd needs a special wa for tail updates */ > - if (IS_GEN6(dev_priv)) > + if (GT_GEN(dev_priv, 6)) > engine->set_default_submission = gen6_bsd_set_default_submission; > engine->emit_flush = gen6_bsd_ring_flush; > engine->irq_enable_mask = GT_BSD_USER_INTERRUPT; > } else { > engine->emit_flush = bsd_ring_flush; > - if (IS_GEN5(dev_priv)) > + if (GT_GEN(dev_priv, 5)) > engine->irq_enable_mask = ILK_BSD_USER_INTERRUPT; > else > engine->irq_enable_mask = I915_BSD_USER_INTERRUPT; > diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h > index 8a2270b209b0..e6b24cbf3b04 100644 > --- a/drivers/gpu/drm/i915/intel_ringbuffer.h > +++ b/drivers/gpu/drm/i915/intel_ringbuffer.h > @@ -93,11 +93,11 @@ hangcheck_action_to_str(const enum intel_engine_hangcheck_action a) > #define I915_MAX_SUBSLICES 8 > > #define instdone_slice_mask(dev_priv__) \ > - (IS_GEN7(dev_priv__) ? \ > + (GT_GEN(dev_priv__, 7) ? \ > 1 : INTEL_INFO(dev_priv__)->sseu.slice_mask) > > #define instdone_subslice_mask(dev_priv__) \ > - (IS_GEN7(dev_priv__) ? \ > + (GT_GEN(dev_priv__, 7) ? \ > 1 : INTEL_INFO(dev_priv__)->sseu.subslice_mask[0]) > > #define for_each_instdone_slice_subslice(dev_priv__, slice__, subslice__) \ > diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c > index 6c453366cd24..b164a2c4b058 100644 > --- a/drivers/gpu/drm/i915/intel_runtime_pm.c > +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c > @@ -3027,7 +3027,7 @@ static uint32_t get_allowed_dc_mask(const struct drm_i915_private *dev_priv, > * suspend/resume, so allow it unconditionally. > */ > mask = DC_STATE_EN_DC9; > - } else if (IS_GEN10(dev_priv) || IS_GEN9_BC(dev_priv)) { > + } else if (GT_GEN(dev_priv, 10) || IS_GEN9_BC(dev_priv)) { > max_dc = 2; > mask = 0; > } else if (IS_GEN9_LP(dev_priv)) { > diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c > index f15b27983fbf..049e679e4145 100644 > --- a/drivers/gpu/drm/i915/intel_sprite.c > +++ b/drivers/gpu/drm/i915/intel_sprite.c > @@ -1083,7 +1083,7 @@ static u32 g4x_sprite_ctl(const struct intel_crtc_state *crtc_state, > > dvscntr = DVS_ENABLE | DVS_GAMMA_ENABLE; > > - if (IS_GEN6(dev_priv)) > + if (GT_GEN(dev_priv, 6)) > dvscntr |= DVS_TRICKLE_FEED_DISABLE; > > switch (fb->format->format) { > @@ -1979,7 +1979,7 @@ static bool skl_plane_has_planar(struct drm_i915_private *dev_priv, > if (IS_SKYLAKE(dev_priv) || IS_BROXTON(dev_priv)) > return false; > > - if (IS_GEN9(dev_priv) && !IS_GEMINILAKE(dev_priv) && pipe == PIPE_C) > + if (GT_GEN(dev_priv, 9) && !IS_GEMINILAKE(dev_priv) && pipe == PIPE_C) > return false; > > if (plane_id != PLANE_PRIMARY && plane_id != PLANE_SPRITE0) > @@ -2188,7 +2188,7 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv, > plane->check_plane = g4x_sprite_check; > > modifiers = i9xx_plane_format_modifiers; > - if (IS_GEN6(dev_priv)) { > + if (GT_GEN(dev_priv, 6)) { > formats = snb_plane_formats; > num_formats = ARRAY_SIZE(snb_plane_formats); > > diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c > index b34c318b238d..9eca84e7baa5 100644 > --- a/drivers/gpu/drm/i915/intel_uc.c > +++ b/drivers/gpu/drm/i915/intel_uc.c > @@ -354,7 +354,7 @@ int intel_uc_init_hw(struct drm_i915_private *i915) > > /* WaEnableuKernelHeaderValidFix:skl */ > /* WaEnableGuCBootHashCheckNotSet:skl,bxt,kbl */ > - if (IS_GEN9(i915)) > + if (GT_GEN(i915, 9)) > attempts = 3; > else > attempts = 1; > diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c > index 4ffe26cc3c3f..2e98416467a0 100644 > --- a/drivers/gpu/drm/i915/intel_uncore.c > +++ b/drivers/gpu/drm/i915/intel_uncore.c > @@ -528,7 +528,7 @@ check_for_unclaimed_mmio(struct drm_i915_private *dev_priv) > if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) > ret |= vlv_check_for_unclaimed_mmio(dev_priv); > > - if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv)) > + if (GT_GEN(dev_priv, 6) || GT_GEN(dev_priv, 7)) > ret |= gen6_check_for_fifo_debug(dev_priv); > > return ret; > @@ -556,7 +556,7 @@ static void __intel_uncore_early_sanitize(struct drm_i915_private *dev_priv, > dev_priv->uncore.funcs.force_wake_get(dev_priv, > restore_forcewake); > > - if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv)) > + if (GT_GEN(dev_priv, 6) || GT_GEN(dev_priv, 7)) > dev_priv->uncore.fifo_count = > fifo_free_entries(dev_priv); > spin_unlock_irq(&dev_priv->uncore.lock); > @@ -1398,7 +1398,7 @@ static void intel_uncore_fw_domains_init(struct drm_i915_private *dev_priv) > if (INTEL_GEN(dev_priv) <= 5 || intel_vgpu_active(dev_priv)) > return; > > - if (IS_GEN6(dev_priv)) { > + if (GT_GEN(dev_priv, 6)) { > dev_priv->uncore.fw_reset = 0; > dev_priv->uncore.fw_set = FORCEWAKE_KERNEL; > dev_priv->uncore.fw_clear = 0; > @@ -1437,7 +1437,7 @@ static void intel_uncore_fw_domains_init(struct drm_i915_private *dev_priv) > FORCEWAKE_MEDIA_VEBOX_GEN11(i), > FORCEWAKE_ACK_MEDIA_VEBOX_GEN11(i)); > } > - } else if (IS_GEN10(dev_priv) || IS_GEN9(dev_priv)) { > + } else if (GT_GEN(dev_priv, 10) || GT_GEN(dev_priv, 9)) { > dev_priv->uncore.funcs.force_wake_get = > fw_domains_get_with_fallback; > dev_priv->uncore.funcs.force_wake_put = fw_domains_put; > @@ -1503,7 +1503,7 @@ static void intel_uncore_fw_domains_init(struct drm_i915_private *dev_priv) > fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER, > FORCEWAKE, FORCEWAKE_ACK); > } > - } else if (IS_GEN6(dev_priv)) { > + } else if (GT_GEN(dev_priv, 6)) { > dev_priv->uncore.funcs.force_wake_get = > fw_domains_get_with_thread_status; > dev_priv->uncore.funcs.force_wake_put = fw_domains_put; > @@ -1570,7 +1570,7 @@ void intel_uncore_init(struct drm_i915_private *dev_priv) > if (GT_GEN_RANGE(dev_priv, 2, 4) || intel_vgpu_active(dev_priv)) { > ASSIGN_WRITE_MMIO_VFUNCS(dev_priv, gen2); > ASSIGN_READ_MMIO_VFUNCS(dev_priv, gen2); > - } else if (IS_GEN5(dev_priv)) { > + } else if (GT_GEN(dev_priv, 5)) { > ASSIGN_WRITE_MMIO_VFUNCS(dev_priv, gen5); > ASSIGN_READ_MMIO_VFUNCS(dev_priv, gen5); > } else if (GT_GEN_RANGE(dev_priv, 6, 7)) { > @@ -1582,7 +1582,7 @@ void intel_uncore_init(struct drm_i915_private *dev_priv) > } else { > ASSIGN_READ_MMIO_VFUNCS(dev_priv, gen6); > } > - } else if (IS_GEN8(dev_priv)) { > + } else if (GT_GEN(dev_priv, 8)) { > if (IS_CHERRYVIEW(dev_priv)) { > ASSIGN_FW_DOMAINS_TABLE(__chv_fw_ranges); > ASSIGN_WRITE_MMIO_VFUNCS(dev_priv, fwtable); > @@ -2173,7 +2173,7 @@ static reset_func intel_get_gpu_reset(struct drm_i915_private *dev_priv) > return gen8_reset_engines; > else if (INTEL_GEN(dev_priv) >= 6) > return gen6_reset_engines; > - else if (IS_GEN5(dev_priv)) > + else if (GT_GEN(dev_priv, 5)) > return ironlake_do_reset; > else if (IS_G4X(dev_priv)) > return g4x_do_reset; > @@ -2341,7 +2341,7 @@ intel_uncore_forcewake_for_write(struct drm_i915_private *dev_priv, > fw_domains = __gen11_fwtable_reg_write_fw_domains(offset); > } else if (HAS_FWTABLE(dev_priv) && !IS_VALLEYVIEW(dev_priv)) { > fw_domains = __fwtable_reg_write_fw_domains(offset); > - } else if (IS_GEN8(dev_priv)) { > + } else if (GT_GEN(dev_priv, 8)) { > fw_domains = __gen8_reg_write_fw_domains(offset); > } else if (GT_GEN_RANGE(dev_priv, 6, 7)) { > fw_domains = FORCEWAKE_RENDER; > diff --git a/drivers/gpu/drm/i915/intel_wopcm.c b/drivers/gpu/drm/i915/intel_wopcm.c > index 92cb82dd0c07..3987207cddd0 100644 > --- a/drivers/gpu/drm/i915/intel_wopcm.c > +++ b/drivers/gpu/drm/i915/intel_wopcm.c > @@ -130,11 +130,11 @@ static inline int check_hw_restriction(struct drm_i915_private *i915, > { > int err = 0; > > - if (IS_GEN9(i915)) > + if (GT_GEN(i915, 9)) > err = gen9_check_dword_gap(guc_wopcm_base, guc_wopcm_size); > > if (!err && > - (IS_GEN9(i915) || IS_CNL_REVID(i915, CNL_REVID_A0, CNL_REVID_A0))) > + (GT_GEN(i915, 9) || IS_CNL_REVID(i915, CNL_REVID_A0, CNL_REVID_A0))) > err = gen9_check_huc_fw_fits(guc_wopcm_size, huc_fw_size); > > return err; > -- > 2.19.1.1.g56c4683e68 > _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [PATCH v2 3/7] drm/i915: replace IS_GEN<N> with GT_GEN(..., N) 2018-11-21 22:20 ` Rodrigo Vivi @ 2018-11-23 12:42 ` Jani Nikula 2018-11-26 18:49 ` Rodrigo Vivi 0 siblings, 1 reply; 38+ messages in thread From: Jani Nikula @ 2018-11-23 12:42 UTC (permalink / raw) To: Rodrigo Vivi, Lucas De Marchi; +Cc: intel-gfx On Wed, 21 Nov 2018, Rodrigo Vivi <rodrigo.vivi@intel.com> wrote: > On Tue, Nov 06, 2018 at 01:51:19PM -0800, Lucas De Marchi wrote: >> Define GT_GEN() similarly to our GT_GEN_RANGE() and convert users of >> IS_GEN<N> to pss the gen as parameter. This prepares for the addition >> of display gen checks by renaming the IS_GENx() and using common code >> for all the n gens. >> >> The following spatch was used to convert the users of these macros: >> >> @@ >> expression e; >> @@ >> ( >> - IS_GEN2(e) >> + GT_GEN(e, 2) >> | >> - IS_GEN3(e) >> + GT_GEN(e, 3) >> | >> - IS_GEN4(e) >> + GT_GEN(e, 4) >> | >> - IS_GEN5(e) >> + GT_GEN(e, 5) >> | >> - IS_GEN6(e) >> + GT_GEN(e, 6) >> | >> - IS_GEN7(e) >> + GT_GEN(e, 7) >> | >> - IS_GEN8(e) >> + GT_GEN(e, 8) >> | >> - IS_GEN9(e) >> + GT_GEN(e, 9) >> | >> - IS_GEN10(e) >> + GT_GEN(e, 10) >> | >> - IS_GEN11(e) >> + GT_GEN(e, 11) >> ) >> >> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> > > Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> I think this is a contentious patch. I am not sure I agree with the change. Please hold off on merging until further discussion. Thanks, Jani. -- Jani Nikula, Intel Open Source Graphics Center _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [PATCH v2 3/7] drm/i915: replace IS_GEN<N> with GT_GEN(..., N) 2018-11-23 12:42 ` Jani Nikula @ 2018-11-26 18:49 ` Rodrigo Vivi 2018-11-27 8:31 ` Jani Nikula 0 siblings, 1 reply; 38+ messages in thread From: Rodrigo Vivi @ 2018-11-26 18:49 UTC (permalink / raw) To: Jani Nikula; +Cc: intel-gfx, Lucas De Marchi On Fri, Nov 23, 2018 at 02:42:59PM +0200, Jani Nikula wrote: > On Wed, 21 Nov 2018, Rodrigo Vivi <rodrigo.vivi@intel.com> wrote: > > On Tue, Nov 06, 2018 at 01:51:19PM -0800, Lucas De Marchi wrote: > >> Define GT_GEN() similarly to our GT_GEN_RANGE() and convert users of > >> IS_GEN<N> to pss the gen as parameter. This prepares for the addition > >> of display gen checks by renaming the IS_GENx() and using common code > >> for all the n gens. > >> > >> The following spatch was used to convert the users of these macros: > >> > >> @@ > >> expression e; > >> @@ > >> ( > >> - IS_GEN2(e) > >> + GT_GEN(e, 2) > >> | > >> - IS_GEN3(e) > >> + GT_GEN(e, 3) > >> | > >> - IS_GEN4(e) > >> + GT_GEN(e, 4) > >> | > >> - IS_GEN5(e) > >> + GT_GEN(e, 5) > >> | > >> - IS_GEN6(e) > >> + GT_GEN(e, 6) > >> | > >> - IS_GEN7(e) > >> + GT_GEN(e, 7) > >> | > >> - IS_GEN8(e) > >> + GT_GEN(e, 8) > >> | > >> - IS_GEN9(e) > >> + GT_GEN(e, 9) > >> | > >> - IS_GEN10(e) > >> + GT_GEN(e, 10) > >> | > >> - IS_GEN11(e) > >> + GT_GEN(e, 11) > >> ) > >> > >> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> > > > > Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> > > I think this is a contentious patch. I am not sure I agree with the > change. Please hold off on merging until further discussion. Yeap. I just reviewed the ones that no body raised any issue yet. So it would pop up on their inbox again for a double change to complain. I didn't add reviewed on the patches we are still discussing exactly to avoid merging it without finishing the discussions. Thanks, Rodrigo. > > > Thanks, > Jani. > > -- > Jani Nikula, Intel Open Source Graphics Center _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [PATCH v2 3/7] drm/i915: replace IS_GEN<N> with GT_GEN(..., N) 2018-11-26 18:49 ` Rodrigo Vivi @ 2018-11-27 8:31 ` Jani Nikula 2018-11-28 0:09 ` Rodrigo Vivi 0 siblings, 1 reply; 38+ messages in thread From: Jani Nikula @ 2018-11-27 8:31 UTC (permalink / raw) To: Rodrigo Vivi; +Cc: intel-gfx, Lucas De Marchi On Mon, 26 Nov 2018, Rodrigo Vivi <rodrigo.vivi@intel.com> wrote: > On Fri, Nov 23, 2018 at 02:42:59PM +0200, Jani Nikula wrote: >> On Wed, 21 Nov 2018, Rodrigo Vivi <rodrigo.vivi@intel.com> wrote: >> > On Tue, Nov 06, 2018 at 01:51:19PM -0800, Lucas De Marchi wrote: >> >> Define GT_GEN() similarly to our GT_GEN_RANGE() and convert users of >> >> IS_GEN<N> to pss the gen as parameter. This prepares for the addition >> >> of display gen checks by renaming the IS_GENx() and using common code >> >> for all the n gens. >> >> >> >> The following spatch was used to convert the users of these macros: >> >> >> >> @@ >> >> expression e; >> >> @@ >> >> ( >> >> - IS_GEN2(e) >> >> + GT_GEN(e, 2) >> >> | >> >> - IS_GEN3(e) >> >> + GT_GEN(e, 3) >> >> | >> >> - IS_GEN4(e) >> >> + GT_GEN(e, 4) >> >> | >> >> - IS_GEN5(e) >> >> + GT_GEN(e, 5) >> >> | >> >> - IS_GEN6(e) >> >> + GT_GEN(e, 6) >> >> | >> >> - IS_GEN7(e) >> >> + GT_GEN(e, 7) >> >> | >> >> - IS_GEN8(e) >> >> + GT_GEN(e, 8) >> >> | >> >> - IS_GEN9(e) >> >> + GT_GEN(e, 9) >> >> | >> >> - IS_GEN10(e) >> >> + GT_GEN(e, 10) >> >> | >> >> - IS_GEN11(e) >> >> + GT_GEN(e, 11) >> >> ) >> >> >> >> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> >> > >> > Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> >> >> I think this is a contentious patch. I am not sure I agree with the >> change. Please hold off on merging until further discussion. > > Yeap. I just reviewed the ones that no body raised any issue yet. > So it would pop up on their inbox again for a double change to complain. > > I didn't add reviewed on the patches we are still discussing exactly > to avoid merging it without finishing the discussions. I don't think we've reached consensus on IS_GEN -> GT_GEN. BR, Jani. > > Thanks, > Rodrigo. > >> >> >> Thanks, >> Jani. >> >> -- >> Jani Nikula, Intel Open Source Graphics Center -- Jani Nikula, Intel Open Source Graphics Center _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [PATCH v2 3/7] drm/i915: replace IS_GEN<N> with GT_GEN(..., N) 2018-11-27 8:31 ` Jani Nikula @ 2018-11-28 0:09 ` Rodrigo Vivi 0 siblings, 0 replies; 38+ messages in thread From: Rodrigo Vivi @ 2018-11-28 0:09 UTC (permalink / raw) To: Jani Nikula; +Cc: intel-gfx, Lucas De Marchi On Tue, Nov 27, 2018 at 10:31:49AM +0200, Jani Nikula wrote: > On Mon, 26 Nov 2018, Rodrigo Vivi <rodrigo.vivi@intel.com> wrote: > > On Fri, Nov 23, 2018 at 02:42:59PM +0200, Jani Nikula wrote: > >> On Wed, 21 Nov 2018, Rodrigo Vivi <rodrigo.vivi@intel.com> wrote: > >> > On Tue, Nov 06, 2018 at 01:51:19PM -0800, Lucas De Marchi wrote: > >> >> Define GT_GEN() similarly to our GT_GEN_RANGE() and convert users of > >> >> IS_GEN<N> to pss the gen as parameter. This prepares for the addition > >> >> of display gen checks by renaming the IS_GENx() and using common code > >> >> for all the n gens. > >> >> > >> >> The following spatch was used to convert the users of these macros: > >> >> > >> >> @@ > >> >> expression e; > >> >> @@ > >> >> ( > >> >> - IS_GEN2(e) > >> >> + GT_GEN(e, 2) > >> >> | > >> >> - IS_GEN3(e) > >> >> + GT_GEN(e, 3) > >> >> | > >> >> - IS_GEN4(e) > >> >> + GT_GEN(e, 4) > >> >> | > >> >> - IS_GEN5(e) > >> >> + GT_GEN(e, 5) > >> >> | > >> >> - IS_GEN6(e) > >> >> + GT_GEN(e, 6) > >> >> | > >> >> - IS_GEN7(e) > >> >> + GT_GEN(e, 7) > >> >> | > >> >> - IS_GEN8(e) > >> >> + GT_GEN(e, 8) > >> >> | > >> >> - IS_GEN9(e) > >> >> + GT_GEN(e, 9) > >> >> | > >> >> - IS_GEN10(e) > >> >> + GT_GEN(e, 10) > >> >> | > >> >> - IS_GEN11(e) > >> >> + GT_GEN(e, 11) > >> >> ) > >> >> > >> >> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> > >> > > >> > Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> > >> > >> I think this is a contentious patch. I am not sure I agree with the > >> change. Please hold off on merging until further discussion. > > > > Yeap. I just reviewed the ones that no body raised any issue yet. > > So it would pop up on their inbox again for a double change to complain. > > > > I didn't add reviewed on the patches we are still discussing exactly > > to avoid merging it without finishing the discussions. > > I don't think we've reached consensus on IS_GEN -> GT_GEN. yeap... I just noticed this on the other branch of this thread :( > > BR, > Jani. > > > > > > Thanks, > > Rodrigo. > > > >> > >> > >> Thanks, > >> Jani. > >> > >> -- > >> Jani Nikula, Intel Open Source Graphics Center > > -- > Jani Nikula, Intel Open Source Graphics Center _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 38+ messages in thread
* [PATCH v2 4/7] drm/i915: rename IS_GEN9_* to GT_GEN9_* 2018-11-06 21:51 [PATCH v2 0/7] Make GEN macros more similar Lucas De Marchi ` (2 preceding siblings ...) 2018-11-06 21:51 ` [PATCH v2 3/7] drm/i915: replace IS_GEN<N> with GT_GEN(..., N) Lucas De Marchi @ 2018-11-06 21:51 ` Lucas De Marchi 2018-11-21 22:22 ` Rodrigo Vivi 2018-11-06 21:51 ` [PATCH v2 5/7] drm/i915: replace gen checks using operators by GT_GEN/GT_GEN_RANGE Lucas De Marchi ` (7 subsequent siblings) 11 siblings, 1 reply; 38+ messages in thread From: Lucas De Marchi @ 2018-11-06 21:51 UTC (permalink / raw) To: intel-gfx; +Cc: Rodrigo Vivi Like it was done for the generic IS_GEN -> GT_GEN rename, but since the LP/BC variants only exist in gen 9, keep the single macro definition. Also move the define to be together with GT_GEN(). Users were converted with: sed -i 's/IS_GEN9_/GT_GEN9_/g' \ drivers/gpu/drm/i915/*.{c,h} \ drivers/gpu/drm/i915/*/*.{c,h} Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> --- drivers/gpu/drm/i915/i915_debugfs.c | 22 ++++++------- drivers/gpu/drm/i915/i915_drv.c | 10 +++--- drivers/gpu/drm/i915/i915_drv.h | 9 ++--- drivers/gpu/drm/i915/i915_gem_gtt.c | 6 ++-- drivers/gpu/drm/i915/i915_irq.c | 12 +++---- drivers/gpu/drm/i915/i915_reg.h | 4 +-- drivers/gpu/drm/i915/intel_bios.c | 4 +-- drivers/gpu/drm/i915/intel_cdclk.c | 10 +++--- drivers/gpu/drm/i915/intel_color.c | 2 +- drivers/gpu/drm/i915/intel_csr.c | 2 +- drivers/gpu/drm/i915/intel_ddi.c | 42 ++++++++++++------------ drivers/gpu/drm/i915/intel_device_info.c | 12 +++---- drivers/gpu/drm/i915/intel_display.c | 18 +++++----- drivers/gpu/drm/i915/intel_dp.c | 28 ++++++++-------- drivers/gpu/drm/i915/intel_dp_mst.c | 2 +- drivers/gpu/drm/i915/intel_dpll_mgr.c | 4 +-- drivers/gpu/drm/i915/intel_fbc.c | 2 +- drivers/gpu/drm/i915/intel_guc_fw.c | 2 +- drivers/gpu/drm/i915/intel_hdmi.c | 4 +-- drivers/gpu/drm/i915/intel_i2c.c | 12 +++---- drivers/gpu/drm/i915/intel_mocs.c | 4 +-- drivers/gpu/drm/i915/intel_panel.c | 2 +- drivers/gpu/drm/i915/intel_pm.c | 18 +++++----- drivers/gpu/drm/i915/intel_runtime_pm.c | 22 ++++++------- drivers/gpu/drm/i915/intel_wopcm.c | 2 +- drivers/gpu/drm/i915/intel_workarounds.c | 4 +-- drivers/gpu/drm/i915/vlv_dsi.c | 40 +++++++++++----------- 27 files changed, 150 insertions(+), 149 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index 2514ec4d97d4..5e4a934c0dea 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -1123,7 +1123,7 @@ static int i915_frequency_info(struct seq_file *m, void *unused) int max_freq; rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS); - if (IS_GEN9_LP(dev_priv)) { + if (GT_GEN9_LP(dev_priv)) { rp_state_cap = I915_READ(BXT_RP_STATE_CAP); gt_perf_status = I915_READ(BXT_GT_PERF_STATUS); } else { @@ -1230,22 +1230,22 @@ static int i915_frequency_info(struct seq_file *m, void *unused) seq_printf(m, "Down threshold: %d%%\n", rps->power.down_threshold); - max_freq = (IS_GEN9_LP(dev_priv) ? rp_state_cap >> 0 : + max_freq = (GT_GEN9_LP(dev_priv) ? rp_state_cap >> 0 : rp_state_cap >> 16) & 0xff; - max_freq *= (IS_GEN9_BC(dev_priv) || + max_freq *= (GT_GEN9_BC(dev_priv) || INTEL_GEN(dev_priv) >= 10 ? GEN9_FREQ_SCALER : 1); seq_printf(m, "Lowest (RPN) frequency: %dMHz\n", intel_gpu_freq(dev_priv, max_freq)); max_freq = (rp_state_cap & 0xff00) >> 8; - max_freq *= (IS_GEN9_BC(dev_priv) || + max_freq *= (GT_GEN9_BC(dev_priv) || INTEL_GEN(dev_priv) >= 10 ? GEN9_FREQ_SCALER : 1); seq_printf(m, "Nominal (RP1) frequency: %dMHz\n", intel_gpu_freq(dev_priv, max_freq)); - max_freq = (IS_GEN9_LP(dev_priv) ? rp_state_cap >> 16 : + max_freq = (GT_GEN9_LP(dev_priv) ? rp_state_cap >> 16 : rp_state_cap >> 0) & 0xff; - max_freq *= (IS_GEN9_BC(dev_priv) || + max_freq *= (GT_GEN9_BC(dev_priv) || INTEL_GEN(dev_priv) >= 10 ? GEN9_FREQ_SCALER : 1); seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n", intel_gpu_freq(dev_priv, max_freq)); @@ -1824,7 +1824,7 @@ static int i915_ring_freq_table(struct seq_file *m, void *unused) min_gpu_freq = rps->min_freq; max_gpu_freq = rps->max_freq; - if (IS_GEN9_BC(dev_priv) || INTEL_GEN(dev_priv) >= 10) { + if (GT_GEN9_BC(dev_priv) || INTEL_GEN(dev_priv) >= 10) { /* Convert GT frequency to 50 HZ units */ min_gpu_freq /= GEN9_FREQ_SCALER; max_gpu_freq /= GEN9_FREQ_SCALER; @@ -1839,7 +1839,7 @@ static int i915_ring_freq_table(struct seq_file *m, void *unused) &ia_freq); seq_printf(m, "%d\t\t%d\t\t\t\t%d\n", intel_gpu_freq(dev_priv, (gpu_freq * - (IS_GEN9_BC(dev_priv) || + (GT_GEN9_BC(dev_priv) || INTEL_GEN(dev_priv) >= 10 ? GEN9_FREQ_SCALER : 1))), ((ia_freq >> 0) & 0xff) * 100, @@ -2922,7 +2922,7 @@ static int i915_dmc_info(struct seq_file *m, void *unused) seq_printf(m, "DC3 -> DC5 count: %d\n", I915_READ(IS_BROXTON(dev_priv) ? BXT_CSR_DC3_DC5_COUNT : SKL_CSR_DC3_DC5_COUNT)); - if (!IS_GEN9_LP(dev_priv)) + if (!GT_GEN9_LP(dev_priv)) seq_printf(m, "DC5 -> DC6 count: %d\n", I915_READ(SKL_CSR_DC5_DC6_COUNT)); @@ -4423,14 +4423,14 @@ static void gen9_sseu_device_status(struct drm_i915_private *dev_priv, sseu->slice_mask |= BIT(s); - if (IS_GEN9_BC(dev_priv)) + if (GT_GEN9_BC(dev_priv)) sseu->subslice_mask[s] = INTEL_INFO(dev_priv)->sseu.subslice_mask[s]; for (ss = 0; ss < info->sseu.max_subslices; ss++) { unsigned int eu_cnt; - if (IS_GEN9_LP(dev_priv)) { + if (GT_GEN9_LP(dev_priv)) { if (!(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss)))) /* skip disabled subslice */ continue; diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index d2bdd7112c5d..8ff2acdec1f5 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -1322,7 +1322,7 @@ intel_get_dram_info(struct drm_i915_private *dev_priv) * This is only used for the level 0 watermark latency * w/a which does not apply to bxt/glk. */ - dram_info->is_16gb_dimm = !IS_GEN9_LP(dev_priv); + dram_info->is_16gb_dimm = !GT_GEN9_LP(dev_priv); if (INTEL_GEN(dev_priv) < 9 || IS_GEMINILAKE(dev_priv)) return; @@ -1962,7 +1962,7 @@ static int i915_drm_suspend_late(struct drm_device *dev, bool hibernation) get_suspend_mode(dev_priv, hibernation)); ret = 0; - if (INTEL_GEN(dev_priv) >= 11 || IS_GEN9_LP(dev_priv)) + if (INTEL_GEN(dev_priv) >= 11 || GT_GEN9_LP(dev_priv)) bxt_enable_dc9(dev_priv); else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) hsw_enable_pc8(dev_priv); @@ -2152,7 +2152,7 @@ static int i915_drm_resume_early(struct drm_device *dev) intel_uncore_resume_early(dev_priv); - if (INTEL_GEN(dev_priv) >= 11 || IS_GEN9_LP(dev_priv)) { + if (INTEL_GEN(dev_priv) >= 11 || GT_GEN9_LP(dev_priv)) { gen9_sanitize_dc_state(dev_priv); bxt_disable_dc9(dev_priv); } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { @@ -2922,7 +2922,7 @@ static int intel_runtime_suspend(struct device *kdev) if (INTEL_GEN(dev_priv) >= 11) { icl_display_core_uninit(dev_priv); bxt_enable_dc9(dev_priv); - } else if (IS_GEN9_LP(dev_priv)) { + } else if (GT_GEN9_LP(dev_priv)) { bxt_display_core_uninit(dev_priv); bxt_enable_dc9(dev_priv); } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { @@ -3018,7 +3018,7 @@ static int intel_runtime_resume(struct device *kdev) DC_STATE_EN_UPTO_DC5) gen9_enable_dc5(dev_priv); } - } else if (IS_GEN9_LP(dev_priv)) { + } else if (GT_GEN9_LP(dev_priv)) { bxt_disable_dc9(dev_priv); bxt_display_core_init(dev_priv, true); if (dev_priv->csr.dmc_payload && diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index f11aad5cd7fb..08c879f17b40 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -2360,6 +2360,8 @@ intel_info(const struct drm_i915_private *dev_priv) #define REVID_FOREVER 0xff #define INTEL_REVID(dev_priv) ((dev_priv)->drm.pdev->revision) +#define IS_LP(dev_priv) (INTEL_INFO(dev_priv)->is_lp) + #define GEN_FOREVER (0) #define INTEL_GEN_MASK(s, e) ( \ @@ -2381,6 +2383,9 @@ intel_info(const struct drm_i915_private *dev_priv) (BUILD_BUG_ON_ZERO(!__builtin_constant_p(n)) + \ (!!((dev_priv)->info.gen_mask & BIT((n) - 1)))) +#define GT_GEN9_LP(dev_priv) (GT_GEN(dev_priv, 9) && IS_LP(dev_priv)) +#define GT_GEN9_BC(dev_priv) (GT_GEN(dev_priv, 9) && !IS_LP(dev_priv)) + /* * Return true if revision is in range [since,until] inclusive. * @@ -2532,10 +2537,6 @@ intel_info(const struct drm_i915_private *dev_priv) #define IS_ICL_REVID(p, since, until) \ (IS_ICELAKE(p) && IS_REVID(p, since, until)) -#define IS_LP(dev_priv) (INTEL_INFO(dev_priv)->is_lp) -#define IS_GEN9_LP(dev_priv) (GT_GEN(dev_priv, 9) && IS_LP(dev_priv)) -#define IS_GEN9_BC(dev_priv) (GT_GEN(dev_priv, 9) && !IS_LP(dev_priv)) - #define ENGINE_MASK(id) BIT(id) #define RENDER_RING ENGINE_MASK(RCS) #define BSD_RING ENGINE_MASK(VCS) diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c index 1723f374c5a8..4ae6166c6593 100644 --- a/drivers/gpu/drm/i915/i915_gem_gtt.c +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c @@ -2168,7 +2168,7 @@ static void gtt_write_workarounds(struct drm_i915_private *dev_priv) I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW); else if (IS_CHERRYVIEW(dev_priv)) I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_CHV); - else if (IS_GEN9_LP(dev_priv)) + else if (GT_GEN9_LP(dev_priv)) I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_BXT); else if (INTEL_GEN(dev_priv) >= 9) I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_SKL); @@ -3002,7 +3002,7 @@ static int ggtt_probe_common(struct i915_ggtt *ggtt, u64 size) * resort to an uncached mapping. The WC issue is easily caught by the * readback check when writing GTT PTE entries. */ - if (IS_GEN9_LP(dev_priv) || INTEL_GEN(dev_priv) >= 10) + if (GT_GEN9_LP(dev_priv) || INTEL_GEN(dev_priv) >= 10) ggtt->gsm = ioremap_nocache(phys_addr, size); else ggtt->gsm = ioremap_wc(phys_addr, size); @@ -3303,7 +3303,7 @@ static void setup_private_pat(struct drm_i915_private *dev_priv) if (INTEL_GEN(dev_priv) >= 10) cnl_setup_private_ppat(ppat); - else if (IS_CHERRYVIEW(dev_priv) || IS_GEN9_LP(dev_priv)) + else if (IS_CHERRYVIEW(dev_priv) || GT_GEN9_LP(dev_priv)) chv_setup_private_ppat(ppat); else bdw_setup_private_ppat(ppat); diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index 3ed545c2d508..e53e9ccf90f6 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -2791,7 +2791,7 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl) found = true; } - if (IS_GEN9_LP(dev_priv)) { + if (GT_GEN9_LP(dev_priv)) { tmp_mask = iir & BXT_DE_PORT_HOTPLUG_MASK; if (tmp_mask) { bxt_hpd_irq_handler(dev_priv, tmp_mask, @@ -2807,7 +2807,7 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl) } } - if (IS_GEN9_LP(dev_priv) && (iir & BXT_DE_PORT_GMBUS)) { + if (GT_GEN9_LP(dev_priv) && (iir & BXT_DE_PORT_GMBUS)) { gmbus_irq_handler(dev_priv); found = true; } @@ -4211,7 +4211,7 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv) de_pipe_masked |= GEN9_DE_PIPE_IRQ_FAULT_ERRORS; de_port_masked |= GEN9_AUX_CHANNEL_B | GEN9_AUX_CHANNEL_C | GEN9_AUX_CHANNEL_D; - if (IS_GEN9_LP(dev_priv)) + if (GT_GEN9_LP(dev_priv)) de_port_masked |= BXT_DE_PORT_GMBUS; } else { de_pipe_masked |= GEN8_DE_PIPE_IRQ_FAULT_ERRORS; @@ -4227,7 +4227,7 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv) GEN8_PIPE_FIFO_UNDERRUN; de_port_enables = de_port_masked; - if (IS_GEN9_LP(dev_priv)) + if (GT_GEN9_LP(dev_priv)) de_port_enables |= BXT_DE_PORT_HOTPLUG_MASK; else if (IS_BROADWELL(dev_priv)) de_port_enables |= GEN8_PORT_DP_A_HOTPLUG; @@ -4255,7 +4255,7 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv) GEN3_IRQ_INIT(GEN11_DE_HPD_, ~de_hpd_masked, de_hpd_enables); gen11_hpd_detection_setup(dev_priv); - } else if (IS_GEN9_LP(dev_priv)) { + } else if (GT_GEN9_LP(dev_priv)) { bxt_hpd_detection_setup(dev_priv); } else if (IS_BROADWELL(dev_priv)) { ilk_hpd_detection_setup(dev_priv); @@ -4898,7 +4898,7 @@ void intel_irq_init(struct drm_i915_private *dev_priv) dev->driver->irq_uninstall = gen8_irq_reset; dev->driver->enable_vblank = gen8_enable_vblank; dev->driver->disable_vblank = gen8_disable_vblank; - if (IS_GEN9_LP(dev_priv)) + if (GT_GEN9_LP(dev_priv)) dev_priv->display.hpd_irq_setup = bxt_hpd_irq_setup; else if (HAS_PCH_SPT(dev_priv) || HAS_PCH_KBP(dev_priv) || HAS_PCH_CNP(dev_priv)) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 158cf4716d03..33febd5a9eac 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -3814,7 +3814,7 @@ enum i915_power_well_id { #define INTERVAL_1_33_US(us) (((us) * 3) >> 2) #define INTERVAL_0_833_US(us) (((us) * 6) / 5) #define GT_INTERVAL_FROM_US(dev_priv, us) (INTEL_GEN(dev_priv) >= 9 ? \ - (IS_GEN9_LP(dev_priv) ? \ + (GT_GEN9_LP(dev_priv) ? \ INTERVAL_0_833_US(us) : \ INTERVAL_1_33_US(us)) : \ INTERVAL_1_28_US(us)) @@ -3823,7 +3823,7 @@ enum i915_power_well_id { #define INTERVAL_1_33_TO_US(interval) (((interval) << 2) / 3) #define INTERVAL_0_833_TO_US(interval) (((interval) * 5) / 6) #define GT_PM_INTERVAL_TO_US(dev_priv, interval) (INTEL_GEN(dev_priv) >= 9 ? \ - (IS_GEN9_LP(dev_priv) ? \ + (GT_GEN9_LP(dev_priv) ? \ INTERVAL_0_833_TO_US(interval) : \ INTERVAL_1_33_TO_US(interval)) : \ INTERVAL_1_28_TO_US(interval)) diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c index fb918e942e9a..8fa3c79c5f4a 100644 --- a/drivers/gpu/drm/i915/intel_bios.c +++ b/drivers/gpu/drm/i915/intel_bios.c @@ -711,7 +711,7 @@ parse_psr(struct drm_i915_private *dev_priv, const struct bdb_header *bdb) * Old decimal value is wake up time in multiples of 100 us. */ if (bdb->version >= 205 && - (IS_GEN9_BC(dev_priv) || IS_GEMINILAKE(dev_priv) || + (GT_GEN9_BC(dev_priv) || IS_GEMINILAKE(dev_priv) || INTEL_GEN(dev_priv) >= 10)) { switch (psr_table->tp1_wakeup_time) { case 0: @@ -2070,7 +2070,7 @@ intel_bios_is_port_hpd_inverted(struct drm_i915_private *dev_priv, const struct child_device_config *child; int i; - if (WARN_ON_ONCE(!IS_GEN9_LP(dev_priv))) + if (WARN_ON_ONCE(!GT_GEN9_LP(dev_priv))) return false; for (i = 0; i < dev_priv->vbt.child_dev_num; i++) { diff --git a/drivers/gpu/drm/i915/intel_cdclk.c b/drivers/gpu/drm/i915/intel_cdclk.c index db0edd01c973..37835d547d68 100644 --- a/drivers/gpu/drm/i915/intel_cdclk.c +++ b/drivers/gpu/drm/i915/intel_cdclk.c @@ -2565,7 +2565,7 @@ void intel_update_max_cdclk(struct drm_i915_private *dev_priv) dev_priv->max_cdclk_freq = 652800; } else if (IS_CANNONLAKE(dev_priv)) { dev_priv->max_cdclk_freq = 528000; - } else if (IS_GEN9_BC(dev_priv)) { + } else if (GT_GEN9_BC(dev_priv)) { u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK; int max_cdclk, vco; @@ -2775,11 +2775,11 @@ void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv) dev_priv->display.set_cdclk = bdw_set_cdclk; dev_priv->display.modeset_calc_cdclk = bdw_modeset_calc_cdclk; - } else if (IS_GEN9_LP(dev_priv)) { + } else if (GT_GEN9_LP(dev_priv)) { dev_priv->display.set_cdclk = bxt_set_cdclk; dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk; - } else if (IS_GEN9_BC(dev_priv)) { + } else if (GT_GEN9_BC(dev_priv)) { dev_priv->display.set_cdclk = skl_set_cdclk; dev_priv->display.modeset_calc_cdclk = skl_modeset_calc_cdclk; @@ -2796,9 +2796,9 @@ void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv) dev_priv->display.get_cdclk = icl_get_cdclk; else if (IS_CANNONLAKE(dev_priv)) dev_priv->display.get_cdclk = cnl_get_cdclk; - else if (IS_GEN9_BC(dev_priv)) + else if (GT_GEN9_BC(dev_priv)) dev_priv->display.get_cdclk = skl_get_cdclk; - else if (IS_GEN9_LP(dev_priv)) + else if (GT_GEN9_LP(dev_priv)) dev_priv->display.get_cdclk = bxt_get_cdclk; else if (IS_BROADWELL(dev_priv)) dev_priv->display.get_cdclk = bdw_get_cdclk; diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c index 5127da286a2b..91a46e4f3453 100644 --- a/drivers/gpu/drm/i915/intel_color.c +++ b/drivers/gpu/drm/i915/intel_color.c @@ -655,7 +655,7 @@ void intel_color_init(struct drm_crtc *crtc) } else if (IS_HASWELL(dev_priv)) { dev_priv->display.load_csc_matrix = ilk_load_csc_matrix; dev_priv->display.load_luts = haswell_load_luts; - } else if (IS_BROADWELL(dev_priv) || IS_GEN9_BC(dev_priv) || + } else if (IS_BROADWELL(dev_priv) || GT_GEN9_BC(dev_priv) || IS_BROXTON(dev_priv)) { dev_priv->display.load_csc_matrix = ilk_load_csc_matrix; dev_priv->display.load_luts = broadwell_load_luts; diff --git a/drivers/gpu/drm/i915/intel_csr.c b/drivers/gpu/drm/i915/intel_csr.c index fc7bd21fa586..2b5658143e19 100644 --- a/drivers/gpu/drm/i915/intel_csr.c +++ b/drivers/gpu/drm/i915/intel_csr.c @@ -232,7 +232,7 @@ static void gen9_set_dc_state_debugmask(struct drm_i915_private *dev_priv) mask = DC_STATE_DEBUG_MASK_MEMORY_UP; - if (IS_GEN9_LP(dev_priv)) + if (GT_GEN9_LP(dev_priv)) mask |= DC_STATE_DEBUG_MASK_CORES; /* The below bit doesn't need to be cleared ever afterwards */ diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c index ab9a36c4ba3b..c8390eebe8e3 100644 --- a/drivers/gpu/drm/i915/intel_ddi.c +++ b/drivers/gpu/drm/i915/intel_ddi.c @@ -728,7 +728,7 @@ static const struct ddi_buf_trans * intel_ddi_get_buf_trans_edp(struct drm_i915_private *dev_priv, enum port port, int *n_entries) { - if (IS_GEN9_BC(dev_priv)) { + if (GT_GEN9_BC(dev_priv)) { const struct ddi_buf_trans *ddi_translations = skl_get_buf_trans_edp(dev_priv, n_entries); *n_entries = skl_buf_trans_num_entries(port, *n_entries); @@ -764,7 +764,7 @@ static const struct ddi_buf_trans * intel_ddi_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries) { - if (IS_GEN9_BC(dev_priv)) { + if (GT_GEN9_BC(dev_priv)) { return skl_get_buf_trans_hdmi(dev_priv, n_entries); } else if (IS_BROADWELL(dev_priv)) { *n_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi); @@ -925,10 +925,10 @@ static int intel_ddi_hdmi_level(struct drm_i915_private *dev_priv, enum port por } else if (IS_CANNONLAKE(dev_priv)) { cnl_get_buf_trans_hdmi(dev_priv, &n_entries); default_entry = n_entries - 1; - } else if (IS_GEN9_LP(dev_priv)) { + } else if (GT_GEN9_LP(dev_priv)) { bxt_get_buf_trans_hdmi(dev_priv, &n_entries); default_entry = n_entries - 1; - } else if (IS_GEN9_BC(dev_priv)) { + } else if (GT_GEN9_BC(dev_priv)) { intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries); default_entry = 8; } else if (IS_BROADWELL(dev_priv)) { @@ -979,7 +979,7 @@ static void intel_prepare_dp_ddi_buffers(struct intel_encoder *encoder, &n_entries); /* If we're boosting the current, set bit 31 of trans1 */ - if (IS_GEN9_BC(dev_priv) && + if (GT_GEN9_BC(dev_priv) && dev_priv->vbt.ddi_port_info[port].dp_boost_level) iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE; @@ -1013,7 +1013,7 @@ static void intel_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder, level = n_entries - 1; /* If we're boosting the current, set bit 31 of trans1 */ - if (IS_GEN9_BC(dev_priv) && + if (GT_GEN9_BC(dev_priv) && dev_priv->vbt.ddi_port_info[port].hdmi_boost_level) iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE; @@ -1741,9 +1741,9 @@ static void intel_ddi_clock_get(struct intel_encoder *encoder, icl_ddi_clock_get(encoder, pipe_config); else if (IS_CANNONLAKE(dev_priv)) cnl_ddi_clock_get(encoder, pipe_config); - else if (IS_GEN9_LP(dev_priv)) + else if (GT_GEN9_LP(dev_priv)) bxt_ddi_clock_get(encoder, pipe_config); - else if (IS_GEN9_BC(dev_priv)) + else if (GT_GEN9_BC(dev_priv)) skl_ddi_clock_get(encoder, pipe_config); else if (INTEL_GEN(dev_priv) <= 8) hsw_ddi_clock_get(encoder, pipe_config); @@ -2067,7 +2067,7 @@ bool intel_ddi_get_hw_state(struct intel_encoder *encoder, DRM_DEBUG_KMS("No pipe for ddi port %c found\n", port_name(port)); out: - if (ret && IS_GEN9_LP(dev_priv)) { + if (ret && GT_GEN9_LP(dev_priv)) { tmp = I915_READ(BXT_PHY_CTL(port)); if ((tmp & (BXT_PHY_CMNLANE_POWERDOWN_ACK | BXT_PHY_LANE_POWERDOWN_ACK | @@ -2254,7 +2254,7 @@ u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder) cnl_get_buf_trans_edp(dev_priv, &n_entries); else cnl_get_buf_trans_dp(dev_priv, &n_entries); - } else if (IS_GEN9_LP(dev_priv)) { + } else if (GT_GEN9_LP(dev_priv)) { if (encoder->type == INTEL_OUTPUT_EDP) bxt_get_buf_trans_edp(dev_priv, &n_entries); else @@ -2736,7 +2736,7 @@ uint32_t ddi_signal_levels(struct intel_dp *intel_dp) struct intel_encoder *encoder = &dport->base; int level = intel_ddi_dp_level(intel_dp); - if (IS_GEN9_BC(dev_priv)) + if (GT_GEN9_BC(dev_priv)) skl_ddi_set_iboost(encoder, level, encoder->type); return DDI_BUF_TRANS_SELECT(level); @@ -2877,7 +2877,7 @@ static void intel_ddi_clk_select(struct intel_encoder *encoder, val = I915_READ(DPCLKA_CFGCR0); val &= ~DPCLKA_CFGCR0_DDI_CLK_OFF(port); I915_WRITE(DPCLKA_CFGCR0, val); - } else if (IS_GEN9_BC(dev_priv)) { + } else if (GT_GEN9_BC(dev_priv)) { /* DDI -> PLL mapping */ val = I915_READ(DPLL_CTRL2); @@ -2906,7 +2906,7 @@ static void intel_ddi_clk_disable(struct intel_encoder *encoder) } else if (IS_CANNONLAKE(dev_priv)) { I915_WRITE(DPCLKA_CFGCR0, I915_READ(DPCLKA_CFGCR0) | DPCLKA_CFGCR0_DDI_CLK_OFF(port)); - } else if (IS_GEN9_BC(dev_priv)) { + } else if (GT_GEN9_BC(dev_priv)) { I915_WRITE(DPLL_CTRL2, I915_READ(DPLL_CTRL2) | DPLL_CTRL2_DDI_CLK_OFF(port)); } else if (INTEL_GEN(dev_priv) < 9) { @@ -3075,7 +3075,7 @@ static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder, level, encoder->type); else if (IS_CANNONLAKE(dev_priv)) cnl_ddi_vswing_sequence(encoder, level, encoder->type); - else if (IS_GEN9_LP(dev_priv)) + else if (GT_GEN9_LP(dev_priv)) bxt_ddi_vswing_sequence(encoder, level, encoder->type); else intel_prepare_dp_ddi_buffers(encoder, crtc_state); @@ -3117,14 +3117,14 @@ static void intel_ddi_pre_enable_hdmi(struct intel_encoder *encoder, level, INTEL_OUTPUT_HDMI); else if (IS_CANNONLAKE(dev_priv)) cnl_ddi_vswing_sequence(encoder, level, INTEL_OUTPUT_HDMI); - else if (IS_GEN9_LP(dev_priv)) + else if (GT_GEN9_LP(dev_priv)) bxt_ddi_vswing_sequence(encoder, level, INTEL_OUTPUT_HDMI); else intel_prepare_hdmi_ddi_buffers(encoder, level); icl_enable_phy_clock_gating(dig_port); - if (IS_GEN9_BC(dev_priv)) + if (GT_GEN9_BC(dev_priv)) skl_ddi_set_iboost(encoder, level, INTEL_OUTPUT_HDMI); intel_ddi_enable_pipe_clock(crtc_state); @@ -3345,7 +3345,7 @@ static void intel_enable_ddi_hdmi(struct intel_encoder *encoder, connector->base.id, connector->name); /* Display WA #1143: skl,kbl,cfl */ - if (IS_GEN9_BC(dev_priv)) { + if (GT_GEN9_BC(dev_priv)) { /* * For some reason these chicken bits have been * stuffed into a transcoder register, event though @@ -3500,7 +3500,7 @@ intel_ddi_pre_pll_enable(struct intel_encoder *encoder, intel_display_power_get(dev_priv, intel_ddi_main_link_aux_domain(dig_port)); - if (IS_GEN9_LP(dev_priv)) + if (GT_GEN9_LP(dev_priv)) bxt_ddi_phy_set_lane_optim_mask(encoder, crtc_state->lane_lat_optim_mask); @@ -3704,7 +3704,7 @@ void intel_ddi_get_config(struct intel_encoder *encoder, intel_ddi_clock_get(encoder, pipe_config); - if (IS_GEN9_LP(dev_priv)) + if (GT_GEN9_LP(dev_priv)) pipe_config->lane_lat_optim_mask = bxt_ddi_phy_get_lane_lat_optim_mask(encoder); @@ -3745,7 +3745,7 @@ static bool intel_ddi_compute_config(struct intel_encoder *encoder, else ret = intel_dp_compute_config(encoder, pipe_config, conn_state); - if (IS_GEN9_LP(dev_priv) && ret) + if (GT_GEN9_LP(dev_priv) && ret) pipe_config->lane_lat_optim_mask = bxt_ddi_phy_calc_lane_lat_optim_mask(pipe_config->lane_count); @@ -3952,7 +3952,7 @@ static bool intel_ddi_a_force_4_lanes(struct intel_digital_port *dport) /* Broxton/Geminilake: Bspec says that DDI_A_4_LANES is the only * supported configuration */ - if (IS_GEN9_LP(dev_priv)) + if (GT_GEN9_LP(dev_priv)) return true; /* Cannonlake: Most of SKUs don't support DDI_E, and the only diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c index 7f712cd238fe..ab967781f495 100644 --- a/drivers/gpu/drm/i915/intel_device_info.c +++ b/drivers/gpu/drm/i915/intel_device_info.c @@ -339,8 +339,8 @@ static void gen9_sseu_info_init(struct drm_i915_private *dev_priv) sseu->slice_mask = (fuse2 & GEN8_F2_S_ENA_MASK) >> GEN8_F2_S_ENA_SHIFT; /* BXT has a single slice and at most 3 subslices. */ - sseu->max_slices = IS_GEN9_LP(dev_priv) ? 1 : 3; - sseu->max_subslices = IS_GEN9_LP(dev_priv) ? 3 : 4; + sseu->max_slices = GT_GEN9_LP(dev_priv) ? 1 : 3; + sseu->max_subslices = GT_GEN9_LP(dev_priv) ? 3 : 4; sseu->max_eus_per_subslice = 8; /* @@ -409,12 +409,12 @@ static void gen9_sseu_info_init(struct drm_i915_private *dev_priv) * pair per subslice. */ sseu->has_slice_pg = - !IS_GEN9_LP(dev_priv) && hweight8(sseu->slice_mask) > 1; + !GT_GEN9_LP(dev_priv) && hweight8(sseu->slice_mask) > 1; sseu->has_subslice_pg = - IS_GEN9_LP(dev_priv) && sseu_subslice_total(sseu) > 1; + GT_GEN9_LP(dev_priv) && sseu_subslice_total(sseu) > 1; sseu->has_eu_pg = sseu->eu_per_subslice > 2; - if (IS_GEN9_LP(dev_priv)) { + if (GT_GEN9_LP(dev_priv)) { #define IS_SS_DISABLED(ss) (!(sseu->subslice_mask[0] & BIT(ss))) info->has_pooled_eu = hweight8(sseu->subslice_mask[0]) == 3; @@ -671,7 +671,7 @@ static u32 read_timestamp_frequency(struct drm_i915_private *dev_priv) if ((ctc_reg & CTC_SOURCE_PARAMETER_MASK) == CTC_SOURCE_DIVIDE_LOGIC) { freq = read_reference_ts_freq(dev_priv); } else { - freq = IS_GEN9_LP(dev_priv) ? f19_2_mhz : f24_mhz; + freq = GT_GEN9_LP(dev_priv) ? f19_2_mhz : f24_mhz; /* Now figure out how the command stream's timestamp * register increments from this frequency (it might diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 904950a65c1b..b13956966a58 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -556,12 +556,12 @@ static bool intel_PLL_is_valid(struct drm_i915_private *dev_priv, INTELPllInvalid("m1 out of range\n"); if (!IS_PINEVIEW(dev_priv) && !IS_VALLEYVIEW(dev_priv) && - !IS_CHERRYVIEW(dev_priv) && !IS_GEN9_LP(dev_priv)) + !IS_CHERRYVIEW(dev_priv) && !GT_GEN9_LP(dev_priv)) if (clock->m1 <= clock->m2) INTELPllInvalid("m1 <= m2\n"); if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) && - !IS_GEN9_LP(dev_priv)) { + !GT_GEN9_LP(dev_priv)) { if (clock->p < limit->p.min || limit->p.max < clock->p) INTELPllInvalid("p out of range\n"); if (clock->m < limit->m.min || limit->m.max < clock->m) @@ -9481,9 +9481,9 @@ static void haswell_get_ddi_port_state(struct intel_crtc *crtc, icelake_get_ddi_pll(dev_priv, port, pipe_config); else if (IS_CANNONLAKE(dev_priv)) cannonlake_get_ddi_pll(dev_priv, port, pipe_config); - else if (IS_GEN9_BC(dev_priv)) + else if (GT_GEN9_BC(dev_priv)) skylake_get_ddi_pll(dev_priv, port, pipe_config); - else if (IS_GEN9_LP(dev_priv)) + else if (GT_GEN9_LP(dev_priv)) bxt_get_ddi_pll(dev_priv, port, pipe_config); else haswell_get_ddi_pll(dev_priv, port, pipe_config); @@ -9530,7 +9530,7 @@ static bool haswell_get_pipe_config(struct intel_crtc *crtc, active = hsw_get_transcoder_state(crtc, pipe_config, &power_domain_mask); - if (IS_GEN9_LP(dev_priv) && + if (GT_GEN9_LP(dev_priv) && bxt_get_dsi_transcoder_state(crtc, pipe_config, &power_domain_mask)) { WARN_ON(active); active = true; @@ -14101,7 +14101,7 @@ void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv) static void intel_pps_init(struct drm_i915_private *dev_priv) { - if (HAS_PCH_SPLIT(dev_priv) || IS_GEN9_LP(dev_priv)) + if (HAS_PCH_SPLIT(dev_priv) || GT_GEN9_LP(dev_priv)) dev_priv->pps_mmio_base = PCH_PPS_BASE; else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) dev_priv->pps_mmio_base = VLV_PPS_BASE; @@ -14139,7 +14139,7 @@ static void intel_setup_outputs(struct drm_i915_private *dev_priv) intel_ddi_init(dev_priv, PORT_E); intel_ddi_init(dev_priv, PORT_F); icl_dsi_init(dev_priv); - } else if (IS_GEN9_LP(dev_priv)) { + } else if (GT_GEN9_LP(dev_priv)) { /* * FIXME: Broxton doesn't support port detection via the * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to @@ -14160,7 +14160,7 @@ static void intel_setup_outputs(struct drm_i915_private *dev_priv) */ found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED; /* WaIgnoreDDIAStrap: skl */ - if (found || IS_GEN9_BC(dev_priv)) + if (found || GT_GEN9_BC(dev_priv)) intel_ddi_init(dev_priv, PORT_A); /* DDI B, C, D, and F detection is indicated by the SFUSE_STRAP @@ -14178,7 +14178,7 @@ static void intel_setup_outputs(struct drm_i915_private *dev_priv) /* * On SKL we don't have a way to detect DDI-E so we rely on VBT. */ - if (IS_GEN9_BC(dev_priv) && + if (GT_GEN9_BC(dev_priv) && (dev_priv->vbt.ddi_port_info[PORT_E].supports_dp || dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi || dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi)) diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index 9e410b04f99d..7f6ceb00574f 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -346,10 +346,10 @@ intel_dp_set_source_rates(struct intel_dp *intel_dp) max_rate = cnl_max_source_rate(intel_dp); else max_rate = icl_max_source_rate(intel_dp); - } else if (IS_GEN9_LP(dev_priv)) { + } else if (GT_GEN9_LP(dev_priv)) { source_rates = bxt_rates; size = ARRAY_SIZE(bxt_rates); - } else if (IS_GEN9_BC(dev_priv)) { + } else if (GT_GEN9_BC(dev_priv)) { source_rates = skl_rates; size = ARRAY_SIZE(skl_rates); } else if ((IS_HASWELL(dev_priv) && !IS_HSW_ULX(dev_priv)) || @@ -884,7 +884,7 @@ void intel_power_sequencer_reset(struct drm_i915_private *dev_priv) struct intel_encoder *encoder; if (WARN_ON(!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) && - !IS_GEN9_LP(dev_priv))) + !GT_GEN9_LP(dev_priv))) return; /* @@ -905,7 +905,7 @@ void intel_power_sequencer_reset(struct drm_i915_private *dev_priv) if (encoder->type != INTEL_OUTPUT_EDP) continue; - if (IS_GEN9_LP(dev_priv)) + if (GT_GEN9_LP(dev_priv)) intel_dp->pps_reset = true; else intel_dp->pps_pipe = INVALID_PIPE; @@ -928,7 +928,7 @@ static void intel_pps_get_registers(struct intel_dp *intel_dp, memset(regs, 0, sizeof(*regs)); - if (IS_GEN9_LP(dev_priv)) + if (GT_GEN9_LP(dev_priv)) pps_idx = bxt_power_sequencer_idx(intel_dp); else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) pps_idx = vlv_power_sequencer_pipe(intel_dp); @@ -937,7 +937,7 @@ static void intel_pps_get_registers(struct intel_dp *intel_dp, regs->pp_stat = PP_STATUS(pps_idx); regs->pp_on = PP_ON_DELAYS(pps_idx); regs->pp_off = PP_OFF_DELAYS(pps_idx); - if (!IS_GEN9_LP(dev_priv) && !HAS_PCH_CNP(dev_priv) && + if (!GT_GEN9_LP(dev_priv) && !HAS_PCH_CNP(dev_priv) && !HAS_PCH_ICP(dev_priv)) regs->pp_div = PP_DIVISOR(pps_idx); } @@ -3648,7 +3648,7 @@ intel_dp_set_signal_levels(struct intel_dp *intel_dp) uint32_t signal_levels, mask = 0; uint8_t train_set = intel_dp->train_set[0]; - if (IS_GEN9_LP(dev_priv) || INTEL_GEN(dev_priv) >= 10) { + if (GT_GEN9_LP(dev_priv) || INTEL_GEN(dev_priv) >= 10) { signal_levels = bxt_signal_levels(intel_dp); } else if (HAS_DDI(dev_priv)) { signal_levels = ddi_signal_levels(intel_dp); @@ -5026,9 +5026,9 @@ bool intel_digital_port_connected(struct intel_encoder *encoder) if (INTEL_GEN(dev_priv) >= 11) return icl_digital_port_connected(encoder); - else if (GT_GEN(dev_priv, 10) || IS_GEN9_BC(dev_priv)) + else if (GT_GEN(dev_priv, 10) || GT_GEN9_BC(dev_priv)) return spt_digital_port_connected(encoder); - else if (IS_GEN9_LP(dev_priv)) + else if (GT_GEN9_LP(dev_priv)) return bxt_digital_port_connected(encoder); else if (GT_GEN(dev_priv, 8)) return bdw_digital_port_connected(encoder); @@ -5780,7 +5780,7 @@ intel_pps_readout_hw_state(struct intel_dp *intel_dp, struct edp_power_seq *seq) pp_on = I915_READ(regs.pp_on); pp_off = I915_READ(regs.pp_off); - if (!IS_GEN9_LP(dev_priv) && !HAS_PCH_CNP(dev_priv) && + if (!GT_GEN9_LP(dev_priv) && !HAS_PCH_CNP(dev_priv) && !HAS_PCH_ICP(dev_priv)) { I915_WRITE(regs.pp_ctrl, pp_ctl); pp_div = I915_READ(regs.pp_div); @@ -5799,7 +5799,7 @@ intel_pps_readout_hw_state(struct intel_dp *intel_dp, struct edp_power_seq *seq) seq->t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >> PANEL_POWER_DOWN_DELAY_SHIFT; - if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv) || + if (GT_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv) || HAS_PCH_ICP(dev_priv)) { seq->t11_t12 = ((pp_ctl & BXT_POWER_CYCLE_DELAY_MASK) >> BXT_POWER_CYCLE_DELAY_SHIFT) * 1000; @@ -5971,7 +5971,7 @@ intel_dp_init_panel_power_sequencer_registers(struct intel_dp *intel_dp, (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT); /* Compute the divisor for the pp clock, simply match the Bspec * formula. */ - if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv) || + if (GT_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv) || HAS_PCH_ICP(dev_priv)) { pp_div = I915_READ(regs.pp_ctrl); pp_div &= ~BXT_POWER_CYCLE_DELAY_MASK; @@ -6008,7 +6008,7 @@ intel_dp_init_panel_power_sequencer_registers(struct intel_dp *intel_dp, I915_WRITE(regs.pp_on, pp_on); I915_WRITE(regs.pp_off, pp_off); - if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv) || + if (GT_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv) || HAS_PCH_ICP(dev_priv)) I915_WRITE(regs.pp_ctrl, pp_div); else @@ -6017,7 +6017,7 @@ intel_dp_init_panel_power_sequencer_registers(struct intel_dp *intel_dp, DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n", I915_READ(regs.pp_on), I915_READ(regs.pp_off), - (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv) || + (GT_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv) || HAS_PCH_ICP(dev_priv)) ? (I915_READ(regs.pp_ctrl) & BXT_POWER_CYCLE_DELAY_MASK) : I915_READ(regs.pp_div)); diff --git a/drivers/gpu/drm/i915/intel_dp_mst.c b/drivers/gpu/drm/i915/intel_dp_mst.c index 8b71d64ebd9d..9bf8b86c60df 100644 --- a/drivers/gpu/drm/i915/intel_dp_mst.c +++ b/drivers/gpu/drm/i915/intel_dp_mst.c @@ -98,7 +98,7 @@ static bool intel_dp_mst_compute_config(struct intel_encoder *encoder, pipe_config->dp_m_n.tu = slots; - if (IS_GEN9_LP(dev_priv)) + if (GT_GEN9_LP(dev_priv)) pipe_config->lane_lat_optim_mask = bxt_ddi_phy_calc_lane_lat_optim_mask(pipe_config->lane_count); diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c index 901e15063b24..5d756fdd1e7e 100644 --- a/drivers/gpu/drm/i915/intel_dpll_mgr.c +++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c @@ -3212,9 +3212,9 @@ void intel_shared_dpll_init(struct drm_device *dev) dpll_mgr = &icl_pll_mgr; else if (IS_CANNONLAKE(dev_priv)) dpll_mgr = &cnl_pll_mgr; - else if (IS_GEN9_BC(dev_priv)) + else if (GT_GEN9_BC(dev_priv)) dpll_mgr = &skl_pll_mgr; - else if (IS_GEN9_LP(dev_priv)) + else if (GT_GEN9_LP(dev_priv)) dpll_mgr = &bxt_pll_mgr; else if (HAS_DDI(dev_priv)) dpll_mgr = &hsw_pll_mgr; diff --git a/drivers/gpu/drm/i915/intel_fbc.c b/drivers/gpu/drm/i915/intel_fbc.c index 549e3dc0e457..7ed976ada979 100644 --- a/drivers/gpu/drm/i915/intel_fbc.c +++ b/drivers/gpu/drm/i915/intel_fbc.c @@ -444,7 +444,7 @@ static int find_compression_threshold(struct drm_i915_private *dev_priv, * reserved range size, so it always assumes the maximum (8mb) is used. * If we enable FBC using a CFB on that memory range we'll get FIFO * underruns, even if that range is not reserved by the BIOS. */ - if (IS_BROADWELL(dev_priv) || IS_GEN9_BC(dev_priv)) + if (IS_BROADWELL(dev_priv) || GT_GEN9_BC(dev_priv)) end = resource_size(&dev_priv->dsm) - 8 * 1024 * 1024; else end = U64_MAX; diff --git a/drivers/gpu/drm/i915/intel_guc_fw.c b/drivers/gpu/drm/i915/intel_guc_fw.c index 9fdce47755e2..586f435633c7 100644 --- a/drivers/gpu/drm/i915/intel_guc_fw.c +++ b/drivers/gpu/drm/i915/intel_guc_fw.c @@ -109,7 +109,7 @@ static void guc_prepare_xfer(struct intel_guc *guc) GUC_ENABLE_READ_CACHE_FOR_WOPCM_DATA | GUC_ENABLE_MIA_CLOCK_GATING); - if (IS_GEN9_LP(dev_priv)) + if (GT_GEN9_LP(dev_priv)) I915_WRITE(GEN9LP_GT_PM_CONFIG, GT_DOORBELL_ENABLE); else I915_WRITE(GEN9_GT_PM_CONFIG, GT_DOORBELL_ENABLE); diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c index bc5b945f9a71..f954c2883f92 100644 --- a/drivers/gpu/drm/i915/intel_hdmi.c +++ b/drivers/gpu/drm/i915/intel_hdmi.c @@ -1529,7 +1529,7 @@ hdmi_port_clock_valid(struct intel_hdmi *hdmi, return MODE_CLOCK_HIGH; /* BXT DPLL can't generate 223-240 MHz */ - if (IS_GEN9_LP(dev_priv) && clock > 223333 && clock < 240000) + if (GT_GEN9_LP(dev_priv) && clock > 223333 && clock < 240000) return MODE_CLOCK_RANGE; /* CHV DPLL can't generate 216-240 MHz */ @@ -2321,7 +2321,7 @@ static u8 intel_hdmi_ddc_pin(struct drm_i915_private *dev_priv, if (IS_CHERRYVIEW(dev_priv)) ddc_pin = chv_port_to_ddc_pin(dev_priv, port); - else if (IS_GEN9_LP(dev_priv)) + else if (GT_GEN9_LP(dev_priv)) ddc_pin = bxt_port_to_ddc_pin(dev_priv, port); else if (HAS_PCH_CNP(dev_priv)) ddc_pin = cnp_port_to_ddc_pin(dev_priv, port); diff --git a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu/drm/i915/intel_i2c.c index 33d87ab93fdd..86d898844a97 100644 --- a/drivers/gpu/drm/i915/intel_i2c.c +++ b/drivers/gpu/drm/i915/intel_i2c.c @@ -93,9 +93,9 @@ static const struct gmbus_pin *get_gmbus_pin(struct drm_i915_private *dev_priv, return &gmbus_pins_icp[pin]; else if (HAS_PCH_CNP(dev_priv)) return &gmbus_pins_cnp[pin]; - else if (IS_GEN9_LP(dev_priv)) + else if (GT_GEN9_LP(dev_priv)) return &gmbus_pins_bxt[pin]; - else if (IS_GEN9_BC(dev_priv)) + else if (GT_GEN9_BC(dev_priv)) return &gmbus_pins_skl[pin]; else if (IS_BROADWELL(dev_priv)) return &gmbus_pins_bdw[pin]; @@ -112,9 +112,9 @@ bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv, size = ARRAY_SIZE(gmbus_pins_icp); else if (HAS_PCH_CNP(dev_priv)) size = ARRAY_SIZE(gmbus_pins_cnp); - else if (IS_GEN9_LP(dev_priv)) + else if (GT_GEN9_LP(dev_priv)) size = ARRAY_SIZE(gmbus_pins_bxt); - else if (IS_GEN9_BC(dev_priv)) + else if (GT_GEN9_BC(dev_priv)) size = ARRAY_SIZE(gmbus_pins_skl); else if (IS_BROADWELL(dev_priv)) size = ARRAY_SIZE(gmbus_pins_bdw); @@ -576,7 +576,7 @@ do_gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num, int ret = 0; /* Display WA #0868: skl,bxt,kbl,cfl,glk,cnl */ - if (IS_GEN9_LP(dev_priv)) + if (GT_GEN9_LP(dev_priv)) bxt_gmbus_clock_gating(dev_priv, false); else if (HAS_PCH_SPT(dev_priv) || HAS_PCH_KBP(dev_priv) || HAS_PCH_CNP(dev_priv)) @@ -686,7 +686,7 @@ do_gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num, out: /* Display WA #0868: skl,bxt,kbl,cfl,glk,cnl */ - if (IS_GEN9_LP(dev_priv)) + if (GT_GEN9_LP(dev_priv)) bxt_gmbus_clock_gating(dev_priv, true); else if (HAS_PCH_SPT(dev_priv) || HAS_PCH_KBP(dev_priv) || HAS_PCH_CNP(dev_priv)) diff --git a/drivers/gpu/drm/i915/intel_mocs.c b/drivers/gpu/drm/i915/intel_mocs.c index 8201774c2c0f..6b9076fd5836 100644 --- a/drivers/gpu/drm/i915/intel_mocs.c +++ b/drivers/gpu/drm/i915/intel_mocs.c @@ -178,12 +178,12 @@ static bool get_mocs_settings(struct drm_i915_private *dev_priv, { bool result = false; - if (IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv) || + if (GT_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv) || IS_ICELAKE(dev_priv)) { table->size = ARRAY_SIZE(skylake_mocs_table); table->table = skylake_mocs_table; result = true; - } else if (IS_GEN9_LP(dev_priv)) { + } else if (GT_GEN9_LP(dev_priv)) { table->size = ARRAY_SIZE(broxton_mocs_table); table->table = broxton_mocs_table; result = true; diff --git a/drivers/gpu/drm/i915/intel_panel.c b/drivers/gpu/drm/i915/intel_panel.c index e658904c5576..78d5b9da3a02 100644 --- a/drivers/gpu/drm/i915/intel_panel.c +++ b/drivers/gpu/drm/i915/intel_panel.c @@ -1839,7 +1839,7 @@ intel_panel_init_backlight_funcs(struct intel_panel *panel) intel_dsi_dcs_init_backlight_funcs(connector) == 0) return; - if (IS_GEN9_LP(dev_priv)) { + if (GT_GEN9_LP(dev_priv)) { panel->backlight.setup = bxt_setup_backlight; panel->backlight.enable = bxt_enable_backlight; panel->backlight.disable = bxt_disable_backlight; diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 74e14d8848f8..3a321600bb78 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -3602,7 +3602,7 @@ static bool skl_needs_memory_bw_wa(struct intel_atomic_state *state) { struct drm_i915_private *dev_priv = to_i915(state->base.dev); - if (IS_GEN9_BC(dev_priv) || IS_BROXTON(dev_priv)) + if (GT_GEN9_BC(dev_priv) || IS_BROXTON(dev_priv)) return true; return false; @@ -3611,7 +3611,7 @@ static bool skl_needs_memory_bw_wa(struct intel_atomic_state *state) static bool intel_has_sagv(struct drm_i915_private *dev_priv) { - return (IS_GEN9_BC(dev_priv) || INTEL_GEN(dev_priv) >= 10) && + return (GT_GEN9_BC(dev_priv) || INTEL_GEN(dev_priv) >= 10) && dev_priv->sagv_status != I915_SAGV_NOT_CONTROLLED; } @@ -6894,7 +6894,7 @@ static bool sanitize_rc6(struct drm_i915_private *i915) info->has_rc6 = 0; if (info->has_rc6 && - IS_GEN9_LP(i915) && !bxt_check_bios_rc6_setup(i915)) { + GT_GEN9_LP(i915) && !bxt_check_bios_rc6_setup(i915)) { DRM_INFO("RC6 disabled by BIOS\n"); info->has_rc6 = 0; } @@ -6918,7 +6918,7 @@ static void gen6_init_rps_frequencies(struct drm_i915_private *dev_priv) /* All of these values are in units of 50MHz */ /* static values from HW: RP0 > RP1 > RPn (min_freq) */ - if (IS_GEN9_LP(dev_priv)) { + if (GT_GEN9_LP(dev_priv)) { u32 rp_state_cap = I915_READ(BXT_RP_STATE_CAP); rps->rp0_freq = (rp_state_cap >> 16) & 0xff; rps->rp1_freq = (rp_state_cap >> 8) & 0xff; @@ -6934,7 +6934,7 @@ static void gen6_init_rps_frequencies(struct drm_i915_private *dev_priv) rps->efficient_freq = rps->rp1_freq; if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv) || - IS_GEN9_BC(dev_priv) || INTEL_GEN(dev_priv) >= 10) { + GT_GEN9_BC(dev_priv) || INTEL_GEN(dev_priv) >= 10) { u32 ddcc_status = 0; if (sandybridge_pcode_read(dev_priv, @@ -6947,7 +6947,7 @@ static void gen6_init_rps_frequencies(struct drm_i915_private *dev_priv) rps->max_freq); } - if (IS_GEN9_BC(dev_priv) || INTEL_GEN(dev_priv) >= 10) { + if (GT_GEN9_BC(dev_priv) || INTEL_GEN(dev_priv) >= 10) { /* Store the frequency values in 16.66 MHZ units, which is * the natural hardware unit for SKL */ @@ -7285,7 +7285,7 @@ static void gen6_update_ring_freq(struct drm_i915_private *dev_priv) min_gpu_freq = rps->min_freq; max_gpu_freq = rps->max_freq; - if (IS_GEN9_BC(dev_priv) || INTEL_GEN(dev_priv) >= 10) { + if (GT_GEN9_BC(dev_priv) || INTEL_GEN(dev_priv) >= 10) { /* Convert GT frequency to 50 HZ units */ min_gpu_freq /= GEN9_FREQ_SCALER; max_gpu_freq /= GEN9_FREQ_SCALER; @@ -7300,7 +7300,7 @@ static void gen6_update_ring_freq(struct drm_i915_private *dev_priv) const int diff = max_gpu_freq - gpu_freq; unsigned int ia_freq = 0, ring_freq = 0; - if (IS_GEN9_BC(dev_priv) || INTEL_GEN(dev_priv) >= 10) { + if (GT_GEN9_BC(dev_priv) || INTEL_GEN(dev_priv) >= 10) { /* * ring_freq = 2 * GT. ring_freq is in 100MHz units * No floor required for ring frequency on SKL. @@ -9885,7 +9885,7 @@ u64 intel_rc6_residency_ns(struct drm_i915_private *dev_priv, time_hw = vlv_residency_raw(dev_priv, reg); } else { /* 833.33ns units on Gen9LP, 1.28us elsewhere. */ - if (IS_GEN9_LP(dev_priv)) { + if (GT_GEN9_LP(dev_priv)) { mul = 10000; div = 12; } else { diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c index b164a2c4b058..3b78afe0a790 100644 --- a/drivers/gpu/drm/i915/intel_runtime_pm.c +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c @@ -581,7 +581,7 @@ static u32 gen9_dc_mask(struct drm_i915_private *dev_priv) mask = DC_STATE_EN_UPTO_DC5; if (INTEL_GEN(dev_priv) >= 11) mask |= DC_STATE_EN_UPTO_DC6 | DC_STATE_EN_DC9; - else if (IS_GEN9_LP(dev_priv)) + else if (GT_GEN9_LP(dev_priv)) mask |= DC_STATE_EN_DC9; else mask |= DC_STATE_EN_UPTO_DC6; @@ -725,7 +725,7 @@ void gen9_enable_dc5(struct drm_i915_private *dev_priv) DRM_DEBUG_KMS("Enabling DC5\n"); /* Wa Display #1183: skl,kbl,cfl */ - if (IS_GEN9_BC(dev_priv)) + if (GT_GEN9_BC(dev_priv)) I915_WRITE(GEN8_CHICKEN_DCPR_1, I915_READ(GEN8_CHICKEN_DCPR_1) | SKL_SELECT_ALTERNATE_DC_EXIT); @@ -749,7 +749,7 @@ void skl_enable_dc6(struct drm_i915_private *dev_priv) DRM_DEBUG_KMS("Enabling DC6\n"); /* Wa Display #1183: skl,kbl,cfl */ - if (IS_GEN9_BC(dev_priv)) + if (GT_GEN9_BC(dev_priv)) I915_WRITE(GEN8_CHICKEN_DCPR_1, I915_READ(GEN8_CHICKEN_DCPR_1) | SKL_SELECT_ALTERNATE_DC_EXIT); @@ -841,7 +841,7 @@ static void gen9_dc_off_power_well_enable(struct drm_i915_private *dev_priv, gen9_assert_dbuf_enabled(dev_priv); - if (IS_GEN9_LP(dev_priv)) + if (GT_GEN9_LP(dev_priv)) bxt_verify_ddi_phy_power_wells(dev_priv); } @@ -3027,10 +3027,10 @@ static uint32_t get_allowed_dc_mask(const struct drm_i915_private *dev_priv, * suspend/resume, so allow it unconditionally. */ mask = DC_STATE_EN_DC9; - } else if (GT_GEN(dev_priv, 10) || IS_GEN9_BC(dev_priv)) { + } else if (GT_GEN(dev_priv, 10) || GT_GEN9_BC(dev_priv)) { max_dc = 2; mask = 0; - } else if (IS_GEN9_LP(dev_priv)) { + } else if (GT_GEN9_LP(dev_priv)) { max_dc = 1; mask = DC_STATE_EN_DC9; } else { @@ -3143,7 +3143,7 @@ int intel_power_domains_init(struct drm_i915_private *dev_priv) err = set_power_wells(power_domains, glk_power_wells); } else if (IS_BROXTON(dev_priv)) { err = set_power_wells(power_domains, bxt_power_wells); - } else if (IS_GEN9_BC(dev_priv)) { + } else if (GT_GEN9_BC(dev_priv)) { err = set_power_wells(power_domains, skl_power_wells); } else if (IS_CHERRYVIEW(dev_priv)) { err = set_power_wells(power_domains, chv_power_wells); @@ -3814,9 +3814,9 @@ void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume) icl_display_core_init(dev_priv, resume); } else if (IS_CANNONLAKE(dev_priv)) { cnl_display_core_init(dev_priv, resume); - } else if (IS_GEN9_BC(dev_priv)) { + } else if (GT_GEN9_BC(dev_priv)) { skl_display_core_init(dev_priv, resume); - } else if (IS_GEN9_LP(dev_priv)) { + } else if (GT_GEN9_LP(dev_priv)) { bxt_display_core_init(dev_priv, resume); } else if (IS_CHERRYVIEW(dev_priv)) { mutex_lock(&power_domains->lock); @@ -3945,9 +3945,9 @@ void intel_power_domains_suspend(struct drm_i915_private *dev_priv, icl_display_core_uninit(dev_priv); else if (IS_CANNONLAKE(dev_priv)) cnl_display_core_uninit(dev_priv); - else if (IS_GEN9_BC(dev_priv)) + else if (GT_GEN9_BC(dev_priv)) skl_display_core_uninit(dev_priv); - else if (IS_GEN9_LP(dev_priv)) + else if (GT_GEN9_LP(dev_priv)) bxt_display_core_uninit(dev_priv); power_domains->display_core_suspended = true; diff --git a/drivers/gpu/drm/i915/intel_wopcm.c b/drivers/gpu/drm/i915/intel_wopcm.c index 3987207cddd0..0a5c68acf3dd 100644 --- a/drivers/gpu/drm/i915/intel_wopcm.c +++ b/drivers/gpu/drm/i915/intel_wopcm.c @@ -78,7 +78,7 @@ void intel_wopcm_init_early(struct intel_wopcm *wopcm) static inline u32 context_reserved_size(struct drm_i915_private *i915) { - if (IS_GEN9_LP(i915)) + if (GT_GEN9_LP(i915)) return BXT_WOPCM_RC6_CTX_RESERVED; else if (INTEL_GEN(i915) >= 10) return CNL_WOPCM_HW_CTX_RESERVED; diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c index d7176213e3ce..db899cc5c981 100644 --- a/drivers/gpu/drm/i915/intel_workarounds.c +++ b/drivers/gpu/drm/i915/intel_workarounds.c @@ -300,7 +300,7 @@ static int gen9_ctx_workarounds_init(struct drm_i915_private *dev_priv) GEN9_PREEMPT_GPGPU_COMMAND_LEVEL); /* WaClearHIZ_WM_CHICKEN3:bxt,glk */ - if (IS_GEN9_LP(dev_priv)) + if (GT_GEN9_LP(dev_priv)) WA_SET_BIT_MASKED(GEN9_WM_CHICKEN3, GEN9_FACTOR_IN_CLR_VAL_HIZ); return 0; @@ -620,7 +620,7 @@ static void gen9_gt_workarounds_apply(struct drm_i915_private *dev_priv) BDW_DISABLE_HDC_INVALIDATION); /* WaProgramL3SqcReg1DefaultForPerf:bxt,glk */ - if (IS_GEN9_LP(dev_priv)) { + if (GT_GEN9_LP(dev_priv)) { u32 val = I915_READ(GEN8_L3SQCREG1); val &= ~L3_PRIO_CREDITS_MASK; diff --git a/drivers/gpu/drm/i915/vlv_dsi.c b/drivers/gpu/drm/i915/vlv_dsi.c index bab87b62bc2d..a06221dca0ec 100644 --- a/drivers/gpu/drm/i915/vlv_dsi.c +++ b/drivers/gpu/drm/i915/vlv_dsi.c @@ -290,7 +290,7 @@ static bool intel_dsi_compute_config(struct intel_encoder *encoder, /* DSI uses short packets for sync events, so clear mode flags for DSI */ adjusted_mode->flags = 0; - if (IS_GEN9_LP(dev_priv)) { + if (GT_GEN9_LP(dev_priv)) { /* Enable Frame time stamp based scanline reporting */ adjusted_mode->private_flags |= I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP; @@ -510,7 +510,7 @@ static void intel_dsi_device_ready(struct intel_encoder *encoder) if (IS_GEMINILAKE(dev_priv)) glk_dsi_device_ready(encoder); - else if (IS_GEN9_LP(dev_priv)) + else if (GT_GEN9_LP(dev_priv)) bxt_dsi_device_ready(encoder); else vlv_dsi_device_ready(encoder); @@ -591,7 +591,7 @@ static void vlv_dsi_clear_device_ready(struct intel_encoder *encoder) DRM_DEBUG_KMS("\n"); for_each_dsi_port(port, intel_dsi->ports) { /* Common bit for both MIPI Port A & MIPI Port C on VLV/CHV */ - i915_reg_t port_ctrl = IS_GEN9_LP(dev_priv) ? + i915_reg_t port_ctrl = GT_GEN9_LP(dev_priv) ? BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(PORT_A); u32 val; @@ -611,7 +611,7 @@ static void vlv_dsi_clear_device_ready(struct intel_encoder *encoder) * On VLV/CHV, wait till Clock lanes are in LP-00 state for MIPI * Port A only. MIPI Port C has no similar bit for checking. */ - if ((IS_GEN9_LP(dev_priv) || port == PORT_A) && + if ((GT_GEN9_LP(dev_priv) || port == PORT_A) && intel_wait_for_register(dev_priv, port_ctrl, AFE_LATCHOUT, 0, 30)) @@ -637,7 +637,7 @@ static void intel_dsi_port_enable(struct intel_encoder *encoder, if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) { u32 temp; - if (IS_GEN9_LP(dev_priv)) { + if (GT_GEN9_LP(dev_priv)) { for_each_dsi_port(port, intel_dsi->ports) { temp = I915_READ(MIPI_CTRL(port)); temp &= ~BXT_PIXEL_OVERLAP_CNT_MASK | @@ -655,7 +655,7 @@ static void intel_dsi_port_enable(struct intel_encoder *encoder, } for_each_dsi_port(port, intel_dsi->ports) { - i915_reg_t port_ctrl = IS_GEN9_LP(dev_priv) ? + i915_reg_t port_ctrl = GT_GEN9_LP(dev_priv) ? BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port); u32 temp; @@ -688,7 +688,7 @@ static void intel_dsi_port_disable(struct intel_encoder *encoder) enum port port; for_each_dsi_port(port, intel_dsi->ports) { - i915_reg_t port_ctrl = IS_GEN9_LP(dev_priv) ? + i915_reg_t port_ctrl = GT_GEN9_LP(dev_priv) ? BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port); u32 temp; @@ -765,7 +765,7 @@ static void intel_dsi_pre_enable(struct intel_encoder *encoder, * The BIOS may leave the PLL in a wonky state where it doesn't * lock. It needs to be fully powered down to fix it. */ - if (IS_GEN9_LP(dev_priv)) { + if (GT_GEN9_LP(dev_priv)) { bxt_dsi_pll_disable(encoder); bxt_dsi_pll_enable(encoder, pipe_config); } else { @@ -927,7 +927,7 @@ static void intel_dsi_post_disable(struct intel_encoder *encoder, val & ~MIPIO_RST_CTRL); } - if (IS_GEN9_LP(dev_priv)) { + if (GT_GEN9_LP(dev_priv)) { bxt_dsi_pll_disable(encoder); } else { u32 val; @@ -974,12 +974,12 @@ static bool intel_dsi_get_hw_state(struct intel_encoder *encoder, * configuration, otherwise accessing DSI registers will hang the * machine. See BSpec North Display Engine registers/MIPI[BXT]. */ - if (IS_GEN9_LP(dev_priv) && !bxt_dsi_pll_is_enabled(dev_priv)) + if (GT_GEN9_LP(dev_priv) && !bxt_dsi_pll_is_enabled(dev_priv)) goto out_put_power; /* XXX: this only works for one DSI output */ for_each_dsi_port(port, intel_dsi->ports) { - i915_reg_t ctrl_reg = IS_GEN9_LP(dev_priv) ? + i915_reg_t ctrl_reg = GT_GEN9_LP(dev_priv) ? BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port); bool enabled = I915_READ(ctrl_reg) & DPI_ENABLE; @@ -1004,7 +1004,7 @@ static bool intel_dsi_get_hw_state(struct intel_encoder *encoder, if (!(I915_READ(MIPI_DEVICE_READY(port)) & DEVICE_READY)) continue; - if (IS_GEN9_LP(dev_priv)) { + if (GT_GEN9_LP(dev_priv)) { u32 tmp = I915_READ(MIPI_CTRL(port)); tmp &= BXT_PIPE_SELECT_MASK; tmp >>= BXT_PIPE_SELECT_SHIFT; @@ -1197,7 +1197,7 @@ static void intel_dsi_get_config(struct intel_encoder *encoder, pipe_config->output_types |= BIT(INTEL_OUTPUT_DSI); - if (IS_GEN9_LP(dev_priv)) { + if (GT_GEN9_LP(dev_priv)) { bxt_dsi_get_pipe_config(encoder, pipe_config); pclk = bxt_dsi_get_pclk(encoder, pipe_config->pipe_bpp, pipe_config); @@ -1265,7 +1265,7 @@ static void set_dsi_timings(struct drm_encoder *encoder, hbp = txbyteclkhs(hbp, bpp, lane_count, intel_dsi->burst_mode_ratio); for_each_dsi_port(port, intel_dsi->ports) { - if (IS_GEN9_LP(dev_priv)) { + if (GT_GEN9_LP(dev_priv)) { /* * Program hdisplay and vdisplay on MIPI transcoder. * This is different from calculated hactive and @@ -1352,7 +1352,7 @@ static void intel_dsi_prepare(struct intel_encoder *intel_encoder, tmp &= ~READ_REQUEST_PRIORITY_MASK; I915_WRITE(MIPI_CTRL(port), tmp | READ_REQUEST_PRIORITY_HIGH); - } else if (IS_GEN9_LP(dev_priv)) { + } else if (GT_GEN9_LP(dev_priv)) { enum pipe pipe = intel_crtc->pipe; tmp = I915_READ(MIPI_CTRL(port)); @@ -1390,7 +1390,7 @@ static void intel_dsi_prepare(struct intel_encoder *intel_encoder, if (intel_dsi->clock_stop) tmp |= CLOCKSTOP; - if (IS_GEN9_LP(dev_priv)) { + if (GT_GEN9_LP(dev_priv)) { tmp |= BXT_DPHY_DEFEATURE_EN; if (!is_cmd_mode(intel_dsi)) tmp |= BXT_DEFEATURE_DPI_FIFO_CTR; @@ -1441,7 +1441,7 @@ static void intel_dsi_prepare(struct intel_encoder *intel_encoder, I915_WRITE(MIPI_INIT_COUNT(port), txclkesc(intel_dsi->escape_clk_div, 100)); - if (IS_GEN9_LP(dev_priv) && (!intel_dsi->dual_link)) { + if (GT_GEN9_LP(dev_priv) && (!intel_dsi->dual_link)) { /* * BXT spec says write MIPI_INIT_COUNT for * both the ports, even if only one is @@ -1520,7 +1520,7 @@ static void intel_dsi_unprepare(struct intel_encoder *encoder) /* Panel commands can be sent when clock is in LP11 */ I915_WRITE(MIPI_DEVICE_READY(port), 0x0); - if (IS_GEN9_LP(dev_priv)) + if (GT_GEN9_LP(dev_priv)) bxt_dsi_reset_clocks(encoder, port); else vlv_dsi_reset_clocks(encoder, port); @@ -1629,7 +1629,7 @@ void vlv_dsi_init(struct drm_i915_private *dev_priv) if (!intel_bios_is_dsi_present(dev_priv, &port)) return; - if (IS_GEN9_LP(dev_priv)) + if (GT_GEN9_LP(dev_priv)) dev_priv->mipi_mmio_base = BXT_MIPI_BASE; else dev_priv->mipi_mmio_base = VLV_MIPI_BASE; @@ -1668,7 +1668,7 @@ void vlv_dsi_init(struct drm_i915_private *dev_priv) * On BYT/CHV, pipe A maps to MIPI DSI port A, pipe B maps to MIPI DSI * port C. BXT isn't limited like this. */ - if (IS_GEN9_LP(dev_priv)) + if (GT_GEN9_LP(dev_priv)) intel_encoder->crtc_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C); else if (port == PORT_A) intel_encoder->crtc_mask = BIT(PIPE_A); -- 2.19.1.1.g56c4683e68 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 38+ messages in thread
* Re: [PATCH v2 4/7] drm/i915: rename IS_GEN9_* to GT_GEN9_* 2018-11-06 21:51 ` [PATCH v2 4/7] drm/i915: rename IS_GEN9_* to GT_GEN9_* Lucas De Marchi @ 2018-11-21 22:22 ` Rodrigo Vivi 0 siblings, 0 replies; 38+ messages in thread From: Rodrigo Vivi @ 2018-11-21 22:22 UTC (permalink / raw) To: Lucas De Marchi; +Cc: intel-gfx On Tue, Nov 06, 2018 at 01:51:20PM -0800, Lucas De Marchi wrote: > Like it was done for the generic IS_GEN -> GT_GEN rename, but since > the LP/BC variants only exist in gen 9, keep the single macro > definition. Also move the define to be together with GT_GEN(). > > Users were converted with: > > sed -i 's/IS_GEN9_/GT_GEN9_/g' \ > drivers/gpu/drm/i915/*.{c,h} \ > drivers/gpu/drm/i915/*/*.{c,h} > > Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> > --- > drivers/gpu/drm/i915/i915_debugfs.c | 22 ++++++------- > drivers/gpu/drm/i915/i915_drv.c | 10 +++--- > drivers/gpu/drm/i915/i915_drv.h | 9 ++--- > drivers/gpu/drm/i915/i915_gem_gtt.c | 6 ++-- > drivers/gpu/drm/i915/i915_irq.c | 12 +++---- > drivers/gpu/drm/i915/i915_reg.h | 4 +-- > drivers/gpu/drm/i915/intel_bios.c | 4 +-- > drivers/gpu/drm/i915/intel_cdclk.c | 10 +++--- > drivers/gpu/drm/i915/intel_color.c | 2 +- > drivers/gpu/drm/i915/intel_csr.c | 2 +- > drivers/gpu/drm/i915/intel_ddi.c | 42 ++++++++++++------------ > drivers/gpu/drm/i915/intel_device_info.c | 12 +++---- > drivers/gpu/drm/i915/intel_display.c | 18 +++++----- > drivers/gpu/drm/i915/intel_dp.c | 28 ++++++++-------- > drivers/gpu/drm/i915/intel_dp_mst.c | 2 +- > drivers/gpu/drm/i915/intel_dpll_mgr.c | 4 +-- > drivers/gpu/drm/i915/intel_fbc.c | 2 +- > drivers/gpu/drm/i915/intel_guc_fw.c | 2 +- > drivers/gpu/drm/i915/intel_hdmi.c | 4 +-- > drivers/gpu/drm/i915/intel_i2c.c | 12 +++---- > drivers/gpu/drm/i915/intel_mocs.c | 4 +-- > drivers/gpu/drm/i915/intel_panel.c | 2 +- > drivers/gpu/drm/i915/intel_pm.c | 18 +++++----- > drivers/gpu/drm/i915/intel_runtime_pm.c | 22 ++++++------- > drivers/gpu/drm/i915/intel_wopcm.c | 2 +- > drivers/gpu/drm/i915/intel_workarounds.c | 4 +-- > drivers/gpu/drm/i915/vlv_dsi.c | 40 +++++++++++----------- > 27 files changed, 150 insertions(+), 149 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c > index 2514ec4d97d4..5e4a934c0dea 100644 > --- a/drivers/gpu/drm/i915/i915_debugfs.c > +++ b/drivers/gpu/drm/i915/i915_debugfs.c > @@ -1123,7 +1123,7 @@ static int i915_frequency_info(struct seq_file *m, void *unused) > int max_freq; > > rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS); > - if (IS_GEN9_LP(dev_priv)) { > + if (GT_GEN9_LP(dev_priv)) { > rp_state_cap = I915_READ(BXT_RP_STATE_CAP); > gt_perf_status = I915_READ(BXT_GT_PERF_STATUS); > } else { > @@ -1230,22 +1230,22 @@ static int i915_frequency_info(struct seq_file *m, void *unused) > seq_printf(m, "Down threshold: %d%%\n", > rps->power.down_threshold); > > - max_freq = (IS_GEN9_LP(dev_priv) ? rp_state_cap >> 0 : > + max_freq = (GT_GEN9_LP(dev_priv) ? rp_state_cap >> 0 : > rp_state_cap >> 16) & 0xff; > - max_freq *= (IS_GEN9_BC(dev_priv) || > + max_freq *= (GT_GEN9_BC(dev_priv) || > INTEL_GEN(dev_priv) >= 10 ? GEN9_FREQ_SCALER : 1); > seq_printf(m, "Lowest (RPN) frequency: %dMHz\n", > intel_gpu_freq(dev_priv, max_freq)); > > max_freq = (rp_state_cap & 0xff00) >> 8; > - max_freq *= (IS_GEN9_BC(dev_priv) || > + max_freq *= (GT_GEN9_BC(dev_priv) || > INTEL_GEN(dev_priv) >= 10 ? GEN9_FREQ_SCALER : 1); > seq_printf(m, "Nominal (RP1) frequency: %dMHz\n", > intel_gpu_freq(dev_priv, max_freq)); > > - max_freq = (IS_GEN9_LP(dev_priv) ? rp_state_cap >> 16 : > + max_freq = (GT_GEN9_LP(dev_priv) ? rp_state_cap >> 16 : > rp_state_cap >> 0) & 0xff; > - max_freq *= (IS_GEN9_BC(dev_priv) || > + max_freq *= (GT_GEN9_BC(dev_priv) || > INTEL_GEN(dev_priv) >= 10 ? GEN9_FREQ_SCALER : 1); > seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n", > intel_gpu_freq(dev_priv, max_freq)); > @@ -1824,7 +1824,7 @@ static int i915_ring_freq_table(struct seq_file *m, void *unused) > > min_gpu_freq = rps->min_freq; > max_gpu_freq = rps->max_freq; > - if (IS_GEN9_BC(dev_priv) || INTEL_GEN(dev_priv) >= 10) { > + if (GT_GEN9_BC(dev_priv) || INTEL_GEN(dev_priv) >= 10) { > /* Convert GT frequency to 50 HZ units */ > min_gpu_freq /= GEN9_FREQ_SCALER; > max_gpu_freq /= GEN9_FREQ_SCALER; > @@ -1839,7 +1839,7 @@ static int i915_ring_freq_table(struct seq_file *m, void *unused) > &ia_freq); > seq_printf(m, "%d\t\t%d\t\t\t\t%d\n", > intel_gpu_freq(dev_priv, (gpu_freq * > - (IS_GEN9_BC(dev_priv) || > + (GT_GEN9_BC(dev_priv) || > INTEL_GEN(dev_priv) >= 10 ? > GEN9_FREQ_SCALER : 1))), > ((ia_freq >> 0) & 0xff) * 100, > @@ -2922,7 +2922,7 @@ static int i915_dmc_info(struct seq_file *m, void *unused) > seq_printf(m, "DC3 -> DC5 count: %d\n", > I915_READ(IS_BROXTON(dev_priv) ? BXT_CSR_DC3_DC5_COUNT : > SKL_CSR_DC3_DC5_COUNT)); > - if (!IS_GEN9_LP(dev_priv)) > + if (!GT_GEN9_LP(dev_priv)) > seq_printf(m, "DC5 -> DC6 count: %d\n", > I915_READ(SKL_CSR_DC5_DC6_COUNT)); > > @@ -4423,14 +4423,14 @@ static void gen9_sseu_device_status(struct drm_i915_private *dev_priv, > > sseu->slice_mask |= BIT(s); > > - if (IS_GEN9_BC(dev_priv)) > + if (GT_GEN9_BC(dev_priv)) > sseu->subslice_mask[s] = > INTEL_INFO(dev_priv)->sseu.subslice_mask[s]; > > for (ss = 0; ss < info->sseu.max_subslices; ss++) { > unsigned int eu_cnt; > > - if (IS_GEN9_LP(dev_priv)) { > + if (GT_GEN9_LP(dev_priv)) { > if (!(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss)))) > /* skip disabled subslice */ > continue; > diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c > index d2bdd7112c5d..8ff2acdec1f5 100644 > --- a/drivers/gpu/drm/i915/i915_drv.c > +++ b/drivers/gpu/drm/i915/i915_drv.c > @@ -1322,7 +1322,7 @@ intel_get_dram_info(struct drm_i915_private *dev_priv) > * This is only used for the level 0 watermark latency > * w/a which does not apply to bxt/glk. > */ > - dram_info->is_16gb_dimm = !IS_GEN9_LP(dev_priv); > + dram_info->is_16gb_dimm = !GT_GEN9_LP(dev_priv); > > if (INTEL_GEN(dev_priv) < 9 || IS_GEMINILAKE(dev_priv)) > return; > @@ -1962,7 +1962,7 @@ static int i915_drm_suspend_late(struct drm_device *dev, bool hibernation) > get_suspend_mode(dev_priv, hibernation)); > > ret = 0; > - if (INTEL_GEN(dev_priv) >= 11 || IS_GEN9_LP(dev_priv)) > + if (INTEL_GEN(dev_priv) >= 11 || GT_GEN9_LP(dev_priv)) > bxt_enable_dc9(dev_priv); > else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) > hsw_enable_pc8(dev_priv); > @@ -2152,7 +2152,7 @@ static int i915_drm_resume_early(struct drm_device *dev) > > intel_uncore_resume_early(dev_priv); > > - if (INTEL_GEN(dev_priv) >= 11 || IS_GEN9_LP(dev_priv)) { > + if (INTEL_GEN(dev_priv) >= 11 || GT_GEN9_LP(dev_priv)) { > gen9_sanitize_dc_state(dev_priv); > bxt_disable_dc9(dev_priv); > } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { > @@ -2922,7 +2922,7 @@ static int intel_runtime_suspend(struct device *kdev) > if (INTEL_GEN(dev_priv) >= 11) { > icl_display_core_uninit(dev_priv); > bxt_enable_dc9(dev_priv); > - } else if (IS_GEN9_LP(dev_priv)) { > + } else if (GT_GEN9_LP(dev_priv)) { > bxt_display_core_uninit(dev_priv); > bxt_enable_dc9(dev_priv); > } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { > @@ -3018,7 +3018,7 @@ static int intel_runtime_resume(struct device *kdev) > DC_STATE_EN_UPTO_DC5) > gen9_enable_dc5(dev_priv); > } > - } else if (IS_GEN9_LP(dev_priv)) { > + } else if (GT_GEN9_LP(dev_priv)) { > bxt_disable_dc9(dev_priv); > bxt_display_core_init(dev_priv, true); > if (dev_priv->csr.dmc_payload && > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h > index f11aad5cd7fb..08c879f17b40 100644 > --- a/drivers/gpu/drm/i915/i915_drv.h > +++ b/drivers/gpu/drm/i915/i915_drv.h > @@ -2360,6 +2360,8 @@ intel_info(const struct drm_i915_private *dev_priv) > #define REVID_FOREVER 0xff > #define INTEL_REVID(dev_priv) ((dev_priv)->drm.pdev->revision) > > +#define IS_LP(dev_priv) (INTEL_INFO(dev_priv)->is_lp) > + > #define GEN_FOREVER (0) > > #define INTEL_GEN_MASK(s, e) ( \ > @@ -2381,6 +2383,9 @@ intel_info(const struct drm_i915_private *dev_priv) > (BUILD_BUG_ON_ZERO(!__builtin_constant_p(n)) + \ > (!!((dev_priv)->info.gen_mask & BIT((n) - 1)))) > > +#define GT_GEN9_LP(dev_priv) (GT_GEN(dev_priv, 9) && IS_LP(dev_priv)) > +#define GT_GEN9_BC(dev_priv) (GT_GEN(dev_priv, 9) && !IS_LP(dev_priv)) > + > /* > * Return true if revision is in range [since,until] inclusive. > * > @@ -2532,10 +2537,6 @@ intel_info(const struct drm_i915_private *dev_priv) > #define IS_ICL_REVID(p, since, until) \ > (IS_ICELAKE(p) && IS_REVID(p, since, until)) > > -#define IS_LP(dev_priv) (INTEL_INFO(dev_priv)->is_lp) > -#define IS_GEN9_LP(dev_priv) (GT_GEN(dev_priv, 9) && IS_LP(dev_priv)) > -#define IS_GEN9_BC(dev_priv) (GT_GEN(dev_priv, 9) && !IS_LP(dev_priv)) > - > #define ENGINE_MASK(id) BIT(id) > #define RENDER_RING ENGINE_MASK(RCS) > #define BSD_RING ENGINE_MASK(VCS) > diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c > index 1723f374c5a8..4ae6166c6593 100644 > --- a/drivers/gpu/drm/i915/i915_gem_gtt.c > +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c > @@ -2168,7 +2168,7 @@ static void gtt_write_workarounds(struct drm_i915_private *dev_priv) > I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW); > else if (IS_CHERRYVIEW(dev_priv)) > I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_CHV); > - else if (IS_GEN9_LP(dev_priv)) > + else if (GT_GEN9_LP(dev_priv)) > I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_BXT); > else if (INTEL_GEN(dev_priv) >= 9) > I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_SKL); > @@ -3002,7 +3002,7 @@ static int ggtt_probe_common(struct i915_ggtt *ggtt, u64 size) > * resort to an uncached mapping. The WC issue is easily caught by the > * readback check when writing GTT PTE entries. > */ > - if (IS_GEN9_LP(dev_priv) || INTEL_GEN(dev_priv) >= 10) > + if (GT_GEN9_LP(dev_priv) || INTEL_GEN(dev_priv) >= 10) > ggtt->gsm = ioremap_nocache(phys_addr, size); > else > ggtt->gsm = ioremap_wc(phys_addr, size); > @@ -3303,7 +3303,7 @@ static void setup_private_pat(struct drm_i915_private *dev_priv) > > if (INTEL_GEN(dev_priv) >= 10) > cnl_setup_private_ppat(ppat); > - else if (IS_CHERRYVIEW(dev_priv) || IS_GEN9_LP(dev_priv)) > + else if (IS_CHERRYVIEW(dev_priv) || GT_GEN9_LP(dev_priv)) > chv_setup_private_ppat(ppat); > else > bdw_setup_private_ppat(ppat); > diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c > index 3ed545c2d508..e53e9ccf90f6 100644 > --- a/drivers/gpu/drm/i915/i915_irq.c > +++ b/drivers/gpu/drm/i915/i915_irq.c > @@ -2791,7 +2791,7 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl) > found = true; > } > > - if (IS_GEN9_LP(dev_priv)) { > + if (GT_GEN9_LP(dev_priv)) { > tmp_mask = iir & BXT_DE_PORT_HOTPLUG_MASK; > if (tmp_mask) { > bxt_hpd_irq_handler(dev_priv, tmp_mask, > @@ -2807,7 +2807,7 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl) > } > } > > - if (IS_GEN9_LP(dev_priv) && (iir & BXT_DE_PORT_GMBUS)) { > + if (GT_GEN9_LP(dev_priv) && (iir & BXT_DE_PORT_GMBUS)) { > gmbus_irq_handler(dev_priv); > found = true; > } > @@ -4211,7 +4211,7 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv) > de_pipe_masked |= GEN9_DE_PIPE_IRQ_FAULT_ERRORS; > de_port_masked |= GEN9_AUX_CHANNEL_B | GEN9_AUX_CHANNEL_C | > GEN9_AUX_CHANNEL_D; > - if (IS_GEN9_LP(dev_priv)) > + if (GT_GEN9_LP(dev_priv)) > de_port_masked |= BXT_DE_PORT_GMBUS; > } else { > de_pipe_masked |= GEN8_DE_PIPE_IRQ_FAULT_ERRORS; > @@ -4227,7 +4227,7 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv) > GEN8_PIPE_FIFO_UNDERRUN; > > de_port_enables = de_port_masked; > - if (IS_GEN9_LP(dev_priv)) > + if (GT_GEN9_LP(dev_priv)) > de_port_enables |= BXT_DE_PORT_HOTPLUG_MASK; > else if (IS_BROADWELL(dev_priv)) > de_port_enables |= GEN8_PORT_DP_A_HOTPLUG; > @@ -4255,7 +4255,7 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv) > > GEN3_IRQ_INIT(GEN11_DE_HPD_, ~de_hpd_masked, de_hpd_enables); > gen11_hpd_detection_setup(dev_priv); > - } else if (IS_GEN9_LP(dev_priv)) { > + } else if (GT_GEN9_LP(dev_priv)) { > bxt_hpd_detection_setup(dev_priv); > } else if (IS_BROADWELL(dev_priv)) { > ilk_hpd_detection_setup(dev_priv); > @@ -4898,7 +4898,7 @@ void intel_irq_init(struct drm_i915_private *dev_priv) > dev->driver->irq_uninstall = gen8_irq_reset; > dev->driver->enable_vblank = gen8_enable_vblank; > dev->driver->disable_vblank = gen8_disable_vblank; > - if (IS_GEN9_LP(dev_priv)) > + if (GT_GEN9_LP(dev_priv)) > dev_priv->display.hpd_irq_setup = bxt_hpd_irq_setup; > else if (HAS_PCH_SPT(dev_priv) || HAS_PCH_KBP(dev_priv) || > HAS_PCH_CNP(dev_priv)) > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index 158cf4716d03..33febd5a9eac 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -3814,7 +3814,7 @@ enum i915_power_well_id { > #define INTERVAL_1_33_US(us) (((us) * 3) >> 2) > #define INTERVAL_0_833_US(us) (((us) * 6) / 5) > #define GT_INTERVAL_FROM_US(dev_priv, us) (INTEL_GEN(dev_priv) >= 9 ? \ > - (IS_GEN9_LP(dev_priv) ? \ > + (GT_GEN9_LP(dev_priv) ? \ > INTERVAL_0_833_US(us) : \ > INTERVAL_1_33_US(us)) : \ > INTERVAL_1_28_US(us)) > @@ -3823,7 +3823,7 @@ enum i915_power_well_id { > #define INTERVAL_1_33_TO_US(interval) (((interval) << 2) / 3) > #define INTERVAL_0_833_TO_US(interval) (((interval) * 5) / 6) > #define GT_PM_INTERVAL_TO_US(dev_priv, interval) (INTEL_GEN(dev_priv) >= 9 ? \ > - (IS_GEN9_LP(dev_priv) ? \ > + (GT_GEN9_LP(dev_priv) ? \ > INTERVAL_0_833_TO_US(interval) : \ > INTERVAL_1_33_TO_US(interval)) : \ > INTERVAL_1_28_TO_US(interval)) > diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c > index fb918e942e9a..8fa3c79c5f4a 100644 > --- a/drivers/gpu/drm/i915/intel_bios.c > +++ b/drivers/gpu/drm/i915/intel_bios.c > @@ -711,7 +711,7 @@ parse_psr(struct drm_i915_private *dev_priv, const struct bdb_header *bdb) > * Old decimal value is wake up time in multiples of 100 us. > */ > if (bdb->version >= 205 && > - (IS_GEN9_BC(dev_priv) || IS_GEMINILAKE(dev_priv) || > + (GT_GEN9_BC(dev_priv) || IS_GEMINILAKE(dev_priv) || > INTEL_GEN(dev_priv) >= 10)) { > switch (psr_table->tp1_wakeup_time) { > case 0: > @@ -2070,7 +2070,7 @@ intel_bios_is_port_hpd_inverted(struct drm_i915_private *dev_priv, > const struct child_device_config *child; > int i; > > - if (WARN_ON_ONCE(!IS_GEN9_LP(dev_priv))) > + if (WARN_ON_ONCE(!GT_GEN9_LP(dev_priv))) > return false; > > for (i = 0; i < dev_priv->vbt.child_dev_num; i++) { > diff --git a/drivers/gpu/drm/i915/intel_cdclk.c b/drivers/gpu/drm/i915/intel_cdclk.c > index db0edd01c973..37835d547d68 100644 > --- a/drivers/gpu/drm/i915/intel_cdclk.c > +++ b/drivers/gpu/drm/i915/intel_cdclk.c > @@ -2565,7 +2565,7 @@ void intel_update_max_cdclk(struct drm_i915_private *dev_priv) > dev_priv->max_cdclk_freq = 652800; > } else if (IS_CANNONLAKE(dev_priv)) { > dev_priv->max_cdclk_freq = 528000; > - } else if (IS_GEN9_BC(dev_priv)) { > + } else if (GT_GEN9_BC(dev_priv)) { > u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK; > int max_cdclk, vco; > > @@ -2775,11 +2775,11 @@ void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv) > dev_priv->display.set_cdclk = bdw_set_cdclk; > dev_priv->display.modeset_calc_cdclk = > bdw_modeset_calc_cdclk; > - } else if (IS_GEN9_LP(dev_priv)) { > + } else if (GT_GEN9_LP(dev_priv)) { > dev_priv->display.set_cdclk = bxt_set_cdclk; > dev_priv->display.modeset_calc_cdclk = > bxt_modeset_calc_cdclk; > - } else if (IS_GEN9_BC(dev_priv)) { > + } else if (GT_GEN9_BC(dev_priv)) { > dev_priv->display.set_cdclk = skl_set_cdclk; > dev_priv->display.modeset_calc_cdclk = > skl_modeset_calc_cdclk; > @@ -2796,9 +2796,9 @@ void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv) > dev_priv->display.get_cdclk = icl_get_cdclk; > else if (IS_CANNONLAKE(dev_priv)) > dev_priv->display.get_cdclk = cnl_get_cdclk; > - else if (IS_GEN9_BC(dev_priv)) > + else if (GT_GEN9_BC(dev_priv)) > dev_priv->display.get_cdclk = skl_get_cdclk; > - else if (IS_GEN9_LP(dev_priv)) > + else if (GT_GEN9_LP(dev_priv)) > dev_priv->display.get_cdclk = bxt_get_cdclk; > else if (IS_BROADWELL(dev_priv)) > dev_priv->display.get_cdclk = bdw_get_cdclk; > diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c > index 5127da286a2b..91a46e4f3453 100644 > --- a/drivers/gpu/drm/i915/intel_color.c > +++ b/drivers/gpu/drm/i915/intel_color.c > @@ -655,7 +655,7 @@ void intel_color_init(struct drm_crtc *crtc) > } else if (IS_HASWELL(dev_priv)) { > dev_priv->display.load_csc_matrix = ilk_load_csc_matrix; > dev_priv->display.load_luts = haswell_load_luts; > - } else if (IS_BROADWELL(dev_priv) || IS_GEN9_BC(dev_priv) || > + } else if (IS_BROADWELL(dev_priv) || GT_GEN9_BC(dev_priv) || > IS_BROXTON(dev_priv)) { > dev_priv->display.load_csc_matrix = ilk_load_csc_matrix; > dev_priv->display.load_luts = broadwell_load_luts; > diff --git a/drivers/gpu/drm/i915/intel_csr.c b/drivers/gpu/drm/i915/intel_csr.c > index fc7bd21fa586..2b5658143e19 100644 > --- a/drivers/gpu/drm/i915/intel_csr.c > +++ b/drivers/gpu/drm/i915/intel_csr.c > @@ -232,7 +232,7 @@ static void gen9_set_dc_state_debugmask(struct drm_i915_private *dev_priv) > > mask = DC_STATE_DEBUG_MASK_MEMORY_UP; > > - if (IS_GEN9_LP(dev_priv)) > + if (GT_GEN9_LP(dev_priv)) > mask |= DC_STATE_DEBUG_MASK_CORES; > > /* The below bit doesn't need to be cleared ever afterwards */ > diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c > index ab9a36c4ba3b..c8390eebe8e3 100644 > --- a/drivers/gpu/drm/i915/intel_ddi.c > +++ b/drivers/gpu/drm/i915/intel_ddi.c > @@ -728,7 +728,7 @@ static const struct ddi_buf_trans * > intel_ddi_get_buf_trans_edp(struct drm_i915_private *dev_priv, > enum port port, int *n_entries) > { > - if (IS_GEN9_BC(dev_priv)) { > + if (GT_GEN9_BC(dev_priv)) { > const struct ddi_buf_trans *ddi_translations = > skl_get_buf_trans_edp(dev_priv, n_entries); > *n_entries = skl_buf_trans_num_entries(port, *n_entries); > @@ -764,7 +764,7 @@ static const struct ddi_buf_trans * > intel_ddi_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, > int *n_entries) > { > - if (IS_GEN9_BC(dev_priv)) { > + if (GT_GEN9_BC(dev_priv)) { > return skl_get_buf_trans_hdmi(dev_priv, n_entries); > } else if (IS_BROADWELL(dev_priv)) { > *n_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi); > @@ -925,10 +925,10 @@ static int intel_ddi_hdmi_level(struct drm_i915_private *dev_priv, enum port por > } else if (IS_CANNONLAKE(dev_priv)) { > cnl_get_buf_trans_hdmi(dev_priv, &n_entries); > default_entry = n_entries - 1; > - } else if (IS_GEN9_LP(dev_priv)) { > + } else if (GT_GEN9_LP(dev_priv)) { > bxt_get_buf_trans_hdmi(dev_priv, &n_entries); > default_entry = n_entries - 1; > - } else if (IS_GEN9_BC(dev_priv)) { > + } else if (GT_GEN9_BC(dev_priv)) { > intel_ddi_get_buf_trans_hdmi(dev_priv, &n_entries); > default_entry = 8; > } else if (IS_BROADWELL(dev_priv)) { > @@ -979,7 +979,7 @@ static void intel_prepare_dp_ddi_buffers(struct intel_encoder *encoder, > &n_entries); > > /* If we're boosting the current, set bit 31 of trans1 */ > - if (IS_GEN9_BC(dev_priv) && > + if (GT_GEN9_BC(dev_priv) && > dev_priv->vbt.ddi_port_info[port].dp_boost_level) > iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE; > > @@ -1013,7 +1013,7 @@ static void intel_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder, > level = n_entries - 1; > > /* If we're boosting the current, set bit 31 of trans1 */ > - if (IS_GEN9_BC(dev_priv) && > + if (GT_GEN9_BC(dev_priv) && > dev_priv->vbt.ddi_port_info[port].hdmi_boost_level) > iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE; > > @@ -1741,9 +1741,9 @@ static void intel_ddi_clock_get(struct intel_encoder *encoder, > icl_ddi_clock_get(encoder, pipe_config); > else if (IS_CANNONLAKE(dev_priv)) > cnl_ddi_clock_get(encoder, pipe_config); > - else if (IS_GEN9_LP(dev_priv)) > + else if (GT_GEN9_LP(dev_priv)) > bxt_ddi_clock_get(encoder, pipe_config); > - else if (IS_GEN9_BC(dev_priv)) > + else if (GT_GEN9_BC(dev_priv)) > skl_ddi_clock_get(encoder, pipe_config); > else if (INTEL_GEN(dev_priv) <= 8) > hsw_ddi_clock_get(encoder, pipe_config); > @@ -2067,7 +2067,7 @@ bool intel_ddi_get_hw_state(struct intel_encoder *encoder, > DRM_DEBUG_KMS("No pipe for ddi port %c found\n", port_name(port)); > > out: > - if (ret && IS_GEN9_LP(dev_priv)) { > + if (ret && GT_GEN9_LP(dev_priv)) { > tmp = I915_READ(BXT_PHY_CTL(port)); > if ((tmp & (BXT_PHY_CMNLANE_POWERDOWN_ACK | > BXT_PHY_LANE_POWERDOWN_ACK | > @@ -2254,7 +2254,7 @@ u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder) > cnl_get_buf_trans_edp(dev_priv, &n_entries); > else > cnl_get_buf_trans_dp(dev_priv, &n_entries); > - } else if (IS_GEN9_LP(dev_priv)) { > + } else if (GT_GEN9_LP(dev_priv)) { > if (encoder->type == INTEL_OUTPUT_EDP) > bxt_get_buf_trans_edp(dev_priv, &n_entries); > else > @@ -2736,7 +2736,7 @@ uint32_t ddi_signal_levels(struct intel_dp *intel_dp) > struct intel_encoder *encoder = &dport->base; > int level = intel_ddi_dp_level(intel_dp); > > - if (IS_GEN9_BC(dev_priv)) > + if (GT_GEN9_BC(dev_priv)) > skl_ddi_set_iboost(encoder, level, encoder->type); > > return DDI_BUF_TRANS_SELECT(level); > @@ -2877,7 +2877,7 @@ static void intel_ddi_clk_select(struct intel_encoder *encoder, > val = I915_READ(DPCLKA_CFGCR0); > val &= ~DPCLKA_CFGCR0_DDI_CLK_OFF(port); > I915_WRITE(DPCLKA_CFGCR0, val); > - } else if (IS_GEN9_BC(dev_priv)) { > + } else if (GT_GEN9_BC(dev_priv)) { > /* DDI -> PLL mapping */ > val = I915_READ(DPLL_CTRL2); > > @@ -2906,7 +2906,7 @@ static void intel_ddi_clk_disable(struct intel_encoder *encoder) > } else if (IS_CANNONLAKE(dev_priv)) { > I915_WRITE(DPCLKA_CFGCR0, I915_READ(DPCLKA_CFGCR0) | > DPCLKA_CFGCR0_DDI_CLK_OFF(port)); > - } else if (IS_GEN9_BC(dev_priv)) { > + } else if (GT_GEN9_BC(dev_priv)) { > I915_WRITE(DPLL_CTRL2, I915_READ(DPLL_CTRL2) | > DPLL_CTRL2_DDI_CLK_OFF(port)); > } else if (INTEL_GEN(dev_priv) < 9) { > @@ -3075,7 +3075,7 @@ static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder, > level, encoder->type); > else if (IS_CANNONLAKE(dev_priv)) > cnl_ddi_vswing_sequence(encoder, level, encoder->type); > - else if (IS_GEN9_LP(dev_priv)) > + else if (GT_GEN9_LP(dev_priv)) > bxt_ddi_vswing_sequence(encoder, level, encoder->type); > else > intel_prepare_dp_ddi_buffers(encoder, crtc_state); > @@ -3117,14 +3117,14 @@ static void intel_ddi_pre_enable_hdmi(struct intel_encoder *encoder, > level, INTEL_OUTPUT_HDMI); > else if (IS_CANNONLAKE(dev_priv)) > cnl_ddi_vswing_sequence(encoder, level, INTEL_OUTPUT_HDMI); > - else if (IS_GEN9_LP(dev_priv)) > + else if (GT_GEN9_LP(dev_priv)) > bxt_ddi_vswing_sequence(encoder, level, INTEL_OUTPUT_HDMI); > else > intel_prepare_hdmi_ddi_buffers(encoder, level); > > icl_enable_phy_clock_gating(dig_port); > > - if (IS_GEN9_BC(dev_priv)) > + if (GT_GEN9_BC(dev_priv)) > skl_ddi_set_iboost(encoder, level, INTEL_OUTPUT_HDMI); > > intel_ddi_enable_pipe_clock(crtc_state); > @@ -3345,7 +3345,7 @@ static void intel_enable_ddi_hdmi(struct intel_encoder *encoder, > connector->base.id, connector->name); > > /* Display WA #1143: skl,kbl,cfl */ > - if (IS_GEN9_BC(dev_priv)) { > + if (GT_GEN9_BC(dev_priv)) { > /* > * For some reason these chicken bits have been > * stuffed into a transcoder register, event though > @@ -3500,7 +3500,7 @@ intel_ddi_pre_pll_enable(struct intel_encoder *encoder, > intel_display_power_get(dev_priv, > intel_ddi_main_link_aux_domain(dig_port)); > > - if (IS_GEN9_LP(dev_priv)) > + if (GT_GEN9_LP(dev_priv)) > bxt_ddi_phy_set_lane_optim_mask(encoder, > crtc_state->lane_lat_optim_mask); > > @@ -3704,7 +3704,7 @@ void intel_ddi_get_config(struct intel_encoder *encoder, > > intel_ddi_clock_get(encoder, pipe_config); > > - if (IS_GEN9_LP(dev_priv)) > + if (GT_GEN9_LP(dev_priv)) > pipe_config->lane_lat_optim_mask = > bxt_ddi_phy_get_lane_lat_optim_mask(encoder); > > @@ -3745,7 +3745,7 @@ static bool intel_ddi_compute_config(struct intel_encoder *encoder, > else > ret = intel_dp_compute_config(encoder, pipe_config, conn_state); > > - if (IS_GEN9_LP(dev_priv) && ret) > + if (GT_GEN9_LP(dev_priv) && ret) > pipe_config->lane_lat_optim_mask = > bxt_ddi_phy_calc_lane_lat_optim_mask(pipe_config->lane_count); > > @@ -3952,7 +3952,7 @@ static bool intel_ddi_a_force_4_lanes(struct intel_digital_port *dport) > /* Broxton/Geminilake: Bspec says that DDI_A_4_LANES is the only > * supported configuration > */ > - if (IS_GEN9_LP(dev_priv)) > + if (GT_GEN9_LP(dev_priv)) > return true; > > /* Cannonlake: Most of SKUs don't support DDI_E, and the only > diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c > index 7f712cd238fe..ab967781f495 100644 > --- a/drivers/gpu/drm/i915/intel_device_info.c > +++ b/drivers/gpu/drm/i915/intel_device_info.c > @@ -339,8 +339,8 @@ static void gen9_sseu_info_init(struct drm_i915_private *dev_priv) > sseu->slice_mask = (fuse2 & GEN8_F2_S_ENA_MASK) >> GEN8_F2_S_ENA_SHIFT; > > /* BXT has a single slice and at most 3 subslices. */ > - sseu->max_slices = IS_GEN9_LP(dev_priv) ? 1 : 3; > - sseu->max_subslices = IS_GEN9_LP(dev_priv) ? 3 : 4; > + sseu->max_slices = GT_GEN9_LP(dev_priv) ? 1 : 3; > + sseu->max_subslices = GT_GEN9_LP(dev_priv) ? 3 : 4; > sseu->max_eus_per_subslice = 8; > > /* > @@ -409,12 +409,12 @@ static void gen9_sseu_info_init(struct drm_i915_private *dev_priv) > * pair per subslice. > */ > sseu->has_slice_pg = > - !IS_GEN9_LP(dev_priv) && hweight8(sseu->slice_mask) > 1; > + !GT_GEN9_LP(dev_priv) && hweight8(sseu->slice_mask) > 1; > sseu->has_subslice_pg = > - IS_GEN9_LP(dev_priv) && sseu_subslice_total(sseu) > 1; > + GT_GEN9_LP(dev_priv) && sseu_subslice_total(sseu) > 1; > sseu->has_eu_pg = sseu->eu_per_subslice > 2; > > - if (IS_GEN9_LP(dev_priv)) { > + if (GT_GEN9_LP(dev_priv)) { > #define IS_SS_DISABLED(ss) (!(sseu->subslice_mask[0] & BIT(ss))) > info->has_pooled_eu = hweight8(sseu->subslice_mask[0]) == 3; > > @@ -671,7 +671,7 @@ static u32 read_timestamp_frequency(struct drm_i915_private *dev_priv) > if ((ctc_reg & CTC_SOURCE_PARAMETER_MASK) == CTC_SOURCE_DIVIDE_LOGIC) { > freq = read_reference_ts_freq(dev_priv); > } else { > - freq = IS_GEN9_LP(dev_priv) ? f19_2_mhz : f24_mhz; > + freq = GT_GEN9_LP(dev_priv) ? f19_2_mhz : f24_mhz; > > /* Now figure out how the command stream's timestamp > * register increments from this frequency (it might > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c > index 904950a65c1b..b13956966a58 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -556,12 +556,12 @@ static bool intel_PLL_is_valid(struct drm_i915_private *dev_priv, > INTELPllInvalid("m1 out of range\n"); > > if (!IS_PINEVIEW(dev_priv) && !IS_VALLEYVIEW(dev_priv) && > - !IS_CHERRYVIEW(dev_priv) && !IS_GEN9_LP(dev_priv)) > + !IS_CHERRYVIEW(dev_priv) && !GT_GEN9_LP(dev_priv)) > if (clock->m1 <= clock->m2) > INTELPllInvalid("m1 <= m2\n"); > > if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) && > - !IS_GEN9_LP(dev_priv)) { > + !GT_GEN9_LP(dev_priv)) { > if (clock->p < limit->p.min || limit->p.max < clock->p) > INTELPllInvalid("p out of range\n"); > if (clock->m < limit->m.min || limit->m.max < clock->m) > @@ -9481,9 +9481,9 @@ static void haswell_get_ddi_port_state(struct intel_crtc *crtc, > icelake_get_ddi_pll(dev_priv, port, pipe_config); > else if (IS_CANNONLAKE(dev_priv)) > cannonlake_get_ddi_pll(dev_priv, port, pipe_config); > - else if (IS_GEN9_BC(dev_priv)) > + else if (GT_GEN9_BC(dev_priv)) > skylake_get_ddi_pll(dev_priv, port, pipe_config); > - else if (IS_GEN9_LP(dev_priv)) > + else if (GT_GEN9_LP(dev_priv)) > bxt_get_ddi_pll(dev_priv, port, pipe_config); > else > haswell_get_ddi_pll(dev_priv, port, pipe_config); > @@ -9530,7 +9530,7 @@ static bool haswell_get_pipe_config(struct intel_crtc *crtc, > > active = hsw_get_transcoder_state(crtc, pipe_config, &power_domain_mask); > > - if (IS_GEN9_LP(dev_priv) && > + if (GT_GEN9_LP(dev_priv) && > bxt_get_dsi_transcoder_state(crtc, pipe_config, &power_domain_mask)) { > WARN_ON(active); > active = true; > @@ -14101,7 +14101,7 @@ void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv) > > static void intel_pps_init(struct drm_i915_private *dev_priv) > { > - if (HAS_PCH_SPLIT(dev_priv) || IS_GEN9_LP(dev_priv)) > + if (HAS_PCH_SPLIT(dev_priv) || GT_GEN9_LP(dev_priv)) > dev_priv->pps_mmio_base = PCH_PPS_BASE; > else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) > dev_priv->pps_mmio_base = VLV_PPS_BASE; > @@ -14139,7 +14139,7 @@ static void intel_setup_outputs(struct drm_i915_private *dev_priv) > intel_ddi_init(dev_priv, PORT_E); > intel_ddi_init(dev_priv, PORT_F); > icl_dsi_init(dev_priv); > - } else if (IS_GEN9_LP(dev_priv)) { > + } else if (GT_GEN9_LP(dev_priv)) { > /* > * FIXME: Broxton doesn't support port detection via the > * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to > @@ -14160,7 +14160,7 @@ static void intel_setup_outputs(struct drm_i915_private *dev_priv) > */ > found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED; > /* WaIgnoreDDIAStrap: skl */ > - if (found || IS_GEN9_BC(dev_priv)) > + if (found || GT_GEN9_BC(dev_priv)) > intel_ddi_init(dev_priv, PORT_A); > > /* DDI B, C, D, and F detection is indicated by the SFUSE_STRAP > @@ -14178,7 +14178,7 @@ static void intel_setup_outputs(struct drm_i915_private *dev_priv) > /* > * On SKL we don't have a way to detect DDI-E so we rely on VBT. > */ > - if (IS_GEN9_BC(dev_priv) && > + if (GT_GEN9_BC(dev_priv) && > (dev_priv->vbt.ddi_port_info[PORT_E].supports_dp || > dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi || > dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi)) > diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c > index 9e410b04f99d..7f6ceb00574f 100644 > --- a/drivers/gpu/drm/i915/intel_dp.c > +++ b/drivers/gpu/drm/i915/intel_dp.c > @@ -346,10 +346,10 @@ intel_dp_set_source_rates(struct intel_dp *intel_dp) > max_rate = cnl_max_source_rate(intel_dp); > else > max_rate = icl_max_source_rate(intel_dp); > - } else if (IS_GEN9_LP(dev_priv)) { > + } else if (GT_GEN9_LP(dev_priv)) { > source_rates = bxt_rates; > size = ARRAY_SIZE(bxt_rates); > - } else if (IS_GEN9_BC(dev_priv)) { > + } else if (GT_GEN9_BC(dev_priv)) { > source_rates = skl_rates; > size = ARRAY_SIZE(skl_rates); > } else if ((IS_HASWELL(dev_priv) && !IS_HSW_ULX(dev_priv)) || > @@ -884,7 +884,7 @@ void intel_power_sequencer_reset(struct drm_i915_private *dev_priv) > struct intel_encoder *encoder; > > if (WARN_ON(!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) && > - !IS_GEN9_LP(dev_priv))) > + !GT_GEN9_LP(dev_priv))) > return; > > /* > @@ -905,7 +905,7 @@ void intel_power_sequencer_reset(struct drm_i915_private *dev_priv) > if (encoder->type != INTEL_OUTPUT_EDP) > continue; > > - if (IS_GEN9_LP(dev_priv)) > + if (GT_GEN9_LP(dev_priv)) > intel_dp->pps_reset = true; > else > intel_dp->pps_pipe = INVALID_PIPE; > @@ -928,7 +928,7 @@ static void intel_pps_get_registers(struct intel_dp *intel_dp, > > memset(regs, 0, sizeof(*regs)); > > - if (IS_GEN9_LP(dev_priv)) > + if (GT_GEN9_LP(dev_priv)) > pps_idx = bxt_power_sequencer_idx(intel_dp); > else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) > pps_idx = vlv_power_sequencer_pipe(intel_dp); > @@ -937,7 +937,7 @@ static void intel_pps_get_registers(struct intel_dp *intel_dp, > regs->pp_stat = PP_STATUS(pps_idx); > regs->pp_on = PP_ON_DELAYS(pps_idx); > regs->pp_off = PP_OFF_DELAYS(pps_idx); > - if (!IS_GEN9_LP(dev_priv) && !HAS_PCH_CNP(dev_priv) && > + if (!GT_GEN9_LP(dev_priv) && !HAS_PCH_CNP(dev_priv) && > !HAS_PCH_ICP(dev_priv)) > regs->pp_div = PP_DIVISOR(pps_idx); > } > @@ -3648,7 +3648,7 @@ intel_dp_set_signal_levels(struct intel_dp *intel_dp) > uint32_t signal_levels, mask = 0; > uint8_t train_set = intel_dp->train_set[0]; > > - if (IS_GEN9_LP(dev_priv) || INTEL_GEN(dev_priv) >= 10) { > + if (GT_GEN9_LP(dev_priv) || INTEL_GEN(dev_priv) >= 10) { > signal_levels = bxt_signal_levels(intel_dp); > } else if (HAS_DDI(dev_priv)) { > signal_levels = ddi_signal_levels(intel_dp); > @@ -5026,9 +5026,9 @@ bool intel_digital_port_connected(struct intel_encoder *encoder) > > if (INTEL_GEN(dev_priv) >= 11) > return icl_digital_port_connected(encoder); > - else if (GT_GEN(dev_priv, 10) || IS_GEN9_BC(dev_priv)) > + else if (GT_GEN(dev_priv, 10) || GT_GEN9_BC(dev_priv)) > return spt_digital_port_connected(encoder); > - else if (IS_GEN9_LP(dev_priv)) > + else if (GT_GEN9_LP(dev_priv)) > return bxt_digital_port_connected(encoder); > else if (GT_GEN(dev_priv, 8)) > return bdw_digital_port_connected(encoder); > @@ -5780,7 +5780,7 @@ intel_pps_readout_hw_state(struct intel_dp *intel_dp, struct edp_power_seq *seq) > > pp_on = I915_READ(regs.pp_on); > pp_off = I915_READ(regs.pp_off); > - if (!IS_GEN9_LP(dev_priv) && !HAS_PCH_CNP(dev_priv) && > + if (!GT_GEN9_LP(dev_priv) && !HAS_PCH_CNP(dev_priv) && > !HAS_PCH_ICP(dev_priv)) { > I915_WRITE(regs.pp_ctrl, pp_ctl); > pp_div = I915_READ(regs.pp_div); > @@ -5799,7 +5799,7 @@ intel_pps_readout_hw_state(struct intel_dp *intel_dp, struct edp_power_seq *seq) > seq->t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >> > PANEL_POWER_DOWN_DELAY_SHIFT; > > - if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv) || > + if (GT_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv) || > HAS_PCH_ICP(dev_priv)) { > seq->t11_t12 = ((pp_ctl & BXT_POWER_CYCLE_DELAY_MASK) >> > BXT_POWER_CYCLE_DELAY_SHIFT) * 1000; > @@ -5971,7 +5971,7 @@ intel_dp_init_panel_power_sequencer_registers(struct intel_dp *intel_dp, > (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT); > /* Compute the divisor for the pp clock, simply match the Bspec > * formula. */ > - if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv) || > + if (GT_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv) || > HAS_PCH_ICP(dev_priv)) { > pp_div = I915_READ(regs.pp_ctrl); > pp_div &= ~BXT_POWER_CYCLE_DELAY_MASK; > @@ -6008,7 +6008,7 @@ intel_dp_init_panel_power_sequencer_registers(struct intel_dp *intel_dp, > > I915_WRITE(regs.pp_on, pp_on); > I915_WRITE(regs.pp_off, pp_off); > - if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv) || > + if (GT_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv) || > HAS_PCH_ICP(dev_priv)) > I915_WRITE(regs.pp_ctrl, pp_div); > else > @@ -6017,7 +6017,7 @@ intel_dp_init_panel_power_sequencer_registers(struct intel_dp *intel_dp, > DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n", > I915_READ(regs.pp_on), > I915_READ(regs.pp_off), > - (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv) || > + (GT_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv) || > HAS_PCH_ICP(dev_priv)) ? > (I915_READ(regs.pp_ctrl) & BXT_POWER_CYCLE_DELAY_MASK) : > I915_READ(regs.pp_div)); > diff --git a/drivers/gpu/drm/i915/intel_dp_mst.c b/drivers/gpu/drm/i915/intel_dp_mst.c > index 8b71d64ebd9d..9bf8b86c60df 100644 > --- a/drivers/gpu/drm/i915/intel_dp_mst.c > +++ b/drivers/gpu/drm/i915/intel_dp_mst.c > @@ -98,7 +98,7 @@ static bool intel_dp_mst_compute_config(struct intel_encoder *encoder, > > pipe_config->dp_m_n.tu = slots; > > - if (IS_GEN9_LP(dev_priv)) > + if (GT_GEN9_LP(dev_priv)) > pipe_config->lane_lat_optim_mask = > bxt_ddi_phy_calc_lane_lat_optim_mask(pipe_config->lane_count); > > diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c > index 901e15063b24..5d756fdd1e7e 100644 > --- a/drivers/gpu/drm/i915/intel_dpll_mgr.c > +++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c > @@ -3212,9 +3212,9 @@ void intel_shared_dpll_init(struct drm_device *dev) > dpll_mgr = &icl_pll_mgr; > else if (IS_CANNONLAKE(dev_priv)) > dpll_mgr = &cnl_pll_mgr; > - else if (IS_GEN9_BC(dev_priv)) > + else if (GT_GEN9_BC(dev_priv)) > dpll_mgr = &skl_pll_mgr; > - else if (IS_GEN9_LP(dev_priv)) > + else if (GT_GEN9_LP(dev_priv)) > dpll_mgr = &bxt_pll_mgr; > else if (HAS_DDI(dev_priv)) > dpll_mgr = &hsw_pll_mgr; > diff --git a/drivers/gpu/drm/i915/intel_fbc.c b/drivers/gpu/drm/i915/intel_fbc.c > index 549e3dc0e457..7ed976ada979 100644 > --- a/drivers/gpu/drm/i915/intel_fbc.c > +++ b/drivers/gpu/drm/i915/intel_fbc.c > @@ -444,7 +444,7 @@ static int find_compression_threshold(struct drm_i915_private *dev_priv, > * reserved range size, so it always assumes the maximum (8mb) is used. > * If we enable FBC using a CFB on that memory range we'll get FIFO > * underruns, even if that range is not reserved by the BIOS. */ > - if (IS_BROADWELL(dev_priv) || IS_GEN9_BC(dev_priv)) > + if (IS_BROADWELL(dev_priv) || GT_GEN9_BC(dev_priv)) > end = resource_size(&dev_priv->dsm) - 8 * 1024 * 1024; > else > end = U64_MAX; > diff --git a/drivers/gpu/drm/i915/intel_guc_fw.c b/drivers/gpu/drm/i915/intel_guc_fw.c > index 9fdce47755e2..586f435633c7 100644 > --- a/drivers/gpu/drm/i915/intel_guc_fw.c > +++ b/drivers/gpu/drm/i915/intel_guc_fw.c > @@ -109,7 +109,7 @@ static void guc_prepare_xfer(struct intel_guc *guc) > GUC_ENABLE_READ_CACHE_FOR_WOPCM_DATA | > GUC_ENABLE_MIA_CLOCK_GATING); > > - if (IS_GEN9_LP(dev_priv)) > + if (GT_GEN9_LP(dev_priv)) > I915_WRITE(GEN9LP_GT_PM_CONFIG, GT_DOORBELL_ENABLE); > else > I915_WRITE(GEN9_GT_PM_CONFIG, GT_DOORBELL_ENABLE); > diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c > index bc5b945f9a71..f954c2883f92 100644 > --- a/drivers/gpu/drm/i915/intel_hdmi.c > +++ b/drivers/gpu/drm/i915/intel_hdmi.c > @@ -1529,7 +1529,7 @@ hdmi_port_clock_valid(struct intel_hdmi *hdmi, > return MODE_CLOCK_HIGH; > > /* BXT DPLL can't generate 223-240 MHz */ > - if (IS_GEN9_LP(dev_priv) && clock > 223333 && clock < 240000) > + if (GT_GEN9_LP(dev_priv) && clock > 223333 && clock < 240000) > return MODE_CLOCK_RANGE; > > /* CHV DPLL can't generate 216-240 MHz */ > @@ -2321,7 +2321,7 @@ static u8 intel_hdmi_ddc_pin(struct drm_i915_private *dev_priv, > > if (IS_CHERRYVIEW(dev_priv)) > ddc_pin = chv_port_to_ddc_pin(dev_priv, port); > - else if (IS_GEN9_LP(dev_priv)) > + else if (GT_GEN9_LP(dev_priv)) > ddc_pin = bxt_port_to_ddc_pin(dev_priv, port); > else if (HAS_PCH_CNP(dev_priv)) > ddc_pin = cnp_port_to_ddc_pin(dev_priv, port); > diff --git a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu/drm/i915/intel_i2c.c > index 33d87ab93fdd..86d898844a97 100644 > --- a/drivers/gpu/drm/i915/intel_i2c.c > +++ b/drivers/gpu/drm/i915/intel_i2c.c > @@ -93,9 +93,9 @@ static const struct gmbus_pin *get_gmbus_pin(struct drm_i915_private *dev_priv, > return &gmbus_pins_icp[pin]; > else if (HAS_PCH_CNP(dev_priv)) > return &gmbus_pins_cnp[pin]; > - else if (IS_GEN9_LP(dev_priv)) > + else if (GT_GEN9_LP(dev_priv)) > return &gmbus_pins_bxt[pin]; > - else if (IS_GEN9_BC(dev_priv)) > + else if (GT_GEN9_BC(dev_priv)) > return &gmbus_pins_skl[pin]; > else if (IS_BROADWELL(dev_priv)) > return &gmbus_pins_bdw[pin]; > @@ -112,9 +112,9 @@ bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv, > size = ARRAY_SIZE(gmbus_pins_icp); > else if (HAS_PCH_CNP(dev_priv)) > size = ARRAY_SIZE(gmbus_pins_cnp); > - else if (IS_GEN9_LP(dev_priv)) > + else if (GT_GEN9_LP(dev_priv)) > size = ARRAY_SIZE(gmbus_pins_bxt); > - else if (IS_GEN9_BC(dev_priv)) > + else if (GT_GEN9_BC(dev_priv)) > size = ARRAY_SIZE(gmbus_pins_skl); > else if (IS_BROADWELL(dev_priv)) > size = ARRAY_SIZE(gmbus_pins_bdw); > @@ -576,7 +576,7 @@ do_gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num, > int ret = 0; > > /* Display WA #0868: skl,bxt,kbl,cfl,glk,cnl */ > - if (IS_GEN9_LP(dev_priv)) > + if (GT_GEN9_LP(dev_priv)) > bxt_gmbus_clock_gating(dev_priv, false); > else if (HAS_PCH_SPT(dev_priv) || > HAS_PCH_KBP(dev_priv) || HAS_PCH_CNP(dev_priv)) > @@ -686,7 +686,7 @@ do_gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num, > > out: > /* Display WA #0868: skl,bxt,kbl,cfl,glk,cnl */ > - if (IS_GEN9_LP(dev_priv)) > + if (GT_GEN9_LP(dev_priv)) > bxt_gmbus_clock_gating(dev_priv, true); > else if (HAS_PCH_SPT(dev_priv) || > HAS_PCH_KBP(dev_priv) || HAS_PCH_CNP(dev_priv)) > diff --git a/drivers/gpu/drm/i915/intel_mocs.c b/drivers/gpu/drm/i915/intel_mocs.c > index 8201774c2c0f..6b9076fd5836 100644 > --- a/drivers/gpu/drm/i915/intel_mocs.c > +++ b/drivers/gpu/drm/i915/intel_mocs.c > @@ -178,12 +178,12 @@ static bool get_mocs_settings(struct drm_i915_private *dev_priv, > { > bool result = false; > > - if (IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv) || > + if (GT_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv) || > IS_ICELAKE(dev_priv)) { > table->size = ARRAY_SIZE(skylake_mocs_table); > table->table = skylake_mocs_table; > result = true; > - } else if (IS_GEN9_LP(dev_priv)) { > + } else if (GT_GEN9_LP(dev_priv)) { > table->size = ARRAY_SIZE(broxton_mocs_table); > table->table = broxton_mocs_table; > result = true; > diff --git a/drivers/gpu/drm/i915/intel_panel.c b/drivers/gpu/drm/i915/intel_panel.c > index e658904c5576..78d5b9da3a02 100644 > --- a/drivers/gpu/drm/i915/intel_panel.c > +++ b/drivers/gpu/drm/i915/intel_panel.c > @@ -1839,7 +1839,7 @@ intel_panel_init_backlight_funcs(struct intel_panel *panel) > intel_dsi_dcs_init_backlight_funcs(connector) == 0) > return; > > - if (IS_GEN9_LP(dev_priv)) { > + if (GT_GEN9_LP(dev_priv)) { > panel->backlight.setup = bxt_setup_backlight; > panel->backlight.enable = bxt_enable_backlight; > panel->backlight.disable = bxt_disable_backlight; > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c > index 74e14d8848f8..3a321600bb78 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -3602,7 +3602,7 @@ static bool skl_needs_memory_bw_wa(struct intel_atomic_state *state) > { > struct drm_i915_private *dev_priv = to_i915(state->base.dev); > > - if (IS_GEN9_BC(dev_priv) || IS_BROXTON(dev_priv)) > + if (GT_GEN9_BC(dev_priv) || IS_BROXTON(dev_priv)) > return true; > > return false; > @@ -3611,7 +3611,7 @@ static bool skl_needs_memory_bw_wa(struct intel_atomic_state *state) > static bool > intel_has_sagv(struct drm_i915_private *dev_priv) > { > - return (IS_GEN9_BC(dev_priv) || INTEL_GEN(dev_priv) >= 10) && > + return (GT_GEN9_BC(dev_priv) || INTEL_GEN(dev_priv) >= 10) && > dev_priv->sagv_status != I915_SAGV_NOT_CONTROLLED; > } > > @@ -6894,7 +6894,7 @@ static bool sanitize_rc6(struct drm_i915_private *i915) > info->has_rc6 = 0; > > if (info->has_rc6 && > - IS_GEN9_LP(i915) && !bxt_check_bios_rc6_setup(i915)) { > + GT_GEN9_LP(i915) && !bxt_check_bios_rc6_setup(i915)) { > DRM_INFO("RC6 disabled by BIOS\n"); > info->has_rc6 = 0; > } > @@ -6918,7 +6918,7 @@ static void gen6_init_rps_frequencies(struct drm_i915_private *dev_priv) > /* All of these values are in units of 50MHz */ > > /* static values from HW: RP0 > RP1 > RPn (min_freq) */ > - if (IS_GEN9_LP(dev_priv)) { > + if (GT_GEN9_LP(dev_priv)) { > u32 rp_state_cap = I915_READ(BXT_RP_STATE_CAP); > rps->rp0_freq = (rp_state_cap >> 16) & 0xff; > rps->rp1_freq = (rp_state_cap >> 8) & 0xff; > @@ -6934,7 +6934,7 @@ static void gen6_init_rps_frequencies(struct drm_i915_private *dev_priv) > > rps->efficient_freq = rps->rp1_freq; > if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv) || > - IS_GEN9_BC(dev_priv) || INTEL_GEN(dev_priv) >= 10) { > + GT_GEN9_BC(dev_priv) || INTEL_GEN(dev_priv) >= 10) { > u32 ddcc_status = 0; > > if (sandybridge_pcode_read(dev_priv, > @@ -6947,7 +6947,7 @@ static void gen6_init_rps_frequencies(struct drm_i915_private *dev_priv) > rps->max_freq); > } > > - if (IS_GEN9_BC(dev_priv) || INTEL_GEN(dev_priv) >= 10) { > + if (GT_GEN9_BC(dev_priv) || INTEL_GEN(dev_priv) >= 10) { > /* Store the frequency values in 16.66 MHZ units, which is > * the natural hardware unit for SKL > */ > @@ -7285,7 +7285,7 @@ static void gen6_update_ring_freq(struct drm_i915_private *dev_priv) > > min_gpu_freq = rps->min_freq; > max_gpu_freq = rps->max_freq; > - if (IS_GEN9_BC(dev_priv) || INTEL_GEN(dev_priv) >= 10) { > + if (GT_GEN9_BC(dev_priv) || INTEL_GEN(dev_priv) >= 10) { > /* Convert GT frequency to 50 HZ units */ > min_gpu_freq /= GEN9_FREQ_SCALER; > max_gpu_freq /= GEN9_FREQ_SCALER; > @@ -7300,7 +7300,7 @@ static void gen6_update_ring_freq(struct drm_i915_private *dev_priv) > const int diff = max_gpu_freq - gpu_freq; > unsigned int ia_freq = 0, ring_freq = 0; > > - if (IS_GEN9_BC(dev_priv) || INTEL_GEN(dev_priv) >= 10) { > + if (GT_GEN9_BC(dev_priv) || INTEL_GEN(dev_priv) >= 10) { > /* > * ring_freq = 2 * GT. ring_freq is in 100MHz units > * No floor required for ring frequency on SKL. > @@ -9885,7 +9885,7 @@ u64 intel_rc6_residency_ns(struct drm_i915_private *dev_priv, > time_hw = vlv_residency_raw(dev_priv, reg); > } else { > /* 833.33ns units on Gen9LP, 1.28us elsewhere. */ > - if (IS_GEN9_LP(dev_priv)) { > + if (GT_GEN9_LP(dev_priv)) { > mul = 10000; > div = 12; > } else { > diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c > index b164a2c4b058..3b78afe0a790 100644 > --- a/drivers/gpu/drm/i915/intel_runtime_pm.c > +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c > @@ -581,7 +581,7 @@ static u32 gen9_dc_mask(struct drm_i915_private *dev_priv) > mask = DC_STATE_EN_UPTO_DC5; > if (INTEL_GEN(dev_priv) >= 11) > mask |= DC_STATE_EN_UPTO_DC6 | DC_STATE_EN_DC9; > - else if (IS_GEN9_LP(dev_priv)) > + else if (GT_GEN9_LP(dev_priv)) > mask |= DC_STATE_EN_DC9; > else > mask |= DC_STATE_EN_UPTO_DC6; > @@ -725,7 +725,7 @@ void gen9_enable_dc5(struct drm_i915_private *dev_priv) > DRM_DEBUG_KMS("Enabling DC5\n"); > > /* Wa Display #1183: skl,kbl,cfl */ > - if (IS_GEN9_BC(dev_priv)) > + if (GT_GEN9_BC(dev_priv)) > I915_WRITE(GEN8_CHICKEN_DCPR_1, I915_READ(GEN8_CHICKEN_DCPR_1) | > SKL_SELECT_ALTERNATE_DC_EXIT); > > @@ -749,7 +749,7 @@ void skl_enable_dc6(struct drm_i915_private *dev_priv) > DRM_DEBUG_KMS("Enabling DC6\n"); > > /* Wa Display #1183: skl,kbl,cfl */ > - if (IS_GEN9_BC(dev_priv)) > + if (GT_GEN9_BC(dev_priv)) > I915_WRITE(GEN8_CHICKEN_DCPR_1, I915_READ(GEN8_CHICKEN_DCPR_1) | > SKL_SELECT_ALTERNATE_DC_EXIT); > > @@ -841,7 +841,7 @@ static void gen9_dc_off_power_well_enable(struct drm_i915_private *dev_priv, > > gen9_assert_dbuf_enabled(dev_priv); > > - if (IS_GEN9_LP(dev_priv)) > + if (GT_GEN9_LP(dev_priv)) > bxt_verify_ddi_phy_power_wells(dev_priv); > } > > @@ -3027,10 +3027,10 @@ static uint32_t get_allowed_dc_mask(const struct drm_i915_private *dev_priv, > * suspend/resume, so allow it unconditionally. > */ > mask = DC_STATE_EN_DC9; > - } else if (GT_GEN(dev_priv, 10) || IS_GEN9_BC(dev_priv)) { > + } else if (GT_GEN(dev_priv, 10) || GT_GEN9_BC(dev_priv)) { > max_dc = 2; > mask = 0; > - } else if (IS_GEN9_LP(dev_priv)) { > + } else if (GT_GEN9_LP(dev_priv)) { > max_dc = 1; > mask = DC_STATE_EN_DC9; > } else { > @@ -3143,7 +3143,7 @@ int intel_power_domains_init(struct drm_i915_private *dev_priv) > err = set_power_wells(power_domains, glk_power_wells); > } else if (IS_BROXTON(dev_priv)) { > err = set_power_wells(power_domains, bxt_power_wells); > - } else if (IS_GEN9_BC(dev_priv)) { > + } else if (GT_GEN9_BC(dev_priv)) { > err = set_power_wells(power_domains, skl_power_wells); > } else if (IS_CHERRYVIEW(dev_priv)) { > err = set_power_wells(power_domains, chv_power_wells); > @@ -3814,9 +3814,9 @@ void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume) > icl_display_core_init(dev_priv, resume); > } else if (IS_CANNONLAKE(dev_priv)) { > cnl_display_core_init(dev_priv, resume); > - } else if (IS_GEN9_BC(dev_priv)) { > + } else if (GT_GEN9_BC(dev_priv)) { > skl_display_core_init(dev_priv, resume); > - } else if (IS_GEN9_LP(dev_priv)) { > + } else if (GT_GEN9_LP(dev_priv)) { > bxt_display_core_init(dev_priv, resume); > } else if (IS_CHERRYVIEW(dev_priv)) { > mutex_lock(&power_domains->lock); > @@ -3945,9 +3945,9 @@ void intel_power_domains_suspend(struct drm_i915_private *dev_priv, > icl_display_core_uninit(dev_priv); > else if (IS_CANNONLAKE(dev_priv)) > cnl_display_core_uninit(dev_priv); > - else if (IS_GEN9_BC(dev_priv)) > + else if (GT_GEN9_BC(dev_priv)) > skl_display_core_uninit(dev_priv); > - else if (IS_GEN9_LP(dev_priv)) > + else if (GT_GEN9_LP(dev_priv)) > bxt_display_core_uninit(dev_priv); > > power_domains->display_core_suspended = true; > diff --git a/drivers/gpu/drm/i915/intel_wopcm.c b/drivers/gpu/drm/i915/intel_wopcm.c > index 3987207cddd0..0a5c68acf3dd 100644 > --- a/drivers/gpu/drm/i915/intel_wopcm.c > +++ b/drivers/gpu/drm/i915/intel_wopcm.c > @@ -78,7 +78,7 @@ void intel_wopcm_init_early(struct intel_wopcm *wopcm) > > static inline u32 context_reserved_size(struct drm_i915_private *i915) > { > - if (IS_GEN9_LP(i915)) > + if (GT_GEN9_LP(i915)) > return BXT_WOPCM_RC6_CTX_RESERVED; > else if (INTEL_GEN(i915) >= 10) > return CNL_WOPCM_HW_CTX_RESERVED; > diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c > index d7176213e3ce..db899cc5c981 100644 > --- a/drivers/gpu/drm/i915/intel_workarounds.c > +++ b/drivers/gpu/drm/i915/intel_workarounds.c > @@ -300,7 +300,7 @@ static int gen9_ctx_workarounds_init(struct drm_i915_private *dev_priv) > GEN9_PREEMPT_GPGPU_COMMAND_LEVEL); > > /* WaClearHIZ_WM_CHICKEN3:bxt,glk */ > - if (IS_GEN9_LP(dev_priv)) > + if (GT_GEN9_LP(dev_priv)) > WA_SET_BIT_MASKED(GEN9_WM_CHICKEN3, GEN9_FACTOR_IN_CLR_VAL_HIZ); > > return 0; > @@ -620,7 +620,7 @@ static void gen9_gt_workarounds_apply(struct drm_i915_private *dev_priv) > BDW_DISABLE_HDC_INVALIDATION); > > /* WaProgramL3SqcReg1DefaultForPerf:bxt,glk */ > - if (IS_GEN9_LP(dev_priv)) { > + if (GT_GEN9_LP(dev_priv)) { > u32 val = I915_READ(GEN8_L3SQCREG1); > > val &= ~L3_PRIO_CREDITS_MASK; > diff --git a/drivers/gpu/drm/i915/vlv_dsi.c b/drivers/gpu/drm/i915/vlv_dsi.c > index bab87b62bc2d..a06221dca0ec 100644 > --- a/drivers/gpu/drm/i915/vlv_dsi.c > +++ b/drivers/gpu/drm/i915/vlv_dsi.c > @@ -290,7 +290,7 @@ static bool intel_dsi_compute_config(struct intel_encoder *encoder, > /* DSI uses short packets for sync events, so clear mode flags for DSI */ > adjusted_mode->flags = 0; > > - if (IS_GEN9_LP(dev_priv)) { > + if (GT_GEN9_LP(dev_priv)) { > /* Enable Frame time stamp based scanline reporting */ > adjusted_mode->private_flags |= > I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP; > @@ -510,7 +510,7 @@ static void intel_dsi_device_ready(struct intel_encoder *encoder) > > if (IS_GEMINILAKE(dev_priv)) > glk_dsi_device_ready(encoder); > - else if (IS_GEN9_LP(dev_priv)) > + else if (GT_GEN9_LP(dev_priv)) > bxt_dsi_device_ready(encoder); > else > vlv_dsi_device_ready(encoder); > @@ -591,7 +591,7 @@ static void vlv_dsi_clear_device_ready(struct intel_encoder *encoder) > DRM_DEBUG_KMS("\n"); > for_each_dsi_port(port, intel_dsi->ports) { > /* Common bit for both MIPI Port A & MIPI Port C on VLV/CHV */ > - i915_reg_t port_ctrl = IS_GEN9_LP(dev_priv) ? > + i915_reg_t port_ctrl = GT_GEN9_LP(dev_priv) ? > BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(PORT_A); > u32 val; > > @@ -611,7 +611,7 @@ static void vlv_dsi_clear_device_ready(struct intel_encoder *encoder) > * On VLV/CHV, wait till Clock lanes are in LP-00 state for MIPI > * Port A only. MIPI Port C has no similar bit for checking. > */ > - if ((IS_GEN9_LP(dev_priv) || port == PORT_A) && > + if ((GT_GEN9_LP(dev_priv) || port == PORT_A) && > intel_wait_for_register(dev_priv, > port_ctrl, AFE_LATCHOUT, 0, > 30)) > @@ -637,7 +637,7 @@ static void intel_dsi_port_enable(struct intel_encoder *encoder, > > if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) { > u32 temp; > - if (IS_GEN9_LP(dev_priv)) { > + if (GT_GEN9_LP(dev_priv)) { > for_each_dsi_port(port, intel_dsi->ports) { > temp = I915_READ(MIPI_CTRL(port)); > temp &= ~BXT_PIXEL_OVERLAP_CNT_MASK | > @@ -655,7 +655,7 @@ static void intel_dsi_port_enable(struct intel_encoder *encoder, > } > > for_each_dsi_port(port, intel_dsi->ports) { > - i915_reg_t port_ctrl = IS_GEN9_LP(dev_priv) ? > + i915_reg_t port_ctrl = GT_GEN9_LP(dev_priv) ? > BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port); > u32 temp; > > @@ -688,7 +688,7 @@ static void intel_dsi_port_disable(struct intel_encoder *encoder) > enum port port; > > for_each_dsi_port(port, intel_dsi->ports) { > - i915_reg_t port_ctrl = IS_GEN9_LP(dev_priv) ? > + i915_reg_t port_ctrl = GT_GEN9_LP(dev_priv) ? > BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port); > u32 temp; > > @@ -765,7 +765,7 @@ static void intel_dsi_pre_enable(struct intel_encoder *encoder, > * The BIOS may leave the PLL in a wonky state where it doesn't > * lock. It needs to be fully powered down to fix it. > */ > - if (IS_GEN9_LP(dev_priv)) { > + if (GT_GEN9_LP(dev_priv)) { > bxt_dsi_pll_disable(encoder); > bxt_dsi_pll_enable(encoder, pipe_config); > } else { > @@ -927,7 +927,7 @@ static void intel_dsi_post_disable(struct intel_encoder *encoder, > val & ~MIPIO_RST_CTRL); > } > > - if (IS_GEN9_LP(dev_priv)) { > + if (GT_GEN9_LP(dev_priv)) { > bxt_dsi_pll_disable(encoder); > } else { > u32 val; > @@ -974,12 +974,12 @@ static bool intel_dsi_get_hw_state(struct intel_encoder *encoder, > * configuration, otherwise accessing DSI registers will hang the > * machine. See BSpec North Display Engine registers/MIPI[BXT]. > */ > - if (IS_GEN9_LP(dev_priv) && !bxt_dsi_pll_is_enabled(dev_priv)) > + if (GT_GEN9_LP(dev_priv) && !bxt_dsi_pll_is_enabled(dev_priv)) > goto out_put_power; > > /* XXX: this only works for one DSI output */ > for_each_dsi_port(port, intel_dsi->ports) { > - i915_reg_t ctrl_reg = IS_GEN9_LP(dev_priv) ? > + i915_reg_t ctrl_reg = GT_GEN9_LP(dev_priv) ? > BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port); > bool enabled = I915_READ(ctrl_reg) & DPI_ENABLE; > > @@ -1004,7 +1004,7 @@ static bool intel_dsi_get_hw_state(struct intel_encoder *encoder, > if (!(I915_READ(MIPI_DEVICE_READY(port)) & DEVICE_READY)) > continue; > > - if (IS_GEN9_LP(dev_priv)) { > + if (GT_GEN9_LP(dev_priv)) { > u32 tmp = I915_READ(MIPI_CTRL(port)); > tmp &= BXT_PIPE_SELECT_MASK; > tmp >>= BXT_PIPE_SELECT_SHIFT; > @@ -1197,7 +1197,7 @@ static void intel_dsi_get_config(struct intel_encoder *encoder, > > pipe_config->output_types |= BIT(INTEL_OUTPUT_DSI); > > - if (IS_GEN9_LP(dev_priv)) { > + if (GT_GEN9_LP(dev_priv)) { > bxt_dsi_get_pipe_config(encoder, pipe_config); > pclk = bxt_dsi_get_pclk(encoder, pipe_config->pipe_bpp, > pipe_config); > @@ -1265,7 +1265,7 @@ static void set_dsi_timings(struct drm_encoder *encoder, > hbp = txbyteclkhs(hbp, bpp, lane_count, intel_dsi->burst_mode_ratio); > > for_each_dsi_port(port, intel_dsi->ports) { > - if (IS_GEN9_LP(dev_priv)) { > + if (GT_GEN9_LP(dev_priv)) { > /* > * Program hdisplay and vdisplay on MIPI transcoder. > * This is different from calculated hactive and > @@ -1352,7 +1352,7 @@ static void intel_dsi_prepare(struct intel_encoder *intel_encoder, > tmp &= ~READ_REQUEST_PRIORITY_MASK; > I915_WRITE(MIPI_CTRL(port), tmp | > READ_REQUEST_PRIORITY_HIGH); > - } else if (IS_GEN9_LP(dev_priv)) { > + } else if (GT_GEN9_LP(dev_priv)) { > enum pipe pipe = intel_crtc->pipe; > > tmp = I915_READ(MIPI_CTRL(port)); > @@ -1390,7 +1390,7 @@ static void intel_dsi_prepare(struct intel_encoder *intel_encoder, > if (intel_dsi->clock_stop) > tmp |= CLOCKSTOP; > > - if (IS_GEN9_LP(dev_priv)) { > + if (GT_GEN9_LP(dev_priv)) { > tmp |= BXT_DPHY_DEFEATURE_EN; > if (!is_cmd_mode(intel_dsi)) > tmp |= BXT_DEFEATURE_DPI_FIFO_CTR; > @@ -1441,7 +1441,7 @@ static void intel_dsi_prepare(struct intel_encoder *intel_encoder, > I915_WRITE(MIPI_INIT_COUNT(port), > txclkesc(intel_dsi->escape_clk_div, 100)); > > - if (IS_GEN9_LP(dev_priv) && (!intel_dsi->dual_link)) { > + if (GT_GEN9_LP(dev_priv) && (!intel_dsi->dual_link)) { > /* > * BXT spec says write MIPI_INIT_COUNT for > * both the ports, even if only one is > @@ -1520,7 +1520,7 @@ static void intel_dsi_unprepare(struct intel_encoder *encoder) > /* Panel commands can be sent when clock is in LP11 */ > I915_WRITE(MIPI_DEVICE_READY(port), 0x0); > > - if (IS_GEN9_LP(dev_priv)) > + if (GT_GEN9_LP(dev_priv)) > bxt_dsi_reset_clocks(encoder, port); > else > vlv_dsi_reset_clocks(encoder, port); > @@ -1629,7 +1629,7 @@ void vlv_dsi_init(struct drm_i915_private *dev_priv) > if (!intel_bios_is_dsi_present(dev_priv, &port)) > return; > > - if (IS_GEN9_LP(dev_priv)) > + if (GT_GEN9_LP(dev_priv)) > dev_priv->mipi_mmio_base = BXT_MIPI_BASE; > else > dev_priv->mipi_mmio_base = VLV_MIPI_BASE; > @@ -1668,7 +1668,7 @@ void vlv_dsi_init(struct drm_i915_private *dev_priv) > * On BYT/CHV, pipe A maps to MIPI DSI port A, pipe B maps to MIPI DSI > * port C. BXT isn't limited like this. > */ > - if (IS_GEN9_LP(dev_priv)) > + if (GT_GEN9_LP(dev_priv)) > intel_encoder->crtc_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C); > else if (port == PORT_A) > intel_encoder->crtc_mask = BIT(PIPE_A); > -- > 2.19.1.1.g56c4683e68 > _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 38+ messages in thread
* [PATCH v2 5/7] drm/i915: replace gen checks using operators by GT_GEN/GT_GEN_RANGE 2018-11-06 21:51 [PATCH v2 0/7] Make GEN macros more similar Lucas De Marchi ` (3 preceding siblings ...) 2018-11-06 21:51 ` [PATCH v2 4/7] drm/i915: rename IS_GEN9_* to GT_GEN9_* Lucas De Marchi @ 2018-11-06 21:51 ` Lucas De Marchi 2018-11-06 21:51 ` [PATCH v2 6/7] drm/i915: merge gen checks to use range Lucas De Marchi ` (6 subsequent siblings) 11 siblings, 0 replies; 38+ messages in thread From: Lucas De Marchi @ 2018-11-06 21:51 UTC (permalink / raw) To: intel-gfx; +Cc: Rodrigo Vivi By using only the mask turn the GT GEN checks to use always the same macros. This opens the possibility for the compiler to merge the bitfields and make it easier to extend for other gens. This patch has been generated in 2 steps due to my lack of knowledge on how to make the embedded python to work with Coccinelle. First the the following spatch: @gt@ expression E; constant C; @@ - INTEL_GEN(E) > C + GT_GEN_RANGE(E, C + ONE___FIXMEUP, GEN_FOREVER) @lt@ expression E; constant C; @@ - INTEL_GEN(E) < C + GT_GEN_RANGE(E, 0, C - ONE___FIXMEUP) @eq@ expression E; constant C; @@ - INTEL_GEN(E) == C + GT_GEN(E, C) @ge@ expression E; constant C; @@ - INTEL_GEN(E) >= C + GT_GEN_RANGE(E, C, GEN_FOREVER) @le@ expression E; constant C; @@ - INTEL_GEN(E) <= C + GT_GEN_RANGE(E, 0, C) Accompanied with the followup awk script due to my lack of knowledge on how to use it with Coccinelle only: awk -i inplace ' match($0, /([0-9]+) - ONE___FIXMEUP/, oldgen) { newgen = oldgen[0] - 1; gsub(/[0-9]+ - ONE___FIXMEUP/, newgen); } /.*/ { print $0 }' drivers/gpu/drm/i915/{*.[ch],*/*[.ch]} awk -i inplace ' match($0, /([0-9]+) \+ ONE___FIXMEUP/, oldgen) { newgen = oldgen[0] + 1; gsub(/[0-9]+ \+ ONE___FIXMEUP/, newgen); } /.*/ { print $0 }' drivers/gpu/drm/i915/{*.[ch],*/*[.ch]} Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> --- drivers/gpu/drm/i915/gvt/gtt.c | 4 +- drivers/gpu/drm/i915/gvt/handlers.c | 2 +- drivers/gpu/drm/i915/i915_debugfs.c | 107 ++++----- drivers/gpu/drm/i915/i915_drv.c | 26 +-- drivers/gpu/drm/i915/i915_drv.h | 18 +- drivers/gpu/drm/i915/i915_gem.c | 18 +- drivers/gpu/drm/i915/i915_gem_context.c | 2 +- drivers/gpu/drm/i915/i915_gem_execbuffer.c | 2 +- drivers/gpu/drm/i915/i915_gem_fence_reg.c | 6 +- drivers/gpu/drm/i915/i915_gem_gtt.c | 26 +-- drivers/gpu/drm/i915/i915_gem_stolen.c | 6 +- drivers/gpu/drm/i915/i915_gem_tiling.c | 8 +- drivers/gpu/drm/i915/i915_gpu_error.c | 42 ++-- drivers/gpu/drm/i915/i915_irq.c | 88 +++---- drivers/gpu/drm/i915/i915_perf.c | 2 +- drivers/gpu/drm/i915/i915_pmu.c | 6 +- drivers/gpu/drm/i915/i915_reg.h | 4 +- drivers/gpu/drm/i915/i915_suspend.c | 12 +- drivers/gpu/drm/i915/i915_sysfs.c | 2 +- drivers/gpu/drm/i915/intel_atomic.c | 2 +- drivers/gpu/drm/i915/intel_audio.c | 2 +- drivers/gpu/drm/i915/intel_bios.c | 4 +- drivers/gpu/drm/i915/intel_cdclk.c | 8 +- drivers/gpu/drm/i915/intel_color.c | 4 +- drivers/gpu/drm/i915/intel_crt.c | 6 +- drivers/gpu/drm/i915/intel_ddi.c | 16 +- drivers/gpu/drm/i915/intel_device_info.c | 18 +- drivers/gpu/drm/i915/intel_display.c | 216 +++++++++--------- drivers/gpu/drm/i915/intel_dp.c | 32 +-- drivers/gpu/drm/i915/intel_dpll_mgr.c | 6 +- drivers/gpu/drm/i915/intel_drv.h | 2 +- drivers/gpu/drm/i915/intel_engine_cs.c | 28 +-- drivers/gpu/drm/i915/intel_fbc.c | 26 +-- drivers/gpu/drm/i915/intel_fifo_underrun.c | 2 +- drivers/gpu/drm/i915/intel_hangcheck.c | 2 +- drivers/gpu/drm/i915/intel_hdcp.c | 2 +- drivers/gpu/drm/i915/intel_hdmi.c | 14 +- drivers/gpu/drm/i915/intel_i2c.c | 2 +- drivers/gpu/drm/i915/intel_lrc.c | 20 +- drivers/gpu/drm/i915/intel_lvds.c | 10 +- drivers/gpu/drm/i915/intel_mocs.c | 2 +- drivers/gpu/drm/i915/intel_overlay.c | 2 +- drivers/gpu/drm/i915/intel_panel.c | 10 +- drivers/gpu/drm/i915/intel_pipe_crc.c | 4 +- drivers/gpu/drm/i915/intel_pm.c | 128 +++++------ drivers/gpu/drm/i915/intel_psr.c | 22 +- drivers/gpu/drm/i915/intel_ringbuffer.c | 32 +-- drivers/gpu/drm/i915/intel_runtime_pm.c | 10 +- drivers/gpu/drm/i915/intel_sdvo.c | 14 +- drivers/gpu/drm/i915/intel_sprite.c | 28 +-- drivers/gpu/drm/i915/intel_tv.c | 2 +- drivers/gpu/drm/i915/intel_uc.c | 2 +- drivers/gpu/drm/i915/intel_uncore.c | 30 +-- drivers/gpu/drm/i915/intel_wopcm.c | 2 +- drivers/gpu/drm/i915/intel_workarounds.c | 10 +- .../drm/i915/selftests/i915_gem_coherency.c | 4 +- .../gpu/drm/i915/selftests/i915_gem_context.c | 8 +- .../gpu/drm/i915/selftests/i915_gem_object.c | 12 +- .../gpu/drm/i915/selftests/intel_hangcheck.c | 8 +- drivers/gpu/drm/i915/selftests/intel_lrc.c | 2 +- drivers/gpu/drm/i915/selftests/intel_uncore.c | 2 +- .../drm/i915/selftests/intel_workarounds.c | 2 +- 62 files changed, 570 insertions(+), 569 deletions(-) diff --git a/drivers/gpu/drm/i915/gvt/gtt.c b/drivers/gpu/drm/i915/gvt/gtt.c index 2402395a068d..bc79c154391d 100644 --- a/drivers/gpu/drm/i915/gvt/gtt.c +++ b/drivers/gpu/drm/i915/gvt/gtt.c @@ -1025,12 +1025,12 @@ static bool vgpu_ips_enabled(struct intel_vgpu *vgpu) { struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; - if (INTEL_GEN(dev_priv) == 9 || INTEL_GEN(dev_priv) == 10) { + if (GT_GEN(dev_priv, 9) || GT_GEN(dev_priv, 10)) { u32 ips = vgpu_vreg_t(vgpu, GEN8_GAMW_ECO_DEV_RW_IA) & GAMW_ECO_ENABLE_64K_IPS_FIELD; return ips == GAMW_ECO_ENABLE_64K_IPS_FIELD; - } else if (INTEL_GEN(dev_priv) >= 11) { + } else if (GT_GEN_RANGE(dev_priv, 11, GEN_FOREVER)) { /* 64K paging only controlled by IPS bit in PTE now. */ return true; } else diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c index 90f50f67909a..0dec066dab5d 100644 --- a/drivers/gpu/drm/i915/gvt/handlers.c +++ b/drivers/gpu/drm/i915/gvt/handlers.c @@ -215,7 +215,7 @@ static int gamw_echo_dev_rw_ia_write(struct intel_vgpu *vgpu, { u32 ips = (*(u32 *)p_data) & GAMW_ECO_ENABLE_64K_IPS_FIELD; - if (INTEL_GEN(vgpu->gvt->dev_priv) <= 10) { + if (GT_GEN_RANGE(vgpu->gvt->dev_priv, 0, 10)) { if (ips == GAMW_ECO_ENABLE_64K_IPS_FIELD) gvt_dbg_core("vgpu%d: ips enabled\n", vgpu->id); else if (!ips) diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index 5e4a934c0dea..ec26076aaecc 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -762,7 +762,7 @@ static int i915_interrupt_info(struct seq_file *m, void *data) I915_READ(GEN8_PCU_IIR)); seq_printf(m, "PCU interrupt enable:\t%08x\n", I915_READ(GEN8_PCU_IER)); - } else if (INTEL_GEN(dev_priv) >= 11) { + } else if (GT_GEN_RANGE(dev_priv, 11, GEN_FOREVER)) { seq_printf(m, "Master Interrupt Control: %08x\n", I915_READ(GEN11_GFX_MSTR_IRQ)); @@ -783,7 +783,7 @@ static int i915_interrupt_info(struct seq_file *m, void *data) I915_READ(GEN11_DISPLAY_INT_CTL)); gen8_display_interrupt_info(m); - } else if (INTEL_GEN(dev_priv) >= 8) { + } else if (GT_GEN_RANGE(dev_priv, 8, GEN_FOREVER)) { seq_printf(m, "Master Interrupt Control:\t%08x\n", I915_READ(GEN8_MASTER_IRQ)); @@ -879,7 +879,7 @@ static int i915_interrupt_info(struct seq_file *m, void *data) I915_READ(GTIMR)); } - if (INTEL_GEN(dev_priv) >= 11) { + if (GT_GEN_RANGE(dev_priv, 11, GEN_FOREVER)) { seq_printf(m, "RCS Intr Mask:\t %08x\n", I915_READ(GEN11_RCS0_RSVD_INTR_MASK)); seq_printf(m, "BCS Intr Mask:\t %08x\n", @@ -899,7 +899,7 @@ static int i915_interrupt_info(struct seq_file *m, void *data) seq_printf(m, "Gunit/CSME Intr Mask:\t %08x\n", I915_READ(GEN11_GUNIT_CSME_INTR_MASK)); - } else if (INTEL_GEN(dev_priv) >= 6) { + } else if (GT_GEN_RANGE(dev_priv, 6, GEN_FOREVER)) { for_each_engine(engine, dev_priv, id) { seq_printf(m, "Graphics Interrupt mask (%s): %08x\n", @@ -1111,7 +1111,7 @@ static int i915_frequency_info(struct seq_file *m, void *unused) "efficient (RPe) frequency: %d MHz\n", intel_gpu_freq(dev_priv, rps->efficient_freq)); mutex_unlock(&dev_priv->pcu_lock); - } else if (INTEL_GEN(dev_priv) >= 6) { + } else if (GT_GEN_RANGE(dev_priv, 6, GEN_FOREVER)) { u32 rp_state_limits; u32 gt_perf_status; u32 rp_state_cap; @@ -1135,7 +1135,7 @@ static int i915_frequency_info(struct seq_file *m, void *unused) intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); reqf = I915_READ(GEN6_RPNSWREQ); - if (INTEL_GEN(dev_priv) >= 9) + if (GT_GEN_RANGE(dev_priv, 9, GEN_FOREVER)) reqf >>= 23; else { reqf &= ~GEN6_TURBO_DISABLE; @@ -1162,7 +1162,7 @@ static int i915_frequency_info(struct seq_file *m, void *unused) intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); - if (INTEL_GEN(dev_priv) >= 11) { + if (GT_GEN_RANGE(dev_priv, 11, GEN_FOREVER)) { pm_ier = I915_READ(GEN11_GPM_WGBOXPERF_INTR_ENABLE); pm_imr = I915_READ(GEN11_GPM_WGBOXPERF_INTR_MASK); /* @@ -1171,7 +1171,7 @@ static int i915_frequency_info(struct seq_file *m, void *unused) */ pm_isr = 0; pm_iir = 0; - } else if (INTEL_GEN(dev_priv) >= 8) { + } else if (GT_GEN_RANGE(dev_priv, 8, GEN_FOREVER)) { pm_ier = I915_READ(GEN8_GT_IER(2)); pm_imr = I915_READ(GEN8_GT_IMR(2)); pm_isr = I915_READ(GEN8_GT_ISR(2)); @@ -1194,14 +1194,14 @@ static int i915_frequency_info(struct seq_file *m, void *unused) seq_printf(m, "PM IER=0x%08x IMR=0x%08x, MASK=0x%08x\n", pm_ier, pm_imr, pm_mask); - if (INTEL_GEN(dev_priv) <= 10) + if (GT_GEN_RANGE(dev_priv, 0, 10)) seq_printf(m, "PM ISR=0x%08x IIR=0x%08x\n", pm_isr, pm_iir); seq_printf(m, "pm_intrmsk_mbz: 0x%08x\n", rps->pm_intrmsk_mbz); seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status); seq_printf(m, "Render p-state ratio: %d\n", - (gt_perf_status & (INTEL_GEN(dev_priv) >= 9 ? 0x1ff00 : 0xff00)) >> 8); + (gt_perf_status & (GT_GEN_RANGE(dev_priv, 9, GEN_FOREVER) ? 0x1ff00 : 0xff00)) >> 8); seq_printf(m, "Render p-state VID: %d\n", gt_perf_status & 0xff); seq_printf(m, "Render p-state limit: %d\n", @@ -1233,20 +1233,20 @@ static int i915_frequency_info(struct seq_file *m, void *unused) max_freq = (GT_GEN9_LP(dev_priv) ? rp_state_cap >> 0 : rp_state_cap >> 16) & 0xff; max_freq *= (GT_GEN9_BC(dev_priv) || - INTEL_GEN(dev_priv) >= 10 ? GEN9_FREQ_SCALER : 1); + GT_GEN_RANGE(dev_priv, 10, GEN_FOREVER) ? GEN9_FREQ_SCALER : 1); seq_printf(m, "Lowest (RPN) frequency: %dMHz\n", intel_gpu_freq(dev_priv, max_freq)); max_freq = (rp_state_cap & 0xff00) >> 8; max_freq *= (GT_GEN9_BC(dev_priv) || - INTEL_GEN(dev_priv) >= 10 ? GEN9_FREQ_SCALER : 1); + GT_GEN_RANGE(dev_priv, 10, GEN_FOREVER) ? GEN9_FREQ_SCALER : 1); seq_printf(m, "Nominal (RP1) frequency: %dMHz\n", intel_gpu_freq(dev_priv, max_freq)); max_freq = (GT_GEN9_LP(dev_priv) ? rp_state_cap >> 16 : rp_state_cap >> 0) & 0xff; max_freq *= (GT_GEN9_BC(dev_priv) || - INTEL_GEN(dev_priv) >= 10 ? GEN9_FREQ_SCALER : 1); + GT_GEN_RANGE(dev_priv, 10, GEN_FOREVER) ? GEN9_FREQ_SCALER : 1); seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n", intel_gpu_freq(dev_priv, max_freq)); seq_printf(m, "Max overclocked frequency: %dMHz\n", @@ -1288,13 +1288,13 @@ static void i915_instdone_info(struct drm_i915_private *dev_priv, seq_printf(m, "\t\tINSTDONE: 0x%08x\n", instdone->instdone); - if (INTEL_GEN(dev_priv) <= 3) + if (GT_GEN_RANGE(dev_priv, 0, 3)) return; seq_printf(m, "\t\tSC_INSTDONE: 0x%08x\n", instdone->slice_common); - if (INTEL_GEN(dev_priv) <= 6) + if (GT_GEN_RANGE(dev_priv, 0, 6)) return; for_each_instdone_slice_subslice(dev_priv, slice, subslice) @@ -1535,12 +1535,12 @@ static int gen6_drpc_info(struct seq_file *m) trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true); rcctl1 = I915_READ(GEN6_RC_CONTROL); - if (INTEL_GEN(dev_priv) >= 9) { + if (GT_GEN_RANGE(dev_priv, 9, GEN_FOREVER)) { gen9_powergate_enable = I915_READ(GEN9_PG_ENABLE); gen9_powergate_status = I915_READ(GEN9_PWRGT_DOMAIN_STATUS); } - if (INTEL_GEN(dev_priv) <= 7) { + if (GT_GEN_RANGE(dev_priv, 0, 7)) { mutex_lock(&dev_priv->pcu_lock); sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids); @@ -1551,7 +1551,7 @@ static int gen6_drpc_info(struct seq_file *m) yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE)); seq_printf(m, "RC6 Enabled: %s\n", yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE)); - if (INTEL_GEN(dev_priv) >= 9) { + if (GT_GEN_RANGE(dev_priv, 9, GEN_FOREVER)) { seq_printf(m, "Render Well Gating Enabled: %s\n", yesno(gen9_powergate_enable & GEN9_RENDER_PG_ENABLE)); seq_printf(m, "Media Well Gating Enabled: %s\n", @@ -1585,7 +1585,7 @@ static int gen6_drpc_info(struct seq_file *m) seq_printf(m, "Core Power Down: %s\n", yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK)); - if (INTEL_GEN(dev_priv) >= 9) { + if (GT_GEN_RANGE(dev_priv, 9, GEN_FOREVER)) { seq_printf(m, "Render Power Well: %s\n", (gen9_powergate_status & GEN9_PWRGT_RENDER_STATUS_MASK) ? "Up" : "Down"); @@ -1601,7 +1601,7 @@ static int gen6_drpc_info(struct seq_file *m) print_rc6_res(m, "RC6+ residency since boot:", GEN6_GT_GFX_RC6p); print_rc6_res(m, "RC6++ residency since boot:", GEN6_GT_GFX_RC6pp); - if (INTEL_GEN(dev_priv) <= 7) { + if (GT_GEN_RANGE(dev_priv, 0, 7)) { seq_printf(m, "RC6 voltage: %dmV\n", GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff))); seq_printf(m, "RC6+ voltage: %dmV\n", @@ -1622,7 +1622,7 @@ static int i915_drpc_info(struct seq_file *m, void *unused) if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) err = vlv_drpc_info(m); - else if (INTEL_GEN(dev_priv) >= 6) + else if (GT_GEN_RANGE(dev_priv, 6, GEN_FOREVER)) err = gen6_drpc_info(m); else err = ironlake_drpc_info(m); @@ -1664,11 +1664,11 @@ static int i915_fbc_status(struct seq_file *m, void *unused) if (intel_fbc_is_active(dev_priv)) { u32 mask; - if (INTEL_GEN(dev_priv) >= 8) + if (GT_GEN_RANGE(dev_priv, 8, GEN_FOREVER)) mask = I915_READ(IVB_FBC_STATUS2) & BDW_FBC_COMP_SEG_MASK; - else if (INTEL_GEN(dev_priv) >= 7) + else if (GT_GEN_RANGE(dev_priv, 7, GEN_FOREVER)) mask = I915_READ(IVB_FBC_STATUS2) & IVB_FBC_COMP_SEG_MASK; - else if (INTEL_GEN(dev_priv) >= 5) + else if (GT_GEN_RANGE(dev_priv, 5, GEN_FOREVER)) mask = I915_READ(ILK_DPFC_STATUS) & ILK_DPFC_COMP_SEG_MASK; else if (IS_G4X(dev_priv)) mask = I915_READ(DPFC_STATUS) & DPFC_COMP_SEG_MASK; @@ -1689,7 +1689,7 @@ static int i915_fbc_false_color_get(void *data, u64 *val) { struct drm_i915_private *dev_priv = data; - if (INTEL_GEN(dev_priv) < 7 || !HAS_FBC(dev_priv)) + if (GT_GEN_RANGE(dev_priv, 0, 6) || !HAS_FBC(dev_priv)) return -ENODEV; *val = dev_priv->fbc.false_color; @@ -1702,7 +1702,7 @@ static int i915_fbc_false_color_set(void *data, u64 val) struct drm_i915_private *dev_priv = data; u32 reg; - if (INTEL_GEN(dev_priv) < 7 || !HAS_FBC(dev_priv)) + if (GT_GEN_RANGE(dev_priv, 0, 6) || !HAS_FBC(dev_priv)) return -ENODEV; mutex_lock(&dev_priv->fbc.lock); @@ -1734,7 +1734,7 @@ static int i915_ips_status(struct seq_file *m, void *unused) seq_printf(m, "Enabled by kernel parameter: %s\n", yesno(i915_modparams.enable_ips)); - if (INTEL_GEN(dev_priv) >= 8) { + if (GT_GEN_RANGE(dev_priv, 8, GEN_FOREVER)) { seq_puts(m, "Currently: unknown\n"); } else { if (I915_READ(IPS_CTL) & IPS_ENABLE) @@ -1756,7 +1756,7 @@ static int i915_sr_status(struct seq_file *m, void *unused) intel_runtime_pm_get(dev_priv); intel_display_power_get(dev_priv, POWER_DOMAIN_INIT); - if (INTEL_GEN(dev_priv) >= 9) + if (GT_GEN_RANGE(dev_priv, 9, GEN_FOREVER)) /* no global SR status; inspect per-plane WM */; else if (HAS_PCH_SPLIT(dev_priv)) sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN; @@ -1824,7 +1824,7 @@ static int i915_ring_freq_table(struct seq_file *m, void *unused) min_gpu_freq = rps->min_freq; max_gpu_freq = rps->max_freq; - if (GT_GEN9_BC(dev_priv) || INTEL_GEN(dev_priv) >= 10) { + if (GT_GEN9_BC(dev_priv) || GT_GEN_RANGE(dev_priv, 10, GEN_FOREVER)) { /* Convert GT frequency to 50 HZ units */ min_gpu_freq /= GEN9_FREQ_SCALER; max_gpu_freq /= GEN9_FREQ_SCALER; @@ -1840,7 +1840,7 @@ static int i915_ring_freq_table(struct seq_file *m, void *unused) seq_printf(m, "%d\t\t%d\t\t\t\t%d\n", intel_gpu_freq(dev_priv, (gpu_freq * (GT_GEN9_BC(dev_priv) || - INTEL_GEN(dev_priv) >= 10 ? + GT_GEN_RANGE(dev_priv, 10, GEN_FOREVER) ? GEN9_FREQ_SCALER : 1))), ((ia_freq >> 0) & 0xff) * 100, ((ia_freq >> 8) & 0xff) * 100); @@ -2039,7 +2039,7 @@ static int i915_swizzle_info(struct seq_file *m, void *data) I915_READ16(C0DRB3)); seq_printf(m, "C1DRB3 = 0x%04x\n", I915_READ16(C1DRB3)); - } else if (INTEL_GEN(dev_priv) >= 6) { + } else if (GT_GEN_RANGE(dev_priv, 6, GEN_FOREVER)) { seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n", I915_READ(MAD_DIMM_C0)); seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n", @@ -2048,7 +2048,7 @@ static int i915_swizzle_info(struct seq_file *m, void *data) I915_READ(MAD_DIMM_C2)); seq_printf(m, "TILECTL = 0x%08x\n", I915_READ(TILECTL)); - if (INTEL_GEN(dev_priv) >= 8) + if (GT_GEN_RANGE(dev_priv, 8, GEN_FOREVER)) seq_printf(m, "GAMTARBMODE = 0x%08x\n", I915_READ(GAMTARBMODE)); else @@ -2156,9 +2156,9 @@ static int i915_ppgtt_info(struct seq_file *m, void *data) intel_runtime_pm_get(dev_priv); - if (INTEL_GEN(dev_priv) >= 8) + if (GT_GEN_RANGE(dev_priv, 8, GEN_FOREVER)) gen8_ppgtt_info(m, dev_priv); - else if (INTEL_GEN(dev_priv) >= 6) + else if (GT_GEN_RANGE(dev_priv, 6, GEN_FOREVER)) gen6_ppgtt_info(m, dev_priv); list_for_each_entry_reverse(file, &dev->filelist, lhead) { @@ -2269,7 +2269,7 @@ static int i915_rps_boost_info(struct seq_file *m, void *data) atomic_read(&rps->boosts)); mutex_unlock(&dev->filelist_mutex); - if (INTEL_GEN(dev_priv) >= 6 && + if (GT_GEN_RANGE(dev_priv, 6, GEN_FOREVER) && rps->enabled && dev_priv->gt.active_requests) { u32 rpup, rpupei; @@ -2300,7 +2300,8 @@ static int i915_rps_boost_info(struct seq_file *m, void *data) static int i915_llc(struct seq_file *m, void *data) { struct drm_i915_private *dev_priv = node_to_i915(m->private); - const bool edram = INTEL_GEN(dev_priv) > 8; + const bool edram = GT_GEN_RANGE(dev_priv, 9, + GEN_FOREVER); seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev_priv))); seq_printf(m, "%s: %lluMB\n", edram ? "eDRAM" : "eLLC", @@ -2821,7 +2822,7 @@ static int i915_energy_uJ(struct seq_file *m, void *data) unsigned long long power; u32 units; - if (INTEL_GEN(dev_priv) < 6) + if (GT_GEN_RANGE(dev_priv, 0, 5)) return -ENODEV; intel_runtime_pm_get(dev_priv); @@ -2916,7 +2917,7 @@ static int i915_dmc_info(struct seq_file *m, void *unused) seq_printf(m, "version: %d.%d\n", CSR_VERSION_MAJOR(csr->version), CSR_VERSION_MINOR(csr->version)); - if (WARN_ON(INTEL_GEN(dev_priv) > 11)) + if (WARN_ON(GT_GEN_RANGE(dev_priv, 12, GEN_FOREVER))) goto out; seq_printf(m, "DC3 -> DC5 count: %d\n", @@ -3442,7 +3443,7 @@ static int i915_ddb_info(struct seq_file *m, void *unused) enum pipe pipe; int plane; - if (INTEL_GEN(dev_priv) < 9) + if (GT_GEN_RANGE(dev_priv, 0, 8)) return -ENODEV; drm_modeset_lock_all(dev); @@ -3811,7 +3812,7 @@ static void wm_latency_show(struct seq_file *m, const uint16_t wm[8]) * - WM1+ latency values in 0.5us units * - latencies are in us on gen9/vlv/chv */ - if (INTEL_GEN(dev_priv) >= 9 || + if (GT_GEN_RANGE(dev_priv, 9, GEN_FOREVER) || IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv) || IS_G4X(dev_priv)) @@ -3831,7 +3832,7 @@ static int pri_wm_latency_show(struct seq_file *m, void *data) struct drm_i915_private *dev_priv = m->private; const uint16_t *latencies; - if (INTEL_GEN(dev_priv) >= 9) + if (GT_GEN_RANGE(dev_priv, 9, GEN_FOREVER)) latencies = dev_priv->wm.skl_latency; else latencies = dev_priv->wm.pri_latency; @@ -3846,7 +3847,7 @@ static int spr_wm_latency_show(struct seq_file *m, void *data) struct drm_i915_private *dev_priv = m->private; const uint16_t *latencies; - if (INTEL_GEN(dev_priv) >= 9) + if (GT_GEN_RANGE(dev_priv, 9, GEN_FOREVER)) latencies = dev_priv->wm.skl_latency; else latencies = dev_priv->wm.spr_latency; @@ -3861,7 +3862,7 @@ static int cur_wm_latency_show(struct seq_file *m, void *data) struct drm_i915_private *dev_priv = m->private; const uint16_t *latencies; - if (INTEL_GEN(dev_priv) >= 9) + if (GT_GEN_RANGE(dev_priv, 9, GEN_FOREVER)) latencies = dev_priv->wm.skl_latency; else latencies = dev_priv->wm.cur_latency; @@ -3875,7 +3876,7 @@ static int pri_wm_latency_open(struct inode *inode, struct file *file) { struct drm_i915_private *dev_priv = inode->i_private; - if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv)) + if (GT_GEN_RANGE(dev_priv, 0, 4) && !IS_G4X(dev_priv)) return -ENODEV; return single_open(file, pri_wm_latency_show, dev_priv); @@ -3954,7 +3955,7 @@ static ssize_t pri_wm_latency_write(struct file *file, const char __user *ubuf, struct drm_i915_private *dev_priv = m->private; uint16_t *latencies; - if (INTEL_GEN(dev_priv) >= 9) + if (GT_GEN_RANGE(dev_priv, 9, GEN_FOREVER)) latencies = dev_priv->wm.skl_latency; else latencies = dev_priv->wm.pri_latency; @@ -3969,7 +3970,7 @@ static ssize_t spr_wm_latency_write(struct file *file, const char __user *ubuf, struct drm_i915_private *dev_priv = m->private; uint16_t *latencies; - if (INTEL_GEN(dev_priv) >= 9) + if (GT_GEN_RANGE(dev_priv, 9, GEN_FOREVER)) latencies = dev_priv->wm.skl_latency; else latencies = dev_priv->wm.spr_latency; @@ -3984,7 +3985,7 @@ static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf, struct drm_i915_private *dev_priv = m->private; uint16_t *latencies; - if (INTEL_GEN(dev_priv) >= 9) + if (GT_GEN_RANGE(dev_priv, 9, GEN_FOREVER)) latencies = dev_priv->wm.skl_latency; else latencies = dev_priv->wm.cur_latency; @@ -4141,7 +4142,7 @@ i915_ring_test_irq_set(void *data, u64 val) * From icl, we can no longer individually mask interrupt generation * from each engine. */ - if (INTEL_GEN(i915) >= 11) + if (GT_GEN_RANGE(i915, 11, GEN_FOREVER)) return -ENODEV; val &= INTEL_INFO(i915)->ring_mask; @@ -4519,7 +4520,7 @@ static int i915_sseu_status(struct seq_file *m, void *unused) struct drm_i915_private *dev_priv = node_to_i915(m->private); struct sseu_dev_info sseu; - if (INTEL_GEN(dev_priv) < 8) + if (GT_GEN_RANGE(dev_priv, 0, 7)) return -ENODEV; seq_puts(m, "SSEU Device Info\n"); @@ -4540,7 +4541,7 @@ static int i915_sseu_status(struct seq_file *m, void *unused) broadwell_sseu_device_status(dev_priv, &sseu); } else if (GT_GEN(dev_priv, 9)) { gen9_sseu_device_status(dev_priv, &sseu); - } else if (INTEL_GEN(dev_priv) >= 10) { + } else if (GT_GEN_RANGE(dev_priv, 10, GEN_FOREVER)) { gen10_sseu_device_status(dev_priv, &sseu); } @@ -4555,7 +4556,7 @@ static int i915_forcewake_open(struct inode *inode, struct file *file) { struct drm_i915_private *i915 = inode->i_private; - if (INTEL_GEN(i915) < 6) + if (GT_GEN_RANGE(i915, 0, 5)) return 0; intel_runtime_pm_get(i915); @@ -4568,7 +4569,7 @@ static int i915_forcewake_release(struct inode *inode, struct file *file) { struct drm_i915_private *i915 = inode->i_private; - if (INTEL_GEN(i915) < 6) + if (GT_GEN_RANGE(i915, 0, 5)) return 0; intel_uncore_forcewake_user_put(i915); @@ -4664,7 +4665,7 @@ static int i915_drrs_ctl_set(void *data, u64 val) struct drm_device *dev = &dev_priv->drm; struct intel_crtc *crtc; - if (INTEL_GEN(dev_priv) < 7) + if (GT_GEN_RANGE(dev_priv, 0, 6)) return -ENODEV; for_each_intel_crtc(dev, crtc) { diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index 8ff2acdec1f5..226030c0787f 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -472,12 +472,12 @@ static int i915_get_bridge_dev(struct drm_i915_private *dev_priv) static int intel_alloc_mchbar_resource(struct drm_i915_private *dev_priv) { - int reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915; + int reg = GT_GEN_RANGE(dev_priv, 4, GEN_FOREVER) ? MCHBAR_I965 : MCHBAR_I915; u32 temp_lo, temp_hi = 0; u64 mchbar_addr; int ret; - if (INTEL_GEN(dev_priv) >= 4) + if (GT_GEN_RANGE(dev_priv, 4, GEN_FOREVER)) pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi); pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo); mchbar_addr = ((u64)temp_hi << 32) | temp_lo; @@ -504,7 +504,7 @@ intel_alloc_mchbar_resource(struct drm_i915_private *dev_priv) return ret; } - if (INTEL_GEN(dev_priv) >= 4) + if (GT_GEN_RANGE(dev_priv, 4, GEN_FOREVER)) pci_write_config_dword(dev_priv->bridge_dev, reg + 4, upper_32_bits(dev_priv->mch_res.start)); @@ -517,7 +517,7 @@ intel_alloc_mchbar_resource(struct drm_i915_private *dev_priv) static void intel_setup_mchbar(struct drm_i915_private *dev_priv) { - int mchbar_reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915; + int mchbar_reg = GT_GEN_RANGE(dev_priv, 4, GEN_FOREVER) ? MCHBAR_I965 : MCHBAR_I915; u32 temp; bool enabled; @@ -556,7 +556,7 @@ intel_setup_mchbar(struct drm_i915_private *dev_priv) static void intel_teardown_mchbar(struct drm_i915_private *dev_priv) { - int mchbar_reg = INTEL_GEN(dev_priv) >= 4 ? MCHBAR_I965 : MCHBAR_I915; + int mchbar_reg = GT_GEN_RANGE(dev_priv, 4, GEN_FOREVER) ? MCHBAR_I965 : MCHBAR_I915; if (dev_priv->mchbar_need_disable) { if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) { @@ -964,7 +964,7 @@ static int i915_mmio_setup(struct drm_i915_private *dev_priv) * the register BAR remains the same size for all the earlier * generations up to Ironlake. */ - if (INTEL_GEN(dev_priv) < 5) + if (GT_GEN_RANGE(dev_priv, 0, 4)) mmio_size = 512 * 1024; else mmio_size = 2 * 1024 * 1024; @@ -1324,7 +1324,7 @@ intel_get_dram_info(struct drm_i915_private *dev_priv) */ dram_info->is_16gb_dimm = !GT_GEN9_LP(dev_priv); - if (INTEL_GEN(dev_priv) < 9 || IS_GEMINILAKE(dev_priv)) + if (GT_GEN_RANGE(dev_priv, 0, 8) || IS_GEMINILAKE(dev_priv)) return; /* Need to calculate bandwidth only for Gen9 */ @@ -1464,7 +1464,7 @@ static int i915_driver_init_hw(struct drm_i915_private *dev_priv) * device. The kernel then disables that interrupt source and so * prevents the other device from working properly. */ - if (INTEL_GEN(dev_priv) >= 5) { + if (GT_GEN_RANGE(dev_priv, 5, GEN_FOREVER)) { if (pci_enable_msi(pdev) < 0) DRM_DEBUG_DRIVER("can't enable MSI"); } @@ -1962,7 +1962,7 @@ static int i915_drm_suspend_late(struct drm_device *dev, bool hibernation) get_suspend_mode(dev_priv, hibernation)); ret = 0; - if (INTEL_GEN(dev_priv) >= 11 || GT_GEN9_LP(dev_priv)) + if (GT_GEN_RANGE(dev_priv, 11, GEN_FOREVER) || GT_GEN9_LP(dev_priv)) bxt_enable_dc9(dev_priv); else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) hsw_enable_pc8(dev_priv); @@ -1989,7 +1989,7 @@ static int i915_drm_suspend_late(struct drm_device *dev, bool hibernation) * Fujitsu FSC S7110 * Acer Aspire 1830T */ - if (!(hibernation && INTEL_GEN(dev_priv) < 6)) + if (!(hibernation && GT_GEN_RANGE(dev_priv, 0, 5))) pci_set_power_state(pdev, PCI_D3hot); out: @@ -2152,7 +2152,7 @@ static int i915_drm_resume_early(struct drm_device *dev) intel_uncore_resume_early(dev_priv); - if (INTEL_GEN(dev_priv) >= 11 || GT_GEN9_LP(dev_priv)) { + if (GT_GEN_RANGE(dev_priv, 11, GEN_FOREVER) || GT_GEN9_LP(dev_priv)) { gen9_sanitize_dc_state(dev_priv); bxt_disable_dc9(dev_priv); } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { @@ -2919,7 +2919,7 @@ static int intel_runtime_suspend(struct device *kdev) intel_uncore_suspend(dev_priv); ret = 0; - if (INTEL_GEN(dev_priv) >= 11) { + if (GT_GEN_RANGE(dev_priv, 11, GEN_FOREVER)) { icl_display_core_uninit(dev_priv); bxt_enable_dc9(dev_priv); } else if (GT_GEN9_LP(dev_priv)) { @@ -3007,7 +3007,7 @@ static int intel_runtime_resume(struct device *kdev) if (intel_uncore_unclaimed_mmio(dev_priv)) DRM_DEBUG_DRIVER("Unclaimed access during suspend, bios?\n"); - if (INTEL_GEN(dev_priv) >= 11) { + if (GT_GEN_RANGE(dev_priv, 11, GEN_FOREVER)) { bxt_disable_dc9(dev_priv); icl_display_core_init(dev_priv, true); if (dev_priv->csr.dmc_payload) { diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 08c879f17b40..4440ac225441 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -2600,8 +2600,8 @@ intel_info(const struct drm_i915_private *dev_priv) (IS_CANNONLAKE(dev_priv) || \ IS_SKL_GT3(dev_priv) || IS_SKL_GT4(dev_priv)) -#define HAS_GMBUS_IRQ(dev_priv) (INTEL_GEN(dev_priv) >= 4) -#define HAS_GMBUS_BURST_READ(dev_priv) (INTEL_GEN(dev_priv) >= 10 || \ +#define HAS_GMBUS_IRQ(dev_priv) (GT_GEN_RANGE(dev_priv, 4, GEN_FOREVER)) +#define HAS_GMBUS_BURST_READ(dev_priv) (GT_GEN_RANGE(dev_priv, 10, GEN_FOREVER) || \ IS_GEMINILAKE(dev_priv) || \ IS_KABYLAKE(dev_priv)) @@ -2614,9 +2614,9 @@ intel_info(const struct drm_i915_private *dev_priv) #define SUPPORTS_TV(dev_priv) ((dev_priv)->info.supports_tv) #define I915_HAS_HOTPLUG(dev_priv) ((dev_priv)->info.has_hotplug) -#define HAS_FW_BLC(dev_priv) (INTEL_GEN(dev_priv) > 2) +#define HAS_FW_BLC(dev_priv) (GT_GEN_RANGE(dev_priv, 3, GEN_FOREVER)) #define HAS_FBC(dev_priv) ((dev_priv)->info.has_fbc) -#define HAS_CUR_FBC(dev_priv) (!HAS_GMCH_DISPLAY(dev_priv) && INTEL_GEN(dev_priv) >= 7) +#define HAS_CUR_FBC(dev_priv) (!HAS_GMCH_DISPLAY(dev_priv) && GT_GEN_RANGE(dev_priv, 7, GEN_FOREVER)) #define HAS_IPS(dev_priv) (IS_HSW_ULT(dev_priv) || IS_BROADWELL(dev_priv)) @@ -2698,7 +2698,7 @@ intel_info(const struct drm_i915_private *dev_priv) #define HAS_GMCH_DISPLAY(dev_priv) ((dev_priv)->info.has_gmch_display) -#define HAS_LSPCON(dev_priv) (INTEL_GEN(dev_priv) >= 9) +#define HAS_LSPCON(dev_priv) (GT_GEN_RANGE(dev_priv, 9, GEN_FOREVER)) /* DPF == dynamic parity feature */ #define HAS_L3_DPF(dev_priv) ((dev_priv)->info.has_l3_dpf) @@ -2721,7 +2721,7 @@ static inline bool intel_vtd_active(void) static inline bool intel_scanout_needs_vtd_wa(struct drm_i915_private *dev_priv) { - return INTEL_GEN(dev_priv) >= 6 && intel_vtd_active(); + return GT_GEN_RANGE(dev_priv, 6, GEN_FOREVER) && intel_vtd_active(); } static inline bool @@ -3309,7 +3309,7 @@ void i915_gem_flush_ggtt_writes(struct drm_i915_private *dev_priv); static inline void i915_gem_chipset_flush(struct drm_i915_private *dev_priv) { wmb(); - if (INTEL_GEN(dev_priv) < 6) + if (GT_GEN_RANGE(dev_priv, 0, 5)) intel_gtt_chipset_flush(); } @@ -3688,7 +3688,7 @@ static inline i915_reg_t i915_vgacntrl_reg(struct drm_i915_private *dev_priv) { if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) return VLV_VGACNTRL; - else if (INTEL_GEN(dev_priv) >= 5) + else if (GT_GEN_RANGE(dev_priv, 5, GEN_FOREVER)) return CPU_VGACNTRL; else return VGACNTRL; @@ -3848,7 +3848,7 @@ int remap_io_mapping(struct vm_area_struct *vma, static inline int intel_hws_csb_write_index(struct drm_i915_private *i915) { - if (INTEL_GEN(i915) >= 10) + if (GT_GEN_RANGE(i915, 10, GEN_FOREVER)) return CNL_HWS_CSB_WRITE_INDEX; else return I915_HWS_CSB_WRITE_INDEX; diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index d50955f7fe3f..fef3e4f58c74 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -171,7 +171,7 @@ static u32 __i915_gem_park(struct drm_i915_private *i915) i915->gt.awake = false; - if (INTEL_GEN(i915) >= 6) + if (GT_GEN_RANGE(i915, 6, GEN_FOREVER)) gen6_rps_idle(i915); intel_display_power_put(i915, POWER_DOMAIN_GT_IRQ); @@ -226,7 +226,7 @@ void i915_gem_unpark(struct drm_i915_private *i915) intel_enable_gt_powersave(i915); i915_update_gfx_val(i915); - if (INTEL_GEN(i915) >= 6) + if (GT_GEN_RANGE(i915, 6, GEN_FOREVER)) gen6_rps_busy(i915); i915_pmu_gt_unparked(i915); @@ -489,7 +489,7 @@ i915_gem_object_wait_fence(struct dma_fence *fence, * each client to waitboost once in a busy period. */ if (rps_client && !i915_request_started(rq)) { - if (INTEL_GEN(rq->i915) >= 6) + if (GT_GEN_RANGE(rq->i915, 6, GEN_FOREVER)) gen6_rps_boost(rq, rps_client); } @@ -3338,7 +3338,7 @@ void i915_gem_set_wedged(struct drm_i915_private *i915) i915->caps.scheduler = 0; /* Even if the GPU reset fails, it should still stop the engines */ - if (INTEL_GEN(i915) >= 5) + if (GT_GEN_RANGE(i915, 5, GEN_FOREVER)) intel_gpu_reset(i915, ALL_ENGINES); /* @@ -5054,7 +5054,7 @@ void i915_gem_sanitize(struct drm_i915_private *i915) * of the reset, so this could be applied to even earlier gen. */ err = -ENODEV; - if (INTEL_GEN(i915) >= 5 && intel_has_gpu_reset(i915)) + if (GT_GEN_RANGE(i915, 5, GEN_FOREVER) && intel_has_gpu_reset(i915)) err = WARN_ON(intel_gpu_reset(i915, ALL_ENGINES)); if (!err) intel_engines_sanitize(i915); @@ -5216,7 +5216,7 @@ void i915_gem_resume(struct drm_i915_private *i915) void i915_gem_init_swizzling(struct drm_i915_private *dev_priv) { - if (INTEL_GEN(dev_priv) < 5 || + if (GT_GEN_RANGE(dev_priv, 0, 4) || dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE) return; @@ -5290,7 +5290,7 @@ int i915_gem_init_hw(struct drm_i915_private *dev_priv) /* Double layer security blanket, see i915_gem_init() */ intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); - if (HAS_EDRAM(dev_priv) && INTEL_GEN(dev_priv) < 9) + if (HAS_EDRAM(dev_priv) && GT_GEN_RANGE(dev_priv, 0, 8)) I915_WRITE(HSW_IDICR, I915_READ(HSW_IDICR) | IDIHASHMSK(0xf)); if (IS_HASWELL(dev_priv)) @@ -5699,10 +5699,10 @@ i915_gem_load_init_fences(struct drm_i915_private *dev_priv) { int i; - if (INTEL_GEN(dev_priv) >= 7 && !IS_VALLEYVIEW(dev_priv) && + if (GT_GEN_RANGE(dev_priv, 7, GEN_FOREVER) && !IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) dev_priv->num_fence_regs = 32; - else if (INTEL_GEN(dev_priv) >= 4 || + else if (GT_GEN_RANGE(dev_priv, 4, GEN_FOREVER) || IS_I945G(dev_priv) || IS_I945GM(dev_priv) || IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) dev_priv->num_fence_regs = 16; diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c index 031a2a358f19..09cc74420409 100644 --- a/drivers/gpu/drm/i915/i915_gem_context.c +++ b/drivers/gpu/drm/i915/i915_gem_context.c @@ -121,7 +121,7 @@ static inline int new_hw_id(struct drm_i915_private *i915, gfp_t gfp) lockdep_assert_held(&i915->contexts.mutex); - if (INTEL_GEN(i915) >= 11) + if (GT_GEN_RANGE(i915, 11, GEN_FOREVER)) max = GEN11_MAX_CONTEXT_HW_ID; else if (USES_GUC_SUBMISSION(i915)) /* diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c index f1df4114305a..9b936e5877fe 100644 --- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c +++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c @@ -2518,7 +2518,7 @@ i915_gem_execbuffer_ioctl(struct drm_device *dev, void *data, exec2_list[i].relocs_ptr = exec_list[i].relocs_ptr; exec2_list[i].alignment = exec_list[i].alignment; exec2_list[i].offset = exec_list[i].offset; - if (INTEL_GEN(to_i915(dev)) < 4) + if (GT_GEN_RANGE(to_i915(dev), 0, 3)) exec2_list[i].flags = EXEC_OBJECT_NEEDS_FENCE; else exec2_list[i].flags = 0; diff --git a/drivers/gpu/drm/i915/i915_gem_fence_reg.c b/drivers/gpu/drm/i915/i915_gem_fence_reg.c index caafbf7e62a4..3f45b94d9cc0 100644 --- a/drivers/gpu/drm/i915/i915_gem_fence_reg.c +++ b/drivers/gpu/drm/i915/i915_gem_fence_reg.c @@ -64,7 +64,7 @@ static void i965_write_fence_reg(struct drm_i915_fence_reg *fence, int fence_pitch_shift; u64 val; - if (INTEL_GEN(fence->i915) >= 6) { + if (GT_GEN_RANGE(fence->i915, 6, GEN_FOREVER)) { fence_reg_lo = FENCE_REG_GEN6_LO(fence->id); fence_reg_hi = FENCE_REG_GEN6_HI(fence->id); fence_pitch_shift = GEN6_FENCE_PITCH_SHIFT; @@ -557,7 +557,7 @@ i915_gem_detect_bit_6_swizzle(struct drm_i915_private *dev_priv) uint32_t swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN; uint32_t swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN; - if (INTEL_GEN(dev_priv) >= 8 || IS_VALLEYVIEW(dev_priv)) { + if (GT_GEN_RANGE(dev_priv, 8, GEN_FOREVER) || IS_VALLEYVIEW(dev_priv)) { /* * On BDW+, swizzling is not used. We leave the CPU memory * controller in charge of optimizing memory accesses without @@ -567,7 +567,7 @@ i915_gem_detect_bit_6_swizzle(struct drm_i915_private *dev_priv) */ swizzle_x = I915_BIT_6_SWIZZLE_NONE; swizzle_y = I915_BIT_6_SWIZZLE_NONE; - } else if (INTEL_GEN(dev_priv) >= 6) { + } else if (GT_GEN_RANGE(dev_priv, 6, GEN_FOREVER)) { if (dev_priv->preserve_bios_swizzle) { if (I915_READ(DISP_ARB_CTL) & DISP_TILE_SURFACE_SWIZZLING) { diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c index 4ae6166c6593..95001f074e72 100644 --- a/drivers/gpu/drm/i915/i915_gem_gtt.c +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c @@ -2170,7 +2170,7 @@ static void gtt_write_workarounds(struct drm_i915_private *dev_priv) I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_CHV); else if (GT_GEN9_LP(dev_priv)) I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_BXT); - else if (INTEL_GEN(dev_priv) >= 9) + else if (GT_GEN_RANGE(dev_priv, 9, GEN_FOREVER)) I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_SKL); /* @@ -2185,7 +2185,7 @@ static void gtt_write_workarounds(struct drm_i915_private *dev_priv) * driver. */ if (HAS_PAGE_SIZES(dev_priv, I915_GTT_PAGE_SIZE_64K) && - INTEL_GEN(dev_priv) <= 10) + GT_GEN_RANGE(dev_priv, 0, 10)) I915_WRITE(GEN8_GAMW_ECO_DEV_RW_IA, I915_READ(GEN8_GAMW_ECO_DEV_RW_IA) | GAMW_ECO_ENABLE_64K_IPS_FIELD); @@ -2206,7 +2206,7 @@ int i915_ppgtt_init_hw(struct drm_i915_private *dev_priv) static struct i915_hw_ppgtt * __hw_ppgtt_create(struct drm_i915_private *i915) { - if (INTEL_GEN(i915) < 8) + if (GT_GEN_RANGE(i915, 0, 7)) return gen6_ppgtt_create(i915); else return gen8_ppgtt_create(i915); @@ -2335,9 +2335,9 @@ static void gen8_check_faults(struct drm_i915_private *dev_priv) void i915_check_and_clear_faults(struct drm_i915_private *dev_priv) { /* From GEN8 onwards we only have one 'All Engine Fault Register' */ - if (INTEL_GEN(dev_priv) >= 8) + if (GT_GEN_RANGE(dev_priv, 8, GEN_FOREVER)) gen8_check_faults(dev_priv); - else if (INTEL_GEN(dev_priv) >= 6) + else if (GT_GEN_RANGE(dev_priv, 6, GEN_FOREVER)) gen6_check_faults(dev_priv); else return; @@ -2352,7 +2352,7 @@ void i915_gem_suspend_gtt_mappings(struct drm_i915_private *dev_priv) /* Don't bother messing with faults pre GEN6 as we have little * documentation supporting that it's a good idea. */ - if (INTEL_GEN(dev_priv) < 6) + if (GT_GEN_RANGE(dev_priv, 0, 5)) return; i915_check_and_clear_faults(dev_priv); @@ -3002,7 +3002,7 @@ static int ggtt_probe_common(struct i915_ggtt *ggtt, u64 size) * resort to an uncached mapping. The WC issue is easily caught by the * readback check when writing GTT PTE entries. */ - if (GT_GEN9_LP(dev_priv) || INTEL_GEN(dev_priv) >= 10) + if (GT_GEN9_LP(dev_priv) || GT_GEN_RANGE(dev_priv, 10, GEN_FOREVER)) ggtt->gsm = ioremap_nocache(phys_addr, size); else ggtt->gsm = ioremap_wc(phys_addr, size); @@ -3301,7 +3301,7 @@ static void setup_private_pat(struct drm_i915_private *dev_priv) ppat->i915 = dev_priv; - if (INTEL_GEN(dev_priv) >= 10) + if (GT_GEN_RANGE(dev_priv, 10, GEN_FOREVER)) cnl_setup_private_ppat(ppat); else if (IS_CHERRYVIEW(dev_priv) || GT_GEN9_LP(dev_priv)) chv_setup_private_ppat(ppat); @@ -3420,7 +3420,7 @@ static int gen6_gmch_probe(struct i915_ggtt *ggtt) ggtt->vm.pte_encode = hsw_pte_encode; else if (IS_VALLEYVIEW(dev_priv)) ggtt->vm.pte_encode = byt_pte_encode; - else if (INTEL_GEN(dev_priv) >= 7) + else if (GT_GEN_RANGE(dev_priv, 7, GEN_FOREVER)) ggtt->vm.pte_encode = ivb_pte_encode; else ggtt->vm.pte_encode = snb_pte_encode; @@ -3487,9 +3487,9 @@ int i915_ggtt_probe_hw(struct drm_i915_private *dev_priv) ggtt->vm.i915 = dev_priv; ggtt->vm.dma = &dev_priv->drm.pdev->dev; - if (INTEL_GEN(dev_priv) <= 5) + if (GT_GEN_RANGE(dev_priv, 0, 5)) ret = i915_gmch_probe(ggtt); - else if (INTEL_GEN(dev_priv) < 8) + else if (GT_GEN_RANGE(dev_priv, 0, 7)) ret = gen6_gmch_probe(ggtt); else ret = gen8_gmch_probe(ggtt); @@ -3588,7 +3588,7 @@ int i915_ggtt_init_hw(struct drm_i915_private *dev_priv) int i915_ggtt_enable_hw(struct drm_i915_private *dev_priv) { - if (INTEL_GEN(dev_priv) < 6 && !intel_enable_gtt()) + if (GT_GEN_RANGE(dev_priv, 0, 5) && !intel_enable_gtt()) return -EIO; return 0; @@ -3650,7 +3650,7 @@ void i915_gem_restore_gtt_mappings(struct drm_i915_private *dev_priv) ggtt->vm.closed = false; i915_ggtt_invalidate(dev_priv); - if (INTEL_GEN(dev_priv) >= 8) { + if (GT_GEN_RANGE(dev_priv, 8, GEN_FOREVER)) { struct intel_ppat *ppat = &dev_priv->ppat; bitmap_set(ppat->dirty, 0, ppat->max_entries); diff --git a/drivers/gpu/drm/i915/i915_gem_stolen.c b/drivers/gpu/drm/i915/i915_gem_stolen.c index d01dea84ffae..b346b874a82f 100644 --- a/drivers/gpu/drm/i915/i915_gem_stolen.c +++ b/drivers/gpu/drm/i915/i915_gem_stolen.c @@ -52,7 +52,7 @@ int i915_gem_stolen_insert_node_in_range(struct drm_i915_private *dev_priv, return -ENODEV; /* WaSkipStolenMemoryFirstPage:bdw+ */ - if (INTEL_GEN(dev_priv) >= 8 && start < 4096) + if (GT_GEN_RANGE(dev_priv, 8, GEN_FOREVER) && start < 4096) start = 4096; mutex_lock(&dev_priv->mm.stolen_lock); @@ -95,7 +95,7 @@ static int i915_adjust_stolen(struct drm_i915_private *dev_priv, */ /* Make sure we don't clobber the GTT if it's within stolen memory */ - if (INTEL_GEN(dev_priv) <= 4 && + if (GT_GEN_RANGE(dev_priv, 0, 4) && !IS_G33(dev_priv) && !IS_PINEVIEW(dev_priv) && !IS_G4X(dev_priv)) { struct resource stolen[2] = {*dsm, *dsm}; struct resource ggtt_res; @@ -384,7 +384,7 @@ int i915_gem_init_stolen(struct drm_i915_private *dev_priv) return 0; } - if (intel_vtd_active() && INTEL_GEN(dev_priv) < 8) { + if (intel_vtd_active() && GT_GEN_RANGE(dev_priv, 0, 7)) { DRM_INFO("DMAR active, disabling use of stolen memory\n"); return 0; } diff --git a/drivers/gpu/drm/i915/i915_gem_tiling.c b/drivers/gpu/drm/i915/i915_gem_tiling.c index 8a1976c523b0..430d4da67d8a 100644 --- a/drivers/gpu/drm/i915/i915_gem_tiling.c +++ b/drivers/gpu/drm/i915/i915_gem_tiling.c @@ -80,7 +80,7 @@ u32 i915_gem_fence_size(struct drm_i915_private *i915, GEM_BUG_ON(!stride); - if (INTEL_GEN(i915) >= 4) { + if (GT_GEN_RANGE(i915, 4, GEN_FOREVER)) { stride *= i915_gem_tile_height(tiling); GEM_BUG_ON(!IS_ALIGNED(stride, I965_FENCE_PAGE)); return roundup(size, stride); @@ -120,7 +120,7 @@ u32 i915_gem_fence_alignment(struct drm_i915_private *i915, u32 size, if (tiling == I915_TILING_NONE) return I915_GTT_MIN_ALIGNMENT; - if (INTEL_GEN(i915) >= 4) + if (GT_GEN_RANGE(i915, 4, GEN_FOREVER)) return I965_FENCE_PAGE; /* @@ -148,10 +148,10 @@ i915_tiling_ok(struct drm_i915_gem_object *obj, /* check maximum stride & object size */ /* i965+ stores the end address of the gtt mapping in the fence * reg, so dont bother to check the size */ - if (INTEL_GEN(i915) >= 7) { + if (GT_GEN_RANGE(i915, 7, GEN_FOREVER)) { if (stride / 128 > GEN7_FENCE_MAX_PITCH_VAL) return false; - } else if (INTEL_GEN(i915) >= 4) { + } else if (GT_GEN_RANGE(i915, 4, GEN_FOREVER)) { if (stride / 128 > I965_FENCE_MAX_PITCH_VAL) return false; } else { diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c index c7b492b6cf4e..0de8ce65053d 100644 --- a/drivers/gpu/drm/i915/i915_gpu_error.c +++ b/drivers/gpu/drm/i915/i915_gpu_error.c @@ -411,13 +411,13 @@ static void error_print_instdone(struct drm_i915_error_state_buf *m, err_printf(m, " INSTDONE: 0x%08x\n", ee->instdone.instdone); - if (ee->engine_id != RCS || INTEL_GEN(m->i915) <= 3) + if (ee->engine_id != RCS || GT_GEN_RANGE(m->i915, 0, 3)) return; err_printf(m, " SC_INSTDONE: 0x%08x\n", ee->instdone.slice_common); - if (INTEL_GEN(m->i915) <= 6) + if (GT_GEN_RANGE(m->i915, 0, 6)) return; for_each_instdone_slice_subslice(m->i915, slice, subslice) @@ -492,7 +492,7 @@ static void error_print_engine(struct drm_i915_error_state_buf *m, upper_32_bits(start), lower_32_bits(start), upper_32_bits(end), lower_32_bits(end)); } - if (INTEL_GEN(m->i915) >= 4) { + if (GT_GEN_RANGE(m->i915, 4, GEN_FOREVER)) { err_printf(m, " BBADDR: 0x%08x_%08x\n", (u32)(ee->bbaddr>>32), (u32)ee->bbaddr); err_printf(m, " BB_STATE: 0x%08x\n", ee->bbstate); @@ -501,7 +501,7 @@ static void error_print_engine(struct drm_i915_error_state_buf *m, err_printf(m, " INSTPM: 0x%08x\n", ee->instpm); err_printf(m, " FADDR: 0x%08x %08x\n", upper_32_bits(ee->faddr), lower_32_bits(ee->faddr)); - if (INTEL_GEN(m->i915) >= 6) { + if (GT_GEN_RANGE(m->i915, 6, GEN_FOREVER)) { err_printf(m, " RC PSMI: 0x%08x\n", ee->rc_psmi); err_printf(m, " FAULT_REG: 0x%08x\n", ee->fault_reg); err_printf(m, " SYNC_0: 0x%08x\n", @@ -515,7 +515,7 @@ static void error_print_engine(struct drm_i915_error_state_buf *m, if (HAS_PPGTT(m->i915)) { err_printf(m, " GFX_MODE: 0x%08x\n", ee->vm_info.gfx_mode); - if (INTEL_GEN(m->i915) >= 8) { + if (GT_GEN_RANGE(m->i915, 8, GEN_FOREVER)) { int i; for (i = 0; i < 4; i++) err_printf(m, " PDP%d: 0x%016llx\n", @@ -710,10 +710,10 @@ int i915_error_state_to_str(struct drm_i915_error_state_buf *m, for (i = 0; i < error->nfence; i++) err_printf(m, " fence[%d] = %08llx\n", i, error->fence[i]); - if (INTEL_GEN(dev_priv) >= 6) { + if (GT_GEN_RANGE(dev_priv, 6, GEN_FOREVER)) { err_printf(m, "ERROR: 0x%08x\n", error->error); - if (INTEL_GEN(dev_priv) >= 8) + if (GT_GEN_RANGE(dev_priv, 8, GEN_FOREVER)) err_printf(m, "FAULT_TLB_DATA: 0x%08x 0x%08x\n", error->fault_data1, error->fault_data0); @@ -1106,10 +1106,10 @@ static void gem_record_fences(struct i915_gpu_state *error) struct drm_i915_private *dev_priv = error->i915; int i; - if (INTEL_GEN(dev_priv) >= 6) { + if (GT_GEN_RANGE(dev_priv, 6, GEN_FOREVER)) { for (i = 0; i < dev_priv->num_fence_regs; i++) error->fence[i] = I915_READ64(FENCE_REG_GEN6_LO(i)); - } else if (INTEL_GEN(dev_priv) >= 4) { + } else if (GT_GEN_RANGE(dev_priv, 4, GEN_FOREVER)) { for (i = 0; i < dev_priv->num_fence_regs; i++) error->fence[i] = I915_READ64(FENCE_REG_965_LO(i)); } else { @@ -1190,9 +1190,9 @@ static void error_record_engine_registers(struct i915_gpu_state *error, { struct drm_i915_private *dev_priv = engine->i915; - if (INTEL_GEN(dev_priv) >= 6) { + if (GT_GEN_RANGE(dev_priv, 6, GEN_FOREVER)) { ee->rc_psmi = I915_READ(RING_PSMI_CTL(engine->mmio_base)); - if (INTEL_GEN(dev_priv) >= 8) { + if (GT_GEN_RANGE(dev_priv, 8, GEN_FOREVER)) { ee->fault_reg = I915_READ(GEN8_RING_FAULT_REG); } else { gen6_record_semaphore_state(engine, ee); @@ -1200,13 +1200,13 @@ static void error_record_engine_registers(struct i915_gpu_state *error, } } - if (INTEL_GEN(dev_priv) >= 4) { + if (GT_GEN_RANGE(dev_priv, 4, GEN_FOREVER)) { ee->faddr = I915_READ(RING_DMA_FADD(engine->mmio_base)); ee->ipeir = I915_READ(RING_IPEIR(engine->mmio_base)); ee->ipehr = I915_READ(RING_IPEHR(engine->mmio_base)); ee->instps = I915_READ(RING_INSTPS(engine->mmio_base)); ee->bbaddr = I915_READ(RING_BBADDR(engine->mmio_base)); - if (INTEL_GEN(dev_priv) >= 8) { + if (GT_GEN_RANGE(dev_priv, 8, GEN_FOREVER)) { ee->faddr |= (u64) I915_READ(RING_DMA_FADD_UDW(engine->mmio_base)) << 32; ee->bbaddr |= (u64) I915_READ(RING_BBADDR_UDW(engine->mmio_base)) << 32; } @@ -1228,7 +1228,7 @@ static void error_record_engine_registers(struct i915_gpu_state *error, ee->head = I915_READ_HEAD(engine); ee->tail = I915_READ_TAIL(engine); ee->ctl = I915_READ_CTL(engine); - if (INTEL_GEN(dev_priv) > 2) + if (GT_GEN_RANGE(dev_priv, 3, GEN_FOREVER)) ee->mode = I915_READ_MODE(engine); if (!HWS_NEEDS_PHYSICAL(dev_priv)) { @@ -1278,7 +1278,7 @@ static void error_record_engine_registers(struct i915_gpu_state *error, else if (GT_GEN(dev_priv, 7)) ee->vm_info.pp_dir_base = I915_READ(RING_PP_DIR_BASE(engine)); - else if (INTEL_GEN(dev_priv) >= 8) + else if (GT_GEN_RANGE(dev_priv, 8, GEN_FOREVER)) for (i = 0; i < 4; i++) { ee->vm_info.pdp[i] = I915_READ(GEN8_RING_PDP_UDW(engine, i)); @@ -1648,7 +1648,7 @@ static void capture_reg_state(struct i915_gpu_state *error) if (GT_GEN(dev_priv, 7)) error->err_int = I915_READ(GEN7_ERR_INT); - if (INTEL_GEN(dev_priv) >= 8) { + if (GT_GEN_RANGE(dev_priv, 8, GEN_FOREVER)) { error->fault_data0 = I915_READ(GEN8_FAULT_TLB_DATA0); error->fault_data1 = I915_READ(GEN8_FAULT_TLB_DATA1); } @@ -1660,16 +1660,16 @@ static void capture_reg_state(struct i915_gpu_state *error) } /* 2: Registers which belong to multiple generations */ - if (INTEL_GEN(dev_priv) >= 7) + if (GT_GEN_RANGE(dev_priv, 7, GEN_FOREVER)) error->forcewake = I915_READ_FW(FORCEWAKE_MT); - if (INTEL_GEN(dev_priv) >= 6) { + if (GT_GEN_RANGE(dev_priv, 6, GEN_FOREVER)) { error->derrmr = I915_READ(DERRMR); error->error = I915_READ(ERROR_GEN6); error->done_reg = I915_READ(DONE_REG); } - if (INTEL_GEN(dev_priv) >= 5) + if (GT_GEN_RANGE(dev_priv, 5, GEN_FOREVER)) error->ccid = I915_READ(CCID); /* 3: Feature specific registers */ @@ -1679,7 +1679,7 @@ static void capture_reg_state(struct i915_gpu_state *error) } /* 4: Everything else */ - if (INTEL_GEN(dev_priv) >= 11) { + if (GT_GEN_RANGE(dev_priv, 11, GEN_FOREVER)) { error->ier = I915_READ(GEN8_DE_MISC_IER); error->gtier[0] = I915_READ(GEN11_RENDER_COPY_INTR_ENABLE); error->gtier[1] = I915_READ(GEN11_VCS_VECS_INTR_ENABLE); @@ -1688,7 +1688,7 @@ static void capture_reg_state(struct i915_gpu_state *error) error->gtier[4] = I915_READ(GEN11_CRYPTO_RSVD_INTR_ENABLE); error->gtier[5] = I915_READ(GEN11_GUNIT_CSME_INTR_ENABLE); error->ngtier = 6; - } else if (INTEL_GEN(dev_priv) >= 8) { + } else if (GT_GEN_RANGE(dev_priv, 8, GEN_FOREVER)) { error->ier = I915_READ(GEN8_DE_MISC_IER); for (i = 0; i < 4; i++) error->gtier[i] = I915_READ(GEN8_GT_IER(i)); diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index e53e9ccf90f6..04f2ecc09383 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -359,16 +359,16 @@ void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask) static i915_reg_t gen6_pm_iir(struct drm_i915_private *dev_priv) { - WARN_ON_ONCE(INTEL_GEN(dev_priv) >= 11); + WARN_ON_ONCE(GT_GEN_RANGE(dev_priv, 11, GEN_FOREVER)); - return INTEL_GEN(dev_priv) >= 8 ? GEN8_GT_IIR(2) : GEN6_PMIIR; + return GT_GEN_RANGE(dev_priv, 8, GEN_FOREVER) ? GEN8_GT_IIR(2) : GEN6_PMIIR; } static i915_reg_t gen6_pm_imr(struct drm_i915_private *dev_priv) { - if (INTEL_GEN(dev_priv) >= 11) + if (GT_GEN_RANGE(dev_priv, 11, GEN_FOREVER)) return GEN11_GPM_WGBOXPERF_INTR_MASK; - else if (INTEL_GEN(dev_priv) >= 8) + else if (GT_GEN_RANGE(dev_priv, 8, GEN_FOREVER)) return GEN8_GT_IMR(2); else return GEN6_PMIMR; @@ -376,9 +376,9 @@ static i915_reg_t gen6_pm_imr(struct drm_i915_private *dev_priv) static i915_reg_t gen6_pm_ier(struct drm_i915_private *dev_priv) { - if (INTEL_GEN(dev_priv) >= 11) + if (GT_GEN_RANGE(dev_priv, 11, GEN_FOREVER)) return GEN11_GPM_WGBOXPERF_INTR_ENABLE; - else if (INTEL_GEN(dev_priv) >= 8) + else if (GT_GEN_RANGE(dev_priv, 8, GEN_FOREVER)) return GEN8_GT_IER(2); else return GEN6_PMIER; @@ -493,7 +493,7 @@ void gen6_enable_rps_interrupts(struct drm_i915_private *dev_priv) spin_lock_irq(&dev_priv->irq_lock); WARN_ON_ONCE(rps->pm_iir); - if (INTEL_GEN(dev_priv) >= 11) + if (GT_GEN_RANGE(dev_priv, 11, GEN_FOREVER)) WARN_ON_ONCE(gen11_reset_one_iir(dev_priv, 0, GEN11_GTPM)); else WARN_ON_ONCE(I915_READ(gen6_pm_iir(dev_priv)) & dev_priv->pm_rps_events); @@ -527,7 +527,7 @@ void gen6_disable_rps_interrupts(struct drm_i915_private *dev_priv) * state of the worker can be discarded. */ cancel_work_sync(&rps->work); - if (INTEL_GEN(dev_priv) >= 11) + if (GT_GEN_RANGE(dev_priv, 11, GEN_FOREVER)) gen11_reset_rps_interrupts(dev_priv); else gen6_reset_rps_interrupts(dev_priv); @@ -668,7 +668,7 @@ u32 i915_pipestat_enable_mask(struct drm_i915_private *dev_priv, lockdep_assert_held(&dev_priv->irq_lock); - if (INTEL_GEN(dev_priv) < 5) + if (GT_GEN_RANGE(dev_priv, 0, 4)) goto out; /* @@ -759,7 +759,7 @@ static void i915_enable_asle_pipestat(struct drm_i915_private *dev_priv) spin_lock_irq(&dev_priv->irq_lock); i915_enable_pipestat(dev_priv, PIPE_B, PIPE_LEGACY_BLC_EVENT_STATUS); - if (INTEL_GEN(dev_priv) >= 4) + if (GT_GEN_RANGE(dev_priv, 4, GEN_FOREVER)) i915_enable_pipestat(dev_priv, PIPE_A, PIPE_LEGACY_BLC_EVENT_STATUS); @@ -1030,7 +1030,7 @@ static bool i915_get_crtc_scanoutpos(struct drm_device *dev, unsigned int pipe, if (stime) *stime = ktime_get(); - if (GT_GEN(dev_priv, 2) || IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5) { + if (GT_GEN(dev_priv, 2) || IS_G4X(dev_priv) || GT_GEN_RANGE(dev_priv, 5, GEN_FOREVER)) { /* No obvious pixelcount register. Only query vertical * scanout position from Display scan line register. */ @@ -1090,7 +1090,7 @@ static bool i915_get_crtc_scanoutpos(struct drm_device *dev, unsigned int pipe, else position += vtotal - vbl_end; - if (GT_GEN(dev_priv, 2) || IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5) { + if (GT_GEN(dev_priv, 2) || IS_G4X(dev_priv) || GT_GEN_RANGE(dev_priv, 5, GEN_FOREVER)) { *vpos = position; *hpos = 0; } else { @@ -1756,7 +1756,7 @@ static void display_pipe_crc_irq_handler(struct drm_i915_private *dev_priv, * don't trust that one either. */ if (pipe_crc->skipped <= 0 || - (INTEL_GEN(dev_priv) >= 8 && pipe_crc->skipped == 1)) { + (GT_GEN_RANGE(dev_priv, 8, GEN_FOREVER) && pipe_crc->skipped == 1)) { pipe_crc->skipped++; spin_unlock(&pipe_crc->lock); return; @@ -1806,12 +1806,12 @@ static void i9xx_pipe_crc_irq_handler(struct drm_i915_private *dev_priv, { uint32_t res1, res2; - if (INTEL_GEN(dev_priv) >= 3) + if (GT_GEN_RANGE(dev_priv, 3, GEN_FOREVER)) res1 = I915_READ(PIPE_CRC_RES_RES1_I915(pipe)); else res1 = 0; - if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv)) + if (GT_GEN_RANGE(dev_priv, 5, GEN_FOREVER) || IS_G4X(dev_priv)) res2 = I915_READ(PIPE_CRC_RES_RES2_G4X(pipe)); else res2 = 0; @@ -1840,7 +1840,7 @@ static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir) spin_unlock(&dev_priv->irq_lock); } - if (INTEL_GEN(dev_priv) >= 8) + if (GT_GEN_RANGE(dev_priv, 8, GEN_FOREVER)) return; if (HAS_VEBOX(dev_priv)) { @@ -2633,7 +2633,7 @@ static irqreturn_t ironlake_irq_handler(int irq, void *arg) if (gt_iir) { I915_WRITE(GTIIR, gt_iir); ret = IRQ_HANDLED; - if (INTEL_GEN(dev_priv) >= 6) + if (GT_GEN_RANGE(dev_priv, 6, GEN_FOREVER)) snb_gt_irq_handler(dev_priv, gt_iir); else ilk_gt_irq_handler(dev_priv, gt_iir); @@ -2643,13 +2643,13 @@ static irqreturn_t ironlake_irq_handler(int irq, void *arg) if (de_iir) { I915_WRITE(DEIIR, de_iir); ret = IRQ_HANDLED; - if (INTEL_GEN(dev_priv) >= 7) + if (GT_GEN_RANGE(dev_priv, 7, GEN_FOREVER)) ivb_display_irq_handler(dev_priv, de_iir); else ilk_display_irq_handler(dev_priv, de_iir); } - if (INTEL_GEN(dev_priv) >= 6) { + if (GT_GEN_RANGE(dev_priv, 6, GEN_FOREVER)) { u32 pm_iir = I915_READ(GEN6_PMIIR); if (pm_iir) { I915_WRITE(GEN6_PMIIR, pm_iir); @@ -2753,7 +2753,7 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl) DRM_ERROR("The master control interrupt lied (DE MISC)!\n"); } - if (INTEL_GEN(dev_priv) >= 11 && (master_ctl & GEN11_DE_HPD_IRQ)) { + if (GT_GEN_RANGE(dev_priv, 11, GEN_FOREVER) && (master_ctl & GEN11_DE_HPD_IRQ)) { iir = I915_READ(GEN11_DE_HPD_IIR); if (iir) { I915_WRITE(GEN11_DE_HPD_IIR, iir); @@ -2774,16 +2774,16 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl) ret = IRQ_HANDLED; tmp_mask = GEN8_AUX_CHANNEL_A; - if (INTEL_GEN(dev_priv) >= 9) + if (GT_GEN_RANGE(dev_priv, 9, GEN_FOREVER)) tmp_mask |= GEN9_AUX_CHANNEL_B | GEN9_AUX_CHANNEL_C | GEN9_AUX_CHANNEL_D; - if (INTEL_GEN(dev_priv) >= 11) + if (GT_GEN_RANGE(dev_priv, 11, GEN_FOREVER)) tmp_mask |= ICL_AUX_CHANNEL_E; if (IS_CNL_WITH_PORT_F(dev_priv) || - INTEL_GEN(dev_priv) >= 11) + GT_GEN_RANGE(dev_priv, 11, GEN_FOREVER)) tmp_mask |= CNL_AUX_CHANNEL_F; if (iir & tmp_mask) { @@ -2844,7 +2844,7 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl) intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe); fault_errors = iir; - if (INTEL_GEN(dev_priv) >= 9) + if (GT_GEN_RANGE(dev_priv, 9, GEN_FOREVER)) fault_errors &= GEN9_DE_PIPE_IRQ_FAULT_ERRORS; else fault_errors &= GEN8_DE_PIPE_IRQ_FAULT_ERRORS; @@ -3246,7 +3246,7 @@ void i915_clear_error_registers(struct drm_i915_private *dev_priv) if (!GT_GEN(dev_priv, 2)) I915_WRITE(PGTBL_ER, I915_READ(PGTBL_ER)); - if (INTEL_GEN(dev_priv) < 4) + if (GT_GEN_RANGE(dev_priv, 0, 3)) I915_WRITE(IPEIR, I915_READ(IPEIR)); else I915_WRITE(IPEIR_I965, I915_READ(IPEIR_I965)); @@ -3263,11 +3263,11 @@ void i915_clear_error_registers(struct drm_i915_private *dev_priv) I915_WRITE(IIR, I915_MASTER_ERROR_INTERRUPT); } - if (INTEL_GEN(dev_priv) >= 8) { + if (GT_GEN_RANGE(dev_priv, 8, GEN_FOREVER)) { I915_WRITE(GEN8_RING_FAULT_REG, I915_READ(GEN8_RING_FAULT_REG) & ~RING_FAULT_VALID); POSTING_READ(GEN8_RING_FAULT_REG); - } else if (INTEL_GEN(dev_priv) >= 6) { + } else if (GT_GEN_RANGE(dev_priv, 6, GEN_FOREVER)) { struct intel_engine_cs *engine; enum intel_engine_id id; @@ -3417,7 +3417,7 @@ static int ironlake_enable_vblank(struct drm_device *dev, unsigned int pipe) { struct drm_i915_private *dev_priv = to_i915(dev); unsigned long irqflags; - uint32_t bit = INTEL_GEN(dev_priv) >= 7 ? + uint32_t bit = GT_GEN_RANGE(dev_priv, 7, GEN_FOREVER) ? DE_PIPE_VBLANK_IVB(pipe) : DE_PIPE_VBLANK(pipe); spin_lock_irqsave(&dev_priv->irq_lock, irqflags); @@ -3479,7 +3479,7 @@ static void ironlake_disable_vblank(struct drm_device *dev, unsigned int pipe) { struct drm_i915_private *dev_priv = to_i915(dev); unsigned long irqflags; - uint32_t bit = INTEL_GEN(dev_priv) >= 7 ? + uint32_t bit = GT_GEN_RANGE(dev_priv, 7, GEN_FOREVER) ? DE_PIPE_VBLANK_IVB(pipe) : DE_PIPE_VBLANK(pipe); spin_lock_irqsave(&dev_priv->irq_lock, irqflags); @@ -3531,7 +3531,7 @@ static void ibx_irq_pre_postinstall(struct drm_device *dev) static void gen5_gt_irq_reset(struct drm_i915_private *dev_priv) { GEN3_IRQ_RESET(GT); - if (INTEL_GEN(dev_priv) >= 6) + if (GT_GEN_RANGE(dev_priv, 6, GEN_FOREVER)) GEN3_IRQ_RESET(GEN6_PM); } @@ -3932,12 +3932,12 @@ static void ilk_hpd_irq_setup(struct drm_i915_private *dev_priv) { u32 hotplug_irqs, enabled_irqs; - if (INTEL_GEN(dev_priv) >= 8) { + if (GT_GEN_RANGE(dev_priv, 8, GEN_FOREVER)) { hotplug_irqs = GEN8_PORT_DP_A_HOTPLUG; enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_bdw); bdw_update_port_irq(dev_priv, hotplug_irqs, enabled_irqs); - } else if (INTEL_GEN(dev_priv) >= 7) { + } else if (GT_GEN_RANGE(dev_priv, 7, GEN_FOREVER)) { hotplug_irqs = DE_DP_A_HOTPLUG_IVB; enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_ivb); @@ -4050,7 +4050,7 @@ static void gen5_gt_irq_postinstall(struct drm_device *dev) GEN3_IRQ_INIT(GT, dev_priv->gt_irq_mask, gt_irqs); - if (INTEL_GEN(dev_priv) >= 6) { + if (GT_GEN_RANGE(dev_priv, 6, GEN_FOREVER)) { /* * RPS interrupts will get enabled/disabled on demand when RPS * itself is enabled/disabled. @@ -4070,7 +4070,7 @@ static int ironlake_irq_postinstall(struct drm_device *dev) struct drm_i915_private *dev_priv = to_i915(dev); u32 display_mask, extra_mask; - if (INTEL_GEN(dev_priv) >= 7) { + if (GT_GEN_RANGE(dev_priv, 7, GEN_FOREVER)) { display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE_IVB | DE_PCH_EVENT_IVB | DE_AUX_CHANNEL_A_IVB); extra_mask = (DE_PIPEC_VBLANK_IVB | DE_PIPEB_VBLANK_IVB | @@ -4204,10 +4204,10 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv) u32 de_misc_masked = GEN8_DE_EDP_PSR; enum pipe pipe; - if (INTEL_GEN(dev_priv) <= 10) + if (GT_GEN_RANGE(dev_priv, 0, 10)) de_misc_masked |= GEN8_DE_MISC_GSE; - if (INTEL_GEN(dev_priv) >= 9) { + if (GT_GEN_RANGE(dev_priv, 9, GEN_FOREVER)) { de_pipe_masked |= GEN9_DE_PIPE_IRQ_FAULT_ERRORS; de_port_masked |= GEN9_AUX_CHANNEL_B | GEN9_AUX_CHANNEL_C | GEN9_AUX_CHANNEL_D; @@ -4217,10 +4217,10 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv) de_pipe_masked |= GEN8_DE_PIPE_IRQ_FAULT_ERRORS; } - if (INTEL_GEN(dev_priv) >= 11) + if (GT_GEN_RANGE(dev_priv, 11, GEN_FOREVER)) de_port_masked |= ICL_AUX_CHANNEL_E; - if (IS_CNL_WITH_PORT_F(dev_priv) || INTEL_GEN(dev_priv) >= 11) + if (IS_CNL_WITH_PORT_F(dev_priv) || GT_GEN_RANGE(dev_priv, 11, GEN_FOREVER)) de_port_masked |= CNL_AUX_CHANNEL_F; de_pipe_enables = de_pipe_masked | GEN8_PIPE_VBLANK | @@ -4248,7 +4248,7 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv) GEN3_IRQ_INIT(GEN8_DE_PORT_, ~de_port_masked, de_port_enables); GEN3_IRQ_INIT(GEN8_DE_MISC_, ~de_misc_masked, de_misc_masked); - if (INTEL_GEN(dev_priv) >= 11) { + if (GT_GEN_RANGE(dev_priv, 11, GEN_FOREVER)) { u32 de_hpd_masked = 0; u32 de_hpd_enables = GEN11_DE_TC_HOTPLUG_MASK | GEN11_DE_TBT_HOTPLUG_MASK; @@ -4827,16 +4827,16 @@ void intel_irq_init(struct drm_i915_private *dev_priv) * * TODO: verify if this can be reproduced on VLV,CHV. */ - if (INTEL_GEN(dev_priv) <= 7) + if (GT_GEN_RANGE(dev_priv, 0, 7)) rps->pm_intrmsk_mbz |= GEN6_PM_RP_UP_EI_EXPIRED; - if (INTEL_GEN(dev_priv) >= 8) + if (GT_GEN_RANGE(dev_priv, 8, GEN_FOREVER)) rps->pm_intrmsk_mbz |= GEN8_PMINTR_DISABLE_REDIRECT_TO_GUC; if (GT_GEN(dev_priv, 2)) { /* Gen2 doesn't have a hardware frame counter */ dev->max_vblank_count = 0; - } else if (IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5) { + } else if (IS_G4X(dev_priv) || GT_GEN_RANGE(dev_priv, 5, GEN_FOREVER)) { dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */ dev->driver->get_vblank_counter = g4x_get_vblank_counter; } else { @@ -4883,7 +4883,7 @@ void intel_irq_init(struct drm_i915_private *dev_priv) dev->driver->enable_vblank = i965_enable_vblank; dev->driver->disable_vblank = i965_disable_vblank; dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup; - } else if (INTEL_GEN(dev_priv) >= 11) { + } else if (GT_GEN_RANGE(dev_priv, 11, GEN_FOREVER)) { dev->driver->irq_handler = gen11_irq_handler; dev->driver->irq_preinstall = gen11_irq_reset; dev->driver->irq_postinstall = gen11_irq_postinstall; @@ -4891,7 +4891,7 @@ void intel_irq_init(struct drm_i915_private *dev_priv) dev->driver->enable_vblank = gen8_enable_vblank; dev->driver->disable_vblank = gen8_disable_vblank; dev_priv->display.hpd_irq_setup = gen11_hpd_irq_setup; - } else if (INTEL_GEN(dev_priv) >= 8) { + } else if (GT_GEN_RANGE(dev_priv, 8, GEN_FOREVER)) { dev->driver->irq_handler = gen8_irq_handler; dev->driver->irq_preinstall = gen8_irq_reset; dev->driver->irq_postinstall = gen8_irq_postinstall; diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c index afbccc144c66..5cc1ffa621a7 100644 --- a/drivers/gpu/drm/i915/i915_perf.c +++ b/drivers/gpu/drm/i915/i915_perf.c @@ -3245,7 +3245,7 @@ int i915_perf_add_config_ioctl(struct drm_device *dev, void *data, goto reg_err; } - if (INTEL_GEN(dev_priv) < 8) { + if (GT_GEN_RANGE(dev_priv, 0, 7)) { if (args->n_flex_regs != 0) { err = -EINVAL; goto reg_err; diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c index d6c8f8fdfda5..93dace5fce3a 100644 --- a/drivers/gpu/drm/i915/i915_pmu.c +++ b/drivers/gpu/drm/i915/i915_pmu.c @@ -326,7 +326,7 @@ engine_event_status(struct intel_engine_cs *engine, case I915_SAMPLE_WAIT: break; case I915_SAMPLE_SEMA: - if (INTEL_GEN(engine->i915) < 6) + if (GT_GEN_RANGE(engine->i915, 0, 5)) return -ENODEV; break; default: @@ -346,7 +346,7 @@ config_status(struct drm_i915_private *i915, u64 config) return -ENODEV; /* Fall-through. */ case I915_PMU_REQUESTED_FREQUENCY: - if (INTEL_GEN(i915) < 6) + if (GT_GEN_RANGE(i915, 0, 5)) return -ENODEV; break; case I915_PMU_INTERRUPTS: @@ -1036,7 +1036,7 @@ void i915_pmu_register(struct drm_i915_private *i915) { int ret; - if (INTEL_GEN(i915) <= 2) { + if (GT_GEN_RANGE(i915, 0, 2)) { DRM_INFO("PMU not supported for this GPU."); return; } diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 33febd5a9eac..0c806230ca35 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -3813,7 +3813,7 @@ enum i915_power_well_id { #define INTERVAL_1_28_US(us) roundup(((us) * 100) >> 7, 25) #define INTERVAL_1_33_US(us) (((us) * 3) >> 2) #define INTERVAL_0_833_US(us) (((us) * 6) / 5) -#define GT_INTERVAL_FROM_US(dev_priv, us) (INTEL_GEN(dev_priv) >= 9 ? \ +#define GT_INTERVAL_FROM_US(dev_priv, us) (GT_GEN_RANGE(dev_priv, 9, GEN_FOREVER) ? \ (GT_GEN9_LP(dev_priv) ? \ INTERVAL_0_833_US(us) : \ INTERVAL_1_33_US(us)) : \ @@ -3822,7 +3822,7 @@ enum i915_power_well_id { #define INTERVAL_1_28_TO_US(interval) (((interval) << 7) / 100) #define INTERVAL_1_33_TO_US(interval) (((interval) << 2) / 3) #define INTERVAL_0_833_TO_US(interval) (((interval) * 5) / 6) -#define GT_PM_INTERVAL_TO_US(dev_priv, interval) (INTEL_GEN(dev_priv) >= 9 ? \ +#define GT_PM_INTERVAL_TO_US(dev_priv, interval) (GT_GEN_RANGE(dev_priv, 9, GEN_FOREVER) ? \ (GT_GEN9_LP(dev_priv) ? \ INTERVAL_0_833_TO_US(interval) : \ INTERVAL_1_33_TO_US(interval)) : \ diff --git a/drivers/gpu/drm/i915/i915_suspend.c b/drivers/gpu/drm/i915/i915_suspend.c index b47b822fa6d6..e7a57005ff0e 100644 --- a/drivers/gpu/drm/i915/i915_suspend.c +++ b/drivers/gpu/drm/i915/i915_suspend.c @@ -32,25 +32,25 @@ static void i915_save_display(struct drm_i915_private *dev_priv) { /* Display arbitration control */ - if (INTEL_GEN(dev_priv) <= 4) + if (GT_GEN_RANGE(dev_priv, 0, 4)) dev_priv->regfile.saveDSPARB = I915_READ(DSPARB); /* save FBC interval */ - if (HAS_FBC(dev_priv) && INTEL_GEN(dev_priv) <= 4 && !IS_G4X(dev_priv)) + if (HAS_FBC(dev_priv) && GT_GEN_RANGE(dev_priv, 0, 4) && !IS_G4X(dev_priv)) dev_priv->regfile.saveFBC_CONTROL = I915_READ(FBC_CONTROL); } static void i915_restore_display(struct drm_i915_private *dev_priv) { /* Display arbitration */ - if (INTEL_GEN(dev_priv) <= 4) + if (GT_GEN_RANGE(dev_priv, 0, 4)) I915_WRITE(DSPARB, dev_priv->regfile.saveDSPARB); /* only restore FBC info on the platform that supports FBC*/ intel_fbc_global_disable(dev_priv); /* restore FBC interval */ - if (HAS_FBC(dev_priv) && INTEL_GEN(dev_priv) <= 4 && !IS_G4X(dev_priv)) + if (HAS_FBC(dev_priv) && GT_GEN_RANGE(dev_priv, 0, 4) && !IS_G4X(dev_priv)) I915_WRITE(FBC_CONTROL, dev_priv->regfile.saveFBC_CONTROL); i915_redisable_vga(dev_priv); @@ -70,7 +70,7 @@ int i915_save_state(struct drm_i915_private *dev_priv) &dev_priv->regfile.saveGCDGMBUS); /* Cache mode state */ - if (INTEL_GEN(dev_priv) < 7) + if (GT_GEN_RANGE(dev_priv, 0, 6)) dev_priv->regfile.saveCACHE_MODE_0 = I915_READ(CACHE_MODE_0); /* Memory Arbitration state */ @@ -114,7 +114,7 @@ int i915_restore_state(struct drm_i915_private *dev_priv) i915_restore_display(dev_priv); /* Cache mode state */ - if (INTEL_GEN(dev_priv) < 7) + if (GT_GEN_RANGE(dev_priv, 0, 6)) I915_WRITE(CACHE_MODE_0, dev_priv->regfile.saveCACHE_MODE_0 | 0xffff0000); diff --git a/drivers/gpu/drm/i915/i915_sysfs.c b/drivers/gpu/drm/i915/i915_sysfs.c index e5e6f6bb2b05..c8786a5654e4 100644 --- a/drivers/gpu/drm/i915/i915_sysfs.c +++ b/drivers/gpu/drm/i915/i915_sysfs.c @@ -617,7 +617,7 @@ void i915_setup_sysfs(struct drm_i915_private *dev_priv) ret = 0; if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) ret = sysfs_create_files(&kdev->kobj, vlv_attrs); - else if (INTEL_GEN(dev_priv) >= 6) + else if (GT_GEN_RANGE(dev_priv, 6, GEN_FOREVER)) ret = sysfs_create_files(&kdev->kobj, gen6_attrs); if (ret) DRM_ERROR("RPS sysfs setup failed\n"); diff --git a/drivers/gpu/drm/i915/intel_atomic.c b/drivers/gpu/drm/i915/intel_atomic.c index 74dc23f67151..acd8804b0368 100644 --- a/drivers/gpu/drm/i915/intel_atomic.c +++ b/drivers/gpu/drm/i915/intel_atomic.c @@ -248,7 +248,7 @@ static void intel_atomic_setup_scaler(struct intel_crtc_scaler_state *scaler_sta if (plane_state->linked_plane) mode |= PS_PLANE_Y_SEL(plane_state->linked_plane->id); } - } else if (INTEL_GEN(dev_priv) > 9 || IS_GEMINILAKE(dev_priv)) { + } else if (GT_GEN_RANGE(dev_priv, 10, GEN_FOREVER) || IS_GEMINILAKE(dev_priv)) { mode = PS_SCALER_MODE_NORMAL; } else if (num_scalers_need == 1 && intel_crtc->num_scalers > 1) { /* diff --git a/drivers/gpu/drm/i915/intel_audio.c b/drivers/gpu/drm/i915/intel_audio.c index 7f47bacbef20..c2e8a53710b8 100644 --- a/drivers/gpu/drm/i915/intel_audio.c +++ b/drivers/gpu/drm/i915/intel_audio.c @@ -733,7 +733,7 @@ void intel_init_audio_hooks(struct drm_i915_private *dev_priv) } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { dev_priv->display.audio_codec_enable = ilk_audio_codec_enable; dev_priv->display.audio_codec_disable = ilk_audio_codec_disable; - } else if (IS_HASWELL(dev_priv) || INTEL_GEN(dev_priv) >= 8) { + } else if (IS_HASWELL(dev_priv) || GT_GEN_RANGE(dev_priv, 8, GEN_FOREVER)) { dev_priv->display.audio_codec_enable = hsw_audio_codec_enable; dev_priv->display.audio_codec_disable = hsw_audio_codec_disable; } else if (HAS_PCH_SPLIT(dev_priv)) { diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c index 8fa3c79c5f4a..69e41089d7de 100644 --- a/drivers/gpu/drm/i915/intel_bios.c +++ b/drivers/gpu/drm/i915/intel_bios.c @@ -516,7 +516,7 @@ parse_driver_features(struct drm_i915_private *dev_priv, if (!driver) return; - if (INTEL_GEN(dev_priv) >= 5) { + if (GT_GEN_RANGE(dev_priv, 5, GEN_FOREVER)) { /* * Note that we consider BDB_DRIVER_FEATURE_INT_SDVO_LVDS * to mean "eDP". The VBT spec doesn't agree with that @@ -712,7 +712,7 @@ parse_psr(struct drm_i915_private *dev_priv, const struct bdb_header *bdb) */ if (bdb->version >= 205 && (GT_GEN9_BC(dev_priv) || IS_GEMINILAKE(dev_priv) || - INTEL_GEN(dev_priv) >= 10)) { + GT_GEN_RANGE(dev_priv, 10, GEN_FOREVER))) { switch (psr_table->tp1_wakeup_time) { case 0: dev_priv->vbt.psr.tp1_wakeup_time_us = 500; diff --git a/drivers/gpu/drm/i915/intel_cdclk.c b/drivers/gpu/drm/i915/intel_cdclk.c index 37835d547d68..87af19d11d1e 100644 --- a/drivers/gpu/drm/i915/intel_cdclk.c +++ b/drivers/gpu/drm/i915/intel_cdclk.c @@ -2138,7 +2138,7 @@ void intel_set_cdclk(struct drm_i915_private *dev_priv, static int intel_pixel_rate_to_cdclk(struct drm_i915_private *dev_priv, int pixel_rate) { - if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) + if (GT_GEN_RANGE(dev_priv, 10, GEN_FOREVER) || IS_GEMINILAKE(dev_priv)) return DIV_ROUND_UP(pixel_rate, 2); else if (GT_GEN(dev_priv, 9) || IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) @@ -2197,7 +2197,7 @@ int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state) * at probe time. If we probe without displays, we'll still end up using * the platform minimum CDCLK, failing audio probe. */ - if (INTEL_GEN(dev_priv) >= 9) + if (GT_GEN_RANGE(dev_priv, 9, GEN_FOREVER)) min_cdclk = max(2 * 96000, min_cdclk); /* @@ -2535,14 +2535,14 @@ static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv) { int max_cdclk_freq = dev_priv->max_cdclk_freq; - if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) + if (GT_GEN_RANGE(dev_priv, 10, GEN_FOREVER) || IS_GEMINILAKE(dev_priv)) return 2 * max_cdclk_freq; else if (GT_GEN(dev_priv, 9) || IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) return max_cdclk_freq; else if (IS_CHERRYVIEW(dev_priv)) return max_cdclk_freq*95/100; - else if (INTEL_GEN(dev_priv) < 4) + else if (GT_GEN_RANGE(dev_priv, 0, 3)) return 2*max_cdclk_freq*90/100; else return max_cdclk_freq*90/100; diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c index 91a46e4f3453..19a96b6dc9b5 100644 --- a/drivers/gpu/drm/i915/intel_color.c +++ b/drivers/gpu/drm/i915/intel_color.c @@ -146,7 +146,7 @@ static void ilk_load_csc_matrix(struct drm_crtc_state *crtc_state) * FIXME if there's a gamma LUT after the CSC, we should * do the range compression using the gamma LUT instead. */ - if (INTEL_GEN(dev_priv) >= 8 || IS_HASWELL(dev_priv)) + if (GT_GEN_RANGE(dev_priv, 8, GEN_FOREVER) || IS_HASWELL(dev_priv)) limited_color_range = intel_crtc_state->limited_color_range; if (intel_crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 || @@ -229,7 +229,7 @@ static void ilk_load_csc_matrix(struct drm_crtc_state *crtc_state) I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0); I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0); - if (INTEL_GEN(dev_priv) > 6) { + if (GT_GEN_RANGE(dev_priv, 7, GEN_FOREVER)) { uint16_t postoff = 0; if (limited_color_range) diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c index b37224227420..dbc97c29f7e5 100644 --- a/drivers/gpu/drm/i915/intel_crt.c +++ b/drivers/gpu/drm/i915/intel_crt.c @@ -156,7 +156,7 @@ static void intel_crt_set_dpms(struct intel_encoder *encoder, const struct drm_display_mode *adjusted_mode = &crtc_state->base.adjusted_mode; u32 adpa; - if (INTEL_GEN(dev_priv) >= 5) + if (GT_GEN_RANGE(dev_priv, 5, GEN_FOREVER)) adpa = ADPA_HOTPLUG_BITS; else adpa = 0; @@ -833,7 +833,7 @@ intel_crt_detect(struct drm_connector *connector, if (ret > 0) { if (intel_crt_detect_ddc(connector)) status = connector_status_connected; - else if (INTEL_GEN(dev_priv) < 4) + else if (GT_GEN_RANGE(dev_priv, 0, 3)) status = intel_crt_load_detect(crt, to_intel_crtc(connector->state->crtc)->pipe); else if (i915_modparams.load_detect_test) @@ -883,7 +883,7 @@ void intel_crt_reset(struct drm_encoder *encoder) struct drm_i915_private *dev_priv = to_i915(encoder->dev); struct intel_crt *crt = intel_encoder_to_crt(to_intel_encoder(encoder)); - if (INTEL_GEN(dev_priv) >= 5) { + if (GT_GEN_RANGE(dev_priv, 5, GEN_FOREVER)) { u32 adpa; adpa = I915_READ(crt->adpa_reg); diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c index c8390eebe8e3..2664b782054d 100644 --- a/drivers/gpu/drm/i915/intel_ddi.c +++ b/drivers/gpu/drm/i915/intel_ddi.c @@ -1369,7 +1369,7 @@ static int cnl_calc_wrpll_link(struct drm_i915_private *dev_priv, uint32_t cfgcr0, cfgcr1; uint32_t p0, p1, p2, dco_freq, ref_clock; - if (INTEL_GEN(dev_priv) >= 11) { + if (GT_GEN_RANGE(dev_priv, 11, GEN_FOREVER)) { cfgcr0 = I915_READ(ICL_DPLL_CFGCR0(pll_id)); cfgcr1 = I915_READ(ICL_DPLL_CFGCR1(pll_id)); } else { @@ -1745,7 +1745,7 @@ static void intel_ddi_clock_get(struct intel_encoder *encoder, bxt_ddi_clock_get(encoder, pipe_config); else if (GT_GEN9_BC(dev_priv)) skl_ddi_clock_get(encoder, pipe_config); - else if (INTEL_GEN(dev_priv) <= 8) + else if (GT_GEN_RANGE(dev_priv, 0, 8)) hsw_ddi_clock_get(encoder, pipe_config); } @@ -2888,7 +2888,7 @@ static void intel_ddi_clk_select(struct intel_encoder *encoder, I915_WRITE(DPLL_CTRL2, val); - } else if (INTEL_GEN(dev_priv) < 9) { + } else if (GT_GEN_RANGE(dev_priv, 0, 8)) { I915_WRITE(PORT_CLK_SEL(port), hsw_pll_to_ddi_pll_sel(pll)); } @@ -2909,7 +2909,7 @@ static void intel_ddi_clk_disable(struct intel_encoder *encoder) } else if (GT_GEN9_BC(dev_priv)) { I915_WRITE(DPLL_CTRL2, I915_READ(DPLL_CTRL2) | DPLL_CTRL2_DDI_CLK_OFF(port)); - } else if (INTEL_GEN(dev_priv) < 9) { + } else if (GT_GEN_RANGE(dev_priv, 0, 8)) { I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE); } } @@ -3084,7 +3084,7 @@ static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder, if (!is_mst) intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON); intel_dp_start_link_train(intel_dp); - if (port != PORT_A || INTEL_GEN(dev_priv) >= 9) + if (port != PORT_A || GT_GEN_RANGE(dev_priv, 9, GEN_FOREVER)) intel_dp_stop_link_train(intel_dp); icl_enable_phy_clock_gating(dig_port); @@ -3318,7 +3318,7 @@ static void intel_enable_ddi_dp(struct intel_encoder *encoder, struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); enum port port = encoder->port; - if (port == PORT_A && INTEL_GEN(dev_priv) < 9) + if (port == PORT_A && GT_GEN_RANGE(dev_priv, 0, 8)) intel_dp_stop_link_train(intel_dp); intel_edp_backlight_on(crtc_state, conn_state); @@ -3974,7 +3974,7 @@ intel_ddi_max_lanes(struct intel_digital_port *intel_dport) enum port port = intel_dport->base.port; int max_lanes = 4; - if (INTEL_GEN(dev_priv) >= 11) + if (GT_GEN_RANGE(dev_priv, 11, GEN_FOREVER)) return max_lanes; if (port == PORT_A || port == PORT_E) { @@ -4060,7 +4060,7 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port) for_each_pipe(dev_priv, pipe) intel_encoder->crtc_mask |= BIT(pipe); - if (INTEL_GEN(dev_priv) >= 11) + if (GT_GEN_RANGE(dev_priv, 11, GEN_FOREVER)) intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) & DDI_BUF_PORT_REVERSAL; else diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c index ab967781f495..bad3eb2428ac 100644 --- a/drivers/gpu/drm/i915/intel_device_info.c +++ b/drivers/gpu/drm/i915/intel_device_info.c @@ -648,7 +648,7 @@ static u32 read_timestamp_frequency(struct drm_i915_private *dev_priv) u32 f19_2_mhz = 19200; u32 f24_mhz = 24000; - if (INTEL_GEN(dev_priv) <= 4) { + if (GT_GEN_RANGE(dev_priv, 0, 4)) { /* PRMs say: * * "The value in this register increments once every 16 @@ -656,7 +656,7 @@ static u32 read_timestamp_frequency(struct drm_i915_private *dev_priv) * (“CLKCFG”) MCHBAR register) */ return dev_priv->rawclk_freq / 16; - } else if (INTEL_GEN(dev_priv) <= 8) { + } else if (GT_GEN_RANGE(dev_priv, 0, 8)) { /* PRMs say: * * "The PCU TSC counts 10ns increments; this timestamp @@ -664,7 +664,7 @@ static u32 read_timestamp_frequency(struct drm_i915_private *dev_priv) * rolling over every 1.5 hours). */ return f12_5_mhz; - } else if (INTEL_GEN(dev_priv) <= 9) { + } else if (GT_GEN_RANGE(dev_priv, 0, 9)) { u32 ctc_reg = I915_READ(CTC_MODE); u32 freq = 0; @@ -682,7 +682,7 @@ static u32 read_timestamp_frequency(struct drm_i915_private *dev_priv) } return freq; - } else if (INTEL_GEN(dev_priv) <= 11) { + } else if (GT_GEN_RANGE(dev_priv, 0, 11)) { u32 ctc_reg = I915_READ(CTC_MODE); u32 freq = 0; @@ -696,7 +696,7 @@ static u32 read_timestamp_frequency(struct drm_i915_private *dev_priv) } else { u32 rpm_config_reg = I915_READ(RPM_CONFIG0); - if (INTEL_GEN(dev_priv) <= 10) + if (GT_GEN_RANGE(dev_priv, 0, 10)) freq = gen10_get_crystal_clock_freq(dev_priv, rpm_config_reg); else @@ -741,7 +741,7 @@ void intel_device_info_runtime_init(struct intel_device_info *info) container_of(info, struct drm_i915_private, info); enum pipe pipe; - if (INTEL_GEN(dev_priv) >= 10) { + if (GT_GEN_RANGE(dev_priv, 10, GEN_FOREVER)) { for_each_pipe(dev_priv, pipe) info->num_scalers[pipe] = 2; } else if (GT_GEN(dev_priv, 9)) { @@ -774,7 +774,7 @@ void intel_device_info_runtime_init(struct intel_device_info *info) } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { for_each_pipe(dev_priv, pipe) info->num_sprites[pipe] = 2; - } else if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv)) { + } else if (GT_GEN_RANGE(dev_priv, 5, GEN_FOREVER) || IS_G4X(dev_priv)) { for_each_pipe(dev_priv, pipe) info->num_sprites[pipe] = 1; } @@ -851,7 +851,7 @@ void intel_device_info_runtime_init(struct intel_device_info *info) gen9_sseu_info_init(dev_priv); else if (GT_GEN(dev_priv, 10)) gen10_sseu_info_init(dev_priv); - else if (INTEL_GEN(dev_priv) >= 11) + else if (GT_GEN_RANGE(dev_priv, 11, GEN_FOREVER)) gen11_sseu_info_init(dev_priv); if (GT_GEN(dev_priv, 6) && intel_vtd_active()) { @@ -883,7 +883,7 @@ void intel_device_info_init_mmio(struct drm_i915_private *dev_priv) u32 media_fuse; unsigned int i; - if (INTEL_GEN(dev_priv) < 11) + if (GT_GEN_RANGE(dev_priv, 0, 10)) return; media_fuse = ~I915_READ(GEN11_GT_VEBOX_VDBOX_DISABLE); diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index b13956966a58..454a7e86adc8 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -1023,7 +1023,7 @@ intel_wait_for_pipe_off(const struct intel_crtc_state *old_crtc_state) struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc); struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); - if (INTEL_GEN(dev_priv) >= 4) { + if (GT_GEN_RANGE(dev_priv, 4, GEN_FOREVER)) { enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder; i915_reg_t reg = PIPECONF(cpu_transcoder); @@ -1480,7 +1480,7 @@ static void i9xx_enable_pll(struct intel_crtc *crtc, POSTING_READ(reg); udelay(150); - if (INTEL_GEN(dev_priv) >= 4) { + if (GT_GEN_RANGE(dev_priv, 4, GEN_FOREVER)) { I915_WRITE(DPLL_MD(crtc->pipe), crtc_state->dpll_hw_state.dpll_md); } else { @@ -1968,12 +1968,12 @@ static unsigned int intel_cursor_alignment(const struct drm_i915_private *dev_pr static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_priv) { - if (INTEL_GEN(dev_priv) >= 9) + if (GT_GEN_RANGE(dev_priv, 9, GEN_FOREVER)) return 256 * 1024; else if (IS_I965G(dev_priv) || IS_I965GM(dev_priv) || IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) return 128 * 1024; - else if (INTEL_GEN(dev_priv) >= 4) + else if (GT_GEN_RANGE(dev_priv, 4, GEN_FOREVER)) return 4 * 1024; else return 0; @@ -1992,7 +1992,7 @@ static unsigned int intel_surf_alignment(const struct drm_framebuffer *fb, case DRM_FORMAT_MOD_LINEAR: return intel_linear_alignment(dev_priv); case I915_FORMAT_MOD_X_TILED: - if (INTEL_GEN(dev_priv) >= 9) + if (GT_GEN_RANGE(dev_priv, 9, GEN_FOREVER)) return 256 * 1024; return 0; case I915_FORMAT_MOD_Y_TILED_CCS: @@ -2011,7 +2011,7 @@ static bool intel_plane_uses_fence(const struct intel_plane_state *plane_state) struct intel_plane *plane = to_intel_plane(plane_state->base.plane); struct drm_i915_private *dev_priv = to_i915(plane->base.dev); - return INTEL_GEN(dev_priv) < 4 || plane->has_fbc; + return GT_GEN_RANGE(dev_priv, 0, 3) || plane->has_fbc; } struct i915_vma * @@ -2087,7 +2087,7 @@ intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb, * mode that matches the user configuration. */ ret = i915_vma_pin_fence(vma); - if (ret != 0 && INTEL_GEN(dev_priv) < 4) { + if (ret != 0 && GT_GEN_RANGE(dev_priv, 0, 3)) { i915_gem_object_unpin_from_display_plane(vma); vma = ERR_PTR(ret); goto err; @@ -3145,12 +3145,12 @@ i9xx_plane_max_stride(struct intel_plane *plane, if (!HAS_GMCH_DISPLAY(dev_priv)) { return 32*1024; - } else if (INTEL_GEN(dev_priv) >= 4) { + } else if (GT_GEN_RANGE(dev_priv, 4, GEN_FOREVER)) { if (modifier == I915_FORMAT_MOD_X_TILED) return 16*1024; else return 32*1024; - } else if (INTEL_GEN(dev_priv) >= 3) { + } else if (GT_GEN_RANGE(dev_priv, 3, GEN_FOREVER)) { if (modifier == I915_FORMAT_MOD_X_TILED) return 8*1024; else @@ -3182,7 +3182,7 @@ static u32 i9xx_plane_ctl(const struct intel_crtc_state *crtc_state, if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) dspcntr |= DISPPLANE_PIPE_CSC_ENABLE; - if (INTEL_GEN(dev_priv) < 5) + if (GT_GEN_RANGE(dev_priv, 0, 4)) dspcntr |= DISPPLANE_SEL_PIPE(crtc->pipe); switch (fb->format->format) { @@ -3212,7 +3212,7 @@ static u32 i9xx_plane_ctl(const struct intel_crtc_state *crtc_state, return 0; } - if (INTEL_GEN(dev_priv) >= 4 && + if (GT_GEN_RANGE(dev_priv, 4, GEN_FOREVER) && fb->modifier == I915_FORMAT_MOD_X_TILED) dspcntr |= DISPPLANE_TILED; @@ -3245,7 +3245,7 @@ int i9xx_check_plane_surface(struct intel_plane_state *plane_state) intel_add_fb_offsets(&src_x, &src_y, plane_state, 0); - if (INTEL_GEN(dev_priv) >= 4) + if (GT_GEN_RANGE(dev_priv, 4, GEN_FOREVER)) offset = intel_plane_compute_aligned_offset(&src_x, &src_y, plane_state, 0); else @@ -3321,14 +3321,14 @@ static void i9xx_update_plane(struct intel_plane *plane, linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0); - if (INTEL_GEN(dev_priv) >= 4) + if (GT_GEN_RANGE(dev_priv, 4, GEN_FOREVER)) dspaddr_offset = plane_state->color_plane[0].offset; else dspaddr_offset = linear_offset; spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); - if (INTEL_GEN(dev_priv) < 4) { + if (GT_GEN_RANGE(dev_priv, 0, 3)) { /* pipesrc and dspsize control the size that is scaled from, * which should always be the user's requested size. */ @@ -3352,7 +3352,7 @@ static void i9xx_update_plane(struct intel_plane *plane, intel_plane_ggtt_offset(plane_state) + dspaddr_offset); I915_WRITE_FW(DSPOFFSET(i9xx_plane), (y << 16) | x); - } else if (INTEL_GEN(dev_priv) >= 4) { + } else if (GT_GEN_RANGE(dev_priv, 4, GEN_FOREVER)) { I915_WRITE_FW(DSPSURF(i9xx_plane), intel_plane_ggtt_offset(plane_state) + dspaddr_offset); @@ -3378,7 +3378,7 @@ static void i9xx_disable_plane(struct intel_plane *plane, spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); I915_WRITE_FW(DSPCNTR(i9xx_plane), 0); - if (INTEL_GEN(dev_priv) >= 4) + if (GT_GEN_RANGE(dev_priv, 4, GEN_FOREVER)) I915_WRITE_FW(DSPSURF(i9xx_plane), 0); else I915_WRITE_FW(DSPADDR(i9xx_plane), 0); @@ -3409,7 +3409,7 @@ static bool i9xx_plane_get_hw_state(struct intel_plane *plane, ret = val & DISPLAY_PLANE_ENABLE; - if (INTEL_GEN(dev_priv) >= 5) + if (GT_GEN_RANGE(dev_priv, 5, GEN_FOREVER)) *pipe = plane->pipe; else *pipe = (val & DISPPLANE_SEL_PIPE_MASK) >> @@ -3619,7 +3619,7 @@ u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state, plane_ctl = PLANE_CTL_ENABLE; - if (INTEL_GEN(dev_priv) < 10 && !IS_GEMINILAKE(dev_priv)) { + if (GT_GEN_RANGE(dev_priv, 0, 9) && !IS_GEMINILAKE(dev_priv)) { plane_ctl |= skl_plane_ctl_alpha(plane_state); plane_ctl |= PLANE_CTL_PIPE_GAMMA_ENABLE | @@ -3637,7 +3637,7 @@ u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state, plane_ctl |= skl_plane_ctl_tiling(fb->modifier); plane_ctl |= skl_plane_ctl_rotate(rotation & DRM_MODE_ROTATE_MASK); - if (INTEL_GEN(dev_priv) >= 10) + if (GT_GEN_RANGE(dev_priv, 10, GEN_FOREVER)) plane_ctl |= cnl_plane_ctl_flip(rotation & DRM_MODE_REFLECT_MASK); @@ -3658,7 +3658,7 @@ u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state, struct intel_plane *plane = to_intel_plane(plane_state->base.plane); u32 plane_color_ctl = 0; - if (INTEL_GEN(dev_priv) < 11) { + if (GT_GEN_RANGE(dev_priv, 0, 10)) { plane_color_ctl |= PLANE_COLOR_PIPE_GAMMA_ENABLE; plane_color_ctl |= PLANE_COLOR_PIPE_CSC_ENABLE; } @@ -3722,7 +3722,7 @@ __intel_display_resume(struct drm_device *dev, static bool gpu_reset_clobbers_display(struct drm_i915_private *dev_priv) { return intel_has_gpu_reset(dev_priv) && - INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv); + GT_GEN_RANGE(dev_priv, 0, 4) && !IS_G4X(dev_priv); } void intel_prepare_reset(struct drm_i915_private *dev_priv) @@ -3858,7 +3858,7 @@ static void intel_update_pipe_config(const struct intel_crtc_state *old_crtc_sta (new_crtc_state->pipe_src_h - 1)); /* on skylake this is done by detaching scalers */ - if (INTEL_GEN(dev_priv) >= 9) { + if (GT_GEN_RANGE(dev_priv, 9, GEN_FOREVER)) { skl_detach_scalers(new_crtc_state); if (new_crtc_state->pch_pfit.enabled) @@ -4823,7 +4823,7 @@ skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach, * Once NV12 is enabled, handle it here while allocating scaler * for NV12. */ - if (INTEL_GEN(dev_priv) >= 9 && crtc_state->base.enable && + if (GT_GEN_RANGE(dev_priv, 9, GEN_FOREVER) && crtc_state->base.enable && need_scaler && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { DRM_DEBUG_KMS("Pipe/Plane scaling not supported with IF-ID mode\n"); return -EINVAL; @@ -5653,7 +5653,7 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config, if (pipe_config->shared_dpll) intel_enable_shared_dpll(pipe_config); - if (INTEL_GEN(dev_priv) >= 11) + if (GT_GEN_RANGE(dev_priv, 11, GEN_FOREVER)) icl_map_plls_to_ports(crtc, pipe_config, old_state); intel_encoders_pre_enable(crtc, pipe_config, old_state); @@ -5692,7 +5692,7 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config, if (psl_clkgate_wa) glk_pipe_scaler_clock_gating_wa(dev_priv, pipe, true); - if (INTEL_GEN(dev_priv) >= 9) + if (GT_GEN_RANGE(dev_priv, 9, GEN_FOREVER)) skylake_pfit_enable(pipe_config); else ironlake_pfit_enable(pipe_config); @@ -5707,7 +5707,7 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config, * Display WA #1153: enable hardware to bypass the alpha math * and rounding for per-pixel values 00 and 0xff */ - if (INTEL_GEN(dev_priv) >= 11) { + if (GT_GEN_RANGE(dev_priv, 11, GEN_FOREVER)) { pipe_chicken = I915_READ(PIPE_CHICKEN(pipe)); if (!(pipe_chicken & PER_PIXEL_ALPHA_BYPASS_EN)) I915_WRITE_FW(PIPE_CHICKEN(pipe), @@ -5721,7 +5721,7 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config, if (dev_priv->display.initial_watermarks != NULL) dev_priv->display.initial_watermarks(old_intel_state, pipe_config); - if (INTEL_GEN(dev_priv) >= 11) + if (GT_GEN_RANGE(dev_priv, 11, GEN_FOREVER)) icl_pipe_mbus_enable(intel_crtc); /* XXX: Do the pipe assertions at the right place for BXT DSI. */ @@ -5850,14 +5850,14 @@ static void haswell_crtc_disable(struct intel_crtc_state *old_crtc_state, if (!transcoder_is_dsi(cpu_transcoder)) intel_ddi_disable_transcoder_func(old_crtc_state); - if (INTEL_GEN(dev_priv) >= 9) + if (GT_GEN_RANGE(dev_priv, 9, GEN_FOREVER)) skylake_scaler_disable(intel_crtc); else ironlake_pfit_disable(old_crtc_state); intel_encoders_post_disable(crtc, old_crtc_state, old_state); - if (INTEL_GEN(dev_priv) >= 11) + if (GT_GEN_RANGE(dev_priv, 11, GEN_FOREVER)) icl_unmap_plls_to_ports(crtc, old_crtc_state, old_state); intel_encoders_post_pll_disable(crtc, old_crtc_state, old_state); @@ -6524,7 +6524,7 @@ static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc) const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); /* GDG double wide on either pipe, otherwise pipe A only */ - return INTEL_GEN(dev_priv) < 4 && + return GT_GEN_RANGE(dev_priv, 0, 3) && (crtc->pipe == PIPE_A || IS_I915G(dev_priv)); } @@ -6584,7 +6584,7 @@ static int intel_crtc_compute_config(struct intel_crtc *crtc, const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; int clock_limit = dev_priv->max_dotclk_freq; - if (INTEL_GEN(dev_priv) < 4) { + if (GT_GEN_RANGE(dev_priv, 0, 3)) { clock_limit = dev_priv->max_cdclk_freq * 9 / 10; /* @@ -6639,8 +6639,8 @@ static int intel_crtc_compute_config(struct intel_crtc *crtc, /* Cantiga+ cannot handle modes with a hsync front porch of 0. * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw. */ - if ((INTEL_GEN(dev_priv) > 4 || IS_G4X(dev_priv)) && - adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay) + if ((GT_GEN_RANGE(dev_priv, 5, GEN_FOREVER) || IS_G4X(dev_priv)) && + adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay) return -EINVAL; intel_crtc_compute_pixel_rate(pipe_config); @@ -6808,7 +6808,7 @@ static void intel_cpu_transcoder_set_m_n(const struct intel_crtc_state *crtc_sta enum pipe pipe = crtc->pipe; enum transcoder transcoder = crtc_state->cpu_transcoder; - if (INTEL_GEN(dev_priv) >= 5) { + if (GT_GEN_RANGE(dev_priv, 5, GEN_FOREVER)) { I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m); I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n); I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m); @@ -7202,7 +7202,7 @@ static void i9xx_compute_dpll(struct intel_crtc *crtc, dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; break; } - if (INTEL_GEN(dev_priv) >= 4) + if (GT_GEN_RANGE(dev_priv, 4, GEN_FOREVER)) dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT); if (crtc_state->sdvo_tv_clock) @@ -7216,7 +7216,7 @@ static void i9xx_compute_dpll(struct intel_crtc *crtc, dpll |= DPLL_VCO_ENABLE; crtc_state->dpll_hw_state.dpll = dpll; - if (INTEL_GEN(dev_priv) >= 4) { + if (GT_GEN_RANGE(dev_priv, 4, GEN_FOREVER)) { u32 dpll_md = (crtc_state->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT; crtc_state->dpll_hw_state.dpll_md = dpll_md; @@ -7290,7 +7290,7 @@ static void intel_set_pipe_timings(const struct intel_crtc_state *crtc_state) vsyncshift += adjusted_mode->crtc_htotal; } - if (INTEL_GEN(dev_priv) > 3) + if (GT_GEN_RANGE(dev_priv, 4, GEN_FOREVER)) I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift); I915_WRITE(HTOTAL(cpu_transcoder), @@ -7450,7 +7450,7 @@ static void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state) } if (crtc_state->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) { - if (INTEL_GEN(dev_priv) < 4 || + if (GT_GEN_RANGE(dev_priv, 0, 3) || intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION; else @@ -7661,7 +7661,7 @@ static void i9xx_get_pfit_config(struct intel_crtc *crtc, struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); uint32_t tmp; - if (INTEL_GEN(dev_priv) <= 3 && + if (GT_GEN_RANGE(dev_priv, 0, 3) && (IS_I830(dev_priv) || !IS_MOBILE(dev_priv))) return; @@ -7670,7 +7670,7 @@ static void i9xx_get_pfit_config(struct intel_crtc *crtc, return; /* Check whether the pfit is attached to our pipe. */ - if (INTEL_GEN(dev_priv) < 4) { + if (GT_GEN_RANGE(dev_priv, 0, 3)) { if (crtc->pipe != PIPE_B) return; } else { @@ -7741,7 +7741,7 @@ i9xx_get_initial_plane_config(struct intel_crtc *crtc, val = I915_READ(DSPCNTR(i9xx_plane)); - if (INTEL_GEN(dev_priv) >= 4) { + if (GT_GEN_RANGE(dev_priv, 4, GEN_FOREVER)) { if (val & DISPPLANE_TILED) { plane_config->tiling = I915_TILING_X; fb->modifier = I915_FORMAT_MOD_X_TILED; @@ -7755,7 +7755,7 @@ i9xx_get_initial_plane_config(struct intel_crtc *crtc, if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { offset = I915_READ(DSPOFFSET(i9xx_plane)); base = I915_READ(DSPSURF(i9xx_plane)) & 0xfffff000; - } else if (INTEL_GEN(dev_priv) >= 4) { + } else if (GT_GEN_RANGE(dev_priv, 4, GEN_FOREVER)) { if (plane_config->tiling) offset = I915_READ(DSPTILEOFF(i9xx_plane)); else @@ -7827,7 +7827,7 @@ static void intel_get_crtc_ycbcr_config(struct intel_crtc *crtc, pipe_config->lspcon_downsampling = false; - if (IS_BROADWELL(dev_priv) || INTEL_GEN(dev_priv) >= 9) { + if (IS_BROADWELL(dev_priv) || GT_GEN_RANGE(dev_priv, 9, GEN_FOREVER)) { u32 tmp = I915_READ(PIPEMISC(crtc->pipe)); if (tmp & PIPEMISC_OUTPUT_COLORSPACE_YUV) { @@ -7839,7 +7839,7 @@ static void intel_get_crtc_ycbcr_config(struct intel_crtc *crtc, if (!blend) output = INTEL_OUTPUT_FORMAT_INVALID; else if (!(IS_GEMINILAKE(dev_priv) || - INTEL_GEN(dev_priv) >= 10)) + GT_GEN_RANGE(dev_priv, 10, GEN_FOREVER))) output = INTEL_OUTPUT_FORMAT_INVALID; else output = INTEL_OUTPUT_FORMAT_YCBCR420; @@ -7905,7 +7905,7 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc, (tmp & PIPECONF_COLOR_RANGE_SELECT)) pipe_config->limited_color_range = true; - if (INTEL_GEN(dev_priv) < 4) + if (GT_GEN_RANGE(dev_priv, 0, 3)) pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE; intel_get_pipe_timings(crtc, pipe_config); @@ -7913,7 +7913,7 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc, i9xx_get_pfit_config(crtc, pipe_config); - if (INTEL_GEN(dev_priv) >= 4) { + if (GT_GEN_RANGE(dev_priv, 4, GEN_FOREVER)) { /* No way to read it out on pipes B and C */ if (IS_CHERRYVIEW(dev_priv) && crtc->pipe != PIPE_A) tmp = dev_priv->chv_dpll_md[crtc->pipe]; @@ -8472,7 +8472,7 @@ static void haswell_set_pipemisc(const struct intel_crtc_state *crtc_state) struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev); - if (IS_BROADWELL(dev_priv) || INTEL_GEN(dev_priv) >= 9) { + if (IS_BROADWELL(dev_priv) || GT_GEN_RANGE(dev_priv, 9, GEN_FOREVER)) { u32 val = 0; switch (crtc_state->pipe_bpp) { @@ -8705,7 +8705,7 @@ static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc, struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); enum pipe pipe = crtc->pipe; - if (INTEL_GEN(dev_priv) >= 5) { + if (GT_GEN_RANGE(dev_priv, 5, GEN_FOREVER)) { m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder)); m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder)); m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder)) @@ -8814,12 +8814,12 @@ skylake_get_initial_plane_config(struct intel_crtc *crtc, val = I915_READ(PLANE_CTL(pipe, plane_id)); - if (INTEL_GEN(dev_priv) >= 11) + if (GT_GEN_RANGE(dev_priv, 11, GEN_FOREVER)) pixel_format = val & ICL_PLANE_CTL_FORMAT_MASK; else pixel_format = val & PLANE_CTL_FORMAT_MASK; - if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) { + if (GT_GEN_RANGE(dev_priv, 10, GEN_FOREVER) || IS_GEMINILAKE(dev_priv)) { alpha = I915_READ(PLANE_COLOR_CTL(pipe, plane_id)); alpha &= PLANE_COLOR_ALPHA_MASK; } else { @@ -9499,7 +9499,7 @@ static void haswell_get_ddi_port_state(struct intel_crtc *crtc, * DDI E. So just check whether this pipe is wired to DDI E and whether * the PCH transcoder is on. */ - if (INTEL_GEN(dev_priv) < 9 && + if (GT_GEN_RANGE(dev_priv, 0, 8) && (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) { pipe_config->has_pch_encoder = true; @@ -9553,7 +9553,7 @@ static bool haswell_get_pipe_config(struct intel_crtc *crtc, power_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe); if (intel_display_power_get_if_enabled(dev_priv, power_domain)) { power_domain_mask |= BIT_ULL(power_domain); - if (INTEL_GEN(dev_priv) >= 9) + if (GT_GEN_RANGE(dev_priv, 9, GEN_FOREVER)) skylake_get_pfit_config(crtc, pipe_config); else ironlake_get_pfit_config(crtc, pipe_config); @@ -9868,14 +9868,14 @@ static u32 i9xx_cursor_ctl(const struct intel_crtc_state *crtc_state, if (GT_GEN(dev_priv, 6) || IS_IVYBRIDGE(dev_priv)) cntl |= MCURSOR_TRICKLE_FEED_DISABLE; - if (INTEL_GEN(dev_priv) <= 10) { + if (GT_GEN_RANGE(dev_priv, 0, 10)) { cntl |= MCURSOR_GAMMA_ENABLE; if (HAS_DDI(dev_priv)) cntl |= MCURSOR_PIPE_CSC_ENABLE; } - if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv)) + if (GT_GEN_RANGE(dev_priv, 0, 4) && !IS_G4X(dev_priv)) cntl |= MCURSOR_PIPE_SELECT(crtc->pipe); switch (plane_state->base.crtc_w) { @@ -10080,7 +10080,7 @@ static bool i9xx_cursor_get_hw_state(struct intel_plane *plane, ret = val & MCURSOR_MODE; - if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv)) + if (GT_GEN_RANGE(dev_priv, 5, GEN_FOREVER) || IS_G4X(dev_priv)) *pipe = plane->pipe; else *pipe = (val & MCURSOR_PIPE_SELECT_MASK) >> @@ -10580,7 +10580,7 @@ int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_crtc_stat struct drm_framebuffer *fb = plane_state->fb; int ret; - if (INTEL_GEN(dev_priv) >= 9 && plane->id != PLANE_CURSOR) { + if (GT_GEN_RANGE(dev_priv, 9, GEN_FOREVER) && plane->id != PLANE_CURSOR) { ret = skl_update_scaler_plane( to_intel_crtc_state(crtc_state), to_intel_plane_state(plane_state)); @@ -10629,21 +10629,21 @@ int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_crtc_stat turn_off, turn_on, mode_changed); if (turn_on) { - if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv)) + if (GT_GEN_RANGE(dev_priv, 0, 4) && !IS_G4X(dev_priv)) pipe_config->update_wm_pre = true; /* must disable cxsr around plane enable/disable */ if (plane->id != PLANE_CURSOR) pipe_config->disable_cxsr = true; } else if (turn_off) { - if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv)) + if (GT_GEN_RANGE(dev_priv, 0, 4) && !IS_G4X(dev_priv)) pipe_config->update_wm_post = true; /* must disable cxsr around plane enable/disable */ if (plane->id != PLANE_CURSOR) pipe_config->disable_cxsr = true; } else if (intel_wm_need_update(&plane->base, plane_state)) { - if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv)) { + if (GT_GEN_RANGE(dev_priv, 0, 4) && !IS_G4X(dev_priv)) { /* FIXME bollocks */ pipe_config->update_wm_pre = true; pipe_config->update_wm_post = true; @@ -10755,7 +10755,7 @@ static int icl_check_nv12_planes(struct intel_crtc_state *crtc_state) struct intel_plane_state *plane_state; int i; - if (INTEL_GEN(dev_priv) < 11) + if (GT_GEN_RANGE(dev_priv, 0, 10)) return 0; /* @@ -10878,11 +10878,11 @@ static int intel_crtc_atomic_check(struct drm_crtc *crtc, return ret; } } else if (dev_priv->display.compute_intermediate_wm) { - if (HAS_PCH_SPLIT(dev_priv) && INTEL_GEN(dev_priv) < 9) + if (HAS_PCH_SPLIT(dev_priv) && GT_GEN_RANGE(dev_priv, 0, 8)) pipe_config->wm.ilk.intermediate = pipe_config->wm.ilk.optimal; } - if (INTEL_GEN(dev_priv) >= 9) { + if (GT_GEN_RANGE(dev_priv, 9, GEN_FOREVER)) { if (mode_changed) ret = skl_update_scaler_crtc(pipe_config); @@ -10978,7 +10978,7 @@ compute_baseline_pipe_bpp(struct intel_crtc *crtc, if ((IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))) bpp = 10*3; - else if (INTEL_GEN(dev_priv) >= 5) + else if (GT_GEN_RANGE(dev_priv, 5, GEN_FOREVER)) bpp = 12*3; else bpp = 8*3; @@ -11134,7 +11134,7 @@ static void intel_dump_pipe_config(struct intel_crtc *crtc, pipe_config->pipe_src_w, pipe_config->pipe_src_h, pipe_config->pixel_rate); - if (INTEL_GEN(dev_priv) >= 9) + if (GT_GEN_RANGE(dev_priv, 9, GEN_FOREVER)) DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n", crtc->num_scalers, pipe_config->scaler_state.scaler_users, @@ -11175,7 +11175,7 @@ static void intel_dump_pipe_config(struct intel_crtc *crtc, plane->base.id, plane->name, fb->base.id, fb->width, fb->height, drm_get_format_name(fb->format->format, &format_name)); - if (INTEL_GEN(dev_priv) >= 9) + if (GT_GEN_RANGE(dev_priv, 9, GEN_FOREVER)) DRM_DEBUG_KMS("\tscaler:%d src %dx%d+%d+%d dst %dx%d+%d+%d\n", state->scaler_id, state->base.src.x1 >> 16, @@ -11664,7 +11664,7 @@ intel_pipe_config_compare(struct drm_i915_private *dev_priv, PIPE_CONF_CHECK_I(lane_count); PIPE_CONF_CHECK_X(lane_lat_optim_mask); - if (INTEL_GEN(dev_priv) < 8) { + if (GT_GEN_RANGE(dev_priv, 0, 7)) { PIPE_CONF_CHECK_M_N(dp_m_n); if (current_config->has_drrs) @@ -11691,7 +11691,7 @@ intel_pipe_config_compare(struct drm_i915_private *dev_priv, PIPE_CONF_CHECK_I(pixel_multiplier); PIPE_CONF_CHECK_I(output_format); PIPE_CONF_CHECK_BOOL(has_hdmi_sink); - if ((INTEL_GEN(dev_priv) < 8 && !IS_HASWELL(dev_priv)) || + if ((GT_GEN_RANGE(dev_priv, 0, 7) && !IS_HASWELL(dev_priv)) || IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) PIPE_CONF_CHECK_BOOL(limited_color_range); @@ -11717,7 +11717,7 @@ intel_pipe_config_compare(struct drm_i915_private *dev_priv, PIPE_CONF_CHECK_X(gmch_pfit.control); /* pfit ratios are autocomputed by the hw on gen4+ */ - if (INTEL_GEN(dev_priv) < 4) + if (GT_GEN_RANGE(dev_priv, 0, 3)) PIPE_CONF_CHECK_X(gmch_pfit.pgm_ratios); PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits); @@ -11773,7 +11773,7 @@ intel_pipe_config_compare(struct drm_i915_private *dev_priv, PIPE_CONF_CHECK_X(dsi_pll.ctrl); PIPE_CONF_CHECK_X(dsi_pll.div); - if (IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5) + if (IS_G4X(dev_priv) || GT_GEN_RANGE(dev_priv, 5, GEN_FOREVER)) PIPE_CONF_CHECK_I(pipe_bpp); PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock); @@ -11823,7 +11823,7 @@ static void verify_wm_state(struct drm_crtc *crtc, const enum pipe pipe = intel_crtc->pipe; int plane, level, max_level = ilk_wm_max_level(dev_priv); - if (INTEL_GEN(dev_priv) < 9 || !new_state->active) + if (GT_GEN_RANGE(dev_priv, 0, 8) || !new_state->active) return; skl_pipe_wm_get_hw_state(crtc, &hw_wm); @@ -11832,7 +11832,7 @@ static void verify_wm_state(struct drm_crtc *crtc, skl_ddb_get_hw_state(dev_priv, &hw_ddb); sw_ddb = &dev_priv->wm.skl_hw.ddb; - if (INTEL_GEN(dev_priv) >= 11) + if (GT_GEN_RANGE(dev_priv, 11, GEN_FOREVER)) if (hw_ddb.enabled_slices != sw_ddb->enabled_slices) DRM_ERROR("mismatch in DBUF Slices (expected %u, got %u)\n", sw_ddb->enabled_slices, @@ -12665,7 +12665,7 @@ static void skl_update_crtcs(struct drm_atomic_state *state) entries[i] = &to_intel_crtc_state(old_crtc_state)->wm.skl.ddb; /* If 2nd DBuf slice required, enable it here */ - if (INTEL_GEN(dev_priv) >= 11 && required_slices > hw_enabled_slices) + if (GT_GEN_RANGE(dev_priv, 11, GEN_FOREVER) && required_slices > hw_enabled_slices) icl_dbuf_slices_update(dev_priv, required_slices); /* @@ -12720,7 +12720,7 @@ static void skl_update_crtcs(struct drm_atomic_state *state) } while (progress); /* If 2nd DBuf slice is no more required disable it */ - if (INTEL_GEN(dev_priv) >= 11 && required_slices < hw_enabled_slices) + if (GT_GEN_RANGE(dev_priv, 11, GEN_FOREVER) && required_slices < hw_enabled_slices) icl_dbuf_slices_update(dev_priv, required_slices); } @@ -13034,7 +13034,7 @@ static int intel_atomic_commit(struct drm_device *dev, * FIXME doing watermarks and fb cleanup from a vblank worker * (assuming we had any) would solve these problems. */ - if (INTEL_GEN(dev_priv) < 9 && state->legacy_cursor_update) { + if (GT_GEN_RANGE(dev_priv, 0, 8) && state->legacy_cursor_update) { struct intel_crtc_state *new_crtc_state; struct intel_crtc *crtc; int i; @@ -13143,7 +13143,7 @@ static void add_rps_boost_after_vblank(struct drm_crtc *crtc, if (!dma_fence_is_i915(fence)) return; - if (INTEL_GEN(to_i915(crtc->dev)) < 6) + if (GT_GEN_RANGE(to_i915(crtc->dev), 0, 5)) return; if (drm_crtc_vblank_get(crtc)) @@ -13374,7 +13374,7 @@ skl_max_scale(const struct intel_crtc_state *crtc_state, crtc_clock = crtc_state->base.adjusted_mode.crtc_clock; max_dotclk = to_intel_atomic_state(crtc_state->base.state)->cdclk.logical.cdclk; - if (IS_GEMINILAKE(dev_priv) || INTEL_GEN(dev_priv) >= 10) + if (IS_GEMINILAKE(dev_priv) || GT_GEN_RANGE(dev_priv, 10, GEN_FOREVER)) max_dotclk *= 2; if (WARN_ON_ONCE(!crtc_clock || max_dotclk < crtc_clock)) @@ -13423,7 +13423,7 @@ static void intel_begin_crtc_commit(struct drm_crtc *crtc, if (intel_cstate->update_pipe) intel_update_pipe_config(old_intel_cstate, intel_cstate); - else if (INTEL_GEN(dev_priv) >= 9) + else if (GT_GEN_RANGE(dev_priv, 9, GEN_FOREVER)) skl_detach_scalers(intel_cstate); out: @@ -13711,7 +13711,7 @@ static bool i9xx_plane_has_fbc(struct drm_i915_private *dev_priv, else if (IS_IVYBRIDGE(dev_priv)) return i9xx_plane == PLANE_A || i9xx_plane == PLANE_B || i9xx_plane == PLANE_C; - else if (INTEL_GEN(dev_priv) >= 4) + else if (GT_GEN_RANGE(dev_priv, 4, GEN_FOREVER)) return i9xx_plane == PLANE_A || i9xx_plane == PLANE_B; else return i9xx_plane == PLANE_A; @@ -13729,7 +13729,7 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe) int num_formats; int ret; - if (INTEL_GEN(dev_priv) >= 9) + if (GT_GEN_RANGE(dev_priv, 9, GEN_FOREVER)) return skl_universal_plane_create(dev_priv, pipe, PLANE_PRIMARY); @@ -13742,7 +13742,7 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe) * On gen2/3 only plane A can do FBC, but the panel fitter and LVDS * port is hooked to pipe B. Hence we want plane A feeding pipe B. */ - if (HAS_FBC(dev_priv) && INTEL_GEN(dev_priv) < 4) + if (HAS_FBC(dev_priv) && GT_GEN_RANGE(dev_priv, 0, 3)) plane->i9xx_plane = (enum i9xx_plane_id) !pipe; else plane->i9xx_plane = (enum i9xx_plane_id) pipe; @@ -13756,7 +13756,7 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe) fbc->possible_framebuffer_bits |= plane->frontbuffer_bit; } - if (INTEL_GEN(dev_priv) >= 4) { + if (GT_GEN_RANGE(dev_priv, 4, GEN_FOREVER)) { formats = i965_primary_formats; num_formats = ARRAY_SIZE(i965_primary_formats); modifiers = i9xx_format_modifiers; @@ -13784,7 +13784,7 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe) possible_crtcs = BIT(pipe); - if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv)) + if (GT_GEN_RANGE(dev_priv, 5, GEN_FOREVER) || IS_G4X(dev_priv)) ret = drm_universal_plane_init(&dev_priv->drm, &plane->base, possible_crtcs, plane_funcs, formats, num_formats, modifiers, @@ -13804,14 +13804,14 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe) supported_rotations = DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180 | DRM_MODE_REFLECT_X; - } else if (INTEL_GEN(dev_priv) >= 4) { + } else if (GT_GEN_RANGE(dev_priv, 4, GEN_FOREVER)) { supported_rotations = DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180; } else { supported_rotations = DRM_MODE_ROTATE_0; } - if (INTEL_GEN(dev_priv) >= 4) + if (GT_GEN_RANGE(dev_priv, 4, GEN_FOREVER)) drm_plane_create_rotation_property(&plane->base, DRM_MODE_ROTATE_0, supported_rotations); @@ -13875,7 +13875,7 @@ intel_cursor_plane_create(struct drm_i915_private *dev_priv, if (ret) goto fail; - if (INTEL_GEN(dev_priv) >= 4) + if (GT_GEN_RANGE(dev_priv, 4, GEN_FOREVER)) drm_plane_create_rotation_property(&cursor->base, DRM_MODE_ROTATE_0, DRM_MODE_ROTATE_0 | @@ -13975,7 +13975,7 @@ static int intel_crtc_init(struct drm_i915_private *dev_priv, enum pipe pipe) dev_priv->pipe_to_crtc_mapping[pipe] != NULL); dev_priv->pipe_to_crtc_mapping[pipe] = intel_crtc; - if (INTEL_GEN(dev_priv) < 9) { + if (GT_GEN_RANGE(dev_priv, 0, 8)) { enum i9xx_plane_id i9xx_plane = primary->i9xx_plane; BUG_ON(i9xx_plane >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) || @@ -14052,7 +14052,7 @@ static bool has_edp_a(struct drm_i915_private *dev_priv) static bool intel_crt_present(struct drm_i915_private *dev_priv) { - if (INTEL_GEN(dev_priv) >= 9) + if (GT_GEN_RANGE(dev_priv, 9, GEN_FOREVER)) return false; if (IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv)) @@ -14436,7 +14436,7 @@ static int intel_framebuffer_init(struct intel_framebuffer *intel_fb, } /* fall through */ case I915_FORMAT_MOD_Y_TILED: - if (INTEL_GEN(dev_priv) < 9) { + if (GT_GEN_RANGE(dev_priv, 0, 8)) { DRM_DEBUG_KMS("Unsupported tiling 0x%llx!\n", mode_cmd->modifier[0]); goto err; @@ -14455,7 +14455,7 @@ static int intel_framebuffer_init(struct intel_framebuffer *intel_fb, * gen2/3 display engine uses the fence if present, * so the tiling mode must match the fb modifier exactly. */ - if (INTEL_GEN(dev_priv) < 4 && + if (GT_GEN_RANGE(dev_priv, 0, 3) && tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) { DRM_DEBUG_KMS("tiling_mode must match fb modifier exactly on gen2/3\n"); goto err; @@ -14489,7 +14489,7 @@ static int intel_framebuffer_init(struct intel_framebuffer *intel_fb, case DRM_FORMAT_ARGB8888: break; case DRM_FORMAT_XRGB1555: - if (INTEL_GEN(dev_priv) > 3) { + if (GT_GEN_RANGE(dev_priv, 4, GEN_FOREVER)) { DRM_DEBUG_KMS("unsupported pixel format: %s\n", drm_get_format_name(mode_cmd->pixel_format, &format_name)); goto err; @@ -14497,7 +14497,7 @@ static int intel_framebuffer_init(struct intel_framebuffer *intel_fb, break; case DRM_FORMAT_ABGR8888: if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) && - INTEL_GEN(dev_priv) < 9) { + GT_GEN_RANGE(dev_priv, 0, 8)) { DRM_DEBUG_KMS("unsupported pixel format: %s\n", drm_get_format_name(mode_cmd->pixel_format, &format_name)); goto err; @@ -14506,7 +14506,7 @@ static int intel_framebuffer_init(struct intel_framebuffer *intel_fb, case DRM_FORMAT_XBGR8888: case DRM_FORMAT_XRGB2101010: case DRM_FORMAT_XBGR2101010: - if (INTEL_GEN(dev_priv) < 4) { + if (GT_GEN_RANGE(dev_priv, 0, 3)) { DRM_DEBUG_KMS("unsupported pixel format: %s\n", drm_get_format_name(mode_cmd->pixel_format, &format_name)); goto err; @@ -14523,14 +14523,14 @@ static int intel_framebuffer_init(struct intel_framebuffer *intel_fb, case DRM_FORMAT_UYVY: case DRM_FORMAT_YVYU: case DRM_FORMAT_VYUY: - if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv)) { + if (GT_GEN_RANGE(dev_priv, 0, 4) && !IS_G4X(dev_priv)) { DRM_DEBUG_KMS("unsupported pixel format: %s\n", drm_get_format_name(mode_cmd->pixel_format, &format_name)); goto err; } break; case DRM_FORMAT_NV12: - if (INTEL_GEN(dev_priv) < 9 || IS_SKYLAKE(dev_priv) || + if (GT_GEN_RANGE(dev_priv, 0, 8) || IS_SKYLAKE(dev_priv) || IS_BROXTON(dev_priv)) { DRM_DEBUG_KMS("unsupported pixel format: %s\n", drm_get_format_name(mode_cmd->pixel_format, @@ -14677,13 +14677,13 @@ intel_mode_valid(struct drm_device *dev, DRM_MODE_FLAG_CLKDIV2)) return MODE_BAD; - if (INTEL_GEN(dev_priv) >= 9 || + if (GT_GEN_RANGE(dev_priv, 9, GEN_FOREVER) || IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) { hdisplay_max = 8192; /* FDI max 4096 handled elsewhere */ vdisplay_max = 4096; htotal_max = 8192; vtotal_max = 8192; - } else if (INTEL_GEN(dev_priv) >= 3) { + } else if (GT_GEN_RANGE(dev_priv, 3, GEN_FOREVER)) { hdisplay_max = 4096; vdisplay_max = 4096; htotal_max = 8192; @@ -14730,7 +14730,7 @@ void intel_init_display_hooks(struct drm_i915_private *dev_priv) { intel_init_cdclk_hooks(dev_priv); - if (INTEL_GEN(dev_priv) >= 9) { + if (GT_GEN_RANGE(dev_priv, 9, GEN_FOREVER)) { dev_priv->display.get_pipe_config = haswell_get_pipe_config; dev_priv->display.get_initial_plane_config = skylake_get_initial_plane_config; @@ -14809,7 +14809,7 @@ void intel_init_display_hooks(struct drm_i915_private *dev_priv) dev_priv->display.fdi_link_train = hsw_fdi_link_train; } - if (INTEL_GEN(dev_priv) >= 9) + if (GT_GEN_RANGE(dev_priv, 9, GEN_FOREVER)) dev_priv->display.update_crtcs = skl_update_crtcs; else dev_priv->display.update_crtcs = intel_update_crtcs; @@ -15237,7 +15237,7 @@ intel_sanitize_plane_mapping(struct drm_i915_private *dev_priv) { struct intel_crtc *crtc; - if (INTEL_GEN(dev_priv) >= 4) + if (GT_GEN_RANGE(dev_priv, 4, GEN_FOREVER)) return; for_each_intel_crtc(&dev_priv->drm, crtc) { @@ -15398,7 +15398,7 @@ static void intel_sanitize_encoder(struct intel_encoder *encoder) /* notify opregion of the sanitized encoder state */ intel_opregion_notify_encoder(encoder, connector && has_active_crtc); - if (INTEL_GEN(dev_priv) >= 11) + if (GT_GEN_RANGE(dev_priv, 11, GEN_FOREVER)) icl_sanitize_encoder_pll_mapping(encoder); } @@ -15724,7 +15724,7 @@ intel_modeset_setup_hw_state(struct drm_device *dev, } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { vlv_wm_get_hw_state(dev); vlv_wm_sanitize(dev_priv); - } else if (INTEL_GEN(dev_priv) >= 9) { + } else if (GT_GEN_RANGE(dev_priv, 9, GEN_FOREVER)) { skl_wm_get_hw_state(dev); } else if (HAS_PCH_SPLIT(dev_priv)) { ilk_wm_get_hw_state(dev); @@ -15842,7 +15842,7 @@ void intel_modeset_cleanup(struct drm_device *dev) */ int intel_modeset_vga_set_state(struct drm_i915_private *dev_priv, bool state) { - unsigned reg = INTEL_GEN(dev_priv) >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL; + unsigned reg = GT_GEN_RANGE(dev_priv, 6, GEN_FOREVER) ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL; u16 gmch_ctrl; if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) { @@ -15947,13 +15947,13 @@ intel_display_capture_error_state(struct drm_i915_private *dev_priv) error->plane[i].control = I915_READ(DSPCNTR(i)); error->plane[i].stride = I915_READ(DSPSTRIDE(i)); - if (INTEL_GEN(dev_priv) <= 3) { + if (GT_GEN_RANGE(dev_priv, 0, 3)) { error->plane[i].size = I915_READ(DSPSIZE(i)); error->plane[i].pos = I915_READ(DSPPOS(i)); } - if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv)) + if (GT_GEN_RANGE(dev_priv, 0, 7) && !IS_HASWELL(dev_priv)) error->plane[i].addr = I915_READ(DSPADDR(i)); - if (INTEL_GEN(dev_priv) >= 4) { + if (GT_GEN_RANGE(dev_priv, 4, GEN_FOREVER)) { error->plane[i].surface = I915_READ(DSPSURF(i)); error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i)); } @@ -16018,13 +16018,13 @@ intel_display_print_error_state(struct drm_i915_error_state_buf *m, err_printf(m, "Plane [%d]:\n", i); err_printf(m, " CNTR: %08x\n", error->plane[i].control); err_printf(m, " STRIDE: %08x\n", error->plane[i].stride); - if (INTEL_GEN(dev_priv) <= 3) { + if (GT_GEN_RANGE(dev_priv, 0, 3)) { err_printf(m, " SIZE: %08x\n", error->plane[i].size); err_printf(m, " POS: %08x\n", error->plane[i].pos); } - if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv)) + if (GT_GEN_RANGE(dev_priv, 0, 7) && !IS_HASWELL(dev_priv)) err_printf(m, " ADDR: %08x\n", error->plane[i].addr); - if (INTEL_GEN(dev_priv) >= 4) { + if (GT_GEN_RANGE(dev_priv, 4, GEN_FOREVER)) { err_printf(m, " SURF: %08x\n", error->plane[i].surface); err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset); } diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index 7f6ceb00574f..a554c31ffb70 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -339,7 +339,7 @@ intel_dp_set_source_rates(struct intel_dp *intel_dp) /* This should only be done once */ WARN_ON(intel_dp->source_rates || intel_dp->num_source_rates); - if (INTEL_GEN(dev_priv) >= 10) { + if (GT_GEN_RANGE(dev_priv, 10, GEN_FOREVER)) { source_rates = cnl_rates; size = ARRAY_SIZE(cnl_rates); if (GT_GEN(dev_priv, 10)) @@ -535,7 +535,7 @@ intel_dp_mode_valid(struct drm_connector *connector, * Output bpp is stored in 6.4 format so right shift by 4 to get the * integer value since we support only integer values of bpp. */ - if ((INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) && + if ((GT_GEN_RANGE(dev_priv, 10, GEN_FOREVER) || IS_GEMINILAKE(dev_priv)) && drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd)) { if (intel_dp_is_edp(intel_dp)) { dsc_max_output_bpp = @@ -1549,7 +1549,7 @@ intel_dp_aux_init(struct intel_dp *intel_dp) struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); struct intel_encoder *encoder = &dig_port->base; - if (INTEL_GEN(dev_priv) >= 9) { + if (GT_GEN_RANGE(dev_priv, 9, GEN_FOREVER)) { intel_dp->aux_ch_ctl_reg = skl_aux_ctl_reg; intel_dp->aux_ch_data_reg = skl_aux_data_reg; } else if (HAS_PCH_SPLIT(dev_priv)) { @@ -1560,7 +1560,7 @@ intel_dp_aux_init(struct intel_dp *intel_dp) intel_dp->aux_ch_data_reg = g4x_aux_data_reg; } - if (INTEL_GEN(dev_priv) >= 9) + if (GT_GEN_RANGE(dev_priv, 9, GEN_FOREVER)) intel_dp->get_aux_clock_divider = skl_get_aux_clock_divider; else if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider; @@ -1569,7 +1569,7 @@ intel_dp_aux_init(struct intel_dp *intel_dp) else intel_dp->get_aux_clock_divider = g4x_get_aux_clock_divider; - if (INTEL_GEN(dev_priv) >= 9) + if (GT_GEN_RANGE(dev_priv, 9, GEN_FOREVER)) intel_dp->get_aux_send_ctl = skl_get_aux_send_ctl; else intel_dp->get_aux_send_ctl = g4x_get_aux_send_ctl; @@ -1957,7 +1957,7 @@ intel_dp_compute_config(struct intel_encoder *encoder, intel_fixed_panel_mode(intel_connector->panel.fixed_mode, adjusted_mode); - if (INTEL_GEN(dev_priv) >= 9) { + if (GT_GEN_RANGE(dev_priv, 9, GEN_FOREVER)) { int ret; ret = skl_update_scaler_crtc(pipe_config); @@ -3648,7 +3648,7 @@ intel_dp_set_signal_levels(struct intel_dp *intel_dp) uint32_t signal_levels, mask = 0; uint8_t train_set = intel_dp->train_set[0]; - if (GT_GEN9_LP(dev_priv) || INTEL_GEN(dev_priv) >= 10) { + if (GT_GEN9_LP(dev_priv) || GT_GEN_RANGE(dev_priv, 10, GEN_FOREVER)) { signal_levels = bxt_signal_levels(intel_dp); } else if (HAS_DDI(dev_priv)) { signal_levels = ddi_signal_levels(intel_dp); @@ -3926,7 +3926,7 @@ intel_edp_init_dpcd(struct intel_dp *intel_dp) intel_dp_set_common_rates(intel_dp); /* Read the eDP DSC DPCD registers */ - if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) + if (GT_GEN_RANGE(dev_priv, 10, GEN_FOREVER) || IS_GEMINILAKE(dev_priv)) intel_dp_get_dsc_sink_cap(intel_dp); return true; @@ -5024,7 +5024,7 @@ bool intel_digital_port_connected(struct intel_encoder *encoder) return g4x_digital_port_connected(encoder); } - if (INTEL_GEN(dev_priv) >= 11) + if (GT_GEN_RANGE(dev_priv, 11, GEN_FOREVER)) return icl_digital_port_connected(encoder); else if (GT_GEN(dev_priv, 10) || GT_GEN9_BC(dev_priv)) return spt_digital_port_connected(encoder); @@ -5142,7 +5142,7 @@ intel_dp_detect(struct drm_connector *connector, intel_dp_print_rates(intel_dp); /* Read DP Sink DSC Cap DPCD regs for DP v1.4 */ - if (INTEL_GEN(dev_priv) >= 11) + if (GT_GEN_RANGE(dev_priv, 11, GEN_FOREVER)) intel_dp_get_dsc_sink_cap(intel_dp); drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc, @@ -5720,10 +5720,10 @@ bool intel_dp_is_port_edp(struct drm_i915_private *dev_priv, enum port port) * eDP not supported on g4x. so bail out early just * for a bit extra safety in case the VBT is bonkers. */ - if (INTEL_GEN(dev_priv) < 5) + if (GT_GEN_RANGE(dev_priv, 0, 4)) return false; - if (INTEL_GEN(dev_priv) < 9 && port == PORT_A) + if (GT_GEN_RANGE(dev_priv, 0, 8) && port == PORT_A) return true; return intel_bios_is_port_edp(dev_priv, port); @@ -5741,7 +5741,7 @@ intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connect intel_attach_broadcast_rgb_property(connector); if (HAS_GMCH_DISPLAY(dev_priv)) drm_connector_attach_max_bpc_property(connector, 6, 10); - else if (INTEL_GEN(dev_priv) >= 5) + else if (GT_GEN_RANGE(dev_priv, 5, GEN_FOREVER)) drm_connector_attach_max_bpc_property(connector, 6, 12); if (intel_dp_is_edp(intel_dp)) { @@ -6096,7 +6096,7 @@ static void intel_dp_set_drrs_state(struct drm_i915_private *dev_priv, return; } - if (INTEL_GEN(dev_priv) >= 8 && !IS_CHERRYVIEW(dev_priv)) { + if (GT_GEN_RANGE(dev_priv, 8, GEN_FOREVER) && !IS_CHERRYVIEW(dev_priv)) { switch (index) { case DRRS_HIGH_RR: intel_dp_set_m_n(crtc_state, M1_N1); @@ -6108,7 +6108,7 @@ static void intel_dp_set_drrs_state(struct drm_i915_private *dev_priv, default: DRM_ERROR("Unsupported refreshrate type\n"); } - } else if (INTEL_GEN(dev_priv) > 6) { + } else if (GT_GEN_RANGE(dev_priv, 7, GEN_FOREVER)) { i915_reg_t reg = PIPECONF(crtc_state->cpu_transcoder); u32 val; @@ -6381,7 +6381,7 @@ intel_dp_drrs_init(struct intel_connector *connector, INIT_DELAYED_WORK(&dev_priv->drrs.work, intel_edp_drrs_downclock_work); mutex_init(&dev_priv->drrs.mutex); - if (INTEL_GEN(dev_priv) <= 6) { + if (GT_GEN_RANGE(dev_priv, 0, 6)) { DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n"); return NULL; } diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c index 5d756fdd1e7e..7a6cf48471b4 100644 --- a/drivers/gpu/drm/i915/intel_dpll_mgr.c +++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c @@ -211,7 +211,7 @@ void intel_disable_shared_dpll(const struct intel_crtc_state *crtc_state) unsigned int crtc_mask = drm_crtc_mask(&crtc->base); /* PCH only available on ILK+ */ - if (INTEL_GEN(dev_priv) < 5) + if (GT_GEN_RANGE(dev_priv, 0, 4)) return; if (pll == NULL) @@ -1872,7 +1872,7 @@ static void intel_ddi_pll_init(struct drm_device *dev) { struct drm_i915_private *dev_priv = to_i915(dev); - if (INTEL_GEN(dev_priv) < 9) { + if (GT_GEN_RANGE(dev_priv, 0, 8)) { uint32_t val = I915_READ(LCPLL_CTL); /* @@ -2213,7 +2213,7 @@ int cnl_hdmi_pll_ref_clock(struct drm_i915_private *dev_priv) * For ICL+, the spec states: if reference frequency is 38.4, * use 19.2 because the DPLL automatically divides that by 2. */ - if (INTEL_GEN(dev_priv) >= 11 && ref_clock == 38400) + if (GT_GEN_RANGE(dev_priv, 11, GEN_FOREVER) && ref_clock == 38400) ref_clock = 19200; return ref_clock; diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index 6772e9974751..418ceb9a5e82 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -2237,7 +2237,7 @@ static inline bool icl_is_nv12_y_plane(enum plane_id id) static inline bool icl_is_hdr_plane(struct intel_plane *plane) { - if (INTEL_GEN(to_i915(plane->base.dev)) < 11) + if (GT_GEN_RANGE(to_i915(plane->base.dev), 0, 10)) return false; return plane->id < PLANE_SPRITE2; diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c index 4032a635acb5..fdd6966e5b95 100644 --- a/drivers/gpu/drm/i915/intel_engine_cs.c +++ b/drivers/gpu/drm/i915/intel_engine_cs.c @@ -233,7 +233,7 @@ __intel_engine_context_size(struct drm_i915_private *dev_priv, u8 class) case VIDEO_DECODE_CLASS: case VIDEO_ENHANCEMENT_CLASS: case COPY_ENGINE_CLASS: - if (INTEL_GEN(dev_priv) < 8) + if (GT_GEN_RANGE(dev_priv, 0, 7)) return 0; return GEN8_LR_CONTEXT_OTHER_SIZE; } @@ -730,10 +730,10 @@ u64 intel_engine_get_active_head(const struct intel_engine_cs *engine) struct drm_i915_private *dev_priv = engine->i915; u64 acthd; - if (INTEL_GEN(dev_priv) >= 8) + if (GT_GEN_RANGE(dev_priv, 8, GEN_FOREVER)) acthd = I915_READ64_2x32(RING_ACTHD(engine->mmio_base), RING_ACTHD_UDW(engine->mmio_base)); - else if (INTEL_GEN(dev_priv) >= 4) + else if (GT_GEN_RANGE(dev_priv, 4, GEN_FOREVER)) acthd = I915_READ(RING_ACTHD(engine->mmio_base)); else acthd = I915_READ(ACTHD); @@ -746,7 +746,7 @@ u64 intel_engine_get_last_batch_head(const struct intel_engine_cs *engine) struct drm_i915_private *dev_priv = engine->i915; u64 bbaddr; - if (INTEL_GEN(dev_priv) >= 8) + if (GT_GEN_RANGE(dev_priv, 8, GEN_FOREVER)) bbaddr = I915_READ64_2x32(RING_BBADDR(engine->mmio_base), RING_BBADDR_UDW(engine->mmio_base)); else @@ -762,7 +762,7 @@ int intel_engine_stop_cs(struct intel_engine_cs *engine) const i915_reg_t mode = RING_MI_MODE(base); int err; - if (INTEL_GEN(dev_priv) < 3) + if (GT_GEN_RANGE(dev_priv, 0, 2)) return -ENODEV; GEM_TRACE("%s\n", engine->name); @@ -815,7 +815,7 @@ u32 intel_calculate_mcr_s_ss_select(struct drm_i915_private *dev_priv) if (GT_GEN(dev_priv, 10)) mcr_s_ss_select = GEN8_MCR_SLICE(slice) | GEN8_MCR_SUBSLICE(subslice); - else if (INTEL_GEN(dev_priv) >= 11) + else if (GT_GEN_RANGE(dev_priv, 11, GEN_FOREVER)) mcr_s_ss_select = GEN11_MCR_SLICE(slice) | GEN11_MCR_SUBSLICE(subslice); else @@ -835,7 +835,7 @@ read_subslice_reg(struct drm_i915_private *dev_priv, int slice, uint32_t ret; enum forcewake_domains fw_domains; - if (INTEL_GEN(dev_priv) >= 11) { + if (GT_GEN_RANGE(dev_priv, 11, GEN_FOREVER)) { mcr_slice_subslice_mask = GEN11_MCR_SLICE_MASK | GEN11_MCR_SUBSLICE_MASK; mcr_slice_subslice_select = GEN11_MCR_SLICE(slice) | @@ -950,7 +950,7 @@ static bool ring_is_idle(struct intel_engine_cs *engine) idle = false; /* No bit for gen2, so assume the CS parser is idle */ - if (INTEL_GEN(dev_priv) > 2 && !(I915_READ_MODE(engine) & MODE_IDLE)) + if (GT_GEN_RANGE(dev_priv, 3, GEN_FOREVER) && !(I915_READ_MODE(engine) & MODE_IDLE)) idle = false; intel_runtime_pm_put(dev_priv); @@ -1297,13 +1297,13 @@ static void intel_engine_print_registers(const struct intel_engine_cs *engine, drm_printf(m, "\tRING_CTL: 0x%08x%s\n", I915_READ(RING_CTL(engine->mmio_base)), I915_READ(RING_CTL(engine->mmio_base)) & (RING_WAIT | RING_WAIT_SEMAPHORE) ? " [waiting]" : ""); - if (INTEL_GEN(engine->i915) > 2) { + if (GT_GEN_RANGE(engine->i915, 3, GEN_FOREVER)) { drm_printf(m, "\tRING_MODE: 0x%08x%s\n", I915_READ(RING_MI_MODE(engine->mmio_base)), I915_READ(RING_MI_MODE(engine->mmio_base)) & (MODE_IDLE) ? " [idle]" : ""); } - if (INTEL_GEN(dev_priv) >= 6) { + if (GT_GEN_RANGE(dev_priv, 6, GEN_FOREVER)) { drm_printf(m, "\tRING_IMR: %08x\n", I915_READ_IMR(engine)); } @@ -1323,16 +1323,16 @@ static void intel_engine_print_registers(const struct intel_engine_cs *engine, addr = intel_engine_get_last_batch_head(engine); drm_printf(m, "\tBBADDR: 0x%08x_%08x\n", upper_32_bits(addr), lower_32_bits(addr)); - if (INTEL_GEN(dev_priv) >= 8) + if (GT_GEN_RANGE(dev_priv, 8, GEN_FOREVER)) addr = I915_READ64_2x32(RING_DMA_FADD(engine->mmio_base), RING_DMA_FADD_UDW(engine->mmio_base)); - else if (INTEL_GEN(dev_priv) >= 4) + else if (GT_GEN_RANGE(dev_priv, 4, GEN_FOREVER)) addr = I915_READ(RING_DMA_FADD(engine->mmio_base)); else addr = I915_READ(DMA_FADD_I8XX); drm_printf(m, "\tDMA_FADDR: 0x%08x_%08x\n", upper_32_bits(addr), lower_32_bits(addr)); - if (INTEL_GEN(dev_priv) >= 4) { + if (GT_GEN_RANGE(dev_priv, 4, GEN_FOREVER)) { drm_printf(m, "\tIPEIR: 0x%08x\n", I915_READ(RING_IPEIR(engine->mmio_base))); drm_printf(m, "\tIPEHR: 0x%08x\n", @@ -1396,7 +1396,7 @@ static void intel_engine_print_registers(const struct intel_engine_cs *engine, } drm_printf(m, "\t\tHW active? 0x%x\n", execlists->active); rcu_read_unlock(); - } else if (INTEL_GEN(dev_priv) > 6) { + } else if (GT_GEN_RANGE(dev_priv, 7, GEN_FOREVER)) { drm_printf(m, "\tPP_DIR_BASE: 0x%08x\n", I915_READ(RING_PP_DIR_BASE(engine))); drm_printf(m, "\tPP_DIR_BASE_READ: 0x%08x\n", diff --git a/drivers/gpu/drm/i915/intel_fbc.c b/drivers/gpu/drm/i915/intel_fbc.c index 7ed976ada979..9d0d6e440fa6 100644 --- a/drivers/gpu/drm/i915/intel_fbc.c +++ b/drivers/gpu/drm/i915/intel_fbc.c @@ -48,7 +48,7 @@ static inline bool fbc_supported(struct drm_i915_private *dev_priv) static inline bool no_fbc_on_multiple_pipes(struct drm_i915_private *dev_priv) { - return INTEL_GEN(dev_priv) <= 3; + return GT_GEN_RANGE(dev_priv, 0, 3); } /* @@ -86,7 +86,7 @@ static int intel_fbc_calculate_cfb_size(struct drm_i915_private *dev_priv, intel_fbc_get_plane_source_size(cache, NULL, &lines); if (GT_GEN(dev_priv, 7)) lines = min(lines, 2048); - else if (INTEL_GEN(dev_priv) >= 8) + else if (GT_GEN_RANGE(dev_priv, 8, GEN_FOREVER)) lines = min(lines, 2560); /* Hardware needs the full buffer stride, not just the active area. */ @@ -347,7 +347,7 @@ static void gen7_fbc_activate(struct drm_i915_private *dev_priv) static bool intel_fbc_hw_is_active(struct drm_i915_private *dev_priv) { - if (INTEL_GEN(dev_priv) >= 5) + if (GT_GEN_RANGE(dev_priv, 5, GEN_FOREVER)) return ilk_fbc_is_active(dev_priv); else if (IS_GM45(dev_priv)) return g4x_fbc_is_active(dev_priv); @@ -361,9 +361,9 @@ static void intel_fbc_hw_activate(struct drm_i915_private *dev_priv) fbc->active = true; - if (INTEL_GEN(dev_priv) >= 7) + if (GT_GEN_RANGE(dev_priv, 7, GEN_FOREVER)) gen7_fbc_activate(dev_priv); - else if (INTEL_GEN(dev_priv) >= 5) + else if (GT_GEN_RANGE(dev_priv, 5, GEN_FOREVER)) ilk_fbc_activate(dev_priv); else if (IS_GM45(dev_priv)) g4x_fbc_activate(dev_priv); @@ -377,7 +377,7 @@ static void intel_fbc_hw_deactivate(struct drm_i915_private *dev_priv) fbc->active = false; - if (INTEL_GEN(dev_priv) >= 5) + if (GT_GEN_RANGE(dev_priv, 5, GEN_FOREVER)) ilk_fbc_deactivate(dev_priv); else if (IS_GM45(dev_priv)) g4x_fbc_deactivate(dev_priv); @@ -470,7 +470,7 @@ static int find_compression_threshold(struct drm_i915_private *dev_priv, ret = i915_gem_stolen_insert_node_in_range(dev_priv, node, size >>= 1, 4096, 0, end); - if (ret && INTEL_GEN(dev_priv) <= 4) { + if (ret && GT_GEN_RANGE(dev_priv, 0, 4)) { return 0; } else if (ret) { compression_threshold <<= 1; @@ -503,7 +503,7 @@ static int intel_fbc_alloc_cfb(struct intel_crtc *crtc) fbc->threshold = ret; - if (INTEL_GEN(dev_priv) >= 5) + if (GT_GEN_RANGE(dev_priv, 5, GEN_FOREVER)) I915_WRITE(ILK_DPFC_CB_BASE, fbc->compressed_fb.start); else if (IS_GM45(dev_priv)) { I915_WRITE(DPFC_CB_BASE, fbc->compressed_fb.start); @@ -626,10 +626,10 @@ static bool intel_fbc_hw_tracking_covers_screen(struct intel_crtc *crtc) struct intel_fbc *fbc = &dev_priv->fbc; unsigned int effective_w, effective_h, max_w, max_h; - if (INTEL_GEN(dev_priv) >= 8 || IS_HASWELL(dev_priv)) { + if (GT_GEN_RANGE(dev_priv, 8, GEN_FOREVER) || IS_HASWELL(dev_priv)) { max_w = 4096; max_h = 4096; - } else if (IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5) { + } else if (IS_G4X(dev_priv) || GT_GEN_RANGE(dev_priv, 5, GEN_FOREVER)) { max_w = 4096; max_h = 2048; } else { @@ -734,7 +734,7 @@ static bool intel_fbc_can_activate(struct intel_crtc *crtc) fbc->no_fbc_reason = "framebuffer not tiled or fenced"; return false; } - if (INTEL_GEN(dev_priv) <= 4 && !IS_G4X(dev_priv) && + if (GT_GEN_RANGE(dev_priv, 0, 4) && !IS_G4X(dev_priv) && cache->plane.rotation != DRM_MODE_ROTATE_0) { fbc->no_fbc_reason = "rotation unsupported"; return false; @@ -1275,7 +1275,7 @@ static int intel_sanitize_fbc_option(struct drm_i915_private *dev_priv) if (!HAS_FBC(dev_priv)) return 0; - if (IS_BROADWELL(dev_priv) || INTEL_GEN(dev_priv) >= 9) + if (IS_BROADWELL(dev_priv) || GT_GEN_RANGE(dev_priv, 9, GEN_FOREVER)) return 1; return 0; @@ -1321,7 +1321,7 @@ void intel_fbc_init(struct drm_i915_private *dev_priv) } /* This value was pulled out of someone's hat */ - if (INTEL_GEN(dev_priv) <= 4 && !IS_GM45(dev_priv)) + if (GT_GEN_RANGE(dev_priv, 0, 4) && !IS_GM45(dev_priv)) I915_WRITE(FBC_CONTROL, 500 << FBC_CTL_INTERVAL_SHIFT); /* We still don't have any sort of hardware state readout for FBC, so diff --git a/drivers/gpu/drm/i915/intel_fifo_underrun.c b/drivers/gpu/drm/i915/intel_fifo_underrun.c index 06f69bca0ff4..ff76da50153d 100644 --- a/drivers/gpu/drm/i915/intel_fifo_underrun.c +++ b/drivers/gpu/drm/i915/intel_fifo_underrun.c @@ -264,7 +264,7 @@ static bool __intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev, ironlake_set_fifo_underrun_reporting(dev, pipe, enable); else if (GT_GEN(dev_priv, 7)) ivybridge_set_fifo_underrun_reporting(dev, pipe, enable, old); - else if (INTEL_GEN(dev_priv) >= 8) + else if (GT_GEN_RANGE(dev_priv, 8, GEN_FOREVER)) broadwell_set_fifo_underrun_reporting(dev, pipe, enable); return old; diff --git a/drivers/gpu/drm/i915/intel_hangcheck.c b/drivers/gpu/drm/i915/intel_hangcheck.c index 84867ca2cc0c..64cfbc83ad8e 100644 --- a/drivers/gpu/drm/i915/intel_hangcheck.c +++ b/drivers/gpu/drm/i915/intel_hangcheck.c @@ -97,7 +97,7 @@ semaphore_waits_for(struct intel_engine_cs *engine, u32 *seqno) * ringbuffer itself. */ head = I915_READ_HEAD(engine) & HEAD_ADDR; - backwards = (INTEL_GEN(dev_priv) >= 8) ? 5 : 4; + backwards = (GT_GEN_RANGE(dev_priv, 8, GEN_FOREVER)) ? 5 : 4; vaddr = (void __iomem *)engine->buffer->vaddr; for (i = backwards; i; --i) { diff --git a/drivers/gpu/drm/i915/intel_hdcp.c b/drivers/gpu/drm/i915/intel_hdcp.c index 1bf487f94254..726bab95c004 100644 --- a/drivers/gpu/drm/i915/intel_hdcp.c +++ b/drivers/gpu/drm/i915/intel_hdcp.c @@ -768,7 +768,7 @@ static void intel_hdcp_prop_work(struct work_struct *work) bool is_hdcp_supported(struct drm_i915_private *dev_priv, enum port port) { /* PORT E doesn't have HDCP, and PORT F is disabled */ - return ((INTEL_GEN(dev_priv) >= 8 || IS_HASWELL(dev_priv)) && + return ((GT_GEN_RANGE(dev_priv, 8, GEN_FOREVER) || IS_HASWELL(dev_priv)) && !IS_CHERRYVIEW(dev_priv) && port < PORT_E); } diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c index f954c2883f92..98527b905955 100644 --- a/drivers/gpu/drm/i915/intel_hdmi.c +++ b/drivers/gpu/drm/i915/intel_hdmi.c @@ -1476,11 +1476,11 @@ static int intel_hdmi_source_max_tmds_clock(struct intel_encoder *encoder) &dev_priv->vbt.ddi_port_info[encoder->port]; int max_tmds_clock; - if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) + if (GT_GEN_RANGE(dev_priv, 10, GEN_FOREVER) || IS_GEMINILAKE(dev_priv)) max_tmds_clock = 594000; - else if (INTEL_GEN(dev_priv) >= 8 || IS_HASWELL(dev_priv)) + else if (GT_GEN_RANGE(dev_priv, 8, GEN_FOREVER) || IS_HASWELL(dev_priv)) max_tmds_clock = 300000; - else if (INTEL_GEN(dev_priv) >= 5) + else if (GT_GEN_RANGE(dev_priv, 5, GEN_FOREVER)) max_tmds_clock = 225000; else max_tmds_clock = 165000; @@ -1579,7 +1579,7 @@ intel_hdmi_mode_valid(struct drm_connector *connector, true, force_dvi); /* if we can't do 8,12bpc we may still be able to do 10bpc */ - if (status != MODE_OK && INTEL_GEN(dev_priv) >= 11) + if (status != MODE_OK && GT_GEN_RANGE(dev_priv, 11, GEN_FOREVER)) status = hdmi_port_clock_valid(hdmi, clock * 5 / 4, true, force_dvi); } @@ -1602,7 +1602,7 @@ static bool hdmi_deep_color_possible(const struct intel_crtc_state *crtc_state, if (HAS_GMCH_DISPLAY(dev_priv)) return false; - if (bpc == 10 && INTEL_GEN(dev_priv) < 11) + if (bpc == 10 && GT_GEN_RANGE(dev_priv, 0, 10)) return false; if (crtc_state->pipe_bpp <= 8*3) @@ -1797,7 +1797,7 @@ bool intel_hdmi_compute_config(struct intel_encoder *encoder, pipe_config->lane_count = 4; - if (scdc->scrambling.supported && (INTEL_GEN(dev_priv) >= 10 || + if (scdc->scrambling.supported && (GT_GEN_RANGE(dev_priv, 10, GEN_FOREVER) || IS_GEMINILAKE(dev_priv))) { if (scdc->scrambling.low_rates) pipe_config->hdmi_scrambling = true; @@ -2399,7 +2399,7 @@ void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port, connector->doublescan_allowed = 0; connector->stereo_allowed = 1; - if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) + if (GT_GEN_RANGE(dev_priv, 10, GEN_FOREVER) || IS_GEMINILAKE(dev_priv)) connector->ycbcr_420_allowed = true; intel_hdmi->ddc_bus = intel_hdmi_ddc_pin(dev_priv, port); diff --git a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu/drm/i915/intel_i2c.c index 86d898844a97..f85eaa57fa35 100644 --- a/drivers/gpu/drm/i915/intel_i2c.c +++ b/drivers/gpu/drm/i915/intel_i2c.c @@ -362,7 +362,7 @@ gmbus_wait_idle(struct drm_i915_private *dev_priv) static inline unsigned int gmbus_max_xfer_size(struct drm_i915_private *dev_priv) { - return INTEL_GEN(dev_priv) >= 9 ? GEN9_GMBUS_BYTE_COUNT_MAX : + return GT_GEN_RANGE(dev_priv, 9, GEN_FOREVER) ? GEN9_GMBUS_BYTE_COUNT_MAX : GMBUS_BYTE_COUNT_MAX; } diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c index d8b53a0eac09..fd24c3939f46 100644 --- a/drivers/gpu/drm/i915/intel_lrc.c +++ b/drivers/gpu/drm/i915/intel_lrc.c @@ -239,7 +239,7 @@ intel_lr_context_descriptor_update(struct i915_gem_context *ctx, * Consider updating oa_get_render_ctx_id in i915_perf.c when changing * anything below. */ - if (INTEL_GEN(ctx->i915) >= 11) { + if (GT_GEN_RANGE(ctx->i915, 11, GEN_FOREVER)) { GEM_BUG_ON(ctx->hw_id >= BIT(GEN11_SW_CTX_ID_WIDTH)); desc |= (u64)ctx->hw_id << GEN11_SW_CTX_ID_SHIFT; /* bits 37-47 */ @@ -1587,7 +1587,7 @@ static void enable_execlists(struct intel_engine_cs *engine) * deeper FIFO it's not needed and it's not worth adding * more statements to the irq handler to support it. */ - if (INTEL_GEN(dev_priv) >= 11) + if (GT_GEN_RANGE(dev_priv, 11, GEN_FOREVER)) I915_WRITE(RING_MODE_GEN7(engine), _MASKED_BIT_DISABLE(GEN11_GFX_DISABLE_LEGACY_MODE)); else @@ -2167,7 +2167,7 @@ logical_ring_default_vfuncs(struct intel_engine_cs *engine) engine->set_default_submission = intel_execlists_set_default_submission; - if (INTEL_GEN(engine->i915) < 11) { + if (GT_GEN_RANGE(engine->i915, 0, 10)) { engine->irq_enable = gen8_logical_ring_enable_irq; engine->irq_disable = gen8_logical_ring_disable_irq; } else { @@ -2186,7 +2186,7 @@ logical_ring_default_irqs(struct intel_engine_cs *engine) { unsigned int shift = 0; - if (INTEL_GEN(engine->i915) < 11) { + if (GT_GEN_RANGE(engine->i915, 0, 10)) { const u8 irq_shifts[] = { [RCS] = GEN8_RCS_IRQ_SHIFT, [BCS] = GEN8_BCS_IRQ_SHIFT, @@ -2286,7 +2286,7 @@ int logical_render_ring_init(struct intel_engine_cs *engine) engine->irq_keep_mask |= GT_RENDER_L3_PARITY_ERROR_INTERRUPT; /* Override some for render ring. */ - if (INTEL_GEN(dev_priv) >= 9) + if (GT_GEN_RANGE(dev_priv, 9, GEN_FOREVER)) engine->init_hw = gen9_init_render_ring; else engine->init_hw = gen8_init_render_ring; @@ -2340,7 +2340,7 @@ make_rpcs(struct drm_i915_private *dev_priv) * No explicit RPCS request is needed to ensure full * slice/subslice/EU enablement prior to Gen9. */ - if (INTEL_GEN(dev_priv) < 9) + if (GT_GEN_RANGE(dev_priv, 0, 8)) return 0; /* @@ -2384,7 +2384,7 @@ make_rpcs(struct drm_i915_private *dev_priv) if (INTEL_INFO(dev_priv)->sseu.has_slice_pg) { u32 mask, val = slices; - if (INTEL_GEN(dev_priv) >= 11) { + if (GT_GEN_RANGE(dev_priv, 11, GEN_FOREVER)) { mask = GEN11_RPCS_S_CNT_MASK; val <<= GEN11_RPCS_S_CNT_SHIFT; } else { @@ -2483,7 +2483,7 @@ static void execlists_init_reg_state(u32 *regs, CTX_REG(regs, CTX_CONTEXT_CONTROL, RING_CONTEXT_CONTROL(engine), _MASKED_BIT_DISABLE(CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT) | _MASKED_BIT_ENABLE(CTX_CTRL_INHIBIT_SYN_CTX_SWITCH)); - if (INTEL_GEN(dev_priv) < 11) { + if (GT_GEN_RANGE(dev_priv, 0, 10)) { regs[CTX_CONTEXT_CONTROL + 1] |= _MASKED_BIT_DISABLE(CTX_CTRL_ENGINE_CTX_SAVE_INHIBIT | CTX_CTRL_RS_CTX_ENABLE); @@ -2555,7 +2555,7 @@ static void execlists_init_reg_state(u32 *regs, } regs[CTX_END] = MI_BATCH_BUFFER_END; - if (INTEL_GEN(dev_priv) >= 10) + if (GT_GEN_RANGE(dev_priv, 10, GEN_FOREVER)) regs[CTX_END] |= BIT(0); } @@ -2610,7 +2610,7 @@ populate_lr_context(struct i915_gem_context *ctx, if (!engine->default_state) regs[CTX_CONTEXT_CONTROL + 1] |= _MASKED_BIT_ENABLE(CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT); - if (ctx == ctx->i915->preempt_context && INTEL_GEN(engine->i915) < 11) + if (ctx == ctx->i915->preempt_context && GT_GEN_RANGE(engine->i915, 0, 10)) regs[CTX_CONTEXT_CONTROL + 1] |= _MASKED_BIT_ENABLE(CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT | CTX_CTRL_ENGINE_CTX_SAVE_INHIBIT); diff --git a/drivers/gpu/drm/i915/intel_lvds.c b/drivers/gpu/drm/i915/intel_lvds.c index 79fa6b09a8db..968aa3a86350 100644 --- a/drivers/gpu/drm/i915/intel_lvds.c +++ b/drivers/gpu/drm/i915/intel_lvds.c @@ -129,12 +129,12 @@ static void intel_lvds_get_config(struct intel_encoder *encoder, pipe_config->base.adjusted_mode.flags |= flags; - if (INTEL_GEN(dev_priv) < 5) + if (GT_GEN_RANGE(dev_priv, 0, 4)) pipe_config->gmch_pfit.lvds_border_bits = tmp & LVDS_BORDER_ENABLE; /* gen2/3 store dither state in pfit control, needs to match */ - if (INTEL_GEN(dev_priv) < 4) { + if (GT_GEN_RANGE(dev_priv, 0, 3)) { tmp = I915_READ(PFIT_CONTROL); pipe_config->gmch_pfit.control |= tmp & PANEL_8TO6_DITHER_ENABLE; @@ -179,7 +179,7 @@ static void intel_lvds_pps_get_hw_state(struct drm_i915_private *dev_priv, /* Convert from 100ms to 100us units */ pps->t4 = val * 1000; - if (INTEL_GEN(dev_priv) <= 4 && + if (GT_GEN_RANGE(dev_priv, 0, 4) && pps->t1_t2 == 0 && pps->t5 == 0 && pps->t3 == 0 && pps->tx == 0) { DRM_DEBUG_KMS("Panel power timings uninitialized, " "setting defaults\n"); @@ -393,7 +393,7 @@ static bool intel_lvds_compute_config(struct intel_encoder *intel_encoder, unsigned int lvds_bpp; /* Should never happen!! */ - if (INTEL_GEN(dev_priv) < 4 && intel_crtc->pipe == 0) { + if (GT_GEN_RANGE(dev_priv, 0, 3) && intel_crtc->pipe == 0) { DRM_ERROR("Can't support LVDS on pipe A\n"); return false; } @@ -810,7 +810,7 @@ static bool intel_lvds_supported(struct drm_i915_private *dev_priv) * Otherwise LVDS was only attached to mobile products, * except for the inglorious 830gm */ - if (INTEL_GEN(dev_priv) <= 4 && + if (GT_GEN_RANGE(dev_priv, 0, 4) && IS_MOBILE(dev_priv) && !IS_I830(dev_priv)) return true; diff --git a/drivers/gpu/drm/i915/intel_mocs.c b/drivers/gpu/drm/i915/intel_mocs.c index 6b9076fd5836..e3168732f90f 100644 --- a/drivers/gpu/drm/i915/intel_mocs.c +++ b/drivers/gpu/drm/i915/intel_mocs.c @@ -188,7 +188,7 @@ static bool get_mocs_settings(struct drm_i915_private *dev_priv, table->table = broxton_mocs_table; result = true; } else { - WARN_ONCE(INTEL_GEN(dev_priv) >= 9, + WARN_ONCE(GT_GEN_RANGE(dev_priv, 9, GEN_FOREVER), "Platform that should have a MOCS table does not.\n"); } diff --git a/drivers/gpu/drm/i915/intel_overlay.c b/drivers/gpu/drm/i915/intel_overlay.c index c8eddf941762..66d4228968c9 100644 --- a/drivers/gpu/drm/i915/intel_overlay.c +++ b/drivers/gpu/drm/i915/intel_overlay.c @@ -897,7 +897,7 @@ static void update_pfit_vscale_ratio(struct intel_overlay *overlay) /* XXX: This is not the same logic as in the xorg driver, but more in * line with the intel documentation for the i965 */ - if (INTEL_GEN(dev_priv) >= 4) { + if (GT_GEN_RANGE(dev_priv, 4, GEN_FOREVER)) { /* on i965 use the PGM reg to read out the autoscaler values */ ratio = I915_READ(PFIT_PGM_RATIOS) >> PFIT_VERT_SCALE_SHIFT_965; } else { diff --git a/drivers/gpu/drm/i915/intel_panel.c b/drivers/gpu/drm/i915/intel_panel.c index 78d5b9da3a02..8de6d1dcfe82 100644 --- a/drivers/gpu/drm/i915/intel_panel.c +++ b/drivers/gpu/drm/i915/intel_panel.c @@ -326,7 +326,7 @@ void intel_gmch_panel_fitting(struct intel_crtc *intel_crtc, break; case DRM_MODE_SCALE_ASPECT: /* Scale but preserve the aspect ratio */ - if (INTEL_GEN(dev_priv) >= 4) + if (GT_GEN_RANGE(dev_priv, 4, GEN_FOREVER)) i965_scale_aspect(pipe_config, &pfit_control); else i9xx_scale_aspect(pipe_config, &pfit_control, @@ -340,7 +340,7 @@ void intel_gmch_panel_fitting(struct intel_crtc *intel_crtc, if (pipe_config->pipe_src_h != adjusted_mode->crtc_vdisplay || pipe_config->pipe_src_w != adjusted_mode->crtc_hdisplay) { pfit_control |= PFIT_ENABLE; - if (INTEL_GEN(dev_priv) >= 4) + if (GT_GEN_RANGE(dev_priv, 4, GEN_FOREVER)) pfit_control |= PFIT_SCALING_AUTO; else pfit_control |= (VERT_AUTO_SCALE | @@ -356,7 +356,7 @@ void intel_gmch_panel_fitting(struct intel_crtc *intel_crtc, /* 965+ wants fuzzy fitting */ /* FIXME: handle multiple panels by failing gracefully */ - if (INTEL_GEN(dev_priv) >= 4) + if (GT_GEN_RANGE(dev_priv, 4, GEN_FOREVER)) pfit_control |= ((intel_crtc->pipe << PFIT_PIPE_SHIFT) | PFIT_FILTER_FUZZY); @@ -367,7 +367,7 @@ void intel_gmch_panel_fitting(struct intel_crtc *intel_crtc, } /* Make sure pre-965 set dither correctly for 18bpp panels. */ - if (INTEL_GEN(dev_priv) < 4 && pipe_config->pipe_bpp == 18) + if (GT_GEN_RANGE(dev_priv, 0, 3) && pipe_config->pipe_bpp == 18) pfit_control |= PANEL_8TO6_DITHER_ENABLE; pipe_config->gmch_pfit.control = pfit_control; @@ -481,7 +481,7 @@ static u32 i9xx_get_backlight(struct intel_connector *connector) u32 val; val = I915_READ(BLC_PWM_CTL) & BACKLIGHT_DUTY_CYCLE_MASK; - if (INTEL_GEN(dev_priv) < 4) + if (GT_GEN_RANGE(dev_priv, 0, 3)) val >>= 1; if (panel->backlight.combination_mode) { diff --git a/drivers/gpu/drm/i915/intel_pipe_crc.c b/drivers/gpu/drm/i915/intel_pipe_crc.c index a426978b233d..597e52bc15e8 100644 --- a/drivers/gpu/drm/i915/intel_pipe_crc.c +++ b/drivers/gpu/drm/i915/intel_pipe_crc.c @@ -429,7 +429,7 @@ static int get_new_crc_ctl_reg(struct drm_i915_private *dev_priv, { if (GT_GEN(dev_priv, 2)) return i8xx_pipe_crc_ctl_reg(source, val); - else if (INTEL_GEN(dev_priv) < 5) + else if (GT_GEN_RANGE(dev_priv, 0, 4)) return i9xx_pipe_crc_ctl_reg(dev_priv, pipe, source, val); else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) return vlv_pipe_crc_ctl_reg(dev_priv, pipe, source, val); @@ -546,7 +546,7 @@ intel_is_valid_crc_source(struct drm_i915_private *dev_priv, { if (GT_GEN(dev_priv, 2)) return i8xx_crc_source_valid(dev_priv, source); - else if (INTEL_GEN(dev_priv) < 5) + else if (GT_GEN_RANGE(dev_priv, 0, 4)) return i9xx_crc_source_valid(dev_priv, source); else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) return vlv_crc_source_valid(dev_priv, source); diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 3a321600bb78..e721e3e80daf 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -2573,9 +2573,9 @@ static uint32_t ilk_compute_fbc_wm(const struct intel_crtc_state *cstate, static unsigned int ilk_display_fifo_size(const struct drm_i915_private *dev_priv) { - if (INTEL_GEN(dev_priv) >= 8) + if (GT_GEN_RANGE(dev_priv, 8, GEN_FOREVER)) return 3072; - else if (INTEL_GEN(dev_priv) >= 7) + else if (GT_GEN_RANGE(dev_priv, 7, GEN_FOREVER)) return 768; else return 512; @@ -2585,10 +2585,10 @@ static unsigned int ilk_plane_wm_reg_max(const struct drm_i915_private *dev_priv, int level, bool is_sprite) { - if (INTEL_GEN(dev_priv) >= 8) + if (GT_GEN_RANGE(dev_priv, 8, GEN_FOREVER)) /* BDW primary/sprite plane watermarks */ return level == 0 ? 255 : 2047; - else if (INTEL_GEN(dev_priv) >= 7) + else if (GT_GEN_RANGE(dev_priv, 7, GEN_FOREVER)) /* IVB/HSW primary/sprite plane watermarks */ return level == 0 ? 127 : 1023; else if (!is_sprite) @@ -2602,7 +2602,7 @@ ilk_plane_wm_reg_max(const struct drm_i915_private *dev_priv, static unsigned int ilk_cursor_wm_reg_max(const struct drm_i915_private *dev_priv, int level) { - if (INTEL_GEN(dev_priv) >= 7) + if (GT_GEN_RANGE(dev_priv, 7, GEN_FOREVER)) return level == 0 ? 63 : 255; else return level == 0 ? 31 : 63; @@ -2610,7 +2610,7 @@ ilk_cursor_wm_reg_max(const struct drm_i915_private *dev_priv, int level) static unsigned int ilk_fbc_wm_reg_max(const struct drm_i915_private *dev_priv) { - if (INTEL_GEN(dev_priv) >= 8) + if (GT_GEN_RANGE(dev_priv, 8, GEN_FOREVER)) return 31; else return 15; @@ -2639,7 +2639,7 @@ static unsigned int ilk_plane_wm_max(const struct drm_device *dev, * FIFO size is only half of the self * refresh FIFO size on ILK/SNB. */ - if (INTEL_GEN(dev_priv) <= 6) + if (GT_GEN_RANGE(dev_priv, 0, 6)) fifo_size /= 2; } @@ -2800,7 +2800,7 @@ hsw_compute_linetime_wm(const struct intel_crtc_state *cstate) static void intel_read_wm_latency(struct drm_i915_private *dev_priv, uint16_t wm[8]) { - if (INTEL_GEN(dev_priv) >= 9) { + if (GT_GEN_RANGE(dev_priv, 9, GEN_FOREVER)) { uint32_t val; int ret, i; int level, max_level = ilk_wm_max_level(dev_priv); @@ -2894,14 +2894,14 @@ static void intel_read_wm_latency(struct drm_i915_private *dev_priv, wm[2] = (sskpd >> 12) & 0xFF; wm[3] = (sskpd >> 20) & 0x1FF; wm[4] = (sskpd >> 32) & 0x1FF; - } else if (INTEL_GEN(dev_priv) >= 6) { + } else if (GT_GEN_RANGE(dev_priv, 6, GEN_FOREVER)) { uint32_t sskpd = I915_READ(MCH_SSKPD); wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK; wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK; wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK; wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK; - } else if (INTEL_GEN(dev_priv) >= 5) { + } else if (GT_GEN_RANGE(dev_priv, 5, GEN_FOREVER)) { uint32_t mltr = I915_READ(MLTR_ILK); /* ILK primary LP0 latency is 700 ns */ @@ -2932,11 +2932,11 @@ static void intel_fixup_cur_wm_latency(struct drm_i915_private *dev_priv, int ilk_wm_max_level(const struct drm_i915_private *dev_priv) { /* how many WM levels are we expecting */ - if (INTEL_GEN(dev_priv) >= 9) + if (GT_GEN_RANGE(dev_priv, 9, GEN_FOREVER)) return 7; else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) return 4; - else if (INTEL_GEN(dev_priv) >= 6) + else if (GT_GEN_RANGE(dev_priv, 6, GEN_FOREVER)) return 3; else return 2; @@ -2961,7 +2961,7 @@ static void intel_print_wm_latency(struct drm_i915_private *dev_priv, * - latencies are in us on gen9. * - before then, WM1+ latency values are in 0.5us units */ - if (INTEL_GEN(dev_priv) >= 9) + if (GT_GEN_RANGE(dev_priv, 9, GEN_FOREVER)) latency *= 10; else if (level > 0) latency *= 5; @@ -3097,7 +3097,7 @@ static int ilk_compute_pipe_wm(struct intel_crtc_state *cstate) usable_level = max_level; /* ILK/SNB: LP2+ watermarks only w/o sprites */ - if (INTEL_GEN(dev_priv) <= 6 && pipe_wm->sprites_enabled) + if (GT_GEN_RANGE(dev_priv, 0, 6) && pipe_wm->sprites_enabled) usable_level = 1; /* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */ @@ -3242,12 +3242,12 @@ static void ilk_wm_merge(struct drm_device *dev, int last_enabled_level = max_level; /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */ - if ((INTEL_GEN(dev_priv) <= 6 || IS_IVYBRIDGE(dev_priv)) && + if ((GT_GEN_RANGE(dev_priv, 0, 6) || IS_IVYBRIDGE(dev_priv)) && config->num_pipes_active > 1) last_enabled_level = 0; /* ILK: FBC WM must be disabled always */ - merged->fbc_wm_enabled = INTEL_GEN(dev_priv) >= 6; + merged->fbc_wm_enabled = GT_GEN_RANGE(dev_priv, 6, GEN_FOREVER); /* merge each WM1+ level */ for (level = 1; level <= max_level; level++) { @@ -3337,7 +3337,7 @@ static void ilk_compute_wm_results(struct drm_device *dev, if (r->enable) results->wm_lp[wm_lp - 1] |= WM1_LP_SR_EN; - if (INTEL_GEN(dev_priv) >= 8) + if (GT_GEN_RANGE(dev_priv, 8, GEN_FOREVER)) results->wm_lp[wm_lp - 1] |= r->fbc_val << WM1_LP_FBC_SHIFT_BDW; else @@ -3348,7 +3348,7 @@ static void ilk_compute_wm_results(struct drm_device *dev, * Always set WM1S_LP_EN when spr_val != 0, even if the * level is disabled. Doing otherwise could cause underruns. */ - if (INTEL_GEN(dev_priv) <= 6 && r->spr_val) { + if (GT_GEN_RANGE(dev_priv, 0, 6) && r->spr_val) { WARN_ON(wm_lp != 1); results->wm_lp_spr[wm_lp - 1] = WM1S_LP_EN | r->spr_val; } else @@ -3553,7 +3553,7 @@ static void ilk_write_wm_values(struct drm_i915_private *dev_priv, previous->wm_lp_spr[0] != results->wm_lp_spr[0]) I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]); - if (INTEL_GEN(dev_priv) >= 7) { + if (GT_GEN_RANGE(dev_priv, 7, GEN_FOREVER)) { if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1]) I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]); if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2]) @@ -3585,7 +3585,7 @@ static u8 intel_enabled_dbuf_slices_num(struct drm_i915_private *dev_priv) enabled_slices = 1; /* Gen prior to GEN11 have only one DBuf slice */ - if (INTEL_GEN(dev_priv) < 11) + if (GT_GEN_RANGE(dev_priv, 0, 10)) return enabled_slices; if (I915_READ(DBUF_CTL_S2) & DBUF_POWER_STATE) @@ -3611,7 +3611,7 @@ static bool skl_needs_memory_bw_wa(struct intel_atomic_state *state) static bool intel_has_sagv(struct drm_i915_private *dev_priv) { - return (GT_GEN9_BC(dev_priv) || INTEL_GEN(dev_priv) >= 10) && + return (GT_GEN9_BC(dev_priv) || GT_GEN_RANGE(dev_priv, 10, GEN_FOREVER)) && dev_priv->sagv_status != I915_SAGV_NOT_CONTROLLED; } @@ -3786,7 +3786,7 @@ static u16 intel_get_ddb_size(struct drm_i915_private *dev_priv, WARN_ON(ddb_size == 0); - if (INTEL_GEN(dev_priv) < 11) + if (GT_GEN_RANGE(dev_priv, 0, 10)) return ddb_size - 4; /* 4 blocks for bypass path allocation */ adjusted_mode = &cstate->base.adjusted_mode; @@ -3896,7 +3896,7 @@ static void skl_ddb_entry_init_from_hw(struct drm_i915_private *dev_priv, { u16 mask; - if (INTEL_GEN(dev_priv) >= 11) + if (GT_GEN_RANGE(dev_priv, 11, GEN_FOREVER)) mask = ICL_DDB_ENTRY_MASK; else mask = SKL_DDB_ENTRY_MASK; @@ -3936,7 +3936,7 @@ skl_ddb_get_hw_plane_state(struct drm_i915_private *dev_priv, val & PLANE_CTL_ALPHA_MASK); val = I915_READ(PLANE_BUF_CFG(pipe, plane_id)); - if (fourcc == DRM_FORMAT_NV12 && INTEL_GEN(dev_priv) < 11) { + if (fourcc == DRM_FORMAT_NV12 && GT_GEN_RANGE(dev_priv, 0, 10)) { val2 = I915_READ(PLANE_NV12_BUF_CFG(pipe, plane_id)); skl_ddb_entry_init_from_hw(dev_priv, @@ -4112,7 +4112,7 @@ int skl_check_pipe_max_pixel_rate(struct intel_crtc *intel_crtc, crtc_clock = crtc_state->adjusted_mode.crtc_clock; dotclk = to_intel_atomic_state(state)->cdclk.logical.cdclk; - if (IS_GEMINILAKE(dev_priv) || INTEL_GEN(dev_priv) >= 10) + if (IS_GEMINILAKE(dev_priv) || GT_GEN_RANGE(dev_priv, 10, GEN_FOREVER)) dotclk *= 2; pipe_max_pixel_rate = div_round_up_u32_fixed16(dotclk, pipe_downscale); @@ -4394,7 +4394,7 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *cstate, return 0; } - if (INTEL_GEN(dev_priv) < 11) + if (GT_GEN_RANGE(dev_priv, 0, 10)) total_data_rate = skl_get_total_relative_data_rate(cstate, plane_data_rate, @@ -4476,7 +4476,7 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *cstate, uv_plane_blocks += div64_u64(alloc_size * uv_data_rate, total_data_rate); /* Gen11+ uses a separate plane for UV watermarks */ - WARN_ON(INTEL_GEN(dev_priv) >= 11 && uv_plane_blocks); + WARN_ON(GT_GEN_RANGE(dev_priv, 11, GEN_FOREVER) && uv_plane_blocks); if (uv_data_rate) { ddb->uv_plane[pipe][plane_id].start = start; @@ -4509,7 +4509,7 @@ skl_wm_method1(const struct drm_i915_private *dev_priv, uint32_t pixel_rate, wm_intermediate_val = latency * pixel_rate * cpp; ret = div_fixed16(wm_intermediate_val, 1000 * dbuf_block_size); - if (INTEL_GEN(dev_priv) >= 10) + if (GT_GEN_RANGE(dev_priv, 10, GEN_FOREVER)) ret = add_fixed16_u32(ret, 1); return ret; @@ -4626,7 +4626,7 @@ skl_compute_plane_wm_params(const struct drm_i915_private *dev_priv, wp->plane_pixel_rate = skl_adjusted_plane_pixel_rate(cstate, intel_pstate); - if (INTEL_GEN(dev_priv) >= 11 && + if (GT_GEN_RANGE(dev_priv, 11, GEN_FOREVER) && fb->modifier == I915_FORMAT_MOD_Yf_TILED && wp->cpp == 8) wp->dbuf_block_size = 256; else @@ -4661,7 +4661,7 @@ skl_compute_plane_wm_params(const struct drm_i915_private *dev_priv, wp->y_min_scanlines, wp->dbuf_block_size); - if (INTEL_GEN(dev_priv) >= 10) + if (GT_GEN_RANGE(dev_priv, 10, GEN_FOREVER)) interm_pbpl++; wp->plane_blocks_per_line = div_fixed16(interm_pbpl, @@ -4778,7 +4778,7 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv, res_blocks = result_prev->plane_res_b; } - if (INTEL_GEN(dev_priv) >= 11) { + if (GT_GEN_RANGE(dev_priv, 11, GEN_FOREVER)) { if (wp->y_tiled) { uint32_t extra_lines; uint_fixed_16_16_t fp_min_disp_buf_needed; @@ -4910,7 +4910,7 @@ static void skl_compute_transition_wm(const struct intel_crtc_state *cstate, goto exit; /* Transition WM are not recommended by HW team for GEN9 */ - if (INTEL_GEN(dev_priv) <= 9) + if (GT_GEN_RANGE(dev_priv, 0, 9)) goto exit; /* Transition WM don't make any sense if ipc is disabled */ @@ -4918,7 +4918,7 @@ static void skl_compute_transition_wm(const struct intel_crtc_state *cstate, goto exit; trans_min = 14; - if (INTEL_GEN(dev_priv) >= 11) + if (GT_GEN_RANGE(dev_priv, 11, GEN_FOREVER)) trans_min = 4; trans_offset_b = trans_min + trans_amount; @@ -5132,7 +5132,7 @@ static void skl_write_plane_wm(struct intel_crtc *intel_crtc, skl_write_wm_level(dev_priv, PLANE_WM_TRANS(pipe, plane_id), &wm->trans_wm); - if (wm->is_planar && INTEL_GEN(dev_priv) < 11) { + if (wm->is_planar && GT_GEN_RANGE(dev_priv, 0, 10)) { skl_ddb_entry_write(dev_priv, PLANE_BUF_CFG(pipe, plane_id), &ddb->uv_plane[pipe][plane_id]); skl_ddb_entry_write(dev_priv, @@ -5141,7 +5141,7 @@ static void skl_write_plane_wm(struct intel_crtc *intel_crtc, } else { skl_ddb_entry_write(dev_priv, PLANE_BUF_CFG(pipe, plane_id), &ddb->plane[pipe][plane_id]); - if (INTEL_GEN(dev_priv) < 11) + if (GT_GEN_RANGE(dev_priv, 0, 10)) I915_WRITE(PLANE_NV12_BUF_CFG(pipe, plane_id), 0x0); } } @@ -5573,7 +5573,7 @@ static void ilk_program_watermarks(struct drm_i915_private *dev_priv) ilk_wm_merge(dev, &config, &max, &lp_wm_1_2); /* 5/6 split only in single pipe config on IVB+ */ - if (INTEL_GEN(dev_priv) >= 7 && + if (GT_GEN_RANGE(dev_priv, 7, GEN_FOREVER) && config.num_pipes_active == 1 && config.sprites_enabled) { ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_5_6, &max); ilk_wm_merge(dev, &config, &max, &lp_wm_5_6); @@ -6176,7 +6176,7 @@ void ilk_wm_get_hw_state(struct drm_device *dev) hw->wm_lp[2] = I915_READ(WM3_LP_ILK); hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK); - if (INTEL_GEN(dev_priv) >= 7) { + if (GT_GEN_RANGE(dev_priv, 7, GEN_FOREVER)) { hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB); hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB); } @@ -6406,7 +6406,7 @@ static u32 intel_rps_limits(struct drm_i915_private *dev_priv, u8 val) * the hw runs at the minimal clock before selecting the desired * frequency, if the down threshold expires in that window we will not * receive a down interrupt. */ - if (INTEL_GEN(dev_priv) >= 9) { + if (GT_GEN_RANGE(dev_priv, 9, GEN_FOREVER)) { limits = (rps->max_freq_softlimit) << 23; if (val <= rps->min_freq_softlimit) limits |= (rps->min_freq_softlimit) << 14; @@ -6540,7 +6540,7 @@ void intel_rps_mark_interactive(struct drm_i915_private *i915, bool interactive) { struct intel_rps *rps = &i915->gt_pm.rps; - if (INTEL_GEN(i915) < 6) + if (GT_GEN_RANGE(i915, 0, 5)) return; mutex_lock(&rps->power.mutex); @@ -6583,7 +6583,7 @@ static int gen6_set_rps(struct drm_i915_private *dev_priv, u8 val) if (val != rps->cur_freq) { gen6_set_rps_thresholds(dev_priv, val); - if (INTEL_GEN(dev_priv) >= 9) + if (GT_GEN_RANGE(dev_priv, 9, GEN_FOREVER)) I915_WRITE(GEN6_RPNSWREQ, GEN9_FREQUENCY(val)); else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) @@ -6934,7 +6934,7 @@ static void gen6_init_rps_frequencies(struct drm_i915_private *dev_priv) rps->efficient_freq = rps->rp1_freq; if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv) || - GT_GEN9_BC(dev_priv) || INTEL_GEN(dev_priv) >= 10) { + GT_GEN9_BC(dev_priv) || GT_GEN_RANGE(dev_priv, 10, GEN_FOREVER)) { u32 ddcc_status = 0; if (sandybridge_pcode_read(dev_priv, @@ -6947,7 +6947,7 @@ static void gen6_init_rps_frequencies(struct drm_i915_private *dev_priv) rps->max_freq); } - if (GT_GEN9_BC(dev_priv) || INTEL_GEN(dev_priv) >= 10) { + if (GT_GEN9_BC(dev_priv) || GT_GEN_RANGE(dev_priv, 10, GEN_FOREVER)) { /* Store the frequency values in 16.66 MHZ units, which is * the natural hardware unit for SKL */ @@ -7014,7 +7014,7 @@ static void gen9_enable_rc6(struct drm_i915_private *dev_priv) I915_WRITE(GEN6_RC_CONTROL, 0); /* 2b: Program RC6 thresholds.*/ - if (INTEL_GEN(dev_priv) >= 10) { + if (GT_GEN_RANGE(dev_priv, 10, GEN_FOREVER)) { I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16 | 85); I915_WRITE(GEN10_MEDIA_WAKE_RATE_LIMIT, 150); } else if (IS_SKYLAKE(dev_priv)) { @@ -7285,7 +7285,7 @@ static void gen6_update_ring_freq(struct drm_i915_private *dev_priv) min_gpu_freq = rps->min_freq; max_gpu_freq = rps->max_freq; - if (GT_GEN9_BC(dev_priv) || INTEL_GEN(dev_priv) >= 10) { + if (GT_GEN9_BC(dev_priv) || GT_GEN_RANGE(dev_priv, 10, GEN_FOREVER)) { /* Convert GT frequency to 50 HZ units */ min_gpu_freq /= GEN9_FREQ_SCALER; max_gpu_freq /= GEN9_FREQ_SCALER; @@ -7300,13 +7300,13 @@ static void gen6_update_ring_freq(struct drm_i915_private *dev_priv) const int diff = max_gpu_freq - gpu_freq; unsigned int ia_freq = 0, ring_freq = 0; - if (GT_GEN9_BC(dev_priv) || INTEL_GEN(dev_priv) >= 10) { + if (GT_GEN9_BC(dev_priv) || GT_GEN_RANGE(dev_priv, 10, GEN_FOREVER)) { /* * ring_freq = 2 * GT. ring_freq is in 100MHz units * No floor required for ring frequency on SKL. */ ring_freq = gpu_freq; - } else if (INTEL_GEN(dev_priv) >= 8) { + } else if (GT_GEN_RANGE(dev_priv, 8, GEN_FOREVER)) { /* max(2 * GT, DDR). NB: GT is 50MHz units */ ring_freq = max(min_ring_freq, gpu_freq); } else if (IS_HASWELL(dev_priv)) { @@ -8323,7 +8323,7 @@ void intel_init_gt_powersave(struct drm_i915_private *dev_priv) cherryview_init_gt_powersave(dev_priv); else if (IS_VALLEYVIEW(dev_priv)) valleyview_init_gt_powersave(dev_priv); - else if (INTEL_GEN(dev_priv) >= 6) + else if (GT_GEN_RANGE(dev_priv, 6, GEN_FOREVER)) gen6_init_rps_frequencies(dev_priv); /* Derive initial user preferences/limits from the hardware limits */ @@ -8378,7 +8378,7 @@ void intel_cleanup_gt_powersave(struct drm_i915_private *dev_priv) */ void intel_suspend_gt_powersave(struct drm_i915_private *dev_priv) { - if (INTEL_GEN(dev_priv) < 6) + if (GT_GEN_RANGE(dev_priv, 0, 5)) return; /* gen6_rps_idle() will be called later to disable interrupts */ @@ -8390,9 +8390,9 @@ void intel_sanitize_gt_powersave(struct drm_i915_private *dev_priv) dev_priv->gt_pm.rc6.enabled = true; /* force RC6 disabling */ intel_disable_gt_powersave(dev_priv); - if (INTEL_GEN(dev_priv) >= 11) + if (GT_GEN_RANGE(dev_priv, 11, GEN_FOREVER)) gen11_reset_rps_interrupts(dev_priv); - else if (INTEL_GEN(dev_priv) >= 6) + else if (GT_GEN_RANGE(dev_priv, 6, GEN_FOREVER)) gen6_reset_rps_interrupts(dev_priv); } @@ -8415,13 +8415,13 @@ static void intel_disable_rc6(struct drm_i915_private *dev_priv) if (!dev_priv->gt_pm.rc6.enabled) return; - if (INTEL_GEN(dev_priv) >= 9) + if (GT_GEN_RANGE(dev_priv, 9, GEN_FOREVER)) gen9_disable_rc6(dev_priv); else if (IS_CHERRYVIEW(dev_priv)) cherryview_disable_rc6(dev_priv); else if (IS_VALLEYVIEW(dev_priv)) valleyview_disable_rc6(dev_priv); - else if (INTEL_GEN(dev_priv) >= 6) + else if (GT_GEN_RANGE(dev_priv, 6, GEN_FOREVER)) gen6_disable_rc6(dev_priv); dev_priv->gt_pm.rc6.enabled = false; @@ -8434,13 +8434,13 @@ static void intel_disable_rps(struct drm_i915_private *dev_priv) if (!dev_priv->gt_pm.rps.enabled) return; - if (INTEL_GEN(dev_priv) >= 9) + if (GT_GEN_RANGE(dev_priv, 9, GEN_FOREVER)) gen9_disable_rps(dev_priv); else if (IS_CHERRYVIEW(dev_priv)) cherryview_disable_rps(dev_priv); else if (IS_VALLEYVIEW(dev_priv)) valleyview_disable_rps(dev_priv); - else if (INTEL_GEN(dev_priv) >= 6) + else if (GT_GEN_RANGE(dev_priv, 6, GEN_FOREVER)) gen6_disable_rps(dev_priv); else if (IS_IRONLAKE_M(dev_priv)) ironlake_disable_drps(dev_priv); @@ -8483,11 +8483,11 @@ static void intel_enable_rc6(struct drm_i915_private *dev_priv) cherryview_enable_rc6(dev_priv); else if (IS_VALLEYVIEW(dev_priv)) valleyview_enable_rc6(dev_priv); - else if (INTEL_GEN(dev_priv) >= 9) + else if (GT_GEN_RANGE(dev_priv, 9, GEN_FOREVER)) gen9_enable_rc6(dev_priv); else if (IS_BROADWELL(dev_priv)) gen8_enable_rc6(dev_priv); - else if (INTEL_GEN(dev_priv) >= 6) + else if (GT_GEN_RANGE(dev_priv, 6, GEN_FOREVER)) gen6_enable_rc6(dev_priv); dev_priv->gt_pm.rc6.enabled = true; @@ -8506,11 +8506,11 @@ static void intel_enable_rps(struct drm_i915_private *dev_priv) cherryview_enable_rps(dev_priv); } else if (IS_VALLEYVIEW(dev_priv)) { valleyview_enable_rps(dev_priv); - } else if (INTEL_GEN(dev_priv) >= 9) { + } else if (GT_GEN_RANGE(dev_priv, 9, GEN_FOREVER)) { gen9_enable_rps(dev_priv); } else if (IS_BROADWELL(dev_priv)) { gen8_enable_rps(dev_priv); - } else if (INTEL_GEN(dev_priv) >= 6) { + } else if (GT_GEN_RANGE(dev_priv, 6, GEN_FOREVER)) { gen6_enable_rps(dev_priv); } else if (IS_IRONLAKE_M(dev_priv)) { ironlake_enable_drps(dev_priv); @@ -9444,7 +9444,7 @@ void intel_init_pm(struct drm_i915_private *dev_priv) i915_ironlake_get_mem_freq(dev_priv); /* For FIFO watermark updates */ - if (INTEL_GEN(dev_priv) >= 9) { + if (GT_GEN_RANGE(dev_priv, 9, GEN_FOREVER)) { skl_setup_wm_latency(dev_priv); dev_priv->display.initial_watermarks = skl_initial_wm; dev_priv->display.atomic_update_watermarks = skl_atomic_update_crtc_wm; @@ -9590,7 +9590,7 @@ int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val *val = I915_READ_FW(GEN6_PCODE_DATA); I915_WRITE_FW(GEN6_PCODE_DATA, 0); - if (INTEL_GEN(dev_priv) > 6) + if (GT_GEN_RANGE(dev_priv, 7, GEN_FOREVER)) status = gen7_check_mailbox_status(dev_priv); else status = gen6_check_mailbox_status(dev_priv); @@ -9638,7 +9638,7 @@ int sandybridge_pcode_write_timeout(struct drm_i915_private *dev_priv, I915_WRITE_FW(GEN6_PCODE_DATA, 0); - if (INTEL_GEN(dev_priv) > 6) + if (GT_GEN_RANGE(dev_priv, 7, GEN_FOREVER)) status = gen7_check_mailbox_status(dev_priv); else status = gen6_check_mailbox_status(dev_priv); @@ -9767,7 +9767,7 @@ static int chv_freq_opcode(struct drm_i915_private *dev_priv, int val) int intel_gpu_freq(struct drm_i915_private *dev_priv, int val) { - if (INTEL_GEN(dev_priv) >= 9) + if (GT_GEN_RANGE(dev_priv, 9, GEN_FOREVER)) return DIV_ROUND_CLOSEST(val * GT_FREQUENCY_MULTIPLIER, GEN9_FREQ_SCALER); else if (IS_CHERRYVIEW(dev_priv)) @@ -9780,7 +9780,7 @@ int intel_gpu_freq(struct drm_i915_private *dev_priv, int val) int intel_freq_opcode(struct drm_i915_private *dev_priv, int val) { - if (INTEL_GEN(dev_priv) >= 9) + if (GT_GEN_RANGE(dev_priv, 9, GEN_FOREVER)) return DIV_ROUND_CLOSEST(val * GEN9_FREQ_SCALER, GT_FREQUENCY_MULTIPLIER); else if (IS_CHERRYVIEW(dev_priv)) @@ -9926,7 +9926,7 @@ u32 intel_get_cagf(struct drm_i915_private *dev_priv, u32 rpstat) { u32 cagf; - if (INTEL_GEN(dev_priv) >= 9) + if (GT_GEN_RANGE(dev_priv, 9, GEN_FOREVER)) cagf = (rpstat & GEN9_CAGF_MASK) >> GEN9_CAGF_SHIFT; else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT; diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c index cacd54cc00e6..66e66a6e63f6 100644 --- a/drivers/gpu/drm/i915/intel_psr.c +++ b/drivers/gpu/drm/i915/intel_psr.c @@ -91,7 +91,7 @@ void intel_psr_irq_control(struct drm_i915_private *dev_priv, u32 debug) debug_mask = EDP_PSR_POST_EXIT(TRANSCODER_EDP) | EDP_PSR_PRE_ENTRY(TRANSCODER_EDP); - if (INTEL_GEN(dev_priv) >= 8) { + if (GT_GEN_RANGE(dev_priv, 8, GEN_FOREVER)) { mask |= EDP_PSR_ERROR(TRANSCODER_A) | EDP_PSR_ERROR(TRANSCODER_B) | EDP_PSR_ERROR(TRANSCODER_C); @@ -153,7 +153,7 @@ void intel_psr_irq_handler(struct drm_i915_private *dev_priv, u32 psr_iir) enum transcoder cpu_transcoder; ktime_t time_ns = ktime_get(); - if (INTEL_GEN(dev_priv) >= 8) + if (GT_GEN_RANGE(dev_priv, 8, GEN_FOREVER)) transcoders |= BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | BIT(TRANSCODER_C); @@ -175,7 +175,7 @@ void intel_psr_irq_handler(struct drm_i915_private *dev_priv, u32 psr_iir) DRM_DEBUG_KMS("[transcoder %s] PSR exit completed\n", transcoder_name(cpu_transcoder)); - if (INTEL_GEN(dev_priv) >= 9) { + if (GT_GEN_RANGE(dev_priv, 9, GEN_FOREVER)) { u32 val = I915_READ(PSR_EVENT(cpu_transcoder)); bool psr2_enabled = dev_priv->psr.psr2_enabled; @@ -242,7 +242,7 @@ void intel_psr_init_dpcd(struct intel_dp *intel_dp) WARN_ON(dev_priv->psr.dp); dev_priv->psr.dp = intel_dp; - if (INTEL_GEN(dev_priv) >= 9 && + if (GT_GEN_RANGE(dev_priv, 9, GEN_FOREVER) && (intel_dp->psr_dpcd[0] == DP_PSR2_WITH_Y_COORD_IS_SUPPORTED)) { bool y_req = intel_dp->psr_dpcd[1] & DP_PSR2_SU_Y_COORDINATE_REQUIRED; @@ -350,7 +350,7 @@ static void intel_psr_enable_sink(struct intel_dp *intel_dp) if (dev_priv->psr.link_standby) dpcd_val |= DP_PSR_MAIN_LINK_ACTIVE; - if (!dev_priv->psr.psr2_enabled && INTEL_GEN(dev_priv) >= 8) + if (!dev_priv->psr.psr2_enabled && GT_GEN_RANGE(dev_priv, 8, GEN_FOREVER)) dpcd_val |= DP_PSR_CRC_VERIFICATION; drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, dpcd_val); @@ -405,7 +405,7 @@ static void hsw_activate_psr1(struct intel_dp *intel_dp) else val |= EDP_PSR_TP1_TP2_SEL; - if (INTEL_GEN(dev_priv) >= 8) + if (GT_GEN_RANGE(dev_priv, 8, GEN_FOREVER)) val |= EDP_PSR_CRC_ENABLE; val |= I915_READ(EDP_PSR_CTL) & EDP_PSR_RESTORE_PSR_ACTIVE_CTX_MASK; @@ -429,7 +429,7 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp) * mesh at all with our frontbuffer tracking. And the hw alone isn't * good enough. */ val |= EDP_PSR2_ENABLE | EDP_SU_TRACK_ENABLE; - if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) + if (GT_GEN_RANGE(dev_priv, 10, GEN_FOREVER) || IS_GEMINILAKE(dev_priv)) val |= EDP_Y_COORDINATE_ENABLE; val |= EDP_PSR2_FRAME_BEFORE_SU(dev_priv->psr.sink_sync_latency + 1); @@ -463,7 +463,7 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp, if (!dev_priv->psr.sink_psr2_support) return false; - if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) { + if (GT_GEN_RANGE(dev_priv, 10, GEN_FOREVER) || IS_GEMINILAKE(dev_priv)) { psr_max_h = 4096; psr_max_v = 2304; } else if (GT_GEN(dev_priv, 9)) { @@ -543,7 +543,7 @@ static void intel_psr_activate(struct intel_dp *intel_dp) { struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); - if (INTEL_GEN(dev_priv) >= 9) + if (GT_GEN_RANGE(dev_priv, 9, GEN_FOREVER)) WARN_ON(I915_READ(EDP_PSR2_CTL) & EDP_PSR2_ENABLE); WARN_ON(I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE); WARN_ON(dev_priv->psr.active); @@ -594,7 +594,7 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp, EDP_PSR_DEBUG_MASK_LPSP | EDP_PSR_DEBUG_MASK_MAX_SLEEP; - if (INTEL_GEN(dev_priv) < 11) + if (GT_GEN_RANGE(dev_priv, 0, 10)) mask |= EDP_PSR_DEBUG_MASK_DISP_REG_WRITE; I915_WRITE(EDP_PSR_DEBUG, mask); @@ -1063,7 +1063,7 @@ void intel_psr_init(struct drm_i915_private *dev_priv) return; if (i915_modparams.enable_psr == -1) - if (INTEL_GEN(dev_priv) < 9 || !dev_priv->vbt.psr.enable) + if (GT_GEN_RANGE(dev_priv, 0, 8) || !dev_priv->vbt.psr.enable) i915_modparams.enable_psr = 0; /* Set link_standby x link_off defaults */ diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index e2907ae38b7f..c060ae613088 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c @@ -349,7 +349,7 @@ static void ring_setup_phys_status_page(struct intel_engine_cs *engine) u32 addr; addr = lower_32_bits(phys); - if (INTEL_GEN(dev_priv) >= 4) + if (GT_GEN_RANGE(dev_priv, 4, GEN_FOREVER)) addr |= (phys >> 28) & 0xf0; I915_WRITE(HWS_PGA, addr); @@ -390,7 +390,7 @@ static void intel_ring_setup_status_page(struct intel_engine_cs *engine) mmio = RING_HWS_PGA(engine->mmio_base); } - if (INTEL_GEN(dev_priv) >= 6) { + if (GT_GEN_RANGE(dev_priv, 6, GEN_FOREVER)) { u32 mask = ~0u; /* @@ -428,7 +428,7 @@ static bool stop_ring(struct intel_engine_cs *engine) { struct drm_i915_private *dev_priv = engine->i915; - if (INTEL_GEN(dev_priv) > 2) { + if (GT_GEN_RANGE(dev_priv, 3, GEN_FOREVER)) { I915_WRITE_MODE(engine, _MASKED_BIT_ENABLE(STOP_RING)); if (intel_wait_for_register(dev_priv, RING_MI_MODE(engine->mmio_base), @@ -537,7 +537,7 @@ static int init_ring_common(struct intel_engine_cs *engine) goto out; } - if (INTEL_GEN(dev_priv) > 2) + if (GT_GEN_RANGE(dev_priv, 3, GEN_FOREVER)) I915_WRITE_MODE(engine, _MASKED_BIT_DISABLE(STOP_RING)); /* Papering over lost _interrupts_ immediately following the restart */ @@ -666,7 +666,7 @@ static int init_render_ring(struct intel_engine_cs *engine) if (GT_GEN_RANGE(dev_priv, 6, 7)) I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING)); - if (INTEL_GEN(dev_priv) >= 6) + if (GT_GEN_RANGE(dev_priv, 6, GEN_FOREVER)) I915_WRITE_IMR(engine, ~engine->irq_keep_mask); return 0; @@ -1457,7 +1457,7 @@ void intel_engine_cleanup(struct intel_engine_cs *engine) { struct drm_i915_private *dev_priv = engine->i915; - WARN_ON(INTEL_GEN(dev_priv) > 2 && + WARN_ON(GT_GEN_RANGE(dev_priv, 3, GEN_FOREVER) && (I915_READ_MODE(engine) & MODE_IDLE) == 0); intel_ring_unpin(engine->buffer); @@ -2086,7 +2086,7 @@ static void intel_ring_init_semaphores(struct drm_i915_private *dev_priv, if (!HAS_LEGACY_SEMAPHORES(dev_priv)) return; - GEM_BUG_ON(INTEL_GEN(dev_priv) < 6); + GEM_BUG_ON(GT_GEN_RANGE(dev_priv, 0, 5)); engine->semaphore.sync_to = gen6_ring_sync_to; engine->semaphore.signal = gen6_signal; @@ -2141,15 +2141,15 @@ static void intel_ring_init_semaphores(struct drm_i915_private *dev_priv, static void intel_ring_init_irq(struct drm_i915_private *dev_priv, struct intel_engine_cs *engine) { - if (INTEL_GEN(dev_priv) >= 6) { + if (GT_GEN_RANGE(dev_priv, 6, GEN_FOREVER)) { engine->irq_enable = gen6_irq_enable; engine->irq_disable = gen6_irq_disable; engine->irq_seqno_barrier = gen6_seqno_barrier; - } else if (INTEL_GEN(dev_priv) >= 5) { + } else if (GT_GEN_RANGE(dev_priv, 5, GEN_FOREVER)) { engine->irq_enable = gen5_irq_enable; engine->irq_disable = gen5_irq_disable; engine->irq_seqno_barrier = gen5_seqno_barrier; - } else if (INTEL_GEN(dev_priv) >= 3) { + } else if (GT_GEN_RANGE(dev_priv, 3, GEN_FOREVER)) { engine->irq_enable = i9xx_irq_enable; engine->irq_disable = i9xx_irq_disable; } else { @@ -2177,7 +2177,7 @@ static void intel_ring_default_vfuncs(struct drm_i915_private *dev_priv, struct intel_engine_cs *engine) { /* gen8+ are only supported with execlists */ - GEM_BUG_ON(INTEL_GEN(dev_priv) >= 8); + GEM_BUG_ON(GT_GEN_RANGE(dev_priv, 8, GEN_FOREVER)); intel_ring_init_irq(dev_priv, engine); intel_ring_init_semaphores(dev_priv, engine); @@ -2205,9 +2205,9 @@ static void intel_ring_default_vfuncs(struct drm_i915_private *dev_priv, engine->set_default_submission = i9xx_set_default_submission; - if (INTEL_GEN(dev_priv) >= 6) + if (GT_GEN_RANGE(dev_priv, 6, GEN_FOREVER)) engine->emit_bb_start = gen6_emit_bb_start; - else if (INTEL_GEN(dev_priv) >= 4) + else if (GT_GEN_RANGE(dev_priv, 4, GEN_FOREVER)) engine->emit_bb_start = i965_emit_bb_start; else if (IS_I830(dev_priv) || IS_I845G(dev_priv)) engine->emit_bb_start = i830_emit_bb_start; @@ -2227,7 +2227,7 @@ int intel_init_render_ring_buffer(struct intel_engine_cs *engine) engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT; - if (INTEL_GEN(dev_priv) >= 6) { + if (GT_GEN_RANGE(dev_priv, 6, GEN_FOREVER)) { engine->init_context = intel_rcs_ctx_init; engine->emit_flush = gen7_render_ring_flush; if (GT_GEN(dev_priv, 6)) @@ -2235,7 +2235,7 @@ int intel_init_render_ring_buffer(struct intel_engine_cs *engine) } else if (GT_GEN(dev_priv, 5)) { engine->emit_flush = gen4_render_ring_flush; } else { - if (INTEL_GEN(dev_priv) < 4) + if (GT_GEN_RANGE(dev_priv, 0, 3)) engine->emit_flush = gen2_render_ring_flush; else engine->emit_flush = gen4_render_ring_flush; @@ -2260,7 +2260,7 @@ int intel_init_bsd_ring_buffer(struct intel_engine_cs *engine) intel_ring_default_vfuncs(dev_priv, engine); - if (INTEL_GEN(dev_priv) >= 6) { + if (GT_GEN_RANGE(dev_priv, 6, GEN_FOREVER)) { /* gen6 bsd needs a special wa for tail updates */ if (GT_GEN(dev_priv, 6)) engine->set_default_submission = gen6_bsd_set_default_submission; diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c index 3b78afe0a790..f295d0df4b0d 100644 --- a/drivers/gpu/drm/i915/intel_runtime_pm.c +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c @@ -369,7 +369,7 @@ static void hsw_power_well_enable(struct drm_i915_private *dev_priv, u32 val; if (wait_fuses) { - pg = INTEL_GEN(dev_priv) >= 11 ? ICL_PW_CTL_IDX_TO_PG(pw_idx) : + pg = GT_GEN_RANGE(dev_priv, 11, GEN_FOREVER) ? ICL_PW_CTL_IDX_TO_PG(pw_idx) : SKL_PW_CTL_IDX_TO_PG(pw_idx); /* * For PW1 we have to wait both for the PW0/PG0 fuse state @@ -579,7 +579,7 @@ static u32 gen9_dc_mask(struct drm_i915_private *dev_priv) u32 mask; mask = DC_STATE_EN_UPTO_DC5; - if (INTEL_GEN(dev_priv) >= 11) + if (GT_GEN_RANGE(dev_priv, 11, GEN_FOREVER)) mask |= DC_STATE_EN_UPTO_DC6 | DC_STATE_EN_DC9; else if (GT_GEN9_LP(dev_priv)) mask |= DC_STATE_EN_DC9; @@ -3019,7 +3019,7 @@ static uint32_t get_allowed_dc_mask(const struct drm_i915_private *dev_priv, int requested_dc; int max_dc; - if (INTEL_GEN(dev_priv) >= 11) { + if (GT_GEN_RANGE(dev_priv, 11, GEN_FOREVER)) { max_dc = 2; /* * DC9 has a separate HW flow from the rest of the DC states, @@ -3220,7 +3220,7 @@ static void gen9_dbuf_disable(struct drm_i915_private *dev_priv) static u8 intel_dbuf_max_slices(struct drm_i915_private *dev_priv) { - if (INTEL_GEN(dev_priv) < 11) + if (GT_GEN_RANGE(dev_priv, 0, 10)) return 1; return 2; } @@ -3826,7 +3826,7 @@ void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume) mutex_lock(&power_domains->lock); vlv_cmnlane_wa(dev_priv); mutex_unlock(&power_domains->lock); - } else if (IS_IVYBRIDGE(dev_priv) || INTEL_GEN(dev_priv) >= 7) + } else if (IS_IVYBRIDGE(dev_priv) || GT_GEN_RANGE(dev_priv, 7, GEN_FOREVER)) intel_pch_reset_handshake(dev_priv, !HAS_PCH_NOP(dev_priv)); /* diff --git a/drivers/gpu/drm/i915/intel_sdvo.c b/drivers/gpu/drm/i915/intel_sdvo.c index 5805ec1aba12..72212b8a4c06 100644 --- a/drivers/gpu/drm/i915/intel_sdvo.c +++ b/drivers/gpu/drm/i915/intel_sdvo.c @@ -1344,13 +1344,13 @@ static void intel_sdvo_pre_enable(struct intel_encoder *intel_encoder, return; /* Set the SDVO control regs. */ - if (INTEL_GEN(dev_priv) >= 4) { + if (GT_GEN_RANGE(dev_priv, 4, GEN_FOREVER)) { /* The real mode polarity is set by the SDVO commands, using * struct intel_sdvo_dtd. */ sdvox = SDVO_VSYNC_ACTIVE_HIGH | SDVO_HSYNC_ACTIVE_HIGH; if (!HAS_PCH_SPLIT(dev_priv) && crtc_state->limited_color_range) sdvox |= HDMI_COLOR_RANGE_16_235; - if (INTEL_GEN(dev_priv) < 5) + if (GT_GEN_RANGE(dev_priv, 0, 4)) sdvox |= SDVO_BORDER_ENABLE; } else { sdvox = I915_READ(intel_sdvo->sdvo_reg); @@ -1367,11 +1367,11 @@ static void intel_sdvo_pre_enable(struct intel_encoder *intel_encoder, sdvox |= SDVO_PIPE_SEL(crtc->pipe); if (crtc_state->has_audio) { - WARN_ON_ONCE(INTEL_GEN(dev_priv) < 4); + WARN_ON_ONCE(GT_GEN_RANGE(dev_priv, 0, 3)); sdvox |= SDVO_AUDIO_ENABLE; } - if (INTEL_GEN(dev_priv) >= 4) { + if (GT_GEN_RANGE(dev_priv, 4, GEN_FOREVER)) { /* done in crtc_mode_set as the dpll_md reg must be written early */ } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) || IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) { @@ -1382,7 +1382,7 @@ static void intel_sdvo_pre_enable(struct intel_encoder *intel_encoder, } if (input_dtd.part2.sdvo_flags & SDVO_NEED_TO_STALL && - INTEL_GEN(dev_priv) < 5) + GT_GEN_RANGE(dev_priv, 0, 4)) sdvox |= SDVO_STALL_SELECT; intel_sdvo_write_sdvox(intel_sdvo, sdvox); } @@ -2451,7 +2451,7 @@ intel_sdvo_add_hdmi_properties(struct intel_sdvo *intel_sdvo, struct drm_i915_private *dev_priv = to_i915(connector->base.base.dev); intel_attach_force_audio_property(&connector->base.base); - if (INTEL_GEN(dev_priv) >= 4 && IS_MOBILE(dev_priv)) { + if (GT_GEN_RANGE(dev_priv, 4, GEN_FOREVER) && IS_MOBILE(dev_priv)) { intel_attach_broadcast_rgb_property(&connector->base.base); } intel_attach_aspect_ratio_property(&connector->base.base); @@ -2521,7 +2521,7 @@ intel_sdvo_dvi_init(struct intel_sdvo *intel_sdvo, int device) connector->connector_type = DRM_MODE_CONNECTOR_DVID; /* gen3 doesn't do the hdmi bits in the SDVO register */ - if (INTEL_GEN(dev_priv) >= 4 && + if (GT_GEN_RANGE(dev_priv, 4, GEN_FOREVER) && intel_sdvo_is_hdmi_connector(intel_sdvo, device)) { connector->connector_type = DRM_MODE_CONNECTOR_HDMIA; intel_sdvo_connector->is_hdmi = true; diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c index 049e679e4145..4c0925615ecd 100644 --- a/drivers/gpu/drm/i915/intel_sprite.c +++ b/drivers/gpu/drm/i915/intel_sprite.c @@ -494,7 +494,7 @@ skl_program_plane(struct intel_plane *plane, spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); - if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) + if (GT_GEN_RANGE(dev_priv, 10, GEN_FOREVER) || IS_GEMINILAKE(dev_priv)) I915_WRITE_FW(PLANE_COLOR_CTL(pipe, plane_id), plane_state->color_ctl); @@ -522,7 +522,7 @@ skl_program_plane(struct intel_plane *plane, I915_WRITE_FW(PLANE_AUX_DIST(pipe, plane_id), (plane_state->color_plane[1].offset - surf_addr) | aux_stride); - if (INTEL_GEN(dev_priv) < 11) + if (GT_GEN_RANGE(dev_priv, 0, 10)) I915_WRITE_FW(PLANE_AUX_OFFSET(pipe, plane_id), (plane_state->color_plane[1].y << 16) | plane_state->color_plane[1].x); @@ -1314,7 +1314,7 @@ g4x_sprite_check(struct intel_crtc_state *crtc_state, int ret; if (intel_fb_scalable(plane_state->base.fb)) { - if (INTEL_GEN(dev_priv) < 7) { + if (GT_GEN_RANGE(dev_priv, 0, 6)) { min_scale = 1; max_scale = 16 << 16; } else if (IS_IVYBRIDGE(dev_priv)) { @@ -1345,7 +1345,7 @@ g4x_sprite_check(struct intel_crtc_state *crtc_state, if (ret) return ret; - if (INTEL_GEN(dev_priv) >= 7) + if (GT_GEN_RANGE(dev_priv, 7, GEN_FOREVER)) plane_state->ctl = ivb_sprite_ctl(crtc_state, plane_state); else plane_state->ctl = g4x_sprite_ctl(crtc_state, plane_state); @@ -1444,7 +1444,7 @@ static int skl_plane_check_fb(const struct intel_crtc_state *crtc_state, */ switch (fb->format->format) { case DRM_FORMAT_RGB565: - if (INTEL_GEN(dev_priv) >= 11) + if (GT_GEN_RANGE(dev_priv, 11, GEN_FOREVER)) break; /* fall through */ case DRM_FORMAT_C8: @@ -1570,7 +1570,7 @@ static int skl_plane_check(struct intel_crtc_state *crtc_state, plane_state->ctl = skl_plane_ctl(crtc_state, plane_state); - if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) + if (GT_GEN_RANGE(dev_priv, 10, GEN_FOREVER) || IS_GEMINILAKE(dev_priv)) plane_state->color_ctl = glk_plane_color_ctl(crtc_state, plane_state); @@ -1579,7 +1579,7 @@ static int skl_plane_check(struct intel_crtc_state *crtc_state, static bool has_dst_key_in_primary_plane(struct drm_i915_private *dev_priv) { - return INTEL_GEN(dev_priv) >= 9; + return GT_GEN_RANGE(dev_priv, 9, GEN_FOREVER); } static void intel_plane_set_ckey(struct intel_plane_state *plane_state, @@ -1603,7 +1603,7 @@ static void intel_plane_set_ckey(struct intel_plane_state *plane_state, * On SKL+ we want dst key enabled on * the primary and not on the sprite. */ - if (INTEL_GEN(dev_priv) >= 9 && plane->id != PLANE_PRIMARY && + if (GT_GEN_RANGE(dev_priv, 9, GEN_FOREVER) && plane->id != PLANE_PRIMARY && set->flags & I915_SET_COLORKEY_DESTINATION) key->flags = 0; } @@ -1642,7 +1642,7 @@ int intel_sprite_set_colorkey_ioctl(struct drm_device *dev, void *data, * Also multiple planes can't do destination keying on the same * pipe simultaneously. */ - if (INTEL_GEN(dev_priv) >= 9 && + if (GT_GEN_RANGE(dev_priv, 9, GEN_FOREVER) && to_intel_plane(plane)->id >= PLANE_SPRITE1 && set->flags & I915_SET_COLORKEY_DESTINATION) return -EINVAL; @@ -1972,7 +1972,7 @@ static bool skl_plane_has_fbc(struct drm_i915_private *dev_priv, static bool skl_plane_has_planar(struct drm_i915_private *dev_priv, enum pipe pipe, enum plane_id plane_id) { - if (INTEL_GEN(dev_priv) >= 11) + if (GT_GEN_RANGE(dev_priv, 11, GEN_FOREVER)) return plane_id <= PLANE_SPRITE3; /* Display WA #0870: skl, bxt */ @@ -1994,7 +1994,7 @@ static bool skl_plane_has_ccs(struct drm_i915_private *dev_priv, if (plane_id == PLANE_CURSOR) return false; - if (INTEL_GEN(dev_priv) >= 10) + if (GT_GEN_RANGE(dev_priv, 10, GEN_FOREVER)) return true; if (IS_GEMINILAKE(dev_priv)) @@ -2104,7 +2104,7 @@ skl_universal_plane_create(struct drm_i915_private *dev_priv, DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_90 | DRM_MODE_ROTATE_180 | DRM_MODE_ROTATE_270; - if (INTEL_GEN(dev_priv) >= 10) + if (GT_GEN_RANGE(dev_priv, 10, GEN_FOREVER)) supported_rotations |= DRM_MODE_REFLECT_X; drm_plane_create_rotation_property(&plane->base, @@ -2148,7 +2148,7 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv, int num_formats; int ret; - if (INTEL_GEN(dev_priv) >= 9) + if (GT_GEN_RANGE(dev_priv, 9, GEN_FOREVER)) return skl_universal_plane_create(dev_priv, pipe, PLANE_SPRITE0 + sprite); @@ -2168,7 +2168,7 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv, modifiers = i9xx_plane_format_modifiers; plane_funcs = &vlv_sprite_funcs; - } else if (INTEL_GEN(dev_priv) >= 7) { + } else if (GT_GEN_RANGE(dev_priv, 7, GEN_FOREVER)) { plane->max_stride = g4x_sprite_max_stride; plane->update_plane = ivb_update_plane; plane->disable_plane = ivb_disable_plane; diff --git a/drivers/gpu/drm/i915/intel_tv.c b/drivers/gpu/drm/i915/intel_tv.c index 860f306a23ba..c4332fed6182 100644 --- a/drivers/gpu/drm/i915/intel_tv.c +++ b/drivers/gpu/drm/i915/intel_tv.c @@ -1069,7 +1069,7 @@ static void intel_tv_pre_enable(struct intel_encoder *encoder, set_color_conversion(dev_priv, color_conversion); - if (INTEL_GEN(dev_priv) >= 4) + if (GT_GEN_RANGE(dev_priv, 4, GEN_FOREVER)) I915_WRITE(TV_CLR_KNOBS, 0x00404000); else I915_WRITE(TV_CLR_KNOBS, 0x00606000); diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c index 9eca84e7baa5..32ceb721b564 100644 --- a/drivers/gpu/drm/i915/intel_uc.c +++ b/drivers/gpu/drm/i915/intel_uc.c @@ -401,7 +401,7 @@ int intel_uc_init_hw(struct drm_i915_private *i915) ret = intel_guc_submission_enable(guc); if (ret) goto err_communication; - } else if (INTEL_GEN(i915) < 11) { + } else if (GT_GEN_RANGE(i915, 0, 10)) { ret = intel_guc_sample_forcewake(guc); if (ret) goto err_communication; diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c index 2e98416467a0..f488cf5d1f43 100644 --- a/drivers/gpu/drm/i915/intel_uncore.c +++ b/drivers/gpu/drm/i915/intel_uncore.c @@ -449,7 +449,7 @@ u64 intel_uncore_edram_size(struct drm_i915_private *dev_priv) /* The needed capability bits for size calculation * are not there with pre gen9 so return 128MB always. */ - if (INTEL_GEN(dev_priv) < 9) + if (GT_GEN_RANGE(dev_priv, 0, 8)) return 128 * 1024 * 1024; return gen9_edram_size(dev_priv); @@ -459,7 +459,7 @@ static void intel_uncore_edram_detect(struct drm_i915_private *dev_priv) { if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv) || - INTEL_GEN(dev_priv) >= 9) { + GT_GEN_RANGE(dev_priv, 9, GEN_FOREVER)) { dev_priv->edram_cap = __raw_i915_read32(dev_priv, HSW_EDRAM_CAP); @@ -877,7 +877,7 @@ find_fw_domain(struct drm_i915_private *dev_priv, u32 offset) { .start = (s), .end = (e), .domains = (d) } #define HAS_FWTABLE(dev_priv) \ - (INTEL_GEN(dev_priv) >= 9 || \ + (GT_GEN_RANGE(dev_priv, 9, GEN_FOREVER) || \ IS_CHERRYVIEW(dev_priv) || \ IS_VALLEYVIEW(dev_priv)) @@ -1395,7 +1395,7 @@ static void fw_domain_fini(struct drm_i915_private *dev_priv, static void intel_uncore_fw_domains_init(struct drm_i915_private *dev_priv) { - if (INTEL_GEN(dev_priv) <= 5 || intel_vgpu_active(dev_priv)) + if (GT_GEN_RANGE(dev_priv, 0, 5) || intel_vgpu_active(dev_priv)) return; if (GT_GEN(dev_priv, 6)) { @@ -1409,7 +1409,7 @@ static void intel_uncore_fw_domains_init(struct drm_i915_private *dev_priv) dev_priv->uncore.fw_clear = _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL); } - if (INTEL_GEN(dev_priv) >= 11) { + if (GT_GEN_RANGE(dev_priv, 11, GEN_FOREVER)) { int i; dev_priv->uncore.funcs.force_wake_get = @@ -1613,7 +1613,7 @@ void intel_uncore_init(struct drm_i915_private *dev_priv) */ void intel_uncore_prune(struct drm_i915_private *dev_priv) { - if (INTEL_GEN(dev_priv) >= 11) { + if (GT_GEN_RANGE(dev_priv, 11, GEN_FOREVER)) { enum forcewake_domains fw_domains = dev_priv->uncore.fw_domains; enum forcewake_domain_id domain_id; int i; @@ -1744,7 +1744,7 @@ static void i915_stop_engines(struct drm_i915_private *dev_priv, struct intel_engine_cs *engine; enum intel_engine_id id; - if (INTEL_GEN(dev_priv) < 3) + if (GT_GEN_RANGE(dev_priv, 0, 2)) return; for_each_engine_masked(engine, dev_priv, engine_mask, id) @@ -2117,7 +2117,7 @@ static int reset_engines(struct drm_i915_private *i915, unsigned int engine_mask, unsigned int retry) { - if (INTEL_GEN(i915) >= 11) + if (GT_GEN_RANGE(i915, 11, GEN_FOREVER)) return gen11_reset_engines(i915, engine_mask); else return gen6_reset_engines(i915, engine_mask, retry); @@ -2169,9 +2169,9 @@ static reset_func intel_get_gpu_reset(struct drm_i915_private *dev_priv) if (!i915_modparams.reset) return NULL; - if (INTEL_GEN(dev_priv) >= 8) + if (GT_GEN_RANGE(dev_priv, 8, GEN_FOREVER)) return gen8_reset_engines; - else if (INTEL_GEN(dev_priv) >= 6) + else if (GT_GEN_RANGE(dev_priv, 6, GEN_FOREVER)) return gen6_reset_engines; else if (GT_GEN(dev_priv, 5)) return ironlake_do_reset; @@ -2179,7 +2179,7 @@ static reset_func intel_get_gpu_reset(struct drm_i915_private *dev_priv) return g4x_do_reset; else if (IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) return g33_do_reset; - else if (INTEL_GEN(dev_priv) >= 3) + else if (GT_GEN_RANGE(dev_priv, 3, GEN_FOREVER)) return i915_do_reset; else return NULL; @@ -2262,7 +2262,7 @@ bool intel_has_reset_engine(struct drm_i915_private *dev_priv) int intel_reset_guc(struct drm_i915_private *dev_priv) { - u32 guc_domain = INTEL_GEN(dev_priv) >= 11 ? GEN11_GRDOM_GUC : + u32 guc_domain = GT_GEN_RANGE(dev_priv, 11, GEN_FOREVER) ? GEN11_GRDOM_GUC : GEN9_GRDOM_GUC; int ret; @@ -2314,11 +2314,11 @@ intel_uncore_forcewake_for_read(struct drm_i915_private *dev_priv, u32 offset = i915_mmio_reg_offset(reg); enum forcewake_domains fw_domains; - if (INTEL_GEN(dev_priv) >= 11) { + if (GT_GEN_RANGE(dev_priv, 11, GEN_FOREVER)) { fw_domains = __gen11_fwtable_reg_read_fw_domains(offset); } else if (HAS_FWTABLE(dev_priv)) { fw_domains = __fwtable_reg_read_fw_domains(offset); - } else if (INTEL_GEN(dev_priv) >= 6) { + } else if (GT_GEN_RANGE(dev_priv, 6, GEN_FOREVER)) { fw_domains = __gen6_reg_read_fw_domains(offset); } else { WARN_ON(!GT_GEN_RANGE(dev_priv, 2, 5)); @@ -2337,7 +2337,7 @@ intel_uncore_forcewake_for_write(struct drm_i915_private *dev_priv, u32 offset = i915_mmio_reg_offset(reg); enum forcewake_domains fw_domains; - if (INTEL_GEN(dev_priv) >= 11) { + if (GT_GEN_RANGE(dev_priv, 11, GEN_FOREVER)) { fw_domains = __gen11_fwtable_reg_write_fw_domains(offset); } else if (HAS_FWTABLE(dev_priv) && !IS_VALLEYVIEW(dev_priv)) { fw_domains = __fwtable_reg_write_fw_domains(offset); diff --git a/drivers/gpu/drm/i915/intel_wopcm.c b/drivers/gpu/drm/i915/intel_wopcm.c index 0a5c68acf3dd..0811fe3885e2 100644 --- a/drivers/gpu/drm/i915/intel_wopcm.c +++ b/drivers/gpu/drm/i915/intel_wopcm.c @@ -80,7 +80,7 @@ static inline u32 context_reserved_size(struct drm_i915_private *i915) { if (GT_GEN9_LP(i915)) return BXT_WOPCM_RC6_CTX_RESERVED; - else if (INTEL_GEN(i915) >= 10) + else if (GT_GEN_RANGE(i915, 10, GEN_FOREVER)) return CNL_WOPCM_HW_CTX_RESERVED; else return 0; diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c index db899cc5c981..1efaa5b5dbcc 100644 --- a/drivers/gpu/drm/i915/intel_workarounds.c +++ b/drivers/gpu/drm/i915/intel_workarounds.c @@ -517,7 +517,7 @@ int intel_ctx_workarounds_init(struct drm_i915_private *dev_priv) dev_priv->workarounds.count = 0; - if (INTEL_GEN(dev_priv) < 8) + if (GT_GEN_RANGE(dev_priv, 0, 7)) err = 0; else if (IS_BROADWELL(dev_priv)) err = bdw_ctx_workarounds_init(dev_priv); @@ -749,7 +749,7 @@ static void wa_init_mcr(struct drm_i915_private *dev_priv) * something more complex that requires checking the range of every * MMIO read). */ - if (INTEL_GEN(dev_priv) >= 10 && + if (GT_GEN_RANGE(dev_priv, 10, GEN_FOREVER) && is_power_of_2(sseu->slice_mask)) { /* * read FUSE3 for enabled L3 Bank IDs, if L3 Bank matches @@ -772,7 +772,7 @@ static void wa_init_mcr(struct drm_i915_private *dev_priv) mcr = I915_READ(GEN8_MCR_SELECTOR); - if (INTEL_GEN(dev_priv) >= 11) + if (GT_GEN_RANGE(dev_priv, 11, GEN_FOREVER)) mcr_slice_subslice_mask = GEN11_MCR_SLICE_MASK | GEN11_MCR_SUBSLICE_MASK; else @@ -916,7 +916,7 @@ static void icl_gt_workarounds_apply(struct drm_i915_private *dev_priv) void intel_gt_workarounds_apply(struct drm_i915_private *dev_priv) { - if (INTEL_GEN(dev_priv) < 8) + if (GT_GEN_RANGE(dev_priv, 0, 7)) return; else if (IS_BROADWELL(dev_priv)) bdw_gt_workarounds_apply(dev_priv); @@ -1033,7 +1033,7 @@ static struct whitelist *whitelist_build(struct intel_engine_cs *engine, w->count = 0; w->nopid = i915_mmio_reg_offset(RING_NOPID(engine->mmio_base)); - if (INTEL_GEN(i915) < 8) + if (GT_GEN_RANGE(i915, 0, 7)) return NULL; else if (IS_BROADWELL(i915)) bdw_whitelist_build(w); diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_coherency.c b/drivers/gpu/drm/i915/selftests/i915_gem_coherency.c index f7392c1ffe75..e4cfdaa5551b 100644 --- a/drivers/gpu/drm/i915/selftests/i915_gem_coherency.c +++ b/drivers/gpu/drm/i915/selftests/i915_gem_coherency.c @@ -215,12 +215,12 @@ static int gpu_set(struct drm_i915_gem_object *obj, return PTR_ERR(cs); } - if (INTEL_GEN(i915) >= 8) { + if (GT_GEN_RANGE(i915, 8, GEN_FOREVER)) { *cs++ = MI_STORE_DWORD_IMM_GEN4 | 1 << 22; *cs++ = lower_32_bits(i915_ggtt_offset(vma) + offset); *cs++ = upper_32_bits(i915_ggtt_offset(vma) + offset); *cs++ = v; - } else if (INTEL_GEN(i915) >= 4) { + } else if (GT_GEN_RANGE(i915, 4, GEN_FOREVER)) { *cs++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT; *cs++ = 0; *cs++ = i915_ggtt_offset(vma) + offset; diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_context.c b/drivers/gpu/drm/i915/selftests/i915_gem_context.c index 7d82043aff10..dd5424f8faa9 100644 --- a/drivers/gpu/drm/i915/selftests/i915_gem_context.c +++ b/drivers/gpu/drm/i915/selftests/i915_gem_context.c @@ -379,7 +379,7 @@ static int gpu_fill(struct drm_i915_gem_object *obj, } flags = 0; - if (INTEL_GEN(vm->i915) <= 5) + if (GT_GEN_RANGE(vm->i915, 0, 5)) flags |= I915_DISPATCH_SECURE; err = engine->emit_bb_start(rq, @@ -799,7 +799,7 @@ static int write_to_scratch(struct i915_gem_context *ctx, } *cmd++ = MI_STORE_DWORD_IMM_GEN4; - if (INTEL_GEN(i915) >= 8) { + if (GT_GEN_RANGE(i915, 8, GEN_FOREVER)) { *cmd++ = lower_32_bits(offset); *cmd++ = upper_32_bits(offset); } else { @@ -887,7 +887,7 @@ static int read_from_scratch(struct i915_gem_context *ctx, } memset(cmd, POISON_INUSE, PAGE_SIZE); - if (INTEL_GEN(i915) >= 8) { + if (GT_GEN_RANGE(i915, 8, GEN_FOREVER)) { *cmd++ = MI_LOAD_REGISTER_MEM_GEN8; *cmd++ = RCS_GPR0; *cmd++ = lower_32_bits(offset); @@ -984,7 +984,7 @@ static int igt_vm_isolation(void *arg) u64 vm_total; int err; - if (INTEL_GEN(i915) < 7) + if (GT_GEN_RANGE(i915, 0, 6)) return 0; /* diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_object.c b/drivers/gpu/drm/i915/selftests/i915_gem_object.c index c3999dd2021e..c35c7b59e7d2 100644 --- a/drivers/gpu/drm/i915/selftests/i915_gem_object.c +++ b/drivers/gpu/drm/i915/selftests/i915_gem_object.c @@ -379,7 +379,7 @@ static int igt_partial_tiling(void *arg) tile.swizzle == I915_BIT_6_SWIZZLE_9_10_17) continue; - if (INTEL_GEN(i915) <= 2) { + if (GT_GEN_RANGE(i915, 0, 2)) { tile.height = 16; tile.width = 128; tile.size = 11; @@ -394,9 +394,9 @@ static int igt_partial_tiling(void *arg) tile.size = 12; } - if (INTEL_GEN(i915) < 4) + if (GT_GEN_RANGE(i915, 0, 3)) max_pitch = 8192 / tile.width; - else if (INTEL_GEN(i915) < 7) + else if (GT_GEN_RANGE(i915, 0, 6)) max_pitch = 128 * I965_FENCE_MAX_PITCH_VAL / tile.width; else max_pitch = 128 * GEN7_FENCE_MAX_PITCH_VAL / tile.width; @@ -409,7 +409,7 @@ static int igt_partial_tiling(void *arg) if (err) goto out_unlock; - if (pitch > 2 && INTEL_GEN(i915) >= 4) { + if (pitch > 2 && GT_GEN_RANGE(i915, 4, GEN_FOREVER)) { tile.stride = tile.width * (pitch - 1); err = check_partial_mapping(obj, &tile, end); if (err == -EINTR) @@ -418,7 +418,7 @@ static int igt_partial_tiling(void *arg) goto out_unlock; } - if (pitch < max_pitch && INTEL_GEN(i915) >= 4) { + if (pitch < max_pitch && GT_GEN_RANGE(i915, 4, GEN_FOREVER)) { tile.stride = tile.width * (pitch + 1); err = check_partial_mapping(obj, &tile, end); if (err == -EINTR) @@ -428,7 +428,7 @@ static int igt_partial_tiling(void *arg) } } - if (INTEL_GEN(i915) >= 4) { + if (GT_GEN_RANGE(i915, 4, GEN_FOREVER)) { for_each_prime_number(pitch, max_pitch) { tile.stride = tile.width * pitch; err = check_partial_mapping(obj, &tile, end); diff --git a/drivers/gpu/drm/i915/selftests/intel_hangcheck.c b/drivers/gpu/drm/i915/selftests/intel_hangcheck.c index 51d0e2bed9e1..3c65059b60db 100644 --- a/drivers/gpu/drm/i915/selftests/intel_hangcheck.c +++ b/drivers/gpu/drm/i915/selftests/intel_hangcheck.c @@ -150,7 +150,7 @@ static int emit_recurse_batch(struct hang *h, } batch = h->batch; - if (INTEL_GEN(i915) >= 8) { + if (GT_GEN_RANGE(i915, 8, GEN_FOREVER)) { *batch++ = MI_STORE_DWORD_IMM_GEN4; *batch++ = lower_32_bits(hws_address(hws, rq)); *batch++ = upper_32_bits(hws_address(hws, rq)); @@ -164,7 +164,7 @@ static int emit_recurse_batch(struct hang *h, *batch++ = MI_BATCH_BUFFER_START | 1 << 8 | 1; *batch++ = lower_32_bits(vma->node.start); *batch++ = upper_32_bits(vma->node.start); - } else if (INTEL_GEN(i915) >= 6) { + } else if (GT_GEN_RANGE(i915, 6, GEN_FOREVER)) { *batch++ = MI_STORE_DWORD_IMM_GEN4; *batch++ = 0; *batch++ = lower_32_bits(hws_address(hws, rq)); @@ -177,7 +177,7 @@ static int emit_recurse_batch(struct hang *h, *batch++ = MI_ARB_CHECK; *batch++ = MI_BATCH_BUFFER_START | 1 << 8; *batch++ = lower_32_bits(vma->node.start); - } else if (INTEL_GEN(i915) >= 4) { + } else if (GT_GEN_RANGE(i915, 4, GEN_FOREVER)) { *batch++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT; *batch++ = 0; *batch++ = lower_32_bits(hws_address(hws, rq)); @@ -207,7 +207,7 @@ static int emit_recurse_batch(struct hang *h, i915_gem_chipset_flush(h->i915); flags = 0; - if (INTEL_GEN(vm->i915) <= 5) + if (GT_GEN_RANGE(vm->i915, 0, 5)) flags |= I915_DISPATCH_SECURE; err = rq->engine->emit_bb_start(rq, vma->node.start, PAGE_SIZE, flags); diff --git a/drivers/gpu/drm/i915/selftests/intel_lrc.c b/drivers/gpu/drm/i915/selftests/intel_lrc.c index 94fc0e5c8766..a00a6931c50a 100644 --- a/drivers/gpu/drm/i915/selftests/intel_lrc.c +++ b/drivers/gpu/drm/i915/selftests/intel_lrc.c @@ -24,7 +24,7 @@ static int spinner_init(struct spinner *spin, struct drm_i915_private *i915) void *vaddr; int err; - GEM_BUG_ON(INTEL_GEN(i915) < 8); + GEM_BUG_ON(GT_GEN_RANGE(i915, 0, 7)); memset(spin, 0, sizeof(*spin)); spin->i915 = i915; diff --git a/drivers/gpu/drm/i915/selftests/intel_uncore.c b/drivers/gpu/drm/i915/selftests/intel_uncore.c index 81d9d31042a9..14406cca480a 100644 --- a/drivers/gpu/drm/i915/selftests/intel_uncore.c +++ b/drivers/gpu/drm/i915/selftests/intel_uncore.c @@ -184,7 +184,7 @@ int intel_uncore_live_selftests(struct drm_i915_private *i915) /* Confirm the table we load is still valid */ err = intel_fw_table_check(i915->uncore.fw_domains_table, i915->uncore.fw_domains_table_entries, - INTEL_GEN(i915) >= 9); + GT_GEN_RANGE(i915, 9, GEN_FOREVER)); if (err) return err; diff --git a/drivers/gpu/drm/i915/selftests/intel_workarounds.c b/drivers/gpu/drm/i915/selftests/intel_workarounds.c index d1a0923d2f38..72573893e78c 100644 --- a/drivers/gpu/drm/i915/selftests/intel_workarounds.c +++ b/drivers/gpu/drm/i915/selftests/intel_workarounds.c @@ -57,7 +57,7 @@ read_nonprivs(struct i915_gem_context *ctx, struct intel_engine_cs *engine) goto err_req; srm = MI_STORE_REGISTER_MEM | MI_SRM_LRM_GLOBAL_GTT; - if (INTEL_GEN(ctx->i915) >= 8) + if (GT_GEN_RANGE(ctx->i915, 8, GEN_FOREVER)) srm++; cs = intel_ring_begin(rq, 4 * RING_MAX_NONPRIV_SLOTS); -- 2.19.1.1.g56c4683e68 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 38+ messages in thread
* [PATCH v2 6/7] drm/i915: merge gen checks to use range 2018-11-06 21:51 [PATCH v2 0/7] Make GEN macros more similar Lucas De Marchi ` (4 preceding siblings ...) 2018-11-06 21:51 ` [PATCH v2 5/7] drm/i915: replace gen checks using operators by GT_GEN/GT_GEN_RANGE Lucas De Marchi @ 2018-11-06 21:51 ` Lucas De Marchi 2018-11-21 22:24 ` Rodrigo Vivi 2018-11-06 21:51 ` [PATCH v2 7/7] drm/i915: remove INTEL_GEN macro Lucas De Marchi ` (5 subsequent siblings) 11 siblings, 1 reply; 38+ messages in thread From: Lucas De Marchi @ 2018-11-06 21:51 UTC (permalink / raw) To: intel-gfx; +Cc: Rodrigo Vivi Instead of using several GT_GEN(), let's pass the range to GT_GEN_RANGE(). By code inspection these were the ranges deemed necessary for spatch: @@ expression e; @@ ( - GT_GEN(e, 3) || GT_GEN(e, 2) + GT_GEN_RANGE(e, 2, 3) | - GT_GEN(e, 3) || GT_GEN(e, 4) + GT_GEN_RANGE(e, 3, 4) | - GT_GEN(e, 5) || GT_GEN(e, 6) + GT_GEN_RANGE(e, 5, 6) | - GT_GEN(e, 6) || GT_GEN(e, 7) + GT_GEN_RANGE(e, 6, 7) | - GT_GEN(e, 7) || GT_GEN(e, 8) + GT_GEN_RANGE(e, 7, 8) | - GT_GEN(e, 8) || GT_GEN(e, 9) + GT_GEN_RANGE(e, 8, 9) | - GT_GEN(e, 10) || GT_GEN(e, 9) + GT_GEN_RANGE(e, 9, 10) | - GT_GEN(e, 9) || GT_GEN(e, 10) + GT_GEN_RANGE(e, 9, 10) ) Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> --- drivers/gpu/drm/i915/gvt/gtt.c | 2 +- drivers/gpu/drm/i915/i915_debugfs.c | 6 +++--- drivers/gpu/drm/i915/i915_gpu_error.c | 2 +- drivers/gpu/drm/i915/i915_perf.c | 2 +- drivers/gpu/drm/i915/intel_crt.c | 2 +- drivers/gpu/drm/i915/intel_device_info.c | 2 +- drivers/gpu/drm/i915/intel_display.c | 2 +- drivers/gpu/drm/i915/intel_engine_cs.c | 2 +- drivers/gpu/drm/i915/intel_fifo_underrun.c | 2 +- drivers/gpu/drm/i915/intel_pipe_crc.c | 4 ++-- drivers/gpu/drm/i915/intel_uncore.c | 6 +++--- 11 files changed, 16 insertions(+), 16 deletions(-) diff --git a/drivers/gpu/drm/i915/gvt/gtt.c b/drivers/gpu/drm/i915/gvt/gtt.c index bc79c154391d..692de9b9779b 100644 --- a/drivers/gpu/drm/i915/gvt/gtt.c +++ b/drivers/gpu/drm/i915/gvt/gtt.c @@ -1025,7 +1025,7 @@ static bool vgpu_ips_enabled(struct intel_vgpu *vgpu) { struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; - if (GT_GEN(dev_priv, 9) || GT_GEN(dev_priv, 10)) { + if (GT_GEN_RANGE(dev_priv, 9, 10)) { u32 ips = vgpu_vreg_t(vgpu, GEN8_GAMW_ECO_DEV_RW_IA) & GAMW_ECO_ENABLE_64K_IPS_FIELD; diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index ec26076aaecc..9ffcf0be0589 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -2030,7 +2030,7 @@ static int i915_swizzle_info(struct seq_file *m, void *data) seq_printf(m, "bit6 swizzle for Y-tiling = %s\n", swizzle_string(dev_priv->mm.bit_6_swizzle_y)); - if (GT_GEN(dev_priv, 3) || GT_GEN(dev_priv, 4)) { + if (GT_GEN_RANGE(dev_priv, 3, 4)) { seq_printf(m, "DDC = 0x%08x\n", I915_READ(DCC)); seq_printf(m, "DDC2 = 0x%08x\n", @@ -4262,7 +4262,7 @@ i915_cache_sharing_get(void *data, u64 *val) struct drm_i915_private *dev_priv = data; u32 snpcr; - if (!(GT_GEN(dev_priv, 6) || GT_GEN(dev_priv, 7))) + if (!(GT_GEN_RANGE(dev_priv, 6, 7))) return -ENODEV; intel_runtime_pm_get(dev_priv); @@ -4282,7 +4282,7 @@ i915_cache_sharing_set(void *data, u64 val) struct drm_i915_private *dev_priv = data; u32 snpcr; - if (!(GT_GEN(dev_priv, 6) || GT_GEN(dev_priv, 7))) + if (!(GT_GEN_RANGE(dev_priv, 6, 7))) return -ENODEV; if (val > 3) diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c index 0de8ce65053d..e754c0306425 100644 --- a/drivers/gpu/drm/i915/i915_gpu_error.c +++ b/drivers/gpu/drm/i915/i915_gpu_error.c @@ -1673,7 +1673,7 @@ static void capture_reg_state(struct i915_gpu_state *error) error->ccid = I915_READ(CCID); /* 3: Feature specific registers */ - if (GT_GEN(dev_priv, 6) || GT_GEN(dev_priv, 7)) { + if (GT_GEN_RANGE(dev_priv, 6, 7)) { error->gam_ecochk = I915_READ(GAM_ECOCHK); error->gac_eco = I915_READ(GAC_ECO_BITS); } diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c index 5cc1ffa621a7..b5154891e0d7 100644 --- a/drivers/gpu/drm/i915/i915_perf.c +++ b/drivers/gpu/drm/i915/i915_perf.c @@ -3449,7 +3449,7 @@ void i915_perf_init(struct drm_i915_private *dev_priv) dev_priv->perf.oa.ops.read = gen8_oa_read; dev_priv->perf.oa.ops.oa_hw_tail_read = gen8_oa_hw_tail_read; - if (GT_GEN(dev_priv, 8) || GT_GEN(dev_priv, 9)) { + if (GT_GEN_RANGE(dev_priv, 8, 9)) { dev_priv->perf.oa.ops.is_valid_b_counter_reg = gen7_is_valid_b_counter_addr; dev_priv->perf.oa.ops.is_valid_mux_reg = diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c index dbc97c29f7e5..cbc76b7b8b74 100644 --- a/drivers/gpu/drm/i915/intel_crt.c +++ b/drivers/gpu/drm/i915/intel_crt.c @@ -322,7 +322,7 @@ intel_crt_mode_valid(struct drm_connector *connector, * DAC limit supposedly 355 MHz. */ max_clock = 270000; - else if (GT_GEN(dev_priv, 3) || GT_GEN(dev_priv, 4)) + else if (GT_GEN_RANGE(dev_priv, 3, 4)) max_clock = 400000; else max_clock = 350000; diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c index bad3eb2428ac..1761529f3e69 100644 --- a/drivers/gpu/drm/i915/intel_device_info.c +++ b/drivers/gpu/drm/i915/intel_device_info.c @@ -783,7 +783,7 @@ void intel_device_info_runtime_init(struct intel_device_info *info) DRM_INFO("Display disabled (module parameter)\n"); info->num_pipes = 0; } else if (info->num_pipes > 0 && - (GT_GEN(dev_priv, 7) || GT_GEN(dev_priv, 8)) && + (GT_GEN_RANGE(dev_priv, 7, 8)) && HAS_PCH_SPLIT(dev_priv)) { u32 fuse_strap = I915_READ(FUSE_STRAP); u32 sfuse_strap = I915_READ(SFUSE_STRAP); diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 454a7e86adc8..0288169c1462 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -10684,7 +10684,7 @@ int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_crtc_stat * the w/a on all three platforms. */ if (plane->id == PLANE_SPRITE0 && - (GT_GEN(dev_priv, 5) || GT_GEN(dev_priv, 6) || + (GT_GEN_RANGE(dev_priv, 5, 6) || IS_IVYBRIDGE(dev_priv)) && (turn_on || (!needs_scaling(old_plane_state) && needs_scaling(to_intel_plane_state(plane_state))))) diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c index fdd6966e5b95..db1a5d07e2e0 100644 --- a/drivers/gpu/drm/i915/intel_engine_cs.c +++ b/drivers/gpu/drm/i915/intel_engine_cs.c @@ -438,7 +438,7 @@ void intel_engine_init_global_seqno(struct intel_engine_cs *engine, u32 seqno) * the semaphore value, then when the seqno moves backwards all * future waits will complete instantly (causing rendering corruption). */ - if (GT_GEN(dev_priv, 6) || GT_GEN(dev_priv, 7)) { + if (GT_GEN_RANGE(dev_priv, 6, 7)) { I915_WRITE(RING_SYNC_0(engine->mmio_base), 0); I915_WRITE(RING_SYNC_1(engine->mmio_base), 0); if (HAS_VEBOX(dev_priv)) diff --git a/drivers/gpu/drm/i915/intel_fifo_underrun.c b/drivers/gpu/drm/i915/intel_fifo_underrun.c index ff76da50153d..e1d48193ab0b 100644 --- a/drivers/gpu/drm/i915/intel_fifo_underrun.c +++ b/drivers/gpu/drm/i915/intel_fifo_underrun.c @@ -260,7 +260,7 @@ static bool __intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev, if (HAS_GMCH_DISPLAY(dev_priv)) i9xx_set_fifo_underrun_reporting(dev, pipe, enable, old); - else if (GT_GEN(dev_priv, 5) || GT_GEN(dev_priv, 6)) + else if (GT_GEN_RANGE(dev_priv, 5, 6)) ironlake_set_fifo_underrun_reporting(dev, pipe, enable); else if (GT_GEN(dev_priv, 7)) ivybridge_set_fifo_underrun_reporting(dev, pipe, enable, old); diff --git a/drivers/gpu/drm/i915/intel_pipe_crc.c b/drivers/gpu/drm/i915/intel_pipe_crc.c index 597e52bc15e8..1ffa81f0be3c 100644 --- a/drivers/gpu/drm/i915/intel_pipe_crc.c +++ b/drivers/gpu/drm/i915/intel_pipe_crc.c @@ -433,7 +433,7 @@ static int get_new_crc_ctl_reg(struct drm_i915_private *dev_priv, return i9xx_pipe_crc_ctl_reg(dev_priv, pipe, source, val); else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) return vlv_pipe_crc_ctl_reg(dev_priv, pipe, source, val); - else if (GT_GEN(dev_priv, 5) || GT_GEN(dev_priv, 6)) + else if (GT_GEN_RANGE(dev_priv, 5, 6)) return ilk_pipe_crc_ctl_reg(source, val); else return ivb_pipe_crc_ctl_reg(dev_priv, pipe, source, val, set_wa); @@ -550,7 +550,7 @@ intel_is_valid_crc_source(struct drm_i915_private *dev_priv, return i9xx_crc_source_valid(dev_priv, source); else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) return vlv_crc_source_valid(dev_priv, source); - else if (GT_GEN(dev_priv, 5) || GT_GEN(dev_priv, 6)) + else if (GT_GEN_RANGE(dev_priv, 5, 6)) return ilk_crc_source_valid(dev_priv, source); else return ivb_crc_source_valid(dev_priv, source); diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c index f488cf5d1f43..88ffcde16fc6 100644 --- a/drivers/gpu/drm/i915/intel_uncore.c +++ b/drivers/gpu/drm/i915/intel_uncore.c @@ -528,7 +528,7 @@ check_for_unclaimed_mmio(struct drm_i915_private *dev_priv) if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) ret |= vlv_check_for_unclaimed_mmio(dev_priv); - if (GT_GEN(dev_priv, 6) || GT_GEN(dev_priv, 7)) + if (GT_GEN_RANGE(dev_priv, 6, 7)) ret |= gen6_check_for_fifo_debug(dev_priv); return ret; @@ -556,7 +556,7 @@ static void __intel_uncore_early_sanitize(struct drm_i915_private *dev_priv, dev_priv->uncore.funcs.force_wake_get(dev_priv, restore_forcewake); - if (GT_GEN(dev_priv, 6) || GT_GEN(dev_priv, 7)) + if (GT_GEN_RANGE(dev_priv, 6, 7)) dev_priv->uncore.fifo_count = fifo_free_entries(dev_priv); spin_unlock_irq(&dev_priv->uncore.lock); @@ -1437,7 +1437,7 @@ static void intel_uncore_fw_domains_init(struct drm_i915_private *dev_priv) FORCEWAKE_MEDIA_VEBOX_GEN11(i), FORCEWAKE_ACK_MEDIA_VEBOX_GEN11(i)); } - } else if (GT_GEN(dev_priv, 10) || GT_GEN(dev_priv, 9)) { + } else if (GT_GEN_RANGE(dev_priv, 9, 10)) { dev_priv->uncore.funcs.force_wake_get = fw_domains_get_with_fallback; dev_priv->uncore.funcs.force_wake_put = fw_domains_put; -- 2.19.1.1.g56c4683e68 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 38+ messages in thread
* Re: [PATCH v2 6/7] drm/i915: merge gen checks to use range 2018-11-06 21:51 ` [PATCH v2 6/7] drm/i915: merge gen checks to use range Lucas De Marchi @ 2018-11-21 22:24 ` Rodrigo Vivi 0 siblings, 0 replies; 38+ messages in thread From: Rodrigo Vivi @ 2018-11-21 22:24 UTC (permalink / raw) To: Lucas De Marchi; +Cc: intel-gfx On Tue, Nov 06, 2018 at 01:51:22PM -0800, Lucas De Marchi wrote: > Instead of using several GT_GEN(), let's pass the range to > GT_GEN_RANGE(). By code inspection these were the ranges deemed > necessary for spatch: > > @@ > expression e; > @@ > ( > - GT_GEN(e, 3) || GT_GEN(e, 2) > + GT_GEN_RANGE(e, 2, 3) > | > - GT_GEN(e, 3) || GT_GEN(e, 4) > + GT_GEN_RANGE(e, 3, 4) > | > - GT_GEN(e, 5) || GT_GEN(e, 6) > + GT_GEN_RANGE(e, 5, 6) > | > - GT_GEN(e, 6) || GT_GEN(e, 7) > + GT_GEN_RANGE(e, 6, 7) > | > - GT_GEN(e, 7) || GT_GEN(e, 8) > + GT_GEN_RANGE(e, 7, 8) > | > - GT_GEN(e, 8) || GT_GEN(e, 9) > + GT_GEN_RANGE(e, 8, 9) > | > - GT_GEN(e, 10) || GT_GEN(e, 9) > + GT_GEN_RANGE(e, 9, 10) > | > - GT_GEN(e, 9) || GT_GEN(e, 10) > + GT_GEN_RANGE(e, 9, 10) > ) > > Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> a good start point although I believe we will need to do more changes later... Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> > --- > drivers/gpu/drm/i915/gvt/gtt.c | 2 +- > drivers/gpu/drm/i915/i915_debugfs.c | 6 +++--- > drivers/gpu/drm/i915/i915_gpu_error.c | 2 +- > drivers/gpu/drm/i915/i915_perf.c | 2 +- > drivers/gpu/drm/i915/intel_crt.c | 2 +- > drivers/gpu/drm/i915/intel_device_info.c | 2 +- > drivers/gpu/drm/i915/intel_display.c | 2 +- > drivers/gpu/drm/i915/intel_engine_cs.c | 2 +- > drivers/gpu/drm/i915/intel_fifo_underrun.c | 2 +- > drivers/gpu/drm/i915/intel_pipe_crc.c | 4 ++-- > drivers/gpu/drm/i915/intel_uncore.c | 6 +++--- > 11 files changed, 16 insertions(+), 16 deletions(-) > > diff --git a/drivers/gpu/drm/i915/gvt/gtt.c b/drivers/gpu/drm/i915/gvt/gtt.c > index bc79c154391d..692de9b9779b 100644 > --- a/drivers/gpu/drm/i915/gvt/gtt.c > +++ b/drivers/gpu/drm/i915/gvt/gtt.c > @@ -1025,7 +1025,7 @@ static bool vgpu_ips_enabled(struct intel_vgpu *vgpu) > { > struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv; > > - if (GT_GEN(dev_priv, 9) || GT_GEN(dev_priv, 10)) { > + if (GT_GEN_RANGE(dev_priv, 9, 10)) { > u32 ips = vgpu_vreg_t(vgpu, GEN8_GAMW_ECO_DEV_RW_IA) & > GAMW_ECO_ENABLE_64K_IPS_FIELD; > > diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c > index ec26076aaecc..9ffcf0be0589 100644 > --- a/drivers/gpu/drm/i915/i915_debugfs.c > +++ b/drivers/gpu/drm/i915/i915_debugfs.c > @@ -2030,7 +2030,7 @@ static int i915_swizzle_info(struct seq_file *m, void *data) > seq_printf(m, "bit6 swizzle for Y-tiling = %s\n", > swizzle_string(dev_priv->mm.bit_6_swizzle_y)); > > - if (GT_GEN(dev_priv, 3) || GT_GEN(dev_priv, 4)) { > + if (GT_GEN_RANGE(dev_priv, 3, 4)) { > seq_printf(m, "DDC = 0x%08x\n", > I915_READ(DCC)); > seq_printf(m, "DDC2 = 0x%08x\n", > @@ -4262,7 +4262,7 @@ i915_cache_sharing_get(void *data, u64 *val) > struct drm_i915_private *dev_priv = data; > u32 snpcr; > > - if (!(GT_GEN(dev_priv, 6) || GT_GEN(dev_priv, 7))) > + if (!(GT_GEN_RANGE(dev_priv, 6, 7))) > return -ENODEV; > > intel_runtime_pm_get(dev_priv); > @@ -4282,7 +4282,7 @@ i915_cache_sharing_set(void *data, u64 val) > struct drm_i915_private *dev_priv = data; > u32 snpcr; > > - if (!(GT_GEN(dev_priv, 6) || GT_GEN(dev_priv, 7))) > + if (!(GT_GEN_RANGE(dev_priv, 6, 7))) > return -ENODEV; > > if (val > 3) > diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c > index 0de8ce65053d..e754c0306425 100644 > --- a/drivers/gpu/drm/i915/i915_gpu_error.c > +++ b/drivers/gpu/drm/i915/i915_gpu_error.c > @@ -1673,7 +1673,7 @@ static void capture_reg_state(struct i915_gpu_state *error) > error->ccid = I915_READ(CCID); > > /* 3: Feature specific registers */ > - if (GT_GEN(dev_priv, 6) || GT_GEN(dev_priv, 7)) { > + if (GT_GEN_RANGE(dev_priv, 6, 7)) { > error->gam_ecochk = I915_READ(GAM_ECOCHK); > error->gac_eco = I915_READ(GAC_ECO_BITS); > } > diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c > index 5cc1ffa621a7..b5154891e0d7 100644 > --- a/drivers/gpu/drm/i915/i915_perf.c > +++ b/drivers/gpu/drm/i915/i915_perf.c > @@ -3449,7 +3449,7 @@ void i915_perf_init(struct drm_i915_private *dev_priv) > dev_priv->perf.oa.ops.read = gen8_oa_read; > dev_priv->perf.oa.ops.oa_hw_tail_read = gen8_oa_hw_tail_read; > > - if (GT_GEN(dev_priv, 8) || GT_GEN(dev_priv, 9)) { > + if (GT_GEN_RANGE(dev_priv, 8, 9)) { > dev_priv->perf.oa.ops.is_valid_b_counter_reg = > gen7_is_valid_b_counter_addr; > dev_priv->perf.oa.ops.is_valid_mux_reg = > diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c > index dbc97c29f7e5..cbc76b7b8b74 100644 > --- a/drivers/gpu/drm/i915/intel_crt.c > +++ b/drivers/gpu/drm/i915/intel_crt.c > @@ -322,7 +322,7 @@ intel_crt_mode_valid(struct drm_connector *connector, > * DAC limit supposedly 355 MHz. > */ > max_clock = 270000; > - else if (GT_GEN(dev_priv, 3) || GT_GEN(dev_priv, 4)) > + else if (GT_GEN_RANGE(dev_priv, 3, 4)) > max_clock = 400000; > else > max_clock = 350000; > diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c > index bad3eb2428ac..1761529f3e69 100644 > --- a/drivers/gpu/drm/i915/intel_device_info.c > +++ b/drivers/gpu/drm/i915/intel_device_info.c > @@ -783,7 +783,7 @@ void intel_device_info_runtime_init(struct intel_device_info *info) > DRM_INFO("Display disabled (module parameter)\n"); > info->num_pipes = 0; > } else if (info->num_pipes > 0 && > - (GT_GEN(dev_priv, 7) || GT_GEN(dev_priv, 8)) && > + (GT_GEN_RANGE(dev_priv, 7, 8)) && > HAS_PCH_SPLIT(dev_priv)) { > u32 fuse_strap = I915_READ(FUSE_STRAP); > u32 sfuse_strap = I915_READ(SFUSE_STRAP); > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c > index 454a7e86adc8..0288169c1462 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -10684,7 +10684,7 @@ int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_crtc_stat > * the w/a on all three platforms. > */ > if (plane->id == PLANE_SPRITE0 && > - (GT_GEN(dev_priv, 5) || GT_GEN(dev_priv, 6) || > + (GT_GEN_RANGE(dev_priv, 5, 6) || > IS_IVYBRIDGE(dev_priv)) && > (turn_on || (!needs_scaling(old_plane_state) && > needs_scaling(to_intel_plane_state(plane_state))))) > diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c > index fdd6966e5b95..db1a5d07e2e0 100644 > --- a/drivers/gpu/drm/i915/intel_engine_cs.c > +++ b/drivers/gpu/drm/i915/intel_engine_cs.c > @@ -438,7 +438,7 @@ void intel_engine_init_global_seqno(struct intel_engine_cs *engine, u32 seqno) > * the semaphore value, then when the seqno moves backwards all > * future waits will complete instantly (causing rendering corruption). > */ > - if (GT_GEN(dev_priv, 6) || GT_GEN(dev_priv, 7)) { > + if (GT_GEN_RANGE(dev_priv, 6, 7)) { > I915_WRITE(RING_SYNC_0(engine->mmio_base), 0); > I915_WRITE(RING_SYNC_1(engine->mmio_base), 0); > if (HAS_VEBOX(dev_priv)) > diff --git a/drivers/gpu/drm/i915/intel_fifo_underrun.c b/drivers/gpu/drm/i915/intel_fifo_underrun.c > index ff76da50153d..e1d48193ab0b 100644 > --- a/drivers/gpu/drm/i915/intel_fifo_underrun.c > +++ b/drivers/gpu/drm/i915/intel_fifo_underrun.c > @@ -260,7 +260,7 @@ static bool __intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev, > > if (HAS_GMCH_DISPLAY(dev_priv)) > i9xx_set_fifo_underrun_reporting(dev, pipe, enable, old); > - else if (GT_GEN(dev_priv, 5) || GT_GEN(dev_priv, 6)) > + else if (GT_GEN_RANGE(dev_priv, 5, 6)) > ironlake_set_fifo_underrun_reporting(dev, pipe, enable); > else if (GT_GEN(dev_priv, 7)) > ivybridge_set_fifo_underrun_reporting(dev, pipe, enable, old); > diff --git a/drivers/gpu/drm/i915/intel_pipe_crc.c b/drivers/gpu/drm/i915/intel_pipe_crc.c > index 597e52bc15e8..1ffa81f0be3c 100644 > --- a/drivers/gpu/drm/i915/intel_pipe_crc.c > +++ b/drivers/gpu/drm/i915/intel_pipe_crc.c > @@ -433,7 +433,7 @@ static int get_new_crc_ctl_reg(struct drm_i915_private *dev_priv, > return i9xx_pipe_crc_ctl_reg(dev_priv, pipe, source, val); > else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) > return vlv_pipe_crc_ctl_reg(dev_priv, pipe, source, val); > - else if (GT_GEN(dev_priv, 5) || GT_GEN(dev_priv, 6)) > + else if (GT_GEN_RANGE(dev_priv, 5, 6)) > return ilk_pipe_crc_ctl_reg(source, val); > else > return ivb_pipe_crc_ctl_reg(dev_priv, pipe, source, val, set_wa); > @@ -550,7 +550,7 @@ intel_is_valid_crc_source(struct drm_i915_private *dev_priv, > return i9xx_crc_source_valid(dev_priv, source); > else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) > return vlv_crc_source_valid(dev_priv, source); > - else if (GT_GEN(dev_priv, 5) || GT_GEN(dev_priv, 6)) > + else if (GT_GEN_RANGE(dev_priv, 5, 6)) > return ilk_crc_source_valid(dev_priv, source); > else > return ivb_crc_source_valid(dev_priv, source); > diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c > index f488cf5d1f43..88ffcde16fc6 100644 > --- a/drivers/gpu/drm/i915/intel_uncore.c > +++ b/drivers/gpu/drm/i915/intel_uncore.c > @@ -528,7 +528,7 @@ check_for_unclaimed_mmio(struct drm_i915_private *dev_priv) > if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) > ret |= vlv_check_for_unclaimed_mmio(dev_priv); > > - if (GT_GEN(dev_priv, 6) || GT_GEN(dev_priv, 7)) > + if (GT_GEN_RANGE(dev_priv, 6, 7)) > ret |= gen6_check_for_fifo_debug(dev_priv); > > return ret; > @@ -556,7 +556,7 @@ static void __intel_uncore_early_sanitize(struct drm_i915_private *dev_priv, > dev_priv->uncore.funcs.force_wake_get(dev_priv, > restore_forcewake); > > - if (GT_GEN(dev_priv, 6) || GT_GEN(dev_priv, 7)) > + if (GT_GEN_RANGE(dev_priv, 6, 7)) > dev_priv->uncore.fifo_count = > fifo_free_entries(dev_priv); > spin_unlock_irq(&dev_priv->uncore.lock); > @@ -1437,7 +1437,7 @@ static void intel_uncore_fw_domains_init(struct drm_i915_private *dev_priv) > FORCEWAKE_MEDIA_VEBOX_GEN11(i), > FORCEWAKE_ACK_MEDIA_VEBOX_GEN11(i)); > } > - } else if (GT_GEN(dev_priv, 10) || GT_GEN(dev_priv, 9)) { > + } else if (GT_GEN_RANGE(dev_priv, 9, 10)) { > dev_priv->uncore.funcs.force_wake_get = > fw_domains_get_with_fallback; > dev_priv->uncore.funcs.force_wake_put = fw_domains_put; > -- > 2.19.1.1.g56c4683e68 > _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 38+ messages in thread
* [PATCH v2 7/7] drm/i915: remove INTEL_GEN macro 2018-11-06 21:51 [PATCH v2 0/7] Make GEN macros more similar Lucas De Marchi ` (5 preceding siblings ...) 2018-11-06 21:51 ` [PATCH v2 6/7] drm/i915: merge gen checks to use range Lucas De Marchi @ 2018-11-06 21:51 ` Lucas De Marchi 2018-11-07 10:05 ` [PATCH v2 0/7] Make GEN macros more similar Tvrtko Ursulin ` (4 subsequent siblings) 11 siblings, 0 replies; 38+ messages in thread From: Lucas De Marchi @ 2018-11-06 21:51 UTC (permalink / raw) To: intel-gfx; +Cc: Rodrigo Vivi After all the conversion to prefer using GT_GEN() and GT_GEN_RANGE() macros, let's remove INTEL_GEN() because a) it only returns the GT gen and b) leaving it there makes it too easy for people using it as they shouldn't. There are some cases in which is ok to get the gen field, like debug messages, switch and missing cases etc. For those, let's use the slightly more verbose route through INTEL_INFO(). This was generated with: @@ expression E; @@ - INTEL_GEN(E) + INTEL_INFO(E)->gen Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> --- drivers/gpu/drm/i915/i915_debugfs.c | 2 +- drivers/gpu/drm/i915/i915_drv.h | 1 - drivers/gpu/drm/i915/i915_gem_execbuffer.c | 4 ++-- drivers/gpu/drm/i915/i915_gem_render_state.c | 2 +- drivers/gpu/drm/i915/i915_gem_stolen.c | 2 +- drivers/gpu/drm/i915/i915_gpu_error.c | 2 +- drivers/gpu/drm/i915/i915_perf.c | 4 ++-- drivers/gpu/drm/i915/intel_bios.c | 2 +- drivers/gpu/drm/i915/intel_dp.c | 2 +- drivers/gpu/drm/i915/intel_engine_cs.c | 10 +++++----- drivers/gpu/drm/i915/intel_lrc.c | 8 ++++---- drivers/gpu/drm/i915/intel_workarounds.c | 6 +++--- drivers/gpu/drm/i915/selftests/huge_pages.c | 2 +- drivers/gpu/drm/i915/selftests/i915_gem_context.c | 2 +- drivers/gpu/drm/i915/selftests/i915_request.c | 2 +- 15 files changed, 25 insertions(+), 26 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index 9ffcf0be0589..dc8d12666834 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -43,7 +43,7 @@ static int i915_capabilities(struct seq_file *m, void *data) const struct intel_device_info *info = INTEL_INFO(dev_priv); struct drm_printer p = drm_seq_file_printer(m); - seq_printf(m, "gen: %d\n", INTEL_GEN(dev_priv)); + seq_printf(m, "gen: %d\n", INTEL_INFO(dev_priv)->gen); seq_printf(m, "platform: %s\n", intel_platform_name(info->platform)); seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev_priv)); diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 4440ac225441..7d7593dcefeb 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -2354,7 +2354,6 @@ intel_info(const struct drm_i915_private *dev_priv) #define INTEL_INFO(dev_priv) intel_info((dev_priv)) #define DRIVER_CAPS(dev_priv) (&(dev_priv)->caps) -#define INTEL_GEN(dev_priv) ((dev_priv)->info.gen) #define INTEL_DEVID(dev_priv) ((dev_priv)->info.device_id) #define REVID_FOREVER 0xff diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c index 9b936e5877fe..dad86d2bc8dc 100644 --- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c +++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c @@ -261,7 +261,7 @@ struct i915_execbuffer { struct drm_mm_node node; /** temporary GTT binding */ unsigned long vaddr; /** Current kmap address */ unsigned long page; /** Currently mapped page index */ - unsigned int gen; /** Cached value of INTEL_GEN */ + unsigned int gen; /** Cached value of device_info */ bool use_64bit_reloc : 1; bool has_llc : 1; bool has_fence : 1; @@ -907,7 +907,7 @@ static void reloc_cache_init(struct reloc_cache *cache, cache->page = -1; cache->vaddr = 0; /* Must be a variable in the struct to allow GCC to unroll. */ - cache->gen = INTEL_GEN(i915); + cache->gen = INTEL_INFO(i915)->gen; cache->has_llc = HAS_LLC(i915); cache->use_64bit_reloc = HAS_64BIT_RELOC(i915); cache->has_fence = cache->gen < 4; diff --git a/drivers/gpu/drm/i915/i915_gem_render_state.c b/drivers/gpu/drm/i915/i915_gem_render_state.c index 90baf9086d0a..2f2d04fd1156 100644 --- a/drivers/gpu/drm/i915/i915_gem_render_state.c +++ b/drivers/gpu/drm/i915/i915_gem_render_state.c @@ -45,7 +45,7 @@ render_state_get_rodata(const struct intel_engine_cs *engine) if (engine->id != RCS) return NULL; - switch (INTEL_GEN(engine->i915)) { + switch (INTEL_INFO(engine->i915)->gen) { case 6: return &gen6_null_state; case 7: diff --git a/drivers/gpu/drm/i915/i915_gem_stolen.c b/drivers/gpu/drm/i915/i915_gem_stolen.c index b346b874a82f..9b6d476fb736 100644 --- a/drivers/gpu/drm/i915/i915_gem_stolen.c +++ b/drivers/gpu/drm/i915/i915_gem_stolen.c @@ -404,7 +404,7 @@ int i915_gem_init_stolen(struct drm_i915_private *dev_priv) reserved_base = stolen_top; reserved_size = 0; - switch (INTEL_GEN(dev_priv)) { + switch (INTEL_INFO(dev_priv)->gen) { case 2: case 3: break; diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c index e754c0306425..42815e7eeeb0 100644 --- a/drivers/gpu/drm/i915/i915_gpu_error.c +++ b/drivers/gpu/drm/i915/i915_gpu_error.c @@ -1718,7 +1718,7 @@ static void i915_error_capture_msg(struct drm_i915_private *dev_priv, len = scnprintf(error->error_msg, sizeof(error->error_msg), "GPU HANG: ecode %d:%d:0x%08x", - INTEL_GEN(dev_priv), engine_id, ecode); + INTEL_INFO(dev_priv)->gen, engine_id, ecode); if (engine_id != -1 && error->engine[engine_id].context.pid) len += scnprintf(error->error_msg + len, diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c index b5154891e0d7..8275f7ebbade 100644 --- a/drivers/gpu/drm/i915/i915_perf.c +++ b/drivers/gpu/drm/i915/i915_perf.c @@ -1236,7 +1236,7 @@ static int oa_get_render_ctx_id(struct i915_perf_stream *stream) if (IS_ERR(ce)) return PTR_ERR(ce); - switch (INTEL_GEN(i915)) { + switch (INTEL_INFO(i915)->gen) { case 7: { /* * On Haswell we don't do any post processing of the reports @@ -1292,7 +1292,7 @@ static int oa_get_render_ctx_id(struct i915_perf_stream *stream) } default: - MISSING_CASE(INTEL_GEN(i915)); + MISSING_CASE(INTEL_INFO(i915)->gen); } DRM_DEBUG_DRIVER("filtering on ctx_id=0x%x ctx_id_mask=0x%x\n", diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c index 69e41089d7de..04d0bbb09cbf 100644 --- a/drivers/gpu/drm/i915/intel_bios.c +++ b/drivers/gpu/drm/i915/intel_bios.c @@ -389,7 +389,7 @@ parse_sdvo_panel_data(struct drm_i915_private *dev_priv, static int intel_bios_ssc_frequency(struct drm_i915_private *dev_priv, bool alternate) { - switch (INTEL_GEN(dev_priv)) { + switch (INTEL_INFO(dev_priv)->gen) { case 2: return alternate ? 66667 : 48000; case 3: diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index a554c31ffb70..904f27598a99 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -5039,7 +5039,7 @@ bool intel_digital_port_connected(struct intel_encoder *encoder) else if (GT_GEN(dev_priv, 5)) return ilk_digital_port_connected(encoder); - MISSING_CASE(INTEL_GEN(dev_priv)); + MISSING_CASE(INTEL_INFO(dev_priv)->gen); return false; } diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c index db1a5d07e2e0..7e72e1408d3b 100644 --- a/drivers/gpu/drm/i915/intel_engine_cs.c +++ b/drivers/gpu/drm/i915/intel_engine_cs.c @@ -195,9 +195,9 @@ __intel_engine_context_size(struct drm_i915_private *dev_priv, u8 class) switch (class) { case RENDER_CLASS: - switch (INTEL_GEN(dev_priv)) { + switch (INTEL_INFO(dev_priv)->gen) { default: - MISSING_CASE(INTEL_GEN(dev_priv)); + MISSING_CASE(INTEL_INFO(dev_priv)->gen); return DEFAULT_LR_CONTEXT_RENDER_SIZE; case 11: return GEN11_LR_CONTEXT_RENDER_SIZE; @@ -245,7 +245,7 @@ static u32 __engine_mmio_base(struct drm_i915_private *i915, int i; for (i = 0; i < MAX_MMIO_BASES; i++) - if (INTEL_GEN(i915) >= bases[i].gen) + if (INTEL_INFO(i915)->gen >= bases[i].gen) break; GEM_BUG_ON(i == MAX_MMIO_BASES); @@ -891,7 +891,7 @@ void intel_engine_get_instdone(struct intel_engine_cs *engine, memset(instdone, 0, sizeof(*instdone)); - switch (INTEL_GEN(dev_priv)) { + switch (INTEL_INFO(dev_priv)->gen) { default: instdone->instdone = I915_READ(RING_INSTDONE(mmio_base)); @@ -1189,7 +1189,7 @@ void intel_engine_lost_context(struct intel_engine_cs *engine) bool intel_engine_can_store_dword(struct intel_engine_cs *engine) { - switch (INTEL_GEN(engine->i915)) { + switch (INTEL_INFO(engine->i915)->gen) { case 2: return false; /* uses physical not virtual addresses */ case 3: diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c index fd24c3939f46..e5ab0c9b0cf0 100644 --- a/drivers/gpu/drm/i915/intel_lrc.c +++ b/drivers/gpu/drm/i915/intel_lrc.c @@ -1518,7 +1518,7 @@ static int intel_init_workaround_bb(struct intel_engine_cs *engine) if (GEM_DEBUG_WARN_ON(engine->id != RCS)) return -EINVAL; - switch (INTEL_GEN(engine->i915)) { + switch (INTEL_INFO(engine->i915)->gen) { case 11: return 0; case 10: @@ -1534,7 +1534,7 @@ static int intel_init_workaround_bb(struct intel_engine_cs *engine) wa_bb_fn[1] = NULL; break; default: - MISSING_CASE(INTEL_GEN(engine->i915)); + MISSING_CASE(INTEL_INFO(engine->i915)->gen); return 0; } @@ -2436,9 +2436,9 @@ static u32 intel_lr_indirect_ctx_offset(struct intel_engine_cs *engine) { u32 indirect_ctx_offset; - switch (INTEL_GEN(engine->i915)) { + switch (INTEL_INFO(engine->i915)->gen) { default: - MISSING_CASE(INTEL_GEN(engine->i915)); + MISSING_CASE(INTEL_INFO(engine->i915)->gen); /* fall through */ case 11: indirect_ctx_offset = diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c index 1efaa5b5dbcc..f4a820092b4c 100644 --- a/drivers/gpu/drm/i915/intel_workarounds.c +++ b/drivers/gpu/drm/i915/intel_workarounds.c @@ -538,7 +538,7 @@ int intel_ctx_workarounds_init(struct drm_i915_private *dev_priv) else if (IS_ICELAKE(dev_priv)) err = icl_ctx_workarounds_init(dev_priv); else - MISSING_CASE(INTEL_GEN(dev_priv)); + MISSING_CASE(INTEL_INFO(dev_priv)->gen); if (err) return err; @@ -937,7 +937,7 @@ void intel_gt_workarounds_apply(struct drm_i915_private *dev_priv) else if (IS_ICELAKE(dev_priv)) icl_gt_workarounds_apply(dev_priv); else - MISSING_CASE(INTEL_GEN(dev_priv)); + MISSING_CASE(INTEL_INFO(dev_priv)->gen); } struct whitelist { @@ -1054,7 +1054,7 @@ static struct whitelist *whitelist_build(struct intel_engine_cs *engine, else if (IS_ICELAKE(i915)) icl_whitelist_build(w); else - MISSING_CASE(INTEL_GEN(i915)); + MISSING_CASE(INTEL_INFO(i915)->gen); return w; } diff --git a/drivers/gpu/drm/i915/selftests/huge_pages.c b/drivers/gpu/drm/i915/selftests/huge_pages.c index 26c065c8d2c0..5fe9cb6c433f 100644 --- a/drivers/gpu/drm/i915/selftests/huge_pages.c +++ b/drivers/gpu/drm/i915/selftests/huge_pages.c @@ -893,7 +893,7 @@ static struct i915_vma * gpu_write_dw(struct i915_vma *vma, u64 offset, u32 val) { struct drm_i915_private *i915 = vma->vm->i915; - const int gen = INTEL_GEN(i915); + const int gen = INTEL_INFO(i915)->gen; unsigned int count = vma->size >> PAGE_SHIFT; struct drm_i915_gem_object *obj; struct i915_vma *batch; diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_context.c b/drivers/gpu/drm/i915/selftests/i915_gem_context.c index dd5424f8faa9..fe800cb24180 100644 --- a/drivers/gpu/drm/i915/selftests/i915_gem_context.c +++ b/drivers/gpu/drm/i915/selftests/i915_gem_context.c @@ -253,7 +253,7 @@ static struct i915_vma * gpu_fill_dw(struct i915_vma *vma, u64 offset, unsigned long count, u32 value) { struct drm_i915_gem_object *obj; - const int gen = INTEL_GEN(vma->vm->i915); + const int gen = INTEL_INFO(vma->vm->i915)->gen; unsigned long n, size; u32 *cmd; int err; diff --git a/drivers/gpu/drm/i915/selftests/i915_request.c b/drivers/gpu/drm/i915/selftests/i915_request.c index 07e557815308..cce1e3c9c28b 100644 --- a/drivers/gpu/drm/i915/selftests/i915_request.c +++ b/drivers/gpu/drm/i915/selftests/i915_request.c @@ -564,7 +564,7 @@ static struct i915_vma *recursive_batch(struct drm_i915_private *i915) struct i915_address_space *vm = ctx->ppgtt ? &ctx->ppgtt->vm : &i915->ggtt.vm; struct drm_i915_gem_object *obj; - const int gen = INTEL_GEN(i915); + const int gen = INTEL_INFO(i915)->gen; struct i915_vma *vma; u32 *cmd; int err; -- 2.19.1.1.g56c4683e68 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 38+ messages in thread
* Re: [PATCH v2 0/7] Make GEN macros more similar 2018-11-06 21:51 [PATCH v2 0/7] Make GEN macros more similar Lucas De Marchi ` (6 preceding siblings ...) 2018-11-06 21:51 ` [PATCH v2 7/7] drm/i915: remove INTEL_GEN macro Lucas De Marchi @ 2018-11-07 10:05 ` Tvrtko Ursulin 2018-11-08 0:57 ` Lucas De Marchi 2018-11-07 14:10 ` ✗ Fi.CI.CHECKPATCH: warning for Make GEN macros more similar (rev2) Patchwork ` (3 subsequent siblings) 11 siblings, 1 reply; 38+ messages in thread From: Tvrtko Ursulin @ 2018-11-07 10:05 UTC (permalink / raw) To: Lucas De Marchi, intel-gfx; +Cc: Rodrigo Vivi On 06/11/2018 21:51, Lucas De Marchi wrote: > This is the second version of the series trying to make GEN checks > more similar. These or roughly the changes from v1: > > - We don't have a single macro receiving 2 or 3 parameters. Now there > is GT_GEN_RANGE(), and GT_GEN(). The firs is the conversion from > IS_GEN() while the second is the conversion from IS_GEN<N>() > - Bring GEN_FOREVER back to be used with above macros > - Patch converting <, <=, ==, >, >= checks using INTEL_GEN() to > use the macros above was added > - INTEL_GEN() is removed to avoid it being used when we should prefer > the new macros > > The idea of the names is to pave the way for checks of the display version, > which would be named DISPLAY_GEN(), DISPLAY_GEN_RANGE(). > > In the commit messages we have the scripts to regenerate the patch to make > it easier to apply after the discussions and also to be able to convert > inflight patches. > > Sorry in advance for the noise this causes in the codebase, but hopefully > it is for the greater good. > > > Lucas De Marchi (6): > Revert "drm/i915: Kill GEN_FOREVER" > drm/i915: replace IS_GEN<N> with GT_GEN(..., N) > drm/i915: rename IS_GEN9_* to GT_GEN9_* > drm/i915: replace gen checks using operators by GT_GEN/GT_GEN_RANGE I have reservations about this patch, where I think forcing only one flavour maybe is not the best thing. Because for plain if-ladder cases it feels more readable to stick with the current scheme of arithmetic comparisons. And it is more efficient in code as well. Range checks are on the other hand useful either when combined in the same conditional as some other bitmask based test, or when both ends of the comparison edge are bound. > drm/i915: merge gen checks to use range > drm/i915: remove INTEL_GEN macro I have reservations about this as as well, especially considering the previous paragraph. But even on it's own I am not sure we want to go back to more verbose. Perhaps in the new scheme of things it should be renamed to INTEL_GT_GEN? I know it doesn't fit nicely with the naming scheme of GT/DISPLAY_GEN.. so maybe: GT_GEN -> IS_GT_GEN GT_GEN_RANGE -> IS_GT_GEN_RANGE INTEL_GEN -> GT_GEN (but churn!?) This leaves GT and DISPLAY namespaces completely parallel in syntax and semantics. Regards, Tvrtko > > Rodrigo Vivi (1): > drm/i915: Rename IS_GEN to GT_RANGE > > drivers/gpu/drm/i915/gvt/gtt.c | 4 +- > drivers/gpu/drm/i915/gvt/handlers.c | 2 +- > drivers/gpu/drm/i915/gvt/vgpu.c | 4 +- > drivers/gpu/drm/i915/i915_cmd_parser.c | 2 +- > drivers/gpu/drm/i915/i915_debugfs.c | 145 +++++---- > drivers/gpu/drm/i915/i915_drv.c | 50 +-- > drivers/gpu/drm/i915/i915_drv.h | 67 ++-- > drivers/gpu/drm/i915/i915_gem.c | 30 +- > drivers/gpu/drm/i915/i915_gem_context.c | 4 +- > drivers/gpu/drm/i915/i915_gem_execbuffer.c | 10 +- > drivers/gpu/drm/i915/i915_gem_fence_reg.c | 16 +- > drivers/gpu/drm/i915/i915_gem_gtt.c | 36 +- > drivers/gpu/drm/i915/i915_gem_render_state.c | 2 +- > drivers/gpu/drm/i915/i915_gem_stolen.c | 15 +- > drivers/gpu/drm/i915/i915_gem_tiling.c | 12 +- > drivers/gpu/drm/i915/i915_gpu_error.c | 62 ++-- > drivers/gpu/drm/i915/i915_irq.c | 120 +++---- > drivers/gpu/drm/i915/i915_perf.c | 14 +- > drivers/gpu/drm/i915/i915_pmu.c | 6 +- > drivers/gpu/drm/i915/i915_reg.h | 8 +- > drivers/gpu/drm/i915/i915_suspend.c | 24 +- > drivers/gpu/drm/i915/i915_sysfs.c | 2 +- > drivers/gpu/drm/i915/intel_atomic.c | 4 +- > drivers/gpu/drm/i915/intel_audio.c | 4 +- > drivers/gpu/drm/i915/intel_bios.c | 12 +- > drivers/gpu/drm/i915/intel_cdclk.c | 28 +- > drivers/gpu/drm/i915/intel_color.c | 6 +- > drivers/gpu/drm/i915/intel_crt.c | 12 +- > drivers/gpu/drm/i915/intel_csr.c | 2 +- > drivers/gpu/drm/i915/intel_ddi.c | 58 ++-- > drivers/gpu/drm/i915/intel_device_info.c | 46 +-- > drivers/gpu/drm/i915/intel_display.c | 308 +++++++++--------- > drivers/gpu/drm/i915/intel_dp.c | 82 ++--- > drivers/gpu/drm/i915/intel_dp_mst.c | 2 +- > drivers/gpu/drm/i915/intel_dpll_mgr.c | 10 +- > drivers/gpu/drm/i915/intel_drv.h | 2 +- > drivers/gpu/drm/i915/intel_engine_cs.c | 44 +-- > drivers/gpu/drm/i915/intel_fbc.c | 52 +-- > drivers/gpu/drm/i915/intel_fifo_underrun.c | 8 +- > drivers/gpu/drm/i915/intel_guc_fw.c | 4 +- > drivers/gpu/drm/i915/intel_hangcheck.c | 6 +- > drivers/gpu/drm/i915/intel_hdcp.c | 2 +- > drivers/gpu/drm/i915/intel_hdmi.c | 18 +- > drivers/gpu/drm/i915/intel_i2c.c | 14 +- > drivers/gpu/drm/i915/intel_lrc.c | 32 +- > drivers/gpu/drm/i915/intel_lvds.c | 14 +- > drivers/gpu/drm/i915/intel_mocs.c | 8 +- > drivers/gpu/drm/i915/intel_overlay.c | 12 +- > drivers/gpu/drm/i915/intel_panel.c | 20 +- > drivers/gpu/drm/i915/intel_pipe_crc.c | 12 +- > drivers/gpu/drm/i915/intel_pm.c | 196 +++++------ > drivers/gpu/drm/i915/intel_psr.c | 26 +- > drivers/gpu/drm/i915/intel_ringbuffer.c | 68 ++-- > drivers/gpu/drm/i915/intel_ringbuffer.h | 4 +- > drivers/gpu/drm/i915/intel_runtime_pm.c | 32 +- > drivers/gpu/drm/i915/intel_sdvo.c | 14 +- > drivers/gpu/drm/i915/intel_sprite.c | 34 +- > drivers/gpu/drm/i915/intel_tv.c | 2 +- > drivers/gpu/drm/i915/intel_uc.c | 4 +- > drivers/gpu/drm/i915/intel_uncore.c | 60 ++-- > drivers/gpu/drm/i915/intel_wopcm.c | 8 +- > drivers/gpu/drm/i915/intel_workarounds.c | 20 +- > drivers/gpu/drm/i915/selftests/huge_pages.c | 2 +- > .../drm/i915/selftests/i915_gem_coherency.c | 4 +- > .../gpu/drm/i915/selftests/i915_gem_context.c | 10 +- > .../gpu/drm/i915/selftests/i915_gem_object.c | 12 +- > drivers/gpu/drm/i915/selftests/i915_request.c | 2 +- > .../gpu/drm/i915/selftests/intel_hangcheck.c | 8 +- > drivers/gpu/drm/i915/selftests/intel_lrc.c | 2 +- > drivers/gpu/drm/i915/selftests/intel_uncore.c | 2 +- > .../drm/i915/selftests/intel_workarounds.c | 2 +- > drivers/gpu/drm/i915/vlv_dsi.c | 40 +-- > 72 files changed, 1003 insertions(+), 1006 deletions(-) > _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [PATCH v2 0/7] Make GEN macros more similar 2018-11-07 10:05 ` [PATCH v2 0/7] Make GEN macros more similar Tvrtko Ursulin @ 2018-11-08 0:57 ` Lucas De Marchi 2018-11-08 11:23 ` Tvrtko Ursulin 0 siblings, 1 reply; 38+ messages in thread From: Lucas De Marchi @ 2018-11-08 0:57 UTC (permalink / raw) To: Tvrtko Ursulin; +Cc: intel-gfx, Rodrigo Vivi On Wed, Nov 07, 2018 at 10:05:19AM +0000, Tvrtko Ursulin wrote: > > On 06/11/2018 21:51, Lucas De Marchi wrote: > > This is the second version of the series trying to make GEN checks > > more similar. These or roughly the changes from v1: > > > > - We don't have a single macro receiving 2 or 3 parameters. Now there > > is GT_GEN_RANGE(), and GT_GEN(). The firs is the conversion from > > IS_GEN() while the second is the conversion from IS_GEN<N>() > > - Bring GEN_FOREVER back to be used with above macros > > - Patch converting <, <=, ==, >, >= checks using INTEL_GEN() to > > use the macros above was added > > - INTEL_GEN() is removed to avoid it being used when we should prefer > > the new macros > > > > The idea of the names is to pave the way for checks of the display version, > > which would be named DISPLAY_GEN(), DISPLAY_GEN_RANGE(). > > > > In the commit messages we have the scripts to regenerate the patch to make > > it easier to apply after the discussions and also to be able to convert > > inflight patches. > > > > Sorry in advance for the noise this causes in the codebase, but hopefully > > it is for the greater good. > > > > > > Lucas De Marchi (6): > > Revert "drm/i915: Kill GEN_FOREVER" > > drm/i915: replace IS_GEN<N> with GT_GEN(..., N) > > drm/i915: rename IS_GEN9_* to GT_GEN9_* > > drm/i915: replace gen checks using operators by GT_GEN/GT_GEN_RANGE > > I have reservations about this patch, where I think forcing only one flavour > maybe is not the best thing. Because for plain if-ladder cases it feels more > readable to stick with the current scheme of arithmetic comparisons. And it > is more efficient in code as well. > > Range checks are on the other hand useful either when combined in the same > conditional as some other bitmask based test, or when both ends of the > comparison edge are bound. So are you against changing the == to use the macros, changing the >=, >, <, <=, or all of them? Looking at the changes to ==, they seem very reasonable and in a few cases it allowed the next patch to merge them in a GT_GEN_RANGE() -- yes the patch ordering was on purpose to allow that. The others are indeed debatable. However IMO for the cases it makes sense, there's always the fallback if (dev_priv->info.gen == 10) ... else if (dev_priv->info.gen == 11) ... else if (dev_priv->info.gen < 5) ... We can go on a case by case manner in this patch rather than the mass conversion for these. > > > drm/i915: merge gen checks to use range > > drm/i915: remove INTEL_GEN macro > > I have reservations about this as as well, especially considering the > previous paragraph. But even on it's own I am not sure we want to go back to > more verbose. see above. IMO it's not actually so verbose as one would think. if (INTEL_GEN(dev_priv) == 11) vs if (dev_priv->info.gen == 11) The "verbose" version is actually one character less and one lookup less to what the macro is doing underneath. Of course that means a lot of churn to the codebase when/if we change where the gen number is located, but that number is at the same place since its introduction in 2010 (commit c96c3a8cb7fadcb33d9a5ebe35fcee8b7d0a7946) > Perhaps in the new scheme of things it should be renamed to INTEL_GT_GEN? I > know it doesn't fit nicely with the naming scheme of GT/DISPLAY_GEN.. so > maybe: > > GT_GEN -> IS_GT_GEN > GT_GEN_RANGE -> IS_GT_GEN_RANGE > INTEL_GEN -> GT_GEN (but churn!?) I still think INTEL_GEN() is not bringing much clarity and forcing the other macros to have the IS_ prefix. > > This leaves GT and DISPLAY namespaces completely parallel in syntax and > semantics. > > Regards, > > Tvrtko > > > > > > > Rodrigo Vivi (1): > > drm/i915: Rename IS_GEN to GT_RANGE > > > > drivers/gpu/drm/i915/gvt/gtt.c | 4 +- > > drivers/gpu/drm/i915/gvt/handlers.c | 2 +- > > drivers/gpu/drm/i915/gvt/vgpu.c | 4 +- > > drivers/gpu/drm/i915/i915_cmd_parser.c | 2 +- > > drivers/gpu/drm/i915/i915_debugfs.c | 145 +++++---- > > drivers/gpu/drm/i915/i915_drv.c | 50 +-- > > drivers/gpu/drm/i915/i915_drv.h | 67 ++-- > > drivers/gpu/drm/i915/i915_gem.c | 30 +- > > drivers/gpu/drm/i915/i915_gem_context.c | 4 +- > > drivers/gpu/drm/i915/i915_gem_execbuffer.c | 10 +- > > drivers/gpu/drm/i915/i915_gem_fence_reg.c | 16 +- > > drivers/gpu/drm/i915/i915_gem_gtt.c | 36 +- > > drivers/gpu/drm/i915/i915_gem_render_state.c | 2 +- > > drivers/gpu/drm/i915/i915_gem_stolen.c | 15 +- > > drivers/gpu/drm/i915/i915_gem_tiling.c | 12 +- > > drivers/gpu/drm/i915/i915_gpu_error.c | 62 ++-- > > drivers/gpu/drm/i915/i915_irq.c | 120 +++---- > > drivers/gpu/drm/i915/i915_perf.c | 14 +- > > drivers/gpu/drm/i915/i915_pmu.c | 6 +- > > drivers/gpu/drm/i915/i915_reg.h | 8 +- > > drivers/gpu/drm/i915/i915_suspend.c | 24 +- > > drivers/gpu/drm/i915/i915_sysfs.c | 2 +- > > drivers/gpu/drm/i915/intel_atomic.c | 4 +- > > drivers/gpu/drm/i915/intel_audio.c | 4 +- > > drivers/gpu/drm/i915/intel_bios.c | 12 +- > > drivers/gpu/drm/i915/intel_cdclk.c | 28 +- > > drivers/gpu/drm/i915/intel_color.c | 6 +- > > drivers/gpu/drm/i915/intel_crt.c | 12 +- > > drivers/gpu/drm/i915/intel_csr.c | 2 +- > > drivers/gpu/drm/i915/intel_ddi.c | 58 ++-- > > drivers/gpu/drm/i915/intel_device_info.c | 46 +-- > > drivers/gpu/drm/i915/intel_display.c | 308 +++++++++--------- > > drivers/gpu/drm/i915/intel_dp.c | 82 ++--- > > drivers/gpu/drm/i915/intel_dp_mst.c | 2 +- > > drivers/gpu/drm/i915/intel_dpll_mgr.c | 10 +- > > drivers/gpu/drm/i915/intel_drv.h | 2 +- > > drivers/gpu/drm/i915/intel_engine_cs.c | 44 +-- > > drivers/gpu/drm/i915/intel_fbc.c | 52 +-- > > drivers/gpu/drm/i915/intel_fifo_underrun.c | 8 +- > > drivers/gpu/drm/i915/intel_guc_fw.c | 4 +- > > drivers/gpu/drm/i915/intel_hangcheck.c | 6 +- > > drivers/gpu/drm/i915/intel_hdcp.c | 2 +- > > drivers/gpu/drm/i915/intel_hdmi.c | 18 +- > > drivers/gpu/drm/i915/intel_i2c.c | 14 +- > > drivers/gpu/drm/i915/intel_lrc.c | 32 +- > > drivers/gpu/drm/i915/intel_lvds.c | 14 +- > > drivers/gpu/drm/i915/intel_mocs.c | 8 +- > > drivers/gpu/drm/i915/intel_overlay.c | 12 +- > > drivers/gpu/drm/i915/intel_panel.c | 20 +- > > drivers/gpu/drm/i915/intel_pipe_crc.c | 12 +- > > drivers/gpu/drm/i915/intel_pm.c | 196 +++++------ > > drivers/gpu/drm/i915/intel_psr.c | 26 +- > > drivers/gpu/drm/i915/intel_ringbuffer.c | 68 ++-- > > drivers/gpu/drm/i915/intel_ringbuffer.h | 4 +- > > drivers/gpu/drm/i915/intel_runtime_pm.c | 32 +- > > drivers/gpu/drm/i915/intel_sdvo.c | 14 +- > > drivers/gpu/drm/i915/intel_sprite.c | 34 +- > > drivers/gpu/drm/i915/intel_tv.c | 2 +- > > drivers/gpu/drm/i915/intel_uc.c | 4 +- > > drivers/gpu/drm/i915/intel_uncore.c | 60 ++-- > > drivers/gpu/drm/i915/intel_wopcm.c | 8 +- > > drivers/gpu/drm/i915/intel_workarounds.c | 20 +- > > drivers/gpu/drm/i915/selftests/huge_pages.c | 2 +- > > .../drm/i915/selftests/i915_gem_coherency.c | 4 +- > > .../gpu/drm/i915/selftests/i915_gem_context.c | 10 +- > > .../gpu/drm/i915/selftests/i915_gem_object.c | 12 +- > > drivers/gpu/drm/i915/selftests/i915_request.c | 2 +- > > .../gpu/drm/i915/selftests/intel_hangcheck.c | 8 +- > > drivers/gpu/drm/i915/selftests/intel_lrc.c | 2 +- > > drivers/gpu/drm/i915/selftests/intel_uncore.c | 2 +- > > .../drm/i915/selftests/intel_workarounds.c | 2 +- > > drivers/gpu/drm/i915/vlv_dsi.c | 40 +-- > > 72 files changed, 1003 insertions(+), 1006 deletions(-) > > _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [PATCH v2 0/7] Make GEN macros more similar 2018-11-08 0:57 ` Lucas De Marchi @ 2018-11-08 11:23 ` Tvrtko Ursulin 2018-11-19 22:20 ` Lucas De Marchi 0 siblings, 1 reply; 38+ messages in thread From: Tvrtko Ursulin @ 2018-11-08 11:23 UTC (permalink / raw) To: Lucas De Marchi; +Cc: intel-gfx, Rodrigo Vivi On 08/11/2018 00:57, Lucas De Marchi wrote: > On Wed, Nov 07, 2018 at 10:05:19AM +0000, Tvrtko Ursulin wrote: >> >> On 06/11/2018 21:51, Lucas De Marchi wrote: >>> This is the second version of the series trying to make GEN checks >>> more similar. These or roughly the changes from v1: >>> >>> - We don't have a single macro receiving 2 or 3 parameters. Now there >>> is GT_GEN_RANGE(), and GT_GEN(). The firs is the conversion from >>> IS_GEN() while the second is the conversion from IS_GEN<N>() >>> - Bring GEN_FOREVER back to be used with above macros >>> - Patch converting <, <=, ==, >, >= checks using INTEL_GEN() to >>> use the macros above was added >>> - INTEL_GEN() is removed to avoid it being used when we should prefer >>> the new macros >>> >>> The idea of the names is to pave the way for checks of the display version, >>> which would be named DISPLAY_GEN(), DISPLAY_GEN_RANGE(). >>> >>> In the commit messages we have the scripts to regenerate the patch to make >>> it easier to apply after the discussions and also to be able to convert >>> inflight patches. >>> >>> Sorry in advance for the noise this causes in the codebase, but hopefully >>> it is for the greater good. >>> >>> >>> Lucas De Marchi (6): >>> Revert "drm/i915: Kill GEN_FOREVER" >>> drm/i915: replace IS_GEN<N> with GT_GEN(..., N) >>> drm/i915: rename IS_GEN9_* to GT_GEN9_* >>> drm/i915: replace gen checks using operators by GT_GEN/GT_GEN_RANGE >> >> I have reservations about this patch, where I think forcing only one flavour >> maybe is not the best thing. Because for plain if-ladder cases it feels more >> readable to stick with the current scheme of arithmetic comparisons. And it >> is more efficient in code as well. >> >> Range checks are on the other hand useful either when combined in the same >> conditional as some other bitmask based test, or when both ends of the >> comparison edge are bound. > > So are you against changing the == to use the macros, changing the >=, >, <, <=, > or all of them? Definitely not all of them. Just plain if ladders I think are definitely more readable in source and result in better code in the normal fashion of: if (gen >= 11) else if (gen >= 9) else if (gen >= 7) ... etc ... Where I think it makes sense is when either both edges are bound, like: if (gen < 11 || gen >= 8) if (gen >= 10 || gen == 8) But not sure how many of those there are. What definitely exists in large-ish numbers are: if (gen >= 11 || IS_PLATFORM) At some point I had a prototype which puts the gen and platform masks into a bag of bits and then, depending on bits locality, this too can be compressed to a single bitmask test. However I felt that was going too far, and the issue is achieving interesting bits locality for it too work. But I digress. > Looking at the changes to ==, they seem very reasonable and in a few cases it allowed > the next patch to merge them in a GT_GEN_RANGE() -- yes the patch ordering was on > purpose to allow that. Yep those are the good ones. > The others are indeed debatable. However IMO for the cases it makes sense, > there's always the fallback > > if (dev_priv->info.gen == 10) > ... > else if (dev_priv->info.gen == 11) > ... > else if (dev_priv->info.gen < 5) > ... > > We can go on a case by case manner in this patch rather than the mass conversion > for these. > >> >>> drm/i915: merge gen checks to use range >>> drm/i915: remove INTEL_GEN macro >> >> I have reservations about this as as well, especially considering the >> previous paragraph. But even on it's own I am not sure we want to go back to >> more verbose. > > see above. IMO it's not actually so verbose as one would think. > > if (INTEL_GEN(dev_priv) == 11) > vs > if (dev_priv->info.gen == 11) I think it should be: if (INTEL_INFO(dev_priv)->gen == 11) Which is a tiny bit longer.. > The "verbose" version is actually one character less and one lookup less > to what the macro is doing underneath. Of course that means a lot of churn > to the codebase when/if we change where the gen number is located, but that > number is at the same place since its introduction in 2010 > (commit c96c3a8cb7fadcb33d9a5ebe35fcee8b7d0a7946) I am pretty sure we went through patches to a) move towards INTEL_INFO and b) replace INTEL_INFO(dev_priv)->gen with INTEL_GEN. So I don't see an advantage of reverting that, just so that we can lose the IS_ prefix below. >> Perhaps in the new scheme of things it should be renamed to INTEL_GT_GEN? I >> know it doesn't fit nicely with the naming scheme of GT/DISPLAY_GEN.. so >> maybe: >> >> GT_GEN -> IS_GT_GEN >> GT_GEN_RANGE -> IS_GT_GEN_RANGE >> INTEL_GEN -> GT_GEN (but churn!?) > > I still think INTEL_GEN() is not bringing much clarity and forcing > the other macros to have the IS_ prefix. Is the IS_ prefix that bad? I agree my idea does not decrease the amount of churn, since it said to replace INTEL_GEN with INTEL_GT_GEN. But in the light of the GT/DISPLAY split, and if we agree to leave a lot of the arithmetic comparison in (dialing down of "drm/i915: replace gen checks using operators by GT_GEN/GT_GEN_RANGE"), then it feels going back to INTEL_INFO(dev_priv)->gen throughout the code is undoing some work, just so you can remove the INTEL_GEN macro instead of renaming it INTEL_GT_GEN. Don't know, it's my opinion at least and more people are welcome to chime in with theirs. Regards, Tvrtko P.S. Reminded me of this tangential attempt as well: https://patchwork.freedesktop.org/patch/206168/, which I thought was a good way to make the code more elegant. >> >> This leaves GT and DISPLAY namespaces completely parallel in syntax and >> semantics. >> >> Regards, >> >> Tvrtko >> >> >> >>> >>> Rodrigo Vivi (1): >>> drm/i915: Rename IS_GEN to GT_RANGE >>> >>> drivers/gpu/drm/i915/gvt/gtt.c | 4 +- >>> drivers/gpu/drm/i915/gvt/handlers.c | 2 +- >>> drivers/gpu/drm/i915/gvt/vgpu.c | 4 +- >>> drivers/gpu/drm/i915/i915_cmd_parser.c | 2 +- >>> drivers/gpu/drm/i915/i915_debugfs.c | 145 +++++---- >>> drivers/gpu/drm/i915/i915_drv.c | 50 +-- >>> drivers/gpu/drm/i915/i915_drv.h | 67 ++-- >>> drivers/gpu/drm/i915/i915_gem.c | 30 +- >>> drivers/gpu/drm/i915/i915_gem_context.c | 4 +- >>> drivers/gpu/drm/i915/i915_gem_execbuffer.c | 10 +- >>> drivers/gpu/drm/i915/i915_gem_fence_reg.c | 16 +- >>> drivers/gpu/drm/i915/i915_gem_gtt.c | 36 +- >>> drivers/gpu/drm/i915/i915_gem_render_state.c | 2 +- >>> drivers/gpu/drm/i915/i915_gem_stolen.c | 15 +- >>> drivers/gpu/drm/i915/i915_gem_tiling.c | 12 +- >>> drivers/gpu/drm/i915/i915_gpu_error.c | 62 ++-- >>> drivers/gpu/drm/i915/i915_irq.c | 120 +++---- >>> drivers/gpu/drm/i915/i915_perf.c | 14 +- >>> drivers/gpu/drm/i915/i915_pmu.c | 6 +- >>> drivers/gpu/drm/i915/i915_reg.h | 8 +- >>> drivers/gpu/drm/i915/i915_suspend.c | 24 +- >>> drivers/gpu/drm/i915/i915_sysfs.c | 2 +- >>> drivers/gpu/drm/i915/intel_atomic.c | 4 +- >>> drivers/gpu/drm/i915/intel_audio.c | 4 +- >>> drivers/gpu/drm/i915/intel_bios.c | 12 +- >>> drivers/gpu/drm/i915/intel_cdclk.c | 28 +- >>> drivers/gpu/drm/i915/intel_color.c | 6 +- >>> drivers/gpu/drm/i915/intel_crt.c | 12 +- >>> drivers/gpu/drm/i915/intel_csr.c | 2 +- >>> drivers/gpu/drm/i915/intel_ddi.c | 58 ++-- >>> drivers/gpu/drm/i915/intel_device_info.c | 46 +-- >>> drivers/gpu/drm/i915/intel_display.c | 308 +++++++++--------- >>> drivers/gpu/drm/i915/intel_dp.c | 82 ++--- >>> drivers/gpu/drm/i915/intel_dp_mst.c | 2 +- >>> drivers/gpu/drm/i915/intel_dpll_mgr.c | 10 +- >>> drivers/gpu/drm/i915/intel_drv.h | 2 +- >>> drivers/gpu/drm/i915/intel_engine_cs.c | 44 +-- >>> drivers/gpu/drm/i915/intel_fbc.c | 52 +-- >>> drivers/gpu/drm/i915/intel_fifo_underrun.c | 8 +- >>> drivers/gpu/drm/i915/intel_guc_fw.c | 4 +- >>> drivers/gpu/drm/i915/intel_hangcheck.c | 6 +- >>> drivers/gpu/drm/i915/intel_hdcp.c | 2 +- >>> drivers/gpu/drm/i915/intel_hdmi.c | 18 +- >>> drivers/gpu/drm/i915/intel_i2c.c | 14 +- >>> drivers/gpu/drm/i915/intel_lrc.c | 32 +- >>> drivers/gpu/drm/i915/intel_lvds.c | 14 +- >>> drivers/gpu/drm/i915/intel_mocs.c | 8 +- >>> drivers/gpu/drm/i915/intel_overlay.c | 12 +- >>> drivers/gpu/drm/i915/intel_panel.c | 20 +- >>> drivers/gpu/drm/i915/intel_pipe_crc.c | 12 +- >>> drivers/gpu/drm/i915/intel_pm.c | 196 +++++------ >>> drivers/gpu/drm/i915/intel_psr.c | 26 +- >>> drivers/gpu/drm/i915/intel_ringbuffer.c | 68 ++-- >>> drivers/gpu/drm/i915/intel_ringbuffer.h | 4 +- >>> drivers/gpu/drm/i915/intel_runtime_pm.c | 32 +- >>> drivers/gpu/drm/i915/intel_sdvo.c | 14 +- >>> drivers/gpu/drm/i915/intel_sprite.c | 34 +- >>> drivers/gpu/drm/i915/intel_tv.c | 2 +- >>> drivers/gpu/drm/i915/intel_uc.c | 4 +- >>> drivers/gpu/drm/i915/intel_uncore.c | 60 ++-- >>> drivers/gpu/drm/i915/intel_wopcm.c | 8 +- >>> drivers/gpu/drm/i915/intel_workarounds.c | 20 +- >>> drivers/gpu/drm/i915/selftests/huge_pages.c | 2 +- >>> .../drm/i915/selftests/i915_gem_coherency.c | 4 +- >>> .../gpu/drm/i915/selftests/i915_gem_context.c | 10 +- >>> .../gpu/drm/i915/selftests/i915_gem_object.c | 12 +- >>> drivers/gpu/drm/i915/selftests/i915_request.c | 2 +- >>> .../gpu/drm/i915/selftests/intel_hangcheck.c | 8 +- >>> drivers/gpu/drm/i915/selftests/intel_lrc.c | 2 +- >>> drivers/gpu/drm/i915/selftests/intel_uncore.c | 2 +- >>> .../drm/i915/selftests/intel_workarounds.c | 2 +- >>> drivers/gpu/drm/i915/vlv_dsi.c | 40 +-- >>> 72 files changed, 1003 insertions(+), 1006 deletions(-) >>> > _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [PATCH v2 0/7] Make GEN macros more similar 2018-11-08 11:23 ` Tvrtko Ursulin @ 2018-11-19 22:20 ` Lucas De Marchi 2018-11-20 13:40 ` Tvrtko Ursulin ` (2 more replies) 0 siblings, 3 replies; 38+ messages in thread From: Lucas De Marchi @ 2018-11-19 22:20 UTC (permalink / raw) To: Tvrtko Ursulin; +Cc: intel-gfx, Lucas De Marchi, Rodrigo Vivi On Thu, Nov 08, 2018 at 11:23:46AM +0000, Tvrtko Ursulin wrote: > > On 08/11/2018 00:57, Lucas De Marchi wrote: > > On Wed, Nov 07, 2018 at 10:05:19AM +0000, Tvrtko Ursulin wrote: > > > > > > On 06/11/2018 21:51, Lucas De Marchi wrote: > > > > This is the second version of the series trying to make GEN checks > > > > more similar. These or roughly the changes from v1: > > > > > > > > - We don't have a single macro receiving 2 or 3 parameters. Now there > > > > is GT_GEN_RANGE(), and GT_GEN(). The firs is the conversion from > > > > IS_GEN() while the second is the conversion from IS_GEN<N>() > > > > - Bring GEN_FOREVER back to be used with above macros > > > > - Patch converting <, <=, ==, >, >= checks using INTEL_GEN() to > > > > use the macros above was added > > > > - INTEL_GEN() is removed to avoid it being used when we should prefer > > > > the new macros > > > > > > > > The idea of the names is to pave the way for checks of the display version, > > > > which would be named DISPLAY_GEN(), DISPLAY_GEN_RANGE(). > > > > > > > > In the commit messages we have the scripts to regenerate the patch to make > > > > it easier to apply after the discussions and also to be able to convert > > > > inflight patches. > > > > > > > > Sorry in advance for the noise this causes in the codebase, but hopefully > > > > it is for the greater good. > > > > > > > > > > > > Lucas De Marchi (6): > > > > Revert "drm/i915: Kill GEN_FOREVER" > > > > drm/i915: replace IS_GEN<N> with GT_GEN(..., N) > > > > drm/i915: rename IS_GEN9_* to GT_GEN9_* > > > > drm/i915: replace gen checks using operators by GT_GEN/GT_GEN_RANGE > > > > > > I have reservations about this patch, where I think forcing only one flavour > > > maybe is not the best thing. Because for plain if-ladder cases it feels more > > > readable to stick with the current scheme of arithmetic comparisons. And it > > > is more efficient in code as well. > > > > > > Range checks are on the other hand useful either when combined in the same > > > conditional as some other bitmask based test, or when both ends of the > > > comparison edge are bound. > > > > So are you against changing the == to use the macros, changing the >=, >, <, <=, > > or all of them? > > Definitely not all of them. Just plain if ladders I think are definitely > more readable in source and result in better code in the normal fashion of: > > if (gen >= 11) > else if (gen >= 9) > else if (gen >= 7) > ... etc ... > > Where I think it makes sense is when either both edges are bound, like: > > if (gen < 11 || gen >= 8) > if (gen >= 10 || gen == 8) ok, I will take a look before respinning this. > > But not sure how many of those there are. > > What definitely exists in large-ish numbers are: > > if (gen >= 11 || IS_PLATFORM) > > At some point I had a prototype which puts the gen and platform masks into a > bag of bits and then, depending on bits locality, this too can be compressed > to a single bitmask test. However I felt that was going too far, and the > issue is achieving interesting bits locality for it too work. But I digress. > > > Looking at the changes to ==, they seem very reasonable and in a few cases it allowed > > the next patch to merge them in a GT_GEN_RANGE() -- yes the patch ordering was on > > purpose to allow that. > > Yep those are the good ones. > > > The others are indeed debatable. However IMO for the cases it makes sense, > > there's always the fallback > > > > if (dev_priv->info.gen == 10) > > ... > > else if (dev_priv->info.gen == 11) > > ... > > else if (dev_priv->info.gen < 5) > > ... > > > > We can go on a case by case manner in this patch rather than the mass conversion > > for these. > > > > > > > > > drm/i915: merge gen checks to use range > > > > drm/i915: remove INTEL_GEN macro > > > > > > I have reservations about this as as well, especially considering the > > > previous paragraph. But even on it's own I am not sure we want to go back to > > > more verbose. > > > > see above. IMO it's not actually so verbose as one would think. > > > > if (INTEL_GEN(dev_priv) == 11) > > vs > > if (dev_priv->info.gen == 11) > > I think it should be: > > if (INTEL_INFO(dev_priv)->gen == 11) > > Which is a tiny bit longer.. If it's longer, why bother? We could just as well do for the if ladders: gen = dev_priv->info.gen; or gen = INTEL_INFO(dev_priv)->gen In your other series you would be moving gen to a runtime info, so this would cause the same amount of churn (although I disagree with moving gen to a runtime info just because of the mock struct). > > > The "verbose" version is actually one character less and one lookup less > > to what the macro is doing underneath. Of course that means a lot of churn > > to the codebase when/if we change where the gen number is located, but that > > number is at the same place since its introduction in 2010 > > (commit c96c3a8cb7fadcb33d9a5ebe35fcee8b7d0a7946) > > I am pretty sure we went through patches to a) move towards INTEL_INFO and > b) replace INTEL_INFO(dev_priv)->gen with INTEL_GEN. So I don't see an > advantage of reverting that, just so that we can lose the IS_ prefix below. > > > > Perhaps in the new scheme of things it should be renamed to INTEL_GT_GEN? I > > > know it doesn't fit nicely with the naming scheme of GT/DISPLAY_GEN.. so > > > maybe: > > > > > > GT_GEN -> IS_GT_GEN > > > GT_GEN_RANGE -> IS_GT_GEN_RANGE > > > INTEL_GEN -> GT_GEN (but churn!?) > > > > I still think INTEL_GEN() is not bringing much clarity and forcing > > the other macros to have the IS_ prefix. > > Is the IS_ prefix that bad? > > I agree my idea does not decrease the amount of churn, since it said to > replace INTEL_GEN with INTEL_GT_GEN. But in the light of the GT/DISPLAY > split, and if we agree to leave a lot of the arithmetic comparison in > (dialing down of "drm/i915: replace gen checks using operators by > GT_GEN/GT_GEN_RANGE"), then it feels going back to INTEL_INFO(dev_priv)->gen > throughout the code is undoing some work, just so you can remove the > INTEL_GEN macro instead of renaming it INTEL_GT_GEN. > > Don't know, it's my opinion at least and more people are welcome to chime in > with theirs. Any others to chime in on this? Jani, Ville, Rodrigo? thanks Lucas De Marchi > > Regards, > > Tvrtko > > P.S. Reminded me of this tangential attempt as well: > https://patchwork.freedesktop.org/patch/206168/, which I thought was a good > way to make the code more elegant. > > > > > > > > This leaves GT and DISPLAY namespaces completely parallel in syntax and > > > semantics. > > > > > > Regards, > > > > > > Tvrtko > > > > > > > > > > > > > > > > > Rodrigo Vivi (1): > > > > drm/i915: Rename IS_GEN to GT_RANGE > > > > > > > > drivers/gpu/drm/i915/gvt/gtt.c | 4 +- > > > > drivers/gpu/drm/i915/gvt/handlers.c | 2 +- > > > > drivers/gpu/drm/i915/gvt/vgpu.c | 4 +- > > > > drivers/gpu/drm/i915/i915_cmd_parser.c | 2 +- > > > > drivers/gpu/drm/i915/i915_debugfs.c | 145 +++++---- > > > > drivers/gpu/drm/i915/i915_drv.c | 50 +-- > > > > drivers/gpu/drm/i915/i915_drv.h | 67 ++-- > > > > drivers/gpu/drm/i915/i915_gem.c | 30 +- > > > > drivers/gpu/drm/i915/i915_gem_context.c | 4 +- > > > > drivers/gpu/drm/i915/i915_gem_execbuffer.c | 10 +- > > > > drivers/gpu/drm/i915/i915_gem_fence_reg.c | 16 +- > > > > drivers/gpu/drm/i915/i915_gem_gtt.c | 36 +- > > > > drivers/gpu/drm/i915/i915_gem_render_state.c | 2 +- > > > > drivers/gpu/drm/i915/i915_gem_stolen.c | 15 +- > > > > drivers/gpu/drm/i915/i915_gem_tiling.c | 12 +- > > > > drivers/gpu/drm/i915/i915_gpu_error.c | 62 ++-- > > > > drivers/gpu/drm/i915/i915_irq.c | 120 +++---- > > > > drivers/gpu/drm/i915/i915_perf.c | 14 +- > > > > drivers/gpu/drm/i915/i915_pmu.c | 6 +- > > > > drivers/gpu/drm/i915/i915_reg.h | 8 +- > > > > drivers/gpu/drm/i915/i915_suspend.c | 24 +- > > > > drivers/gpu/drm/i915/i915_sysfs.c | 2 +- > > > > drivers/gpu/drm/i915/intel_atomic.c | 4 +- > > > > drivers/gpu/drm/i915/intel_audio.c | 4 +- > > > > drivers/gpu/drm/i915/intel_bios.c | 12 +- > > > > drivers/gpu/drm/i915/intel_cdclk.c | 28 +- > > > > drivers/gpu/drm/i915/intel_color.c | 6 +- > > > > drivers/gpu/drm/i915/intel_crt.c | 12 +- > > > > drivers/gpu/drm/i915/intel_csr.c | 2 +- > > > > drivers/gpu/drm/i915/intel_ddi.c | 58 ++-- > > > > drivers/gpu/drm/i915/intel_device_info.c | 46 +-- > > > > drivers/gpu/drm/i915/intel_display.c | 308 +++++++++--------- > > > > drivers/gpu/drm/i915/intel_dp.c | 82 ++--- > > > > drivers/gpu/drm/i915/intel_dp_mst.c | 2 +- > > > > drivers/gpu/drm/i915/intel_dpll_mgr.c | 10 +- > > > > drivers/gpu/drm/i915/intel_drv.h | 2 +- > > > > drivers/gpu/drm/i915/intel_engine_cs.c | 44 +-- > > > > drivers/gpu/drm/i915/intel_fbc.c | 52 +-- > > > > drivers/gpu/drm/i915/intel_fifo_underrun.c | 8 +- > > > > drivers/gpu/drm/i915/intel_guc_fw.c | 4 +- > > > > drivers/gpu/drm/i915/intel_hangcheck.c | 6 +- > > > > drivers/gpu/drm/i915/intel_hdcp.c | 2 +- > > > > drivers/gpu/drm/i915/intel_hdmi.c | 18 +- > > > > drivers/gpu/drm/i915/intel_i2c.c | 14 +- > > > > drivers/gpu/drm/i915/intel_lrc.c | 32 +- > > > > drivers/gpu/drm/i915/intel_lvds.c | 14 +- > > > > drivers/gpu/drm/i915/intel_mocs.c | 8 +- > > > > drivers/gpu/drm/i915/intel_overlay.c | 12 +- > > > > drivers/gpu/drm/i915/intel_panel.c | 20 +- > > > > drivers/gpu/drm/i915/intel_pipe_crc.c | 12 +- > > > > drivers/gpu/drm/i915/intel_pm.c | 196 +++++------ > > > > drivers/gpu/drm/i915/intel_psr.c | 26 +- > > > > drivers/gpu/drm/i915/intel_ringbuffer.c | 68 ++-- > > > > drivers/gpu/drm/i915/intel_ringbuffer.h | 4 +- > > > > drivers/gpu/drm/i915/intel_runtime_pm.c | 32 +- > > > > drivers/gpu/drm/i915/intel_sdvo.c | 14 +- > > > > drivers/gpu/drm/i915/intel_sprite.c | 34 +- > > > > drivers/gpu/drm/i915/intel_tv.c | 2 +- > > > > drivers/gpu/drm/i915/intel_uc.c | 4 +- > > > > drivers/gpu/drm/i915/intel_uncore.c | 60 ++-- > > > > drivers/gpu/drm/i915/intel_wopcm.c | 8 +- > > > > drivers/gpu/drm/i915/intel_workarounds.c | 20 +- > > > > drivers/gpu/drm/i915/selftests/huge_pages.c | 2 +- > > > > .../drm/i915/selftests/i915_gem_coherency.c | 4 +- > > > > .../gpu/drm/i915/selftests/i915_gem_context.c | 10 +- > > > > .../gpu/drm/i915/selftests/i915_gem_object.c | 12 +- > > > > drivers/gpu/drm/i915/selftests/i915_request.c | 2 +- > > > > .../gpu/drm/i915/selftests/intel_hangcheck.c | 8 +- > > > > drivers/gpu/drm/i915/selftests/intel_lrc.c | 2 +- > > > > drivers/gpu/drm/i915/selftests/intel_uncore.c | 2 +- > > > > .../drm/i915/selftests/intel_workarounds.c | 2 +- > > > > drivers/gpu/drm/i915/vlv_dsi.c | 40 +-- > > > > 72 files changed, 1003 insertions(+), 1006 deletions(-) > > > > > > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [PATCH v2 0/7] Make GEN macros more similar 2018-11-19 22:20 ` Lucas De Marchi @ 2018-11-20 13:40 ` Tvrtko Ursulin 2018-11-21 22:19 ` Rodrigo Vivi 2018-11-23 12:44 ` Jani Nikula 2 siblings, 0 replies; 38+ messages in thread From: Tvrtko Ursulin @ 2018-11-20 13:40 UTC (permalink / raw) To: Lucas De Marchi; +Cc: intel-gfx, Lucas De Marchi, Rodrigo Vivi On 19/11/2018 22:20, Lucas De Marchi wrote: > On Thu, Nov 08, 2018 at 11:23:46AM +0000, Tvrtko Ursulin wrote: [snip] >>> So are you against changing the == to use the macros, changing the >=, >, <, <=, >>> or all of them? >> >> Definitely not all of them. Just plain if ladders I think are definitely >> more readable in source and result in better code in the normal fashion of: >> >> if (gen >= 11) >> else if (gen >= 9) >> else if (gen >= 7) >> ... etc ... >> >> Where I think it makes sense is when either both edges are bound, like: >> >> if (gen < 11 || gen >= 8) >> if (gen >= 10 || gen == 8) > > ok, I will take a look before respinning this. I forgot about the per-SKU builds when replying on this point. So I think we need to add them as the benefit of using range masks throughout. Question of whether people can stomach the ugliness still remains. But at least for me personally, I think if we want to get to per-SKU builds one day, then we'll have to do this. >> >> But not sure how many of those there are. >> >> What definitely exists in large-ish numbers are: >> >> if (gen >= 11 || IS_PLATFORM) >> >> At some point I had a prototype which puts the gen and platform masks into a >> bag of bits and then, depending on bits locality, this too can be compressed >> to a single bitmask test. However I felt that was going too far, and the >> issue is achieving interesting bits locality for it too work. But I digress. >> >>> Looking at the changes to ==, they seem very reasonable and in a few cases it allowed >>> the next patch to merge them in a GT_GEN_RANGE() -- yes the patch ordering was on >>> purpose to allow that. >> >> Yep those are the good ones. >> >>> The others are indeed debatable. However IMO for the cases it makes sense, >>> there's always the fallback >>> >>> if (dev_priv->info.gen == 10) >>> ... >>> else if (dev_priv->info.gen == 11) >>> ... >>> else if (dev_priv->info.gen < 5) >>> ... >>> >>> We can go on a case by case manner in this patch rather than the mass conversion >>> for these. >>> >>>> >>>>> drm/i915: merge gen checks to use range >>>>> drm/i915: remove INTEL_GEN macro >>>> >>>> I have reservations about this as as well, especially considering the >>>> previous paragraph. But even on it's own I am not sure we want to go back to >>>> more verbose. >>> >>> see above. IMO it's not actually so verbose as one would think. >>> >>> if (INTEL_GEN(dev_priv) == 11) >>> vs >>> if (dev_priv->info.gen == 11) >> >> I think it should be: >> >> if (INTEL_INFO(dev_priv)->gen == 11) >> >> Which is a tiny bit longer.. > > If it's longer, why bother? We could just as well do for the if ladders: > > gen = dev_priv->info.gen; > or > gen = INTEL_INFO(dev_priv)->gen > > In your other series you would be moving gen to a runtime info, so this > would cause the same amount of churn (although I disagree with moving gen to a runtime > info just because of the mock struct). We agreed there that gen in runtime should be avoided if at all possible. It seems that the consensus is to have macros to access device info, whether the current, or two flavours of it in the future. So I think only the question of naming remains on this item. Regards, Tvrtko _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [PATCH v2 0/7] Make GEN macros more similar 2018-11-19 22:20 ` Lucas De Marchi 2018-11-20 13:40 ` Tvrtko Ursulin @ 2018-11-21 22:19 ` Rodrigo Vivi 2018-11-22 8:54 ` Tvrtko Ursulin 2018-11-23 12:44 ` Jani Nikula 2 siblings, 1 reply; 38+ messages in thread From: Rodrigo Vivi @ 2018-11-21 22:19 UTC (permalink / raw) To: Lucas De Marchi; +Cc: intel-gfx, Lucas De Marchi On Mon, Nov 19, 2018 at 02:20:55PM -0800, Lucas De Marchi wrote: > On Thu, Nov 08, 2018 at 11:23:46AM +0000, Tvrtko Ursulin wrote: > > > > On 08/11/2018 00:57, Lucas De Marchi wrote: > > > On Wed, Nov 07, 2018 at 10:05:19AM +0000, Tvrtko Ursulin wrote: > > > > > > > > On 06/11/2018 21:51, Lucas De Marchi wrote: > > > > > This is the second version of the series trying to make GEN checks > > > > > more similar. These or roughly the changes from v1: > > > > > > > > > > - We don't have a single macro receiving 2 or 3 parameters. Now there > > > > > is GT_GEN_RANGE(), and GT_GEN(). The firs is the conversion from > > > > > IS_GEN() while the second is the conversion from IS_GEN<N>() > > > > > - Bring GEN_FOREVER back to be used with above macros > > > > > - Patch converting <, <=, ==, >, >= checks using INTEL_GEN() to > > > > > use the macros above was added > > > > > - INTEL_GEN() is removed to avoid it being used when we should prefer > > > > > the new macros > > > > > > > > > > The idea of the names is to pave the way for checks of the display version, > > > > > which would be named DISPLAY_GEN(), DISPLAY_GEN_RANGE(). > > > > > > > > > > In the commit messages we have the scripts to regenerate the patch to make > > > > > it easier to apply after the discussions and also to be able to convert > > > > > inflight patches. > > > > > > > > > > Sorry in advance for the noise this causes in the codebase, but hopefully > > > > > it is for the greater good. > > > > > > > > > > > > > > > Lucas De Marchi (6): > > > > > Revert "drm/i915: Kill GEN_FOREVER" > > > > > drm/i915: replace IS_GEN<N> with GT_GEN(..., N) > > > > > drm/i915: rename IS_GEN9_* to GT_GEN9_* > > > > > drm/i915: replace gen checks using operators by GT_GEN/GT_GEN_RANGE > > > > > > > > I have reservations about this patch, where I think forcing only one flavour > > > > maybe is not the best thing. Because for plain if-ladder cases it feels more > > > > readable to stick with the current scheme of arithmetic comparisons. And it > > > > is more efficient in code as well. > > > > > > > > Range checks are on the other hand useful either when combined in the same > > > > conditional as some other bitmask based test, or when both ends of the > > > > comparison edge are bound. > > > > > > So are you against changing the == to use the macros, changing the >=, >, <, <=, > > > or all of them? > > > > Definitely not all of them. Just plain if ladders I think are definitely > > more readable in source and result in better code in the normal fashion of: > > > > if (gen >= 11) > > else if (gen >= 9) > > else if (gen >= 7) > > ... etc ... > > > > Where I think it makes sense is when either both edges are bound, like: > > > > if (gen < 11 || gen >= 8) > > if (gen >= 10 || gen == 8) > > ok, I will take a look before respinning this. > > > > > But not sure how many of those there are. > > > > What definitely exists in large-ish numbers are: specially on display side... > > > > if (gen >= 11 || IS_PLATFORM) My goal is exactly to organize the gen numbers in a way that we minimize this mix as much as possible. > > > > At some point I had a prototype which puts the gen and platform masks into a > > bag of bits and then, depending on bits locality, this too can be compressed > > to a single bitmask test. However I felt that was going too far, and the > > issue is achieving interesting bits locality for it too work. But I digress. > > > > > Looking at the changes to ==, they seem very reasonable and in a few cases it allowed > > > the next patch to merge them in a GT_GEN_RANGE() -- yes the patch ordering was on > > > purpose to allow that. > > > > Yep those are the good ones. > > > > > The others are indeed debatable. However IMO for the cases it makes sense, > > > there's always the fallback > > > > > > if (dev_priv->info.gen == 10) > > > ... > > > else if (dev_priv->info.gen == 11) > > > ... > > > else if (dev_priv->info.gen < 5) > > > ... > > > > > > We can go on a case by case manner in this patch rather than the mass conversion > > > for these. > > > > > > > > > > > > drm/i915: merge gen checks to use range > > > > > drm/i915: remove INTEL_GEN macro > > > > > > > > I have reservations about this as as well, especially considering the > > > > previous paragraph. But even on it's own I am not sure we want to go back to > > > > more verbose. > > > > > > see above. IMO it's not actually so verbose as one would think. > > > > > > if (INTEL_GEN(dev_priv) == 11) > > > vs > > > if (dev_priv->info.gen == 11) > > > > I think it should be: > > > > if (INTEL_INFO(dev_priv)->gen == 11) > > > > Which is a tiny bit longer.. > > If it's longer, why bother? We could just as well do for the if ladders: > > gen = dev_priv->info.gen; > or > gen = INTEL_INFO(dev_priv)->gen > > In your other series you would be moving gen to a runtime info, so this > would cause the same amount of churn (although I disagree with moving gen to a runtime > info just because of the mock struct). > > > > > > > The "verbose" version is actually one character less and one lookup less > > > to what the macro is doing underneath. Of course that means a lot of churn > > > to the codebase when/if we change where the gen number is located, but that > > > number is at the same place since its introduction in 2010 > > > (commit c96c3a8cb7fadcb33d9a5ebe35fcee8b7d0a7946) > > > > I am pretty sure we went through patches to a) move towards INTEL_INFO and > > b) replace INTEL_INFO(dev_priv)->gen with INTEL_GEN. So I don't see an > > advantage of reverting that, just so that we can lose the IS_ prefix below. > > > > > > Perhaps in the new scheme of things it should be renamed to INTEL_GT_GEN? I > > > > know it doesn't fit nicely with the naming scheme of GT/DISPLAY_GEN.. so > > > > maybe: > > > > > > > > GT_GEN -> IS_GT_GEN > > > > GT_GEN_RANGE -> IS_GT_GEN_RANGE > > > > INTEL_GEN -> GT_GEN (but churn!?) > > > > > > I still think INTEL_GEN() is not bringing much clarity and forcing > > > the other macros to have the IS_ prefix. > > > > Is the IS_ prefix that bad? I personally don't like it... but maybe it is just my bad english?! 1. if gen 9 2. if is gen 9 3. if this is a gen 9 platform I like more the option 1... > > > > I agree my idea does not decrease the amount of churn, since it said to > > replace INTEL_GEN with INTEL_GT_GEN. But in the light of the GT/DISPLAY > > split, and if we agree to leave a lot of the arithmetic comparison in > > (dialing down of "drm/i915: replace gen checks using operators by > > GT_GEN/GT_GEN_RANGE"), then it feels going back to INTEL_INFO(dev_priv)->gen > > throughout the code is undoing some work, just so you can remove the > > INTEL_GEN macro instead of renaming it INTEL_GT_GEN. > > > > Don't know, it's my opinion at least and more people are welcome to chime in > > with theirs. > > Any others to chime in on this? Jani, Ville, Rodrigo? I don't like mixed styles much. If we don't kill the macro we will continue having mixed cases. So I'm in favor of the approach of this series here. Thanks, Rodrigo. > > thanks > Lucas De Marchi > > > > > Regards, > > > > Tvrtko > > > > P.S. Reminded me of this tangential attempt as well: > > https://patchwork.freedesktop.org/patch/206168/, which I thought was a good > > way to make the code more elegant. > > > > > > > > > > > > This leaves GT and DISPLAY namespaces completely parallel in syntax and > > > > semantics. > > > > > > > > Regards, > > > > > > > > Tvrtko > > > > > > > > > > > > > > > > > > > > > > Rodrigo Vivi (1): > > > > > drm/i915: Rename IS_GEN to GT_RANGE > > > > > > > > > > drivers/gpu/drm/i915/gvt/gtt.c | 4 +- > > > > > drivers/gpu/drm/i915/gvt/handlers.c | 2 +- > > > > > drivers/gpu/drm/i915/gvt/vgpu.c | 4 +- > > > > > drivers/gpu/drm/i915/i915_cmd_parser.c | 2 +- > > > > > drivers/gpu/drm/i915/i915_debugfs.c | 145 +++++---- > > > > > drivers/gpu/drm/i915/i915_drv.c | 50 +-- > > > > > drivers/gpu/drm/i915/i915_drv.h | 67 ++-- > > > > > drivers/gpu/drm/i915/i915_gem.c | 30 +- > > > > > drivers/gpu/drm/i915/i915_gem_context.c | 4 +- > > > > > drivers/gpu/drm/i915/i915_gem_execbuffer.c | 10 +- > > > > > drivers/gpu/drm/i915/i915_gem_fence_reg.c | 16 +- > > > > > drivers/gpu/drm/i915/i915_gem_gtt.c | 36 +- > > > > > drivers/gpu/drm/i915/i915_gem_render_state.c | 2 +- > > > > > drivers/gpu/drm/i915/i915_gem_stolen.c | 15 +- > > > > > drivers/gpu/drm/i915/i915_gem_tiling.c | 12 +- > > > > > drivers/gpu/drm/i915/i915_gpu_error.c | 62 ++-- > > > > > drivers/gpu/drm/i915/i915_irq.c | 120 +++---- > > > > > drivers/gpu/drm/i915/i915_perf.c | 14 +- > > > > > drivers/gpu/drm/i915/i915_pmu.c | 6 +- > > > > > drivers/gpu/drm/i915/i915_reg.h | 8 +- > > > > > drivers/gpu/drm/i915/i915_suspend.c | 24 +- > > > > > drivers/gpu/drm/i915/i915_sysfs.c | 2 +- > > > > > drivers/gpu/drm/i915/intel_atomic.c | 4 +- > > > > > drivers/gpu/drm/i915/intel_audio.c | 4 +- > > > > > drivers/gpu/drm/i915/intel_bios.c | 12 +- > > > > > drivers/gpu/drm/i915/intel_cdclk.c | 28 +- > > > > > drivers/gpu/drm/i915/intel_color.c | 6 +- > > > > > drivers/gpu/drm/i915/intel_crt.c | 12 +- > > > > > drivers/gpu/drm/i915/intel_csr.c | 2 +- > > > > > drivers/gpu/drm/i915/intel_ddi.c | 58 ++-- > > > > > drivers/gpu/drm/i915/intel_device_info.c | 46 +-- > > > > > drivers/gpu/drm/i915/intel_display.c | 308 +++++++++--------- > > > > > drivers/gpu/drm/i915/intel_dp.c | 82 ++--- > > > > > drivers/gpu/drm/i915/intel_dp_mst.c | 2 +- > > > > > drivers/gpu/drm/i915/intel_dpll_mgr.c | 10 +- > > > > > drivers/gpu/drm/i915/intel_drv.h | 2 +- > > > > > drivers/gpu/drm/i915/intel_engine_cs.c | 44 +-- > > > > > drivers/gpu/drm/i915/intel_fbc.c | 52 +-- > > > > > drivers/gpu/drm/i915/intel_fifo_underrun.c | 8 +- > > > > > drivers/gpu/drm/i915/intel_guc_fw.c | 4 +- > > > > > drivers/gpu/drm/i915/intel_hangcheck.c | 6 +- > > > > > drivers/gpu/drm/i915/intel_hdcp.c | 2 +- > > > > > drivers/gpu/drm/i915/intel_hdmi.c | 18 +- > > > > > drivers/gpu/drm/i915/intel_i2c.c | 14 +- > > > > > drivers/gpu/drm/i915/intel_lrc.c | 32 +- > > > > > drivers/gpu/drm/i915/intel_lvds.c | 14 +- > > > > > drivers/gpu/drm/i915/intel_mocs.c | 8 +- > > > > > drivers/gpu/drm/i915/intel_overlay.c | 12 +- > > > > > drivers/gpu/drm/i915/intel_panel.c | 20 +- > > > > > drivers/gpu/drm/i915/intel_pipe_crc.c | 12 +- > > > > > drivers/gpu/drm/i915/intel_pm.c | 196 +++++------ > > > > > drivers/gpu/drm/i915/intel_psr.c | 26 +- > > > > > drivers/gpu/drm/i915/intel_ringbuffer.c | 68 ++-- > > > > > drivers/gpu/drm/i915/intel_ringbuffer.h | 4 +- > > > > > drivers/gpu/drm/i915/intel_runtime_pm.c | 32 +- > > > > > drivers/gpu/drm/i915/intel_sdvo.c | 14 +- > > > > > drivers/gpu/drm/i915/intel_sprite.c | 34 +- > > > > > drivers/gpu/drm/i915/intel_tv.c | 2 +- > > > > > drivers/gpu/drm/i915/intel_uc.c | 4 +- > > > > > drivers/gpu/drm/i915/intel_uncore.c | 60 ++-- > > > > > drivers/gpu/drm/i915/intel_wopcm.c | 8 +- > > > > > drivers/gpu/drm/i915/intel_workarounds.c | 20 +- > > > > > drivers/gpu/drm/i915/selftests/huge_pages.c | 2 +- > > > > > .../drm/i915/selftests/i915_gem_coherency.c | 4 +- > > > > > .../gpu/drm/i915/selftests/i915_gem_context.c | 10 +- > > > > > .../gpu/drm/i915/selftests/i915_gem_object.c | 12 +- > > > > > drivers/gpu/drm/i915/selftests/i915_request.c | 2 +- > > > > > .../gpu/drm/i915/selftests/intel_hangcheck.c | 8 +- > > > > > drivers/gpu/drm/i915/selftests/intel_lrc.c | 2 +- > > > > > drivers/gpu/drm/i915/selftests/intel_uncore.c | 2 +- > > > > > .../drm/i915/selftests/intel_workarounds.c | 2 +- > > > > > drivers/gpu/drm/i915/vlv_dsi.c | 40 +-- > > > > > 72 files changed, 1003 insertions(+), 1006 deletions(-) > > > > > > > > > > _______________________________________________ > > Intel-gfx mailing list > > Intel-gfx@lists.freedesktop.org > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [PATCH v2 0/7] Make GEN macros more similar 2018-11-21 22:19 ` Rodrigo Vivi @ 2018-11-22 8:54 ` Tvrtko Ursulin 2018-11-26 18:46 ` Rodrigo Vivi 0 siblings, 1 reply; 38+ messages in thread From: Tvrtko Ursulin @ 2018-11-22 8:54 UTC (permalink / raw) To: Rodrigo Vivi, Lucas De Marchi; +Cc: intel-gfx, Lucas De Marchi On 21/11/2018 22:19, Rodrigo Vivi wrote: > On Mon, Nov 19, 2018 at 02:20:55PM -0800, Lucas De Marchi wrote: >> On Thu, Nov 08, 2018 at 11:23:46AM +0000, Tvrtko Ursulin wrote: >>> >>> On 08/11/2018 00:57, Lucas De Marchi wrote: >>>> On Wed, Nov 07, 2018 at 10:05:19AM +0000, Tvrtko Ursulin wrote: >>>>> >>>>> On 06/11/2018 21:51, Lucas De Marchi wrote: >>>>>> This is the second version of the series trying to make GEN checks >>>>>> more similar. These or roughly the changes from v1: >>>>>> >>>>>> - We don't have a single macro receiving 2 or 3 parameters. Now there >>>>>> is GT_GEN_RANGE(), and GT_GEN(). The firs is the conversion from >>>>>> IS_GEN() while the second is the conversion from IS_GEN<N>() >>>>>> - Bring GEN_FOREVER back to be used with above macros >>>>>> - Patch converting <, <=, ==, >, >= checks using INTEL_GEN() to >>>>>> use the macros above was added >>>>>> - INTEL_GEN() is removed to avoid it being used when we should prefer >>>>>> the new macros >>>>>> >>>>>> The idea of the names is to pave the way for checks of the display version, >>>>>> which would be named DISPLAY_GEN(), DISPLAY_GEN_RANGE(). >>>>>> >>>>>> In the commit messages we have the scripts to regenerate the patch to make >>>>>> it easier to apply after the discussions and also to be able to convert >>>>>> inflight patches. >>>>>> >>>>>> Sorry in advance for the noise this causes in the codebase, but hopefully >>>>>> it is for the greater good. >>>>>> >>>>>> >>>>>> Lucas De Marchi (6): >>>>>> Revert "drm/i915: Kill GEN_FOREVER" >>>>>> drm/i915: replace IS_GEN<N> with GT_GEN(..., N) >>>>>> drm/i915: rename IS_GEN9_* to GT_GEN9_* >>>>>> drm/i915: replace gen checks using operators by GT_GEN/GT_GEN_RANGE >>>>> >>>>> I have reservations about this patch, where I think forcing only one flavour >>>>> maybe is not the best thing. Because for plain if-ladder cases it feels more >>>>> readable to stick with the current scheme of arithmetic comparisons. And it >>>>> is more efficient in code as well. >>>>> >>>>> Range checks are on the other hand useful either when combined in the same >>>>> conditional as some other bitmask based test, or when both ends of the >>>>> comparison edge are bound. >>>> >>>> So are you against changing the == to use the macros, changing the >=, >, <, <=, >>>> or all of them? >>> >>> Definitely not all of them. Just plain if ladders I think are definitely >>> more readable in source and result in better code in the normal fashion of: >>> >>> if (gen >= 11) >>> else if (gen >= 9) >>> else if (gen >= 7) >>> ... etc ... >>> >>> Where I think it makes sense is when either both edges are bound, like: >>> >>> if (gen < 11 || gen >= 8) >>> if (gen >= 10 || gen == 8) >> >> ok, I will take a look before respinning this. >> >>> >>> But not sure how many of those there are. >>> >>> What definitely exists in large-ish numbers are: > > specially on display side... > >>> >>> if (gen >= 11 || IS_PLATFORM) > > My goal is exactly to organize the gen numbers in a way that > we minimize this mix as much as possible. > >>> >>> At some point I had a prototype which puts the gen and platform masks into a >>> bag of bits and then, depending on bits locality, this too can be compressed >>> to a single bitmask test. However I felt that was going too far, and the >>> issue is achieving interesting bits locality for it too work. But I digress. >>> >>>> Looking at the changes to ==, they seem very reasonable and in a few cases it allowed >>>> the next patch to merge them in a GT_GEN_RANGE() -- yes the patch ordering was on >>>> purpose to allow that. >>> >>> Yep those are the good ones. >>> >>>> The others are indeed debatable. However IMO for the cases it makes sense, >>>> there's always the fallback >>>> >>>> if (dev_priv->info.gen == 10) >>>> ... >>>> else if (dev_priv->info.gen == 11) >>>> ... >>>> else if (dev_priv->info.gen < 5) >>>> ... >>>> >>>> We can go on a case by case manner in this patch rather than the mass conversion >>>> for these. >>>> >>>>> >>>>>> drm/i915: merge gen checks to use range >>>>>> drm/i915: remove INTEL_GEN macro >>>>> >>>>> I have reservations about this as as well, especially considering the >>>>> previous paragraph. But even on it's own I am not sure we want to go back to >>>>> more verbose. >>>> >>>> see above. IMO it's not actually so verbose as one would think. >>>> >>>> if (INTEL_GEN(dev_priv) == 11) >>>> vs >>>> if (dev_priv->info.gen == 11) >>> >>> I think it should be: >>> >>> if (INTEL_INFO(dev_priv)->gen == 11) >>> >>> Which is a tiny bit longer.. >> >> If it's longer, why bother? We could just as well do for the if ladders: >> >> gen = dev_priv->info.gen; >> or >> gen = INTEL_INFO(dev_priv)->gen >> >> In your other series you would be moving gen to a runtime info, so this >> would cause the same amount of churn (although I disagree with moving gen to a runtime >> info just because of the mock struct). >> >> >>> >>>> The "verbose" version is actually one character less and one lookup less >>>> to what the macro is doing underneath. Of course that means a lot of churn >>>> to the codebase when/if we change where the gen number is located, but that >>>> number is at the same place since its introduction in 2010 >>>> (commit c96c3a8cb7fadcb33d9a5ebe35fcee8b7d0a7946) >>> >>> I am pretty sure we went through patches to a) move towards INTEL_INFO and >>> b) replace INTEL_INFO(dev_priv)->gen with INTEL_GEN. So I don't see an >>> advantage of reverting that, just so that we can lose the IS_ prefix below. >>> >>>>> Perhaps in the new scheme of things it should be renamed to INTEL_GT_GEN? I >>>>> know it doesn't fit nicely with the naming scheme of GT/DISPLAY_GEN.. so >>>>> maybe: >>>>> >>>>> GT_GEN -> IS_GT_GEN >>>>> GT_GEN_RANGE -> IS_GT_GEN_RANGE >>>>> INTEL_GEN -> GT_GEN (but churn!?) >>>> >>>> I still think INTEL_GEN() is not bringing much clarity and forcing >>>> the other macros to have the IS_ prefix. >>> >>> Is the IS_ prefix that bad? > > I personally don't like it... but maybe it is just my bad english?! > > 1. if gen 9 > 2. if is gen 9 > 3. if this is a gen 9 platform > > I like more the option 1... > >>> >>> I agree my idea does not decrease the amount of churn, since it said to >>> replace INTEL_GEN with INTEL_GT_GEN. But in the light of the GT/DISPLAY >>> split, and if we agree to leave a lot of the arithmetic comparison in >>> (dialing down of "drm/i915: replace gen checks using operators by >>> GT_GEN/GT_GEN_RANGE"), then it feels going back to INTEL_INFO(dev_priv)->gen >>> throughout the code is undoing some work, just so you can remove the >>> INTEL_GEN macro instead of renaming it INTEL_GT_GEN. >>> >>> Don't know, it's my opinion at least and more people are welcome to chime in >>> with theirs. >> >> Any others to chime in on this? Jani, Ville, Rodrigo? > > I don't like mixed styles much. If we don't kill the macro we will continue > having mixed cases. > > So I'm in favor of the approach of this series here. Including the removal of INTEL_GEN macro? Or what do you propose for that one? Can't be called GT_GEN now since that has been used up... Regards, Tvrtko _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [PATCH v2 0/7] Make GEN macros more similar 2018-11-22 8:54 ` Tvrtko Ursulin @ 2018-11-26 18:46 ` Rodrigo Vivi 2018-11-27 8:37 ` Jani Nikula 0 siblings, 1 reply; 38+ messages in thread From: Rodrigo Vivi @ 2018-11-26 18:46 UTC (permalink / raw) To: Tvrtko Ursulin; +Cc: intel-gfx, Lucas De Marchi On Thu, Nov 22, 2018 at 08:54:30AM +0000, Tvrtko Ursulin wrote: > > > On 21/11/2018 22:19, Rodrigo Vivi wrote: > > On Mon, Nov 19, 2018 at 02:20:55PM -0800, Lucas De Marchi wrote: > > > On Thu, Nov 08, 2018 at 11:23:46AM +0000, Tvrtko Ursulin wrote: > > > > > > > > On 08/11/2018 00:57, Lucas De Marchi wrote: > > > > > On Wed, Nov 07, 2018 at 10:05:19AM +0000, Tvrtko Ursulin wrote: > > > > > > > > > > > > On 06/11/2018 21:51, Lucas De Marchi wrote: > > > > > > > This is the second version of the series trying to make GEN checks > > > > > > > more similar. These or roughly the changes from v1: > > > > > > > > > > > > > > - We don't have a single macro receiving 2 or 3 parameters. Now there > > > > > > > is GT_GEN_RANGE(), and GT_GEN(). The firs is the conversion from > > > > > > > IS_GEN() while the second is the conversion from IS_GEN<N>() > > > > > > > - Bring GEN_FOREVER back to be used with above macros > > > > > > > - Patch converting <, <=, ==, >, >= checks using INTEL_GEN() to > > > > > > > use the macros above was added > > > > > > > - INTEL_GEN() is removed to avoid it being used when we should prefer > > > > > > > the new macros > > > > > > > > > > > > > > The idea of the names is to pave the way for checks of the display version, > > > > > > > which would be named DISPLAY_GEN(), DISPLAY_GEN_RANGE(). > > > > > > > > > > > > > > In the commit messages we have the scripts to regenerate the patch to make > > > > > > > it easier to apply after the discussions and also to be able to convert > > > > > > > inflight patches. > > > > > > > > > > > > > > Sorry in advance for the noise this causes in the codebase, but hopefully > > > > > > > it is for the greater good. > > > > > > > > > > > > > > > > > > > > > Lucas De Marchi (6): > > > > > > > Revert "drm/i915: Kill GEN_FOREVER" > > > > > > > drm/i915: replace IS_GEN<N> with GT_GEN(..., N) > > > > > > > drm/i915: rename IS_GEN9_* to GT_GEN9_* > > > > > > > drm/i915: replace gen checks using operators by GT_GEN/GT_GEN_RANGE > > > > > > > > > > > > I have reservations about this patch, where I think forcing only one flavour > > > > > > maybe is not the best thing. Because for plain if-ladder cases it feels more > > > > > > readable to stick with the current scheme of arithmetic comparisons. And it > > > > > > is more efficient in code as well. > > > > > > > > > > > > Range checks are on the other hand useful either when combined in the same > > > > > > conditional as some other bitmask based test, or when both ends of the > > > > > > comparison edge are bound. > > > > > > > > > > So are you against changing the == to use the macros, changing the >=, >, <, <=, > > > > > or all of them? > > > > > > > > Definitely not all of them. Just plain if ladders I think are definitely > > > > more readable in source and result in better code in the normal fashion of: > > > > > > > > if (gen >= 11) > > > > else if (gen >= 9) > > > > else if (gen >= 7) > > > > ... etc ... > > > > > > > > Where I think it makes sense is when either both edges are bound, like: > > > > > > > > if (gen < 11 || gen >= 8) > > > > if (gen >= 10 || gen == 8) > > > > > > ok, I will take a look before respinning this. > > > > > > > > > > > But not sure how many of those there are. > > > > > > > > What definitely exists in large-ish numbers are: > > > > specially on display side... > > > > > > > > > > if (gen >= 11 || IS_PLATFORM) > > > > My goal is exactly to organize the gen numbers in a way that > > we minimize this mix as much as possible. > > > > > > > > > > At some point I had a prototype which puts the gen and platform masks into a > > > > bag of bits and then, depending on bits locality, this too can be compressed > > > > to a single bitmask test. However I felt that was going too far, and the > > > > issue is achieving interesting bits locality for it too work. But I digress. > > > > > > > > > Looking at the changes to ==, they seem very reasonable and in a few cases it allowed > > > > > the next patch to merge them in a GT_GEN_RANGE() -- yes the patch ordering was on > > > > > purpose to allow that. > > > > > > > > Yep those are the good ones. > > > > > > > > > The others are indeed debatable. However IMO for the cases it makes sense, > > > > > there's always the fallback > > > > > > > > > > if (dev_priv->info.gen == 10) > > > > > ... > > > > > else if (dev_priv->info.gen == 11) > > > > > ... > > > > > else if (dev_priv->info.gen < 5) > > > > > ... > > > > > > > > > > We can go on a case by case manner in this patch rather than the mass conversion > > > > > for these. > > > > > > > > > > > > > > > > > > drm/i915: merge gen checks to use range > > > > > > > drm/i915: remove INTEL_GEN macro > > > > > > > > > > > > I have reservations about this as as well, especially considering the > > > > > > previous paragraph. But even on it's own I am not sure we want to go back to > > > > > > more verbose. > > > > > > > > > > see above. IMO it's not actually so verbose as one would think. > > > > > > > > > > if (INTEL_GEN(dev_priv) == 11) > > > > > vs > > > > > if (dev_priv->info.gen == 11) > > > > > > > > I think it should be: > > > > > > > > if (INTEL_INFO(dev_priv)->gen == 11) > > > > > > > > Which is a tiny bit longer.. > > > > > > If it's longer, why bother? We could just as well do for the if ladders: > > > > > > gen = dev_priv->info.gen; > > > or > > > gen = INTEL_INFO(dev_priv)->gen > > > > > > In your other series you would be moving gen to a runtime info, so this > > > would cause the same amount of churn (although I disagree with moving gen to a runtime > > > info just because of the mock struct). > > > > > > > > > > > > > > > The "verbose" version is actually one character less and one lookup less > > > > > to what the macro is doing underneath. Of course that means a lot of churn > > > > > to the codebase when/if we change where the gen number is located, but that > > > > > number is at the same place since its introduction in 2010 > > > > > (commit c96c3a8cb7fadcb33d9a5ebe35fcee8b7d0a7946) > > > > > > > > I am pretty sure we went through patches to a) move towards INTEL_INFO and > > > > b) replace INTEL_INFO(dev_priv)->gen with INTEL_GEN. So I don't see an > > > > advantage of reverting that, just so that we can lose the IS_ prefix below. > > > > > > > > > > Perhaps in the new scheme of things it should be renamed to INTEL_GT_GEN? I > > > > > > know it doesn't fit nicely with the naming scheme of GT/DISPLAY_GEN.. so > > > > > > maybe: > > > > > > > > > > > > GT_GEN -> IS_GT_GEN > > > > > > GT_GEN_RANGE -> IS_GT_GEN_RANGE > > > > > > INTEL_GEN -> GT_GEN (but churn!?) > > > > > > > > > > I still think INTEL_GEN() is not bringing much clarity and forcing > > > > > the other macros to have the IS_ prefix. > > > > > > > > Is the IS_ prefix that bad? > > > > I personally don't like it... but maybe it is just my bad english?! > > > > 1. if gen 9 > > 2. if is gen 9 > > 3. if this is a gen 9 platform > > > > I like more the option 1... > > > > > > > > > > I agree my idea does not decrease the amount of churn, since it said to > > > > replace INTEL_GEN with INTEL_GT_GEN. But in the light of the GT/DISPLAY > > > > split, and if we agree to leave a lot of the arithmetic comparison in > > > > (dialing down of "drm/i915: replace gen checks using operators by > > > > GT_GEN/GT_GEN_RANGE"), then it feels going back to INTEL_INFO(dev_priv)->gen > > > > throughout the code is undoing some work, just so you can remove the > > > > INTEL_GEN macro instead of renaming it INTEL_GT_GEN. > > > > > > > > Don't know, it's my opinion at least and more people are welcome to chime in > > > > with theirs. > > > > > > Any others to chime in on this? Jani, Ville, Rodrigo? > > > > I don't like mixed styles much. If we don't kill the macro we will continue > > having mixed cases. > > > > So I'm in favor of the approach of this series here. > > Including the removal of INTEL_GEN macro? Or what do you propose for that > one? Can't be called GT_GEN now since that has been used up... Yes, including the removal of INTEL_GEN macro. I don't like the mixed styles like using INTEL_GEN(d) > 7 in one place and INTEL_GEN_RANGE(d, 7, FOREVER) in another place. The meaning is the same so we should stick with one of the usages. I see that there were many cases where having the info->gen number directly is useful. But I'd prefer to use that on a direct fashion rather than keeping this macro. Because if we keep the macro developers will eventually end up adding the mixed style back. Using direct info->gen as Lucas already showed has almost same number of chars than the macro, but requires more attention what is a good thing. > > Regards, > > Tvrtko _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [PATCH v2 0/7] Make GEN macros more similar 2018-11-26 18:46 ` Rodrigo Vivi @ 2018-11-27 8:37 ` Jani Nikula 2018-11-27 9:36 ` Lucas De Marchi 0 siblings, 1 reply; 38+ messages in thread From: Jani Nikula @ 2018-11-27 8:37 UTC (permalink / raw) To: Rodrigo Vivi, Tvrtko Ursulin; +Cc: intel-gfx, Lucas De Marchi On Mon, 26 Nov 2018, Rodrigo Vivi <rodrigo.vivi@intel.com> wrote: > On Thu, Nov 22, 2018 at 08:54:30AM +0000, Tvrtko Ursulin wrote: >> >> >> On 21/11/2018 22:19, Rodrigo Vivi wrote: >> > On Mon, Nov 19, 2018 at 02:20:55PM -0800, Lucas De Marchi wrote: >> > > On Thu, Nov 08, 2018 at 11:23:46AM +0000, Tvrtko Ursulin wrote: >> > > > >> > > > On 08/11/2018 00:57, Lucas De Marchi wrote: >> > > > > On Wed, Nov 07, 2018 at 10:05:19AM +0000, Tvrtko Ursulin wrote: >> > > > > > >> > > > > > On 06/11/2018 21:51, Lucas De Marchi wrote: >> > > > > > > This is the second version of the series trying to make GEN checks >> > > > > > > more similar. These or roughly the changes from v1: >> > > > > > > >> > > > > > > - We don't have a single macro receiving 2 or 3 parameters. Now there >> > > > > > > is GT_GEN_RANGE(), and GT_GEN(). The firs is the conversion from >> > > > > > > IS_GEN() while the second is the conversion from IS_GEN<N>() >> > > > > > > - Bring GEN_FOREVER back to be used with above macros >> > > > > > > - Patch converting <, <=, ==, >, >= checks using INTEL_GEN() to >> > > > > > > use the macros above was added >> > > > > > > - INTEL_GEN() is removed to avoid it being used when we should prefer >> > > > > > > the new macros >> > > > > > > >> > > > > > > The idea of the names is to pave the way for checks of the display version, >> > > > > > > which would be named DISPLAY_GEN(), DISPLAY_GEN_RANGE(). >> > > > > > > >> > > > > > > In the commit messages we have the scripts to regenerate the patch to make >> > > > > > > it easier to apply after the discussions and also to be able to convert >> > > > > > > inflight patches. >> > > > > > > >> > > > > > > Sorry in advance for the noise this causes in the codebase, but hopefully >> > > > > > > it is for the greater good. >> > > > > > > >> > > > > > > >> > > > > > > Lucas De Marchi (6): >> > > > > > > Revert "drm/i915: Kill GEN_FOREVER" >> > > > > > > drm/i915: replace IS_GEN<N> with GT_GEN(..., N) >> > > > > > > drm/i915: rename IS_GEN9_* to GT_GEN9_* >> > > > > > > drm/i915: replace gen checks using operators by GT_GEN/GT_GEN_RANGE >> > > > > > >> > > > > > I have reservations about this patch, where I think forcing only one flavour >> > > > > > maybe is not the best thing. Because for plain if-ladder cases it feels more >> > > > > > readable to stick with the current scheme of arithmetic comparisons. And it >> > > > > > is more efficient in code as well. >> > > > > > >> > > > > > Range checks are on the other hand useful either when combined in the same >> > > > > > conditional as some other bitmask based test, or when both ends of the >> > > > > > comparison edge are bound. >> > > > > >> > > > > So are you against changing the == to use the macros, changing the >=, >, <, <=, >> > > > > or all of them? >> > > > >> > > > Definitely not all of them. Just plain if ladders I think are definitely >> > > > more readable in source and result in better code in the normal fashion of: >> > > > >> > > > if (gen >= 11) >> > > > else if (gen >= 9) >> > > > else if (gen >= 7) >> > > > ... etc ... >> > > > >> > > > Where I think it makes sense is when either both edges are bound, like: >> > > > >> > > > if (gen < 11 || gen >= 8) >> > > > if (gen >= 10 || gen == 8) >> > > >> > > ok, I will take a look before respinning this. >> > > >> > > > >> > > > But not sure how many of those there are. >> > > > >> > > > What definitely exists in large-ish numbers are: >> > >> > specially on display side... >> > >> > > > >> > > > if (gen >= 11 || IS_PLATFORM) >> > >> > My goal is exactly to organize the gen numbers in a way that >> > we minimize this mix as much as possible. >> > >> > > > >> > > > At some point I had a prototype which puts the gen and platform masks into a >> > > > bag of bits and then, depending on bits locality, this too can be compressed >> > > > to a single bitmask test. However I felt that was going too far, and the >> > > > issue is achieving interesting bits locality for it too work. But I digress. >> > > > >> > > > > Looking at the changes to ==, they seem very reasonable and in a few cases it allowed >> > > > > the next patch to merge them in a GT_GEN_RANGE() -- yes the patch ordering was on >> > > > > purpose to allow that. >> > > > >> > > > Yep those are the good ones. >> > > > >> > > > > The others are indeed debatable. However IMO for the cases it makes sense, >> > > > > there's always the fallback >> > > > > >> > > > > if (dev_priv->info.gen == 10) >> > > > > ... >> > > > > else if (dev_priv->info.gen == 11) >> > > > > ... >> > > > > else if (dev_priv->info.gen < 5) >> > > > > ... >> > > > > >> > > > > We can go on a case by case manner in this patch rather than the mass conversion >> > > > > for these. >> > > > > >> > > > > > >> > > > > > > drm/i915: merge gen checks to use range >> > > > > > > drm/i915: remove INTEL_GEN macro >> > > > > > >> > > > > > I have reservations about this as as well, especially considering the >> > > > > > previous paragraph. But even on it's own I am not sure we want to go back to >> > > > > > more verbose. >> > > > > >> > > > > see above. IMO it's not actually so verbose as one would think. >> > > > > >> > > > > if (INTEL_GEN(dev_priv) == 11) >> > > > > vs >> > > > > if (dev_priv->info.gen == 11) >> > > > >> > > > I think it should be: >> > > > >> > > > if (INTEL_INFO(dev_priv)->gen == 11) >> > > > >> > > > Which is a tiny bit longer.. >> > > >> > > If it's longer, why bother? We could just as well do for the if ladders: >> > > >> > > gen = dev_priv->info.gen; >> > > or >> > > gen = INTEL_INFO(dev_priv)->gen >> > > >> > > In your other series you would be moving gen to a runtime info, so this >> > > would cause the same amount of churn (although I disagree with moving gen to a runtime >> > > info just because of the mock struct). >> > > >> > > >> > > > >> > > > > The "verbose" version is actually one character less and one lookup less >> > > > > to what the macro is doing underneath. Of course that means a lot of churn >> > > > > to the codebase when/if we change where the gen number is located, but that >> > > > > number is at the same place since its introduction in 2010 >> > > > > (commit c96c3a8cb7fadcb33d9a5ebe35fcee8b7d0a7946) >> > > > >> > > > I am pretty sure we went through patches to a) move towards INTEL_INFO and >> > > > b) replace INTEL_INFO(dev_priv)->gen with INTEL_GEN. So I don't see an >> > > > advantage of reverting that, just so that we can lose the IS_ prefix below. >> > > > >> > > > > > Perhaps in the new scheme of things it should be renamed to INTEL_GT_GEN? I >> > > > > > know it doesn't fit nicely with the naming scheme of GT/DISPLAY_GEN.. so >> > > > > > maybe: >> > > > > > >> > > > > > GT_GEN -> IS_GT_GEN >> > > > > > GT_GEN_RANGE -> IS_GT_GEN_RANGE >> > > > > > INTEL_GEN -> GT_GEN (but churn!?) >> > > > > >> > > > > I still think INTEL_GEN() is not bringing much clarity and forcing >> > > > > the other macros to have the IS_ prefix. >> > > > >> > > > Is the IS_ prefix that bad? >> > >> > I personally don't like it... but maybe it is just my bad english?! >> > >> > 1. if gen 9 >> > 2. if is gen 9 >> > 3. if this is a gen 9 platform >> > >> > I like more the option 1... >> > >> > > > >> > > > I agree my idea does not decrease the amount of churn, since it said to >> > > > replace INTEL_GEN with INTEL_GT_GEN. But in the light of the GT/DISPLAY >> > > > split, and if we agree to leave a lot of the arithmetic comparison in >> > > > (dialing down of "drm/i915: replace gen checks using operators by >> > > > GT_GEN/GT_GEN_RANGE"), then it feels going back to INTEL_INFO(dev_priv)->gen >> > > > throughout the code is undoing some work, just so you can remove the >> > > > INTEL_GEN macro instead of renaming it INTEL_GT_GEN. >> > > > >> > > > Don't know, it's my opinion at least and more people are welcome to chime in >> > > > with theirs. >> > > >> > > Any others to chime in on this? Jani, Ville, Rodrigo? >> > >> > I don't like mixed styles much. If we don't kill the macro we will continue >> > having mixed cases. >> > >> > So I'm in favor of the approach of this series here. >> >> Including the removal of INTEL_GEN macro? Or what do you propose for that >> one? Can't be called GT_GEN now since that has been used up... > > Yes, including the removal of INTEL_GEN macro. > > I don't like the mixed styles like using INTEL_GEN(d) > 7 in one place > and INTEL_GEN_RANGE(d, 7, FOREVER) in another place. > > The meaning is the same so we should stick with one of the usages. > > I see that there were many cases where having the info->gen number > directly is useful. But I'd prefer to use that on a direct fashion > rather than keeping this macro. > > Because if we keep the macro developers will eventually end up > adding the mixed style back. > > Using direct info->gen as Lucas already showed has almost same number > of chars than the macro, but requires more attention what is a good > thing. I prefer using INTEL_GEN() because it hides where the gen comes from, and we can change it on a whim. If we keep using dev_priv->info.gen we'll need to change that already when info becomes a pointer, i.e. dev_priv->info->gen. Throughout the codebase. With INTEL_GEN() it's just a couple of places. If mixed use is a problem, then rename gen to __gen. I even sent a patch for it, but didn't get it merged. BR, Jani. -- Jani Nikula, Intel Open Source Graphics Center _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [PATCH v2 0/7] Make GEN macros more similar 2018-11-27 8:37 ` Jani Nikula @ 2018-11-27 9:36 ` Lucas De Marchi 2018-11-27 11:35 ` Tvrtko Ursulin 0 siblings, 1 reply; 38+ messages in thread From: Lucas De Marchi @ 2018-11-27 9:36 UTC (permalink / raw) To: Jani Nikula; +Cc: intel-gfx, Lucas De Marchi, Rodrigo Vivi On Tue, Nov 27, 2018 at 10:37:21AM +0200, Jani Nikula wrote: > On Mon, 26 Nov 2018, Rodrigo Vivi <rodrigo.vivi@intel.com> wrote: > > On Thu, Nov 22, 2018 at 08:54:30AM +0000, Tvrtko Ursulin wrote: > >> > >> > >> On 21/11/2018 22:19, Rodrigo Vivi wrote: > >> > On Mon, Nov 19, 2018 at 02:20:55PM -0800, Lucas De Marchi wrote: > >> > > On Thu, Nov 08, 2018 at 11:23:46AM +0000, Tvrtko Ursulin wrote: > >> > > > > >> > > > On 08/11/2018 00:57, Lucas De Marchi wrote: > >> > > > > On Wed, Nov 07, 2018 at 10:05:19AM +0000, Tvrtko Ursulin wrote: > >> > > > > > > >> > > > > > On 06/11/2018 21:51, Lucas De Marchi wrote: > >> > > > > > > This is the second version of the series trying to make GEN checks > >> > > > > > > more similar. These or roughly the changes from v1: > >> > > > > > > > >> > > > > > > - We don't have a single macro receiving 2 or 3 parameters. Now there > >> > > > > > > is GT_GEN_RANGE(), and GT_GEN(). The firs is the conversion from > >> > > > > > > IS_GEN() while the second is the conversion from IS_GEN<N>() > >> > > > > > > - Bring GEN_FOREVER back to be used with above macros > >> > > > > > > - Patch converting <, <=, ==, >, >= checks using INTEL_GEN() to > >> > > > > > > use the macros above was added > >> > > > > > > - INTEL_GEN() is removed to avoid it being used when we should prefer > >> > > > > > > the new macros > >> > > > > > > > >> > > > > > > The idea of the names is to pave the way for checks of the display version, > >> > > > > > > which would be named DISPLAY_GEN(), DISPLAY_GEN_RANGE(). > >> > > > > > > > >> > > > > > > In the commit messages we have the scripts to regenerate the patch to make > >> > > > > > > it easier to apply after the discussions and also to be able to convert > >> > > > > > > inflight patches. > >> > > > > > > > >> > > > > > > Sorry in advance for the noise this causes in the codebase, but hopefully > >> > > > > > > it is for the greater good. > >> > > > > > > > >> > > > > > > > >> > > > > > > Lucas De Marchi (6): > >> > > > > > > Revert "drm/i915: Kill GEN_FOREVER" > >> > > > > > > drm/i915: replace IS_GEN<N> with GT_GEN(..., N) > >> > > > > > > drm/i915: rename IS_GEN9_* to GT_GEN9_* > >> > > > > > > drm/i915: replace gen checks using operators by GT_GEN/GT_GEN_RANGE > >> > > > > > > >> > > > > > I have reservations about this patch, where I think forcing only one flavour > >> > > > > > maybe is not the best thing. Because for plain if-ladder cases it feels more > >> > > > > > readable to stick with the current scheme of arithmetic comparisons. And it > >> > > > > > is more efficient in code as well. > >> > > > > > > >> > > > > > Range checks are on the other hand useful either when combined in the same > >> > > > > > conditional as some other bitmask based test, or when both ends of the > >> > > > > > comparison edge are bound. > >> > > > > > >> > > > > So are you against changing the == to use the macros, changing the >=, >, <, <=, > >> > > > > or all of them? > >> > > > > >> > > > Definitely not all of them. Just plain if ladders I think are definitely > >> > > > more readable in source and result in better code in the normal fashion of: > >> > > > > >> > > > if (gen >= 11) > >> > > > else if (gen >= 9) > >> > > > else if (gen >= 7) > >> > > > ... etc ... > >> > > > > >> > > > Where I think it makes sense is when either both edges are bound, like: > >> > > > > >> > > > if (gen < 11 || gen >= 8) > >> > > > if (gen >= 10 || gen == 8) > >> > > > >> > > ok, I will take a look before respinning this. > >> > > > >> > > > > >> > > > But not sure how many of those there are. > >> > > > > >> > > > What definitely exists in large-ish numbers are: > >> > > >> > specially on display side... > >> > > >> > > > > >> > > > if (gen >= 11 || IS_PLATFORM) > >> > > >> > My goal is exactly to organize the gen numbers in a way that > >> > we minimize this mix as much as possible. > >> > > >> > > > > >> > > > At some point I had a prototype which puts the gen and platform masks into a > >> > > > bag of bits and then, depending on bits locality, this too can be compressed > >> > > > to a single bitmask test. However I felt that was going too far, and the > >> > > > issue is achieving interesting bits locality for it too work. But I digress. > >> > > > > >> > > > > Looking at the changes to ==, they seem very reasonable and in a few cases it allowed > >> > > > > the next patch to merge them in a GT_GEN_RANGE() -- yes the patch ordering was on > >> > > > > purpose to allow that. > >> > > > > >> > > > Yep those are the good ones. > >> > > > > >> > > > > The others are indeed debatable. However IMO for the cases it makes sense, > >> > > > > there's always the fallback > >> > > > > > >> > > > > if (dev_priv->info.gen == 10) > >> > > > > ... > >> > > > > else if (dev_priv->info.gen == 11) > >> > > > > ... > >> > > > > else if (dev_priv->info.gen < 5) > >> > > > > ... > >> > > > > > >> > > > > We can go on a case by case manner in this patch rather than the mass conversion > >> > > > > for these. > >> > > > > > >> > > > > > > >> > > > > > > drm/i915: merge gen checks to use range > >> > > > > > > drm/i915: remove INTEL_GEN macro > >> > > > > > > >> > > > > > I have reservations about this as as well, especially considering the > >> > > > > > previous paragraph. But even on it's own I am not sure we want to go back to > >> > > > > > more verbose. > >> > > > > > >> > > > > see above. IMO it's not actually so verbose as one would think. > >> > > > > > >> > > > > if (INTEL_GEN(dev_priv) == 11) > >> > > > > vs > >> > > > > if (dev_priv->info.gen == 11) > >> > > > > >> > > > I think it should be: > >> > > > > >> > > > if (INTEL_INFO(dev_priv)->gen == 11) > >> > > > > >> > > > Which is a tiny bit longer.. > >> > > > >> > > If it's longer, why bother? We could just as well do for the if ladders: > >> > > > >> > > gen = dev_priv->info.gen; > >> > > or > >> > > gen = INTEL_INFO(dev_priv)->gen > >> > > > >> > > In your other series you would be moving gen to a runtime info, so this > >> > > would cause the same amount of churn (although I disagree with moving gen to a runtime > >> > > info just because of the mock struct). > >> > > > >> > > > >> > > > > >> > > > > The "verbose" version is actually one character less and one lookup less > >> > > > > to what the macro is doing underneath. Of course that means a lot of churn > >> > > > > to the codebase when/if we change where the gen number is located, but that > >> > > > > number is at the same place since its introduction in 2010 > >> > > > > (commit c96c3a8cb7fadcb33d9a5ebe35fcee8b7d0a7946) > >> > > > > >> > > > I am pretty sure we went through patches to a) move towards INTEL_INFO and > >> > > > b) replace INTEL_INFO(dev_priv)->gen with INTEL_GEN. So I don't see an > >> > > > advantage of reverting that, just so that we can lose the IS_ prefix below. > >> > > > > >> > > > > > Perhaps in the new scheme of things it should be renamed to INTEL_GT_GEN? I > >> > > > > > know it doesn't fit nicely with the naming scheme of GT/DISPLAY_GEN.. so > >> > > > > > maybe: > >> > > > > > > >> > > > > > GT_GEN -> IS_GT_GEN > >> > > > > > GT_GEN_RANGE -> IS_GT_GEN_RANGE > >> > > > > > INTEL_GEN -> GT_GEN (but churn!?) > >> > > > > > >> > > > > I still think INTEL_GEN() is not bringing much clarity and forcing > >> > > > > the other macros to have the IS_ prefix. > >> > > > > >> > > > Is the IS_ prefix that bad? > >> > > >> > I personally don't like it... but maybe it is just my bad english?! > >> > > >> > 1. if gen 9 > >> > 2. if is gen 9 > >> > 3. if this is a gen 9 platform > >> > > >> > I like more the option 1... > >> > > >> > > > > >> > > > I agree my idea does not decrease the amount of churn, since it said to > >> > > > replace INTEL_GEN with INTEL_GT_GEN. But in the light of the GT/DISPLAY > >> > > > split, and if we agree to leave a lot of the arithmetic comparison in > >> > > > (dialing down of "drm/i915: replace gen checks using operators by > >> > > > GT_GEN/GT_GEN_RANGE"), then it feels going back to INTEL_INFO(dev_priv)->gen > >> > > > throughout the code is undoing some work, just so you can remove the > >> > > > INTEL_GEN macro instead of renaming it INTEL_GT_GEN. > >> > > > > >> > > > Don't know, it's my opinion at least and more people are welcome to chime in > >> > > > with theirs. > >> > > > >> > > Any others to chime in on this? Jani, Ville, Rodrigo? > >> > > >> > I don't like mixed styles much. If we don't kill the macro we will continue > >> > having mixed cases. > >> > > >> > So I'm in favor of the approach of this series here. > >> > >> Including the removal of INTEL_GEN macro? Or what do you propose for that > >> one? Can't be called GT_GEN now since that has been used up... > > > > Yes, including the removal of INTEL_GEN macro. > > > > I don't like the mixed styles like using INTEL_GEN(d) > 7 in one place > > and INTEL_GEN_RANGE(d, 7, FOREVER) in another place. > > > > The meaning is the same so we should stick with one of the usages. > > > > I see that there were many cases where having the info->gen number > > directly is useful. But I'd prefer to use that on a direct fashion > > rather than keeping this macro. > > > > Because if we keep the macro developers will eventually end up > > adding the mixed style back. > > > > Using direct info->gen as Lucas already showed has almost same number > > of chars than the macro, but requires more attention what is a good > > thing. > > I prefer using INTEL_GEN() because it hides where the gen comes from, > and we can change it on a whim. If we keep using dev_priv->info.gen > we'll need to change that already when info becomes a pointer, > i.e. dev_priv->info->gen. Throughout the codebase. With INTEL_GEN() it's > just a couple of places. patch 7 actually does: - INTEL_GEN(E) + INTEL_INFO(E)->gen So still using the macro and if info becomes a pointer it would still be correct. My main motivation for removing it is not INTEL_GEN() itself, but because that would force us to keep the IS_ prefix in the other macros. IS_GT_GEN_RANGE is too big and ugly IMO. If my previous proposal of using a single macro for both range and single gen would be accepted, I think keeping the IS_ prefix would not be so ugly. Anyway, considering the addition of display macros, do you think it should be like below? IS_GEN -> IS_GT_GEN() `> IS_GT_GEN_RANGE() (dialing down on the changes as suggested by Tvrtko to preserve plain if ladders and simple unbound ranges) IS_GEN<N> -> IS_GT_GEN(..., N) INTEL_GEN -> GT_GEN() IS_DISPLAY_GEN() IS_DISPLAY_GEN_RANGE() DISPLAY_GEN() Other option: just do the IS_GEN<N> IS_GEN(..., N), that was the original motivation for this series, and remember that gen here refers to GT. Lucas De Marchi > > If mixed use is a problem, then rename gen to __gen. I even sent a patch > for it, but didn't get it merged. > > BR, > Jani. > > > -- > Jani Nikula, Intel Open Source Graphics Center _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [PATCH v2 0/7] Make GEN macros more similar 2018-11-27 9:36 ` Lucas De Marchi @ 2018-11-27 11:35 ` Tvrtko Ursulin 2018-11-28 0:19 ` Rodrigo Vivi 0 siblings, 1 reply; 38+ messages in thread From: Tvrtko Ursulin @ 2018-11-27 11:35 UTC (permalink / raw) To: Lucas De Marchi, Jani Nikula; +Cc: intel-gfx, Lucas De Marchi, Rodrigo Vivi On 27/11/2018 09:36, Lucas De Marchi wrote: > On Tue, Nov 27, 2018 at 10:37:21AM +0200, Jani Nikula wrote: >> On Mon, 26 Nov 2018, Rodrigo Vivi <rodrigo.vivi@intel.com> wrote: >>> On Thu, Nov 22, 2018 at 08:54:30AM +0000, Tvrtko Ursulin wrote: >>>> >>>> >>>> On 21/11/2018 22:19, Rodrigo Vivi wrote: >>>>> On Mon, Nov 19, 2018 at 02:20:55PM -0800, Lucas De Marchi wrote: >>>>>> On Thu, Nov 08, 2018 at 11:23:46AM +0000, Tvrtko Ursulin wrote: >>>>>>> >>>>>>> On 08/11/2018 00:57, Lucas De Marchi wrote: >>>>>>>> On Wed, Nov 07, 2018 at 10:05:19AM +0000, Tvrtko Ursulin wrote: >>>>>>>>> >>>>>>>>> On 06/11/2018 21:51, Lucas De Marchi wrote: >>>>>>>>>> This is the second version of the series trying to make GEN checks >>>>>>>>>> more similar. These or roughly the changes from v1: >>>>>>>>>> >>>>>>>>>> - We don't have a single macro receiving 2 or 3 parameters. Now there >>>>>>>>>> is GT_GEN_RANGE(), and GT_GEN(). The firs is the conversion from >>>>>>>>>> IS_GEN() while the second is the conversion from IS_GEN<N>() >>>>>>>>>> - Bring GEN_FOREVER back to be used with above macros >>>>>>>>>> - Patch converting <, <=, ==, >, >= checks using INTEL_GEN() to >>>>>>>>>> use the macros above was added >>>>>>>>>> - INTEL_GEN() is removed to avoid it being used when we should prefer >>>>>>>>>> the new macros >>>>>>>>>> >>>>>>>>>> The idea of the names is to pave the way for checks of the display version, >>>>>>>>>> which would be named DISPLAY_GEN(), DISPLAY_GEN_RANGE(). >>>>>>>>>> >>>>>>>>>> In the commit messages we have the scripts to regenerate the patch to make >>>>>>>>>> it easier to apply after the discussions and also to be able to convert >>>>>>>>>> inflight patches. >>>>>>>>>> >>>>>>>>>> Sorry in advance for the noise this causes in the codebase, but hopefully >>>>>>>>>> it is for the greater good. >>>>>>>>>> >>>>>>>>>> >>>>>>>>>> Lucas De Marchi (6): >>>>>>>>>> Revert "drm/i915: Kill GEN_FOREVER" >>>>>>>>>> drm/i915: replace IS_GEN<N> with GT_GEN(..., N) >>>>>>>>>> drm/i915: rename IS_GEN9_* to GT_GEN9_* >>>>>>>>>> drm/i915: replace gen checks using operators by GT_GEN/GT_GEN_RANGE >>>>>>>>> >>>>>>>>> I have reservations about this patch, where I think forcing only one flavour >>>>>>>>> maybe is not the best thing. Because for plain if-ladder cases it feels more >>>>>>>>> readable to stick with the current scheme of arithmetic comparisons. And it >>>>>>>>> is more efficient in code as well. >>>>>>>>> >>>>>>>>> Range checks are on the other hand useful either when combined in the same >>>>>>>>> conditional as some other bitmask based test, or when both ends of the >>>>>>>>> comparison edge are bound. >>>>>>>> >>>>>>>> So are you against changing the == to use the macros, changing the >=, >, <, <=, >>>>>>>> or all of them? >>>>>>> >>>>>>> Definitely not all of them. Just plain if ladders I think are definitely >>>>>>> more readable in source and result in better code in the normal fashion of: >>>>>>> >>>>>>> if (gen >= 11) >>>>>>> else if (gen >= 9) >>>>>>> else if (gen >= 7) >>>>>>> ... etc ... >>>>>>> >>>>>>> Where I think it makes sense is when either both edges are bound, like: >>>>>>> >>>>>>> if (gen < 11 || gen >= 8) >>>>>>> if (gen >= 10 || gen == 8) >>>>>> >>>>>> ok, I will take a look before respinning this. >>>>>> >>>>>>> >>>>>>> But not sure how many of those there are. >>>>>>> >>>>>>> What definitely exists in large-ish numbers are: >>>>> >>>>> specially on display side... >>>>> >>>>>>> >>>>>>> if (gen >= 11 || IS_PLATFORM) >>>>> >>>>> My goal is exactly to organize the gen numbers in a way that >>>>> we minimize this mix as much as possible. >>>>> >>>>>>> >>>>>>> At some point I had a prototype which puts the gen and platform masks into a >>>>>>> bag of bits and then, depending on bits locality, this too can be compressed >>>>>>> to a single bitmask test. However I felt that was going too far, and the >>>>>>> issue is achieving interesting bits locality for it too work. But I digress. >>>>>>> >>>>>>>> Looking at the changes to ==, they seem very reasonable and in a few cases it allowed >>>>>>>> the next patch to merge them in a GT_GEN_RANGE() -- yes the patch ordering was on >>>>>>>> purpose to allow that. >>>>>>> >>>>>>> Yep those are the good ones. >>>>>>> >>>>>>>> The others are indeed debatable. However IMO for the cases it makes sense, >>>>>>>> there's always the fallback >>>>>>>> >>>>>>>> if (dev_priv->info.gen == 10) >>>>>>>> ... >>>>>>>> else if (dev_priv->info.gen == 11) >>>>>>>> ... >>>>>>>> else if (dev_priv->info.gen < 5) >>>>>>>> ... >>>>>>>> >>>>>>>> We can go on a case by case manner in this patch rather than the mass conversion >>>>>>>> for these. >>>>>>>> >>>>>>>>> >>>>>>>>>> drm/i915: merge gen checks to use range >>>>>>>>>> drm/i915: remove INTEL_GEN macro >>>>>>>>> >>>>>>>>> I have reservations about this as as well, especially considering the >>>>>>>>> previous paragraph. But even on it's own I am not sure we want to go back to >>>>>>>>> more verbose. >>>>>>>> >>>>>>>> see above. IMO it's not actually so verbose as one would think. >>>>>>>> >>>>>>>> if (INTEL_GEN(dev_priv) == 11) >>>>>>>> vs >>>>>>>> if (dev_priv->info.gen == 11) >>>>>>> >>>>>>> I think it should be: >>>>>>> >>>>>>> if (INTEL_INFO(dev_priv)->gen == 11) >>>>>>> >>>>>>> Which is a tiny bit longer.. >>>>>> >>>>>> If it's longer, why bother? We could just as well do for the if ladders: >>>>>> >>>>>> gen = dev_priv->info.gen; >>>>>> or >>>>>> gen = INTEL_INFO(dev_priv)->gen >>>>>> >>>>>> In your other series you would be moving gen to a runtime info, so this >>>>>> would cause the same amount of churn (although I disagree with moving gen to a runtime >>>>>> info just because of the mock struct). >>>>>> >>>>>> >>>>>>> >>>>>>>> The "verbose" version is actually one character less and one lookup less >>>>>>>> to what the macro is doing underneath. Of course that means a lot of churn >>>>>>>> to the codebase when/if we change where the gen number is located, but that >>>>>>>> number is at the same place since its introduction in 2010 >>>>>>>> (commit c96c3a8cb7fadcb33d9a5ebe35fcee8b7d0a7946) >>>>>>> >>>>>>> I am pretty sure we went through patches to a) move towards INTEL_INFO and >>>>>>> b) replace INTEL_INFO(dev_priv)->gen with INTEL_GEN. So I don't see an >>>>>>> advantage of reverting that, just so that we can lose the IS_ prefix below. >>>>>>> >>>>>>>>> Perhaps in the new scheme of things it should be renamed to INTEL_GT_GEN? I >>>>>>>>> know it doesn't fit nicely with the naming scheme of GT/DISPLAY_GEN.. so >>>>>>>>> maybe: >>>>>>>>> >>>>>>>>> GT_GEN -> IS_GT_GEN >>>>>>>>> GT_GEN_RANGE -> IS_GT_GEN_RANGE >>>>>>>>> INTEL_GEN -> GT_GEN (but churn!?) >>>>>>>> >>>>>>>> I still think INTEL_GEN() is not bringing much clarity and forcing >>>>>>>> the other macros to have the IS_ prefix. >>>>>>> >>>>>>> Is the IS_ prefix that bad? >>>>> >>>>> I personally don't like it... but maybe it is just my bad english?! >>>>> >>>>> 1. if gen 9 >>>>> 2. if is gen 9 >>>>> 3. if this is a gen 9 platform >>>>> >>>>> I like more the option 1... >>>>> >>>>>>> >>>>>>> I agree my idea does not decrease the amount of churn, since it said to >>>>>>> replace INTEL_GEN with INTEL_GT_GEN. But in the light of the GT/DISPLAY >>>>>>> split, and if we agree to leave a lot of the arithmetic comparison in >>>>>>> (dialing down of "drm/i915: replace gen checks using operators by >>>>>>> GT_GEN/GT_GEN_RANGE"), then it feels going back to INTEL_INFO(dev_priv)->gen >>>>>>> throughout the code is undoing some work, just so you can remove the >>>>>>> INTEL_GEN macro instead of renaming it INTEL_GT_GEN. >>>>>>> >>>>>>> Don't know, it's my opinion at least and more people are welcome to chime in >>>>>>> with theirs. >>>>>> >>>>>> Any others to chime in on this? Jani, Ville, Rodrigo? >>>>> >>>>> I don't like mixed styles much. If we don't kill the macro we will continue >>>>> having mixed cases. >>>>> >>>>> So I'm in favor of the approach of this series here. >>>> >>>> Including the removal of INTEL_GEN macro? Or what do you propose for that >>>> one? Can't be called GT_GEN now since that has been used up... >>> >>> Yes, including the removal of INTEL_GEN macro. >>> >>> I don't like the mixed styles like using INTEL_GEN(d) > 7 in one place >>> and INTEL_GEN_RANGE(d, 7, FOREVER) in another place. >>> >>> The meaning is the same so we should stick with one of the usages. >>> >>> I see that there were many cases where having the info->gen number >>> directly is useful. But I'd prefer to use that on a direct fashion >>> rather than keeping this macro. >>> >>> Because if we keep the macro developers will eventually end up >>> adding the mixed style back. >>> >>> Using direct info->gen as Lucas already showed has almost same number >>> of chars than the macro, but requires more attention what is a good >>> thing. >> >> I prefer using INTEL_GEN() because it hides where the gen comes from, >> and we can change it on a whim. If we keep using dev_priv->info.gen >> we'll need to change that already when info becomes a pointer, >> i.e. dev_priv->info->gen. Throughout the codebase. With INTEL_GEN() it's >> just a couple of places. > > patch 7 actually does: > > - INTEL_GEN(E) > + INTEL_INFO(E)->gen > > So still using the macro and if info becomes a pointer it would still be > correct. My main motivation for removing it is not INTEL_GEN() itself, > but because that would force us to keep the IS_ prefix in the other > macros. IS_GT_GEN_RANGE is too big and ugly IMO. If my > previous proposal of using a single macro for both range and single gen > would be accepted, I think keeping the IS_ prefix would not be so ugly. > > Anyway, considering the addition of display macros, do you think it should > be like below? > > IS_GEN -> IS_GT_GEN() > `> IS_GT_GEN_RANGE() (dialing down on the changes as suggested by > Tvrtko to preserve plain if ladders and > simple unbound ranges) More range macro usage will help future per SKU builds work. So as said in my previous reply, if people can stomach this, I am okay with having this conversion as well. (From arithmetic gen comparison to ...GEN_RANGE everywhere.) That would also makes the question of INTEL_GEN mostly irrelevant. So I think above is the main point to clarify first. Then on the question of IS_ prefix or not, I don't feel very strongly about it. IS_ has a nice parallel with HAS_ and IS_platform, but I agree it doesn't look the prettiest (IS_GT_GEN). So don't know, whatever the vote ends up being. Regards, Tvrtko > IS_GEN<N> -> IS_GT_GEN(..., N) > INTEL_GEN -> GT_GEN() > > IS_DISPLAY_GEN() > IS_DISPLAY_GEN_RANGE() > DISPLAY_GEN() > > > Other option: just do the IS_GEN<N> IS_GEN(..., N), > that was the original motivation for this series, and remember that > gen here refers to GT. > > Lucas De Marchi > >> >> If mixed use is a problem, then rename gen to __gen. I even sent a patch >> for it, but didn't get it merged. >> >> BR, >> Jani. >> >> >> -- >> Jani Nikula, Intel Open Source Graphics Center > _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [PATCH v2 0/7] Make GEN macros more similar 2018-11-27 11:35 ` Tvrtko Ursulin @ 2018-11-28 0:19 ` Rodrigo Vivi 2018-11-28 17:22 ` Lucas De Marchi 0 siblings, 1 reply; 38+ messages in thread From: Rodrigo Vivi @ 2018-11-28 0:19 UTC (permalink / raw) To: Tvrtko Ursulin; +Cc: intel-gfx, Lucas De Marchi On Tue, Nov 27, 2018 at 11:35:54AM +0000, Tvrtko Ursulin wrote: > > On 27/11/2018 09:36, Lucas De Marchi wrote: > > On Tue, Nov 27, 2018 at 10:37:21AM +0200, Jani Nikula wrote: > > > On Mon, 26 Nov 2018, Rodrigo Vivi <rodrigo.vivi@intel.com> wrote: > > > > On Thu, Nov 22, 2018 at 08:54:30AM +0000, Tvrtko Ursulin wrote: > > > > > > > > > > > > > > > On 21/11/2018 22:19, Rodrigo Vivi wrote: > > > > > > On Mon, Nov 19, 2018 at 02:20:55PM -0800, Lucas De Marchi wrote: > > > > > > > On Thu, Nov 08, 2018 at 11:23:46AM +0000, Tvrtko Ursulin wrote: > > > > > > > > > > > > > > > > On 08/11/2018 00:57, Lucas De Marchi wrote: > > > > > > > > > On Wed, Nov 07, 2018 at 10:05:19AM +0000, Tvrtko Ursulin wrote: > > > > > > > > > > > > > > > > > > > > On 06/11/2018 21:51, Lucas De Marchi wrote: > > > > > > > > > > > This is the second version of the series trying to make GEN checks > > > > > > > > > > > more similar. These or roughly the changes from v1: > > > > > > > > > > > > > > > > > > > > > > - We don't have a single macro receiving 2 or 3 parameters. Now there > > > > > > > > > > > is GT_GEN_RANGE(), and GT_GEN(). The firs is the conversion from > > > > > > > > > > > IS_GEN() while the second is the conversion from IS_GEN<N>() > > > > > > > > > > > - Bring GEN_FOREVER back to be used with above macros > > > > > > > > > > > - Patch converting <, <=, ==, >, >= checks using INTEL_GEN() to > > > > > > > > > > > use the macros above was added > > > > > > > > > > > - INTEL_GEN() is removed to avoid it being used when we should prefer > > > > > > > > > > > the new macros > > > > > > > > > > > > > > > > > > > > > > The idea of the names is to pave the way for checks of the display version, > > > > > > > > > > > which would be named DISPLAY_GEN(), DISPLAY_GEN_RANGE(). > > > > > > > > > > > > > > > > > > > > > > In the commit messages we have the scripts to regenerate the patch to make > > > > > > > > > > > it easier to apply after the discussions and also to be able to convert > > > > > > > > > > > inflight patches. > > > > > > > > > > > > > > > > > > > > > > Sorry in advance for the noise this causes in the codebase, but hopefully > > > > > > > > > > > it is for the greater good. > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > Lucas De Marchi (6): > > > > > > > > > > > Revert "drm/i915: Kill GEN_FOREVER" > > > > > > > > > > > drm/i915: replace IS_GEN<N> with GT_GEN(..., N) > > > > > > > > > > > drm/i915: rename IS_GEN9_* to GT_GEN9_* > > > > > > > > > > > drm/i915: replace gen checks using operators by GT_GEN/GT_GEN_RANGE > > > > > > > > > > > > > > > > > > > > I have reservations about this patch, where I think forcing only one flavour > > > > > > > > > > maybe is not the best thing. Because for plain if-ladder cases it feels more > > > > > > > > > > readable to stick with the current scheme of arithmetic comparisons. And it > > > > > > > > > > is more efficient in code as well. > > > > > > > > > > > > > > > > > > > > Range checks are on the other hand useful either when combined in the same > > > > > > > > > > conditional as some other bitmask based test, or when both ends of the > > > > > > > > > > comparison edge are bound. > > > > > > > > > > > > > > > > > > So are you against changing the == to use the macros, changing the >=, >, <, <=, > > > > > > > > > or all of them? > > > > > > > > > > > > > > > > Definitely not all of them. Just plain if ladders I think are definitely > > > > > > > > more readable in source and result in better code in the normal fashion of: > > > > > > > > > > > > > > > > if (gen >= 11) > > > > > > > > else if (gen >= 9) > > > > > > > > else if (gen >= 7) > > > > > > > > ... etc ... > > > > > > > > > > > > > > > > Where I think it makes sense is when either both edges are bound, like: > > > > > > > > > > > > > > > > if (gen < 11 || gen >= 8) > > > > > > > > if (gen >= 10 || gen == 8) > > > > > > > > > > > > > > ok, I will take a look before respinning this. > > > > > > > > > > > > > > > > > > > > > > > But not sure how many of those there are. > > > > > > > > > > > > > > > > What definitely exists in large-ish numbers are: > > > > > > > > > > > > specially on display side... > > > > > > > > > > > > > > > > > > > > > > if (gen >= 11 || IS_PLATFORM) > > > > > > > > > > > > My goal is exactly to organize the gen numbers in a way that > > > > > > we minimize this mix as much as possible. > > > > > > > > > > > > > > > > > > > > > > At some point I had a prototype which puts the gen and platform masks into a > > > > > > > > bag of bits and then, depending on bits locality, this too can be compressed > > > > > > > > to a single bitmask test. However I felt that was going too far, and the > > > > > > > > issue is achieving interesting bits locality for it too work. But I digress. > > > > > > > > > > > > > > > > > Looking at the changes to ==, they seem very reasonable and in a few cases it allowed > > > > > > > > > the next patch to merge them in a GT_GEN_RANGE() -- yes the patch ordering was on > > > > > > > > > purpose to allow that. > > > > > > > > > > > > > > > > Yep those are the good ones. > > > > > > > > > > > > > > > > > The others are indeed debatable. However IMO for the cases it makes sense, > > > > > > > > > there's always the fallback > > > > > > > > > > > > > > > > > > if (dev_priv->info.gen == 10) > > > > > > > > > ... > > > > > > > > > else if (dev_priv->info.gen == 11) > > > > > > > > > ... > > > > > > > > > else if (dev_priv->info.gen < 5) > > > > > > > > > ... > > > > > > > > > > > > > > > > > > We can go on a case by case manner in this patch rather than the mass conversion > > > > > > > > > for these. > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > drm/i915: merge gen checks to use range > > > > > > > > > > > drm/i915: remove INTEL_GEN macro > > > > > > > > > > > > > > > > > > > > I have reservations about this as as well, especially considering the > > > > > > > > > > previous paragraph. But even on it's own I am not sure we want to go back to > > > > > > > > > > more verbose. > > > > > > > > > > > > > > > > > > see above. IMO it's not actually so verbose as one would think. > > > > > > > > > > > > > > > > > > if (INTEL_GEN(dev_priv) == 11) > > > > > > > > > vs > > > > > > > > > if (dev_priv->info.gen == 11) > > > > > > > > > > > > > > > > I think it should be: > > > > > > > > > > > > > > > > if (INTEL_INFO(dev_priv)->gen == 11) > > > > > > > > > > > > > > > > Which is a tiny bit longer.. > > > > > > > > > > > > > > If it's longer, why bother? We could just as well do for the if ladders: > > > > > > > > > > > > > > gen = dev_priv->info.gen; > > > > > > > or > > > > > > > gen = INTEL_INFO(dev_priv)->gen > > > > > > > > > > > > > > In your other series you would be moving gen to a runtime info, so this > > > > > > > would cause the same amount of churn (although I disagree with moving gen to a runtime > > > > > > > info just because of the mock struct). > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > The "verbose" version is actually one character less and one lookup less > > > > > > > > > to what the macro is doing underneath. Of course that means a lot of churn > > > > > > > > > to the codebase when/if we change where the gen number is located, but that > > > > > > > > > number is at the same place since its introduction in 2010 > > > > > > > > > (commit c96c3a8cb7fadcb33d9a5ebe35fcee8b7d0a7946) > > > > > > > > > > > > > > > > I am pretty sure we went through patches to a) move towards INTEL_INFO and > > > > > > > > b) replace INTEL_INFO(dev_priv)->gen with INTEL_GEN. So I don't see an > > > > > > > > advantage of reverting that, just so that we can lose the IS_ prefix below. > > > > > > > > > > > > > > > > > > Perhaps in the new scheme of things it should be renamed to INTEL_GT_GEN? I > > > > > > > > > > know it doesn't fit nicely with the naming scheme of GT/DISPLAY_GEN.. so > > > > > > > > > > maybe: > > > > > > > > > > > > > > > > > > > > GT_GEN -> IS_GT_GEN > > > > > > > > > > GT_GEN_RANGE -> IS_GT_GEN_RANGE > > > > > > > > > > INTEL_GEN -> GT_GEN (but churn!?) > > > > > > > > > > > > > > > > > > I still think INTEL_GEN() is not bringing much clarity and forcing > > > > > > > > > the other macros to have the IS_ prefix. > > > > > > > > > > > > > > > > Is the IS_ prefix that bad? > > > > > > > > > > > > I personally don't like it... but maybe it is just my bad english?! > > > > > > > > > > > > 1. if gen 9 > > > > > > 2. if is gen 9 > > > > > > 3. if this is a gen 9 platform > > > > > > > > > > > > I like more the option 1... > > > > > > > > > > > > > > > > > > > > > > I agree my idea does not decrease the amount of churn, since it said to > > > > > > > > replace INTEL_GEN with INTEL_GT_GEN. But in the light of the GT/DISPLAY > > > > > > > > split, and if we agree to leave a lot of the arithmetic comparison in > > > > > > > > (dialing down of "drm/i915: replace gen checks using operators by > > > > > > > > GT_GEN/GT_GEN_RANGE"), then it feels going back to INTEL_INFO(dev_priv)->gen > > > > > > > > throughout the code is undoing some work, just so you can remove the > > > > > > > > INTEL_GEN macro instead of renaming it INTEL_GT_GEN. > > > > > > > > > > > > > > > > Don't know, it's my opinion at least and more people are welcome to chime in > > > > > > > > with theirs. > > > > > > > > > > > > > > Any others to chime in on this? Jani, Ville, Rodrigo? > > > > > > > > > > > > I don't like mixed styles much. If we don't kill the macro we will continue > > > > > > having mixed cases. > > > > > > > > > > > > So I'm in favor of the approach of this series here. > > > > > > > > > > Including the removal of INTEL_GEN macro? Or what do you propose for that > > > > > one? Can't be called GT_GEN now since that has been used up... > > > > > > > > Yes, including the removal of INTEL_GEN macro. > > > > > > > > I don't like the mixed styles like using INTEL_GEN(d) > 7 in one place > > > > and INTEL_GEN_RANGE(d, 7, FOREVER) in another place. > > > > > > > > The meaning is the same so we should stick with one of the usages. > > > > > > > > I see that there were many cases where having the info->gen number > > > > directly is useful. But I'd prefer to use that on a direct fashion > > > > rather than keeping this macro. > > > > > > > > Because if we keep the macro developers will eventually end up > > > > adding the mixed style back. > > > > > > > > Using direct info->gen as Lucas already showed has almost same number > > > > of chars than the macro, but requires more attention what is a good > > > > thing. > > > > > > I prefer using INTEL_GEN() because it hides where the gen comes from, > > > and we can change it on a whim. If we keep using dev_priv->info.gen > > > we'll need to change that already when info becomes a pointer, > > > i.e. dev_priv->info->gen. Throughout the codebase. With INTEL_GEN() it's > > > just a couple of places. > > > > patch 7 actually does: > > > > - INTEL_GEN(E) > > + INTEL_INFO(E)->gen > > > > So still using the macro and if info becomes a pointer it would still be > > correct. My main motivation for removing it is not INTEL_GEN() itself, > > but because that would force us to keep the IS_ prefix in the other > > macros. IS_GT_GEN_RANGE is too big and ugly IMO. If my > > previous proposal of using a single macro for both range and single gen > > would be accepted, I think keeping the IS_ prefix would not be so ugly. > > > > Anyway, considering the addition of display macros, do you think it should > > be like below? > > > > IS_GEN -> IS_GT_GEN() > > `> IS_GT_GEN_RANGE() (dialing down on the changes as suggested by > > Tvrtko to preserve plain if ladders and > > simple unbound ranges) > > More range macro usage will help future per SKU builds work. So as said in > my previous reply, if people can stomach this, I am okay with having this > conversion as well. (From arithmetic gen comparison to ...GEN_RANGE > everywhere.) > > That would also makes the question of INTEL_GEN mostly irrelevant. So I > think above is the main point to clarify first. > > Then on the question of IS_ prefix or not, I don't feel very strongly about > it. IS_ has a nice parallel with HAS_ and IS_platform, but I agree it > doesn't look the prettiest (IS_GT_GEN). So don't know, whatever the vote > ends up being. okay, the HAS_ parallel is a good point... but still in that case my brain prefers if HAS_FEATURE than if FEATURE because "FEATURE what?" Like if feature was more "transitive" requiring something else. while for "is" my brain prefers if PLATFORM than if IS_PLATFORM because here it seems more "intransitive"... like... self contained meaning where "is" can be implicit. > > Regards, > > Tvrtko > > > IS_GEN<N> -> IS_GT_GEN(..., N) > > INTEL_GEN -> GT_GEN() > > > > IS_DISPLAY_GEN() > > IS_DISPLAY_GEN_RANGE() > > DISPLAY_GEN() > > > > > > Other option: just do the IS_GEN<N> IS_GEN(..., N), > > that was the original motivation for this series, and remember that > > gen here refers to GT. > > > > Lucas De Marchi > > > > > > > > If mixed use is a problem, then rename gen to __gen. I even sent a patch > > > for it, but didn't get it merged. > > > > > > BR, > > > Jani. > > > > > > > > > -- > > > Jani Nikula, Intel Open Source Graphics Center > > _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [PATCH v2 0/7] Make GEN macros more similar 2018-11-28 0:19 ` Rodrigo Vivi @ 2018-11-28 17:22 ` Lucas De Marchi 0 siblings, 0 replies; 38+ messages in thread From: Lucas De Marchi @ 2018-11-28 17:22 UTC (permalink / raw) To: Rodrigo Vivi; +Cc: intel-gfx, Lucas De Marchi On Tue, Nov 27, 2018 at 04:19:23PM -0800, Rodrigo Vivi wrote: > > Then on the question of IS_ prefix or not, I don't feel very strongly about > > it. IS_ has a nice parallel with HAS_ and IS_platform, but I agree it > > doesn't look the prettiest (IS_GT_GEN). So don't know, whatever the vote > > ends up being. > > okay, the HAS_ parallel is a good point... > > but still in that case my brain prefers > > if HAS_FEATURE > than > if FEATURE > > because "FEATURE what?" Like if feature was more "transitive" requiring something else. > > while for "is" my brain prefers > > if PLATFORM > than > if IS_PLATFORM > > because here it seems more "intransitive"... > like... self contained meaning where "is" can be implicit. for me both IS_PLATFORM and PLATFORM make sense. IS_ prefix is used in several other places for things like that. I just don't like the outcome of having it: gigantic horrendous macros like IS_GT_GEN_RANGE(). Lucas De Marchi _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [PATCH v2 0/7] Make GEN macros more similar 2018-11-19 22:20 ` Lucas De Marchi 2018-11-20 13:40 ` Tvrtko Ursulin 2018-11-21 22:19 ` Rodrigo Vivi @ 2018-11-23 12:44 ` Jani Nikula 2 siblings, 0 replies; 38+ messages in thread From: Jani Nikula @ 2018-11-23 12:44 UTC (permalink / raw) To: Lucas De Marchi, Tvrtko Ursulin; +Cc: intel-gfx, Lucas De Marchi, Rodrigo Vivi On Mon, 19 Nov 2018, Lucas De Marchi <lucas.de.marchi@gmail.com> wrote: > On Thu, Nov 08, 2018 at 11:23:46AM +0000, Tvrtko Ursulin wrote: >> Don't know, it's my opinion at least and more people are welcome to chime in >> with theirs. > > Any others to chime in on this? Jani, Ville, Rodrigo? Please hold until all aspects have been discussed. Thanks, Jani. -- Jani Nikula, Intel Open Source Graphics Center _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 38+ messages in thread
* ✗ Fi.CI.CHECKPATCH: warning for Make GEN macros more similar (rev2) 2018-11-06 21:51 [PATCH v2 0/7] Make GEN macros more similar Lucas De Marchi ` (7 preceding siblings ...) 2018-11-07 10:05 ` [PATCH v2 0/7] Make GEN macros more similar Tvrtko Ursulin @ 2018-11-07 14:10 ` Patchwork 2018-11-07 14:14 ` ✗ Fi.CI.SPARSE: " Patchwork ` (2 subsequent siblings) 11 siblings, 0 replies; 38+ messages in thread From: Patchwork @ 2018-11-07 14:10 UTC (permalink / raw) To: Lucas De Marchi; +Cc: intel-gfx == Series Details == Series: Make GEN macros more similar (rev2) URL : https://patchwork.freedesktop.org/series/51860/ State : warning == Summary == $ dim checkpatch origin/drm-tip d15504ef1f13 Revert "drm/i915: Kill GEN_FOREVER" 322b4c9622f1 drm/i915: Rename IS_GEN to GT_RANGE 0bbf4afc4405 drm/i915: replace IS_GEN<N> with GT_GEN(..., N) -:263: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'dev_priv' - possible side-effects? #263: FILE: drivers/gpu/drm/i915/i915_drv.h:2536: +#define IS_GEN9_LP(dev_priv) (GT_GEN(dev_priv, 9) && IS_LP(dev_priv)) -:264: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'dev_priv' - possible side-effects? #264: FILE: drivers/gpu/drm/i915/i915_drv.h:2537: +#define IS_GEN9_BC(dev_priv) (GT_GEN(dev_priv, 9) && !IS_LP(dev_priv)) -:282: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'dev_priv' - possible side-effects? #282: FILE: drivers/gpu/drm/i915/i915_drv.h:2610: +#define HAS_128_BYTE_Y_TILING(dev_priv) (!GT_GEN(dev_priv, 2) && \ !(IS_I915G(dev_priv) || \ IS_I915GM(dev_priv))) -:442: CHECK:COMPARISON_TO_NULL: Comparison to NULL could be written "!r" #442: FILE: drivers/gpu/drm/i915/i915_gem_stolen.c:159: + if (r == NULL && !GT_GEN(dev_priv, 3)) { -:1127: CHECK:CAMELCASE: Avoid CamelCase: <ILK_eDP_A_DISABLE> #1127: FILE: drivers/gpu/drm/i915/intel_display.c:14047: + if (GT_GEN(dev_priv, 5) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE)) total: 0 errors, 0 warnings, 5 checks, 1787 lines checked 36dad133f489 drm/i915: rename IS_GEN9_* to GT_GEN9_* -:169: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'dev_priv' - possible side-effects? #169: FILE: drivers/gpu/drm/i915/i915_drv.h:2386: +#define GT_GEN9_LP(dev_priv) (GT_GEN(dev_priv, 9) && IS_LP(dev_priv)) -:170: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'dev_priv' - possible side-effects? #170: FILE: drivers/gpu/drm/i915/i915_drv.h:2387: +#define GT_GEN9_BC(dev_priv) (GT_GEN(dev_priv, 9) && !IS_LP(dev_priv)) -:293: ERROR:CODE_INDENT: code indent should use tabs where possible #293: FILE: drivers/gpu/drm/i915/i915_reg.h:3826: + (GT_GEN9_LP(dev_priv) ? \$ -:293: WARNING:LEADING_SPACE: please, no spaces at the start of a line #293: FILE: drivers/gpu/drm/i915/i915_reg.h:3826: + (GT_GEN9_LP(dev_priv) ? \$ -:1311: CHECK:UNNECESSARY_PARENTHESES: Unnecessary parentheses around '!intel_dsi->dual_link' #1311: FILE: drivers/gpu/drm/i915/vlv_dsi.c:1444: + if (GT_GEN9_LP(dev_priv) && (!intel_dsi->dual_link)) { total: 1 errors, 1 warnings, 3 checks, 1093 lines checked 8d54865b9953 drm/i915: replace gen checks using operators by GT_GEN/GT_GEN_RANGE -:179: WARNING:LONG_LINE: line over 100 characters #179: FILE: drivers/gpu/drm/i915/i915_debugfs.c:1204: + (gt_perf_status & (GT_GEN_RANGE(dev_priv, 9, GEN_FOREVER) ? 0x1ff00 : 0xff00)) >> 8); -:321: WARNING:SUSPECT_CODE_INDENT: suspect code indent for conditional statements (8, 63) #321: FILE: drivers/gpu/drm/i915/i915_debugfs.c:1759: + if (GT_GEN_RANGE(dev_priv, 9, GEN_FOREVER)) /* no global SR status; inspect per-plane WM */; -:674: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'dev_priv' - possible side-effects? #674: FILE: drivers/gpu/drm/i915/i915_drv.h:2604: +#define HAS_GMBUS_BURST_READ(dev_priv) (GT_GEN_RANGE(dev_priv, 10, GEN_FOREVER) || \ IS_GEMINILAKE(dev_priv) || \ IS_KABYLAKE(dev_priv)) -:683: WARNING:SPACE_BEFORE_TAB: please, no space before tabs #683: FILE: drivers/gpu/drm/i915/i915_drv.h:2617: +#define HAS_FW_BLC(dev_priv) ^I(GT_GEN_RANGE(dev_priv, 3, GEN_FOREVER))$ -:686: WARNING:LONG_LINE: line over 100 characters #686: FILE: drivers/gpu/drm/i915/i915_drv.h:2619: +#define HAS_CUR_FBC(dev_priv) (!HAS_GMCH_DISPLAY(dev_priv) && GT_GEN_RANGE(dev_priv, 7, GEN_FOREVER)) -:686: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'dev_priv' - possible side-effects? #686: FILE: drivers/gpu/drm/i915/i915_drv.h:2619: +#define HAS_CUR_FBC(dev_priv) (!HAS_GMCH_DISPLAY(dev_priv) && GT_GEN_RANGE(dev_priv, 7, GEN_FOREVER)) -:1609: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses #1609: FILE: drivers/gpu/drm/i915/i915_reg.h:3816: +#define GT_INTERVAL_FROM_US(dev_priv, us) (GT_GEN_RANGE(dev_priv, 9, GEN_FOREVER) ? \ (GT_GEN9_LP(dev_priv) ? \ INTERVAL_0_833_US(us) : \ INTERVAL_1_33_US(us)) : \ -:1609: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'dev_priv' - possible side-effects? #1609: FILE: drivers/gpu/drm/i915/i915_reg.h:3816: +#define GT_INTERVAL_FROM_US(dev_priv, us) (GT_GEN_RANGE(dev_priv, 9, GEN_FOREVER) ? \ (GT_GEN9_LP(dev_priv) ? \ INTERVAL_0_833_US(us) : \ INTERVAL_1_33_US(us)) : \ -:1609: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'us' - possible side-effects? #1609: FILE: drivers/gpu/drm/i915/i915_reg.h:3816: +#define GT_INTERVAL_FROM_US(dev_priv, us) (GT_GEN_RANGE(dev_priv, 9, GEN_FOREVER) ? \ (GT_GEN9_LP(dev_priv) ? \ INTERVAL_0_833_US(us) : \ INTERVAL_1_33_US(us)) : \ -:1618: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses #1618: FILE: drivers/gpu/drm/i915/i915_reg.h:3825: +#define GT_PM_INTERVAL_TO_US(dev_priv, interval) (GT_GEN_RANGE(dev_priv, 9, GEN_FOREVER) ? \ (GT_GEN9_LP(dev_priv) ? \ INTERVAL_0_833_TO_US(interval) : \ INTERVAL_1_33_TO_US(interval)) : \ -:1618: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'dev_priv' - possible side-effects? #1618: FILE: drivers/gpu/drm/i915/i915_reg.h:3825: +#define GT_PM_INTERVAL_TO_US(dev_priv, interval) (GT_GEN_RANGE(dev_priv, 9, GEN_FOREVER) ? \ (GT_GEN9_LP(dev_priv) ? \ INTERVAL_0_833_TO_US(interval) : \ INTERVAL_1_33_TO_US(interval)) : \ -:1618: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'interval' - possible side-effects? #1618: FILE: drivers/gpu/drm/i915/i915_reg.h:3825: +#define GT_PM_INTERVAL_TO_US(dev_priv, interval) (GT_GEN_RANGE(dev_priv, 9, GEN_FOREVER) ? \ (GT_GEN9_LP(dev_priv) ? \ INTERVAL_0_833_TO_US(interval) : \ INTERVAL_1_33_TO_US(interval)) : \ -:2429: CHECK:UNNECESSARY_PARENTHESES: Unnecessary parentheses around 'port == PORT_E' #2429: FILE: drivers/gpu/drm/i915/intel_display.c:9502: + if (GT_GEN_RANGE(dev_priv, 0, 8) && (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) { -:2877: WARNING:UNSPECIFIED_INT: Prefer 'unsigned int' to bare use of 'unsigned' #2877: FILE: drivers/gpu/drm/i915/intel_display.c:15845: + unsigned reg = GT_GEN_RANGE(dev_priv, 6, GEN_FOREVER) ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL; -:3185: WARNING:BRACES: braces {} are not necessary for single statement blocks #3185: FILE: drivers/gpu/drm/i915/intel_engine_cs.c:1306: + if (GT_GEN_RANGE(dev_priv, 6, GEN_FOREVER)) { drm_printf(m, "\tRING_IMR: %08x\n", I915_READ_IMR(engine)); } -:4249: CHECK:UNNECESSARY_PARENTHESES: Unnecessary parentheses around 'intel_dp->psr_dpcd[0] == DP_PSR2_WITH_Y_COORD_IS_SUPPORTED' #4249: FILE: drivers/gpu/drm/i915/intel_psr.c:245: + if (GT_GEN_RANGE(dev_priv, 9, GEN_FOREVER) && (intel_dp->psr_dpcd[0] == DP_PSR2_WITH_Y_COORD_IS_SUPPORTED)) { -:4547: WARNING:BRACES: braces {} are not necessary for single statement blocks #4547: FILE: drivers/gpu/drm/i915/intel_sdvo.c:2454: + if (GT_GEN_RANGE(dev_priv, 4, GEN_FOREVER) && IS_MOBILE(dev_priv)) { intel_attach_broadcast_rgb_property(&connector->base.base); } total: 2 errors, 7 warnings, 8 checks, 4310 lines checked 90392f31f7da drm/i915: merge gen checks to use range 73c65e0e7e5f drm/i915: remove INTEL_GEN macro _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 38+ messages in thread
* ✗ Fi.CI.SPARSE: warning for Make GEN macros more similar (rev2) 2018-11-06 21:51 [PATCH v2 0/7] Make GEN macros more similar Lucas De Marchi ` (8 preceding siblings ...) 2018-11-07 14:10 ` ✗ Fi.CI.CHECKPATCH: warning for Make GEN macros more similar (rev2) Patchwork @ 2018-11-07 14:14 ` Patchwork 2018-11-07 14:30 ` ✓ Fi.CI.BAT: success " Patchwork 2018-11-07 21:17 ` ✓ Fi.CI.IGT: " Patchwork 11 siblings, 0 replies; 38+ messages in thread From: Patchwork @ 2018-11-07 14:14 UTC (permalink / raw) To: Lucas De Marchi; +Cc: intel-gfx == Series Details == Series: Make GEN macros more similar (rev2) URL : https://patchwork.freedesktop.org/series/51860/ State : warning == Summary == $ dim sparse origin/drm-tip Sparse version: v0.5.2 Commit: Revert "drm/i915: Kill GEN_FOREVER" -drivers/gpu/drm/i915/selftests/../i915_drv.h:3705:16: warning: expression using sizeof(void) +drivers/gpu/drm/i915/selftests/../i915_drv.h:3713:16: warning: expression using sizeof(void) Commit: drm/i915: Rename IS_GEN to GT_RANGE Okay! Commit: drm/i915: replace IS_GEN<N> with GT_GEN(..., N) -O:drivers/gpu/drm/i915/intel_cdclk.c:2178:37: warning: expression using sizeof(void) -O:drivers/gpu/drm/i915/intel_cdclk.c:2181:37: warning: expression using sizeof(void) +drivers/gpu/drm/i915/intel_cdclk.c:2178:37: warning: expression using sizeof(void) +drivers/gpu/drm/i915/intel_cdclk.c:2181:37: warning: expression using sizeof(void) -O:drivers/gpu/drm/i915/intel_fbc.c:88:25: warning: expression using sizeof(void) -O:drivers/gpu/drm/i915/intel_fbc.c:90:25: warning: expression using sizeof(void) +drivers/gpu/drm/i915/intel_fbc.c:88:25: warning: expression using sizeof(void) +drivers/gpu/drm/i915/intel_fbc.c:90:25: warning: expression using sizeof(void) -drivers/gpu/drm/i915/selftests/../i915_drv.h:3713:16: warning: expression using sizeof(void) +drivers/gpu/drm/i915/selftests/../i915_drv.h:3700:16: warning: expression using sizeof(void) Commit: drm/i915: rename IS_GEN9_* to GT_GEN9_* -drivers/gpu/drm/i915/selftests/../i915_drv.h:3700:16: warning: expression using sizeof(void) +drivers/gpu/drm/i915/selftests/../i915_drv.h:3701:16: warning: expression using sizeof(void) Commit: drm/i915: replace gen checks using operators by GT_GEN/GT_GEN_RANGE -O:drivers/gpu/drm/i915/intel_cdclk.c:2201:29: warning: expression using sizeof(void) +drivers/gpu/drm/i915/intel_cdclk.c:2201:29: warning: expression using sizeof(void) -O:drivers/gpu/drm/i915/intel_fbc.c:88:25: warning: expression using sizeof(void) -O:drivers/gpu/drm/i915/intel_fbc.c:90:25: warning: expression using sizeof(void) +drivers/gpu/drm/i915/intel_fbc.c:88:25: warning: expression using sizeof(void) +drivers/gpu/drm/i915/intel_fbc.c:90:25: warning: expression using sizeof(void) Commit: drm/i915: merge gen checks to use range Okay! Commit: drm/i915: remove INTEL_GEN macro -drivers/gpu/drm/i915/selftests/../i915_drv.h:3701:16: warning: expression using sizeof(void) +drivers/gpu/drm/i915/selftests/../i915_drv.h:3700:16: warning: expression using sizeof(void) _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 38+ messages in thread
* ✓ Fi.CI.BAT: success for Make GEN macros more similar (rev2) 2018-11-06 21:51 [PATCH v2 0/7] Make GEN macros more similar Lucas De Marchi ` (9 preceding siblings ...) 2018-11-07 14:14 ` ✗ Fi.CI.SPARSE: " Patchwork @ 2018-11-07 14:30 ` Patchwork 2018-11-07 21:17 ` ✓ Fi.CI.IGT: " Patchwork 11 siblings, 0 replies; 38+ messages in thread From: Patchwork @ 2018-11-07 14:30 UTC (permalink / raw) To: Lucas De Marchi; +Cc: intel-gfx == Series Details == Series: Make GEN macros more similar (rev2) URL : https://patchwork.freedesktop.org/series/51860/ State : success == Summary == = CI Bug Log - changes from CI_DRM_5097 -> Patchwork_10747 = == Summary - WARNING == Minor unknown changes coming with Patchwork_10747 need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_10747, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://patchwork.freedesktop.org/api/1.0/series/51860/revisions/2/mbox/ == Possible new issues == Here are the unknown changes that may have been introduced in Patchwork_10747: === IGT changes === ==== Warnings ==== igt@gem_exec_basic@basic-render: fi-bsw-n3050: PASS -> SKIP +85 == Known issues == Here are the changes found in Patchwork_10747 that come from known issues: === IGT changes === ==== Issues hit ==== igt@drv_module_reload@basic-reload-inject: fi-byt-clapper: PASS -> WARN (fdo#108688) igt@gem_ctx_create@basic-files: fi-bsw-n3050: PASS -> DMESG-FAIL (fdo#108656) fi-icl-u2: PASS -> DMESG-WARN (fdo#107724) igt@gem_exec_suspend@basic-s3: fi-ctg-p8600: PASS -> INCOMPLETE (fdo#102997) igt@kms_cursor_legacy@basic-flip-before-cursor-varying-size: fi-bsw-n3050: PASS -> DMESG-WARN (fdo#108656) +82 igt@kms_pipe_crc_basic@read-crc-pipe-b-frame-sequence: fi-byt-squawks: PASS -> FAIL (fdo#103191, fdo#107362, fdo#107119) igt@pm_rpm@module-reload: fi-byt-clapper: PASS -> FAIL (fdo#108675) ==== Possible fixes ==== igt@gem_exec_suspend@basic-s3: fi-blb-e6850: INCOMPLETE (fdo#107718) -> PASS igt@kms_frontbuffer_tracking@basic: fi-byt-clapper: FAIL (fdo#103167) -> PASS igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a: fi-byt-clapper: FAIL (fdo#107362) -> PASS igt@kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence: fi-byt-clapper: FAIL (fdo#103191, fdo#107362) -> PASS igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b: fi-cfl-8109u: DMESG-WARN (fdo#107345) -> PASS +2 fdo#102997 https://bugs.freedesktop.org/show_bug.cgi?id=102997 fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167 fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191 fdo#107119 https://bugs.freedesktop.org/show_bug.cgi?id=107119 fdo#107345 https://bugs.freedesktop.org/show_bug.cgi?id=107345 fdo#107362 https://bugs.freedesktop.org/show_bug.cgi?id=107362 fdo#107718 https://bugs.freedesktop.org/show_bug.cgi?id=107718 fdo#107724 https://bugs.freedesktop.org/show_bug.cgi?id=107724 fdo#108656 https://bugs.freedesktop.org/show_bug.cgi?id=108656 fdo#108675 https://bugs.freedesktop.org/show_bug.cgi?id=108675 fdo#108688 https://bugs.freedesktop.org/show_bug.cgi?id=108688 == Participating hosts (52 -> 52) == No changes in participating hosts == Build changes == * Linux: CI_DRM_5097 -> Patchwork_10747 CI_DRM_5097: c20dfc4f015dfd41246beb7d72338aa50543a5ef @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4711: cc41f4c921e56c62c85ec5349c47022ae9b5f008 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_10747: 73c65e0e7e5f8582a24bd4d3e11501dee33453ef @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 73c65e0e7e5f drm/i915: remove INTEL_GEN macro 90392f31f7da drm/i915: merge gen checks to use range 8d54865b9953 drm/i915: replace gen checks using operators by GT_GEN/GT_GEN_RANGE 36dad133f489 drm/i915: rename IS_GEN9_* to GT_GEN9_* 0bbf4afc4405 drm/i915: replace IS_GEN<N> with GT_GEN(..., N) 322b4c9622f1 drm/i915: Rename IS_GEN to GT_RANGE d15504ef1f13 Revert "drm/i915: Kill GEN_FOREVER" == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10747/issues.html _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 38+ messages in thread
* ✓ Fi.CI.IGT: success for Make GEN macros more similar (rev2) 2018-11-06 21:51 [PATCH v2 0/7] Make GEN macros more similar Lucas De Marchi ` (10 preceding siblings ...) 2018-11-07 14:30 ` ✓ Fi.CI.BAT: success " Patchwork @ 2018-11-07 21:17 ` Patchwork 11 siblings, 0 replies; 38+ messages in thread From: Patchwork @ 2018-11-07 21:17 UTC (permalink / raw) To: Lucas De Marchi; +Cc: intel-gfx == Series Details == Series: Make GEN macros more similar (rev2) URL : https://patchwork.freedesktop.org/series/51860/ State : success == Summary == = CI Bug Log - changes from CI_DRM_5097_full -> Patchwork_10747_full = == Summary - WARNING == Minor unknown changes coming with Patchwork_10747_full need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_10747_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. == Possible new issues == Here are the unknown changes that may have been introduced in Patchwork_10747_full: === IGT changes === ==== Warnings ==== igt@pm_rc6_residency@rc6-accuracy: shard-snb: PASS -> SKIP == Known issues == Here are the changes found in Patchwork_10747_full that come from known issues: === IGT changes === ==== Issues hit ==== igt@gem_eio@reset-stress: shard-apl: PASS -> INCOMPLETE (fdo#103927) +1 igt@gem_exec_create@madvise: shard-apl: PASS -> DMESG-WARN (fdo#108673) igt@kms_busy@extended-modeset-hang-newfb-render-a: shard-skl: NOTRUN -> DMESG-WARN (fdo#107956) +1 igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-c: shard-apl: NOTRUN -> DMESG-WARN (fdo#107956) igt@kms_color@pipe-c-legacy-gamma: shard-apl: PASS -> FAIL (fdo#104782) igt@kms_cursor_crc@cursor-128x128-onscreen: shard-apl: PASS -> FAIL (fdo#103232) igt@kms_cursor_crc@cursor-128x128-random: shard-skl: PASS -> FAIL (fdo#103232) igt@kms_cursor_crc@cursor-64x64-dpms: shard-kbl: PASS -> DMESG-WARN (fdo#105602, fdo#103558) +2 igt@kms_cursor_legacy@2x-long-cursor-vs-flip-atomic: shard-hsw: PASS -> FAIL (fdo#105767) igt@kms_draw_crc@draw-method-xrgb2101010-blt-untiled: shard-skl: PASS -> FAIL (fdo#103184) +1 igt@kms_flip@flip-vs-expired-vblank: shard-skl: PASS -> FAIL (fdo#102887) igt@kms_flip@plain-flip-fb-recreate-interruptible: shard-skl: PASS -> FAIL (fdo#100368) igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-gtt: shard-apl: PASS -> FAIL (fdo#103167) +2 igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-fullscreen: shard-glk: PASS -> FAIL (fdo#103167) igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-indfb-msflip-blt: shard-skl: PASS -> FAIL (fdo#103167) +2 igt@kms_plane@plane-position-covered-pipe-b-planes: shard-apl: PASS -> FAIL (fdo#103166) igt@kms_plane_alpha_blend@pipe-a-coverage-7efc: shard-skl: PASS -> FAIL (fdo#108145, fdo#107815) igt@kms_plane_alpha_blend@pipe-b-alpha-transparant-fb: shard-skl: NOTRUN -> FAIL (fdo#108145) +1 igt@kms_properties@connector-properties-atomic: shard-skl: NOTRUN -> FAIL (fdo#108642) igt@kms_setmode@basic: shard-kbl: PASS -> FAIL (fdo#99912) igt@pm_rpm@modeset-non-lpsp: shard-skl: NOTRUN -> INCOMPLETE (fdo#107807) igt@pm_rpm@pc8-residency: shard-skl: SKIP -> INCOMPLETE (fdo#107807) igt@prime_busy@after-vebox: shard-snb: SKIP -> INCOMPLETE (fdo#105411) ==== Possible fixes ==== igt@gem_ctx_isolation@vecs0-s3: shard-skl: INCOMPLETE (fdo#107773, fdo#104108) -> PASS igt@gem_userptr_blits@stress-mm-invalidate-close-overlap: shard-apl: DMESG-WARN -> PASS igt@kms_available_modes_crc@available_mode_test_crc: shard-apl: FAIL (fdo#106641) -> PASS igt@kms_color@pipe-a-ctm-max: shard-apl: FAIL (fdo#108147) -> PASS igt@kms_cursor_crc@cursor-256x256-random: shard-apl: FAIL (fdo#103232) -> PASS +4 igt@kms_flip@flip-vs-expired-vblank-interruptible: shard-skl: FAIL (fdo#105363) -> PASS igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-pwrite: shard-apl: FAIL (fdo#103167) -> PASS +3 igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-pwrite: shard-glk: FAIL (fdo#103167) -> PASS igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b: shard-apl: INCOMPLETE (fdo#103927) -> PASS +1 igt@kms_plane_alpha_blend@pipe-b-coverage-7efc: shard-skl: FAIL (fdo#107815) -> PASS igt@kms_plane_multiple@atomic-pipe-a-tiling-y: shard-apl: FAIL (fdo#103166) -> PASS igt@kms_plane_multiple@atomic-pipe-a-tiling-yf: shard-glk: FAIL (fdo#103166) -> PASS igt@kms_vblank@pipe-a-accuracy-idle: shard-skl: FAIL (fdo#102583) -> PASS igt@pm_rpm@dpms-lpsp: shard-skl: INCOMPLETE (fdo#107807) -> PASS fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368 fdo#102583 https://bugs.freedesktop.org/show_bug.cgi?id=102583 fdo#102887 https://bugs.freedesktop.org/show_bug.cgi?id=102887 fdo#103166 https://bugs.freedesktop.org/show_bug.cgi?id=103166 fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167 fdo#103184 https://bugs.freedesktop.org/show_bug.cgi?id=103184 fdo#103232 https://bugs.freedesktop.org/show_bug.cgi?id=103232 fdo#103558 https://bugs.freedesktop.org/show_bug.cgi?id=103558 fdo#103927 https://bugs.freedesktop.org/show_bug.cgi?id=103927 fdo#104108 https://bugs.freedesktop.org/show_bug.cgi?id=104108 fdo#104782 https://bugs.freedesktop.org/show_bug.cgi?id=104782 fdo#105363 https://bugs.freedesktop.org/show_bug.cgi?id=105363 fdo#105411 https://bugs.freedesktop.org/show_bug.cgi?id=105411 fdo#105602 https://bugs.freedesktop.org/show_bug.cgi?id=105602 fdo#105767 https://bugs.freedesktop.org/show_bug.cgi?id=105767 fdo#106641 https://bugs.freedesktop.org/show_bug.cgi?id=106641 fdo#107773 https://bugs.freedesktop.org/show_bug.cgi?id=107773 fdo#107807 https://bugs.freedesktop.org/show_bug.cgi?id=107807 fdo#107815 https://bugs.freedesktop.org/show_bug.cgi?id=107815 fdo#107956 https://bugs.freedesktop.org/show_bug.cgi?id=107956 fdo#108145 https://bugs.freedesktop.org/show_bug.cgi?id=108145 fdo#108147 https://bugs.freedesktop.org/show_bug.cgi?id=108147 fdo#108642 https://bugs.freedesktop.org/show_bug.cgi?id=108642 fdo#108673 https://bugs.freedesktop.org/show_bug.cgi?id=108673 fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912 == Participating hosts (6 -> 6) == No changes in participating hosts == Build changes == * Linux: CI_DRM_5097 -> Patchwork_10747 CI_DRM_5097: c20dfc4f015dfd41246beb7d72338aa50543a5ef @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4711: cc41f4c921e56c62c85ec5349c47022ae9b5f008 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_10747: 73c65e0e7e5f8582a24bd4d3e11501dee33453ef @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10747/shards.html _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 38+ messages in thread
end of thread, other threads:[~2018-11-28 17:35 UTC | newest] Thread overview: 38+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2018-11-06 21:51 [PATCH v2 0/7] Make GEN macros more similar Lucas De Marchi 2018-11-06 21:51 ` [PATCH v2 1/7] Revert "drm/i915: Kill GEN_FOREVER" Lucas De Marchi 2018-11-21 22:22 ` Rodrigo Vivi 2018-11-06 21:51 ` [PATCH v2 2/7] drm/i915: Rename IS_GEN to GT_RANGE Lucas De Marchi 2018-11-28 8:02 ` Jani Nikula 2018-11-28 9:27 ` Joonas Lahtinen 2018-11-28 17:04 ` Rodrigo Vivi 2018-11-28 17:34 ` Lucas De Marchi 2018-11-06 21:51 ` [PATCH v2 3/7] drm/i915: replace IS_GEN<N> with GT_GEN(..., N) Lucas De Marchi 2018-11-21 22:20 ` Rodrigo Vivi 2018-11-23 12:42 ` Jani Nikula 2018-11-26 18:49 ` Rodrigo Vivi 2018-11-27 8:31 ` Jani Nikula 2018-11-28 0:09 ` Rodrigo Vivi 2018-11-06 21:51 ` [PATCH v2 4/7] drm/i915: rename IS_GEN9_* to GT_GEN9_* Lucas De Marchi 2018-11-21 22:22 ` Rodrigo Vivi 2018-11-06 21:51 ` [PATCH v2 5/7] drm/i915: replace gen checks using operators by GT_GEN/GT_GEN_RANGE Lucas De Marchi 2018-11-06 21:51 ` [PATCH v2 6/7] drm/i915: merge gen checks to use range Lucas De Marchi 2018-11-21 22:24 ` Rodrigo Vivi 2018-11-06 21:51 ` [PATCH v2 7/7] drm/i915: remove INTEL_GEN macro Lucas De Marchi 2018-11-07 10:05 ` [PATCH v2 0/7] Make GEN macros more similar Tvrtko Ursulin 2018-11-08 0:57 ` Lucas De Marchi 2018-11-08 11:23 ` Tvrtko Ursulin 2018-11-19 22:20 ` Lucas De Marchi 2018-11-20 13:40 ` Tvrtko Ursulin 2018-11-21 22:19 ` Rodrigo Vivi 2018-11-22 8:54 ` Tvrtko Ursulin 2018-11-26 18:46 ` Rodrigo Vivi 2018-11-27 8:37 ` Jani Nikula 2018-11-27 9:36 ` Lucas De Marchi 2018-11-27 11:35 ` Tvrtko Ursulin 2018-11-28 0:19 ` Rodrigo Vivi 2018-11-28 17:22 ` Lucas De Marchi 2018-11-23 12:44 ` Jani Nikula 2018-11-07 14:10 ` ✗ Fi.CI.CHECKPATCH: warning for Make GEN macros more similar (rev2) Patchwork 2018-11-07 14:14 ` ✗ Fi.CI.SPARSE: " Patchwork 2018-11-07 14:30 ` ✓ Fi.CI.BAT: success " Patchwork 2018-11-07 21:17 ` ✓ Fi.CI.IGT: " Patchwork
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