* [U-Boot] [PATCH 1/3] net: Drop CONFIG_TSI108_ETH
@ 2018-05-09 12:24 Tuomas Tynkkynen
2018-05-09 12:24 ` [U-Boot] [PATCH 2/3] i2c: Drop CONFIG_TSI108_I2C Tuomas Tynkkynen
` (2 more replies)
0 siblings, 3 replies; 8+ messages in thread
From: Tuomas Tynkkynen @ 2018-05-09 12:24 UTC (permalink / raw)
To: u-boot
Last user of this driver went away in June 2015 in commit
d928664f4101e24 ("powerpc: 74xx_7xx: remove 74xx_7xx cpu support")
Signed-off-by: Tuomas Tynkkynen <tuomas@tuxera.com>
---
drivers/net/Makefile | 1 -
drivers/net/tsi108_eth.c | 1015 ------------------------------------------
include/netdev.h | 1 -
scripts/config_whitelist.txt | 1 -
4 files changed, 1018 deletions(-)
delete mode 100644 drivers/net/tsi108_eth.c
diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index 851f82fb01..584bfdf2f9 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -58,7 +58,6 @@ obj-$(CONFIG_DRIVER_TI_EMAC) += davinci_emac.o
obj-$(CONFIG_TSEC_ENET) += tsec.o fsl_mdio.o
obj-$(CONFIG_DRIVER_TI_CPSW) += cpsw.o cpsw-common.o
obj-$(CONFIG_FMAN_ENET) += fsl_mdio.o
-obj-$(CONFIG_TSI108_ETH) += tsi108_eth.o
obj-$(CONFIG_ULI526X) += uli526x.o
obj-$(CONFIG_VSC7385_ENET) += vsc7385.o
obj-$(CONFIG_XILINX_AXIEMAC) += xilinx_axi_emac.o
diff --git a/drivers/net/tsi108_eth.c b/drivers/net/tsi108_eth.c
deleted file mode 100644
index 108cf61647..0000000000
--- a/drivers/net/tsi108_eth.c
+++ /dev/null
@@ -1,1015 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/***********************************************************************
- *
- * Copyright (c) 2005 Freescale Semiconductor, Inc.
- *
- * Description:
- * Ethernet interface for Tundra TSI108 bridge chip
- *
- ***********************************************************************/
-
-#include <config.h>
-
-#if !defined(CONFIG_TSI108_ETH_NUM_PORTS) || (CONFIG_TSI108_ETH_NUM_PORTS > 2)
-#error "CONFIG_TSI108_ETH_NUM_PORTS must be defined as 1 or 2"
-#endif
-
-#include <common.h>
-#include <malloc.h>
-#include <net.h>
-#include <netdev.h>
-#include <asm/cache.h>
-
-#ifdef DEBUG
-#define TSI108_ETH_DEBUG 7
-#else
-#define TSI108_ETH_DEBUG 0
-#endif
-
-#if TSI108_ETH_DEBUG > 0
-#define debug_lev(lev, fmt, args...) \
-if (lev <= TSI108_ETH_DEBUG) \
-printf ("%s %d: " fmt, __FUNCTION__, __LINE__, ##args)
-#else
-#define debug_lev(lev, fmt, args...) do{}while(0)
-#endif
-
-#define RX_PRINT_ERRORS
-#define TX_PRINT_ERRORS
-
-#define ETH_BASE (CONFIG_SYS_TSI108_CSR_BASE + 0x6000)
-
-#define ETH_PORT_OFFSET 0x400
-
-#define __REG32(base, offset) (*((volatile u32 *)((char *)(base) + (offset))))
-
-#define reg_MAC_CONFIG_1(base) __REG32(base, 0x00000000)
-#define MAC_CONFIG_1_TX_ENABLE (0x00000001)
-#define MAC_CONFIG_1_SYNC_TX_ENABLE (0x00000002)
-#define MAC_CONFIG_1_RX_ENABLE (0x00000004)
-#define MAC_CONFIG_1_SYNC_RX_ENABLE (0x00000008)
-#define MAC_CONFIG_1_TX_FLOW_CONTROL (0x00000010)
-#define MAC_CONFIG_1_RX_FLOW_CONTROL (0x00000020)
-#define MAC_CONFIG_1_LOOP_BACK (0x00000100)
-#define MAC_CONFIG_1_RESET_TX_FUNCTION (0x00010000)
-#define MAC_CONFIG_1_RESET_RX_FUNCTION (0x00020000)
-#define MAC_CONFIG_1_RESET_TX_MAC (0x00040000)
-#define MAC_CONFIG_1_RESET_RX_MAC (0x00080000)
-#define MAC_CONFIG_1_SIM_RESET (0x40000000)
-#define MAC_CONFIG_1_SOFT_RESET (0x80000000)
-
-#define reg_MAC_CONFIG_2(base) __REG32(base, 0x00000004)
-#define MAC_CONFIG_2_FULL_DUPLEX (0x00000001)
-#define MAC_CONFIG_2_CRC_ENABLE (0x00000002)
-#define MAC_CONFIG_2_PAD_CRC (0x00000004)
-#define MAC_CONFIG_2_LENGTH_CHECK (0x00000010)
-#define MAC_CONFIG_2_HUGE_FRAME (0x00000020)
-#define MAC_CONFIG_2_INTERFACE_MODE(val) (((val) & 0x3) << 8)
-#define MAC_CONFIG_2_PREAMBLE_LENGTH(val) (((val) & 0xf) << 12)
-#define INTERFACE_MODE_NIBBLE 1 /* 10/100 Mb/s MII) */
-#define INTERFACE_MODE_BYTE 2 /* 1000 Mb/s GMII/TBI */
-
-#define reg_MAXIMUM_FRAME_LENGTH(base) __REG32(base, 0x00000010)
-
-#define reg_MII_MGMT_CONFIG(base) __REG32(base, 0x00000020)
-#define MII_MGMT_CONFIG_MGMT_CLOCK_SELECT(val) ((val) & 0x7)
-#define MII_MGMT_CONFIG_NO_PREAMBLE (0x00000010)
-#define MII_MGMT_CONFIG_SCAN_INCREMENT (0x00000020)
-#define MII_MGMT_CONFIG_RESET_MGMT (0x80000000)
-
-#define reg_MII_MGMT_COMMAND(base) __REG32(base, 0x00000024)
-#define MII_MGMT_COMMAND_READ_CYCLE (0x00000001)
-#define MII_MGMT_COMMAND_SCAN_CYCLE (0x00000002)
-
-#define reg_MII_MGMT_ADDRESS(base) __REG32(base, 0x00000028)
-#define reg_MII_MGMT_CONTROL(base) __REG32(base, 0x0000002c)
-#define reg_MII_MGMT_STATUS(base) __REG32(base, 0x00000030)
-
-#define reg_MII_MGMT_INDICATORS(base) __REG32(base, 0x00000034)
-#define MII_MGMT_INDICATORS_BUSY (0x00000001)
-#define MII_MGMT_INDICATORS_SCAN (0x00000002)
-#define MII_MGMT_INDICATORS_NOT_VALID (0x00000004)
-
-#define reg_INTERFACE_STATUS(base) __REG32(base, 0x0000003c)
-#define INTERFACE_STATUS_LINK_FAIL (0x00000008)
-#define INTERFACE_STATUS_EXCESS_DEFER (0x00000200)
-
-#define reg_STATION_ADDRESS_1(base) __REG32(base, 0x00000040)
-#define reg_STATION_ADDRESS_2(base) __REG32(base, 0x00000044)
-
-#define reg_PORT_CONTROL(base) __REG32(base, 0x00000200)
-#define PORT_CONTROL_PRI (0x00000001)
-#define PORT_CONTROL_BPT (0x00010000)
-#define PORT_CONTROL_SPD (0x00040000)
-#define PORT_CONTROL_RBC (0x00080000)
-#define PORT_CONTROL_PRB (0x00200000)
-#define PORT_CONTROL_DIS (0x00400000)
-#define PORT_CONTROL_TBI (0x00800000)
-#define PORT_CONTROL_STE (0x10000000)
-#define PORT_CONTROL_ZOR (0x20000000)
-#define PORT_CONTROL_CLR (0x40000000)
-#define PORT_CONTROL_SRT (0x80000000)
-
-#define reg_TX_CONFIG(base) __REG32(base, 0x00000220)
-#define TX_CONFIG_START_Q (0x00000003)
-#define TX_CONFIG_EHP (0x00400000)
-#define TX_CONFIG_CHP (0x00800000)
-#define TX_CONFIG_RST (0x80000000)
-
-#define reg_TX_CONTROL(base) __REG32(base, 0x00000224)
-#define TX_CONTROL_GO (0x00008000)
-#define TX_CONTROL_MP (0x01000000)
-#define TX_CONTROL_EAI (0x20000000)
-#define TX_CONTROL_ABT (0x40000000)
-#define TX_CONTROL_EII (0x80000000)
-
-#define reg_TX_STATUS(base) __REG32(base, 0x00000228)
-#define TX_STATUS_QUEUE_USABLE (0x0000000f)
-#define TX_STATUS_CURR_Q (0x00000300)
-#define TX_STATUS_ACT (0x00008000)
-#define TX_STATUS_QUEUE_IDLE (0x000f0000)
-#define TX_STATUS_EOQ_PENDING (0x0f000000)
-
-#define reg_TX_EXTENDED_STATUS(base) __REG32(base, 0x0000022c)
-#define TX_EXTENDED_STATUS_END_OF_QUEUE_CONDITION (0x0000000f)
-#define TX_EXTENDED_STATUS_END_OF_FRAME_CONDITION (0x00000f00)
-#define TX_EXTENDED_STATUS_DESCRIPTOR_INTERRUPT_CONDITION (0x000f0000)
-#define TX_EXTENDED_STATUS_ERROR_FLAG (0x0f000000)
-
-#define reg_TX_THRESHOLDS(base) __REG32(base, 0x00000230)
-
-#define reg_TX_DIAGNOSTIC_ADDR(base) __REG32(base, 0x00000270)
-#define TX_DIAGNOSTIC_ADDR_INDEX (0x0000007f)
-#define TX_DIAGNOSTIC_ADDR_DFR (0x40000000)
-#define TX_DIAGNOSTIC_ADDR_AI (0x80000000)
-
-#define reg_TX_DIAGNOSTIC_DATA(base) __REG32(base, 0x00000274)
-
-#define reg_TX_ERROR_STATUS(base) __REG32(base, 0x00000278)
-#define TX_ERROR_STATUS (0x00000278)
-#define TX_ERROR_STATUS_QUEUE_0_ERROR_RESPONSE (0x0000000f)
-#define TX_ERROR_STATUS_TEA_ON_QUEUE_0 (0x00000010)
-#define TX_ERROR_STATUS_RER_ON_QUEUE_0 (0x00000020)
-#define TX_ERROR_STATUS_TER_ON_QUEUE_0 (0x00000040)
-#define TX_ERROR_STATUS_DER_ON_QUEUE_0 (0x00000080)
-#define TX_ERROR_STATUS_QUEUE_1_ERROR_RESPONSE (0x00000f00)
-#define TX_ERROR_STATUS_TEA_ON_QUEUE_1 (0x00001000)
-#define TX_ERROR_STATUS_RER_ON_QUEUE_1 (0x00002000)
-#define TX_ERROR_STATUS_TER_ON_QUEUE_1 (0x00004000)
-#define TX_ERROR_STATUS_DER_ON_QUEUE_1 (0x00008000)
-#define TX_ERROR_STATUS_QUEUE_2_ERROR_RESPONSE (0x000f0000)
-#define TX_ERROR_STATUS_TEA_ON_QUEUE_2 (0x00100000)
-#define TX_ERROR_STATUS_RER_ON_QUEUE_2 (0x00200000)
-#define TX_ERROR_STATUS_TER_ON_QUEUE_2 (0x00400000)
-#define TX_ERROR_STATUS_DER_ON_QUEUE_2 (0x00800000)
-#define TX_ERROR_STATUS_QUEUE_3_ERROR_RESPONSE (0x0f000000)
-#define TX_ERROR_STATUS_TEA_ON_QUEUE_3 (0x10000000)
-#define TX_ERROR_STATUS_RER_ON_QUEUE_3 (0x20000000)
-#define TX_ERROR_STATUS_TER_ON_QUEUE_3 (0x40000000)
-#define TX_ERROR_STATUS_DER_ON_QUEUE_3 (0x80000000)
-
-#define reg_TX_QUEUE_0_CONFIG(base) __REG32(base, 0x00000280)
-#define TX_QUEUE_0_CONFIG_OCN_PORT (0x0000003f)
-#define TX_QUEUE_0_CONFIG_BSWP (0x00000400)
-#define TX_QUEUE_0_CONFIG_WSWP (0x00000800)
-#define TX_QUEUE_0_CONFIG_AM (0x00004000)
-#define TX_QUEUE_0_CONFIG_GVI (0x00008000)
-#define TX_QUEUE_0_CONFIG_EEI (0x00010000)
-#define TX_QUEUE_0_CONFIG_ELI (0x00020000)
-#define TX_QUEUE_0_CONFIG_ENI (0x00040000)
-#define TX_QUEUE_0_CONFIG_ESI (0x00080000)
-#define TX_QUEUE_0_CONFIG_EDI (0x00100000)
-
-#define reg_TX_QUEUE_0_BUF_CONFIG(base) __REG32(base, 0x00000284)
-#define TX_QUEUE_0_BUF_CONFIG_OCN_PORT (0x0000003f)
-#define TX_QUEUE_0_BUF_CONFIG_BURST (0x00000300)
-#define TX_QUEUE_0_BUF_CONFIG_BSWP (0x00000400)
-#define TX_QUEUE_0_BUF_CONFIG_WSWP (0x00000800)
-
-#define OCN_PORT_HLP 0 /* HLP Interface */
-#define OCN_PORT_PCI_X 1 /* PCI-X Interface */
-#define OCN_PORT_PROCESSOR_MASTER 2 /* Processor Interface (master) */
-#define OCN_PORT_PROCESSOR_SLAVE 3 /* Processor Interface (slave) */
-#define OCN_PORT_MEMORY 4 /* Memory Controller */
-#define OCN_PORT_DMA 5 /* DMA Controller */
-#define OCN_PORT_ETHERNET 6 /* Ethernet Controller */
-#define OCN_PORT_PRINT 7 /* Print Engine Interface */
-
-#define reg_TX_QUEUE_0_PTR_LOW(base) __REG32(base, 0x00000288)
-
-#define reg_TX_QUEUE_0_PTR_HIGH(base) __REG32(base, 0x0000028c)
-#define TX_QUEUE_0_PTR_HIGH_VALID (0x80000000)
-
-#define reg_RX_CONFIG(base) __REG32(base, 0x00000320)
-#define RX_CONFIG_DEF_Q (0x00000003)
-#define RX_CONFIG_EMF (0x00000100)
-#define RX_CONFIG_EUF (0x00000200)
-#define RX_CONFIG_BFE (0x00000400)
-#define RX_CONFIG_MFE (0x00000800)
-#define RX_CONFIG_UFE (0x00001000)
-#define RX_CONFIG_SE (0x00002000)
-#define RX_CONFIG_ABF (0x00200000)
-#define RX_CONFIG_APE (0x00400000)
-#define RX_CONFIG_CHP (0x00800000)
-#define RX_CONFIG_RST (0x80000000)
-
-#define reg_RX_CONTROL(base) __REG32(base, 0x00000324)
-#define GE_E0_RX_CONTROL_QUEUE_ENABLES (0x0000000f)
-#define GE_E0_RX_CONTROL_GO (0x00008000)
-#define GE_E0_RX_CONTROL_EAI (0x20000000)
-#define GE_E0_RX_CONTROL_ABT (0x40000000)
-#define GE_E0_RX_CONTROL_EII (0x80000000)
-
-#define reg_RX_EXTENDED_STATUS(base) __REG32(base, 0x0000032c)
-#define RX_EXTENDED_STATUS (0x0000032c)
-#define RX_EXTENDED_STATUS_EOQ (0x0000000f)
-#define RX_EXTENDED_STATUS_EOQ_0 (0x00000001)
-#define RX_EXTENDED_STATUS_EOF (0x00000f00)
-#define RX_EXTENDED_STATUS_DESCRIPTOR_INTERRUPT_CONDITION (0x000f0000)
-#define RX_EXTENDED_STATUS_ERROR_FLAG (0x0f000000)
-
-#define reg_RX_THRESHOLDS(base) __REG32(base, 0x00000330)
-
-#define reg_RX_DIAGNOSTIC_ADDR(base) __REG32(base, 0x00000370)
-#define RX_DIAGNOSTIC_ADDR_INDEX (0x0000007f)
-#define RX_DIAGNOSTIC_ADDR_DFR (0x40000000)
-#define RX_DIAGNOSTIC_ADDR_AI (0x80000000)
-
-#define reg_RX_DIAGNOSTIC_DATA(base) __REG32(base, 0x00000374)
-
-#define reg_RX_QUEUE_0_CONFIG(base) __REG32(base, 0x00000380)
-#define RX_QUEUE_0_CONFIG_OCN_PORT (0x0000003f)
-#define RX_QUEUE_0_CONFIG_BSWP (0x00000400)
-#define RX_QUEUE_0_CONFIG_WSWP (0x00000800)
-#define RX_QUEUE_0_CONFIG_AM (0x00004000)
-#define RX_QUEUE_0_CONFIG_EEI (0x00010000)
-#define RX_QUEUE_0_CONFIG_ELI (0x00020000)
-#define RX_QUEUE_0_CONFIG_ENI (0x00040000)
-#define RX_QUEUE_0_CONFIG_ESI (0x00080000)
-#define RX_QUEUE_0_CONFIG_EDI (0x00100000)
-
-#define reg_RX_QUEUE_0_BUF_CONFIG(base) __REG32(base, 0x00000384)
-#define RX_QUEUE_0_BUF_CONFIG_OCN_PORT (0x0000003f)
-#define RX_QUEUE_0_BUF_CONFIG_BURST (0x00000300)
-#define RX_QUEUE_0_BUF_CONFIG_BSWP (0x00000400)
-#define RX_QUEUE_0_BUF_CONFIG_WSWP (0x00000800)
-
-#define reg_RX_QUEUE_0_PTR_LOW(base) __REG32(base, 0x00000388)
-
-#define reg_RX_QUEUE_0_PTR_HIGH(base) __REG32(base, 0x0000038c)
-#define RX_QUEUE_0_PTR_HIGH_VALID (0x80000000)
-
-/*
- * PHY register definitions
- */
-/* the first 15 PHY registers are standard. */
-#define PHY_CTRL_REG 0 /* Control Register */
-#define PHY_STATUS_REG 1 /* Status Regiser */
-#define PHY_ID1_REG 2 /* Phy Id Reg (word 1) */
-#define PHY_ID2_REG 3 /* Phy Id Reg (word 2) */
-#define PHY_AN_ADV_REG 4 /* Autoneg Advertisement */
-#define PHY_LP_ABILITY_REG 5 /* Link Partner Ability (Base Page) */
-#define PHY_AUTONEG_EXP_REG 6 /* Autoneg Expansion Reg */
-#define PHY_NEXT_PAGE_TX_REG 7 /* Next Page TX */
-#define PHY_LP_NEXT_PAGE_REG 8 /* Link Partner Next Page */
-#define PHY_1000T_CTRL_REG 9 /* 1000Base-T Control Reg */
-#define PHY_1000T_STATUS_REG 10 /* 1000Base-T Status Reg */
-#define PHY_EXT_STATUS_REG 11 /* Extended Status Reg */
-
-/*
- * PHY Register bit masks.
- */
-#define PHY_CTRL_RESET (1 << 15)
-#define PHY_CTRL_LOOPBACK (1 << 14)
-#define PHY_CTRL_SPEED0 (1 << 13)
-#define PHY_CTRL_AN_EN (1 << 12)
-#define PHY_CTRL_PWR_DN (1 << 11)
-#define PHY_CTRL_ISOLATE (1 << 10)
-#define PHY_CTRL_RESTART_AN (1 << 9)
-#define PHY_CTRL_FULL_DUPLEX (1 << 8)
-#define PHY_CTRL_CT_EN (1 << 7)
-#define PHY_CTRL_SPEED1 (1 << 6)
-
-#define PHY_STAT_100BASE_T4 (1 << 15)
-#define PHY_STAT_100BASE_X_FD (1 << 14)
-#define PHY_STAT_100BASE_X_HD (1 << 13)
-#define PHY_STAT_10BASE_T_FD (1 << 12)
-#define PHY_STAT_10BASE_T_HD (1 << 11)
-#define PHY_STAT_100BASE_T2_FD (1 << 10)
-#define PHY_STAT_100BASE_T2_HD (1 << 9)
-#define PHY_STAT_EXT_STAT (1 << 8)
-#define PHY_STAT_RESERVED (1 << 7)
-#define PHY_STAT_MFPS (1 << 6) /* Management Frames Preamble Suppression */
-#define PHY_STAT_AN_COMPLETE (1 << 5)
-#define PHY_STAT_REM_FAULT (1 << 4)
-#define PHY_STAT_AN_CAP (1 << 3)
-#define PHY_STAT_LINK_UP (1 << 2)
-#define PHY_STAT_JABBER (1 << 1)
-#define PHY_STAT_EXT_CAP (1 << 0)
-
-#define TBI_CONTROL_2 0x11
-#define TBI_CONTROL_2_ENABLE_COMMA_DETECT 0x0001
-#define TBI_CONTROL_2_ENABLE_WRAP 0x0002
-#define TBI_CONTROL_2_G_MII_MODE 0x0010
-#define TBI_CONTROL_2_RECEIVE_CLOCK_SELECT 0x0020
-#define TBI_CONTROL_2_AUTO_NEGOTIATION_SENSE 0x0100
-#define TBI_CONTROL_2_DISABLE_TRANSMIT_RUNNING_DISPARITY 0x1000
-#define TBI_CONTROL_2_DISABLE_RECEIVE_RUNNING_DISPARITY 0x2000
-#define TBI_CONTROL_2_SHORTCUT_LINK_TIMER 0x4000
-#define TBI_CONTROL_2_SOFT_RESET 0x8000
-
-/* marvel specific */
-#define MV1111_EXT_CTRL1_REG 16 /* PHY Specific Control Reg */
-#define MV1111_SPEC_STAT_REG 17 /* PHY Specific Status Reg */
-#define MV1111_EXT_CTRL2_REG 20 /* Extended PHY Specific Control Reg */
-
-/*
- * MARVELL 88E1111 PHY register bit masks
- */
-/* PHY Specific Status Register (MV1111_EXT_CTRL1_REG) */
-
-#define SPEC_STAT_SPEED_MASK (3 << 14)
-#define SPEC_STAT_FULL_DUP (1 << 13)
-#define SPEC_STAT_PAGE_RCVD (1 << 12)
-#define SPEC_STAT_RESOLVED (1 << 11) /* Speed and Duplex Resolved */
-#define SPEC_STAT_LINK_UP (1 << 10)
-#define SPEC_STAT_CABLE_LEN_MASK (7 << 7)/* Cable Length (100/1000 modes only) */
-#define SPEC_STAT_MDIX (1 << 6)
-#define SPEC_STAT_POLARITY (1 << 1)
-#define SPEC_STAT_JABBER (1 << 0)
-
-#define SPEED_1000 (2 << 14)
-#define SPEED_100 (1 << 14)
-#define SPEED_10 (0 << 14)
-
-#define TBI_ADDR 0x1E /* Ten Bit Interface address */
-
-/* negotiated link parameters */
-#define LINK_SPEED_UNKNOWN 0
-#define LINK_SPEED_10 1
-#define LINK_SPEED_100 2
-#define LINK_SPEED_1000 3
-
-#define LINK_DUPLEX_UNKNOWN 0
-#define LINK_DUPLEX_HALF 1
-#define LINK_DUPLEX_FULL 2
-
-static unsigned int phy_address[] = { 8, 9 };
-
-#define vuint32 volatile u32
-
-/* TX/RX buffer descriptors. MUST be cache line aligned in memory. (32 byte)
- * This structure is accessed by the ethernet DMA engine which means it
- * MUST be in LITTLE ENDIAN format */
-struct dma_descriptor {
- vuint32 start_addr0; /* buffer address, least significant bytes. */
- vuint32 start_addr1; /* buffer address, most significant bytes. */
- vuint32 next_descr_addr0;/* next descriptor address, least significant bytes. Must be 64-bit aligned. */
- vuint32 next_descr_addr1;/* next descriptor address, most significant bytes. */
- vuint32 vlan_byte_count;/* VLAN tag(top 2 bytes) and byte countt (bottom 2 bytes). */
- vuint32 config_status; /* Configuration/Status. */
- vuint32 reserved1; /* reserved to make the descriptor cache line aligned. */
- vuint32 reserved2; /* reserved to make the descriptor cache line aligned. */
-};
-
-/* last next descriptor address flag */
-#define DMA_DESCR_LAST (1 << 31)
-
-/* TX DMA descriptor config status bits */
-#define DMA_DESCR_TX_EOF (1 << 0) /* end of frame */
-#define DMA_DESCR_TX_SOF (1 << 1) /* start of frame */
-#define DMA_DESCR_TX_PFVLAN (1 << 2)
-#define DMA_DESCR_TX_HUGE (1 << 3)
-#define DMA_DESCR_TX_PAD (1 << 4)
-#define DMA_DESCR_TX_CRC (1 << 5)
-#define DMA_DESCR_TX_DESCR_INT (1 << 14)
-#define DMA_DESCR_TX_RETRY_COUNT 0x000F0000
-#define DMA_DESCR_TX_ONE_COLLISION (1 << 20)
-#define DMA_DESCR_TX_LATE_COLLISION (1 << 24)
-#define DMA_DESCR_TX_UNDERRUN (1 << 25)
-#define DMA_DESCR_TX_RETRY_LIMIT (1 << 26)
-#define DMA_DESCR_TX_OK (1 << 30)
-#define DMA_DESCR_TX_OWNER (1 << 31)
-
-/* RX DMA descriptor status bits */
-#define DMA_DESCR_RX_EOF (1 << 0)
-#define DMA_DESCR_RX_SOF (1 << 1)
-#define DMA_DESCR_RX_VTF (1 << 2)
-#define DMA_DESCR_RX_FRAME_IS_TYPE (1 << 3)
-#define DMA_DESCR_RX_SHORT_FRAME (1 << 4)
-#define DMA_DESCR_RX_HASH_MATCH (1 << 7)
-#define DMA_DESCR_RX_BAD_FRAME (1 << 8)
-#define DMA_DESCR_RX_OVERRUN (1 << 9)
-#define DMA_DESCR_RX_MAX_FRAME_LEN (1 << 11)
-#define DMA_DESCR_RX_CRC_ERROR (1 << 12)
-#define DMA_DESCR_RX_DESCR_INT (1 << 13)
-#define DMA_DESCR_RX_OWNER (1 << 15)
-
-#define RX_BUFFER_SIZE PKTSIZE
-#define NUM_RX_DESC PKTBUFSRX
-
-static struct dma_descriptor tx_descriptor __attribute__ ((aligned(32)));
-
-static struct dma_descriptor rx_descr_array[NUM_RX_DESC]
- __attribute__ ((aligned(32)));
-
-static struct dma_descriptor *rx_descr_current;
-
-static int tsi108_eth_probe (struct eth_device *dev, bd_t * bis);
-static int tsi108_eth_send(struct eth_device *dev, void *packet, int length);
-static int tsi108_eth_recv (struct eth_device *dev);
-static void tsi108_eth_halt (struct eth_device *dev);
-static unsigned int read_phy (unsigned int base,
- unsigned int phy_addr, unsigned int phy_reg);
-static void write_phy (unsigned int base,
- unsigned int phy_addr,
- unsigned int phy_reg, unsigned int phy_data);
-
-#if TSI108_ETH_DEBUG > 100
-/*
- * print phy debug infomation
- */
-static void dump_phy_regs (unsigned int phy_addr)
-{
- int i;
-
- printf ("PHY %d registers\n", phy_addr);
- for (i = 0; i <= 30; i++) {
- printf ("%2d 0x%04x\n", i, read_phy (ETH_BASE, phy_addr, i));
- }
- printf ("\n");
-
-}
-#else
-#define dump_phy_regs(base) do{}while(0)
-#endif
-
-#if TSI108_ETH_DEBUG > 100
-/*
- * print debug infomation
- */
-static void tx_diag_regs (unsigned int base)
-{
- int i;
- unsigned long dummy;
-
- printf ("TX diagnostics registers\n");
- reg_TX_DIAGNOSTIC_ADDR(base) = 0x00 | TX_DIAGNOSTIC_ADDR_AI;
- udelay (1000);
- dummy = reg_TX_DIAGNOSTIC_DATA(base);
- for (i = 0x00; i <= 0x05; i++) {
- udelay (1000);
- printf ("0x%02x 0x%08x\n", i, reg_TX_DIAGNOSTIC_DATA(base));
- }
- reg_TX_DIAGNOSTIC_ADDR(base) = 0x40 | TX_DIAGNOSTIC_ADDR_AI;
- udelay (1000);
- dummy = reg_TX_DIAGNOSTIC_DATA(base);
- for (i = 0x40; i <= 0x47; i++) {
- udelay (1000);
- printf ("0x%02x 0x%08x\n", i, reg_TX_DIAGNOSTIC_DATA(base));
- }
- printf ("\n");
-
-}
-#else
-#define tx_diag_regs(base) do{}while(0)
-#endif
-
-#if TSI108_ETH_DEBUG > 100
-/*
- * print debug infomation
- */
-static void rx_diag_regs (unsigned int base)
-{
- int i;
- unsigned long dummy;
-
- printf ("RX diagnostics registers\n");
- reg_RX_DIAGNOSTIC_ADDR(base) = 0x00 | RX_DIAGNOSTIC_ADDR_AI;
- udelay (1000);
- dummy = reg_RX_DIAGNOSTIC_DATA(base);
- for (i = 0x00; i <= 0x05; i++) {
- udelay (1000);
- printf ("0x%02x 0x%08x\n", i, reg_RX_DIAGNOSTIC_DATA(base));
- }
- reg_RX_DIAGNOSTIC_ADDR(base) = 0x40 | RX_DIAGNOSTIC_ADDR_AI;
- udelay (1000);
- dummy = reg_RX_DIAGNOSTIC_DATA(base);
- for (i = 0x08; i <= 0x0a; i++) {
- udelay (1000);
- printf ("0x%02x 0x%08x\n", i, reg_RX_DIAGNOSTIC_DATA(base));
- }
- printf ("\n");
-
-}
-#else
-#define rx_diag_regs(base) do{}while(0)
-#endif
-
-#if TSI108_ETH_DEBUG > 100
-/*
- * print debug infomation
- */
-static void debug_mii_regs (unsigned int base)
-{
- printf ("MII_MGMT_CONFIG 0x%08x\n", reg_MII_MGMT_CONFIG(base));
- printf ("MII_MGMT_COMMAND 0x%08x\n", reg_MII_MGMT_COMMAND(base));
- printf ("MII_MGMT_ADDRESS 0x%08x\n", reg_MII_MGMT_ADDRESS(base));
- printf ("MII_MGMT_CONTROL 0x%08x\n", reg_MII_MGMT_CONTROL(base));
- printf ("MII_MGMT_STATUS 0x%08x\n", reg_MII_MGMT_STATUS(base));
- printf ("MII_MGMT_INDICATORS 0x%08x\n", reg_MII_MGMT_INDICATORS(base));
- printf ("\n");
-
-}
-#else
-#define debug_mii_regs(base) do{}while(0)
-#endif
-
-/*
- * Wait until the phy bus is non-busy
- */
-static void phy_wait (unsigned int base, unsigned int condition)
-{
- int timeout;
-
- timeout = 0;
- while (reg_MII_MGMT_INDICATORS(base) & condition) {
- udelay (10);
- if (++timeout > 10000) {
- printf ("ERROR: timeout waiting for phy bus (%d)\n",
- condition);
- break;
- }
- }
-}
-
-/*
- * read phy register
- */
-static unsigned int read_phy (unsigned int base,
- unsigned int phy_addr, unsigned int phy_reg)
-{
- unsigned int value;
-
- phy_wait (base, MII_MGMT_INDICATORS_BUSY);
-
- reg_MII_MGMT_ADDRESS(base) = (phy_addr << 8) | phy_reg;
-
- /* Ensure that the Read Cycle bit is cleared prior to next read cycle */
- reg_MII_MGMT_COMMAND(base) = 0;
-
- /* start the read */
- reg_MII_MGMT_COMMAND(base) = MII_MGMT_COMMAND_READ_CYCLE;
-
- /* wait for the read to complete */
- phy_wait (base,
- MII_MGMT_INDICATORS_NOT_VALID | MII_MGMT_INDICATORS_BUSY);
-
- value = reg_MII_MGMT_STATUS(base);
-
- reg_MII_MGMT_COMMAND(base) = 0;
-
- return value;
-}
-
-/*
- * write phy register
- */
-static void write_phy (unsigned int base,
- unsigned int phy_addr,
- unsigned int phy_reg, unsigned int phy_data)
-{
- phy_wait (base, MII_MGMT_INDICATORS_BUSY);
-
- reg_MII_MGMT_ADDRESS(base) = (phy_addr << 8) | phy_reg;
-
- /* Ensure that the Read Cycle bit is cleared prior to next cycle */
- reg_MII_MGMT_COMMAND(base) = 0;
-
- /* start the write */
- reg_MII_MGMT_CONTROL(base) = phy_data;
-}
-
-/*
- * configure the marvell 88e1111 phy
- */
-static int marvell_88e_phy_config (struct eth_device *dev, int *speed,
- int *duplex)
-{
- unsigned long base;
- unsigned long phy_addr;
- unsigned int phy_status;
- unsigned int phy_spec_status;
- int timeout;
- int phy_speed;
- int phy_duplex;
- unsigned int value;
-
- phy_speed = LINK_SPEED_UNKNOWN;
- phy_duplex = LINK_DUPLEX_UNKNOWN;
-
- base = dev->iobase;
- phy_addr = (unsigned long)dev->priv;
-
- /* Take the PHY out of reset. */
- write_phy (ETH_BASE, phy_addr, PHY_CTRL_REG, PHY_CTRL_RESET);
-
- /* Wait for the reset process to complete. */
- udelay (10);
- timeout = 0;
- while ((phy_status =
- read_phy (ETH_BASE, phy_addr, PHY_CTRL_REG)) & PHY_CTRL_RESET) {
- udelay (10);
- if (++timeout > 10000) {
- printf ("ERROR: timeout waiting for phy reset\n");
- break;
- }
- }
-
- /* TBI Configuration. */
- write_phy (base, TBI_ADDR, TBI_CONTROL_2, TBI_CONTROL_2_G_MII_MODE |
- TBI_CONTROL_2_RECEIVE_CLOCK_SELECT);
- /* Wait for the link to be established. */
- timeout = 0;
- do {
- udelay (20000);
- phy_status = read_phy (ETH_BASE, phy_addr, PHY_STATUS_REG);
- if (++timeout > 100) {
- debug_lev(1, "ERROR: unable to establish link!!!\n");
- break;
- }
- } while ((phy_status & PHY_STAT_LINK_UP) == 0);
-
- if ((phy_status & PHY_STAT_LINK_UP) == 0)
- return 0;
-
- value = 0;
- phy_spec_status = read_phy (ETH_BASE, phy_addr, MV1111_SPEC_STAT_REG);
- if (phy_spec_status & SPEC_STAT_RESOLVED) {
- switch (phy_spec_status & SPEC_STAT_SPEED_MASK) {
- case SPEED_1000:
- phy_speed = LINK_SPEED_1000;
- value |= PHY_CTRL_SPEED1;
- break;
- case SPEED_100:
- phy_speed = LINK_SPEED_100;
- value |= PHY_CTRL_SPEED0;
- break;
- case SPEED_10:
- phy_speed = LINK_SPEED_10;
- break;
- }
- if (phy_spec_status & SPEC_STAT_FULL_DUP) {
- phy_duplex = LINK_DUPLEX_FULL;
- value |= PHY_CTRL_FULL_DUPLEX;
- } else
- phy_duplex = LINK_DUPLEX_HALF;
- }
- /* set TBI speed */
- write_phy (base, TBI_ADDR, PHY_CTRL_REG, value);
- write_phy (base, TBI_ADDR, PHY_AN_ADV_REG, 0x0060);
-
-#if TSI108_ETH_DEBUG > 0
- printf ("%s link is up", dev->name);
- phy_spec_status = read_phy (ETH_BASE, phy_addr, MV1111_SPEC_STAT_REG);
- if (phy_spec_status & SPEC_STAT_RESOLVED) {
- switch (phy_speed) {
- case LINK_SPEED_1000:
- printf (", 1000 Mbps");
- break;
- case LINK_SPEED_100:
- printf (", 100 Mbps");
- break;
- case LINK_SPEED_10:
- printf (", 10 Mbps");
- break;
- }
- if (phy_duplex == LINK_DUPLEX_FULL)
- printf (", Full duplex");
- else
- printf (", Half duplex");
- }
- printf ("\n");
-#endif
-
- dump_phy_regs (TBI_ADDR);
- if (speed)
- *speed = phy_speed;
- if (duplex)
- *duplex = phy_duplex;
-
- return 1;
-}
-
-/*
- * External interface
- *
- * register the tsi108 ethernet controllers with the multi-ethernet system
- */
-int tsi108_eth_initialize (bd_t * bis)
-{
- struct eth_device *dev;
- int index;
-
- for (index = 0; index < CONFIG_TSI108_ETH_NUM_PORTS; index++) {
- dev = (struct eth_device *)malloc(sizeof(struct eth_device));
- if (!dev) {
- printf("tsi108: Can not allocate memory\n");
- break;
- }
- memset(dev, 0, sizeof(*dev));
- sprintf (dev->name, "TSI108_eth%d", index);
-
- dev->iobase = ETH_BASE + (index * ETH_PORT_OFFSET);
- dev->priv = (void *)(phy_address[index]);
- dev->init = tsi108_eth_probe;
- dev->halt = tsi108_eth_halt;
- dev->send = tsi108_eth_send;
- dev->recv = tsi108_eth_recv;
-
- eth_register(dev);
- }
- return index;
-}
-
-/*
- * probe for and initialize a single ethernet interface
- */
-static int tsi108_eth_probe (struct eth_device *dev, bd_t * bis)
-{
- unsigned long base;
- unsigned long value;
- int index;
- struct dma_descriptor *tx_descr;
- struct dma_descriptor *rx_descr;
- int speed;
- int duplex;
-
- base = dev->iobase;
-
- reg_PORT_CONTROL(base) = PORT_CONTROL_STE | PORT_CONTROL_BPT;
-
- /* Bring DMA/FIFO out of reset. */
- reg_TX_CONFIG(base) = 0x00000000;
- reg_RX_CONFIG(base) = 0x00000000;
-
- reg_TX_THRESHOLDS(base) = (192 << 16) | 192;
- reg_RX_THRESHOLDS(base) = (192 << 16) | 112;
-
- /* Bring MAC out of reset. */
- reg_MAC_CONFIG_1(base) = 0x00000000;
-
- /* DMA MAC configuration. */
- reg_MAC_CONFIG_1(base) =
- MAC_CONFIG_1_RX_ENABLE | MAC_CONFIG_1_TX_ENABLE;
-
- reg_MII_MGMT_CONFIG(base) = MII_MGMT_CONFIG_NO_PREAMBLE;
- reg_MAXIMUM_FRAME_LENGTH(base) = RX_BUFFER_SIZE;
-
- /* Note: Early tsi108 manual did not have correct byte order
- * for the station address.*/
- reg_STATION_ADDRESS_1(base) = (dev->enetaddr[5] << 24) |
- (dev->enetaddr[4] << 16) |
- (dev->enetaddr[3] << 8) | (dev->enetaddr[2] << 0);
-
- reg_STATION_ADDRESS_2(base) = (dev->enetaddr[1] << 24) |
- (dev->enetaddr[0] << 16);
-
- if (marvell_88e_phy_config(dev, &speed, &duplex) == 0)
- return -1;
-
- value =
- MAC_CONFIG_2_PREAMBLE_LENGTH(7) | MAC_CONFIG_2_PAD_CRC |
- MAC_CONFIG_2_CRC_ENABLE;
- if (speed == LINK_SPEED_1000)
- value |= MAC_CONFIG_2_INTERFACE_MODE(INTERFACE_MODE_BYTE);
- else {
- value |= MAC_CONFIG_2_INTERFACE_MODE(INTERFACE_MODE_NIBBLE);
- reg_PORT_CONTROL(base) |= PORT_CONTROL_SPD;
- }
- if (duplex == LINK_DUPLEX_FULL) {
- value |= MAC_CONFIG_2_FULL_DUPLEX;
- reg_PORT_CONTROL(base) &= ~PORT_CONTROL_BPT;
- } else
- reg_PORT_CONTROL(base) |= PORT_CONTROL_BPT;
- reg_MAC_CONFIG_2(base) = value;
-
- reg_RX_CONFIG(base) = RX_CONFIG_SE;
- reg_RX_QUEUE_0_CONFIG(base) = OCN_PORT_MEMORY;
- reg_RX_QUEUE_0_BUF_CONFIG(base) = OCN_PORT_MEMORY;
-
- /* initialize the RX DMA descriptors */
- rx_descr = &rx_descr_array[0];
- rx_descr_current = rx_descr;
- for (index = 0; index < NUM_RX_DESC; index++) {
- /* make sure the receive buffers are not in cache */
- invalidate_dcache_range((unsigned long)net_rx_packets[index],
- (unsigned long)net_rx_packets[index] +
- RX_BUFFER_SIZE);
- rx_descr->start_addr0 =
- cpu_to_le32((vuint32) net_rx_packets[index]);
- rx_descr->start_addr1 = 0;
- rx_descr->next_descr_addr0 =
- cpu_to_le32((vuint32) (rx_descr + 1));
- rx_descr->next_descr_addr1 = 0;
- rx_descr->vlan_byte_count = 0;
- rx_descr->config_status = cpu_to_le32((RX_BUFFER_SIZE << 16) |
- DMA_DESCR_RX_OWNER);
- rx_descr++;
- }
- rx_descr--;
- rx_descr->next_descr_addr0 = 0;
- rx_descr->next_descr_addr1 = cpu_to_le32(DMA_DESCR_LAST);
- /* Push the descriptors to RAM so the ethernet DMA can see them */
- invalidate_dcache_range((unsigned long)rx_descr_array,
- (unsigned long)rx_descr_array +
- sizeof(rx_descr_array));
-
- /* enable RX queue */
- reg_RX_CONTROL(base) = TX_CONTROL_GO | 0x01;
- reg_RX_QUEUE_0_PTR_LOW(base) = (u32) rx_descr_current;
- /* enable receive DMA */
- reg_RX_QUEUE_0_PTR_HIGH(base) = RX_QUEUE_0_PTR_HIGH_VALID;
-
- reg_TX_QUEUE_0_CONFIG(base) = OCN_PORT_MEMORY;
- reg_TX_QUEUE_0_BUF_CONFIG(base) = OCN_PORT_MEMORY;
-
- /* initialize the TX DMA descriptor */
- tx_descr = &tx_descriptor;
-
- tx_descr->start_addr0 = 0;
- tx_descr->start_addr1 = 0;
- tx_descr->next_descr_addr0 = 0;
- tx_descr->next_descr_addr1 = cpu_to_le32(DMA_DESCR_LAST);
- tx_descr->vlan_byte_count = 0;
- tx_descr->config_status = cpu_to_le32(DMA_DESCR_TX_OK |
- DMA_DESCR_TX_SOF |
- DMA_DESCR_TX_EOF);
- /* enable TX queue */
- reg_TX_CONTROL(base) = TX_CONTROL_GO | 0x01;
-
- return 0;
-}
-
-/*
- * send a packet
- */
-static int tsi108_eth_send(struct eth_device *dev, void *packet, int length)
-{
- unsigned long base;
- int timeout;
- struct dma_descriptor *tx_descr;
- unsigned long status;
-
- base = dev->iobase;
- tx_descr = &tx_descriptor;
-
- /* Wait until the last packet has been transmitted. */
- timeout = 0;
- do {
- /* make sure we see the changes made by the DMA engine */
- invalidate_dcache_range((unsigned long)tx_descr,
- (unsigned long)tx_descr +
- sizeof(struct dma_descriptor));
-
- if (timeout != 0)
- udelay (15);
- if (++timeout > 10000) {
- tx_diag_regs(base);
- debug_lev(1,
- "ERROR: timeout waiting for last transmit packet to be sent\n");
- return 0;
- }
- } while (tx_descr->config_status & cpu_to_le32(DMA_DESCR_TX_OWNER));
-
- status = le32_to_cpu(tx_descr->config_status);
- if ((status & DMA_DESCR_TX_OK) == 0) {
-#ifdef TX_PRINT_ERRORS
- printf ("TX packet error: 0x%08lx\n %s%s%s%s\n", status,
- status & DMA_DESCR_TX_OK ? "tx error, " : "",
- status & DMA_DESCR_TX_RETRY_LIMIT ?
- "retry limit reached, " : "",
- status & DMA_DESCR_TX_UNDERRUN ? "underrun, " : "",
- status & DMA_DESCR_TX_LATE_COLLISION ? "late collision, "
- : "");
-#endif
- }
-
- debug_lev (9, "sending packet %d\n", length);
- tx_descr->start_addr0 = cpu_to_le32((vuint32) packet);
- tx_descr->start_addr1 = 0;
- tx_descr->next_descr_addr0 = 0;
- tx_descr->next_descr_addr1 = cpu_to_le32(DMA_DESCR_LAST);
- tx_descr->vlan_byte_count = cpu_to_le32(length);
- tx_descr->config_status = cpu_to_le32(DMA_DESCR_TX_OWNER |
- DMA_DESCR_TX_CRC |
- DMA_DESCR_TX_PAD |
- DMA_DESCR_TX_SOF |
- DMA_DESCR_TX_EOF);
-
- invalidate_dcache_range((unsigned long)tx_descr,
- (unsigned long)tx_descr +
- sizeof(struct dma_descriptor));
-
- invalidate_dcache_range((unsigned long)packet,
- (unsigned long)packet + length);
-
- reg_TX_QUEUE_0_PTR_LOW(base) = (u32) tx_descr;
- reg_TX_QUEUE_0_PTR_HIGH(base) = TX_QUEUE_0_PTR_HIGH_VALID;
-
- return length;
-}
-
-/*
- * Check for received packets and send them up the protocal stack
- */
-static int tsi108_eth_recv (struct eth_device *dev)
-{
- struct dma_descriptor *rx_descr;
- unsigned long base;
- int length = 0;
- unsigned long status;
- uchar *buffer;
-
- base = dev->iobase;
-
- /* make sure we see the changes made by the DMA engine */
- invalidate_dcache_range ((unsigned long)rx_descr_array,
- (unsigned long)rx_descr_array +
- sizeof(rx_descr_array));
-
- /* process all of the received packets */
- rx_descr = rx_descr_current;
- while ((rx_descr->config_status & cpu_to_le32(DMA_DESCR_RX_OWNER)) == 0) {
- /* check for error */
- status = le32_to_cpu(rx_descr->config_status);
- if (status & DMA_DESCR_RX_BAD_FRAME) {
-#ifdef RX_PRINT_ERRORS
- printf ("RX packet error: 0x%08lx\n %s%s%s%s%s%s\n",
- status,
- status & DMA_DESCR_RX_FRAME_IS_TYPE ? "too big, "
- : "",
- status & DMA_DESCR_RX_SHORT_FRAME ? "too short, "
- : "",
- status & DMA_DESCR_RX_BAD_FRAME ? "bad frame, " :
- "",
- status & DMA_DESCR_RX_OVERRUN ? "overrun, " : "",
- status & DMA_DESCR_RX_MAX_FRAME_LEN ?
- "max length, " : "",
- status & DMA_DESCR_RX_CRC_ERROR ? "CRC error, " :
- "");
-#endif
- } else {
- length =
- le32_to_cpu(rx_descr->vlan_byte_count) & 0xFFFF;
-
- /*** process packet ***/
- buffer = (uchar *)(le32_to_cpu(rx_descr->start_addr0));
- net_process_received_packet(buffer, length);
-
- invalidate_dcache_range ((unsigned long)buffer,
- (unsigned long)buffer +
- RX_BUFFER_SIZE);
- }
- /* Give this buffer back to the DMA engine */
- rx_descr->vlan_byte_count = 0;
- rx_descr->config_status = cpu_to_le32 ((RX_BUFFER_SIZE << 16) |
- DMA_DESCR_RX_OWNER);
- /* move descriptor pointer forward */
- rx_descr =
- (struct dma_descriptor
- *)(le32_to_cpu (rx_descr->next_descr_addr0));
- if (rx_descr == 0)
- rx_descr = &rx_descr_array[0];
- }
- /* remember where we are for next time */
- rx_descr_current = rx_descr;
-
- /* If the DMA engine has reached the end of the queue
- * start over at the begining */
- if (reg_RX_EXTENDED_STATUS(base) & RX_EXTENDED_STATUS_EOQ_0) {
-
- reg_RX_EXTENDED_STATUS(base) = RX_EXTENDED_STATUS_EOQ_0;
- reg_RX_QUEUE_0_PTR_LOW(base) = (u32) & rx_descr_array[0];
- reg_RX_QUEUE_0_PTR_HIGH(base) = RX_QUEUE_0_PTR_HIGH_VALID;
- }
-
- return length;
-}
-
-/*
- * disable an ethernet interface
- */
-static void tsi108_eth_halt (struct eth_device *dev)
-{
- unsigned long base;
-
- base = dev->iobase;
-
- /* Put DMA/FIFO into reset state. */
- reg_TX_CONFIG(base) = TX_CONFIG_RST;
- reg_RX_CONFIG(base) = RX_CONFIG_RST;
-
- /* Put MAC into reset state. */
- reg_MAC_CONFIG_1(base) = MAC_CONFIG_1_SOFT_RESET;
-}
diff --git a/include/netdev.h b/include/netdev.h
index 79fcee56d4..f27869072f 100644
--- a/include/netdev.h
+++ b/include/netdev.h
@@ -69,7 +69,6 @@ int sh_eth_initialize(bd_t *bis);
int skge_initialize(bd_t *bis);
int smc91111_initialize(u8 dev_num, int base_addr);
int smc911x_initialize(u8 dev_num, int base_addr);
-int tsi108_eth_initialize(bd_t *bis);
int uec_standard_init(bd_t *bis);
int uli526x_initialize(bd_t *bis);
int armada100_fec_register(unsigned long base_addr);
diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt
index 70b88f86d3..b1b08d4a5d 100644
--- a/scripts/config_whitelist.txt
+++ b/scripts/config_whitelist.txt
@@ -4550,7 +4550,6 @@ CONFIG_TSECV2
CONFIG_TSECV2_1
CONFIG_TSEC_TBI
CONFIG_TSEC_TBICR_SETTINGS
-CONFIG_TSI108_ETH_NUM_PORTS
CONFIG_TUGE1
CONFIG_TULIP
CONFIG_TULIP_FIX_DAVICOM
--
2.16.3
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [U-Boot] [PATCH 2/3] i2c: Drop CONFIG_TSI108_I2C
2018-05-09 12:24 [U-Boot] [PATCH 1/3] net: Drop CONFIG_TSI108_ETH Tuomas Tynkkynen
@ 2018-05-09 12:24 ` Tuomas Tynkkynen
2018-05-09 13:05 ` Heiko Schocher
2018-05-24 12:41 ` [U-Boot] [U-Boot,2/3] " Tom Rini
2018-05-09 12:24 ` [U-Boot] [PATCH 3/3] i2c: Drop CONFIG_SH_SH7734_I2C Tuomas Tynkkynen
2018-05-24 12:41 ` [U-Boot] [U-Boot,1/3] net: Drop CONFIG_TSI108_ETH Tom Rini
2 siblings, 2 replies; 8+ messages in thread
From: Tuomas Tynkkynen @ 2018-05-09 12:24 UTC (permalink / raw)
To: u-boot
Last user of this driver went away in June 2015 in commit
d928664f4101e24 ("powerpc: 74xx_7xx: remove 74xx_7xx cpu support")
Signed-off-by: Tuomas Tynkkynen <tuomas@tuxera.com>
---
doc/driver-model/i2c-howto.txt | 1 -
drivers/i2c/Makefile | 1 -
drivers/i2c/tsi108_i2c.c | 275 -----------------------------------------
include/tsi108.h | 207 -------------------------------
4 files changed, 484 deletions(-)
delete mode 100644 drivers/i2c/tsi108_i2c.c
delete mode 100644 include/tsi108.h
diff --git a/doc/driver-model/i2c-howto.txt b/doc/driver-model/i2c-howto.txt
index 605d3ef7ad..1b2c5312c4 100644
--- a/doc/driver-model/i2c-howto.txt
+++ b/doc/driver-model/i2c-howto.txt
@@ -16,7 +16,6 @@ ones remain:
sh_i2c
sh_sh7734_i2c
soft_i2c
- tsi108_i2c
zynq_i2c
The deadline for this work is the end of June 2017. If no one steps
diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile
index e8bb6327fb..795dd33c64 100644
--- a/drivers/i2c/Makefile
+++ b/drivers/i2c/Makefile
@@ -9,7 +9,6 @@ obj-$(CONFIG_$(SPL_)I2C_CROS_EC_TUNNEL) += cros_ec_tunnel.o
obj-$(CONFIG_$(SPL_)I2C_CROS_EC_LDO) += cros_ec_ldo.o
obj-$(CONFIG_I2C_MV) += mv_i2c.o
-obj-$(CONFIG_TSI108_I2C) += tsi108_i2c.o
obj-$(CONFIG_SH_SH7734_I2C) += sh_sh7734_i2c.o
obj-$(CONFIG_SYS_I2C) += i2c_core.o
obj-$(CONFIG_SYS_I2C_ASPEED) += ast_i2c.o
diff --git a/drivers/i2c/tsi108_i2c.c b/drivers/i2c/tsi108_i2c.c
deleted file mode 100644
index 208c0900ef..0000000000
--- a/drivers/i2c/tsi108_i2c.c
+++ /dev/null
@@ -1,275 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2004 Tundra Semiconductor Corp.
- * Author: Alex Bounine
- *
- * NOTE: This driver should be converted to driver model before June 2017.
- * Please see doc/driver-model/i2c-howto.txt for instructions.
- */
-
-#include <config.h>
-#include <common.h>
-
-#include <tsi108.h>
-
-#if defined(CONFIG_CMD_I2C)
-
-#define I2C_DELAY 100000
-#undef DEBUG_I2C
-
-#ifdef DEBUG_I2C
-#define DPRINT(x) printf (x)
-#else
-#define DPRINT(x)
-#endif
-
-/* All functions assume that Tsi108 I2C block is the only master on the bus */
-/* I2C read helper function */
-
-void i2c_init(int speed, int slaveaddr)
-{
- /*
- * The TSI108 has a fixed I2C clock rate and doesn't support slave
- * operation. This function only exists as a stub to fit into the
- * U-Boot I2C API.
- */
-}
-
-static int i2c_read_byte (
- uint i2c_chan, /* I2C channel number: 0 - main, 1 - SDC SPD */
- uchar chip_addr,/* I2C device address on the bus */
- uint byte_addr, /* Byte address within I2C device */
- uchar * buffer /* pointer to data buffer */
- )
-{
- u32 temp;
- u32 to_count = I2C_DELAY;
- u32 op_status = TSI108_I2C_TIMEOUT_ERR;
- u32 chan_offset = TSI108_I2C_OFFSET;
-
- DPRINT (("I2C read_byte() %d 0x%02x 0x%02x\n",
- i2c_chan, chip_addr, byte_addr));
-
- if (0 != i2c_chan)
- chan_offset = TSI108_I2C_SDRAM_OFFSET;
-
- /* Check if I2C operation is in progress */
- temp = *(u32 *) (CONFIG_SYS_TSI108_CSR_BASE + chan_offset + I2C_CNTRL2);
-
- if (0 == (temp & (I2C_CNTRL2_RD_STATUS | I2C_CNTRL2_WR_STATUS |
- I2C_CNTRL2_START))) {
- /* Set device address and operation (read = 0) */
- temp = (byte_addr << 16) | ((chip_addr & 0x07) << 8) |
- ((chip_addr >> 3) & 0x0F);
- *(u32 *) (CONFIG_SYS_TSI108_CSR_BASE + chan_offset + I2C_CNTRL1) =
- temp;
-
- /* Issue the read command
- * (at this moment all other parameters are 0
- * (size = 1 byte, lane = 0)
- */
-
- *(u32 *) (CONFIG_SYS_TSI108_CSR_BASE + chan_offset + I2C_CNTRL2) =
- (I2C_CNTRL2_START);
-
- /* Wait until operation completed */
- do {
- /* Read I2C operation status */
- temp = *(u32 *) (CONFIG_SYS_TSI108_CSR_BASE + chan_offset + I2C_CNTRL2);
-
- if (0 == (temp & (I2C_CNTRL2_RD_STATUS | I2C_CNTRL2_START))) {
- if (0 == (temp &
- (I2C_CNTRL2_I2C_CFGERR |
- I2C_CNTRL2_I2C_TO_ERR))
- ) {
- op_status = TSI108_I2C_SUCCESS;
-
- temp = *(u32 *) (CONFIG_SYS_TSI108_CSR_BASE +
- chan_offset +
- I2C_RD_DATA);
-
- *buffer = (u8) (temp & 0xFF);
- } else {
- /* report HW error */
- op_status = TSI108_I2C_IF_ERROR;
-
- DPRINT (("I2C HW error reported: 0x%02x\n", temp));
- }
-
- break;
- }
- } while (to_count--);
- } else {
- op_status = TSI108_I2C_IF_BUSY;
-
- DPRINT (("I2C Transaction start failed: 0x%02x\n", temp));
- }
-
- DPRINT (("I2C read_byte() status: 0x%02x\n", op_status));
- return op_status;
-}
-
-/*
- * I2C Read interface as defined in "include/i2c.h" :
- * chip_addr: I2C chip address, range 0..127
- * (to read from SPD channel EEPROM use (0xD0 ... 0xD7)
- * NOTE: The bit 7 in the chip_addr serves as a channel select.
- * This hack is for enabling "i2c sdram" command on Tsi108 boards
- * without changes to common code. Used for I2C reads only.
- * byte_addr: Memory or register address within the chip
- * alen: Number of bytes to use for addr (typically 1, 2 for larger
- * memories, 0 for register type devices with only one
- * register)
- * buffer: Pointer to destination buffer for data to be read
- * len: How many bytes to read
- *
- * Returns: 0 on success, not 0 on failure
- */
-
-int i2c_read (uchar chip_addr, uint byte_addr, int alen,
- uchar * buffer, int len)
-{
- u32 op_status = TSI108_I2C_PARAM_ERR;
- u32 i2c_if = 0;
-
- /* Hack to support second (SPD) I2C controller (SPD EEPROM read only).*/
- if (0xD0 == (chip_addr & ~0x07)) {
- i2c_if = 1;
- chip_addr &= 0x7F;
- }
- /* Check for valid I2C address */
- if (chip_addr <= 0x7F && (byte_addr + len) <= (0x01 << (alen * 8))) {
- while (len--) {
- op_status = i2c_read_byte(i2c_if, chip_addr, byte_addr++, buffer++);
-
- if (TSI108_I2C_SUCCESS != op_status) {
- DPRINT (("I2C read_byte() failed: 0x%02x (%d left)\n", op_status, len));
-
- break;
- }
- }
- }
-
- DPRINT (("I2C read() status: 0x%02x\n", op_status));
- return op_status;
-}
-
-/* I2C write helper function */
-
-static int i2c_write_byte (uchar chip_addr,/* I2C device address on the bus */
- uint byte_addr, /* Byte address within I2C device */
- uchar * buffer /* pointer to data buffer */
- )
-{
- u32 temp;
- u32 to_count = I2C_DELAY;
- u32 op_status = TSI108_I2C_TIMEOUT_ERR;
-
- /* Check if I2C operation is in progress */
- temp = *(u32 *) (CONFIG_SYS_TSI108_CSR_BASE + TSI108_I2C_OFFSET + I2C_CNTRL2);
-
- if (0 == (temp & (I2C_CNTRL2_RD_STATUS | I2C_CNTRL2_WR_STATUS | I2C_CNTRL2_START))) {
- /* Place data into the I2C Tx Register */
- *(u32 *) (CONFIG_SYS_TSI108_CSR_BASE + TSI108_I2C_OFFSET +
- I2C_TX_DATA) = (u32) * buffer;
-
- /* Set device address and operation */
- temp =
- I2C_CNTRL1_I2CWRITE | (byte_addr << 16) |
- ((chip_addr & 0x07) << 8) | ((chip_addr >> 3) & 0x0F);
- *(u32 *) (CONFIG_SYS_TSI108_CSR_BASE + TSI108_I2C_OFFSET +
- I2C_CNTRL1) = temp;
-
- /* Issue the write command (at this moment all other parameters
- * are 0 (size = 1 byte, lane = 0)
- */
-
- *(u32 *) (CONFIG_SYS_TSI108_CSR_BASE + TSI108_I2C_OFFSET +
- I2C_CNTRL2) = (I2C_CNTRL2_START);
-
- op_status = TSI108_I2C_TIMEOUT_ERR;
-
- /* Wait until operation completed */
- do {
- /* Read I2C operation status */
- temp = *(u32 *) (CONFIG_SYS_TSI108_CSR_BASE + TSI108_I2C_OFFSET + I2C_CNTRL2);
-
- if (0 == (temp & (I2C_CNTRL2_WR_STATUS | I2C_CNTRL2_START))) {
- if (0 == (temp &
- (I2C_CNTRL2_I2C_CFGERR |
- I2C_CNTRL2_I2C_TO_ERR))) {
- op_status = TSI108_I2C_SUCCESS;
- } else {
- /* report detected HW error */
- op_status = TSI108_I2C_IF_ERROR;
-
- DPRINT (("I2C HW error reported: 0x%02x\n", temp));
- }
-
- break;
- }
-
- } while (to_count--);
- } else {
- op_status = TSI108_I2C_IF_BUSY;
-
- DPRINT (("I2C Transaction start failed: 0x%02x\n", temp));
- }
-
- return op_status;
-}
-
-/*
- * I2C Write interface as defined in "include/i2c.h" :
- * chip_addr: I2C chip address, range 0..127
- * byte_addr: Memory or register address within the chip
- * alen: Number of bytes to use for addr (typically 1, 2 for larger
- * memories, 0 for register type devices with only one
- * register)
- * buffer: Pointer to data to be written
- * len: How many bytes to write
- *
- * Returns: 0 on success, not 0 on failure
- */
-
-int i2c_write (uchar chip_addr, uint byte_addr, int alen, uchar * buffer,
- int len)
-{
- u32 op_status = TSI108_I2C_PARAM_ERR;
-
- /* Check for valid I2C address */
- if (chip_addr <= 0x7F && (byte_addr + len) <= (0x01 << (alen * 8))) {
- while (len--) {
- op_status =
- i2c_write_byte (chip_addr, byte_addr++, buffer++);
-
- if (TSI108_I2C_SUCCESS != op_status) {
- DPRINT (("I2C write_byte() failed: 0x%02x (%d left)\n", op_status, len));
-
- break;
- }
- }
- }
-
- return op_status;
-}
-
-/*
- * I2C interface function as defined in "include/i2c.h".
- * Probe the given I2C chip address by reading single byte from offset 0.
- * Returns 0 if a chip responded, not 0 on failure.
- */
-
-int i2c_probe (uchar chip)
-{
- u32 tmp;
-
- /*
- * Try to read the first location of the chip.
- * The Tsi108 HW doesn't support sending just the chip address
- * and checkong for an <ACK> back.
- */
- return i2c_read (chip, 0, 1, (uchar *)&tmp, 1);
-}
-
-#endif
diff --git a/include/tsi108.h b/include/tsi108.h
deleted file mode 100644
index 8e246b857e..0000000000
--- a/include/tsi108.h
+++ /dev/null
@@ -1,207 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*****************************************************************************
- * (C) Copyright 2003; Tundra Semiconductor Corp.
- * (C) Copyright 2006; Freescale Semiconductor Corp.
- *****************************************************************************/
-
-/*
- * FILENAME: tsi108.h
- *
- * Originator: Alex Bounine
- *
- * DESCRIPTION:
- * Common definitions for the Tundra Tsi108 bridge chip
- *
- */
-
-#ifndef _TSI108_H_
-#define _TSI108_H_
-
-#define TSI108_HLP_REG_OFFSET (0x0000)
-#define TSI108_PCI_REG_OFFSET (0x1000)
-#define TSI108_CLK_REG_OFFSET (0x2000)
-#define TSI108_PB_REG_OFFSET (0x3000)
-#define TSI108_SD_REG_OFFSET (0x4000)
-#define TSI108_MPIC_REG_OFFSET (0x7400)
-
-#define PB_ID (0x000)
-#define PB_RSR (0x004)
-#define PB_BUS_MS_SELECT (0x008)
-#define PB_ISR (0x00C)
-#define PB_ARB_CTRL (0x018)
-#define PB_PVT_CTRL2 (0x034)
-#define PB_SCR (0x400)
-#define PB_ERRCS (0x404)
-#define PB_AERR (0x408)
-#define PB_REG_BAR (0x410)
-#define PB_OCN_BAR1 (0x414)
-#define PB_OCN_BAR2 (0x418)
-#define PB_SDRAM_BAR1 (0x41C)
-#define PB_SDRAM_BAR2 (0x420)
-#define PB_MCR (0xC00)
-#define PB_MCMD (0xC04)
-
-#define HLP_B0_ADDR (0x000)
-#define HLP_B1_ADDR (0x010)
-#define HLP_B2_ADDR (0x020)
-#define HLP_B3_ADDR (0x030)
-
-#define HLP_B0_MASK (0x004)
-#define HLP_B1_MASK (0x014)
-#define HLP_B2_MASK (0x024)
-#define HLP_B3_MASK (0x034)
-
-#define HLP_B0_CTRL0 (0x008)
-#define HLP_B1_CTRL0 (0x018)
-#define HLP_B2_CTRL0 (0x028)
-#define HLP_B3_CTRL0 (0x038)
-
-#define HLP_B0_CTRL1 (0x00C)
-#define HLP_B1_CTRL1 (0x01C)
-#define HLP_B2_CTRL1 (0x02C)
-#define HLP_B3_CTRL1 (0x03C)
-
-#define PCI_CSR (0x004)
-#define PCI_P2O_BAR0 (0x010)
-#define PCI_P2O_BAR0_UPPER (0x014)
-#define PCI_P2O_BAR2 (0x018)
-#define PCI_P2O_BAR2_UPPER (0x01C)
-#define PCI_P2O_BAR3 (0x020)
-#define PCI_P2O_BAR3_UPPER (0x024)
-
-#define PCI_MISC_CSR (0x040)
-#define PCI_P2O_PAGE_SIZES (0x04C)
-
-#define PCI_PCIX_STAT (0x0F4)
-
-#define PCI_IRP_STAT (0x184)
-
-#define PCI_PFAB_BAR0 (0x204)
-#define PCI_PFAB_BAR0_UPPER (0x208)
-#define PCI_PFAB_IO (0x20C)
-#define PCI_PFAB_IO_UPPER (0x210)
-
-#define PCI_PFAB_MEM32 (0x214)
-#define PCI_PFAB_MEM32_REMAP (0x218)
-#define PCI_PFAB_MEM32_MASK (0x21C)
-
-#define CG_PLL0_CTRL0 (0x210)
-#define CG_PLL0_CTRL1 (0x214)
-#define CG_PLL1_CTRL0 (0x220)
-#define CG_PLL1_CTRL1 (0x224)
-#define CG_PWRUP_STATUS (0x234)
-
-#define MPIC_CSR(n) (0x30C + (n * 0x40))
-
-#define SD_CTRL (0x000)
-#define SD_STATUS (0x004)
-#define SD_TIMING (0x008)
-#define SD_REFRESH (0x00C)
-#define SD_INT_STATUS (0x010)
-#define SD_INT_ENABLE (0x014)
-#define SD_INT_SET (0x018)
-#define SD_D0_CTRL (0x020)
-#define SD_D1_CTRL (0x024)
-#define SD_D0_BAR (0x028)
-#define SD_D1_BAR (0x02C)
-#define SD_ECC_CTRL (0x040)
-#define SD_DLL_STATUS (0x250)
-
-#define TS_SD_CTRL_ENABLE (1 << 31)
-
-#define PB_ERRCS_ES (1 << 1)
-#define PB_ISR_PBS_RD_ERR (1 << 8)
-#define PCI_IRP_STAT_P_CSR (1 << 23)
-
-/*
- * I2C : Register address offset definitions
- */
-#define I2C_CNTRL1 (0x00000000)
-#define I2C_CNTRL2 (0x00000004)
-#define I2C_RD_DATA (0x00000008)
-#define I2C_TX_DATA (0x0000000c)
-
-/*
- * I2C : Register Bit Masks and Reset Values
- * definitions for every register
- */
-
-/* I2C_CNTRL1 : Reset Value */
-#define I2C_CNTRL1_RESET_VALUE (0x0000000a)
-
-/* I2C_CNTRL1 : Register Bits Masks Definitions */
-#define I2C_CNTRL1_DEVCODE (0x0000000f)
-#define I2C_CNTRL1_PAGE (0x00000700)
-#define I2C_CNTRL1_BYTADDR (0x00ff0000)
-#define I2C_CNTRL1_I2CWRITE (0x01000000)
-
-/* I2C_CNTRL1 : Read/Write Bit Mask Definition */
-#define I2C_CNTRL1_RWMASK (0x01ff070f)
-
-/* I2C_CNTRL1 : Unused/Reserved bits Definition */
-#define I2C_CNTRL1_RESERVED (0xfe00f8f0)
-
-/* I2C_CNTRL2 : Reset Value */
-#define I2C_CNTRL2_RESET_VALUE (0x00000000)
-
-/* I2C_CNTRL2 : Register Bits Masks Definitions */
-#define I2C_CNTRL2_SIZE (0x00000003)
-#define I2C_CNTRL2_LANE (0x0000000c)
-#define I2C_CNTRL2_MULTIBYTE (0x00000010)
-#define I2C_CNTRL2_START (0x00000100)
-#define I2C_CNTRL2_WR_STATUS (0x00010000)
-#define I2C_CNTRL2_RD_STATUS (0x00020000)
-#define I2C_CNTRL2_I2C_TO_ERR (0x04000000)
-#define I2C_CNTRL2_I2C_CFGERR (0x08000000)
-#define I2C_CNTRL2_I2C_CMPLT (0x10000000)
-
-/* I2C_CNTRL2 : Read/Write Bit Mask Definition */
-#define I2C_CNTRL2_RWMASK (0x0000011f)
-
-/* I2C_CNTRL2 : Unused/Reserved bits Definition */
-#define I2C_CNTRL2_RESERVED (0xe3fcfee0)
-
-/* I2C_RD_DATA : Reset Value */
-#define I2C_RD_DATA_RESET_VALUE (0x00000000)
-
-/* I2C_RD_DATA : Register Bits Masks Definitions */
-#define I2C_RD_DATA_RBYTE0 (0x000000ff)
-#define I2C_RD_DATA_RBYTE1 (0x0000ff00)
-#define I2C_RD_DATA_RBYTE2 (0x00ff0000)
-#define I2C_RD_DATA_RBYTE3 (0xff000000)
-
-/* I2C_RD_DATA : Read/Write Bit Mask Definition */
-#define I2C_RD_DATA_RWMASK (0x00000000)
-
-/* I2C_RD_DATA : Unused/Reserved bits Definition */
-#define I2C_RD_DATA_RESERVED (0x00000000)
-
-/* I2C_TX_DATA : Reset Value */
-#define I2C_TX_DATA_RESET_VALUE (0x00000000)
-
-/* I2C_TX_DATA : Register Bits Masks Definitions */
-#define I2C_TX_DATA_TBYTE0 (0x000000ff)
-#define I2C_TX_DATA_TBYTE1 (0x0000ff00)
-#define I2C_TX_DATA_TBYTE2 (0x00ff0000)
-#define I2C_TX_DATA_TBYTE3 (0xff000000)
-
-/* I2C_TX_DATA : Read/Write Bit Mask Definition */
-#define I2C_TX_DATA_RWMASK (0xffffffff)
-
-/* I2C_TX_DATA : Unused/Reserved bits Definition */
-#define I2C_TX_DATA_RESERVED (0x00000000)
-
-#define TSI108_I2C_OFFSET 0x7000 /* offset for general use I2C channel */
-#define TSI108_I2C_SDRAM_OFFSET 0x4400 /* offset for SPD I2C channel */
-
-#define I2C_EEPROM_DEVCODE 0xA /* standard I2C EEPROM device code */
-
-/* I2C status codes */
-
-#define TSI108_I2C_SUCCESS 0
-#define TSI108_I2C_PARAM_ERR 1
-#define TSI108_I2C_TIMEOUT_ERR 2
-#define TSI108_I2C_IF_BUSY 3
-#define TSI108_I2C_IF_ERROR 4
-
-#endif /* _TSI108_H_ */
--
2.16.3
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [U-Boot] [PATCH 3/3] i2c: Drop CONFIG_SH_SH7734_I2C
2018-05-09 12:24 [U-Boot] [PATCH 1/3] net: Drop CONFIG_TSI108_ETH Tuomas Tynkkynen
2018-05-09 12:24 ` [U-Boot] [PATCH 2/3] i2c: Drop CONFIG_TSI108_I2C Tuomas Tynkkynen
@ 2018-05-09 12:24 ` Tuomas Tynkkynen
2018-05-09 13:06 ` Heiko Schocher
2018-05-24 12:41 ` [U-Boot] [U-Boot,3/3] " Tom Rini
2018-05-24 12:41 ` [U-Boot] [U-Boot,1/3] net: Drop CONFIG_TSI108_ETH Tom Rini
2 siblings, 2 replies; 8+ messages in thread
From: Tuomas Tynkkynen @ 2018-05-09 12:24 UTC (permalink / raw)
To: u-boot
Last user of this driver went away in May 2017 in commit
eb5ba3aefdf0f6c ("i2c: Drop use of CONFIG_I2C_HARD").
Signed-off-by: Tuomas Tynkkynen <tuomas@tuxera.com>
---
doc/driver-model/i2c-howto.txt | 1 -
drivers/i2c/Makefile | 1 -
drivers/i2c/sh_sh7734_i2c.c | 376 -----------------------------------------
3 files changed, 378 deletions(-)
delete mode 100644 drivers/i2c/sh_sh7734_i2c.c
diff --git a/doc/driver-model/i2c-howto.txt b/doc/driver-model/i2c-howto.txt
index 1b2c5312c4..8ba2f6e267 100644
--- a/doc/driver-model/i2c-howto.txt
+++ b/doc/driver-model/i2c-howto.txt
@@ -14,7 +14,6 @@ ones remain:
ppc4xx_i2c
rcar_i2c
sh_i2c
- sh_sh7734_i2c
soft_i2c
zynq_i2c
diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile
index 795dd33c64..e32d65dc2f 100644
--- a/drivers/i2c/Makefile
+++ b/drivers/i2c/Makefile
@@ -9,7 +9,6 @@ obj-$(CONFIG_$(SPL_)I2C_CROS_EC_TUNNEL) += cros_ec_tunnel.o
obj-$(CONFIG_$(SPL_)I2C_CROS_EC_LDO) += cros_ec_ldo.o
obj-$(CONFIG_I2C_MV) += mv_i2c.o
-obj-$(CONFIG_SH_SH7734_I2C) += sh_sh7734_i2c.o
obj-$(CONFIG_SYS_I2C) += i2c_core.o
obj-$(CONFIG_SYS_I2C_ASPEED) += ast_i2c.o
obj-$(CONFIG_SYS_I2C_AT91) += at91_i2c.o
diff --git a/drivers/i2c/sh_sh7734_i2c.c b/drivers/i2c/sh_sh7734_i2c.c
deleted file mode 100644
index 6fe356baca..0000000000
--- a/drivers/i2c/sh_sh7734_i2c.c
+++ /dev/null
@@ -1,376 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
- * Copyright (C) 2012 Renesas Solutions Corp.
- *
- * NOTE: This driver should be converted to driver model before June 2017.
- * Please see doc/driver-model/i2c-howto.txt for instructions.
- */
-
-#include <common.h>
-#include <i2c.h>
-#include <asm/io.h>
-
-struct sh_i2c {
- u8 iccr1;
- u8 iccr2;
- u8 icmr;
- u8 icier;
- u8 icsr;
- u8 sar;
- u8 icdrt;
- u8 icdrr;
- u8 nf2cyc;
- u8 __pad0;
- u8 __pad1;
-};
-
-static struct sh_i2c *base;
-static u8 iccr1_cks, nf2cyc;
-
-/* ICCR1 */
-#define SH_I2C_ICCR1_ICE (1 << 7)
-#define SH_I2C_ICCR1_RCVD (1 << 6)
-#define SH_I2C_ICCR1_MST (1 << 5)
-#define SH_I2C_ICCR1_TRS (1 << 4)
-#define SH_I2C_ICCR1_MTRS \
- (SH_I2C_ICCR1_MST | SH_I2C_ICCR1_TRS)
-
-/* ICCR1 */
-#define SH_I2C_ICCR2_BBSY (1 << 7)
-#define SH_I2C_ICCR2_SCP (1 << 6)
-#define SH_I2C_ICCR2_SDAO (1 << 5)
-#define SH_I2C_ICCR2_SDAOP (1 << 4)
-#define SH_I2C_ICCR2_SCLO (1 << 3)
-#define SH_I2C_ICCR2_IICRST (1 << 1)
-
-#define SH_I2C_ICIER_TIE (1 << 7)
-#define SH_I2C_ICIER_TEIE (1 << 6)
-#define SH_I2C_ICIER_RIE (1 << 5)
-#define SH_I2C_ICIER_NAKIE (1 << 4)
-#define SH_I2C_ICIER_STIE (1 << 3)
-#define SH_I2C_ICIER_ACKE (1 << 2)
-#define SH_I2C_ICIER_ACKBR (1 << 1)
-#define SH_I2C_ICIER_ACKBT (1 << 0)
-
-#define SH_I2C_ICSR_TDRE (1 << 7)
-#define SH_I2C_ICSR_TEND (1 << 6)
-#define SH_I2C_ICSR_RDRF (1 << 5)
-#define SH_I2C_ICSR_NACKF (1 << 4)
-#define SH_I2C_ICSR_STOP (1 << 3)
-#define SH_I2C_ICSR_ALOVE (1 << 2)
-#define SH_I2C_ICSR_AAS (1 << 1)
-#define SH_I2C_ICSR_ADZ (1 << 0)
-
-#define IRQ_WAIT 1000
-
-static void sh_i2c_send_stop(struct sh_i2c *base)
-{
- clrbits_8(&base->iccr2, SH_I2C_ICCR2_BBSY | SH_I2C_ICCR2_SCP);
-}
-
-static int check_icsr_bits(struct sh_i2c *base, u8 bits)
-{
- int i;
-
- for (i = 0; i < IRQ_WAIT; i++) {
- if (bits & readb(&base->icsr))
- return 0;
- udelay(10);
- }
-
- return 1;
-}
-
-static int check_stop(struct sh_i2c *base)
-{
- int ret = check_icsr_bits(base, SH_I2C_ICSR_STOP);
- clrbits_8(&base->icsr, SH_I2C_ICSR_STOP);
-
- return ret;
-}
-
-static int check_tend(struct sh_i2c *base, int stop)
-{
- int ret = check_icsr_bits(base, SH_I2C_ICSR_TEND);
-
- if (stop) {
- clrbits_8(&base->icsr, SH_I2C_ICSR_STOP);
- sh_i2c_send_stop(base);
- }
-
- clrbits_8(&base->icsr, SH_I2C_ICSR_TEND);
- return ret;
-}
-
-static int check_tdre(struct sh_i2c *base)
-{
- return check_icsr_bits(base, SH_I2C_ICSR_TDRE);
-}
-
-static int check_rdrf(struct sh_i2c *base)
-{
- return check_icsr_bits(base, SH_I2C_ICSR_RDRF);
-}
-
-static int check_bbsy(struct sh_i2c *base)
-{
- int i;
-
- for (i = 0 ; i < IRQ_WAIT ; i++) {
- if (!(SH_I2C_ICCR2_BBSY & readb(&base->iccr2)))
- return 0;
- udelay(10);
- }
- return 1;
-}
-
-static int check_ackbr(struct sh_i2c *base)
-{
- int i;
-
- for (i = 0 ; i < IRQ_WAIT ; i++) {
- if (!(SH_I2C_ICIER_ACKBR & readb(&base->icier)))
- return 0;
- udelay(10);
- }
-
- return 1;
-}
-
-static void sh_i2c_reset(struct sh_i2c *base)
-{
- setbits_8(&base->iccr2, SH_I2C_ICCR2_IICRST);
-
- udelay(100);
-
- clrbits_8(&base->iccr2, SH_I2C_ICCR2_IICRST);
-}
-
-static int i2c_set_addr(struct sh_i2c *base, u8 id, u8 reg)
-{
- if (check_bbsy(base)) {
- puts("i2c bus busy\n");
- goto fail;
- }
-
- setbits_8(&base->iccr1, SH_I2C_ICCR1_MTRS);
- clrsetbits_8(&base->iccr2, SH_I2C_ICCR2_SCP, SH_I2C_ICCR2_BBSY);
-
- writeb((id << 1), &base->icdrt);
-
- if (check_tend(base, 0)) {
- puts("TEND check fail...\n");
- goto fail;
- }
-
- if (check_ackbr(base)) {
- check_tend(base, 0);
- sh_i2c_send_stop(base);
- goto fail;
- }
-
- writeb(reg, &base->icdrt);
-
- if (check_tdre(base)) {
- puts("TDRE check fail...\n");
- goto fail;
- }
-
- if (check_tend(base, 0)) {
- puts("TEND check fail...\n");
- goto fail;
- }
-
- return 0;
-fail:
-
- return 1;
-}
-
-static int
-i2c_raw_write(struct sh_i2c *base, u8 id, u8 reg, u8 *val, int size)
-{
- int i;
-
- if (i2c_set_addr(base, id, reg)) {
- puts("Fail set slave address\n");
- return 1;
- }
-
- for (i = 0; i < size; i++) {
- writeb(val[i], &base->icdrt);
- check_tdre(base);
- }
-
- check_tend(base, 1);
- check_stop(base);
-
- udelay(100);
-
- clrbits_8(&base->iccr1, SH_I2C_ICCR1_MTRS);
- clrbits_8(&base->icsr, SH_I2C_ICSR_TDRE);
- sh_i2c_reset(base);
-
- return 0;
-}
-
-static u8 i2c_raw_read(struct sh_i2c *base, u8 id, u8 reg)
-{
- u8 ret = 0;
-
- if (i2c_set_addr(base, id, reg)) {
- puts("Fail set slave address\n");
- goto fail;
- }
-
- clrsetbits_8(&base->iccr2, SH_I2C_ICCR2_SCP, SH_I2C_ICCR2_BBSY);
- writeb((id << 1) | 1, &base->icdrt);
-
- if (check_tend(base, 0))
- puts("TDRE check fail...\n");
-
- clrsetbits_8(&base->iccr1, SH_I2C_ICCR1_TRS, SH_I2C_ICCR1_MST);
- clrbits_8(&base->icsr, SH_I2C_ICSR_TDRE);
- setbits_8(&base->icier, SH_I2C_ICIER_ACKBT);
- setbits_8(&base->iccr1, SH_I2C_ICCR1_RCVD);
-
- /* read data (dummy) */
- ret = readb(&base->icdrr);
-
- if (check_rdrf(base)) {
- puts("check RDRF error\n");
- goto fail;
- }
-
- clrbits_8(&base->icsr, SH_I2C_ICSR_STOP);
- udelay(1000);
-
- sh_i2c_send_stop(base);
-
- if (check_stop(base)) {
- puts("check STOP error\n");
- goto fail;
- }
-
- clrbits_8(&base->iccr1, SH_I2C_ICCR1_MTRS);
- clrbits_8(&base->icsr, SH_I2C_ICSR_TDRE);
-
- /* data read */
- ret = readb(&base->icdrr);
-
-fail:
- clrbits_8(&base->iccr1, SH_I2C_ICCR1_RCVD);
-
- return ret;
-}
-
-#ifdef CONFIG_I2C_MULTI_BUS
-static unsigned int current_bus;
-
-/**
- * i2c_set_bus_num - change active I2C bus
- * @bus: bus index, zero based
- * @returns: 0 on success, non-0 on failure
- */
-int i2c_set_bus_num(unsigned int bus)
-{
- switch (bus) {
- case 0:
- base = (void *)CONFIG_SH_I2C_BASE0;
- break;
- case 1:
- base = (void *)CONFIG_SH_I2C_BASE1;
- break;
- default:
- printf("Bad bus: %d\n", bus);
- return -1;
- }
-
- current_bus = bus;
-
- return 0;
-}
-
-/**
- * i2c_get_bus_num - returns index of active I2C bus
- */
-unsigned int i2c_get_bus_num(void)
-{
- return current_bus;
-}
-#endif
-
-void i2c_init(int speed, int slaveaddr)
-{
-#ifdef CONFIG_I2C_MULTI_BUS
- current_bus = 0;
-#endif
- base = (struct sh_i2c *)CONFIG_SH_I2C_BASE0;
-
- if (speed == 400000)
- iccr1_cks = 0x07;
- else
- iccr1_cks = 0x0F;
-
- nf2cyc = 1;
-
- /* Reset */
- sh_i2c_reset(base);
-
- /* ICE enable and set clock */
- writeb(SH_I2C_ICCR1_ICE | iccr1_cks, &base->iccr1);
- writeb(nf2cyc, &base->nf2cyc);
-}
-
-/*
- * i2c_read: - Read multiple bytes from an i2c device
- *
- * The higher level routines take into account that this function is only
- * called with len < page length of the device (see configuration file)
- *
- * @chip: address of the chip which is to be read
- * @addr: i2c data address within the chip
- * @alen: length of the i2c data address (1..2 bytes)
- * @buffer: where to write the data
- * @len: how much byte do we want to read
- * @return: 0 in case of success
- */
-int i2c_read(u8 chip, u32 addr, int alen, u8 *buffer, int len)
-{
- int i = 0;
- for (i = 0; i < len; i++)
- buffer[i] = i2c_raw_read(base, chip, addr + i);
-
- return 0;
-}
-
-/*
- * i2c_write: - Write multiple bytes to an i2c device
- *
- * The higher level routines take into account that this function is only
- * called with len < page length of the device (see configuration file)
- *
- * @chip: address of the chip which is to be written
- * @addr: i2c data address within the chip
- * @alen: length of the i2c data address (1..2 bytes)
- * @buffer: where to find the data to be written
- * @len: how much byte do we want to read
- * @return: 0 in case of success
- */
-int i2c_write(u8 chip, u32 addr, int alen, u8 *buffer, int len)
-{
- return i2c_raw_write(base, chip, addr, buffer, len);
-}
-
-/*
- * i2c_probe: - Test if a chip answers for a given i2c address
- *
- * @chip: address of the chip which is searched for
- * @return: 0 if a chip was found, -1 otherwhise
- */
-int i2c_probe(u8 chip)
-{
- u8 byte;
- return i2c_read(chip, 0, 0, &byte, 1);
-}
--
2.16.3
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [U-Boot] [PATCH 2/3] i2c: Drop CONFIG_TSI108_I2C
2018-05-09 12:24 ` [U-Boot] [PATCH 2/3] i2c: Drop CONFIG_TSI108_I2C Tuomas Tynkkynen
@ 2018-05-09 13:05 ` Heiko Schocher
2018-05-24 12:41 ` [U-Boot] [U-Boot,2/3] " Tom Rini
1 sibling, 0 replies; 8+ messages in thread
From: Heiko Schocher @ 2018-05-09 13:05 UTC (permalink / raw)
To: u-boot
Hello Tuomas,
Am 09.05.2018 um 14:24 schrieb Tuomas Tynkkynen:
> Last user of this driver went away in June 2015 in commit
> d928664f4101e24 ("powerpc: 74xx_7xx: remove 74xx_7xx cpu support")
>
> Signed-off-by: Tuomas Tynkkynen <tuomas@tuxera.com>
> ---
> doc/driver-model/i2c-howto.txt | 1 -
> drivers/i2c/Makefile | 1 -
> drivers/i2c/tsi108_i2c.c | 275 -----------------------------------------
> include/tsi108.h | 207 -------------------------------
> 4 files changed, 484 deletions(-)
> delete mode 100644 drivers/i2c/tsi108_i2c.c
> delete mode 100644 include/tsi108.h
Acked-by: Heiko Schocher <hs@denx.de>
Thanks!
bye,
Heiko
>
> diff --git a/doc/driver-model/i2c-howto.txt b/doc/driver-model/i2c-howto.txt
> index 605d3ef7ad..1b2c5312c4 100644
> --- a/doc/driver-model/i2c-howto.txt
> +++ b/doc/driver-model/i2c-howto.txt
> @@ -16,7 +16,6 @@ ones remain:
> sh_i2c
> sh_sh7734_i2c
> soft_i2c
> - tsi108_i2c
> zynq_i2c
>
> The deadline for this work is the end of June 2017. If no one steps
> diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile
> index e8bb6327fb..795dd33c64 100644
> --- a/drivers/i2c/Makefile
> +++ b/drivers/i2c/Makefile
> @@ -9,7 +9,6 @@ obj-$(CONFIG_$(SPL_)I2C_CROS_EC_TUNNEL) += cros_ec_tunnel.o
> obj-$(CONFIG_$(SPL_)I2C_CROS_EC_LDO) += cros_ec_ldo.o
>
> obj-$(CONFIG_I2C_MV) += mv_i2c.o
> -obj-$(CONFIG_TSI108_I2C) += tsi108_i2c.o
> obj-$(CONFIG_SH_SH7734_I2C) += sh_sh7734_i2c.o
> obj-$(CONFIG_SYS_I2C) += i2c_core.o
> obj-$(CONFIG_SYS_I2C_ASPEED) += ast_i2c.o
> diff --git a/drivers/i2c/tsi108_i2c.c b/drivers/i2c/tsi108_i2c.c
> deleted file mode 100644
> index 208c0900ef..0000000000
> --- a/drivers/i2c/tsi108_i2c.c
> +++ /dev/null
> @@ -1,275 +0,0 @@
> -// SPDX-License-Identifier: GPL-2.0+
> -/*
> - * (C) Copyright 2004 Tundra Semiconductor Corp.
> - * Author: Alex Bounine
> - *
> - * NOTE: This driver should be converted to driver model before June 2017.
> - * Please see doc/driver-model/i2c-howto.txt for instructions.
> - */
> -
> -#include <config.h>
> -#include <common.h>
> -
> -#include <tsi108.h>
> -
> -#if defined(CONFIG_CMD_I2C)
> -
> -#define I2C_DELAY 100000
> -#undef DEBUG_I2C
> -
> -#ifdef DEBUG_I2C
> -#define DPRINT(x) printf (x)
> -#else
> -#define DPRINT(x)
> -#endif
> -
> -/* All functions assume that Tsi108 I2C block is the only master on the bus */
> -/* I2C read helper function */
> -
> -void i2c_init(int speed, int slaveaddr)
> -{
> - /*
> - * The TSI108 has a fixed I2C clock rate and doesn't support slave
> - * operation. This function only exists as a stub to fit into the
> - * U-Boot I2C API.
> - */
> -}
> -
> -static int i2c_read_byte (
> - uint i2c_chan, /* I2C channel number: 0 - main, 1 - SDC SPD */
> - uchar chip_addr,/* I2C device address on the bus */
> - uint byte_addr, /* Byte address within I2C device */
> - uchar * buffer /* pointer to data buffer */
> - )
> -{
> - u32 temp;
> - u32 to_count = I2C_DELAY;
> - u32 op_status = TSI108_I2C_TIMEOUT_ERR;
> - u32 chan_offset = TSI108_I2C_OFFSET;
> -
> - DPRINT (("I2C read_byte() %d 0x%02x 0x%02x\n",
> - i2c_chan, chip_addr, byte_addr));
> -
> - if (0 != i2c_chan)
> - chan_offset = TSI108_I2C_SDRAM_OFFSET;
> -
> - /* Check if I2C operation is in progress */
> - temp = *(u32 *) (CONFIG_SYS_TSI108_CSR_BASE + chan_offset + I2C_CNTRL2);
> -
> - if (0 == (temp & (I2C_CNTRL2_RD_STATUS | I2C_CNTRL2_WR_STATUS |
> - I2C_CNTRL2_START))) {
> - /* Set device address and operation (read = 0) */
> - temp = (byte_addr << 16) | ((chip_addr & 0x07) << 8) |
> - ((chip_addr >> 3) & 0x0F);
> - *(u32 *) (CONFIG_SYS_TSI108_CSR_BASE + chan_offset + I2C_CNTRL1) =
> - temp;
> -
> - /* Issue the read command
> - * (at this moment all other parameters are 0
> - * (size = 1 byte, lane = 0)
> - */
> -
> - *(u32 *) (CONFIG_SYS_TSI108_CSR_BASE + chan_offset + I2C_CNTRL2) =
> - (I2C_CNTRL2_START);
> -
> - /* Wait until operation completed */
> - do {
> - /* Read I2C operation status */
> - temp = *(u32 *) (CONFIG_SYS_TSI108_CSR_BASE + chan_offset + I2C_CNTRL2);
> -
> - if (0 == (temp & (I2C_CNTRL2_RD_STATUS | I2C_CNTRL2_START))) {
> - if (0 == (temp &
> - (I2C_CNTRL2_I2C_CFGERR |
> - I2C_CNTRL2_I2C_TO_ERR))
> - ) {
> - op_status = TSI108_I2C_SUCCESS;
> -
> - temp = *(u32 *) (CONFIG_SYS_TSI108_CSR_BASE +
> - chan_offset +
> - I2C_RD_DATA);
> -
> - *buffer = (u8) (temp & 0xFF);
> - } else {
> - /* report HW error */
> - op_status = TSI108_I2C_IF_ERROR;
> -
> - DPRINT (("I2C HW error reported: 0x%02x\n", temp));
> - }
> -
> - break;
> - }
> - } while (to_count--);
> - } else {
> - op_status = TSI108_I2C_IF_BUSY;
> -
> - DPRINT (("I2C Transaction start failed: 0x%02x\n", temp));
> - }
> -
> - DPRINT (("I2C read_byte() status: 0x%02x\n", op_status));
> - return op_status;
> -}
> -
> -/*
> - * I2C Read interface as defined in "include/i2c.h" :
> - * chip_addr: I2C chip address, range 0..127
> - * (to read from SPD channel EEPROM use (0xD0 ... 0xD7)
> - * NOTE: The bit 7 in the chip_addr serves as a channel select.
> - * This hack is for enabling "i2c sdram" command on Tsi108 boards
> - * without changes to common code. Used for I2C reads only.
> - * byte_addr: Memory or register address within the chip
> - * alen: Number of bytes to use for addr (typically 1, 2 for larger
> - * memories, 0 for register type devices with only one
> - * register)
> - * buffer: Pointer to destination buffer for data to be read
> - * len: How many bytes to read
> - *
> - * Returns: 0 on success, not 0 on failure
> - */
> -
> -int i2c_read (uchar chip_addr, uint byte_addr, int alen,
> - uchar * buffer, int len)
> -{
> - u32 op_status = TSI108_I2C_PARAM_ERR;
> - u32 i2c_if = 0;
> -
> - /* Hack to support second (SPD) I2C controller (SPD EEPROM read only).*/
> - if (0xD0 == (chip_addr & ~0x07)) {
> - i2c_if = 1;
> - chip_addr &= 0x7F;
> - }
> - /* Check for valid I2C address */
> - if (chip_addr <= 0x7F && (byte_addr + len) <= (0x01 << (alen * 8))) {
> - while (len--) {
> - op_status = i2c_read_byte(i2c_if, chip_addr, byte_addr++, buffer++);
> -
> - if (TSI108_I2C_SUCCESS != op_status) {
> - DPRINT (("I2C read_byte() failed: 0x%02x (%d left)\n", op_status, len));
> -
> - break;
> - }
> - }
> - }
> -
> - DPRINT (("I2C read() status: 0x%02x\n", op_status));
> - return op_status;
> -}
> -
> -/* I2C write helper function */
> -
> -static int i2c_write_byte (uchar chip_addr,/* I2C device address on the bus */
> - uint byte_addr, /* Byte address within I2C device */
> - uchar * buffer /* pointer to data buffer */
> - )
> -{
> - u32 temp;
> - u32 to_count = I2C_DELAY;
> - u32 op_status = TSI108_I2C_TIMEOUT_ERR;
> -
> - /* Check if I2C operation is in progress */
> - temp = *(u32 *) (CONFIG_SYS_TSI108_CSR_BASE + TSI108_I2C_OFFSET + I2C_CNTRL2);
> -
> - if (0 == (temp & (I2C_CNTRL2_RD_STATUS | I2C_CNTRL2_WR_STATUS | I2C_CNTRL2_START))) {
> - /* Place data into the I2C Tx Register */
> - *(u32 *) (CONFIG_SYS_TSI108_CSR_BASE + TSI108_I2C_OFFSET +
> - I2C_TX_DATA) = (u32) * buffer;
> -
> - /* Set device address and operation */
> - temp =
> - I2C_CNTRL1_I2CWRITE | (byte_addr << 16) |
> - ((chip_addr & 0x07) << 8) | ((chip_addr >> 3) & 0x0F);
> - *(u32 *) (CONFIG_SYS_TSI108_CSR_BASE + TSI108_I2C_OFFSET +
> - I2C_CNTRL1) = temp;
> -
> - /* Issue the write command (at this moment all other parameters
> - * are 0 (size = 1 byte, lane = 0)
> - */
> -
> - *(u32 *) (CONFIG_SYS_TSI108_CSR_BASE + TSI108_I2C_OFFSET +
> - I2C_CNTRL2) = (I2C_CNTRL2_START);
> -
> - op_status = TSI108_I2C_TIMEOUT_ERR;
> -
> - /* Wait until operation completed */
> - do {
> - /* Read I2C operation status */
> - temp = *(u32 *) (CONFIG_SYS_TSI108_CSR_BASE + TSI108_I2C_OFFSET + I2C_CNTRL2);
> -
> - if (0 == (temp & (I2C_CNTRL2_WR_STATUS | I2C_CNTRL2_START))) {
> - if (0 == (temp &
> - (I2C_CNTRL2_I2C_CFGERR |
> - I2C_CNTRL2_I2C_TO_ERR))) {
> - op_status = TSI108_I2C_SUCCESS;
> - } else {
> - /* report detected HW error */
> - op_status = TSI108_I2C_IF_ERROR;
> -
> - DPRINT (("I2C HW error reported: 0x%02x\n", temp));
> - }
> -
> - break;
> - }
> -
> - } while (to_count--);
> - } else {
> - op_status = TSI108_I2C_IF_BUSY;
> -
> - DPRINT (("I2C Transaction start failed: 0x%02x\n", temp));
> - }
> -
> - return op_status;
> -}
> -
> -/*
> - * I2C Write interface as defined in "include/i2c.h" :
> - * chip_addr: I2C chip address, range 0..127
> - * byte_addr: Memory or register address within the chip
> - * alen: Number of bytes to use for addr (typically 1, 2 for larger
> - * memories, 0 for register type devices with only one
> - * register)
> - * buffer: Pointer to data to be written
> - * len: How many bytes to write
> - *
> - * Returns: 0 on success, not 0 on failure
> - */
> -
> -int i2c_write (uchar chip_addr, uint byte_addr, int alen, uchar * buffer,
> - int len)
> -{
> - u32 op_status = TSI108_I2C_PARAM_ERR;
> -
> - /* Check for valid I2C address */
> - if (chip_addr <= 0x7F && (byte_addr + len) <= (0x01 << (alen * 8))) {
> - while (len--) {
> - op_status =
> - i2c_write_byte (chip_addr, byte_addr++, buffer++);
> -
> - if (TSI108_I2C_SUCCESS != op_status) {
> - DPRINT (("I2C write_byte() failed: 0x%02x (%d left)\n", op_status, len));
> -
> - break;
> - }
> - }
> - }
> -
> - return op_status;
> -}
> -
> -/*
> - * I2C interface function as defined in "include/i2c.h".
> - * Probe the given I2C chip address by reading single byte from offset 0.
> - * Returns 0 if a chip responded, not 0 on failure.
> - */
> -
> -int i2c_probe (uchar chip)
> -{
> - u32 tmp;
> -
> - /*
> - * Try to read the first location of the chip.
> - * The Tsi108 HW doesn't support sending just the chip address
> - * and checkong for an <ACK> back.
> - */
> - return i2c_read (chip, 0, 1, (uchar *)&tmp, 1);
> -}
> -
> -#endif
> diff --git a/include/tsi108.h b/include/tsi108.h
> deleted file mode 100644
> index 8e246b857e..0000000000
> --- a/include/tsi108.h
> +++ /dev/null
> @@ -1,207 +0,0 @@
> -/* SPDX-License-Identifier: GPL-2.0+ */
> -/*****************************************************************************
> - * (C) Copyright 2003; Tundra Semiconductor Corp.
> - * (C) Copyright 2006; Freescale Semiconductor Corp.
> - *****************************************************************************/
> -
> -/*
> - * FILENAME: tsi108.h
> - *
> - * Originator: Alex Bounine
> - *
> - * DESCRIPTION:
> - * Common definitions for the Tundra Tsi108 bridge chip
> - *
> - */
> -
> -#ifndef _TSI108_H_
> -#define _TSI108_H_
> -
> -#define TSI108_HLP_REG_OFFSET (0x0000)
> -#define TSI108_PCI_REG_OFFSET (0x1000)
> -#define TSI108_CLK_REG_OFFSET (0x2000)
> -#define TSI108_PB_REG_OFFSET (0x3000)
> -#define TSI108_SD_REG_OFFSET (0x4000)
> -#define TSI108_MPIC_REG_OFFSET (0x7400)
> -
> -#define PB_ID (0x000)
> -#define PB_RSR (0x004)
> -#define PB_BUS_MS_SELECT (0x008)
> -#define PB_ISR (0x00C)
> -#define PB_ARB_CTRL (0x018)
> -#define PB_PVT_CTRL2 (0x034)
> -#define PB_SCR (0x400)
> -#define PB_ERRCS (0x404)
> -#define PB_AERR (0x408)
> -#define PB_REG_BAR (0x410)
> -#define PB_OCN_BAR1 (0x414)
> -#define PB_OCN_BAR2 (0x418)
> -#define PB_SDRAM_BAR1 (0x41C)
> -#define PB_SDRAM_BAR2 (0x420)
> -#define PB_MCR (0xC00)
> -#define PB_MCMD (0xC04)
> -
> -#define HLP_B0_ADDR (0x000)
> -#define HLP_B1_ADDR (0x010)
> -#define HLP_B2_ADDR (0x020)
> -#define HLP_B3_ADDR (0x030)
> -
> -#define HLP_B0_MASK (0x004)
> -#define HLP_B1_MASK (0x014)
> -#define HLP_B2_MASK (0x024)
> -#define HLP_B3_MASK (0x034)
> -
> -#define HLP_B0_CTRL0 (0x008)
> -#define HLP_B1_CTRL0 (0x018)
> -#define HLP_B2_CTRL0 (0x028)
> -#define HLP_B3_CTRL0 (0x038)
> -
> -#define HLP_B0_CTRL1 (0x00C)
> -#define HLP_B1_CTRL1 (0x01C)
> -#define HLP_B2_CTRL1 (0x02C)
> -#define HLP_B3_CTRL1 (0x03C)
> -
> -#define PCI_CSR (0x004)
> -#define PCI_P2O_BAR0 (0x010)
> -#define PCI_P2O_BAR0_UPPER (0x014)
> -#define PCI_P2O_BAR2 (0x018)
> -#define PCI_P2O_BAR2_UPPER (0x01C)
> -#define PCI_P2O_BAR3 (0x020)
> -#define PCI_P2O_BAR3_UPPER (0x024)
> -
> -#define PCI_MISC_CSR (0x040)
> -#define PCI_P2O_PAGE_SIZES (0x04C)
> -
> -#define PCI_PCIX_STAT (0x0F4)
> -
> -#define PCI_IRP_STAT (0x184)
> -
> -#define PCI_PFAB_BAR0 (0x204)
> -#define PCI_PFAB_BAR0_UPPER (0x208)
> -#define PCI_PFAB_IO (0x20C)
> -#define PCI_PFAB_IO_UPPER (0x210)
> -
> -#define PCI_PFAB_MEM32 (0x214)
> -#define PCI_PFAB_MEM32_REMAP (0x218)
> -#define PCI_PFAB_MEM32_MASK (0x21C)
> -
> -#define CG_PLL0_CTRL0 (0x210)
> -#define CG_PLL0_CTRL1 (0x214)
> -#define CG_PLL1_CTRL0 (0x220)
> -#define CG_PLL1_CTRL1 (0x224)
> -#define CG_PWRUP_STATUS (0x234)
> -
> -#define MPIC_CSR(n) (0x30C + (n * 0x40))
> -
> -#define SD_CTRL (0x000)
> -#define SD_STATUS (0x004)
> -#define SD_TIMING (0x008)
> -#define SD_REFRESH (0x00C)
> -#define SD_INT_STATUS (0x010)
> -#define SD_INT_ENABLE (0x014)
> -#define SD_INT_SET (0x018)
> -#define SD_D0_CTRL (0x020)
> -#define SD_D1_CTRL (0x024)
> -#define SD_D0_BAR (0x028)
> -#define SD_D1_BAR (0x02C)
> -#define SD_ECC_CTRL (0x040)
> -#define SD_DLL_STATUS (0x250)
> -
> -#define TS_SD_CTRL_ENABLE (1 << 31)
> -
> -#define PB_ERRCS_ES (1 << 1)
> -#define PB_ISR_PBS_RD_ERR (1 << 8)
> -#define PCI_IRP_STAT_P_CSR (1 << 23)
> -
> -/*
> - * I2C : Register address offset definitions
> - */
> -#define I2C_CNTRL1 (0x00000000)
> -#define I2C_CNTRL2 (0x00000004)
> -#define I2C_RD_DATA (0x00000008)
> -#define I2C_TX_DATA (0x0000000c)
> -
> -/*
> - * I2C : Register Bit Masks and Reset Values
> - * definitions for every register
> - */
> -
> -/* I2C_CNTRL1 : Reset Value */
> -#define I2C_CNTRL1_RESET_VALUE (0x0000000a)
> -
> -/* I2C_CNTRL1 : Register Bits Masks Definitions */
> -#define I2C_CNTRL1_DEVCODE (0x0000000f)
> -#define I2C_CNTRL1_PAGE (0x00000700)
> -#define I2C_CNTRL1_BYTADDR (0x00ff0000)
> -#define I2C_CNTRL1_I2CWRITE (0x01000000)
> -
> -/* I2C_CNTRL1 : Read/Write Bit Mask Definition */
> -#define I2C_CNTRL1_RWMASK (0x01ff070f)
> -
> -/* I2C_CNTRL1 : Unused/Reserved bits Definition */
> -#define I2C_CNTRL1_RESERVED (0xfe00f8f0)
> -
> -/* I2C_CNTRL2 : Reset Value */
> -#define I2C_CNTRL2_RESET_VALUE (0x00000000)
> -
> -/* I2C_CNTRL2 : Register Bits Masks Definitions */
> -#define I2C_CNTRL2_SIZE (0x00000003)
> -#define I2C_CNTRL2_LANE (0x0000000c)
> -#define I2C_CNTRL2_MULTIBYTE (0x00000010)
> -#define I2C_CNTRL2_START (0x00000100)
> -#define I2C_CNTRL2_WR_STATUS (0x00010000)
> -#define I2C_CNTRL2_RD_STATUS (0x00020000)
> -#define I2C_CNTRL2_I2C_TO_ERR (0x04000000)
> -#define I2C_CNTRL2_I2C_CFGERR (0x08000000)
> -#define I2C_CNTRL2_I2C_CMPLT (0x10000000)
> -
> -/* I2C_CNTRL2 : Read/Write Bit Mask Definition */
> -#define I2C_CNTRL2_RWMASK (0x0000011f)
> -
> -/* I2C_CNTRL2 : Unused/Reserved bits Definition */
> -#define I2C_CNTRL2_RESERVED (0xe3fcfee0)
> -
> -/* I2C_RD_DATA : Reset Value */
> -#define I2C_RD_DATA_RESET_VALUE (0x00000000)
> -
> -/* I2C_RD_DATA : Register Bits Masks Definitions */
> -#define I2C_RD_DATA_RBYTE0 (0x000000ff)
> -#define I2C_RD_DATA_RBYTE1 (0x0000ff00)
> -#define I2C_RD_DATA_RBYTE2 (0x00ff0000)
> -#define I2C_RD_DATA_RBYTE3 (0xff000000)
> -
> -/* I2C_RD_DATA : Read/Write Bit Mask Definition */
> -#define I2C_RD_DATA_RWMASK (0x00000000)
> -
> -/* I2C_RD_DATA : Unused/Reserved bits Definition */
> -#define I2C_RD_DATA_RESERVED (0x00000000)
> -
> -/* I2C_TX_DATA : Reset Value */
> -#define I2C_TX_DATA_RESET_VALUE (0x00000000)
> -
> -/* I2C_TX_DATA : Register Bits Masks Definitions */
> -#define I2C_TX_DATA_TBYTE0 (0x000000ff)
> -#define I2C_TX_DATA_TBYTE1 (0x0000ff00)
> -#define I2C_TX_DATA_TBYTE2 (0x00ff0000)
> -#define I2C_TX_DATA_TBYTE3 (0xff000000)
> -
> -/* I2C_TX_DATA : Read/Write Bit Mask Definition */
> -#define I2C_TX_DATA_RWMASK (0xffffffff)
> -
> -/* I2C_TX_DATA : Unused/Reserved bits Definition */
> -#define I2C_TX_DATA_RESERVED (0x00000000)
> -
> -#define TSI108_I2C_OFFSET 0x7000 /* offset for general use I2C channel */
> -#define TSI108_I2C_SDRAM_OFFSET 0x4400 /* offset for SPD I2C channel */
> -
> -#define I2C_EEPROM_DEVCODE 0xA /* standard I2C EEPROM device code */
> -
> -/* I2C status codes */
> -
> -#define TSI108_I2C_SUCCESS 0
> -#define TSI108_I2C_PARAM_ERR 1
> -#define TSI108_I2C_TIMEOUT_ERR 2
> -#define TSI108_I2C_IF_BUSY 3
> -#define TSI108_I2C_IF_ERROR 4
> -
> -#endif /* _TSI108_H_ */
>
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-52 Fax: +49-8142-66989-80 Email: hs at denx.de
^ permalink raw reply [flat|nested] 8+ messages in thread
* [U-Boot] [PATCH 3/3] i2c: Drop CONFIG_SH_SH7734_I2C
2018-05-09 12:24 ` [U-Boot] [PATCH 3/3] i2c: Drop CONFIG_SH_SH7734_I2C Tuomas Tynkkynen
@ 2018-05-09 13:06 ` Heiko Schocher
2018-05-24 12:41 ` [U-Boot] [U-Boot,3/3] " Tom Rini
1 sibling, 0 replies; 8+ messages in thread
From: Heiko Schocher @ 2018-05-09 13:06 UTC (permalink / raw)
To: u-boot
Hello Tuomas,
Am 09.05.2018 um 14:24 schrieb Tuomas Tynkkynen:
> Last user of this driver went away in May 2017 in commit
> eb5ba3aefdf0f6c ("i2c: Drop use of CONFIG_I2C_HARD").
>
> Signed-off-by: Tuomas Tynkkynen <tuomas@tuxera.com>
> ---
> doc/driver-model/i2c-howto.txt | 1 -
> drivers/i2c/Makefile | 1 -
> drivers/i2c/sh_sh7734_i2c.c | 376 -----------------------------------------
> 3 files changed, 378 deletions(-)
> delete mode 100644 drivers/i2c/sh_sh7734_i2c.c
Thanks!
Acked-by: Heiko Schocher <hs@denx.de>
bye,
Heiko
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-52 Fax: +49-8142-66989-80 Email: hs at denx.de
^ permalink raw reply [flat|nested] 8+ messages in thread
* [U-Boot] [U-Boot,1/3] net: Drop CONFIG_TSI108_ETH
2018-05-09 12:24 [U-Boot] [PATCH 1/3] net: Drop CONFIG_TSI108_ETH Tuomas Tynkkynen
2018-05-09 12:24 ` [U-Boot] [PATCH 2/3] i2c: Drop CONFIG_TSI108_I2C Tuomas Tynkkynen
2018-05-09 12:24 ` [U-Boot] [PATCH 3/3] i2c: Drop CONFIG_SH_SH7734_I2C Tuomas Tynkkynen
@ 2018-05-24 12:41 ` Tom Rini
2 siblings, 0 replies; 8+ messages in thread
From: Tom Rini @ 2018-05-24 12:41 UTC (permalink / raw)
To: u-boot
On Wed, May 09, 2018 at 03:24:33PM +0300, Tuomas Tynkkynen wrote:
> Last user of this driver went away in June 2015 in commit
> d928664f4101e24 ("powerpc: 74xx_7xx: remove 74xx_7xx cpu support")
>
> Signed-off-by: Tuomas Tynkkynen <tuomas@tuxera.com>
Applied to u-boot/master, thanks!
--
Tom
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^ permalink raw reply [flat|nested] 8+ messages in thread
* [U-Boot] [U-Boot,2/3] i2c: Drop CONFIG_TSI108_I2C
2018-05-09 12:24 ` [U-Boot] [PATCH 2/3] i2c: Drop CONFIG_TSI108_I2C Tuomas Tynkkynen
2018-05-09 13:05 ` Heiko Schocher
@ 2018-05-24 12:41 ` Tom Rini
1 sibling, 0 replies; 8+ messages in thread
From: Tom Rini @ 2018-05-24 12:41 UTC (permalink / raw)
To: u-boot
On Wed, May 09, 2018 at 03:24:34PM +0300, Tuomas Tynkkynen wrote:
> Last user of this driver went away in June 2015 in commit
> d928664f4101e24 ("powerpc: 74xx_7xx: remove 74xx_7xx cpu support")
>
> Signed-off-by: Tuomas Tynkkynen <tuomas@tuxera.com>
> Acked-by: Heiko Schocher <hs@denx.de>
Applied to u-boot/master, thanks!
--
Tom
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^ permalink raw reply [flat|nested] 8+ messages in thread
* [U-Boot] [U-Boot,3/3] i2c: Drop CONFIG_SH_SH7734_I2C
2018-05-09 12:24 ` [U-Boot] [PATCH 3/3] i2c: Drop CONFIG_SH_SH7734_I2C Tuomas Tynkkynen
2018-05-09 13:06 ` Heiko Schocher
@ 2018-05-24 12:41 ` Tom Rini
1 sibling, 0 replies; 8+ messages in thread
From: Tom Rini @ 2018-05-24 12:41 UTC (permalink / raw)
To: u-boot
On Wed, May 09, 2018 at 03:24:35PM +0300, Tuomas Tynkkynen wrote:
> Last user of this driver went away in May 2017 in commit
> eb5ba3aefdf0f6c ("i2c: Drop use of CONFIG_I2C_HARD").
>
> Signed-off-by: Tuomas Tynkkynen <tuomas@tuxera.com>
> Acked-by: Heiko Schocher <hs@denx.de>
Applied to u-boot/master, thanks!
--
Tom
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^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2018-05-24 12:41 UTC | newest]
Thread overview: 8+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2018-05-09 12:24 [U-Boot] [PATCH 1/3] net: Drop CONFIG_TSI108_ETH Tuomas Tynkkynen
2018-05-09 12:24 ` [U-Boot] [PATCH 2/3] i2c: Drop CONFIG_TSI108_I2C Tuomas Tynkkynen
2018-05-09 13:05 ` Heiko Schocher
2018-05-24 12:41 ` [U-Boot] [U-Boot,2/3] " Tom Rini
2018-05-09 12:24 ` [U-Boot] [PATCH 3/3] i2c: Drop CONFIG_SH_SH7734_I2C Tuomas Tynkkynen
2018-05-09 13:06 ` Heiko Schocher
2018-05-24 12:41 ` [U-Boot] [U-Boot,3/3] " Tom Rini
2018-05-24 12:41 ` [U-Boot] [U-Boot,1/3] net: Drop CONFIG_TSI108_ETH Tom Rini
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