From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
To: Varshini Rajendran <varshini.rajendran@microchip.com>,
tglx@linutronix.de, maz@kernel.org, robh+dt@kernel.org,
krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org,
nicolas.ferre@microchip.com, alexandre.belloni@bootlin.com,
claudiu.beznea@microchip.com, davem@davemloft.net,
edumazet@google.com, kuba@kernel.org, pabeni@redhat.com,
gregkh@linuxfoundation.org, linux@armlinux.org.uk,
mturquette@baylibre.com, sboyd@kernel.org, sre@kernel.org,
broonie@kernel.org, arnd@arndb.de, gregory.clement@bootlin.com,
sudeep.holla@arm.com, balamanikandan.gunasundar@microchip.com,
mihai.sain@microchip.com, linux-kernel@vger.kernel.org,
devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
netdev@vger.kernel.org, linux-usb@vger.kernel.org,
linux-clk@vger.kernel.org, linux-pm@vger.kernel.org
Cc: Hari.PrasathGE@microchip.com, cristian.birsan@microchip.com,
durai.manickamkr@microchip.com, manikandan.m@microchip.com,
dharma.b@microchip.com, nayabbasha.sayed@microchip.com,
balakrishnan.s@microchip.com
Subject: Re: [PATCH 04/21] ARM: dts: at91: sam9x7: add device tree for soc
Date: Mon, 5 Jun 2023 08:39:54 +0200 [thread overview]
Message-ID: <939efed2-521b-baef-2776-7bf937efe3ff@linaro.org> (raw)
In-Reply-To: <20230603200243.243878-5-varshini.rajendran@microchip.com>
On 03/06/2023 22:02, Varshini Rajendran wrote:
> Add device tree file for SAM9X7 SoC family
>
> Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
> [nicolas.ferre@microchip.com: add support for gmac to sam9x7]
> Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
> [balamanikandan.gunasundar@microchip.com: Add device node csi2host and isc]
> Signed-off-by: Balamanikandan Gunasundar <balamanikandan.gunasundar@microchip.com>
> ---
> arch/arm/boot/dts/sam9x7.dtsi | 1333 +++++++++++++++++++++++++++++++++
> 1 file changed, 1333 insertions(+)
> create mode 100644 arch/arm/boot/dts/sam9x7.dtsi
>
> diff --git a/arch/arm/boot/dts/sam9x7.dtsi b/arch/arm/boot/dts/sam9x7.dtsi
> new file mode 100644
> index 000000000000..f98160182fe6
> --- /dev/null
> +++ b/arch/arm/boot/dts/sam9x7.dtsi
> @@ -0,0 +1,1333 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * sam9x7.dtsi - Device Tree Include file for Microchip SAM9X7 SoC family
> + *
> + * Copyright (C) 2022 Microchip Technology Inc. and its subsidiaries
> + *
> + * Author: Varshini Rajendran <varshini.rajendran@microchip.com>
> + */
> +
> +#include <dt-bindings/clock/at91.h>
> +#include <dt-bindings/dma/at91.h>
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/interrupt-controller/irq.h>
> +#include <dt-bindings/mfd/atmel-flexcom.h>
> +#include <dt-bindings/pinctrl/at91.h>
> +
> +/ {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + model = "Microchip SAM9X7 SoC";
> + compatible = "microchip,sam9x7";
> + interrupt-parent = <&aic>;
> +
> + aliases {
> + serial0 = &dbgu;
> + gpio0 = &pioA;
> + gpio1 = &pioB;
> + gpio2 = &pioC;
> + gpio3 = &pioD;
> + };
> +
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + cpu@0 {
> + compatible = "arm,arm926ej-s";
> + device_type = "cpu";
> + reg = <0>;
> + };
> + };
> +
> + clocks {
> + slow_xtal: slow_xtal {
No underscores in node names. Use some common prefix or suffix, e.g. clock-
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + };
> +
> + main_xtal: main_xtal {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + };
> + };
> +
> + sram: sram@300000 {
> + compatible = "mmio-sram";
> + reg = <0x300000 0x10000>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges = <0 0x300000 0x10000>;
> + };
> +
> + ahb {
> + compatible = "simple-bus";
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges;
> +
> + usb0: gadget@500000 {
> + compatible = "microchip,sam9x60-udc";
Aren't you missing specific compatible? This applies everywhere.
> + reg = <0x500000 0x100000>,
> + <0xf803c000 0x400>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + interrupts = <23 IRQ_TYPE_LEVEL_HIGH 2>;
> + clocks = <&pmc PMC_TYPE_PERIPHERAL 23>, <&pmc PMC_TYPE_CORE PMC_UTMI>;
> + clock-names = "pclk", "hclk";
> + assigned-clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>;
> + assigned-clock-rates = <480000000>;
> + status = "disabled";
> + };
> +
> + ohci0: usb@600000 {
> + compatible = "atmel,at91rm9200-ohci", "usb-ohci";
> + reg = <0x600000 0x100000>;
> + interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>;
> + clocks = <&pmc PMC_TYPE_PERIPHERAL 22>, <&pmc PMC_TYPE_PERIPHERAL 22>, <&pmc PMC_TYPE_SYSTEM 6>;
> + clock-names = "ohci_clk", "hclk", "uhpck";
> + status = "disabled";
> + };
> +
> + ehci0: usb@700000 {
> + compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
> + reg = <0x700000 0x100000>;
> + interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>;
> + clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>, <&pmc PMC_TYPE_PERIPHERAL 22>;
> + clock-names = "usb_clk", "ehci_clk";
> + assigned-clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>;
> + assigned-clock-rates = <480000000>;
> + status = "disabled";
> + };
> +
> + sdmmc0: sdio-host@80000000 {
Are you sure you have no dtbs_check warnings for this?
> + compatible = "microchip,sam9x60-sdhci";
> + reg = <0x80000000 0x300>;
> + interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>;
> + clocks = <&pmc PMC_TYPE_PERIPHERAL 12>, <&pmc PMC_TYPE_GCK 12>;
> + clock-names = "hclock", "multclk";
> + assigned-clocks = <&pmc PMC_TYPE_GCK 12>;
> + assigned-clock-rates = <100000000>;
> + status = "disabled";
> + };
> +
> + sdmmc1: sdio-host@90000000 {
> + compatible = "microchip,sam9x60-sdhci";
> + reg = <0x90000000 0x300>;
> + interrupts = <26 IRQ_TYPE_LEVEL_HIGH 0>;
> + clocks = <&pmc PMC_TYPE_PERIPHERAL 26>, <&pmc PMC_TYPE_GCK 26>;
> + clock-names = "hclock", "multclk";
> + assigned-clocks = <&pmc PMC_TYPE_GCK 26>;
> + assigned-clock-rates = <100000000>;
> + status = "disabled";
> + };
> + };
> +
> + apb {
> + compatible = "simple-bus";
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges;
> +
> + flx4: flexcom@f0000000 {
> + compatible = "atmel,sama5d2-flexcom";
> + reg = <0xf0000000 0x200>;
> + clocks = <&pmc PMC_TYPE_PERIPHERAL 13>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges = <0x0 0xf0000000 0x800>;
> + status = "disabled";
> +
> + uart4: serial@200 {
> + compatible = "microchip,sam9x60-usart", "atmel,at91sam9260-usart";
> + reg = <0x200 0x200>;
> + interrupts = <13 IRQ_TYPE_LEVEL_HIGH 7>;
> + dmas = <&dma0
> + (AT91_XDMAC_DT_MEM_IF(0) |
> + AT91_XDMAC_DT_PER_IF(1) |
> + AT91_XDMAC_DT_PERID(8))>,
> + <&dma0
> + (AT91_XDMAC_DT_MEM_IF(0) |
> + AT91_XDMAC_DT_PER_IF(1) |
> + AT91_XDMAC_DT_PERID(9))>;
> + dma-names = "tx", "rx";
> + clocks = <&pmc PMC_TYPE_PERIPHERAL 13>;
> + clock-names = "usart";
> + atmel,use-dma-rx;
> + atmel,use-dma-tx;
> + atmel,fifo-size = <16>;
> + status = "disabled";
> + };
> +
> + spi4: spi@400 {
> + compatible = "microchip,sam9x60-spi", "atmel,at91rm9200-spi";
> + reg = <0x400 0x200>;
> + interrupts = <13 IRQ_TYPE_LEVEL_HIGH 7>;
> + clocks = <&pmc PMC_TYPE_PERIPHERAL 13>;
> + clock-names = "spi_clk";
> + dmas = <&dma0
> + (AT91_XDMAC_DT_MEM_IF(0) |
> + AT91_XDMAC_DT_PER_IF(1) |
> + AT91_XDMAC_DT_PERID(8))>,
> + <&dma0
> + (AT91_XDMAC_DT_MEM_IF(0) |
> + AT91_XDMAC_DT_PER_IF(1) |
> + AT91_XDMAC_DT_PERID(9))>;
> + dma-names = "tx", "rx";
> + atmel,fifo-size = <16>;
> + status = "disabled";
> + };
> +
> + i2c4: i2c@600 {
> + compatible = "microchip,sam9x60-i2c";
> + reg = <0x600 0x200>;
> + interrupts = <13 IRQ_TYPE_LEVEL_HIGH 7>;
> + clocks = <&pmc PMC_TYPE_PERIPHERAL 13>;
> + dmas = <&dma0
> + (AT91_XDMAC_DT_MEM_IF(0) |
> + AT91_XDMAC_DT_PER_IF(1) |
> + AT91_XDMAC_DT_PERID(8))>,
> + <&dma0
> + (AT91_XDMAC_DT_MEM_IF(0) |
> + AT91_XDMAC_DT_PER_IF(1) |
> + AT91_XDMAC_DT_PERID(9))>;
> + dma-names = "tx", "rx";
> + atmel,fifo-size = <16>;
> + status = "disabled";
> + };
> + };
> +
> + flx5: flexcom@f0004000 {
> + compatible = "atmel,sama5d2-flexcom";
> + reg = <0xf0004000 0x200>;
> + clocks = <&pmc PMC_TYPE_PERIPHERAL 14>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges = <0x0 0xf0004000 0x800>;
> + status = "disabled";
> +
> + uart5: serial@200 {
> + compatible = "microchip,sam9x60-usart", "atmel,at91sam9260-usart";
> + reg = <0x200 0x200>;
> + interrupts = <14 IRQ_TYPE_LEVEL_HIGH 7>;
> + dmas = <&dma0
> + (AT91_XDMAC_DT_MEM_IF(0) |
> + AT91_XDMAC_DT_PER_IF(1) |
> + AT91_XDMAC_DT_PERID(10))>,
> + <&dma0
> + (AT91_XDMAC_DT_MEM_IF(0) |
> + AT91_XDMAC_DT_PER_IF(1) |
> + AT91_XDMAC_DT_PERID(11))>;
> + dma-names = "tx", "rx";
> + clocks = <&pmc PMC_TYPE_PERIPHERAL 14>;
> + clock-names = "usart";
> + atmel,use-dma-rx;
> + atmel,use-dma-tx;
> + atmel,fifo-size = <16>;
> + status = "disabled";
> + };
> +
> + spi5: spi@400 {
> + compatible = "microchip,sam9x60-spi", "atmel,at91rm9200-spi";
> + reg = <0x400 0x200>;
> + interrupts = <14 IRQ_TYPE_LEVEL_HIGH 7>;
> + clocks = <&pmc PMC_TYPE_PERIPHERAL 14>;
> + clock-names = "spi_clk";
> + dmas = <&dma0
> + (AT91_XDMAC_DT_MEM_IF(0) |
> + AT91_XDMAC_DT_PER_IF(1) |
> + AT91_XDMAC_DT_PERID(10))>,
> + <&dma0
> + (AT91_XDMAC_DT_MEM_IF(0) |
> + AT91_XDMAC_DT_PER_IF(1) |
> + AT91_XDMAC_DT_PERID(11))>;
> + dma-names = "tx", "rx";
> + atmel,fifo-size = <16>;
> + status = "disabled";
> + };
> +
> + i2c5: i2c@600 {
> + compatible = "microchip,sam9x60-i2c";
> + reg = <0x600 0x200>;
> + interrupts = <14 IRQ_TYPE_LEVEL_HIGH 7>;
> + clocks = <&pmc PMC_TYPE_PERIPHERAL 14>;
> + dmas = <&dma0
> + (AT91_XDMAC_DT_MEM_IF(0) |
> + AT91_XDMAC_DT_PER_IF(1) |
> + AT91_XDMAC_DT_PERID(10))>,
> + <&dma0
> + (AT91_XDMAC_DT_MEM_IF(0) |
> + AT91_XDMAC_DT_PER_IF(1) |
> + AT91_XDMAC_DT_PERID(11))>;
> + dma-names = "tx", "rx";
> + atmel,fifo-size = <16>;
> + status = "disabled";
> + };
> + };
> +
> + dma0: dma-controller@f0008000 {
> + compatible = "microchip,sam9x60-dma", "atmel,sama5d4-dma";
> + reg = <0xf0008000 0x1000>;
> + interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>;
> + #dma-cells = <1>;
> + clocks = <&pmc PMC_TYPE_PERIPHERAL 20>;
> + clock-names = "dma_clk";
> + status = "disabled";
> + };
> +
> + ssc: ssc@f0010000 {
> + compatible = "atmel,at91sam9g45-ssc";
> + reg = <0xf0010000 0x4000>;
> + interrupts = <28 IRQ_TYPE_LEVEL_HIGH 5>;
> + dmas = <&dma0
> + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
> + AT91_XDMAC_DT_PERID(38))>,
> + <&dma0
> + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
> + AT91_XDMAC_DT_PERID(39))>;
> + dma-names = "tx", "rx";
> + clocks = <&pmc PMC_TYPE_PERIPHERAL 28>;
> + clock-names = "pclk";
> + };
> +
> + gpu: gfx2d@f0018000 {
> + compatible = "microchip,sam9x60-gfx2d";
> + reg = <0xf0018000 0x4000>;
> + interrupts = <36 IRQ_TYPE_LEVEL_HIGH 0>;
> + clocks = <&pmc PMC_TYPE_PERIPHERAL 36>;
> + clock-names = "periph_clk";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "disabled";
> + };
> +
> + i2s: i2s@f001c000 {
> + compatible = "microchip,sam9x60-i2smcc";
> + reg = <0xf001c000 0x100>;
> + interrupts = <34 IRQ_TYPE_LEVEL_HIGH 7>;
> + dmas = <&dma0
> + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
> + AT91_XDMAC_DT_PERID(36))>,
> + <&dma0
> + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
> + AT91_XDMAC_DT_PERID(37))>;
> + dma-names = "tx", "rx";
> + clocks = <&pmc PMC_TYPE_PERIPHERAL 34>, <&pmc PMC_TYPE_GCK 34>;
> + clock-names = "pclk", "gclk";
> + status = "disabled";
> + };
> +
> + flx11: flexcom@f0020000 {
> + compatible = "atmel,sama5d2-flexcom";
> + reg = <0xf0020000 0x200>;
> + clocks = <&pmc PMC_TYPE_PERIPHERAL 32>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges = <0x0 0xf0020000 0x800>;
> + status = "disabled";
> +
> + uart11: serial@200 {
> + compatible = "microchip,sam9x60-usart", "atmel,at91sam9260-usart";
> + reg = <0x200 0x200>;
> + interrupts = <32 IRQ_TYPE_LEVEL_HIGH 7>;
> + dmas = <&dma0
> + (AT91_XDMAC_DT_MEM_IF(0) |
> + AT91_XDMAC_DT_PER_IF(1) |
> + AT91_XDMAC_DT_PERID(22))>,
> + <&dma0
> + (AT91_XDMAC_DT_MEM_IF(0) |
> + AT91_XDMAC_DT_PER_IF(1) |
> + AT91_XDMAC_DT_PERID(23))>;
> + dma-names = "tx", "rx";
> + clocks = <&pmc PMC_TYPE_PERIPHERAL 32>;
> + clock-names = "usart";
> + atmel,use-dma-rx;
> + atmel,use-dma-tx;
> + atmel,fifo-size = <16>;
> + status = "disabled";
> + };
> +
> + i2c11: i2c@600 {
> + compatible = "microchip,sam9x60-i2c";
> + reg = <0x600 0x200>;
> + interrupts = <32 IRQ_TYPE_LEVEL_HIGH 7>;
> + clocks = <&pmc PMC_TYPE_PERIPHERAL 32>;
> + dmas = <&dma0
> + (AT91_XDMAC_DT_MEM_IF(0) |
> + AT91_XDMAC_DT_PER_IF(1) |
> + AT91_XDMAC_DT_PERID(22))>,
> + <&dma0
> + (AT91_XDMAC_DT_MEM_IF(0) |
> + AT91_XDMAC_DT_PER_IF(1) |
> + AT91_XDMAC_DT_PERID(23))>;
> + dma-names = "tx", "rx";
> + atmel,fifo-size = <16>;
> + status = "disabled";
> + };
> + };
> +
> + flx12: flexcom@f0024000 {
> + compatible = "atmel,sama5d2-flexcom";
> + reg = <0xf0024000 0x200>;
> + clocks = <&pmc PMC_TYPE_PERIPHERAL 33>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges = <0x0 0xf0024000 0x800>;
> + status = "disabled";
> +
> + uart12: serial@200 {
> + compatible = "microchip,sam9x60-usart", "atmel,at91sam9260-usart";
> + reg = <0x200 0x200>;
> + interrupts = <33 IRQ_TYPE_LEVEL_HIGH 7>;
> + dmas = <&dma0
> + (AT91_XDMAC_DT_MEM_IF(0) |
> + AT91_XDMAC_DT_PER_IF(1) |
> + AT91_XDMAC_DT_PERID(24))>,
> + <&dma0
> + (AT91_XDMAC_DT_MEM_IF(0) |
> + AT91_XDMAC_DT_PER_IF(1) |
> + AT91_XDMAC_DT_PERID(25))>;
> + dma-names = "tx", "rx";
> + clocks = <&pmc PMC_TYPE_PERIPHERAL 33>;
> + clock-names = "usart";
> + atmel,use-dma-rx;
> + atmel,use-dma-tx;
> + atmel,fifo-size = <16>;
> + status = "disabled";
> + };
> +
> + i2c12: i2c@600 {
> + compatible = "microchip,sam9x60-i2c";
> + reg = <0x600 0x200>;
> + interrupts = <33 IRQ_TYPE_LEVEL_HIGH 7>;
> + clocks = <&pmc PMC_TYPE_PERIPHERAL 33>;
> + dmas = <&dma0
> + (AT91_XDMAC_DT_MEM_IF(0) |
> + AT91_XDMAC_DT_PER_IF(1) |
> + AT91_XDMAC_DT_PERID(24))>,
> + <&dma0
> + (AT91_XDMAC_DT_MEM_IF(0) |
> + AT91_XDMAC_DT_PER_IF(1) |
> + AT91_XDMAC_DT_PERID(25))>;
> + dma-names = "tx", "rx";
> + atmel,fifo-size = <16>;
> + status = "disabled";
> + };
> + };
> +
> + pit64b0: timer@f0028000 {
> + compatible = "microchip,sam9x60-pit64b";
> + reg = <0xf0028000 0x100>;
> + interrupts = <37 IRQ_TYPE_LEVEL_HIGH 7>;
> + clocks = <&pmc PMC_TYPE_PERIPHERAL 37>, <&pmc PMC_TYPE_GCK 37>;
> + clock-names = "pclk", "gclk";
> + };
> +
> + sha: sha@f002c000 {
> + compatible = "atmel,at91sam9g46-sha";
> + reg = <0xf002c000 0x100>;
> + interrupts = <41 IRQ_TYPE_LEVEL_HIGH 0>;
> + dmas = <&dma0
> + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
> + AT91_XDMAC_DT_PERID(34))>;
> + dma-names = "tx";
> + clocks = <&pmc PMC_TYPE_PERIPHERAL 41>;
> + clock-names = "sha_clk";
> + };
> +
> + trng: trng@f0030000 {
rng@
> + compatible = "microchip,sam9x60-trng";
> + reg = <0xf0030000 0x100>;
> + interrupts = <38 IRQ_TYPE_LEVEL_HIGH 0>;
> + clocks = <&pmc PMC_TYPE_PERIPHERAL 38>;
> + status = "disabled";
> + };
> +
> + aes: aes@f0034000 {
crypto@
> + compatible = "atmel,at91sam9g46-aes";
> + reg = <0xf0034000 0x100>;
> + interrupts = <39 IRQ_TYPE_LEVEL_HIGH 0>;
> + dmas = <&dma0
> + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
> + AT91_XDMAC_DT_PERID(32))>,
> + <&dma0
> + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
> + AT91_XDMAC_DT_PERID(33))>;
> + dma-names = "tx", "rx";
> + clocks = <&pmc PMC_TYPE_PERIPHERAL 39>;
> + clock-names = "aes_clk";
> + };
> +
> + tdes: tdes@f0038000 {
crypto@
Best regards,
Krzysztof
WARNING: multiple messages have this Message-ID (diff)
From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
To: Varshini Rajendran <varshini.rajendran@microchip.com>,
tglx@linutronix.de, maz@kernel.org, robh+dt@kernel.org,
krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org,
nicolas.ferre@microchip.com, alexandre.belloni@bootlin.com,
claudiu.beznea@microchip.com, davem@davemloft.net,
edumazet@google.com, kuba@kernel.org, pabeni@redhat.com,
gregkh@linuxfoundation.org, linux@armlinux.org.uk,
mturquette@baylibre.com, sboyd@kernel.org, sre@kernel.org,
broonie@kernel.org, arnd@arndb.de, gregory.clement@bootlin.com,
sudeep.holla@arm.com, balamanikandan.gunasundar@microchip.com,
mihai.sain@microchip.com, linux-kernel@vger.kernel.org,
devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
netdev@vger.kernel.org, linux-usb@vger.kernel.org,
linux-clk@vger.kernel.org, linux-pm@vger.kernel.org
Cc: Hari.PrasathGE@microchip.com, cristian.birsan@microchip.com,
durai.manickamkr@microchip.com, manikandan.m@microchip.com,
dharma.b@microchip.com, nayabbasha.sayed@microchip.com,
balakrishnan.s@microchip.com
Subject: Re: [PATCH 04/21] ARM: dts: at91: sam9x7: add device tree for soc
Date: Mon, 5 Jun 2023 08:39:54 +0200 [thread overview]
Message-ID: <939efed2-521b-baef-2776-7bf937efe3ff@linaro.org> (raw)
In-Reply-To: <20230603200243.243878-5-varshini.rajendran@microchip.com>
On 03/06/2023 22:02, Varshini Rajendran wrote:
> Add device tree file for SAM9X7 SoC family
>
> Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
> [nicolas.ferre@microchip.com: add support for gmac to sam9x7]
> Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
> [balamanikandan.gunasundar@microchip.com: Add device node csi2host and isc]
> Signed-off-by: Balamanikandan Gunasundar <balamanikandan.gunasundar@microchip.com>
> ---
> arch/arm/boot/dts/sam9x7.dtsi | 1333 +++++++++++++++++++++++++++++++++
> 1 file changed, 1333 insertions(+)
> create mode 100644 arch/arm/boot/dts/sam9x7.dtsi
>
> diff --git a/arch/arm/boot/dts/sam9x7.dtsi b/arch/arm/boot/dts/sam9x7.dtsi
> new file mode 100644
> index 000000000000..f98160182fe6
> --- /dev/null
> +++ b/arch/arm/boot/dts/sam9x7.dtsi
> @@ -0,0 +1,1333 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * sam9x7.dtsi - Device Tree Include file for Microchip SAM9X7 SoC family
> + *
> + * Copyright (C) 2022 Microchip Technology Inc. and its subsidiaries
> + *
> + * Author: Varshini Rajendran <varshini.rajendran@microchip.com>
> + */
> +
> +#include <dt-bindings/clock/at91.h>
> +#include <dt-bindings/dma/at91.h>
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/interrupt-controller/irq.h>
> +#include <dt-bindings/mfd/atmel-flexcom.h>
> +#include <dt-bindings/pinctrl/at91.h>
> +
> +/ {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + model = "Microchip SAM9X7 SoC";
> + compatible = "microchip,sam9x7";
> + interrupt-parent = <&aic>;
> +
> + aliases {
> + serial0 = &dbgu;
> + gpio0 = &pioA;
> + gpio1 = &pioB;
> + gpio2 = &pioC;
> + gpio3 = &pioD;
> + };
> +
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + cpu@0 {
> + compatible = "arm,arm926ej-s";
> + device_type = "cpu";
> + reg = <0>;
> + };
> + };
> +
> + clocks {
> + slow_xtal: slow_xtal {
No underscores in node names. Use some common prefix or suffix, e.g. clock-
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + };
> +
> + main_xtal: main_xtal {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + };
> + };
> +
> + sram: sram@300000 {
> + compatible = "mmio-sram";
> + reg = <0x300000 0x10000>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges = <0 0x300000 0x10000>;
> + };
> +
> + ahb {
> + compatible = "simple-bus";
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges;
> +
> + usb0: gadget@500000 {
> + compatible = "microchip,sam9x60-udc";
Aren't you missing specific compatible? This applies everywhere.
> + reg = <0x500000 0x100000>,
> + <0xf803c000 0x400>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + interrupts = <23 IRQ_TYPE_LEVEL_HIGH 2>;
> + clocks = <&pmc PMC_TYPE_PERIPHERAL 23>, <&pmc PMC_TYPE_CORE PMC_UTMI>;
> + clock-names = "pclk", "hclk";
> + assigned-clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>;
> + assigned-clock-rates = <480000000>;
> + status = "disabled";
> + };
> +
> + ohci0: usb@600000 {
> + compatible = "atmel,at91rm9200-ohci", "usb-ohci";
> + reg = <0x600000 0x100000>;
> + interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>;
> + clocks = <&pmc PMC_TYPE_PERIPHERAL 22>, <&pmc PMC_TYPE_PERIPHERAL 22>, <&pmc PMC_TYPE_SYSTEM 6>;
> + clock-names = "ohci_clk", "hclk", "uhpck";
> + status = "disabled";
> + };
> +
> + ehci0: usb@700000 {
> + compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
> + reg = <0x700000 0x100000>;
> + interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>;
> + clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>, <&pmc PMC_TYPE_PERIPHERAL 22>;
> + clock-names = "usb_clk", "ehci_clk";
> + assigned-clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>;
> + assigned-clock-rates = <480000000>;
> + status = "disabled";
> + };
> +
> + sdmmc0: sdio-host@80000000 {
Are you sure you have no dtbs_check warnings for this?
> + compatible = "microchip,sam9x60-sdhci";
> + reg = <0x80000000 0x300>;
> + interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>;
> + clocks = <&pmc PMC_TYPE_PERIPHERAL 12>, <&pmc PMC_TYPE_GCK 12>;
> + clock-names = "hclock", "multclk";
> + assigned-clocks = <&pmc PMC_TYPE_GCK 12>;
> + assigned-clock-rates = <100000000>;
> + status = "disabled";
> + };
> +
> + sdmmc1: sdio-host@90000000 {
> + compatible = "microchip,sam9x60-sdhci";
> + reg = <0x90000000 0x300>;
> + interrupts = <26 IRQ_TYPE_LEVEL_HIGH 0>;
> + clocks = <&pmc PMC_TYPE_PERIPHERAL 26>, <&pmc PMC_TYPE_GCK 26>;
> + clock-names = "hclock", "multclk";
> + assigned-clocks = <&pmc PMC_TYPE_GCK 26>;
> + assigned-clock-rates = <100000000>;
> + status = "disabled";
> + };
> + };
> +
> + apb {
> + compatible = "simple-bus";
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges;
> +
> + flx4: flexcom@f0000000 {
> + compatible = "atmel,sama5d2-flexcom";
> + reg = <0xf0000000 0x200>;
> + clocks = <&pmc PMC_TYPE_PERIPHERAL 13>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges = <0x0 0xf0000000 0x800>;
> + status = "disabled";
> +
> + uart4: serial@200 {
> + compatible = "microchip,sam9x60-usart", "atmel,at91sam9260-usart";
> + reg = <0x200 0x200>;
> + interrupts = <13 IRQ_TYPE_LEVEL_HIGH 7>;
> + dmas = <&dma0
> + (AT91_XDMAC_DT_MEM_IF(0) |
> + AT91_XDMAC_DT_PER_IF(1) |
> + AT91_XDMAC_DT_PERID(8))>,
> + <&dma0
> + (AT91_XDMAC_DT_MEM_IF(0) |
> + AT91_XDMAC_DT_PER_IF(1) |
> + AT91_XDMAC_DT_PERID(9))>;
> + dma-names = "tx", "rx";
> + clocks = <&pmc PMC_TYPE_PERIPHERAL 13>;
> + clock-names = "usart";
> + atmel,use-dma-rx;
> + atmel,use-dma-tx;
> + atmel,fifo-size = <16>;
> + status = "disabled";
> + };
> +
> + spi4: spi@400 {
> + compatible = "microchip,sam9x60-spi", "atmel,at91rm9200-spi";
> + reg = <0x400 0x200>;
> + interrupts = <13 IRQ_TYPE_LEVEL_HIGH 7>;
> + clocks = <&pmc PMC_TYPE_PERIPHERAL 13>;
> + clock-names = "spi_clk";
> + dmas = <&dma0
> + (AT91_XDMAC_DT_MEM_IF(0) |
> + AT91_XDMAC_DT_PER_IF(1) |
> + AT91_XDMAC_DT_PERID(8))>,
> + <&dma0
> + (AT91_XDMAC_DT_MEM_IF(0) |
> + AT91_XDMAC_DT_PER_IF(1) |
> + AT91_XDMAC_DT_PERID(9))>;
> + dma-names = "tx", "rx";
> + atmel,fifo-size = <16>;
> + status = "disabled";
> + };
> +
> + i2c4: i2c@600 {
> + compatible = "microchip,sam9x60-i2c";
> + reg = <0x600 0x200>;
> + interrupts = <13 IRQ_TYPE_LEVEL_HIGH 7>;
> + clocks = <&pmc PMC_TYPE_PERIPHERAL 13>;
> + dmas = <&dma0
> + (AT91_XDMAC_DT_MEM_IF(0) |
> + AT91_XDMAC_DT_PER_IF(1) |
> + AT91_XDMAC_DT_PERID(8))>,
> + <&dma0
> + (AT91_XDMAC_DT_MEM_IF(0) |
> + AT91_XDMAC_DT_PER_IF(1) |
> + AT91_XDMAC_DT_PERID(9))>;
> + dma-names = "tx", "rx";
> + atmel,fifo-size = <16>;
> + status = "disabled";
> + };
> + };
> +
> + flx5: flexcom@f0004000 {
> + compatible = "atmel,sama5d2-flexcom";
> + reg = <0xf0004000 0x200>;
> + clocks = <&pmc PMC_TYPE_PERIPHERAL 14>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges = <0x0 0xf0004000 0x800>;
> + status = "disabled";
> +
> + uart5: serial@200 {
> + compatible = "microchip,sam9x60-usart", "atmel,at91sam9260-usart";
> + reg = <0x200 0x200>;
> + interrupts = <14 IRQ_TYPE_LEVEL_HIGH 7>;
> + dmas = <&dma0
> + (AT91_XDMAC_DT_MEM_IF(0) |
> + AT91_XDMAC_DT_PER_IF(1) |
> + AT91_XDMAC_DT_PERID(10))>,
> + <&dma0
> + (AT91_XDMAC_DT_MEM_IF(0) |
> + AT91_XDMAC_DT_PER_IF(1) |
> + AT91_XDMAC_DT_PERID(11))>;
> + dma-names = "tx", "rx";
> + clocks = <&pmc PMC_TYPE_PERIPHERAL 14>;
> + clock-names = "usart";
> + atmel,use-dma-rx;
> + atmel,use-dma-tx;
> + atmel,fifo-size = <16>;
> + status = "disabled";
> + };
> +
> + spi5: spi@400 {
> + compatible = "microchip,sam9x60-spi", "atmel,at91rm9200-spi";
> + reg = <0x400 0x200>;
> + interrupts = <14 IRQ_TYPE_LEVEL_HIGH 7>;
> + clocks = <&pmc PMC_TYPE_PERIPHERAL 14>;
> + clock-names = "spi_clk";
> + dmas = <&dma0
> + (AT91_XDMAC_DT_MEM_IF(0) |
> + AT91_XDMAC_DT_PER_IF(1) |
> + AT91_XDMAC_DT_PERID(10))>,
> + <&dma0
> + (AT91_XDMAC_DT_MEM_IF(0) |
> + AT91_XDMAC_DT_PER_IF(1) |
> + AT91_XDMAC_DT_PERID(11))>;
> + dma-names = "tx", "rx";
> + atmel,fifo-size = <16>;
> + status = "disabled";
> + };
> +
> + i2c5: i2c@600 {
> + compatible = "microchip,sam9x60-i2c";
> + reg = <0x600 0x200>;
> + interrupts = <14 IRQ_TYPE_LEVEL_HIGH 7>;
> + clocks = <&pmc PMC_TYPE_PERIPHERAL 14>;
> + dmas = <&dma0
> + (AT91_XDMAC_DT_MEM_IF(0) |
> + AT91_XDMAC_DT_PER_IF(1) |
> + AT91_XDMAC_DT_PERID(10))>,
> + <&dma0
> + (AT91_XDMAC_DT_MEM_IF(0) |
> + AT91_XDMAC_DT_PER_IF(1) |
> + AT91_XDMAC_DT_PERID(11))>;
> + dma-names = "tx", "rx";
> + atmel,fifo-size = <16>;
> + status = "disabled";
> + };
> + };
> +
> + dma0: dma-controller@f0008000 {
> + compatible = "microchip,sam9x60-dma", "atmel,sama5d4-dma";
> + reg = <0xf0008000 0x1000>;
> + interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>;
> + #dma-cells = <1>;
> + clocks = <&pmc PMC_TYPE_PERIPHERAL 20>;
> + clock-names = "dma_clk";
> + status = "disabled";
> + };
> +
> + ssc: ssc@f0010000 {
> + compatible = "atmel,at91sam9g45-ssc";
> + reg = <0xf0010000 0x4000>;
> + interrupts = <28 IRQ_TYPE_LEVEL_HIGH 5>;
> + dmas = <&dma0
> + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
> + AT91_XDMAC_DT_PERID(38))>,
> + <&dma0
> + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
> + AT91_XDMAC_DT_PERID(39))>;
> + dma-names = "tx", "rx";
> + clocks = <&pmc PMC_TYPE_PERIPHERAL 28>;
> + clock-names = "pclk";
> + };
> +
> + gpu: gfx2d@f0018000 {
> + compatible = "microchip,sam9x60-gfx2d";
> + reg = <0xf0018000 0x4000>;
> + interrupts = <36 IRQ_TYPE_LEVEL_HIGH 0>;
> + clocks = <&pmc PMC_TYPE_PERIPHERAL 36>;
> + clock-names = "periph_clk";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "disabled";
> + };
> +
> + i2s: i2s@f001c000 {
> + compatible = "microchip,sam9x60-i2smcc";
> + reg = <0xf001c000 0x100>;
> + interrupts = <34 IRQ_TYPE_LEVEL_HIGH 7>;
> + dmas = <&dma0
> + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
> + AT91_XDMAC_DT_PERID(36))>,
> + <&dma0
> + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
> + AT91_XDMAC_DT_PERID(37))>;
> + dma-names = "tx", "rx";
> + clocks = <&pmc PMC_TYPE_PERIPHERAL 34>, <&pmc PMC_TYPE_GCK 34>;
> + clock-names = "pclk", "gclk";
> + status = "disabled";
> + };
> +
> + flx11: flexcom@f0020000 {
> + compatible = "atmel,sama5d2-flexcom";
> + reg = <0xf0020000 0x200>;
> + clocks = <&pmc PMC_TYPE_PERIPHERAL 32>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges = <0x0 0xf0020000 0x800>;
> + status = "disabled";
> +
> + uart11: serial@200 {
> + compatible = "microchip,sam9x60-usart", "atmel,at91sam9260-usart";
> + reg = <0x200 0x200>;
> + interrupts = <32 IRQ_TYPE_LEVEL_HIGH 7>;
> + dmas = <&dma0
> + (AT91_XDMAC_DT_MEM_IF(0) |
> + AT91_XDMAC_DT_PER_IF(1) |
> + AT91_XDMAC_DT_PERID(22))>,
> + <&dma0
> + (AT91_XDMAC_DT_MEM_IF(0) |
> + AT91_XDMAC_DT_PER_IF(1) |
> + AT91_XDMAC_DT_PERID(23))>;
> + dma-names = "tx", "rx";
> + clocks = <&pmc PMC_TYPE_PERIPHERAL 32>;
> + clock-names = "usart";
> + atmel,use-dma-rx;
> + atmel,use-dma-tx;
> + atmel,fifo-size = <16>;
> + status = "disabled";
> + };
> +
> + i2c11: i2c@600 {
> + compatible = "microchip,sam9x60-i2c";
> + reg = <0x600 0x200>;
> + interrupts = <32 IRQ_TYPE_LEVEL_HIGH 7>;
> + clocks = <&pmc PMC_TYPE_PERIPHERAL 32>;
> + dmas = <&dma0
> + (AT91_XDMAC_DT_MEM_IF(0) |
> + AT91_XDMAC_DT_PER_IF(1) |
> + AT91_XDMAC_DT_PERID(22))>,
> + <&dma0
> + (AT91_XDMAC_DT_MEM_IF(0) |
> + AT91_XDMAC_DT_PER_IF(1) |
> + AT91_XDMAC_DT_PERID(23))>;
> + dma-names = "tx", "rx";
> + atmel,fifo-size = <16>;
> + status = "disabled";
> + };
> + };
> +
> + flx12: flexcom@f0024000 {
> + compatible = "atmel,sama5d2-flexcom";
> + reg = <0xf0024000 0x200>;
> + clocks = <&pmc PMC_TYPE_PERIPHERAL 33>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges = <0x0 0xf0024000 0x800>;
> + status = "disabled";
> +
> + uart12: serial@200 {
> + compatible = "microchip,sam9x60-usart", "atmel,at91sam9260-usart";
> + reg = <0x200 0x200>;
> + interrupts = <33 IRQ_TYPE_LEVEL_HIGH 7>;
> + dmas = <&dma0
> + (AT91_XDMAC_DT_MEM_IF(0) |
> + AT91_XDMAC_DT_PER_IF(1) |
> + AT91_XDMAC_DT_PERID(24))>,
> + <&dma0
> + (AT91_XDMAC_DT_MEM_IF(0) |
> + AT91_XDMAC_DT_PER_IF(1) |
> + AT91_XDMAC_DT_PERID(25))>;
> + dma-names = "tx", "rx";
> + clocks = <&pmc PMC_TYPE_PERIPHERAL 33>;
> + clock-names = "usart";
> + atmel,use-dma-rx;
> + atmel,use-dma-tx;
> + atmel,fifo-size = <16>;
> + status = "disabled";
> + };
> +
> + i2c12: i2c@600 {
> + compatible = "microchip,sam9x60-i2c";
> + reg = <0x600 0x200>;
> + interrupts = <33 IRQ_TYPE_LEVEL_HIGH 7>;
> + clocks = <&pmc PMC_TYPE_PERIPHERAL 33>;
> + dmas = <&dma0
> + (AT91_XDMAC_DT_MEM_IF(0) |
> + AT91_XDMAC_DT_PER_IF(1) |
> + AT91_XDMAC_DT_PERID(24))>,
> + <&dma0
> + (AT91_XDMAC_DT_MEM_IF(0) |
> + AT91_XDMAC_DT_PER_IF(1) |
> + AT91_XDMAC_DT_PERID(25))>;
> + dma-names = "tx", "rx";
> + atmel,fifo-size = <16>;
> + status = "disabled";
> + };
> + };
> +
> + pit64b0: timer@f0028000 {
> + compatible = "microchip,sam9x60-pit64b";
> + reg = <0xf0028000 0x100>;
> + interrupts = <37 IRQ_TYPE_LEVEL_HIGH 7>;
> + clocks = <&pmc PMC_TYPE_PERIPHERAL 37>, <&pmc PMC_TYPE_GCK 37>;
> + clock-names = "pclk", "gclk";
> + };
> +
> + sha: sha@f002c000 {
> + compatible = "atmel,at91sam9g46-sha";
> + reg = <0xf002c000 0x100>;
> + interrupts = <41 IRQ_TYPE_LEVEL_HIGH 0>;
> + dmas = <&dma0
> + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
> + AT91_XDMAC_DT_PERID(34))>;
> + dma-names = "tx";
> + clocks = <&pmc PMC_TYPE_PERIPHERAL 41>;
> + clock-names = "sha_clk";
> + };
> +
> + trng: trng@f0030000 {
rng@
> + compatible = "microchip,sam9x60-trng";
> + reg = <0xf0030000 0x100>;
> + interrupts = <38 IRQ_TYPE_LEVEL_HIGH 0>;
> + clocks = <&pmc PMC_TYPE_PERIPHERAL 38>;
> + status = "disabled";
> + };
> +
> + aes: aes@f0034000 {
crypto@
> + compatible = "atmel,at91sam9g46-aes";
> + reg = <0xf0034000 0x100>;
> + interrupts = <39 IRQ_TYPE_LEVEL_HIGH 0>;
> + dmas = <&dma0
> + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
> + AT91_XDMAC_DT_PERID(32))>,
> + <&dma0
> + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
> + AT91_XDMAC_DT_PERID(33))>;
> + dma-names = "tx", "rx";
> + clocks = <&pmc PMC_TYPE_PERIPHERAL 39>;
> + clock-names = "aes_clk";
> + };
> +
> + tdes: tdes@f0038000 {
crypto@
Best regards,
Krzysztof
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next prev parent reply other threads:[~2023-06-05 6:40 UTC|newest]
Thread overview: 122+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-06-03 20:02 [PATCH 00/21] Add support for sam9x7 SoC family Varshini Rajendran
2023-06-03 20:02 ` Varshini Rajendran
2023-06-03 20:02 ` [PATCH 01/21] dt-bindings: microchip: atmel,at91rm9200-tcb: add sam9x60 compatible Varshini Rajendran
2023-06-03 20:02 ` Varshini Rajendran
2023-06-05 6:35 ` Krzysztof Kozlowski
2023-06-05 6:35 ` Krzysztof Kozlowski
2023-06-05 7:04 ` Arnd Bergmann
2023-06-05 7:04 ` Arnd Bergmann
2023-06-05 7:34 ` Krzysztof Kozlowski
2023-06-05 7:34 ` Krzysztof Kozlowski
2023-06-05 12:03 ` Nicolas Ferre
2023-06-05 12:03 ` Nicolas Ferre
2023-06-14 19:37 ` Rob Herring
2023-06-14 19:37 ` Rob Herring
2023-06-03 20:02 ` [PATCH 02/21] dt-bindings: usb: ehci: Add atmel at91sam9g45-ehci compatible Varshini Rajendran
2023-06-03 20:02 ` Varshini Rajendran
2023-06-14 19:38 ` Rob Herring
2023-06-14 19:38 ` Rob Herring
2023-06-03 20:02 ` [PATCH 03/21] dt-bindings: usb: generic-ehci: Document clock-names property Varshini Rajendran
2023-06-03 20:02 ` Varshini Rajendran
2023-06-03 21:15 ` Conor Dooley
2023-06-03 21:15 ` Conor Dooley
2023-06-05 12:54 ` Nicolas Ferre
2023-06-05 12:54 ` Nicolas Ferre
2023-06-05 6:36 ` Krzysztof Kozlowski
2023-06-05 6:36 ` Krzysztof Kozlowski
2023-06-03 20:02 ` [PATCH 04/21] ARM: dts: at91: sam9x7: add device tree for soc Varshini Rajendran
2023-06-03 20:02 ` Varshini Rajendran
2023-06-03 21:35 ` Conor Dooley
2023-06-03 21:35 ` Conor Dooley
2023-06-05 6:39 ` Krzysztof Kozlowski [this message]
2023-06-05 6:39 ` Krzysztof Kozlowski
2023-06-05 6:41 ` Krzysztof Kozlowski
2023-06-05 6:41 ` Krzysztof Kozlowski
2023-06-09 5:35 ` Dharma.B
2023-06-09 5:35 ` Dharma.B
2023-06-15 7:36 ` Claudiu.Beznea
2023-06-15 7:36 ` Claudiu.Beznea
2023-06-03 20:02 ` [PATCH 05/21] ARM: configs: at91: enable config flags for sam9x7 SoC Varshini Rajendran
2023-06-03 20:02 ` Varshini Rajendran
2023-06-03 20:02 ` [PATCH 06/21] ARM: configs: at91: add mcan support Varshini Rajendran
2023-06-03 20:02 ` Varshini Rajendran
2023-06-05 6:40 ` Krzysztof Kozlowski
2023-06-05 6:40 ` Krzysztof Kozlowski
2023-06-03 20:02 ` [PATCH 07/21] ARM: configs: at91: Enable csi and isc support Varshini Rajendran
2023-06-03 20:02 ` Varshini Rajendran
2023-06-03 20:02 ` [PATCH 08/21] ARM: at91: pm: add support for sam9x7 soc family Varshini Rajendran
2023-06-03 20:02 ` Varshini Rajendran
2023-06-15 7:42 ` Claudiu.Beznea
2023-06-15 7:42 ` Claudiu.Beznea
2023-06-03 20:02 ` [PATCH 09/21] ARM: at91: pm: add sam9x7 soc init config Varshini Rajendran
2023-06-03 20:02 ` Varshini Rajendran
2023-06-15 7:43 ` Claudiu.Beznea
2023-06-15 7:43 ` Claudiu.Beznea
2023-06-03 20:02 ` [PATCH 10/21] ARM: at91: Kconfig: add config flag for SAM9X7 SoC Varshini Rajendran
2023-06-03 20:02 ` Varshini Rajendran
2023-06-15 7:46 ` Claudiu.Beznea
2023-06-15 7:46 ` Claudiu.Beznea
2023-06-03 20:02 ` [PATCH 11/21] ARM: at91: add support in soc driver for new sam9x7 Varshini Rajendran
2023-06-03 20:02 ` Varshini Rajendran
2023-06-15 7:48 ` Claudiu.Beznea
2023-06-15 7:48 ` Claudiu.Beznea
2023-06-03 20:02 ` [PATCH 12/21] clk: at91: clk-sam9x60-pll: re-factor to support individual core freq outputs Varshini Rajendran
2023-06-03 20:02 ` Varshini Rajendran
2023-06-15 7:54 ` Claudiu.Beznea
2023-06-15 7:54 ` Claudiu.Beznea
2023-06-03 20:02 ` [PATCH 13/21] clk: at91: sam9x7: add support for HW PLL freq dividers Varshini Rajendran
2023-06-03 20:02 ` Varshini Rajendran
2023-06-15 8:00 ` Claudiu.Beznea
2023-06-15 8:00 ` Claudiu.Beznea
2023-06-03 20:02 ` [PATCH 14/21] clk: at91: sam9x7: add sam9x7 pmc driver Varshini Rajendran
2023-06-03 20:02 ` Varshini Rajendran
2023-06-04 18:00 ` Simon Horman
2023-06-04 18:00 ` Simon Horman
2023-06-15 8:39 ` Claudiu.Beznea
2023-06-15 8:39 ` Claudiu.Beznea
2023-06-03 20:02 ` [PATCH 15/21] dt-bindings: irqchip/atmel-aic5: Add support for sam9x7 aic Varshini Rajendran
2023-06-03 20:02 ` Varshini Rajendran
2023-06-03 21:19 ` Conor Dooley
2023-06-03 21:19 ` Conor Dooley
2023-06-03 21:23 ` Conor Dooley
2023-06-03 21:23 ` Conor Dooley
2023-06-04 9:49 ` Arnd Bergmann
2023-06-04 21:08 ` Conor Dooley
2023-06-05 12:37 ` Nicolas Ferre
2023-06-05 12:37 ` Nicolas Ferre
2023-06-14 19:41 ` Rob Herring
2023-06-14 19:41 ` Rob Herring
2023-06-03 20:02 ` [PATCH 16/21] " Varshini Rajendran
2023-06-03 20:02 ` Varshini Rajendran
2023-06-03 20:02 ` [PATCH 17/21] power: reset: at91-poweroff: lookup for proper pmc dt node for sam9x7 Varshini Rajendran
2023-06-03 20:02 ` Varshini Rajendran
2023-06-05 6:43 ` Krzysztof Kozlowski
2023-06-05 6:43 ` Krzysztof Kozlowski
2023-06-05 13:04 ` Nicolas Ferre
2023-06-05 13:04 ` Nicolas Ferre
2023-06-05 13:26 ` Conor Dooley
2023-06-05 13:26 ` Conor Dooley
2023-06-16 17:32 ` Varshini.Rajendran
2023-06-16 17:32 ` Varshini.Rajendran
2023-06-05 13:33 ` Krzysztof Kozlowski
2023-06-05 13:33 ` Krzysztof Kozlowski
2023-06-03 20:02 ` [PATCH 18/21] power: reset: at91-reset: add reset support for sam9x7 soc Varshini Rajendran
2023-06-03 20:02 ` Varshini Rajendran
2023-06-03 20:02 ` [PATCH 19/21] power: reset: at91-reset: add sdhwc " Varshini Rajendran
2023-06-03 20:02 ` Varshini Rajendran
2023-06-03 20:02 ` [PATCH 20/21] dt-bindings: net: cdns,macb: add documentation for sam9x7 ethernet interface Varshini Rajendran
2023-06-03 20:02 ` Varshini Rajendran
2023-06-05 6:42 ` Krzysztof Kozlowski
2023-06-05 6:42 ` Krzysztof Kozlowski
2023-06-14 19:42 ` Rob Herring
2023-06-14 19:42 ` Rob Herring
2023-06-03 20:02 ` [PATCH 21/21] net: macb: add support for gmac to sam9x7 Varshini Rajendran
2023-06-03 20:02 ` Varshini Rajendran
2023-06-05 6:42 ` Krzysztof Kozlowski
2023-06-05 6:42 ` Krzysztof Kozlowski
2023-06-05 12:07 ` Nicolas Ferre
2023-06-05 12:07 ` Nicolas Ferre
2023-06-05 12:21 ` Arnd Bergmann
2023-06-05 12:21 ` Arnd Bergmann
2023-06-05 13:34 ` Krzysztof Kozlowski
2023-06-05 13:34 ` Krzysztof Kozlowski
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