* [Intel-gfx] [PATCH 0/6] drm/i915: Futher optimize plane updates
@ 2022-01-21 11:30 Ville Syrjala
2022-01-21 11:30 ` [Intel-gfx] [PATCH 1/6] drm/i915: Clean up pre-skl primary plane registers Ville Syrjala
` (9 more replies)
0 siblings, 10 replies; 12+ messages in thread
From: Ville Syrjala @ 2022-01-21 11:30 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Optimize icl+ plane updates by moving most register writes
into the .update_noarm() hook. Also stop taking uncore.lock
for plane register writes as well
Ville Syrjälä (6):
drm/i915: Clean up pre-skl primary plane registers
drm/i915: Optimize icl+ universal plane programming
drm/i915: Make skl+ universal plane registers unlocked
drm/i915: Make cursor plane registers unlocked
drm/i915: Make most pre-skl primary plane registers unlocked
drm/i915: Make pre-skl sprite plane registers unlocked
drivers/gpu/drm/i915/display/i9xx_plane.c | 123 ++++++-----
drivers/gpu/drm/i915/display/intel_cursor.c | 10 -
drivers/gpu/drm/i915/display/intel_display.c | 13 +-
drivers/gpu/drm/i915/display/intel_sprite.c | 45 ----
.../drm/i915/display/skl_universal_plane.c | 196 ++++++++++++------
drivers/gpu/drm/i915/gvt/display.c | 4 +-
drivers/gpu/drm/i915/gvt/fb_decoder.c | 18 +-
drivers/gpu/drm/i915/i915_reg.h | 108 ++++++----
drivers/gpu/drm/i915/intel_pm.c | 2 +-
9 files changed, 275 insertions(+), 244 deletions(-)
--
2.32.0
^ permalink raw reply [flat|nested] 12+ messages in thread
* [Intel-gfx] [PATCH 1/6] drm/i915: Clean up pre-skl primary plane registers
2022-01-21 11:30 [Intel-gfx] [PATCH 0/6] drm/i915: Futher optimize plane updates Ville Syrjala
@ 2022-01-21 11:30 ` Ville Syrjala
2022-01-21 17:23 ` Souza, Jose
2022-01-21 11:30 ` [Intel-gfx] [PATCH 2/6] drm/i915: Optimize icl+ universal plane programming Ville Syrjala
` (8 subsequent siblings)
9 siblings, 1 reply; 12+ messages in thread
From: Ville Syrjala @ 2022-01-21 11:30 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Use REG_BIT() & co. for the pre-skl primary plane registers.
Also give everything a consistent namespace.
v2: s/DSP/DISP/ to avoid confusion (José)
Use DISP_WIDTH rather than DISP_POS_X for DSPSIZE (José)
Deal with gvt
Cc: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/i9xx_plane.c | 99 +++++++++--------
drivers/gpu/drm/i915/display/intel_display.c | 13 +--
drivers/gpu/drm/i915/gvt/display.c | 4 +-
drivers/gpu/drm/i915/gvt/fb_decoder.c | 18 ++--
drivers/gpu/drm/i915/i915_reg.h | 108 +++++++++++--------
drivers/gpu/drm/i915/intel_pm.c | 2 +-
6 files changed, 128 insertions(+), 116 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c b/drivers/gpu/drm/i915/display/i9xx_plane.c
index fc6f05146a9f..54f8776ca6b3 100644
--- a/drivers/gpu/drm/i915/display/i9xx_plane.c
+++ b/drivers/gpu/drm/i915/display/i9xx_plane.c
@@ -155,51 +155,51 @@ static u32 i9xx_plane_ctl(const struct intel_crtc_state *crtc_state,
unsigned int rotation = plane_state->hw.rotation;
u32 dspcntr;
- dspcntr = DISPLAY_PLANE_ENABLE;
+ dspcntr = DISP_ENABLE;
if (IS_G4X(dev_priv) || IS_IRONLAKE(dev_priv) ||
IS_SANDYBRIDGE(dev_priv) || IS_IVYBRIDGE(dev_priv))
- dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
+ dspcntr |= DISP_TRICKLE_FEED_DISABLE;
switch (fb->format->format) {
case DRM_FORMAT_C8:
- dspcntr |= DISPPLANE_8BPP;
+ dspcntr |= DISP_FORMAT_8BPP;
break;
case DRM_FORMAT_XRGB1555:
- dspcntr |= DISPPLANE_BGRX555;
+ dspcntr |= DISP_FORMAT_BGRX555;
break;
case DRM_FORMAT_ARGB1555:
- dspcntr |= DISPPLANE_BGRA555;
+ dspcntr |= DISP_FORMAT_BGRA555;
break;
case DRM_FORMAT_RGB565:
- dspcntr |= DISPPLANE_BGRX565;
+ dspcntr |= DISP_FORMAT_BGRX565;
break;
case DRM_FORMAT_XRGB8888:
- dspcntr |= DISPPLANE_BGRX888;
+ dspcntr |= DISP_FORMAT_BGRX888;
break;
case DRM_FORMAT_XBGR8888:
- dspcntr |= DISPPLANE_RGBX888;
+ dspcntr |= DISP_FORMAT_RGBX888;
break;
case DRM_FORMAT_ARGB8888:
- dspcntr |= DISPPLANE_BGRA888;
+ dspcntr |= DISP_FORMAT_BGRA888;
break;
case DRM_FORMAT_ABGR8888:
- dspcntr |= DISPPLANE_RGBA888;
+ dspcntr |= DISP_FORMAT_RGBA888;
break;
case DRM_FORMAT_XRGB2101010:
- dspcntr |= DISPPLANE_BGRX101010;
+ dspcntr |= DISP_FORMAT_BGRX101010;
break;
case DRM_FORMAT_XBGR2101010:
- dspcntr |= DISPPLANE_RGBX101010;
+ dspcntr |= DISP_FORMAT_RGBX101010;
break;
case DRM_FORMAT_ARGB2101010:
- dspcntr |= DISPPLANE_BGRA101010;
+ dspcntr |= DISP_FORMAT_BGRA101010;
break;
case DRM_FORMAT_ABGR2101010:
- dspcntr |= DISPPLANE_RGBA101010;
+ dspcntr |= DISP_FORMAT_RGBA101010;
break;
case DRM_FORMAT_XBGR16161616F:
- dspcntr |= DISPPLANE_RGBX161616;
+ dspcntr |= DISP_FORMAT_RGBX161616;
break;
default:
MISSING_CASE(fb->format->format);
@@ -208,13 +208,13 @@ static u32 i9xx_plane_ctl(const struct intel_crtc_state *crtc_state,
if (DISPLAY_VER(dev_priv) >= 4 &&
fb->modifier == I915_FORMAT_MOD_X_TILED)
- dspcntr |= DISPPLANE_TILED;
+ dspcntr |= DISP_TILED;
if (rotation & DRM_MODE_ROTATE_180)
- dspcntr |= DISPPLANE_ROTATE_180;
+ dspcntr |= DISP_ROTATE_180;
if (rotation & DRM_MODE_REFLECT_X)
- dspcntr |= DISPPLANE_MIRROR;
+ dspcntr |= DISP_MIRROR;
return dspcntr;
}
@@ -354,13 +354,13 @@ static u32 i9xx_plane_ctl_crtc(const struct intel_crtc_state *crtc_state)
u32 dspcntr = 0;
if (crtc_state->gamma_enable)
- dspcntr |= DISPPLANE_GAMMA_ENABLE;
+ dspcntr |= DISP_PIPE_GAMMA_ENABLE;
if (crtc_state->csc_enable)
- dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
+ dspcntr |= DISP_PIPE_CSC_ENABLE;
if (DISPLAY_VER(dev_priv) < 5)
- dspcntr |= DISPPLANE_SEL_PIPE(crtc->pipe);
+ dspcntr |= DISP_PIPE_SEL(crtc->pipe);
return dspcntr;
}
@@ -437,9 +437,9 @@ static void i9xx_plane_update_noarm(struct intel_plane *plane,
* program whatever is there.
*/
intel_de_write_fw(dev_priv, DSPPOS(i9xx_plane),
- (crtc_y << 16) | crtc_x);
+ DISP_POS_Y(crtc_y) | DISP_POS_X(crtc_x));
intel_de_write_fw(dev_priv, DSPSIZE(i9xx_plane),
- ((crtc_h - 1) << 16) | (crtc_w - 1));
+ DISP_HEIGHT(crtc_h - 1) | DISP_WIDTH(crtc_w - 1));
}
spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
@@ -474,20 +474,20 @@ static void i9xx_plane_update_arm(struct intel_plane *plane,
int crtc_h = drm_rect_height(&plane_state->uapi.dst);
intel_de_write_fw(dev_priv, PRIMPOS(i9xx_plane),
- (crtc_y << 16) | crtc_x);
+ PRIM_POS_Y(crtc_y) | PRIM_POS_X(crtc_x));
intel_de_write_fw(dev_priv, PRIMSIZE(i9xx_plane),
- ((crtc_h - 1) << 16) | (crtc_w - 1));
+ PRIM_HEIGHT(crtc_h - 1) | PRIM_WIDTH(crtc_w - 1));
intel_de_write_fw(dev_priv, PRIMCNSTALPHA(i9xx_plane), 0);
}
if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
intel_de_write_fw(dev_priv, DSPOFFSET(i9xx_plane),
- (y << 16) | x);
+ DISP_OFFSET_Y(y) | DISP_OFFSET_X(x));
} else if (DISPLAY_VER(dev_priv) >= 4) {
intel_de_write_fw(dev_priv, DSPLINOFF(i9xx_plane),
linear_offset);
intel_de_write_fw(dev_priv, DSPTILEOFF(i9xx_plane),
- (y << 16) | x);
+ DISP_OFFSET_Y(y) | DISP_OFFSET_X(x));
}
/*
@@ -564,7 +564,7 @@ g4x_primary_async_flip(struct intel_plane *plane,
unsigned long irqflags;
if (async_flip)
- dspcntr |= DISPPLANE_ASYNC_FLIP;
+ dspcntr |= DISP_ASYNC_FLIP;
spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
intel_de_write_fw(dev_priv, DSPCNTR(i9xx_plane), dspcntr);
@@ -696,13 +696,12 @@ static bool i9xx_plane_get_hw_state(struct intel_plane *plane,
val = intel_de_read(dev_priv, DSPCNTR(i9xx_plane));
- ret = val & DISPLAY_PLANE_ENABLE;
+ ret = val & DISP_ENABLE;
if (DISPLAY_VER(dev_priv) >= 5)
*pipe = plane->pipe;
else
- *pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
- DISPPLANE_SEL_PIPE_SHIFT;
+ *pipe = REG_FIELD_GET(DISP_PIPE_SEL_MASK, val);
intel_display_power_put(dev_priv, power_domain, wakeref);
@@ -958,32 +957,32 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
static int i9xx_format_to_fourcc(int format)
{
switch (format) {
- case DISPPLANE_8BPP:
+ case DISP_FORMAT_8BPP:
return DRM_FORMAT_C8;
- case DISPPLANE_BGRA555:
+ case DISP_FORMAT_BGRA555:
return DRM_FORMAT_ARGB1555;
- case DISPPLANE_BGRX555:
+ case DISP_FORMAT_BGRX555:
return DRM_FORMAT_XRGB1555;
- case DISPPLANE_BGRX565:
+ case DISP_FORMAT_BGRX565:
return DRM_FORMAT_RGB565;
default:
- case DISPPLANE_BGRX888:
+ case DISP_FORMAT_BGRX888:
return DRM_FORMAT_XRGB8888;
- case DISPPLANE_RGBX888:
+ case DISP_FORMAT_RGBX888:
return DRM_FORMAT_XBGR8888;
- case DISPPLANE_BGRA888:
+ case DISP_FORMAT_BGRA888:
return DRM_FORMAT_ARGB8888;
- case DISPPLANE_RGBA888:
+ case DISP_FORMAT_RGBA888:
return DRM_FORMAT_ABGR8888;
- case DISPPLANE_BGRX101010:
+ case DISP_FORMAT_BGRX101010:
return DRM_FORMAT_XRGB2101010;
- case DISPPLANE_RGBX101010:
+ case DISP_FORMAT_RGBX101010:
return DRM_FORMAT_XBGR2101010;
- case DISPPLANE_BGRA101010:
+ case DISP_FORMAT_BGRA101010:
return DRM_FORMAT_ARGB2101010;
- case DISPPLANE_RGBA101010:
+ case DISP_FORMAT_RGBA101010:
return DRM_FORMAT_ABGR2101010;
- case DISPPLANE_RGBX161616:
+ case DISP_FORMAT_RGBX161616:
return DRM_FORMAT_XBGR16161616F;
}
}
@@ -1021,26 +1020,26 @@ i9xx_get_initial_plane_config(struct intel_crtc *crtc,
val = intel_de_read(dev_priv, DSPCNTR(i9xx_plane));
if (DISPLAY_VER(dev_priv) >= 4) {
- if (val & DISPPLANE_TILED) {
+ if (val & DISP_TILED) {
plane_config->tiling = I915_TILING_X;
fb->modifier = I915_FORMAT_MOD_X_TILED;
}
- if (val & DISPPLANE_ROTATE_180)
+ if (val & DISP_ROTATE_180)
plane_config->rotation = DRM_MODE_ROTATE_180;
}
if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B &&
- val & DISPPLANE_MIRROR)
+ val & DISP_MIRROR)
plane_config->rotation |= DRM_MODE_REFLECT_X;
- pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
+ pixel_format = val & DISP_FORMAT_MASK;
fourcc = i9xx_format_to_fourcc(pixel_format);
fb->format = drm_format_info(fourcc);
if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
offset = intel_de_read(dev_priv, DSPOFFSET(i9xx_plane));
- base = intel_de_read(dev_priv, DSPSURF(i9xx_plane)) & 0xfffff000;
+ base = intel_de_read(dev_priv, DSPSURF(i9xx_plane)) & DISP_ADDR_MASK;
} else if (DISPLAY_VER(dev_priv) >= 4) {
if (plane_config->tiling)
offset = intel_de_read(dev_priv,
@@ -1048,7 +1047,7 @@ i9xx_get_initial_plane_config(struct intel_crtc *crtc,
else
offset = intel_de_read(dev_priv,
DSPLINOFF(i9xx_plane));
- base = intel_de_read(dev_priv, DSPSURF(i9xx_plane)) & 0xfffff000;
+ base = intel_de_read(dev_priv, DSPSURF(i9xx_plane)) & DISP_ADDR_MASK;
} else {
base = intel_de_read(dev_priv, DSPADDR(i9xx_plane));
}
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 0964b2403e2d..750aa22ec0a7 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -3543,11 +3543,11 @@ static void i9xx_get_pipe_color_config(struct intel_crtc_state *crtc_state)
tmp = intel_de_read(dev_priv, DSPCNTR(i9xx_plane));
- if (tmp & DISPPLANE_GAMMA_ENABLE)
+ if (tmp & DISP_PIPE_GAMMA_ENABLE)
crtc_state->gamma_enable = true;
if (!HAS_GMCH(dev_priv) &&
- tmp & DISPPLANE_PIPE_CSC_ENABLE)
+ tmp & DISP_PIPE_CSC_ENABLE)
crtc_state->csc_enable = true;
}
@@ -9995,14 +9995,11 @@ void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
pipe_name(pipe));
drm_WARN_ON(&dev_priv->drm,
- intel_de_read(dev_priv, DSPCNTR(PLANE_A)) &
- DISPLAY_PLANE_ENABLE);
+ intel_de_read(dev_priv, DSPCNTR(PLANE_A)) & DISP_ENABLE);
drm_WARN_ON(&dev_priv->drm,
- intel_de_read(dev_priv, DSPCNTR(PLANE_B)) &
- DISPLAY_PLANE_ENABLE);
+ intel_de_read(dev_priv, DSPCNTR(PLANE_B)) & DISP_ENABLE);
drm_WARN_ON(&dev_priv->drm,
- intel_de_read(dev_priv, DSPCNTR(PLANE_C)) &
- DISPLAY_PLANE_ENABLE);
+ intel_de_read(dev_priv, DSPCNTR(PLANE_C)) & DISP_ENABLE);
drm_WARN_ON(&dev_priv->drm,
intel_de_read(dev_priv, CURCNTR(PIPE_A)) & MCURSOR_MODE_MASK);
drm_WARN_ON(&dev_priv->drm,
diff --git a/drivers/gpu/drm/i915/gvt/display.c b/drivers/gpu/drm/i915/gvt/display.c
index 8ce5d2b2e330..4d66fb5fb29f 100644
--- a/drivers/gpu/drm/i915/gvt/display.c
+++ b/drivers/gpu/drm/i915/gvt/display.c
@@ -185,7 +185,7 @@ static void emulate_monitor_status_change(struct intel_vgpu *vgpu)
for_each_pipe(dev_priv, pipe) {
vgpu_vreg_t(vgpu, PIPECONF(pipe)) &=
~(PIPECONF_ENABLE | I965_PIPECONF_ACTIVE);
- vgpu_vreg_t(vgpu, DSPCNTR(pipe)) &= ~DISPLAY_PLANE_ENABLE;
+ vgpu_vreg_t(vgpu, DSPCNTR(pipe)) &= ~DISP_ENABLE;
vgpu_vreg_t(vgpu, SPRCTL(pipe)) &= ~SPRITE_ENABLE;
vgpu_vreg_t(vgpu, CURCNTR(pipe)) &= ~MCURSOR_MODE_MASK;
vgpu_vreg_t(vgpu, CURCNTR(pipe)) |= MCURSOR_MODE_DISABLE;
@@ -496,7 +496,7 @@ static void emulate_monitor_status_change(struct intel_vgpu *vgpu)
/* Disable Primary/Sprite/Cursor plane */
for_each_pipe(dev_priv, pipe) {
- vgpu_vreg_t(vgpu, DSPCNTR(pipe)) &= ~DISPLAY_PLANE_ENABLE;
+ vgpu_vreg_t(vgpu, DSPCNTR(pipe)) &= ~DISP_ENABLE;
vgpu_vreg_t(vgpu, SPRCTL(pipe)) &= ~SPRITE_ENABLE;
vgpu_vreg_t(vgpu, CURCNTR(pipe)) &= ~MCURSOR_MODE_MASK;
vgpu_vreg_t(vgpu, CURCNTR(pipe)) |= MCURSOR_MODE_DISABLE;
diff --git a/drivers/gpu/drm/i915/gvt/fb_decoder.c b/drivers/gpu/drm/i915/gvt/fb_decoder.c
index 40ace46bad46..f2a216347d77 100644
--- a/drivers/gpu/drm/i915/gvt/fb_decoder.c
+++ b/drivers/gpu/drm/i915/gvt/fb_decoder.c
@@ -83,22 +83,22 @@ static int bdw_format_to_drm(int format)
int bdw_pixel_formats_index = 6;
switch (format) {
- case DISPPLANE_8BPP:
+ case DISP_FORMAT_8BPP:
bdw_pixel_formats_index = 0;
break;
- case DISPPLANE_BGRX565:
+ case DISP_FORMAT_BGRX565:
bdw_pixel_formats_index = 1;
break;
- case DISPPLANE_BGRX888:
+ case DISP_FORMAT_BGRX888:
bdw_pixel_formats_index = 2;
break;
- case DISPPLANE_RGBX101010:
+ case DISP_FORMAT_RGBX101010:
bdw_pixel_formats_index = 3;
break;
- case DISPPLANE_BGRX101010:
+ case DISP_FORMAT_BGRX101010:
bdw_pixel_formats_index = 4;
break;
- case DISPPLANE_RGBX888:
+ case DISP_FORMAT_RGBX888:
bdw_pixel_formats_index = 5;
break;
@@ -211,7 +211,7 @@ int intel_vgpu_decode_primary_plane(struct intel_vgpu *vgpu,
return -ENODEV;
val = vgpu_vreg_t(vgpu, DSPCNTR(pipe));
- plane->enabled = !!(val & DISPLAY_PLANE_ENABLE);
+ plane->enabled = !!(val & DISP_ENABLE);
if (!plane->enabled)
return -ENODEV;
@@ -231,8 +231,8 @@ int intel_vgpu_decode_primary_plane(struct intel_vgpu *vgpu,
plane->bpp = skl_pixel_formats[fmt].bpp;
plane->drm_format = skl_pixel_formats[fmt].drm_format;
} else {
- plane->tiled = val & DISPPLANE_TILED;
- fmt = bdw_format_to_drm(val & DISPPLANE_PIXFORMAT_MASK);
+ plane->tiled = val & DISP_TILED;
+ fmt = bdw_format_to_drm(val & DISP_FORMAT_MASK);
plane->bpp = bdw_pixel_formats[fmt].bpp;
plane->drm_format = bdw_pixel_formats[fmt].drm_format;
}
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 460bce5c544d..1328d00ddfe8 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5900,49 +5900,54 @@ enum {
/* Display A control */
#define _DSPAADDR_VLV 0x7017C /* vlv/chv */
#define _DSPACNTR 0x70180
-#define DISPLAY_PLANE_ENABLE (1 << 31)
-#define DISPLAY_PLANE_DISABLE 0
-#define DISPPLANE_GAMMA_ENABLE (1 << 30)
-#define DISPPLANE_GAMMA_DISABLE 0
-#define DISPPLANE_PIXFORMAT_MASK (0xf << 26)
-#define DISPPLANE_YUV422 (0x0 << 26)
-#define DISPPLANE_8BPP (0x2 << 26)
-#define DISPPLANE_BGRA555 (0x3 << 26)
-#define DISPPLANE_BGRX555 (0x4 << 26)
-#define DISPPLANE_BGRX565 (0x5 << 26)
-#define DISPPLANE_BGRX888 (0x6 << 26)
-#define DISPPLANE_BGRA888 (0x7 << 26)
-#define DISPPLANE_RGBX101010 (0x8 << 26)
-#define DISPPLANE_RGBA101010 (0x9 << 26)
-#define DISPPLANE_BGRX101010 (0xa << 26)
-#define DISPPLANE_BGRA101010 (0xb << 26)
-#define DISPPLANE_RGBX161616 (0xc << 26)
-#define DISPPLANE_RGBX888 (0xe << 26)
-#define DISPPLANE_RGBA888 (0xf << 26)
-#define DISPPLANE_STEREO_ENABLE (1 << 25)
-#define DISPPLANE_STEREO_DISABLE 0
-#define DISPPLANE_PIPE_CSC_ENABLE (1 << 24) /* ilk+ */
-#define DISPPLANE_SEL_PIPE_SHIFT 24
-#define DISPPLANE_SEL_PIPE_MASK (3 << DISPPLANE_SEL_PIPE_SHIFT)
-#define DISPPLANE_SEL_PIPE(pipe) ((pipe) << DISPPLANE_SEL_PIPE_SHIFT)
-#define DISPPLANE_SRC_KEY_ENABLE (1 << 22)
-#define DISPPLANE_SRC_KEY_DISABLE 0
-#define DISPPLANE_LINE_DOUBLE (1 << 20)
-#define DISPPLANE_NO_LINE_DOUBLE 0
-#define DISPPLANE_STEREO_POLARITY_FIRST 0
-#define DISPPLANE_STEREO_POLARITY_SECOND (1 << 18)
-#define DISPPLANE_ALPHA_PREMULTIPLY (1 << 16) /* CHV pipe B */
-#define DISPPLANE_ROTATE_180 (1 << 15)
-#define DISPPLANE_TRICKLE_FEED_DISABLE (1 << 14) /* Ironlake */
-#define DISPPLANE_TILED (1 << 10)
-#define DISPPLANE_ASYNC_FLIP (1 << 9) /* g4x+ */
-#define DISPPLANE_MIRROR (1 << 8) /* CHV pipe B */
+#define DISP_ENABLE REG_BIT(31)
+#define DISP_PIPE_GAMMA_ENABLE REG_BIT(30)
+#define DISP_FORMAT_MASK REG_GENMASK(29, 26)
+#define DISP_FORMAT_8BPP REG_FIELD_PREP(DISP_FORMAT_MASK, 2)
+#define DISP_FORMAT_BGRA555 REG_FIELD_PREP(DISP_FORMAT_MASK, 3)
+#define DISP_FORMAT_BGRX555 REG_FIELD_PREP(DISP_FORMAT_MASK, 4)
+#define DISP_FORMAT_BGRX565 REG_FIELD_PREP(DISP_FORMAT_MASK, 5)
+#define DISP_FORMAT_BGRX888 REG_FIELD_PREP(DISP_FORMAT_MASK, 6)
+#define DISP_FORMAT_BGRA888 REG_FIELD_PREP(DISP_FORMAT_MASK, 7)
+#define DISP_FORMAT_RGBX101010 REG_FIELD_PREP(DISP_FORMAT_MASK, 8)
+#define DISP_FORMAT_RGBA101010 REG_FIELD_PREP(DISP_FORMAT_MASK, 9)
+#define DISP_FORMAT_BGRX101010 REG_FIELD_PREP(DISP_FORMAT_MASK, 10)
+#define DISP_FORMAT_BGRA101010 REG_FIELD_PREP(DISP_FORMAT_MASK, 11)
+#define DISP_FORMAT_RGBX161616 REG_FIELD_PREP(DISP_FORMAT_MASK, 12)
+#define DISP_FORMAT_RGBX888 REG_FIELD_PREP(DISP_FORMAT_MASK, 14)
+#define DISP_FORMAT_RGBA888 REG_FIELD_PREP(DISP_FORMAT_MASK, 15)
+#define DISP_STEREO_ENABLE REG_BIT(25)
+#define DISP_PIPE_CSC_ENABLE REG_BIT(24) /* ilk+ */
+#define DISP_PIPE_SEL_MASK REG_GENMASK(25, 24)
+#define DISP_PIPE_SEL(pipe) REG_FIELD_PREP(DISP_PIPE_SEL_MASK, (pipe))
+#define DISP_SRC_KEY_ENABLE REG_BIT(22)
+#define DISP_LINE_DOUBLE REG_BIT(20)
+#define DISP_STEREO_POLARITY_SECOND REG_BIT(18)
+#define DISP_ALPHA_PREMULTIPLY REG_BIT(16) /* CHV pipe B */
+#define DISP_ROTATE_180 REG_BIT(15)
+#define DISP_TRICKLE_FEED_DISABLE REG_BIT(14) /* g4x+ */
+#define DISP_TILED REG_BIT(10)
+#define DISP_ASYNC_FLIP REG_BIT(9) /* g4x+ */
+#define DISP_MIRROR REG_BIT(8) /* CHV pipe B */
#define _DSPAADDR 0x70184
#define _DSPASTRIDE 0x70188
#define _DSPAPOS 0x7018C /* reserved */
+#define DISP_POS_Y_MASK REG_GENMASK(31, 0)
+#define DISP_POS_Y(y) REG_FIELD_PREP(DISP_POS_Y_MASK, (y))
+#define DISP_POS_X_MASK REG_GENMASK(15, 0)
+#define DISP_POS_X(x) REG_FIELD_PREP(DISP_POS_X_MASK, (x))
#define _DSPASIZE 0x70190
+#define DISP_HEIGHT_MASK REG_GENMASK(31, 0)
+#define DISP_HEIGHT(h) REG_FIELD_PREP(DISP_HEIGHT_MASK, (h))
+#define DISP_WIDTH_MASK REG_GENMASK(15, 0)
+#define DISP_WIDTH(w) REG_FIELD_PREP(DISP_WIDTH_MASK, (w))
#define _DSPASURF 0x7019C /* 965+ only */
+#define DISP_ADDR_MASK REG_GENMASK(31, 12)
#define _DSPATILEOFF 0x701A4 /* 965+ only */
+#define DISP_OFFSET_Y_MASK REG_GENMASK(31, 16)
+#define DISP_OFFSET_Y(y) REG_FIELD_PREP(DISP_OFFSET_Y_MASK, (y))
+#define DISP_OFFSET_X_MASK REG_GENMASK(15, 0)
+#define DISP_OFFSET_X(x) REG_FIELD_PREP(DISP_OFFSET_X_MASK, (x))
#define _DSPAOFFSET 0x701A4 /* HSW */
#define _DSPASURFLIVE 0x701AC
#define _DSPAGAMC 0x701E0
@@ -5962,15 +5967,28 @@ enum {
/* CHV pipe B blender and primary plane */
#define _CHV_BLEND_A 0x60a00
-#define CHV_BLEND_LEGACY (0 << 30)
-#define CHV_BLEND_ANDROID (1 << 30)
-#define CHV_BLEND_MPO (2 << 30)
-#define CHV_BLEND_MASK (3 << 30)
+#define CHV_BLEND_MASK REG_GENMASK(31, 30)
+#define CHV_BLEND_LEGACY REG_FIELD_PREP(CHV_BLEND_MASK, 0)
+#define CHV_BLEND_ANDROID REG_FIELD_PREP(CHV_BLEND_MASK, 1)
+#define CHV_BLEND_MPO REG_FIELD_PREP(CHV_BLEND_MASK, 2)
#define _CHV_CANVAS_A 0x60a04
+#define CHV_CANVAS_RED_MASK REG_GENMASK(29, 20)
+#define CHV_CANVAS_GREEN_MASK REG_GENMASK(19, 10)
+#define CHV_CANVAS_BLUE_MASK REG_GENMASK(9, 0)
#define _PRIMPOS_A 0x60a08
+#define PRIM_POS_Y_MASK REG_GENMASK(31, 16)
+#define PRIM_POS_Y(y) REG_FIELD_PREP(PRIM_POS_Y_MASK, (y))
+#define PRIM_POS_X_MASK REG_GENMASK(15, 0)
+#define PRIM_POS_X(x) REG_FIELD_PREP(PRIM_POS_X_MASK, (x))
#define _PRIMSIZE_A 0x60a0c
+#define PRIM_HEIGHT_MASK REG_GENMASK(31, 16)
+#define PRIM_HEIGHT(h) REG_FIELD_PREP(PRIM_HEIGHT_MASK, (h))
+#define PRIM_WIDTH_MASK REG_GENMASK(15, 0)
+#define PRIM_WIDTH(w) REG_FIELD_PREP(PRIM_WIDTH_MASK, (w))
#define _PRIMCNSTALPHA_A 0x60a10
-#define PRIM_CONST_ALPHA_ENABLE (1 << 31)
+#define PRIM_CONST_ALPHA_ENABLE REG_BIT(31)
+#define PRIM_CONST_ALPHA_MASK REG_GENMASK(7, 0)
+#define PRIM_CONST_ALPHA(alpha) REG_FIELD_PREP(PRIM_CONST_ALPHA_MASK, (alpha))
#define CHV_BLEND(pipe) _MMIO_TRANS2(pipe, _CHV_BLEND_A)
#define CHV_CANVAS(pipe) _MMIO_TRANS2(pipe, _CHV_CANVAS_A)
@@ -6011,10 +6029,8 @@ enum {
/* Display B control */
#define _DSPBCNTR (DISPLAY_MMIO_BASE(dev_priv) + 0x71180)
-#define DISPPLANE_ALPHA_TRANS_ENABLE (1 << 15)
-#define DISPPLANE_ALPHA_TRANS_DISABLE 0
-#define DISPPLANE_SPRITE_ABOVE_DISPLAY 0
-#define DISPPLANE_SPRITE_ABOVE_OVERLAY (1)
+#define DISP_ALPHA_TRANS_ENABLE REG_BIT(15)
+#define DISP_SPRITE_ABOVE_OVERLAY REG_BIT(0)
#define _DSPBADDR (DISPLAY_MMIO_BASE(dev_priv) + 0x71184)
#define _DSPBSTRIDE (DISPLAY_MMIO_BASE(dev_priv) + 0x71188)
#define _DSPBPOS (DISPLAY_MMIO_BASE(dev_priv) + 0x7118C)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 2ec8e48806b6..c2bb9945f7be 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -7208,7 +7208,7 @@ static void g4x_disable_trickle_feed(struct drm_i915_private *dev_priv)
for_each_pipe(dev_priv, pipe) {
intel_uncore_write(&dev_priv->uncore, DSPCNTR(pipe),
intel_uncore_read(&dev_priv->uncore, DSPCNTR(pipe)) |
- DISPPLANE_TRICKLE_FEED_DISABLE);
+ DISP_TRICKLE_FEED_DISABLE);
intel_uncore_write(&dev_priv->uncore, DSPSURF(pipe), intel_uncore_read(&dev_priv->uncore, DSPSURF(pipe)));
intel_uncore_posting_read(&dev_priv->uncore, DSPSURF(pipe));
--
2.32.0
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [Intel-gfx] [PATCH 2/6] drm/i915: Optimize icl+ universal plane programming
2022-01-21 11:30 [Intel-gfx] [PATCH 0/6] drm/i915: Futher optimize plane updates Ville Syrjala
2022-01-21 11:30 ` [Intel-gfx] [PATCH 1/6] drm/i915: Clean up pre-skl primary plane registers Ville Syrjala
@ 2022-01-21 11:30 ` Ville Syrjala
2022-01-21 11:30 ` [Intel-gfx] [PATCH 3/6] drm/i915: Make skl+ universal plane registers unlocked Ville Syrjala
` (7 subsequent siblings)
9 siblings, 0 replies; 12+ messages in thread
From: Ville Syrjala @ 2022-01-21 11:30 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
On icl+ all plane registers are armed by PLANE_SURF, so we can
move almost everything over into the update_noarm() hook.
The PLANE_CTL write has to stay in the icl_update_arm() hook though
as it still exhibits the somewhat annoying self-arming behaviour
when the plane transitioning from disabled to enabled.
We could either do a full split for skl+ vs. icl+, or we could try
some other kind of split where we'd eg. keep most things in the skl+
functions and call them from the icl+ functions. I think a full split
is probably the cleaner approach since we've anyway accumulated quite
a bit of icl+ specific things, so that is what I opted to do.
Some i915_update_info stats for tgl:
before: after:
Updates: 5043 Updates: 5043
| |
1us | 1us |
|** |***
4us |****** 4us |********
|********** |***********
16us |*********** 16us |**********
|**** |*
66us | 66us |
| |
262us | 262us |
| |
1ms | 1ms |
| |
4ms | 4ms |
| |
17ms | 17ms |
| |
Min update: 3494ns Min update: 2983ns
Max update: 49491ns Max update: 39986ns
Average update: 18031ns Average update: 13423ns
Overruns > 100us: 0 Overruns > 100us: 0
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
.../drm/i915/display/skl_universal_plane.c | 195 ++++++++++++++----
1 file changed, 155 insertions(+), 40 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
index 72dcc341bb1f..07c64ea5b362 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
@@ -619,6 +619,25 @@ skl_plane_disable_arm(struct intel_plane *plane,
spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
+ skl_write_plane_wm(plane, crtc_state);
+
+ intel_de_write_fw(dev_priv, PLANE_CTL(pipe, plane_id), 0);
+ intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id), 0);
+
+ spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
+}
+
+static void
+icl_plane_disable_arm(struct intel_plane *plane,
+ const struct intel_crtc_state *crtc_state)
+{
+ struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
+ enum plane_id plane_id = plane->id;
+ enum pipe pipe = plane->pipe;
+ unsigned long irqflags;
+
+ spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
+
if (icl_is_hdr_plane(dev_priv, plane_id))
intel_de_write_fw(dev_priv, PLANE_CUS_CTL(pipe, plane_id), 0);
@@ -1064,7 +1083,7 @@ static void icl_plane_csc_load_black(struct intel_plane *plane)
intel_de_write_fw(i915, PLANE_CSC_POSTOFF(pipe, plane_id, 2), 0);
}
-static int skl_plane_color_plane(const struct intel_plane_state *plane_state)
+static int icl_plane_color_plane(const struct intel_plane_state *plane_state)
{
/* Program the UV plane on planar master */
if (plane_state->planar_linked_plane && !plane_state->planar_slave)
@@ -1081,9 +1100,7 @@ skl_plane_update_noarm(struct intel_plane *plane,
struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
enum plane_id plane_id = plane->id;
enum pipe pipe = plane->pipe;
- int color_plane = skl_plane_color_plane(plane_state);
- u32 stride = skl_plane_stride(plane_state, color_plane);
- const struct drm_framebuffer *fb = plane_state->hw.fb;
+ u32 stride = skl_plane_stride(plane_state, 0);
int crtc_x = plane_state->uapi.dst.x1;
int crtc_y = plane_state->uapi.dst.y1;
u32 src_w = drm_rect_width(&plane_state->uapi.src) >> 16;
@@ -1098,12 +1115,109 @@ skl_plane_update_noarm(struct intel_plane *plane,
spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
+ intel_de_write_fw(dev_priv, PLANE_STRIDE(pipe, plane_id),
+ PLANE_STRIDE_(stride));
+ intel_de_write_fw(dev_priv, PLANE_POS(pipe, plane_id),
+ PLANE_POS_Y(crtc_y) | PLANE_POS_X(crtc_x));
+ intel_de_write_fw(dev_priv, PLANE_SIZE(pipe, plane_id),
+ PLANE_HEIGHT(src_h - 1) | PLANE_WIDTH(src_w - 1));
+
+ skl_write_plane_wm(plane, crtc_state);
+
+ spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
+}
+
+static void
+skl_plane_update_arm(struct intel_plane *plane,
+ const struct intel_crtc_state *crtc_state,
+ const struct intel_plane_state *plane_state)
+{
+ struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
+ enum plane_id plane_id = plane->id;
+ enum pipe pipe = plane->pipe;
+ u32 x = plane_state->view.color_plane[0].x;
+ u32 y = plane_state->view.color_plane[0].y;
+ u32 plane_ctl, plane_color_ctl = 0;
+ unsigned long irqflags;
+
+ plane_ctl = plane_state->ctl |
+ skl_plane_ctl_crtc(crtc_state);
+
+ if (DISPLAY_VER(dev_priv) >= 10)
+ plane_color_ctl = plane_state->color_ctl |
+ glk_plane_color_ctl_crtc(crtc_state);
+
+ spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
+
+ intel_de_write_fw(dev_priv, PLANE_KEYVAL(pipe, plane_id), skl_plane_keyval(plane_state));
+ intel_de_write_fw(dev_priv, PLANE_KEYMSK(pipe, plane_id), skl_plane_keymsk(plane_state));
+ intel_de_write_fw(dev_priv, PLANE_KEYMAX(pipe, plane_id), skl_plane_keymax(plane_state));
+
+ intel_de_write_fw(dev_priv, PLANE_OFFSET(pipe, plane_id),
+ PLANE_OFFSET_Y(y) | PLANE_OFFSET_X(x));
+
+ intel_de_write_fw(dev_priv, PLANE_AUX_DIST(pipe, plane_id),
+ skl_plane_aux_dist(plane_state, 0));
+
+ intel_de_write_fw(dev_priv, PLANE_AUX_OFFSET(pipe, plane_id),
+ PLANE_OFFSET_Y(plane_state->view.color_plane[1].y) |
+ PLANE_OFFSET_X(plane_state->view.color_plane[1].x));
+
+ if (DISPLAY_VER(dev_priv) >= 10)
+ intel_de_write_fw(dev_priv, PLANE_COLOR_CTL(pipe, plane_id), plane_color_ctl);
+
+ /*
+ * Enable the scaler before the plane so that we don't
+ * get a catastrophic underrun even if the two operations
+ * end up happening in two different frames.
+ *
+ * TODO: split into noarm+arm pair
+ */
+ if (plane_state->scaler_id >= 0)
+ skl_program_plane_scaler(plane, crtc_state, plane_state);
+
/*
- * FIXME: pxp session invalidation can hit any time even at time of commit
- * or after the commit, display content will be garbage.
+ * The control register self-arms if the plane was previously
+ * disabled. Try to make the plane enable atomic by writing
+ * the control register just before the surface register.
*/
- if (plane_state->force_black)
- icl_plane_csc_load_black(plane);
+ intel_de_write_fw(dev_priv, PLANE_CTL(pipe, plane_id), plane_ctl);
+ intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id),
+ skl_plane_surf(plane_state, 0));
+
+ spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
+}
+
+static void
+icl_plane_update_noarm(struct intel_plane *plane,
+ const struct intel_crtc_state *crtc_state,
+ const struct intel_plane_state *plane_state)
+{
+ struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
+ enum plane_id plane_id = plane->id;
+ enum pipe pipe = plane->pipe;
+ int color_plane = icl_plane_color_plane(plane_state);
+ u32 stride = skl_plane_stride(plane_state, color_plane);
+ const struct drm_framebuffer *fb = plane_state->hw.fb;
+ int crtc_x = plane_state->uapi.dst.x1;
+ int crtc_y = plane_state->uapi.dst.y1;
+ int x = plane_state->view.color_plane[color_plane].x;
+ int y = plane_state->view.color_plane[color_plane].y;
+ int src_w = drm_rect_width(&plane_state->uapi.src) >> 16;
+ int src_h = drm_rect_height(&plane_state->uapi.src) >> 16;
+ u32 plane_color_ctl;
+ unsigned long irqflags;
+
+ plane_color_ctl = plane_state->color_ctl |
+ glk_plane_color_ctl_crtc(crtc_state);
+
+ /* The scaler will handle the output position */
+ if (plane_state->scaler_id >= 0) {
+ crtc_x = 0;
+ crtc_y = 0;
+ }
+
+ spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
intel_de_write_fw(dev_priv, PLANE_STRIDE(pipe, plane_id),
PLANE_STRIDE_(stride));
@@ -1112,6 +1226,13 @@ skl_plane_update_noarm(struct intel_plane *plane,
intel_de_write_fw(dev_priv, PLANE_SIZE(pipe, plane_id),
PLANE_HEIGHT(src_h - 1) | PLANE_WIDTH(src_w - 1));
+ intel_de_write_fw(dev_priv, PLANE_KEYVAL(pipe, plane_id), skl_plane_keyval(plane_state));
+ intel_de_write_fw(dev_priv, PLANE_KEYMSK(pipe, plane_id), skl_plane_keymsk(plane_state));
+ intel_de_write_fw(dev_priv, PLANE_KEYMAX(pipe, plane_id), skl_plane_keymax(plane_state));
+
+ intel_de_write_fw(dev_priv, PLANE_OFFSET(pipe, plane_id),
+ PLANE_OFFSET_Y(y) | PLANE_OFFSET_X(x));
+
if (intel_fb_is_rc_ccs_cc_modifier(fb->modifier)) {
intel_de_write_fw(dev_priv, PLANE_CC_VAL(pipe, plane_id, 0),
lower_32_bits(plane_state->ccval));
@@ -1119,61 +1240,49 @@ skl_plane_update_noarm(struct intel_plane *plane,
upper_32_bits(plane_state->ccval));
}
+ intel_de_write_fw(dev_priv, PLANE_AUX_DIST(pipe, plane_id),
+ skl_plane_aux_dist(plane_state, color_plane));
+
if (icl_is_hdr_plane(dev_priv, plane_id))
intel_de_write_fw(dev_priv, PLANE_CUS_CTL(pipe, plane_id),
plane_state->cus_ctl);
+ intel_de_write_fw(dev_priv, PLANE_COLOR_CTL(pipe, plane_id), plane_color_ctl);
+
if (fb->format->is_yuv && icl_is_hdr_plane(dev_priv, plane_id))
icl_program_input_csc(plane, crtc_state, plane_state);
skl_write_plane_wm(plane, crtc_state);
+ /*
+ * FIXME: pxp session invalidation can hit any time even at time of commit
+ * or after the commit, display content will be garbage.
+ */
+ if (plane_state->force_black)
+ icl_plane_csc_load_black(plane);
+
intel_psr2_program_plane_sel_fetch(plane, crtc_state, plane_state, color_plane);
spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
}
static void
-skl_plane_update_arm(struct intel_plane *plane,
+icl_plane_update_arm(struct intel_plane *plane,
const struct intel_crtc_state *crtc_state,
const struct intel_plane_state *plane_state)
{
struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
enum plane_id plane_id = plane->id;
enum pipe pipe = plane->pipe;
- int color_plane = skl_plane_color_plane(plane_state);
- u32 x = plane_state->view.color_plane[color_plane].x;
- u32 y = plane_state->view.color_plane[color_plane].y;
- u32 plane_color_ctl = 0;
- u32 plane_ctl = plane_state->ctl;
+ int color_plane = icl_plane_color_plane(plane_state);
+ u32 plane_ctl;
unsigned long irqflags;
- plane_ctl |= skl_plane_ctl_crtc(crtc_state);
-
- if (DISPLAY_VER(dev_priv) >= 10)
- plane_color_ctl = plane_state->color_ctl |
- glk_plane_color_ctl_crtc(crtc_state);
+ plane_ctl = plane_state->ctl |
+ skl_plane_ctl_crtc(crtc_state);
spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
- intel_de_write_fw(dev_priv, PLANE_KEYVAL(pipe, plane_id), skl_plane_keyval(plane_state));
- intel_de_write_fw(dev_priv, PLANE_KEYMSK(pipe, plane_id), skl_plane_keymsk(plane_state));
- intel_de_write_fw(dev_priv, PLANE_KEYMAX(pipe, plane_id), skl_plane_keymax(plane_state));
-
- intel_de_write_fw(dev_priv, PLANE_OFFSET(pipe, plane_id),
- PLANE_OFFSET_Y(y) | PLANE_OFFSET_X(x));
-
- intel_de_write_fw(dev_priv, PLANE_AUX_DIST(pipe, plane_id),
- skl_plane_aux_dist(plane_state, color_plane));
-
- if (DISPLAY_VER(dev_priv) < 11)
- intel_de_write_fw(dev_priv, PLANE_AUX_OFFSET(pipe, plane_id),
- PLANE_OFFSET_Y(plane_state->view.color_plane[1].y) |
- PLANE_OFFSET_X(plane_state->view.color_plane[1].x));
-
- if (DISPLAY_VER(dev_priv) >= 10)
- intel_de_write_fw(dev_priv, PLANE_COLOR_CTL(pipe, plane_id), plane_color_ctl);
-
/*
* Enable the scaler before the plane so that we don't
* get a catastrophic underrun even if the two operations
@@ -2160,9 +2269,15 @@ skl_universal_plane_create(struct drm_i915_private *dev_priv,
}
plane->max_stride = skl_plane_max_stride;
- plane->update_noarm = skl_plane_update_noarm;
- plane->update_arm = skl_plane_update_arm;
- plane->disable_arm = skl_plane_disable_arm;
+ if (DISPLAY_VER(dev_priv) >= 11) {
+ plane->update_noarm = icl_plane_update_noarm;
+ plane->update_arm = icl_plane_update_arm;
+ plane->disable_arm = icl_plane_disable_arm;
+ } else {
+ plane->update_noarm = skl_plane_update_noarm;
+ plane->update_arm = skl_plane_update_arm;
+ plane->disable_arm = skl_plane_disable_arm;
+ }
plane->get_hw_state = skl_plane_get_hw_state;
plane->check_plane = skl_plane_check;
--
2.32.0
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [Intel-gfx] [PATCH 3/6] drm/i915: Make skl+ universal plane registers unlocked
2022-01-21 11:30 [Intel-gfx] [PATCH 0/6] drm/i915: Futher optimize plane updates Ville Syrjala
2022-01-21 11:30 ` [Intel-gfx] [PATCH 1/6] drm/i915: Clean up pre-skl primary plane registers Ville Syrjala
2022-01-21 11:30 ` [Intel-gfx] [PATCH 2/6] drm/i915: Optimize icl+ universal plane programming Ville Syrjala
@ 2022-01-21 11:30 ` Ville Syrjala
2022-01-21 11:30 ` [Intel-gfx] [PATCH 4/6] drm/i915: Make cursor " Ville Syrjala
` (6 subsequent siblings)
9 siblings, 0 replies; 12+ messages in thread
From: Ville Syrjala @ 2022-01-21 11:30 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Drop the locks around most universal plane register writes.
The lock isn't needed since each plane's register are neatly
contained on their own cachelines.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
.../drm/i915/display/skl_universal_plane.c | 35 -------------------
1 file changed, 35 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
index 07c64ea5b362..c2596b6aa3ab 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
@@ -615,16 +615,11 @@ skl_plane_disable_arm(struct intel_plane *plane,
struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
enum plane_id plane_id = plane->id;
enum pipe pipe = plane->pipe;
- unsigned long irqflags;
-
- spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
skl_write_plane_wm(plane, crtc_state);
intel_de_write_fw(dev_priv, PLANE_CTL(pipe, plane_id), 0);
intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id), 0);
-
- spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
}
static void
@@ -634,9 +629,6 @@ icl_plane_disable_arm(struct intel_plane *plane,
struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
enum plane_id plane_id = plane->id;
enum pipe pipe = plane->pipe;
- unsigned long irqflags;
-
- spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
if (icl_is_hdr_plane(dev_priv, plane_id))
intel_de_write_fw(dev_priv, PLANE_CUS_CTL(pipe, plane_id), 0);
@@ -646,8 +638,6 @@ icl_plane_disable_arm(struct intel_plane *plane,
intel_psr2_disable_plane_sel_fetch(plane, crtc_state);
intel_de_write_fw(dev_priv, PLANE_CTL(pipe, plane_id), 0);
intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id), 0);
-
- spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
}
static bool
@@ -1105,7 +1095,6 @@ skl_plane_update_noarm(struct intel_plane *plane,
int crtc_y = plane_state->uapi.dst.y1;
u32 src_w = drm_rect_width(&plane_state->uapi.src) >> 16;
u32 src_h = drm_rect_height(&plane_state->uapi.src) >> 16;
- unsigned long irqflags;
/* The scaler will handle the output position */
if (plane_state->scaler_id >= 0) {
@@ -1113,8 +1102,6 @@ skl_plane_update_noarm(struct intel_plane *plane,
crtc_y = 0;
}
- spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
-
intel_de_write_fw(dev_priv, PLANE_STRIDE(pipe, plane_id),
PLANE_STRIDE_(stride));
intel_de_write_fw(dev_priv, PLANE_POS(pipe, plane_id),
@@ -1123,8 +1110,6 @@ skl_plane_update_noarm(struct intel_plane *plane,
PLANE_HEIGHT(src_h - 1) | PLANE_WIDTH(src_w - 1));
skl_write_plane_wm(plane, crtc_state);
-
- spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
}
static void
@@ -1138,7 +1123,6 @@ skl_plane_update_arm(struct intel_plane *plane,
u32 x = plane_state->view.color_plane[0].x;
u32 y = plane_state->view.color_plane[0].y;
u32 plane_ctl, plane_color_ctl = 0;
- unsigned long irqflags;
plane_ctl = plane_state->ctl |
skl_plane_ctl_crtc(crtc_state);
@@ -1147,8 +1131,6 @@ skl_plane_update_arm(struct intel_plane *plane,
plane_color_ctl = plane_state->color_ctl |
glk_plane_color_ctl_crtc(crtc_state);
- spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
-
intel_de_write_fw(dev_priv, PLANE_KEYVAL(pipe, plane_id), skl_plane_keyval(plane_state));
intel_de_write_fw(dev_priv, PLANE_KEYMSK(pipe, plane_id), skl_plane_keymsk(plane_state));
intel_de_write_fw(dev_priv, PLANE_KEYMAX(pipe, plane_id), skl_plane_keymax(plane_state));
@@ -1184,8 +1166,6 @@ skl_plane_update_arm(struct intel_plane *plane,
intel_de_write_fw(dev_priv, PLANE_CTL(pipe, plane_id), plane_ctl);
intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id),
skl_plane_surf(plane_state, 0));
-
- spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
}
static void
@@ -1206,7 +1186,6 @@ icl_plane_update_noarm(struct intel_plane *plane,
int src_w = drm_rect_width(&plane_state->uapi.src) >> 16;
int src_h = drm_rect_height(&plane_state->uapi.src) >> 16;
u32 plane_color_ctl;
- unsigned long irqflags;
plane_color_ctl = plane_state->color_ctl |
glk_plane_color_ctl_crtc(crtc_state);
@@ -1217,8 +1196,6 @@ icl_plane_update_noarm(struct intel_plane *plane,
crtc_y = 0;
}
- spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
-
intel_de_write_fw(dev_priv, PLANE_STRIDE(pipe, plane_id),
PLANE_STRIDE_(stride));
intel_de_write_fw(dev_priv, PLANE_POS(pipe, plane_id),
@@ -1262,8 +1239,6 @@ icl_plane_update_noarm(struct intel_plane *plane,
icl_plane_csc_load_black(plane);
intel_psr2_program_plane_sel_fetch(plane, crtc_state, plane_state, color_plane);
-
- spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
}
static void
@@ -1276,13 +1251,10 @@ icl_plane_update_arm(struct intel_plane *plane,
enum pipe pipe = plane->pipe;
int color_plane = icl_plane_color_plane(plane_state);
u32 plane_ctl;
- unsigned long irqflags;
plane_ctl = plane_state->ctl |
skl_plane_ctl_crtc(crtc_state);
- spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
-
/*
* Enable the scaler before the plane so that we don't
* get a catastrophic underrun even if the two operations
@@ -1301,8 +1273,6 @@ icl_plane_update_arm(struct intel_plane *plane,
intel_de_write_fw(dev_priv, PLANE_CTL(pipe, plane_id), plane_ctl);
intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id),
skl_plane_surf(plane_state, color_plane));
-
- spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
}
static void
@@ -1312,7 +1282,6 @@ skl_plane_async_flip(struct intel_plane *plane,
bool async_flip)
{
struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
- unsigned long irqflags;
enum plane_id plane_id = plane->id;
enum pipe pipe = plane->pipe;
u32 plane_ctl = plane_state->ctl;
@@ -1322,13 +1291,9 @@ skl_plane_async_flip(struct intel_plane *plane,
if (async_flip)
plane_ctl |= PLANE_CTL_ASYNC_FLIP;
- spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
-
intel_de_write_fw(dev_priv, PLANE_CTL(pipe, plane_id), plane_ctl);
intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id),
skl_plane_surf(plane_state, 0));
-
- spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
}
static bool intel_format_is_p01x(u32 format)
--
2.32.0
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [Intel-gfx] [PATCH 4/6] drm/i915: Make cursor plane registers unlocked
2022-01-21 11:30 [Intel-gfx] [PATCH 0/6] drm/i915: Futher optimize plane updates Ville Syrjala
` (2 preceding siblings ...)
2022-01-21 11:30 ` [Intel-gfx] [PATCH 3/6] drm/i915: Make skl+ universal plane registers unlocked Ville Syrjala
@ 2022-01-21 11:30 ` Ville Syrjala
2022-01-21 11:30 ` [Intel-gfx] [PATCH 5/6] drm/i915: Make most pre-skl primary " Ville Syrjala
` (5 subsequent siblings)
9 siblings, 0 replies; 12+ messages in thread
From: Ville Syrjala @ 2022-01-21 11:30 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Drop the locks around cursor plane register writes. The
lock isn't needed since each plane's register are neatly
contained on their own cachelines.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_cursor.c | 10 ----------
1 file changed, 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cursor.c b/drivers/gpu/drm/i915/display/intel_cursor.c
index 2ade8fdd9bdd..625c1fb68273 100644
--- a/drivers/gpu/drm/i915/display/intel_cursor.c
+++ b/drivers/gpu/drm/i915/display/intel_cursor.c
@@ -255,7 +255,6 @@ static void i845_cursor_update_arm(struct intel_plane *plane,
{
struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
u32 cntl = 0, base = 0, pos = 0, size = 0;
- unsigned long irqflags;
if (plane_state && plane_state->uapi.visible) {
unsigned int width = drm_rect_width(&plane_state->uapi.dst);
@@ -270,8 +269,6 @@ static void i845_cursor_update_arm(struct intel_plane *plane,
pos = intel_cursor_position(plane_state);
}
- spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
-
/* On these chipsets we can only modify the base/size/stride
* whilst the cursor is disabled.
*/
@@ -290,8 +287,6 @@ static void i845_cursor_update_arm(struct intel_plane *plane,
} else {
intel_de_write_fw(dev_priv, CURPOS(PIPE_A), pos);
}
-
- spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
}
static void i845_cursor_disable_arm(struct intel_plane *plane,
@@ -492,7 +487,6 @@ static void i9xx_cursor_update_arm(struct intel_plane *plane,
struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
enum pipe pipe = plane->pipe;
u32 cntl = 0, base = 0, pos = 0, fbc_ctl = 0;
- unsigned long irqflags;
if (plane_state && plane_state->uapi.visible) {
int width = drm_rect_width(&plane_state->uapi.dst);
@@ -508,8 +502,6 @@ static void i9xx_cursor_update_arm(struct intel_plane *plane,
pos = intel_cursor_position(plane_state);
}
- spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
-
/*
* On some platforms writing CURCNTR first will also
* cause CURPOS to be armed by the CURBASE write.
@@ -555,8 +547,6 @@ static void i9xx_cursor_update_arm(struct intel_plane *plane,
intel_de_write_fw(dev_priv, CURPOS(pipe), pos);
intel_de_write_fw(dev_priv, CURBASE(pipe), base);
}
-
- spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
}
static void i9xx_cursor_disable_arm(struct intel_plane *plane,
--
2.32.0
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [Intel-gfx] [PATCH 5/6] drm/i915: Make most pre-skl primary plane registers unlocked
2022-01-21 11:30 [Intel-gfx] [PATCH 0/6] drm/i915: Futher optimize plane updates Ville Syrjala
` (3 preceding siblings ...)
2022-01-21 11:30 ` [Intel-gfx] [PATCH 4/6] drm/i915: Make cursor " Ville Syrjala
@ 2022-01-21 11:30 ` Ville Syrjala
2022-01-21 11:30 ` [Intel-gfx] [PATCH 6/6] drm/i915: Make pre-skl sprite " Ville Syrjala
` (4 subsequent siblings)
9 siblings, 0 replies; 12+ messages in thread
From: Ville Syrjala @ 2022-01-21 11:30 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Drop the locks around most primary plane register writes.
The lock isn't needed since each plane's register are neatly
contained on their own cachelines.
The one exception we have to make is DSPADDR/DSPSURF which is
(ab)used to also trigger FBC nukes on pre-snb (since the
hardware doesn't seem to have any dedicated mechanism to
trigger nukes). So we need to keep the lock around it to
protect against the rmw performed by the fbc code.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/i9xx_plane.c | 24 +++++++++--------------
1 file changed, 9 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c b/drivers/gpu/drm/i915/display/i9xx_plane.c
index 54f8776ca6b3..bab1027a11f3 100644
--- a/drivers/gpu/drm/i915/display/i9xx_plane.c
+++ b/drivers/gpu/drm/i915/display/i9xx_plane.c
@@ -418,9 +418,6 @@ static void i9xx_plane_update_noarm(struct intel_plane *plane,
{
struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
- unsigned long irqflags;
-
- spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
intel_de_write_fw(dev_priv, DSPSTRIDE(i9xx_plane),
plane_state->view.color_plane[0].mapping_stride);
@@ -441,8 +438,6 @@ static void i9xx_plane_update_noarm(struct intel_plane *plane,
intel_de_write_fw(dev_priv, DSPSIZE(i9xx_plane),
DISP_HEIGHT(crtc_h - 1) | DISP_WIDTH(crtc_w - 1));
}
-
- spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
}
static void i9xx_plane_update_arm(struct intel_plane *plane,
@@ -465,8 +460,6 @@ static void i9xx_plane_update_arm(struct intel_plane *plane,
else
dspaddr_offset = linear_offset;
- spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
-
if (IS_CHERRYVIEW(dev_priv) && i9xx_plane == PLANE_B) {
int crtc_x = plane_state->uapi.dst.x1;
int crtc_y = plane_state->uapi.dst.y1;
@@ -496,13 +489,15 @@ static void i9xx_plane_update_arm(struct intel_plane *plane,
* the control register just before the surface register.
*/
intel_de_write_fw(dev_priv, DSPCNTR(i9xx_plane), dspcntr);
+
+ /* lock to protect against rmw in fbc nuke */
+ spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
if (DISPLAY_VER(dev_priv) >= 4)
intel_de_write_fw(dev_priv, DSPSURF(i9xx_plane),
intel_plane_ggtt_offset(plane_state) + dspaddr_offset);
else
intel_de_write_fw(dev_priv, DSPADDR(i9xx_plane),
intel_plane_ggtt_offset(plane_state) + dspaddr_offset);
-
spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
}
@@ -540,14 +535,14 @@ static void i9xx_plane_disable_arm(struct intel_plane *plane,
*/
dspcntr = i9xx_plane_ctl_crtc(crtc_state);
- spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
-
intel_de_write_fw(dev_priv, DSPCNTR(i9xx_plane), dspcntr);
+
+ /* lock to protect against rmw in fbc nuke */
+ spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
if (DISPLAY_VER(dev_priv) >= 4)
intel_de_write_fw(dev_priv, DSPSURF(i9xx_plane), 0);
else
intel_de_write_fw(dev_priv, DSPADDR(i9xx_plane), 0);
-
spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
}
@@ -566,8 +561,10 @@ g4x_primary_async_flip(struct intel_plane *plane,
if (async_flip)
dspcntr |= DISP_ASYNC_FLIP;
- spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
intel_de_write_fw(dev_priv, DSPCNTR(i9xx_plane), dspcntr);
+
+ /* lock to protect against rmw in fbc nuke */
+ spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
intel_de_write_fw(dev_priv, DSPSURF(i9xx_plane),
intel_plane_ggtt_offset(plane_state) + dspaddr_offset);
spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
@@ -582,12 +579,9 @@ vlv_primary_async_flip(struct intel_plane *plane,
struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
u32 dspaddr_offset = plane_state->view.color_plane[0].offset;
enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
- unsigned long irqflags;
- spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
intel_de_write_fw(dev_priv, DSPADDR_VLV(i9xx_plane),
intel_plane_ggtt_offset(plane_state) + dspaddr_offset);
- spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
}
static void
--
2.32.0
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [Intel-gfx] [PATCH 6/6] drm/i915: Make pre-skl sprite plane registers unlocked
2022-01-21 11:30 [Intel-gfx] [PATCH 0/6] drm/i915: Futher optimize plane updates Ville Syrjala
` (4 preceding siblings ...)
2022-01-21 11:30 ` [Intel-gfx] [PATCH 5/6] drm/i915: Make most pre-skl primary " Ville Syrjala
@ 2022-01-21 11:30 ` Ville Syrjala
2022-01-21 12:44 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: Futher optimize plane updates Patchwork
` (3 subsequent siblings)
9 siblings, 0 replies; 12+ messages in thread
From: Ville Syrjala @ 2022-01-21 11:30 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Drop the locks around sprite plane register writes. The
lock isn't needed since each plane's register are neatly
contained on their own cachelines.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_sprite.c | 45 ---------------------
1 file changed, 45 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
index 7ffca5669ab9..0376fc48c011 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite.c
+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
@@ -429,9 +429,6 @@ vlv_sprite_update_noarm(struct intel_plane *plane,
int crtc_y = plane_state->uapi.dst.y1;
u32 crtc_w = drm_rect_width(&plane_state->uapi.dst);
u32 crtc_h = drm_rect_height(&plane_state->uapi.dst);
- unsigned long irqflags;
-
- spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
intel_de_write_fw(dev_priv, SPSTRIDE(pipe, plane_id),
plane_state->view.color_plane[0].mapping_stride);
@@ -439,8 +436,6 @@ vlv_sprite_update_noarm(struct intel_plane *plane,
SP_POS_Y(crtc_y) | SP_POS_X(crtc_x));
intel_de_write_fw(dev_priv, SPSIZE(pipe, plane_id),
SP_HEIGHT(crtc_h - 1) | SP_WIDTH(crtc_w - 1));
-
- spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
}
static void
@@ -456,14 +451,11 @@ vlv_sprite_update_arm(struct intel_plane *plane,
u32 x = plane_state->view.color_plane[0].x;
u32 y = plane_state->view.color_plane[0].y;
u32 sprctl, linear_offset;
- unsigned long irqflags;
sprctl = plane_state->ctl | vlv_sprite_ctl_crtc(crtc_state);
linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
- spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
-
if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B)
chv_sprite_update_csc(plane_state);
@@ -493,8 +485,6 @@ vlv_sprite_update_arm(struct intel_plane *plane,
vlv_sprite_update_clrc(plane_state);
vlv_sprite_update_gamma(plane_state);
-
- spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
}
static void
@@ -504,14 +494,9 @@ vlv_sprite_disable_arm(struct intel_plane *plane,
struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
enum pipe pipe = plane->pipe;
enum plane_id plane_id = plane->id;
- unsigned long irqflags;
-
- spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
intel_de_write_fw(dev_priv, SPCNTR(pipe, plane_id), 0);
intel_de_write_fw(dev_priv, SPSURF(pipe, plane_id), 0);
-
- spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
}
static bool
@@ -861,15 +846,12 @@ ivb_sprite_update_noarm(struct intel_plane *plane,
u32 src_w = drm_rect_width(&plane_state->uapi.src) >> 16;
u32 src_h = drm_rect_height(&plane_state->uapi.src) >> 16;
u32 sprscale = 0;
- unsigned long irqflags;
if (crtc_w != src_w || crtc_h != src_h)
sprscale = SPRITE_SCALE_ENABLE |
SPRITE_SRC_WIDTH(src_w - 1) |
SPRITE_SRC_HEIGHT(src_h - 1);
- spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
-
intel_de_write_fw(dev_priv, SPRSTRIDE(pipe),
plane_state->view.color_plane[0].mapping_stride);
intel_de_write_fw(dev_priv, SPRPOS(pipe),
@@ -878,8 +860,6 @@ ivb_sprite_update_noarm(struct intel_plane *plane,
SPRITE_HEIGHT(crtc_h - 1) | SPRITE_WIDTH(crtc_w - 1));
if (IS_IVYBRIDGE(dev_priv))
intel_de_write_fw(dev_priv, SPRSCALE(pipe), sprscale);
-
- spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
}
static void
@@ -894,14 +874,11 @@ ivb_sprite_update_arm(struct intel_plane *plane,
u32 x = plane_state->view.color_plane[0].x;
u32 y = plane_state->view.color_plane[0].y;
u32 sprctl, linear_offset;
- unsigned long irqflags;
sprctl = plane_state->ctl | ivb_sprite_ctl_crtc(crtc_state);
linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
- spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
-
if (key->flags) {
intel_de_write_fw(dev_priv, SPRKEYVAL(pipe), key->min_value);
intel_de_write_fw(dev_priv, SPRKEYMSK(pipe),
@@ -930,8 +907,6 @@ ivb_sprite_update_arm(struct intel_plane *plane,
intel_plane_ggtt_offset(plane_state) + sprsurf_offset);
ivb_sprite_update_gamma(plane_state);
-
- spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
}
static void
@@ -940,17 +915,12 @@ ivb_sprite_disable_arm(struct intel_plane *plane,
{
struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
enum pipe pipe = plane->pipe;
- unsigned long irqflags;
-
- spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
intel_de_write_fw(dev_priv, SPRCTL(pipe), 0);
/* Disable the scaler */
if (IS_IVYBRIDGE(dev_priv))
intel_de_write_fw(dev_priv, SPRSCALE(pipe), 0);
intel_de_write_fw(dev_priv, SPRSURF(pipe), 0);
-
- spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
}
static bool
@@ -1203,15 +1173,12 @@ g4x_sprite_update_noarm(struct intel_plane *plane,
u32 src_w = drm_rect_width(&plane_state->uapi.src) >> 16;
u32 src_h = drm_rect_height(&plane_state->uapi.src) >> 16;
u32 dvsscale = 0;
- unsigned long irqflags;
if (crtc_w != src_w || crtc_h != src_h)
dvsscale = DVS_SCALE_ENABLE |
DVS_SRC_WIDTH(src_w - 1) |
DVS_SRC_HEIGHT(src_h - 1);
- spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
-
intel_de_write_fw(dev_priv, DVSSTRIDE(pipe),
plane_state->view.color_plane[0].mapping_stride);
intel_de_write_fw(dev_priv, DVSPOS(pipe),
@@ -1219,8 +1186,6 @@ g4x_sprite_update_noarm(struct intel_plane *plane,
intel_de_write_fw(dev_priv, DVSSIZE(pipe),
DVS_HEIGHT(crtc_h - 1) | DVS_WIDTH(crtc_w - 1));
intel_de_write_fw(dev_priv, DVSSCALE(pipe), dvsscale);
-
- spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
}
static void
@@ -1235,14 +1200,11 @@ g4x_sprite_update_arm(struct intel_plane *plane,
u32 x = plane_state->view.color_plane[0].x;
u32 y = plane_state->view.color_plane[0].y;
u32 dvscntr, linear_offset;
- unsigned long irqflags;
dvscntr = plane_state->ctl | g4x_sprite_ctl_crtc(crtc_state);
linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
- spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
-
if (key->flags) {
intel_de_write_fw(dev_priv, DVSKEYVAL(pipe), key->min_value);
intel_de_write_fw(dev_priv, DVSKEYMSK(pipe),
@@ -1266,8 +1228,6 @@ g4x_sprite_update_arm(struct intel_plane *plane,
g4x_sprite_update_gamma(plane_state);
else
ilk_sprite_update_gamma(plane_state);
-
- spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
}
static void
@@ -1276,16 +1236,11 @@ g4x_sprite_disable_arm(struct intel_plane *plane,
{
struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
enum pipe pipe = plane->pipe;
- unsigned long irqflags;
-
- spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
intel_de_write_fw(dev_priv, DVSCNTR(pipe), 0);
/* Disable the scaler */
intel_de_write_fw(dev_priv, DVSSCALE(pipe), 0);
intel_de_write_fw(dev_priv, DVSSURF(pipe), 0);
-
- spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
}
static bool
--
2.32.0
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: Futher optimize plane updates
2022-01-21 11:30 [Intel-gfx] [PATCH 0/6] drm/i915: Futher optimize plane updates Ville Syrjala
` (5 preceding siblings ...)
2022-01-21 11:30 ` [Intel-gfx] [PATCH 6/6] drm/i915: Make pre-skl sprite " Ville Syrjala
@ 2022-01-21 12:44 ` Patchwork
2022-01-21 13:22 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
` (2 subsequent siblings)
9 siblings, 0 replies; 12+ messages in thread
From: Patchwork @ 2022-01-21 12:44 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Futher optimize plane updates
URL : https://patchwork.freedesktop.org/series/99149/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
^ permalink raw reply [flat|nested] 12+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Futher optimize plane updates
2022-01-21 11:30 [Intel-gfx] [PATCH 0/6] drm/i915: Futher optimize plane updates Ville Syrjala
` (6 preceding siblings ...)
2022-01-21 12:44 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: Futher optimize plane updates Patchwork
@ 2022-01-21 13:22 ` Patchwork
2022-01-21 16:00 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2022-02-09 16:14 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for drm/i915: Futher optimize plane updates (rev2) Patchwork
9 siblings, 0 replies; 12+ messages in thread
From: Patchwork @ 2022-01-21 13:22 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 7430 bytes --]
== Series Details ==
Series: drm/i915: Futher optimize plane updates
URL : https://patchwork.freedesktop.org/series/99149/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11118 -> Patchwork_22055
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22055/index.html
Participating hosts (48 -> 36)
------------------------------
Additional (1): fi-kbl-soraka
Missing (13): fi-ilk-m540 bat-dg1-6 bat-dg1-5 fi-hsw-4200u fi-bsw-cyan bat-adlp-6 bat-adlp-4 fi-ctg-p8600 fi-pnv-d510 bat-rpls-1 fi-bdw-samus bat-jsl-2 bat-jsl-1
Known issues
------------
Here are the changes found in Patchwork_22055 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_exec_fence@basic-busy@bcs0:
- fi-kbl-soraka: NOTRUN -> [SKIP][1] ([fdo#109271]) +8 similar issues
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22055/fi-kbl-soraka/igt@gem_exec_fence@basic-busy@bcs0.html
* igt@gem_exec_suspend@basic-s0@smem:
- fi-tgl-1115g4: [PASS][2] -> [FAIL][3] ([i915#1888])
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11118/fi-tgl-1115g4/igt@gem_exec_suspend@basic-s0@smem.html
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22055/fi-tgl-1115g4/igt@gem_exec_suspend@basic-s0@smem.html
* igt@gem_huc_copy@huc-copy:
- fi-skl-6600u: NOTRUN -> [SKIP][4] ([fdo#109271] / [i915#2190])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22055/fi-skl-6600u/igt@gem_huc_copy@huc-copy.html
- fi-kbl-soraka: NOTRUN -> [SKIP][5] ([fdo#109271] / [i915#2190])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22055/fi-kbl-soraka/igt@gem_huc_copy@huc-copy.html
* igt@gem_lmem_swapping@basic:
- fi-kbl-soraka: NOTRUN -> [SKIP][6] ([fdo#109271] / [i915#4613]) +3 similar issues
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22055/fi-kbl-soraka/igt@gem_lmem_swapping@basic.html
* igt@gem_lmem_swapping@verify-random:
- fi-skl-6600u: NOTRUN -> [SKIP][7] ([fdo#109271] / [i915#4613]) +3 similar issues
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22055/fi-skl-6600u/igt@gem_lmem_swapping@verify-random.html
* igt@i915_selftest@live:
- fi-skl-6600u: NOTRUN -> [INCOMPLETE][8] ([i915#4794])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22055/fi-skl-6600u/igt@i915_selftest@live.html
* igt@i915_selftest@live@gt_pm:
- fi-kbl-soraka: NOTRUN -> [DMESG-FAIL][9] ([i915#1886] / [i915#2291])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22055/fi-kbl-soraka/igt@i915_selftest@live@gt_pm.html
* igt@i915_selftest@live@hangcheck:
- fi-hsw-4770: [PASS][10] -> [INCOMPLETE][11] ([i915#3303])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11118/fi-hsw-4770/igt@i915_selftest@live@hangcheck.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22055/fi-hsw-4770/igt@i915_selftest@live@hangcheck.html
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-kbl-soraka: NOTRUN -> [SKIP][12] ([fdo#109271] / [fdo#111827]) +8 similar issues
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22055/fi-kbl-soraka/igt@kms_chamelium@common-hpd-after-suspend.html
* igt@kms_chamelium@vga-edid-read:
- fi-skl-6600u: NOTRUN -> [SKIP][13] ([fdo#109271] / [fdo#111827]) +8 similar issues
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22055/fi-skl-6600u/igt@kms_chamelium@vga-edid-read.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
- fi-skl-6600u: NOTRUN -> [SKIP][14] ([fdo#109271]) +3 similar issues
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22055/fi-skl-6600u/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
- fi-skl-6600u: NOTRUN -> [SKIP][15] ([fdo#109271] / [i915#533])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22055/fi-skl-6600u/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d.html
- fi-kbl-soraka: NOTRUN -> [SKIP][16] ([fdo#109271] / [i915#533])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22055/fi-kbl-soraka/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d.html
* igt@runner@aborted:
- fi-bdw-5557u: NOTRUN -> [FAIL][17] ([i915#2426] / [i915#4312])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22055/fi-bdw-5557u/igt@runner@aborted.html
- fi-hsw-4770: NOTRUN -> [FAIL][18] ([fdo#109271] / [i915#1436] / [i915#4312])
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22055/fi-hsw-4770/igt@runner@aborted.html
#### Possible fixes ####
* igt@gem_exec_suspend@basic-s3@smem:
- fi-bdw-5557u: [INCOMPLETE][19] ([i915#146]) -> [PASS][20]
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11118/fi-bdw-5557u/igt@gem_exec_suspend@basic-s3@smem.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22055/fi-bdw-5557u/igt@gem_exec_suspend@basic-s3@smem.html
* igt@kms_frontbuffer_tracking@basic:
- fi-cml-u2: [DMESG-WARN][21] ([i915#4269]) -> [PASS][22]
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11118/fi-cml-u2/igt@kms_frontbuffer_tracking@basic.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22055/fi-cml-u2/igt@kms_frontbuffer_tracking@basic.html
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436
[i915#146]: https://gitlab.freedesktop.org/drm/intel/issues/146
[i915#1886]: https://gitlab.freedesktop.org/drm/intel/issues/1886
[i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#2291]: https://gitlab.freedesktop.org/drm/intel/issues/2291
[i915#2426]: https://gitlab.freedesktop.org/drm/intel/issues/2426
[i915#3303]: https://gitlab.freedesktop.org/drm/intel/issues/3303
[i915#4269]: https://gitlab.freedesktop.org/drm/intel/issues/4269
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#4794]: https://gitlab.freedesktop.org/drm/intel/issues/4794
[i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
Build changes
-------------
* Linux: CI_DRM_11118 -> Patchwork_22055
CI-20190529: 20190529
CI_DRM_11118: a8ae2fba8948946087ddc13ec6f4c44b6bcf3c72 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6329: 38f656fdd61119105ecfa2c4dac157cd7dcad204 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_22055: 15e732130874b980597084e6cc85a0a05d1dd88a @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
15e732130874 drm/i915: Make pre-skl sprite plane registers unlocked
f1f82f5f3638 drm/i915: Make most pre-skl primary plane registers unlocked
88627ce4ae5b drm/i915: Make cursor plane registers unlocked
0ebf50b84adb drm/i915: Make skl+ universal plane registers unlocked
b1c93a97170e drm/i915: Optimize icl+ universal plane programming
b957169b7bc6 drm/i915: Clean up pre-skl primary plane registers
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22055/index.html
[-- Attachment #2: Type: text/html, Size: 9481 bytes --]
^ permalink raw reply [flat|nested] 12+ messages in thread
* [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Futher optimize plane updates
2022-01-21 11:30 [Intel-gfx] [PATCH 0/6] drm/i915: Futher optimize plane updates Ville Syrjala
` (7 preceding siblings ...)
2022-01-21 13:22 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
@ 2022-01-21 16:00 ` Patchwork
2022-02-09 16:14 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for drm/i915: Futher optimize plane updates (rev2) Patchwork
9 siblings, 0 replies; 12+ messages in thread
From: Patchwork @ 2022-01-21 16:00 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 30262 bytes --]
== Series Details ==
Series: drm/i915: Futher optimize plane updates
URL : https://patchwork.freedesktop.org/series/99149/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11118_full -> Patchwork_22055_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_22055_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_22055_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Participating hosts (10 -> 10)
------------------------------
No changes in participating hosts
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_22055_full:
### IGT changes ###
#### Possible regressions ####
* igt@kms_cursor_legacy@cursor-vs-flip-atomic-transitions-varying-size:
- shard-iclb: [PASS][1] -> [FAIL][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11118/shard-iclb6/igt@kms_cursor_legacy@cursor-vs-flip-atomic-transitions-varying-size.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22055/shard-iclb7/igt@kms_cursor_legacy@cursor-vs-flip-atomic-transitions-varying-size.html
* igt@perf@stress-open-close:
- shard-iclb: [PASS][3] -> [INCOMPLETE][4]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11118/shard-iclb2/igt@perf@stress-open-close.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22055/shard-iclb5/igt@perf@stress-open-close.html
Known issues
------------
Here are the changes found in Patchwork_22055_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_exec_balancer@parallel-out-fence:
- shard-iclb: [PASS][5] -> [SKIP][6] ([i915#4525]) +1 similar issue
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11118/shard-iclb2/igt@gem_exec_balancer@parallel-out-fence.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22055/shard-iclb5/igt@gem_exec_balancer@parallel-out-fence.html
* igt@gem_exec_capture@pi@bcs0:
- shard-skl: NOTRUN -> [INCOMPLETE][7] ([i915#4547])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22055/shard-skl9/igt@gem_exec_capture@pi@bcs0.html
* igt@gem_exec_fair@basic-deadline:
- shard-skl: NOTRUN -> [FAIL][8] ([i915#2846])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22055/shard-skl4/igt@gem_exec_fair@basic-deadline.html
- shard-glk: [PASS][9] -> [FAIL][10] ([i915#2846])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11118/shard-glk4/igt@gem_exec_fair@basic-deadline.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22055/shard-glk7/igt@gem_exec_fair@basic-deadline.html
- shard-apl: NOTRUN -> [FAIL][11] ([i915#2846])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22055/shard-apl6/igt@gem_exec_fair@basic-deadline.html
* igt@gem_exec_fair@basic-none-share@rcs0:
- shard-iclb: [PASS][12] -> [FAIL][13] ([i915#2842]) +1 similar issue
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11118/shard-iclb8/igt@gem_exec_fair@basic-none-share@rcs0.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22055/shard-iclb7/igt@gem_exec_fair@basic-none-share@rcs0.html
* igt@gem_exec_fair@basic-none@vcs0:
- shard-kbl: [PASS][14] -> [FAIL][15] ([i915#2842]) +1 similar issue
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11118/shard-kbl1/igt@gem_exec_fair@basic-none@vcs0.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22055/shard-kbl7/igt@gem_exec_fair@basic-none@vcs0.html
* igt@gem_exec_fair@basic-none@vcs1:
- shard-iclb: NOTRUN -> [FAIL][16] ([i915#2842])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22055/shard-iclb1/igt@gem_exec_fair@basic-none@vcs1.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-tglb: [PASS][17] -> [FAIL][18] ([i915#2842])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11118/shard-tglb6/igt@gem_exec_fair@basic-pace-share@rcs0.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22055/shard-tglb7/igt@gem_exec_fair@basic-pace-share@rcs0.html
* igt@gem_exec_fair@basic-pace@vcs0:
- shard-kbl: [PASS][19] -> [SKIP][20] ([fdo#109271])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11118/shard-kbl7/igt@gem_exec_fair@basic-pace@vcs0.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22055/shard-kbl3/igt@gem_exec_fair@basic-pace@vcs0.html
* igt@gem_exec_params@no-blt:
- shard-tglb: NOTRUN -> [SKIP][21] ([fdo#109283])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22055/shard-tglb6/igt@gem_exec_params@no-blt.html
* igt@gem_huc_copy@huc-copy:
- shard-tglb: NOTRUN -> [SKIP][22] ([i915#2190])
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22055/shard-tglb6/igt@gem_huc_copy@huc-copy.html
* igt@gem_lmem_swapping@parallel-random:
- shard-skl: NOTRUN -> [SKIP][23] ([fdo#109271] / [i915#4613]) +1 similar issue
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22055/shard-skl4/igt@gem_lmem_swapping@parallel-random.html
* igt@gem_userptr_blits@dmabuf-sync:
- shard-apl: NOTRUN -> [SKIP][24] ([fdo#109271] / [i915#3323])
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22055/shard-apl2/igt@gem_userptr_blits@dmabuf-sync.html
* igt@gem_userptr_blits@vma-merge:
- shard-skl: NOTRUN -> [FAIL][25] ([i915#3318])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22055/shard-skl8/igt@gem_userptr_blits@vma-merge.html
* igt@kms_async_flips@alternate-sync-async-flip:
- shard-glk: [PASS][26] -> [FAIL][27] ([i915#2521])
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11118/shard-glk6/igt@kms_async_flips@alternate-sync-async-flip.html
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22055/shard-glk9/igt@kms_async_flips@alternate-sync-async-flip.html
* igt@kms_big_fb@y-tiled-addfb-size-offset-overflow:
- shard-snb: NOTRUN -> [SKIP][28] ([fdo#109271]) +23 similar issues
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22055/shard-snb4/igt@kms_big_fb@y-tiled-addfb-size-offset-overflow.html
* igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-hflip:
- shard-apl: NOTRUN -> [SKIP][29] ([fdo#109271] / [i915#3777]) +1 similar issue
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22055/shard-apl8/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-hflip.html
* igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-hflip:
- shard-skl: NOTRUN -> [SKIP][30] ([fdo#109271] / [i915#3777]) +2 similar issues
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22055/shard-skl4/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-hflip.html
* igt@kms_ccs@pipe-a-crc-sprite-planes-basic-y_tiled_gen12_rc_ccs:
- shard-apl: NOTRUN -> [SKIP][31] ([fdo#109271]) +93 similar issues
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22055/shard-apl7/igt@kms_ccs@pipe-a-crc-sprite-planes-basic-y_tiled_gen12_rc_ccs.html
* igt@kms_ccs@pipe-b-crc-sprite-planes-basic-y_tiled_gen12_rc_ccs_cc:
- shard-apl: NOTRUN -> [SKIP][32] ([fdo#109271] / [i915#3886]) +4 similar issues
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22055/shard-apl6/igt@kms_ccs@pipe-b-crc-sprite-planes-basic-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_ccs@pipe-c-crc-sprite-planes-basic-y_tiled_gen12_mc_ccs:
- shard-tglb: NOTRUN -> [SKIP][33] ([i915#3689] / [i915#3886])
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22055/shard-tglb8/igt@kms_ccs@pipe-c-crc-sprite-planes-basic-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-c-missing-ccs-buffer-y_tiled_gen12_rc_ccs_cc:
- shard-skl: NOTRUN -> [SKIP][34] ([fdo#109271] / [i915#3886]) +5 similar issues
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22055/shard-skl4/igt@kms_ccs@pipe-c-missing-ccs-buffer-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_chamelium@hdmi-hpd-fast:
- shard-snb: NOTRUN -> [SKIP][35] ([fdo#109271] / [fdo#111827]) +1 similar issue
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22055/shard-snb4/igt@kms_chamelium@hdmi-hpd-fast.html
* igt@kms_color_chamelium@pipe-a-ctm-green-to-red:
- shard-apl: NOTRUN -> [SKIP][36] ([fdo#109271] / [fdo#111827]) +6 similar issues
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22055/shard-apl2/igt@kms_color_chamelium@pipe-a-ctm-green-to-red.html
* igt@kms_color_chamelium@pipe-d-ctm-0-5:
- shard-skl: NOTRUN -> [SKIP][37] ([fdo#109271] / [fdo#111827]) +9 similar issues
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22055/shard-skl4/igt@kms_color_chamelium@pipe-d-ctm-0-5.html
* igt@kms_content_protection@uevent:
- shard-apl: NOTRUN -> [FAIL][38] ([i915#2105])
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22055/shard-apl7/igt@kms_content_protection@uevent.html
* igt@kms_cursor_crc@pipe-b-cursor-32x32-onscreen:
- shard-skl: NOTRUN -> [SKIP][39] ([fdo#109271]) +165 similar issues
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22055/shard-skl4/igt@kms_cursor_crc@pipe-b-cursor-32x32-onscreen.html
* igt@kms_cursor_crc@pipe-d-cursor-32x10-sliding:
- shard-tglb: NOTRUN -> [SKIP][40] ([i915#3359])
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22055/shard-tglb6/igt@kms_cursor_crc@pipe-d-cursor-32x10-sliding.html
* igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@ab-hdmi-a1-hdmi-a2:
- shard-glk: [PASS][41] -> [FAIL][42] ([i915#79]) +1 similar issue
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11118/shard-glk5/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@ab-hdmi-a1-hdmi-a2.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22055/shard-glk3/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@ab-hdmi-a1-hdmi-a2.html
* igt@kms_flip@2x-flip-vs-modeset-vs-hang:
- shard-kbl: NOTRUN -> [SKIP][43] ([fdo#109271]) +4 similar issues
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22055/shard-kbl6/igt@kms_flip@2x-flip-vs-modeset-vs-hang.html
* igt@kms_flip@flip-vs-expired-vblank@b-edp1:
- shard-skl: [PASS][44] -> [FAIL][45] ([i915#79])
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11118/shard-skl6/igt@kms_flip@flip-vs-expired-vblank@b-edp1.html
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22055/shard-skl4/igt@kms_flip@flip-vs-expired-vblank@b-edp1.html
* igt@kms_flip@flip-vs-suspend@c-dp1:
- shard-kbl: [PASS][46] -> [DMESG-WARN][47] ([i915#180]) +9 similar issues
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11118/shard-kbl3/igt@kms_flip@flip-vs-suspend@c-dp1.html
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22055/shard-kbl1/igt@kms_flip@flip-vs-suspend@c-dp1.html
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-indfb-plflip-blt:
- shard-tglb: NOTRUN -> [SKIP][48] ([fdo#109280] / [fdo#111825]) +2 similar issues
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22055/shard-tglb6/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-indfb-plflip-blt.html
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c:
- shard-apl: [PASS][49] -> [DMESG-WARN][50] ([i915#180]) +3 similar issues
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11118/shard-apl6/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22055/shard-apl3/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c.html
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-d:
- shard-skl: NOTRUN -> [SKIP][51] ([fdo#109271] / [i915#533]) +2 similar issues
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22055/shard-skl4/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-d.html
- shard-apl: NOTRUN -> [SKIP][52] ([fdo#109271] / [i915#533]) +1 similar issue
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22055/shard-apl6/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-d.html
* igt@kms_plane_alpha_blend@pipe-b-constant-alpha-max:
- shard-skl: NOTRUN -> [FAIL][53] ([fdo#108145] / [i915#265])
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22055/shard-skl4/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-max.html
* igt@kms_plane_alpha_blend@pipe-c-alpha-basic:
- shard-apl: NOTRUN -> [FAIL][54] ([fdo#108145] / [i915#265])
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22055/shard-apl2/igt@kms_plane_alpha_blend@pipe-c-alpha-basic.html
* igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area:
- shard-skl: NOTRUN -> [SKIP][55] ([fdo#109271] / [i915#658])
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22055/shard-skl4/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area.html
* igt@kms_psr2_su@page_flip-p010:
- shard-apl: NOTRUN -> [SKIP][56] ([fdo#109271] / [i915#658])
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22055/shard-apl2/igt@kms_psr2_su@page_flip-p010.html
* igt@kms_psr@psr2_cursor_render:
- shard-iclb: [PASS][57] -> [SKIP][58] ([fdo#109441]) +2 similar issues
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11118/shard-iclb2/igt@kms_psr@psr2_cursor_render.html
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22055/shard-iclb5/igt@kms_psr@psr2_cursor_render.html
* igt@kms_writeback@writeback-pixel-formats:
- shard-apl: NOTRUN -> [SKIP][59] ([fdo#109271] / [i915#2437])
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22055/shard-apl8/igt@kms_writeback@writeback-pixel-formats.html
* igt@prime_nv_pcopy@test3_1:
- shard-tglb: NOTRUN -> [SKIP][60] ([fdo#109291])
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22055/shard-tglb6/igt@prime_nv_pcopy@test3_1.html
* igt@sysfs_clients@create:
- shard-apl: NOTRUN -> [SKIP][61] ([fdo#109271] / [i915#2994]) +1 similar issue
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22055/shard-apl6/igt@sysfs_clients@create.html
- shard-skl: NOTRUN -> [SKIP][62] ([fdo#109271] / [i915#2994]) +2 similar issues
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22055/shard-skl4/igt@sysfs_clients@create.html
#### Possible fixes ####
* igt@feature_discovery@psr2:
- shard-iclb: [SKIP][63] ([i915#658]) -> [PASS][64]
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11118/shard-iclb3/igt@feature_discovery@psr2.html
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22055/shard-iclb2/igt@feature_discovery@psr2.html
* igt@gem_exec_balancer@parallel-balancer:
- shard-iclb: [SKIP][65] ([i915#4525]) -> [PASS][66] +1 similar issue
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11118/shard-iclb3/igt@gem_exec_balancer@parallel-balancer.html
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22055/shard-iclb2/igt@gem_exec_balancer@parallel-balancer.html
* igt@gem_exec_capture@pi@rcs0:
- shard-skl: [INCOMPLETE][67] ([i915#4547]) -> [PASS][68]
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11118/shard-skl7/igt@gem_exec_capture@pi@rcs0.html
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22055/shard-skl9/igt@gem_exec_capture@pi@rcs0.html
* igt@gem_exec_fair@basic-pace@vecs0:
- shard-kbl: [FAIL][69] ([i915#2842]) -> [PASS][70]
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11118/shard-kbl7/igt@gem_exec_fair@basic-pace@vecs0.html
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22055/shard-kbl3/igt@gem_exec_fair@basic-pace@vecs0.html
* igt@i915_selftest@live@gt_heartbeat:
- shard-tglb: [INCOMPLETE][71] -> [PASS][72]
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11118/shard-tglb8/igt@i915_selftest@live@gt_heartbeat.html
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22055/shard-tglb6/igt@i915_selftest@live@gt_heartbeat.html
* igt@kms_cursor_legacy@2x-flip-vs-cursor-legacy:
- shard-glk: [FAIL][73] ([i915#72]) -> [PASS][74]
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11118/shard-glk5/igt@kms_cursor_legacy@2x-flip-vs-cursor-legacy.html
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22055/shard-glk3/igt@kms_cursor_legacy@2x-flip-vs-cursor-legacy.html
* igt@kms_fbcon_fbt@fbc-suspend:
- shard-apl: [INCOMPLETE][75] ([i915#180] / [i915#1982]) -> [PASS][76]
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11118/shard-apl2/igt@kms_fbcon_fbt@fbc-suspend.html
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22055/shard-apl8/igt@kms_fbcon_fbt@fbc-suspend.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1:
- shard-skl: [FAIL][77] ([i915#79]) -> [PASS][78] +1 similar issue
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11118/shard-skl10/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1.html
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22055/shard-skl1/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1.html
* igt@kms_flip@flip-vs-expired-vblank@b-hdmi-a2:
- shard-glk: [FAIL][79] ([i915#79]) -> [PASS][80]
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11118/shard-glk5/igt@kms_flip@flip-vs-expired-vblank@b-hdmi-a2.html
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22055/shard-glk3/igt@kms_flip@flip-vs-expired-vblank@b-hdmi-a2.html
* igt@kms_flip@flip-vs-fences-interruptible@a-vga1:
- shard-snb: [DMESG-WARN][81] -> [PASS][82]
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11118/shard-snb2/igt@kms_flip@flip-vs-fences-interruptible@a-vga1.html
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22055/shard-snb4/igt@kms_flip@flip-vs-fences-interruptible@a-vga1.html
* igt@kms_flip@flip-vs-fences-interruptible@b-vga1:
- shard-snb: [INCOMPLETE][83] -> [PASS][84]
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11118/shard-snb2/igt@kms_flip@flip-vs-fences-interruptible@b-vga1.html
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22055/shard-snb4/igt@kms_flip@flip-vs-fences-interruptible@b-vga1.html
* igt@kms_flip@flip-vs-suspend-interruptible@a-dp1:
- shard-kbl: [DMESG-WARN][85] ([i915#180]) -> [PASS][86] +3 similar issues
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11118/shard-kbl4/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22055/shard-kbl3/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html
* igt@kms_flip@flip-vs-suspend-interruptible@c-dp1:
- shard-apl: [DMESG-WARN][87] ([i915#180]) -> [PASS][88] +3 similar issues
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11118/shard-apl2/igt@kms_flip@flip-vs-suspend-interruptible@c-dp1.html
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22055/shard-apl7/igt@kms_flip@flip-vs-suspend-interruptible@c-dp1.html
* igt@kms_flip@plain-flip-fb-recreate@b-edp1:
- shard-skl: [FAIL][89] ([i915#2122]) -> [PASS][90] +1 similar issue
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11118/shard-skl8/igt@kms_flip@plain-flip-fb-recreate@b-edp1.html
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22055/shard-skl6/igt@kms_flip@plain-flip-fb-recreate@b-edp1.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-downscaling:
- shard-iclb: [SKIP][91] ([i915#3701]) -> [PASS][92]
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11118/shard-iclb2/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-downscaling.html
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22055/shard-iclb6/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-downscaling.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-upscaling:
- shard-glk: [FAIL][93] ([i915#4911]) -> [PASS][94]
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11118/shard-glk8/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-upscaling.html
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22055/shard-glk1/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-upscaling.html
* igt@kms_psr2_su@frontbuffer-xrgb8888:
- shard-iclb: [SKIP][95] ([fdo#109642] / [fdo#111068] / [i915#658]) -> [PASS][96]
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11118/shard-iclb3/igt@kms_psr2_su@frontbuffer-xrgb8888.html
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22055/shard-iclb2/igt@kms_psr2_su@frontbuffer-xrgb8888.html
* igt@kms_psr@psr2_primary_page_flip:
- shard-iclb: [SKIP][97] ([fdo#109441]) -> [PASS][98] +2 similar issues
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11118/shard-iclb4/igt@kms_psr@psr2_primary_page_flip.html
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22055/shard-iclb2/igt@kms_psr@psr2_primary_page_flip.html
* igt@kms_setmode@basic:
- shard-apl: [FAIL][99] ([i915#31]) -> [PASS][100]
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11118/shard-apl1/igt@kms_setmode@basic.html
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22055/shard-apl2/igt@kms_setmode@basic.html
- shard-glk: [FAIL][101] ([i915#31]) -> [PASS][102]
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11118/shard-glk4/igt@kms_setmode@basic.html
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22055/shard-glk7/igt@kms_setmode@basic.html
* igt@syncobj_wait@wait-all-for-submit-snapshot:
- shard-skl: [FAIL][103] -> [PASS][104]
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11118/shard-skl2/igt@syncobj_wait@wait-all-for-submit-snapshot.html
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22055/shard-skl8/igt@syncobj_wait@wait-all-for-submit-snapshot.html
* igt@sysfs_timeslice_duration@timeout@rcs0:
- shard-skl: [FAIL][105] ([i915#3259]) -> [PASS][106]
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11118/shard-skl9/igt@sysfs_timeslice_duration@timeout@rcs0.html
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22055/shard-skl6/igt@sysfs_timeslice_duration@timeout@rcs0.html
#### Warnings ####
* igt@gem_exec_balancer@parallel-ordering:
- shard-iclb: [SKIP][107] ([i915#4525]) -> [FAIL][108] ([i915#4916])
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11118/shard-iclb8/igt@gem_exec_balancer@parallel-ordering.html
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22055/shard-iclb1/igt@gem_exec_balancer@parallel-ordering.html
* igt@gem_exec_fair@basic-none-rrul@rcs0:
- shard-iclb: [FAIL][109] ([i915#2852]) -> [FAIL][110] ([i915#2842])
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11118/shard-iclb2/igt@gem_exec_fair@basic-none-rrul@rcs0.html
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22055/shard-iclb6/igt@gem_exec_fair@basic-none-rrul@rcs0.html
* igt@i915_pm_rc6_residency@rc6-idle:
- shard-iclb: [WARN][111] ([i915#1804] / [i915#2684]) -> [WARN][112] ([i915#2684])
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11118/shard-iclb3/igt@i915_pm_rc6_residency@rc6-idle.html
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22055/shard-iclb2/igt@i915_pm_rc6_residency@rc6-idle.html
* igt@kms_flip@flip-vs-suspend-interruptible@b-dp1:
- shard-kbl: [DMESG-WARN][113] ([i915#180]) -> [INCOMPLETE][114] ([i915#3614])
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11118/shard-kbl4/igt@kms_flip@flip-vs-suspend-interruptible@b-dp1.html
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22055/shard-kbl3/igt@kms_flip@flip-vs-suspend-interruptible@b-dp1.html
* igt@kms_psr2_sf@cursor-plane-update-sf:
- shard-iclb: [SKIP][115] ([i915#2920]) -> [SKIP][116] ([fdo#111068] / [i915#658])
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11118/shard-iclb2/igt@kms_psr2_sf@cursor-plane-update-sf.html
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22055/shard-iclb5/igt@kms_psr2_sf@cursor-plane-update-sf.html
* igt@kms_psr2_su@page_flip-p010:
- shard-iclb: [SKIP][117] ([fdo#109642] / [fdo#111068] / [i915#658]) -> [FAIL][118] ([i915#4148])
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11118/shard-iclb5/igt@kms_psr2_su@page_flip-p010.html
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22055/shard-iclb2/igt@kms_psr2_su@page_flip-p010.html
* igt@runner@aborted:
- shard-kbl: ([FAIL][119], [FAIL][120], [FAIL][121], [FAIL][122], [FAIL][123], [FAIL][124]) ([i915#1436] / [i915#180] / [i915#1814] / [i915#3002] / [i915#4312]) -> ([FAIL][125], [FAIL][126], [FAIL][127], [FAIL][128], [FAIL][129], [FAIL][130], [FAIL][131], [FAIL][132]) ([i915#1436] / [i915#180] / [i915#1814] / [i915#3002] / [i915#4312] / [i915#602])
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11118/shard-kbl7/igt@runner@aborted.html
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11118/shard-kbl1/igt@runner@aborted.html
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11118/shard-kbl6/igt@runner@aborted.html
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11118/shard-kbl1/igt@runner@aborted.html
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11118/shard-kbl4/igt@runner@aborted.html
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11118/shard-kbl4/igt@runner@aborted.html
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22055/shard-kbl6/igt@runner@aborted.html
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22055/shard-kbl4/igt@runner@aborted.html
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22055/shard-kbl4/igt@runner@aborted.html
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22055/shard-kbl4/igt@runner@aborted.html
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22055/shard-kbl4/igt@runner@aborted.html
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22055/shard-kbl1/igt@runner@aborted.html
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22055/shard-kbl1/igt@runner@aborted.html
[132]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22055/shard-kbl1/igt@runner@aborted.html
- shard-iclb: ([FAIL][133], [FAIL][134]) ([i915#3002] / [i915#4312]) -> ([FAIL][135], [FAIL][136], [FAIL][137]) ([i915#2722] / [i915#3002] / [i915#4312])
[133]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11118/shard-iclb8/igt@runner@aborted.html
[134]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11118/shard-iclb7/igt@runner@aborted.html
[135]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22055/shard-iclb5/igt@runner@aborted.html
[136]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22055/shard-iclb8/igt@runner@aborted.html
[137]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22055/shard-iclb7/igt@runner@aborted.html
- shard-apl: ([FAIL][138], [FAIL][139], [FAIL][140], [FAIL][141], [FAIL][142], [FAIL][143]) ([i915#180] / [i915#1814] / [i915#3002] / [i915#4312]) -> ([FAIL][144], [FAIL][145], [FAIL][146], [FAIL][147], [FAIL][148], [FAIL][149]) ([fdo#109271] / [i915#180] / [i915#1814] / [i915#3002] / [i915#4312])
[138]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11118/shard-apl2/igt@runner@aborted.html
[139]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11118/shard-apl2/igt@runner@aborted.html
[140]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11118/shard-apl2/igt@runner@aborted.html
[141]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11118/shard-apl7/igt@runner@aborted.html
[142]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11118/shard-apl2/igt@runner@aborted.html
[143]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11118/shard-apl1/igt@runner@aborted.html
[144]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22055/shard-apl2/igt@runner@aborted.html
[145]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22055/shard-apl3/igt@runner@aborted.html
[146]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22055/shard-apl8/igt@runner@aborted.html
[147]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22055/shard-apl6/igt@runner@aborted.html
[148]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22055/shard-apl8/igt@runner@aborted.html
[149]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22055/shard-apl3/igt@runner@aborted.html
- shard-skl: ([FAIL][150], [FAIL][151], [FAIL][152], [FAIL][153]) ([i915#2029] / [i915#3002] / [i915#4312]) -> ([FAIL][154], [FAIL][155], [FAIL][156]) ([i915#3002] / [i915#4312])
[150]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11118/shard-skl7/igt@runner@aborted.html
[151]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11118/shard-skl6/igt@runner@aborted.html
[152]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11118/shard-skl5/igt@runner@aborted.html
[153]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11118/shard-skl4/igt@runner@aborted.html
[154]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22055/shard-skl2/igt@runner@aborted.html
[155]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22055/shard-skl9/igt@runner@aborted.html
[156]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22055/shard-skl9/igt@runner@aborted.html
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280
[fdo#109283]: https://bugs.freedesktop.org/show_bug.cgi?id=109283
[fdo#10929
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22055/index.html
[-- Attachment #2: Type: text/html, Size: 34805 bytes --]
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [Intel-gfx] [PATCH 1/6] drm/i915: Clean up pre-skl primary plane registers
2022-01-21 11:30 ` [Intel-gfx] [PATCH 1/6] drm/i915: Clean up pre-skl primary plane registers Ville Syrjala
@ 2022-01-21 17:23 ` Souza, Jose
0 siblings, 0 replies; 12+ messages in thread
From: Souza, Jose @ 2022-01-21 17:23 UTC (permalink / raw)
To: ville.syrjala, intel-gfx
On Fri, 2022-01-21 at 13:30 +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Use REG_BIT() & co. for the pre-skl primary plane registers.
> Also give everything a consistent namespace.
>
> v2: s/DSP/DISP/ to avoid confusion (José)
> Use DISP_WIDTH rather than DISP_POS_X for DSPSIZE (José)
> Deal with gvt
>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
> Cc: José Roberto de Souza <jose.souza@intel.com>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/display/i9xx_plane.c | 99 +++++++++--------
> drivers/gpu/drm/i915/display/intel_display.c | 13 +--
> drivers/gpu/drm/i915/gvt/display.c | 4 +-
> drivers/gpu/drm/i915/gvt/fb_decoder.c | 18 ++--
> drivers/gpu/drm/i915/i915_reg.h | 108 +++++++++++--------
> drivers/gpu/drm/i915/intel_pm.c | 2 +-
> 6 files changed, 128 insertions(+), 116 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c b/drivers/gpu/drm/i915/display/i9xx_plane.c
> index fc6f05146a9f..54f8776ca6b3 100644
> --- a/drivers/gpu/drm/i915/display/i9xx_plane.c
> +++ b/drivers/gpu/drm/i915/display/i9xx_plane.c
> @@ -155,51 +155,51 @@ static u32 i9xx_plane_ctl(const struct intel_crtc_state *crtc_state,
> unsigned int rotation = plane_state->hw.rotation;
> u32 dspcntr;
>
> - dspcntr = DISPLAY_PLANE_ENABLE;
> + dspcntr = DISP_ENABLE;
>
> if (IS_G4X(dev_priv) || IS_IRONLAKE(dev_priv) ||
> IS_SANDYBRIDGE(dev_priv) || IS_IVYBRIDGE(dev_priv))
> - dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
> + dspcntr |= DISP_TRICKLE_FEED_DISABLE;
>
> switch (fb->format->format) {
> case DRM_FORMAT_C8:
> - dspcntr |= DISPPLANE_8BPP;
> + dspcntr |= DISP_FORMAT_8BPP;
> break;
> case DRM_FORMAT_XRGB1555:
> - dspcntr |= DISPPLANE_BGRX555;
> + dspcntr |= DISP_FORMAT_BGRX555;
> break;
> case DRM_FORMAT_ARGB1555:
> - dspcntr |= DISPPLANE_BGRA555;
> + dspcntr |= DISP_FORMAT_BGRA555;
> break;
> case DRM_FORMAT_RGB565:
> - dspcntr |= DISPPLANE_BGRX565;
> + dspcntr |= DISP_FORMAT_BGRX565;
> break;
> case DRM_FORMAT_XRGB8888:
> - dspcntr |= DISPPLANE_BGRX888;
> + dspcntr |= DISP_FORMAT_BGRX888;
> break;
> case DRM_FORMAT_XBGR8888:
> - dspcntr |= DISPPLANE_RGBX888;
> + dspcntr |= DISP_FORMAT_RGBX888;
> break;
> case DRM_FORMAT_ARGB8888:
> - dspcntr |= DISPPLANE_BGRA888;
> + dspcntr |= DISP_FORMAT_BGRA888;
> break;
> case DRM_FORMAT_ABGR8888:
> - dspcntr |= DISPPLANE_RGBA888;
> + dspcntr |= DISP_FORMAT_RGBA888;
> break;
> case DRM_FORMAT_XRGB2101010:
> - dspcntr |= DISPPLANE_BGRX101010;
> + dspcntr |= DISP_FORMAT_BGRX101010;
> break;
> case DRM_FORMAT_XBGR2101010:
> - dspcntr |= DISPPLANE_RGBX101010;
> + dspcntr |= DISP_FORMAT_RGBX101010;
> break;
> case DRM_FORMAT_ARGB2101010:
> - dspcntr |= DISPPLANE_BGRA101010;
> + dspcntr |= DISP_FORMAT_BGRA101010;
> break;
> case DRM_FORMAT_ABGR2101010:
> - dspcntr |= DISPPLANE_RGBA101010;
> + dspcntr |= DISP_FORMAT_RGBA101010;
> break;
> case DRM_FORMAT_XBGR16161616F:
> - dspcntr |= DISPPLANE_RGBX161616;
> + dspcntr |= DISP_FORMAT_RGBX161616;
> break;
> default:
> MISSING_CASE(fb->format->format);
> @@ -208,13 +208,13 @@ static u32 i9xx_plane_ctl(const struct intel_crtc_state *crtc_state,
>
> if (DISPLAY_VER(dev_priv) >= 4 &&
> fb->modifier == I915_FORMAT_MOD_X_TILED)
> - dspcntr |= DISPPLANE_TILED;
> + dspcntr |= DISP_TILED;
>
> if (rotation & DRM_MODE_ROTATE_180)
> - dspcntr |= DISPPLANE_ROTATE_180;
> + dspcntr |= DISP_ROTATE_180;
>
> if (rotation & DRM_MODE_REFLECT_X)
> - dspcntr |= DISPPLANE_MIRROR;
> + dspcntr |= DISP_MIRROR;
>
> return dspcntr;
> }
> @@ -354,13 +354,13 @@ static u32 i9xx_plane_ctl_crtc(const struct intel_crtc_state *crtc_state)
> u32 dspcntr = 0;
>
> if (crtc_state->gamma_enable)
> - dspcntr |= DISPPLANE_GAMMA_ENABLE;
> + dspcntr |= DISP_PIPE_GAMMA_ENABLE;
>
> if (crtc_state->csc_enable)
> - dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
> + dspcntr |= DISP_PIPE_CSC_ENABLE;
>
> if (DISPLAY_VER(dev_priv) < 5)
> - dspcntr |= DISPPLANE_SEL_PIPE(crtc->pipe);
> + dspcntr |= DISP_PIPE_SEL(crtc->pipe);
>
> return dspcntr;
> }
> @@ -437,9 +437,9 @@ static void i9xx_plane_update_noarm(struct intel_plane *plane,
> * program whatever is there.
> */
> intel_de_write_fw(dev_priv, DSPPOS(i9xx_plane),
> - (crtc_y << 16) | crtc_x);
> + DISP_POS_Y(crtc_y) | DISP_POS_X(crtc_x));
> intel_de_write_fw(dev_priv, DSPSIZE(i9xx_plane),
> - ((crtc_h - 1) << 16) | (crtc_w - 1));
> + DISP_HEIGHT(crtc_h - 1) | DISP_WIDTH(crtc_w - 1));
> }
>
> spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
> @@ -474,20 +474,20 @@ static void i9xx_plane_update_arm(struct intel_plane *plane,
> int crtc_h = drm_rect_height(&plane_state->uapi.dst);
>
> intel_de_write_fw(dev_priv, PRIMPOS(i9xx_plane),
> - (crtc_y << 16) | crtc_x);
> + PRIM_POS_Y(crtc_y) | PRIM_POS_X(crtc_x));
> intel_de_write_fw(dev_priv, PRIMSIZE(i9xx_plane),
> - ((crtc_h - 1) << 16) | (crtc_w - 1));
> + PRIM_HEIGHT(crtc_h - 1) | PRIM_WIDTH(crtc_w - 1));
> intel_de_write_fw(dev_priv, PRIMCNSTALPHA(i9xx_plane), 0);
> }
>
> if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
> intel_de_write_fw(dev_priv, DSPOFFSET(i9xx_plane),
> - (y << 16) | x);
> + DISP_OFFSET_Y(y) | DISP_OFFSET_X(x));
> } else if (DISPLAY_VER(dev_priv) >= 4) {
> intel_de_write_fw(dev_priv, DSPLINOFF(i9xx_plane),
> linear_offset);
> intel_de_write_fw(dev_priv, DSPTILEOFF(i9xx_plane),
> - (y << 16) | x);
> + DISP_OFFSET_Y(y) | DISP_OFFSET_X(x));
> }
>
> /*
> @@ -564,7 +564,7 @@ g4x_primary_async_flip(struct intel_plane *plane,
> unsigned long irqflags;
>
> if (async_flip)
> - dspcntr |= DISPPLANE_ASYNC_FLIP;
> + dspcntr |= DISP_ASYNC_FLIP;
>
> spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
> intel_de_write_fw(dev_priv, DSPCNTR(i9xx_plane), dspcntr);
> @@ -696,13 +696,12 @@ static bool i9xx_plane_get_hw_state(struct intel_plane *plane,
>
> val = intel_de_read(dev_priv, DSPCNTR(i9xx_plane));
>
> - ret = val & DISPLAY_PLANE_ENABLE;
> + ret = val & DISP_ENABLE;
>
> if (DISPLAY_VER(dev_priv) >= 5)
> *pipe = plane->pipe;
> else
> - *pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
> - DISPPLANE_SEL_PIPE_SHIFT;
> + *pipe = REG_FIELD_GET(DISP_PIPE_SEL_MASK, val);
>
> intel_display_power_put(dev_priv, power_domain, wakeref);
>
> @@ -958,32 +957,32 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
> static int i9xx_format_to_fourcc(int format)
> {
> switch (format) {
> - case DISPPLANE_8BPP:
> + case DISP_FORMAT_8BPP:
> return DRM_FORMAT_C8;
> - case DISPPLANE_BGRA555:
> + case DISP_FORMAT_BGRA555:
> return DRM_FORMAT_ARGB1555;
> - case DISPPLANE_BGRX555:
> + case DISP_FORMAT_BGRX555:
> return DRM_FORMAT_XRGB1555;
> - case DISPPLANE_BGRX565:
> + case DISP_FORMAT_BGRX565:
> return DRM_FORMAT_RGB565;
> default:
> - case DISPPLANE_BGRX888:
> + case DISP_FORMAT_BGRX888:
> return DRM_FORMAT_XRGB8888;
> - case DISPPLANE_RGBX888:
> + case DISP_FORMAT_RGBX888:
> return DRM_FORMAT_XBGR8888;
> - case DISPPLANE_BGRA888:
> + case DISP_FORMAT_BGRA888:
> return DRM_FORMAT_ARGB8888;
> - case DISPPLANE_RGBA888:
> + case DISP_FORMAT_RGBA888:
> return DRM_FORMAT_ABGR8888;
> - case DISPPLANE_BGRX101010:
> + case DISP_FORMAT_BGRX101010:
> return DRM_FORMAT_XRGB2101010;
> - case DISPPLANE_RGBX101010:
> + case DISP_FORMAT_RGBX101010:
> return DRM_FORMAT_XBGR2101010;
> - case DISPPLANE_BGRA101010:
> + case DISP_FORMAT_BGRA101010:
> return DRM_FORMAT_ARGB2101010;
> - case DISPPLANE_RGBA101010:
> + case DISP_FORMAT_RGBA101010:
> return DRM_FORMAT_ABGR2101010;
> - case DISPPLANE_RGBX161616:
> + case DISP_FORMAT_RGBX161616:
> return DRM_FORMAT_XBGR16161616F;
> }
> }
> @@ -1021,26 +1020,26 @@ i9xx_get_initial_plane_config(struct intel_crtc *crtc,
> val = intel_de_read(dev_priv, DSPCNTR(i9xx_plane));
>
> if (DISPLAY_VER(dev_priv) >= 4) {
> - if (val & DISPPLANE_TILED) {
> + if (val & DISP_TILED) {
> plane_config->tiling = I915_TILING_X;
> fb->modifier = I915_FORMAT_MOD_X_TILED;
> }
>
> - if (val & DISPPLANE_ROTATE_180)
> + if (val & DISP_ROTATE_180)
> plane_config->rotation = DRM_MODE_ROTATE_180;
> }
>
> if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B &&
> - val & DISPPLANE_MIRROR)
> + val & DISP_MIRROR)
> plane_config->rotation |= DRM_MODE_REFLECT_X;
>
> - pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
> + pixel_format = val & DISP_FORMAT_MASK;
> fourcc = i9xx_format_to_fourcc(pixel_format);
> fb->format = drm_format_info(fourcc);
>
> if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
> offset = intel_de_read(dev_priv, DSPOFFSET(i9xx_plane));
> - base = intel_de_read(dev_priv, DSPSURF(i9xx_plane)) & 0xfffff000;
> + base = intel_de_read(dev_priv, DSPSURF(i9xx_plane)) & DISP_ADDR_MASK;
> } else if (DISPLAY_VER(dev_priv) >= 4) {
> if (plane_config->tiling)
> offset = intel_de_read(dev_priv,
> @@ -1048,7 +1047,7 @@ i9xx_get_initial_plane_config(struct intel_crtc *crtc,
> else
> offset = intel_de_read(dev_priv,
> DSPLINOFF(i9xx_plane));
> - base = intel_de_read(dev_priv, DSPSURF(i9xx_plane)) & 0xfffff000;
> + base = intel_de_read(dev_priv, DSPSURF(i9xx_plane)) & DISP_ADDR_MASK;
> } else {
> base = intel_de_read(dev_priv, DSPADDR(i9xx_plane));
> }
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 0964b2403e2d..750aa22ec0a7 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -3543,11 +3543,11 @@ static void i9xx_get_pipe_color_config(struct intel_crtc_state *crtc_state)
>
> tmp = intel_de_read(dev_priv, DSPCNTR(i9xx_plane));
>
> - if (tmp & DISPPLANE_GAMMA_ENABLE)
> + if (tmp & DISP_PIPE_GAMMA_ENABLE)
> crtc_state->gamma_enable = true;
>
> if (!HAS_GMCH(dev_priv) &&
> - tmp & DISPPLANE_PIPE_CSC_ENABLE)
> + tmp & DISP_PIPE_CSC_ENABLE)
> crtc_state->csc_enable = true;
> }
>
> @@ -9995,14 +9995,11 @@ void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
> pipe_name(pipe));
>
> drm_WARN_ON(&dev_priv->drm,
> - intel_de_read(dev_priv, DSPCNTR(PLANE_A)) &
> - DISPLAY_PLANE_ENABLE);
> + intel_de_read(dev_priv, DSPCNTR(PLANE_A)) & DISP_ENABLE);
> drm_WARN_ON(&dev_priv->drm,
> - intel_de_read(dev_priv, DSPCNTR(PLANE_B)) &
> - DISPLAY_PLANE_ENABLE);
> + intel_de_read(dev_priv, DSPCNTR(PLANE_B)) & DISP_ENABLE);
> drm_WARN_ON(&dev_priv->drm,
> - intel_de_read(dev_priv, DSPCNTR(PLANE_C)) &
> - DISPLAY_PLANE_ENABLE);
> + intel_de_read(dev_priv, DSPCNTR(PLANE_C)) & DISP_ENABLE);
> drm_WARN_ON(&dev_priv->drm,
> intel_de_read(dev_priv, CURCNTR(PIPE_A)) & MCURSOR_MODE_MASK);
> drm_WARN_ON(&dev_priv->drm,
> diff --git a/drivers/gpu/drm/i915/gvt/display.c b/drivers/gpu/drm/i915/gvt/display.c
> index 8ce5d2b2e330..4d66fb5fb29f 100644
> --- a/drivers/gpu/drm/i915/gvt/display.c
> +++ b/drivers/gpu/drm/i915/gvt/display.c
> @@ -185,7 +185,7 @@ static void emulate_monitor_status_change(struct intel_vgpu *vgpu)
> for_each_pipe(dev_priv, pipe) {
> vgpu_vreg_t(vgpu, PIPECONF(pipe)) &=
> ~(PIPECONF_ENABLE | I965_PIPECONF_ACTIVE);
> - vgpu_vreg_t(vgpu, DSPCNTR(pipe)) &= ~DISPLAY_PLANE_ENABLE;
> + vgpu_vreg_t(vgpu, DSPCNTR(pipe)) &= ~DISP_ENABLE;
> vgpu_vreg_t(vgpu, SPRCTL(pipe)) &= ~SPRITE_ENABLE;
> vgpu_vreg_t(vgpu, CURCNTR(pipe)) &= ~MCURSOR_MODE_MASK;
> vgpu_vreg_t(vgpu, CURCNTR(pipe)) |= MCURSOR_MODE_DISABLE;
> @@ -496,7 +496,7 @@ static void emulate_monitor_status_change(struct intel_vgpu *vgpu)
>
> /* Disable Primary/Sprite/Cursor plane */
> for_each_pipe(dev_priv, pipe) {
> - vgpu_vreg_t(vgpu, DSPCNTR(pipe)) &= ~DISPLAY_PLANE_ENABLE;
> + vgpu_vreg_t(vgpu, DSPCNTR(pipe)) &= ~DISP_ENABLE;
> vgpu_vreg_t(vgpu, SPRCTL(pipe)) &= ~SPRITE_ENABLE;
> vgpu_vreg_t(vgpu, CURCNTR(pipe)) &= ~MCURSOR_MODE_MASK;
> vgpu_vreg_t(vgpu, CURCNTR(pipe)) |= MCURSOR_MODE_DISABLE;
> diff --git a/drivers/gpu/drm/i915/gvt/fb_decoder.c b/drivers/gpu/drm/i915/gvt/fb_decoder.c
> index 40ace46bad46..f2a216347d77 100644
> --- a/drivers/gpu/drm/i915/gvt/fb_decoder.c
> +++ b/drivers/gpu/drm/i915/gvt/fb_decoder.c
> @@ -83,22 +83,22 @@ static int bdw_format_to_drm(int format)
> int bdw_pixel_formats_index = 6;
>
> switch (format) {
> - case DISPPLANE_8BPP:
> + case DISP_FORMAT_8BPP:
> bdw_pixel_formats_index = 0;
> break;
> - case DISPPLANE_BGRX565:
> + case DISP_FORMAT_BGRX565:
> bdw_pixel_formats_index = 1;
> break;
> - case DISPPLANE_BGRX888:
> + case DISP_FORMAT_BGRX888:
> bdw_pixel_formats_index = 2;
> break;
> - case DISPPLANE_RGBX101010:
> + case DISP_FORMAT_RGBX101010:
> bdw_pixel_formats_index = 3;
> break;
> - case DISPPLANE_BGRX101010:
> + case DISP_FORMAT_BGRX101010:
> bdw_pixel_formats_index = 4;
> break;
> - case DISPPLANE_RGBX888:
> + case DISP_FORMAT_RGBX888:
> bdw_pixel_formats_index = 5;
> break;
>
> @@ -211,7 +211,7 @@ int intel_vgpu_decode_primary_plane(struct intel_vgpu *vgpu,
> return -ENODEV;
>
> val = vgpu_vreg_t(vgpu, DSPCNTR(pipe));
> - plane->enabled = !!(val & DISPLAY_PLANE_ENABLE);
> + plane->enabled = !!(val & DISP_ENABLE);
> if (!plane->enabled)
> return -ENODEV;
>
> @@ -231,8 +231,8 @@ int intel_vgpu_decode_primary_plane(struct intel_vgpu *vgpu,
> plane->bpp = skl_pixel_formats[fmt].bpp;
> plane->drm_format = skl_pixel_formats[fmt].drm_format;
> } else {
> - plane->tiled = val & DISPPLANE_TILED;
> - fmt = bdw_format_to_drm(val & DISPPLANE_PIXFORMAT_MASK);
> + plane->tiled = val & DISP_TILED;
> + fmt = bdw_format_to_drm(val & DISP_FORMAT_MASK);
> plane->bpp = bdw_pixel_formats[fmt].bpp;
> plane->drm_format = bdw_pixel_formats[fmt].drm_format;
> }
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 460bce5c544d..1328d00ddfe8 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -5900,49 +5900,54 @@ enum {
> /* Display A control */
> #define _DSPAADDR_VLV 0x7017C /* vlv/chv */
> #define _DSPACNTR 0x70180
> -#define DISPLAY_PLANE_ENABLE (1 << 31)
> -#define DISPLAY_PLANE_DISABLE 0
> -#define DISPPLANE_GAMMA_ENABLE (1 << 30)
> -#define DISPPLANE_GAMMA_DISABLE 0
> -#define DISPPLANE_PIXFORMAT_MASK (0xf << 26)
> -#define DISPPLANE_YUV422 (0x0 << 26)
> -#define DISPPLANE_8BPP (0x2 << 26)
> -#define DISPPLANE_BGRA555 (0x3 << 26)
> -#define DISPPLANE_BGRX555 (0x4 << 26)
> -#define DISPPLANE_BGRX565 (0x5 << 26)
> -#define DISPPLANE_BGRX888 (0x6 << 26)
> -#define DISPPLANE_BGRA888 (0x7 << 26)
> -#define DISPPLANE_RGBX101010 (0x8 << 26)
> -#define DISPPLANE_RGBA101010 (0x9 << 26)
> -#define DISPPLANE_BGRX101010 (0xa << 26)
> -#define DISPPLANE_BGRA101010 (0xb << 26)
> -#define DISPPLANE_RGBX161616 (0xc << 26)
> -#define DISPPLANE_RGBX888 (0xe << 26)
> -#define DISPPLANE_RGBA888 (0xf << 26)
> -#define DISPPLANE_STEREO_ENABLE (1 << 25)
> -#define DISPPLANE_STEREO_DISABLE 0
> -#define DISPPLANE_PIPE_CSC_ENABLE (1 << 24) /* ilk+ */
> -#define DISPPLANE_SEL_PIPE_SHIFT 24
> -#define DISPPLANE_SEL_PIPE_MASK (3 << DISPPLANE_SEL_PIPE_SHIFT)
> -#define DISPPLANE_SEL_PIPE(pipe) ((pipe) << DISPPLANE_SEL_PIPE_SHIFT)
> -#define DISPPLANE_SRC_KEY_ENABLE (1 << 22)
> -#define DISPPLANE_SRC_KEY_DISABLE 0
> -#define DISPPLANE_LINE_DOUBLE (1 << 20)
> -#define DISPPLANE_NO_LINE_DOUBLE 0
> -#define DISPPLANE_STEREO_POLARITY_FIRST 0
> -#define DISPPLANE_STEREO_POLARITY_SECOND (1 << 18)
> -#define DISPPLANE_ALPHA_PREMULTIPLY (1 << 16) /* CHV pipe B */
> -#define DISPPLANE_ROTATE_180 (1 << 15)
> -#define DISPPLANE_TRICKLE_FEED_DISABLE (1 << 14) /* Ironlake */
> -#define DISPPLANE_TILED (1 << 10)
> -#define DISPPLANE_ASYNC_FLIP (1 << 9) /* g4x+ */
> -#define DISPPLANE_MIRROR (1 << 8) /* CHV pipe B */
> +#define DISP_ENABLE REG_BIT(31)
> +#define DISP_PIPE_GAMMA_ENABLE REG_BIT(30)
> +#define DISP_FORMAT_MASK REG_GENMASK(29, 26)
> +#define DISP_FORMAT_8BPP REG_FIELD_PREP(DISP_FORMAT_MASK, 2)
> +#define DISP_FORMAT_BGRA555 REG_FIELD_PREP(DISP_FORMAT_MASK, 3)
> +#define DISP_FORMAT_BGRX555 REG_FIELD_PREP(DISP_FORMAT_MASK, 4)
> +#define DISP_FORMAT_BGRX565 REG_FIELD_PREP(DISP_FORMAT_MASK, 5)
> +#define DISP_FORMAT_BGRX888 REG_FIELD_PREP(DISP_FORMAT_MASK, 6)
> +#define DISP_FORMAT_BGRA888 REG_FIELD_PREP(DISP_FORMAT_MASK, 7)
> +#define DISP_FORMAT_RGBX101010 REG_FIELD_PREP(DISP_FORMAT_MASK, 8)
> +#define DISP_FORMAT_RGBA101010 REG_FIELD_PREP(DISP_FORMAT_MASK, 9)
> +#define DISP_FORMAT_BGRX101010 REG_FIELD_PREP(DISP_FORMAT_MASK, 10)
> +#define DISP_FORMAT_BGRA101010 REG_FIELD_PREP(DISP_FORMAT_MASK, 11)
> +#define DISP_FORMAT_RGBX161616 REG_FIELD_PREP(DISP_FORMAT_MASK, 12)
> +#define DISP_FORMAT_RGBX888 REG_FIELD_PREP(DISP_FORMAT_MASK, 14)
> +#define DISP_FORMAT_RGBA888 REG_FIELD_PREP(DISP_FORMAT_MASK, 15)
> +#define DISP_STEREO_ENABLE REG_BIT(25)
> +#define DISP_PIPE_CSC_ENABLE REG_BIT(24) /* ilk+ */
> +#define DISP_PIPE_SEL_MASK REG_GENMASK(25, 24)
> +#define DISP_PIPE_SEL(pipe) REG_FIELD_PREP(DISP_PIPE_SEL_MASK, (pipe))
> +#define DISP_SRC_KEY_ENABLE REG_BIT(22)
> +#define DISP_LINE_DOUBLE REG_BIT(20)
> +#define DISP_STEREO_POLARITY_SECOND REG_BIT(18)
> +#define DISP_ALPHA_PREMULTIPLY REG_BIT(16) /* CHV pipe B */
> +#define DISP_ROTATE_180 REG_BIT(15)
> +#define DISP_TRICKLE_FEED_DISABLE REG_BIT(14) /* g4x+ */
> +#define DISP_TILED REG_BIT(10)
> +#define DISP_ASYNC_FLIP REG_BIT(9) /* g4x+ */
> +#define DISP_MIRROR REG_BIT(8) /* CHV pipe B */
> #define _DSPAADDR 0x70184
> #define _DSPASTRIDE 0x70188
> #define _DSPAPOS 0x7018C /* reserved */
> +#define DISP_POS_Y_MASK REG_GENMASK(31, 0)
> +#define DISP_POS_Y(y) REG_FIELD_PREP(DISP_POS_Y_MASK, (y))
> +#define DISP_POS_X_MASK REG_GENMASK(15, 0)
> +#define DISP_POS_X(x) REG_FIELD_PREP(DISP_POS_X_MASK, (x))
> #define _DSPASIZE 0x70190
> +#define DISP_HEIGHT_MASK REG_GENMASK(31, 0)
> +#define DISP_HEIGHT(h) REG_FIELD_PREP(DISP_HEIGHT_MASK, (h))
> +#define DISP_WIDTH_MASK REG_GENMASK(15, 0)
> +#define DISP_WIDTH(w) REG_FIELD_PREP(DISP_WIDTH_MASK, (w))
> #define _DSPASURF 0x7019C /* 965+ only */
> +#define DISP_ADDR_MASK REG_GENMASK(31, 12)
> #define _DSPATILEOFF 0x701A4 /* 965+ only */
> +#define DISP_OFFSET_Y_MASK REG_GENMASK(31, 16)
> +#define DISP_OFFSET_Y(y) REG_FIELD_PREP(DISP_OFFSET_Y_MASK, (y))
> +#define DISP_OFFSET_X_MASK REG_GENMASK(15, 0)
> +#define DISP_OFFSET_X(x) REG_FIELD_PREP(DISP_OFFSET_X_MASK, (x))
> #define _DSPAOFFSET 0x701A4 /* HSW */
> #define _DSPASURFLIVE 0x701AC
> #define _DSPAGAMC 0x701E0
> @@ -5962,15 +5967,28 @@ enum {
>
> /* CHV pipe B blender and primary plane */
> #define _CHV_BLEND_A 0x60a00
> -#define CHV_BLEND_LEGACY (0 << 30)
> -#define CHV_BLEND_ANDROID (1 << 30)
> -#define CHV_BLEND_MPO (2 << 30)
> -#define CHV_BLEND_MASK (3 << 30)
> +#define CHV_BLEND_MASK REG_GENMASK(31, 30)
> +#define CHV_BLEND_LEGACY REG_FIELD_PREP(CHV_BLEND_MASK, 0)
> +#define CHV_BLEND_ANDROID REG_FIELD_PREP(CHV_BLEND_MASK, 1)
> +#define CHV_BLEND_MPO REG_FIELD_PREP(CHV_BLEND_MASK, 2)
> #define _CHV_CANVAS_A 0x60a04
> +#define CHV_CANVAS_RED_MASK REG_GENMASK(29, 20)
> +#define CHV_CANVAS_GREEN_MASK REG_GENMASK(19, 10)
> +#define CHV_CANVAS_BLUE_MASK REG_GENMASK(9, 0)
> #define _PRIMPOS_A 0x60a08
> +#define PRIM_POS_Y_MASK REG_GENMASK(31, 16)
> +#define PRIM_POS_Y(y) REG_FIELD_PREP(PRIM_POS_Y_MASK, (y))
> +#define PRIM_POS_X_MASK REG_GENMASK(15, 0)
> +#define PRIM_POS_X(x) REG_FIELD_PREP(PRIM_POS_X_MASK, (x))
> #define _PRIMSIZE_A 0x60a0c
> +#define PRIM_HEIGHT_MASK REG_GENMASK(31, 16)
> +#define PRIM_HEIGHT(h) REG_FIELD_PREP(PRIM_HEIGHT_MASK, (h))
> +#define PRIM_WIDTH_MASK REG_GENMASK(15, 0)
> +#define PRIM_WIDTH(w) REG_FIELD_PREP(PRIM_WIDTH_MASK, (w))
> #define _PRIMCNSTALPHA_A 0x60a10
> -#define PRIM_CONST_ALPHA_ENABLE (1 << 31)
> +#define PRIM_CONST_ALPHA_ENABLE REG_BIT(31)
> +#define PRIM_CONST_ALPHA_MASK REG_GENMASK(7, 0)
> +#define PRIM_CONST_ALPHA(alpha) REG_FIELD_PREP(PRIM_CONST_ALPHA_MASK, (alpha))
>
> #define CHV_BLEND(pipe) _MMIO_TRANS2(pipe, _CHV_BLEND_A)
> #define CHV_CANVAS(pipe) _MMIO_TRANS2(pipe, _CHV_CANVAS_A)
> @@ -6011,10 +6029,8 @@ enum {
>
> /* Display B control */
> #define _DSPBCNTR (DISPLAY_MMIO_BASE(dev_priv) + 0x71180)
> -#define DISPPLANE_ALPHA_TRANS_ENABLE (1 << 15)
> -#define DISPPLANE_ALPHA_TRANS_DISABLE 0
> -#define DISPPLANE_SPRITE_ABOVE_DISPLAY 0
> -#define DISPPLANE_SPRITE_ABOVE_OVERLAY (1)
> +#define DISP_ALPHA_TRANS_ENABLE REG_BIT(15)
> +#define DISP_SPRITE_ABOVE_OVERLAY REG_BIT(0)
> #define _DSPBADDR (DISPLAY_MMIO_BASE(dev_priv) + 0x71184)
> #define _DSPBSTRIDE (DISPLAY_MMIO_BASE(dev_priv) + 0x71188)
> #define _DSPBPOS (DISPLAY_MMIO_BASE(dev_priv) + 0x7118C)
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 2ec8e48806b6..c2bb9945f7be 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -7208,7 +7208,7 @@ static void g4x_disable_trickle_feed(struct drm_i915_private *dev_priv)
> for_each_pipe(dev_priv, pipe) {
> intel_uncore_write(&dev_priv->uncore, DSPCNTR(pipe),
> intel_uncore_read(&dev_priv->uncore, DSPCNTR(pipe)) |
> - DISPPLANE_TRICKLE_FEED_DISABLE);
> + DISP_TRICKLE_FEED_DISABLE);
>
> intel_uncore_write(&dev_priv->uncore, DSPSURF(pipe), intel_uncore_read(&dev_priv->uncore, DSPSURF(pipe)));
> intel_uncore_posting_read(&dev_priv->uncore, DSPSURF(pipe));
^ permalink raw reply [flat|nested] 12+ messages in thread
* [Intel-gfx] ✗ Fi.CI.BUILD: failure for drm/i915: Futher optimize plane updates (rev2)
2022-01-21 11:30 [Intel-gfx] [PATCH 0/6] drm/i915: Futher optimize plane updates Ville Syrjala
` (8 preceding siblings ...)
2022-01-21 16:00 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
@ 2022-02-09 16:14 ` Patchwork
9 siblings, 0 replies; 12+ messages in thread
From: Patchwork @ 2022-02-09 16:14 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Futher optimize plane updates (rev2)
URL : https://patchwork.freedesktop.org/series/99149/
State : failure
== Summary ==
Applying: drm/i915: Clean up pre-skl primary plane registers
Using index info to reconstruct a base tree...
M drivers/gpu/drm/i915/display/i9xx_plane.c
M drivers/gpu/drm/i915/display/intel_display.c
M drivers/gpu/drm/i915/gvt/display.c
M drivers/gpu/drm/i915/gvt/fb_decoder.c
M drivers/gpu/drm/i915/i915_reg.h
M drivers/gpu/drm/i915/intel_pm.c
Falling back to patching base and 3-way merge...
Auto-merging drivers/gpu/drm/i915/intel_pm.c
Auto-merging drivers/gpu/drm/i915/i915_reg.h
Auto-merging drivers/gpu/drm/i915/gvt/fb_decoder.c
Auto-merging drivers/gpu/drm/i915/gvt/display.c
CONFLICT (content): Merge conflict in drivers/gpu/drm/i915/gvt/display.c
Auto-merging drivers/gpu/drm/i915/display/intel_display.c
Auto-merging drivers/gpu/drm/i915/display/i9xx_plane.c
error: Failed to merge in the changes.
hint: Use 'git am --show-current-patch=diff' to see the failed patch
Patch failed at 0001 drm/i915: Clean up pre-skl primary plane registers
When you have resolved this problem, run "git am --continue".
If you prefer to skip this patch, run "git am --skip" instead.
To restore the original branch and stop patching, run "git am --abort".
^ permalink raw reply [flat|nested] 12+ messages in thread
end of thread, other threads:[~2022-02-09 16:14 UTC | newest]
Thread overview: 12+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-01-21 11:30 [Intel-gfx] [PATCH 0/6] drm/i915: Futher optimize plane updates Ville Syrjala
2022-01-21 11:30 ` [Intel-gfx] [PATCH 1/6] drm/i915: Clean up pre-skl primary plane registers Ville Syrjala
2022-01-21 17:23 ` Souza, Jose
2022-01-21 11:30 ` [Intel-gfx] [PATCH 2/6] drm/i915: Optimize icl+ universal plane programming Ville Syrjala
2022-01-21 11:30 ` [Intel-gfx] [PATCH 3/6] drm/i915: Make skl+ universal plane registers unlocked Ville Syrjala
2022-01-21 11:30 ` [Intel-gfx] [PATCH 4/6] drm/i915: Make cursor " Ville Syrjala
2022-01-21 11:30 ` [Intel-gfx] [PATCH 5/6] drm/i915: Make most pre-skl primary " Ville Syrjala
2022-01-21 11:30 ` [Intel-gfx] [PATCH 6/6] drm/i915: Make pre-skl sprite " Ville Syrjala
2022-01-21 12:44 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: Futher optimize plane updates Patchwork
2022-01-21 13:22 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2022-01-21 16:00 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2022-02-09 16:14 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for drm/i915: Futher optimize plane updates (rev2) Patchwork
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