* [U-Boot] [PATCH 1/1] arm: socfpga: fix qspi flash compatible (add "spi-flash")
@ 2018-01-29 6:36 Simon Goldschmidt
2018-01-29 10:35 ` Marek Vasut
0 siblings, 1 reply; 5+ messages in thread
From: Simon Goldschmidt @ 2018-01-29 6:36 UTC (permalink / raw)
To: u-boot
This patch adds "spi-flash" to the compatible list of the qspi flash
chip for all socfpga boards. This is required to make qspi work on
these boards on top of the recent fixes. Without the "spi-flash"
compatible string for the flash chip, the speed cannot be read and a
speed of 0Hz is used (which results in a divide-by-zero on these
boards).
Signed-off-by: Simon Goldschmidt <sgoldschmidt@de.pepperl-fuchs.com>
---
arch/arm/dts/socfpga_arria5_socdk.dts | 2 +-
arch/arm/dts/socfpga_cyclone5_is1.dts | 2 +-
arch/arm/dts/socfpga_cyclone5_socdk.dts | 2 +-
arch/arm/dts/socfpga_cyclone5_socrates.dts | 2 +-
4 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/arm/dts/socfpga_arria5_socdk.dts b/arch/arm/dts/socfpga_arria5_socdk.dts
index 1e91a65af6..4e4b619f4f 100644
--- a/arch/arm/dts/socfpga_arria5_socdk.dts
+++ b/arch/arm/dts/socfpga_arria5_socdk.dts
@@ -88,7 +88,7 @@
u-boot,dm-pre-reloc;
#address-cells = <1>;
#size-cells = <1>;
- compatible = "n25q00";
+ compatible = "n25q00", "spi-flash";
reg = <0>; /* chip select */
spi-max-frequency = <50000000>;
m25p,fast-read;
diff --git a/arch/arm/dts/socfpga_cyclone5_is1.dts b/arch/arm/dts/socfpga_cyclone5_is1.dts
index 2e2b71fefb..ea323a16ca 100644
--- a/arch/arm/dts/socfpga_cyclone5_is1.dts
+++ b/arch/arm/dts/socfpga_cyclone5_is1.dts
@@ -87,7 +87,7 @@
u-boot,dm-pre-reloc;
#address-cells = <1>;
#size-cells = <1>;
- compatible = "n25q00";
+ compatible = "n25q00", "spi-flash";
reg = <0>; /* chip select */
spi-max-frequency = <100000000>;
m25p,fast-read;
diff --git a/arch/arm/dts/socfpga_cyclone5_socdk.dts b/arch/arm/dts/socfpga_cyclone5_socdk.dts
index 95a8e653d7..3af51134bb 100644
--- a/arch/arm/dts/socfpga_cyclone5_socdk.dts
+++ b/arch/arm/dts/socfpga_cyclone5_socdk.dts
@@ -98,7 +98,7 @@
u-boot,dm-pre-reloc;
#address-cells = <1>;
#size-cells = <1>;
- compatible = "n25q00";
+ compatible = "n25q00", "spi-flash";
reg = <0>; /* chip select */
spi-max-frequency = <100000000>;
m25p,fast-read;
diff --git a/arch/arm/dts/socfpga_cyclone5_socrates.dts b/arch/arm/dts/socfpga_cyclone5_socrates.dts
index e3ae8a8207..e612eeed4f 100644
--- a/arch/arm/dts/socfpga_cyclone5_socrates.dts
+++ b/arch/arm/dts/socfpga_cyclone5_socrates.dts
@@ -68,7 +68,7 @@
flash0: n25q00 at 0 {
#address-cells = <1>;
#size-cells = <1>;
- compatible = "n25q00";
+ compatible = "n25q00", "spi-flash";
reg = <0>; /* chip select */
spi-max-frequency = <50000000>;
m25p,fast-read;
--
2.11.0
^ permalink raw reply related [flat|nested] 5+ messages in thread
* [U-Boot] [PATCH 1/1] arm: socfpga: fix qspi flash compatible (add "spi-flash")
2018-01-29 6:36 [U-Boot] [PATCH 1/1] arm: socfpga: fix qspi flash compatible (add "spi-flash") Simon Goldschmidt
@ 2018-01-29 10:35 ` Marek Vasut
2018-01-29 11:56 ` Simon Goldschmidt
0 siblings, 1 reply; 5+ messages in thread
From: Marek Vasut @ 2018-01-29 10:35 UTC (permalink / raw)
To: u-boot
On 01/29/2018 07:36 AM, Simon Goldschmidt wrote:
> This patch adds "spi-flash" to the compatible list of the qspi flash
> chip for all socfpga boards. This is required to make qspi work on
> these boards on top of the recent fixes. Without the "spi-flash"
> compatible string for the flash chip, the speed cannot be read and a
> speed of 0Hz is used (which results in a divide-by-zero on these
> boards).
>
> Signed-off-by: Simon Goldschmidt <sgoldschmidt@de.pepperl-fuchs.com>
What's the status of the recent fixes ? Are they in already ?
Applied anyway, thanks.
> ---
> arch/arm/dts/socfpga_arria5_socdk.dts | 2 +-
> arch/arm/dts/socfpga_cyclone5_is1.dts | 2 +-
> arch/arm/dts/socfpga_cyclone5_socdk.dts | 2 +-
> arch/arm/dts/socfpga_cyclone5_socrates.dts | 2 +-
> 4 files changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/arch/arm/dts/socfpga_arria5_socdk.dts b/arch/arm/dts/socfpga_arria5_socdk.dts
> index 1e91a65af6..4e4b619f4f 100644
> --- a/arch/arm/dts/socfpga_arria5_socdk.dts
> +++ b/arch/arm/dts/socfpga_arria5_socdk.dts
> @@ -88,7 +88,7 @@
> u-boot,dm-pre-reloc;
> #address-cells = <1>;
> #size-cells = <1>;
> - compatible = "n25q00";
> + compatible = "n25q00", "spi-flash";
> reg = <0>; /* chip select */
> spi-max-frequency = <50000000>;
> m25p,fast-read;
> diff --git a/arch/arm/dts/socfpga_cyclone5_is1.dts b/arch/arm/dts/socfpga_cyclone5_is1.dts
> index 2e2b71fefb..ea323a16ca 100644
> --- a/arch/arm/dts/socfpga_cyclone5_is1.dts
> +++ b/arch/arm/dts/socfpga_cyclone5_is1.dts
> @@ -87,7 +87,7 @@
> u-boot,dm-pre-reloc;
> #address-cells = <1>;
> #size-cells = <1>;
> - compatible = "n25q00";
> + compatible = "n25q00", "spi-flash";
> reg = <0>; /* chip select */
> spi-max-frequency = <100000000>;
> m25p,fast-read;
> diff --git a/arch/arm/dts/socfpga_cyclone5_socdk.dts b/arch/arm/dts/socfpga_cyclone5_socdk.dts
> index 95a8e653d7..3af51134bb 100644
> --- a/arch/arm/dts/socfpga_cyclone5_socdk.dts
> +++ b/arch/arm/dts/socfpga_cyclone5_socdk.dts
> @@ -98,7 +98,7 @@
> u-boot,dm-pre-reloc;
> #address-cells = <1>;
> #size-cells = <1>;
> - compatible = "n25q00";
> + compatible = "n25q00", "spi-flash";
> reg = <0>; /* chip select */
> spi-max-frequency = <100000000>;
> m25p,fast-read;
> diff --git a/arch/arm/dts/socfpga_cyclone5_socrates.dts b/arch/arm/dts/socfpga_cyclone5_socrates.dts
> index e3ae8a8207..e612eeed4f 100644
> --- a/arch/arm/dts/socfpga_cyclone5_socrates.dts
> +++ b/arch/arm/dts/socfpga_cyclone5_socrates.dts
> @@ -68,7 +68,7 @@
> flash0: n25q00 at 0 {
> #address-cells = <1>;
> #size-cells = <1>;
> - compatible = "n25q00";
> + compatible = "n25q00", "spi-flash";
> reg = <0>; /* chip select */
> spi-max-frequency = <50000000>;
> m25p,fast-read;
>
--
Best regards,
Marek Vasut
^ permalink raw reply [flat|nested] 5+ messages in thread
* [U-Boot] [PATCH 1/1] arm: socfpga: fix qspi flash compatible (add "spi-flash")
2018-01-29 10:35 ` Marek Vasut
@ 2018-01-29 11:56 ` Simon Goldschmidt
2018-01-29 12:01 ` Marek Vasut
0 siblings, 1 reply; 5+ messages in thread
From: Simon Goldschmidt @ 2018-01-29 11:56 UTC (permalink / raw)
To: u-boot
On 29.01.2018 11:35, Marek Vasut wrote:
> On 01/29/2018 07:36 AM, Simon Goldschmidt wrote:
>> This patch adds "spi-flash" to the compatible list of the qspi flash
>> chip for all socfpga boards. This is required to make qspi work on
>> these boards on top of the recent fixes. Without the "spi-flash"
>> compatible string for the flash chip, the speed cannot be read and a
>> speed of 0Hz is used (which results in a divide-by-zero on these
>> boards).
>>
>> Signed-off-by: Simon Goldschmidt <sgoldschmidt@de.pepperl-fuchs.com>
> What's the status of the recent fixes ? Are they in already ?
Yes, they were applied via u-boot-spi. Everything should work now.
>
> Applied anyway, thanks.
>
>> ---
>> arch/arm/dts/socfpga_arria5_socdk.dts | 2 +-
>> arch/arm/dts/socfpga_cyclone5_is1.dts | 2 +-
>> arch/arm/dts/socfpga_cyclone5_socdk.dts | 2 +-
>> arch/arm/dts/socfpga_cyclone5_socrates.dts | 2 +-
>> 4 files changed, 4 insertions(+), 4 deletions(-)
>>
>> diff --git a/arch/arm/dts/socfpga_arria5_socdk.dts b/arch/arm/dts/socfpga_arria5_socdk.dts
>> index 1e91a65af6..4e4b619f4f 100644
>> --- a/arch/arm/dts/socfpga_arria5_socdk.dts
>> +++ b/arch/arm/dts/socfpga_arria5_socdk.dts
>> @@ -88,7 +88,7 @@
>> u-boot,dm-pre-reloc;
>> #address-cells = <1>;
>> #size-cells = <1>;
>> - compatible = "n25q00";
>> + compatible = "n25q00", "spi-flash";
>> reg = <0>; /* chip select */
>> spi-max-frequency = <50000000>;
>> m25p,fast-read;
>> diff --git a/arch/arm/dts/socfpga_cyclone5_is1.dts b/arch/arm/dts/socfpga_cyclone5_is1.dts
>> index 2e2b71fefb..ea323a16ca 100644
>> --- a/arch/arm/dts/socfpga_cyclone5_is1.dts
>> +++ b/arch/arm/dts/socfpga_cyclone5_is1.dts
>> @@ -87,7 +87,7 @@
>> u-boot,dm-pre-reloc;
>> #address-cells = <1>;
>> #size-cells = <1>;
>> - compatible = "n25q00";
>> + compatible = "n25q00", "spi-flash";
>> reg = <0>; /* chip select */
>> spi-max-frequency = <100000000>;
>> m25p,fast-read;
>> diff --git a/arch/arm/dts/socfpga_cyclone5_socdk.dts b/arch/arm/dts/socfpga_cyclone5_socdk.dts
>> index 95a8e653d7..3af51134bb 100644
>> --- a/arch/arm/dts/socfpga_cyclone5_socdk.dts
>> +++ b/arch/arm/dts/socfpga_cyclone5_socdk.dts
>> @@ -98,7 +98,7 @@
>> u-boot,dm-pre-reloc;
>> #address-cells = <1>;
>> #size-cells = <1>;
>> - compatible = "n25q00";
>> + compatible = "n25q00", "spi-flash";
>> reg = <0>; /* chip select */
>> spi-max-frequency = <100000000>;
>> m25p,fast-read;
>> diff --git a/arch/arm/dts/socfpga_cyclone5_socrates.dts b/arch/arm/dts/socfpga_cyclone5_socrates.dts
>> index e3ae8a8207..e612eeed4f 100644
>> --- a/arch/arm/dts/socfpga_cyclone5_socrates.dts
>> +++ b/arch/arm/dts/socfpga_cyclone5_socrates.dts
>> @@ -68,7 +68,7 @@
>> flash0: n25q00 at 0 {
>> #address-cells = <1>;
>> #size-cells = <1>;
>> - compatible = "n25q00";
>> + compatible = "n25q00", "spi-flash";
>> reg = <0>; /* chip select */
>> spi-max-frequency = <50000000>;
>> m25p,fast-read;
>>
>
^ permalink raw reply [flat|nested] 5+ messages in thread
* [U-Boot] [PATCH 1/1] arm: socfpga: fix qspi flash compatible (add "spi-flash")
2018-01-29 11:56 ` Simon Goldschmidt
@ 2018-01-29 12:01 ` Marek Vasut
2018-01-29 12:06 ` Simon Goldschmidt
0 siblings, 1 reply; 5+ messages in thread
From: Marek Vasut @ 2018-01-29 12:01 UTC (permalink / raw)
To: u-boot
On 01/29/2018 12:56 PM, Simon Goldschmidt wrote:
> On 29.01.2018 11:35, Marek Vasut wrote:
>> On 01/29/2018 07:36 AM, Simon Goldschmidt wrote:
>>> This patch adds "spi-flash" to the compatible list of the qspi flash
>>> chip for all socfpga boards. This is required to make qspi work on
>>> these boards on top of the recent fixes. Without the "spi-flash"
>>> compatible string for the flash chip, the speed cannot be read and a
>>> speed of 0Hz is used (which results in a divide-by-zero on these
>>> boards).
>>>
>>> Signed-off-by: Simon Goldschmidt <sgoldschmidt@de.pepperl-fuchs.com>
>> What's the status of the recent fixes ? Are they in already ?
>
> Yes, they were applied via u-boot-spi. Everything should work now.
Can you test u-boot/master once they land, so we're sure ? Thanks
--
Best regards,
Marek Vasut
^ permalink raw reply [flat|nested] 5+ messages in thread
* [U-Boot] [PATCH 1/1] arm: socfpga: fix qspi flash compatible (add "spi-flash")
2018-01-29 12:01 ` Marek Vasut
@ 2018-01-29 12:06 ` Simon Goldschmidt
0 siblings, 0 replies; 5+ messages in thread
From: Simon Goldschmidt @ 2018-01-29 12:06 UTC (permalink / raw)
To: u-boot
[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #1: Type: text/plain; charset="utf-8-sig", Size: 2173 bytes --]
Pepperl+Fuchs GmbH, Mannheim
Geschaeftsfuehrer/Managing Directors: Dr.-Ing. Gunther Kegel (Vors./CEO), Werner Guthier, Mehmet Hatiboglu
Vorsitzender des Aufsichtsrats/Chairman of the supervisory board: Claus Michael
Registergericht/Register Court: AG Mannheim HRB 4713
On 29.01.2018 13:01, Marek Vasut wrote:
> On 01/29/2018 12:56 PM, Simon Goldschmidt wrote:
>> On 29.01.2018 11:35, Marek Vasut wrote:
>>> On 01/29/2018 07:36 AM, Simon Goldschmidt wrote:
>>>> This patch adds "spi-flash" to the compatible list of the qspi flash
>>>> chip for all socfpga boards. This is required to make qspi work on
>>>> these boards on top of the recent fixes. Without the "spi-flash"
>>>> compatible string for the flash chip, the speed cannot be read and a
>>>> speed of 0Hz is used (which results in a divide-by-zero on these
>>>> boards).
>>>>
>>>> Signed-off-by: Simon Goldschmidt <sgoldschmidt@de.pepperl-fuchs.com>
>>> What's the status of the recent fixes ? Are they in already ?
>> Yes, they were applied via u-boot-spi. Everything should work now.
> Can you test u-boot/master once they land, so we're sure ? Thanks
Yes, I'll upgrade the version we use internally to v2018.03 RCs as soon
as they are tagged.
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^ permalink raw reply [flat|nested] 5+ messages in thread
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2018-01-29 6:36 [U-Boot] [PATCH 1/1] arm: socfpga: fix qspi flash compatible (add "spi-flash") Simon Goldschmidt
2018-01-29 10:35 ` Marek Vasut
2018-01-29 11:56 ` Simon Goldschmidt
2018-01-29 12:01 ` Marek Vasut
2018-01-29 12:06 ` Simon Goldschmidt
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