* [PATCH v5 0/3] ARM: dts: imx7: add NAND support @ 2017-06-06 6:30 ` Stefan Agner 0 siblings, 0 replies; 26+ messages in thread From: Stefan Agner @ 2017-06-06 6:30 UTC (permalink / raw) To: shawnguo, kernel, sboyd Cc: aisheng.dong, dwmw2, computersforpeace, boris.brezillon, marek.vasut, richard, robh+dt, mark.rutland, han.xu, fabio.estevam, LW, linux-mtd, devicetree, linux-arm-kernel, linux-clk, linux-kernel, Stefan Agner This revision alters the clock tree such that the clock required by the APBH DMA (NAND_USDHC_BUS_CLK_ROOT _after_ gate CCGR20) is available as an independent clock. So far the gate CCGR20 was used by the NAND_ROOT_CLK only. A previous patch added the NAND_ROOT_CLK which also lead to the effect that the clock gate CCGR20 gets enabled: https://patchwork.ozlabs.org/patch/551967/ The data sheet seems to indicate that the APBH DMA only uses hclk which is connected to NAND_USDHC_BUS_CLK_ROOT through gate CCGR20. Tests seem to confirm this wiring. By adding a new clock IMX7D_NAND_USDHC_BUS_RAWNAND_CLK we can assign a clock which also enables the shared CCGR20 gate without changing the DMA driver. This better reflects the true wiring and encapsulates the SoC specific clock wiring in the clock tree instead leaking it into the driver code. Versions 2 and earlier also included NAND driver changes, which are already merged. -- Stefan Changes since v4: - Introduce *_RAWNAND_CLK which represent clocks after CCGR20 - - Add assigned-clocks to set a reasonable parent for raw NAND Changes since v3: - Only specify IMX7D_NAND_USDHC_BUS_ROOT_CLK which seems to be sufficent Changes since v2: - Dropped driver changes, alreay merged Changes since v1: - Make clks_count const - Introduce IS_IMX7D for i.MX 7 SoC's and make it part of GPMI_IS_MX6 Stefan Agner (3): clk: imx7d: create clocks behind rawnand clock gate ARM: dts: imx7: add GPMI NAND and APBH DMA ARM: dts: imx7-colibri: add NAND support arch/arm/boot/dts/imx7-colibri.dtsi | 9 +++++++- arch/arm/boot/dts/imx7s.dtsi | 32 ++++++++++++++++++++++++++- drivers/clk/imx/clk-imx7d.c | 6 +++-- include/dt-bindings/clock/imx7d-clock.h | 4 ++- 4 files changed, 48 insertions(+), 3 deletions(-) base-commit: e2bb3be2c6c623ff0bad975dc9435531f450f0c5 -- git-series 0.9.1 ^ permalink raw reply [flat|nested] 26+ messages in thread
* [PATCH v5 0/3] ARM: dts: imx7: add NAND support @ 2017-06-06 6:30 ` Stefan Agner 0 siblings, 0 replies; 26+ messages in thread From: Stefan Agner @ 2017-06-06 6:30 UTC (permalink / raw) To: linux-arm-kernel This revision alters the clock tree such that the clock required by the APBH DMA (NAND_USDHC_BUS_CLK_ROOT _after_ gate CCGR20) is available as an independent clock. So far the gate CCGR20 was used by the NAND_ROOT_CLK only. A previous patch added the NAND_ROOT_CLK which also lead to the effect that the clock gate CCGR20 gets enabled: https://patchwork.ozlabs.org/patch/551967/ The data sheet seems to indicate that the APBH DMA only uses hclk which is connected to NAND_USDHC_BUS_CLK_ROOT through gate CCGR20. Tests seem to confirm this wiring. By adding a new clock IMX7D_NAND_USDHC_BUS_RAWNAND_CLK we can assign a clock which also enables the shared CCGR20 gate without changing the DMA driver. This better reflects the true wiring and encapsulates the SoC specific clock wiring in the clock tree instead leaking it into the driver code. Versions 2 and earlier also included NAND driver changes, which are already merged. -- Stefan Changes since v4: - Introduce *_RAWNAND_CLK which represent clocks after CCGR20 - - Add assigned-clocks to set a reasonable parent for raw NAND Changes since v3: - Only specify IMX7D_NAND_USDHC_BUS_ROOT_CLK which seems to be sufficent Changes since v2: - Dropped driver changes, alreay merged Changes since v1: - Make clks_count const - Introduce IS_IMX7D for i.MX 7 SoC's and make it part of GPMI_IS_MX6 Stefan Agner (3): clk: imx7d: create clocks behind rawnand clock gate ARM: dts: imx7: add GPMI NAND and APBH DMA ARM: dts: imx7-colibri: add NAND support arch/arm/boot/dts/imx7-colibri.dtsi | 9 +++++++- arch/arm/boot/dts/imx7s.dtsi | 32 ++++++++++++++++++++++++++- drivers/clk/imx/clk-imx7d.c | 6 +++-- include/dt-bindings/clock/imx7d-clock.h | 4 ++- 4 files changed, 48 insertions(+), 3 deletions(-) base-commit: e2bb3be2c6c623ff0bad975dc9435531f450f0c5 -- git-series 0.9.1 ^ permalink raw reply [flat|nested] 26+ messages in thread
* [PATCH v5 1/3] clk: imx7d: create clocks behind rawnand clock gate @ 2017-06-06 6:30 ` Stefan Agner 0 siblings, 0 replies; 26+ messages in thread From: Stefan Agner @ 2017-06-06 6:30 UTC (permalink / raw) To: shawnguo, kernel, sboyd Cc: aisheng.dong, dwmw2, computersforpeace, boris.brezillon, marek.vasut, richard, robh+dt, mark.rutland, han.xu, fabio.estevam, LW, linux-mtd, devicetree, linux-arm-kernel, linux-clk, linux-kernel, Stefan Agner The rawnand clock gate gates two clocks, NAND_USDHC_BUS_CLK_ROOT and NAND_CLK_ROOT. However, the gate has been in the chain of the latter only. This does not allow to use the NAND_USDHC_BUS_CLK_ROOT only, e.g. as required by APBH-Bridge-DMA. Add new clocks which represent the clock after the gate, and use a shared clock gate to correctly model the hardware. Signed-off-by: Stefan Agner <stefan@agner.ch> --- drivers/clk/imx/clk-imx7d.c | 6 ++++-- include/dt-bindings/clock/imx7d-clock.h | 4 +++- 2 files changed, 7 insertions(+), 3 deletions(-) diff --git a/drivers/clk/imx/clk-imx7d.c b/drivers/clk/imx/clk-imx7d.c index 93b0364..e364060 100644 --- a/drivers/clk/imx/clk-imx7d.c +++ b/drivers/clk/imx/clk-imx7d.c @@ -25,6 +25,7 @@ static u32 share_count_sai1; static u32 share_count_sai2; static u32 share_count_sai3; +static u32 share_count_nand; static struct clk_div_table test_div_table[] = { { .val = 3, .div = 1, }, @@ -748,7 +749,7 @@ static void __init imx7d_clocks_init(struct device_node *ccm_node) clks[IMX7D_ENET2_TIME_ROOT_DIV] = imx_clk_divider2("enet2_time_post_div", "enet2_time_pre_div", base + 0xa880, 0, 6); clks[IMX7D_ENET_PHY_REF_ROOT_DIV] = imx_clk_divider2("enet_phy_ref_post_div", "enet_phy_ref_pre_div", base + 0xa900, 0, 6); clks[IMX7D_EIM_ROOT_DIV] = imx_clk_divider2("eim_post_div", "eim_pre_div", base + 0xa980, 0, 6); - clks[IMX7D_NAND_ROOT_DIV] = imx_clk_divider2("nand_post_div", "nand_pre_div", base + 0xaa00, 0, 6); + clks[IMX7D_NAND_ROOT_CLK] = imx_clk_divider2("nand_root_clk", "nand_pre_div", base + 0xaa00, 0, 6); clks[IMX7D_QSPI_ROOT_DIV] = imx_clk_divider2("qspi_post_div", "qspi_pre_div", base + 0xaa80, 0, 6); clks[IMX7D_USDHC1_ROOT_DIV] = imx_clk_divider2("usdhc1_post_div", "usdhc1_pre_div", base + 0xab00, 0, 6); clks[IMX7D_USDHC2_ROOT_DIV] = imx_clk_divider2("usdhc2_post_div", "usdhc2_pre_div", base + 0xab80, 0, 6); @@ -825,7 +826,8 @@ static void __init imx7d_clocks_init(struct device_node *ccm_node) clks[IMX7D_ENET2_TIME_ROOT_CLK] = imx_clk_gate4("enet2_time_root_clk", "enet2_time_post_div", base + 0x4510, 0); clks[IMX7D_ENET_PHY_REF_ROOT_CLK] = imx_clk_gate4("enet_phy_ref_root_clk", "enet_phy_ref_post_div", base + 0x4520, 0); clks[IMX7D_EIM_ROOT_CLK] = imx_clk_gate4("eim_root_clk", "eim_post_div", base + 0x4160, 0); - clks[IMX7D_NAND_ROOT_CLK] = imx_clk_gate4("nand_root_clk", "nand_post_div", base + 0x4140, 0); + clks[IMX7D_NAND_RAWNAND_CLK] = imx_clk_gate2_shared2("nand_rawnand_clk", "nand_root_clk", base + 0x4140, 0, &share_count_nand); + clks[IMX7D_NAND_USDHC_BUS_RAWNAND_CLK] = imx_clk_gate2_shared2("nand_usdhc_rawnand_clk", "nand_usdhc_root_clk", base + 0x4140, 0, &share_count_nand); clks[IMX7D_QSPI_ROOT_CLK] = imx_clk_gate4("qspi_root_clk", "qspi_post_div", base + 0x4150, 0); clks[IMX7D_USDHC1_ROOT_CLK] = imx_clk_gate4("usdhc1_root_clk", "usdhc1_post_div", base + 0x46c0, 0); clks[IMX7D_USDHC2_ROOT_CLK] = imx_clk_gate4("usdhc2_root_clk", "usdhc2_post_div", base + 0x46d0, 0); diff --git a/include/dt-bindings/clock/imx7d-clock.h b/include/dt-bindings/clock/imx7d-clock.h index a7a1a50..de62a83 100644 --- a/include/dt-bindings/clock/imx7d-clock.h +++ b/include/dt-bindings/clock/imx7d-clock.h @@ -450,5 +450,7 @@ #define IMX7D_CLK_ARM 437 #define IMX7D_CKIL 438 #define IMX7D_OCOTP_CLK 439 -#define IMX7D_CLK_END 440 +#define IMX7D_NAND_RAWNAND_CLK 440 +#define IMX7D_NAND_USDHC_BUS_RAWNAND_CLK 441 +#define IMX7D_CLK_END 442 #endif /* __DT_BINDINGS_CLOCK_IMX7D_H */ -- git-series 0.9.1 ^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PATCH v5 1/3] clk: imx7d: create clocks behind rawnand clock gate @ 2017-06-06 6:30 ` Stefan Agner 0 siblings, 0 replies; 26+ messages in thread From: Stefan Agner @ 2017-06-06 6:30 UTC (permalink / raw) To: linux-arm-kernel The rawnand clock gate gates two clocks, NAND_USDHC_BUS_CLK_ROOT and NAND_CLK_ROOT. However, the gate has been in the chain of the latter only. This does not allow to use the NAND_USDHC_BUS_CLK_ROOT only, e.g. as required by APBH-Bridge-DMA. Add new clocks which represent the clock after the gate, and use a shared clock gate to correctly model the hardware. Signed-off-by: Stefan Agner <stefan@agner.ch> --- drivers/clk/imx/clk-imx7d.c | 6 ++++-- include/dt-bindings/clock/imx7d-clock.h | 4 +++- 2 files changed, 7 insertions(+), 3 deletions(-) diff --git a/drivers/clk/imx/clk-imx7d.c b/drivers/clk/imx/clk-imx7d.c index 93b0364..e364060 100644 --- a/drivers/clk/imx/clk-imx7d.c +++ b/drivers/clk/imx/clk-imx7d.c @@ -25,6 +25,7 @@ static u32 share_count_sai1; static u32 share_count_sai2; static u32 share_count_sai3; +static u32 share_count_nand; static struct clk_div_table test_div_table[] = { { .val = 3, .div = 1, }, @@ -748,7 +749,7 @@ static void __init imx7d_clocks_init(struct device_node *ccm_node) clks[IMX7D_ENET2_TIME_ROOT_DIV] = imx_clk_divider2("enet2_time_post_div", "enet2_time_pre_div", base + 0xa880, 0, 6); clks[IMX7D_ENET_PHY_REF_ROOT_DIV] = imx_clk_divider2("enet_phy_ref_post_div", "enet_phy_ref_pre_div", base + 0xa900, 0, 6); clks[IMX7D_EIM_ROOT_DIV] = imx_clk_divider2("eim_post_div", "eim_pre_div", base + 0xa980, 0, 6); - clks[IMX7D_NAND_ROOT_DIV] = imx_clk_divider2("nand_post_div", "nand_pre_div", base + 0xaa00, 0, 6); + clks[IMX7D_NAND_ROOT_CLK] = imx_clk_divider2("nand_root_clk", "nand_pre_div", base + 0xaa00, 0, 6); clks[IMX7D_QSPI_ROOT_DIV] = imx_clk_divider2("qspi_post_div", "qspi_pre_div", base + 0xaa80, 0, 6); clks[IMX7D_USDHC1_ROOT_DIV] = imx_clk_divider2("usdhc1_post_div", "usdhc1_pre_div", base + 0xab00, 0, 6); clks[IMX7D_USDHC2_ROOT_DIV] = imx_clk_divider2("usdhc2_post_div", "usdhc2_pre_div", base + 0xab80, 0, 6); @@ -825,7 +826,8 @@ static void __init imx7d_clocks_init(struct device_node *ccm_node) clks[IMX7D_ENET2_TIME_ROOT_CLK] = imx_clk_gate4("enet2_time_root_clk", "enet2_time_post_div", base + 0x4510, 0); clks[IMX7D_ENET_PHY_REF_ROOT_CLK] = imx_clk_gate4("enet_phy_ref_root_clk", "enet_phy_ref_post_div", base + 0x4520, 0); clks[IMX7D_EIM_ROOT_CLK] = imx_clk_gate4("eim_root_clk", "eim_post_div", base + 0x4160, 0); - clks[IMX7D_NAND_ROOT_CLK] = imx_clk_gate4("nand_root_clk", "nand_post_div", base + 0x4140, 0); + clks[IMX7D_NAND_RAWNAND_CLK] = imx_clk_gate2_shared2("nand_rawnand_clk", "nand_root_clk", base + 0x4140, 0, &share_count_nand); + clks[IMX7D_NAND_USDHC_BUS_RAWNAND_CLK] = imx_clk_gate2_shared2("nand_usdhc_rawnand_clk", "nand_usdhc_root_clk", base + 0x4140, 0, &share_count_nand); clks[IMX7D_QSPI_ROOT_CLK] = imx_clk_gate4("qspi_root_clk", "qspi_post_div", base + 0x4150, 0); clks[IMX7D_USDHC1_ROOT_CLK] = imx_clk_gate4("usdhc1_root_clk", "usdhc1_post_div", base + 0x46c0, 0); clks[IMX7D_USDHC2_ROOT_CLK] = imx_clk_gate4("usdhc2_root_clk", "usdhc2_post_div", base + 0x46d0, 0); diff --git a/include/dt-bindings/clock/imx7d-clock.h b/include/dt-bindings/clock/imx7d-clock.h index a7a1a50..de62a83 100644 --- a/include/dt-bindings/clock/imx7d-clock.h +++ b/include/dt-bindings/clock/imx7d-clock.h @@ -450,5 +450,7 @@ #define IMX7D_CLK_ARM 437 #define IMX7D_CKIL 438 #define IMX7D_OCOTP_CLK 439 -#define IMX7D_CLK_END 440 +#define IMX7D_NAND_RAWNAND_CLK 440 +#define IMX7D_NAND_USDHC_BUS_RAWNAND_CLK 441 +#define IMX7D_CLK_END 442 #endif /* __DT_BINDINGS_CLOCK_IMX7D_H */ -- git-series 0.9.1 ^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PATCH v5 1/3] clk: imx7d: create clocks behind rawnand clock gate @ 2017-06-06 6:30 ` Stefan Agner 0 siblings, 0 replies; 26+ messages in thread From: Stefan Agner @ 2017-06-06 6:30 UTC (permalink / raw) To: shawnguo-DgEjT+Ai2ygdnm+yROfE0A, kernel-bIcnvbaLZ9MEGnE8C9+IrQ, sboyd-sgV2jX0FEOL9JmXXK+q4OQ Cc: aisheng.dong-3arQi8VN3Tc, dwmw2-wEGCiKHe2LqWVfeAwA7xHQ, computersforpeace-Re5JQEeQqe8AvxtiuMwx3w, boris.brezillon-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8, marek.vasut-Re5JQEeQqe8AvxtiuMwx3w, richard-/L3Ra7n9ekc, robh+dt-DgEjT+Ai2ygdnm+yROfE0A, mark.rutland-5wv7dgnIgG8, han.xu-3arQi8VN3Tc, fabio.estevam-KZfg59tc24xl57MIdRCFDg, LW-bxm8fMRDkQLDiMYJYoSAnRvVK+yQ3ZXh, linux-mtd-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, devicetree-u79uwXL29TY76Z2rM5mHXA, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, linux-clk-u79uwXL29TY76Z2rM5mHXA, linux-kernel-u79uwXL29TY76Z2rM5mHXA, Stefan Agner The rawnand clock gate gates two clocks, NAND_USDHC_BUS_CLK_ROOT and NAND_CLK_ROOT. However, the gate has been in the chain of the latter only. This does not allow to use the NAND_USDHC_BUS_CLK_ROOT only, e.g. as required by APBH-Bridge-DMA. Add new clocks which represent the clock after the gate, and use a shared clock gate to correctly model the hardware. Signed-off-by: Stefan Agner <stefan-XLVq0VzYD2Y@public.gmane.org> --- drivers/clk/imx/clk-imx7d.c | 6 ++++-- include/dt-bindings/clock/imx7d-clock.h | 4 +++- 2 files changed, 7 insertions(+), 3 deletions(-) diff --git a/drivers/clk/imx/clk-imx7d.c b/drivers/clk/imx/clk-imx7d.c index 93b0364..e364060 100644 --- a/drivers/clk/imx/clk-imx7d.c +++ b/drivers/clk/imx/clk-imx7d.c @@ -25,6 +25,7 @@ static u32 share_count_sai1; static u32 share_count_sai2; static u32 share_count_sai3; +static u32 share_count_nand; static struct clk_div_table test_div_table[] = { { .val = 3, .div = 1, }, @@ -748,7 +749,7 @@ static void __init imx7d_clocks_init(struct device_node *ccm_node) clks[IMX7D_ENET2_TIME_ROOT_DIV] = imx_clk_divider2("enet2_time_post_div", "enet2_time_pre_div", base + 0xa880, 0, 6); clks[IMX7D_ENET_PHY_REF_ROOT_DIV] = imx_clk_divider2("enet_phy_ref_post_div", "enet_phy_ref_pre_div", base + 0xa900, 0, 6); clks[IMX7D_EIM_ROOT_DIV] = imx_clk_divider2("eim_post_div", "eim_pre_div", base + 0xa980, 0, 6); - clks[IMX7D_NAND_ROOT_DIV] = imx_clk_divider2("nand_post_div", "nand_pre_div", base + 0xaa00, 0, 6); + clks[IMX7D_NAND_ROOT_CLK] = imx_clk_divider2("nand_root_clk", "nand_pre_div", base + 0xaa00, 0, 6); clks[IMX7D_QSPI_ROOT_DIV] = imx_clk_divider2("qspi_post_div", "qspi_pre_div", base + 0xaa80, 0, 6); clks[IMX7D_USDHC1_ROOT_DIV] = imx_clk_divider2("usdhc1_post_div", "usdhc1_pre_div", base + 0xab00, 0, 6); clks[IMX7D_USDHC2_ROOT_DIV] = imx_clk_divider2("usdhc2_post_div", "usdhc2_pre_div", base + 0xab80, 0, 6); @@ -825,7 +826,8 @@ static void __init imx7d_clocks_init(struct device_node *ccm_node) clks[IMX7D_ENET2_TIME_ROOT_CLK] = imx_clk_gate4("enet2_time_root_clk", "enet2_time_post_div", base + 0x4510, 0); clks[IMX7D_ENET_PHY_REF_ROOT_CLK] = imx_clk_gate4("enet_phy_ref_root_clk", "enet_phy_ref_post_div", base + 0x4520, 0); clks[IMX7D_EIM_ROOT_CLK] = imx_clk_gate4("eim_root_clk", "eim_post_div", base + 0x4160, 0); - clks[IMX7D_NAND_ROOT_CLK] = imx_clk_gate4("nand_root_clk", "nand_post_div", base + 0x4140, 0); + clks[IMX7D_NAND_RAWNAND_CLK] = imx_clk_gate2_shared2("nand_rawnand_clk", "nand_root_clk", base + 0x4140, 0, &share_count_nand); + clks[IMX7D_NAND_USDHC_BUS_RAWNAND_CLK] = imx_clk_gate2_shared2("nand_usdhc_rawnand_clk", "nand_usdhc_root_clk", base + 0x4140, 0, &share_count_nand); clks[IMX7D_QSPI_ROOT_CLK] = imx_clk_gate4("qspi_root_clk", "qspi_post_div", base + 0x4150, 0); clks[IMX7D_USDHC1_ROOT_CLK] = imx_clk_gate4("usdhc1_root_clk", "usdhc1_post_div", base + 0x46c0, 0); clks[IMX7D_USDHC2_ROOT_CLK] = imx_clk_gate4("usdhc2_root_clk", "usdhc2_post_div", base + 0x46d0, 0); diff --git a/include/dt-bindings/clock/imx7d-clock.h b/include/dt-bindings/clock/imx7d-clock.h index a7a1a50..de62a83 100644 --- a/include/dt-bindings/clock/imx7d-clock.h +++ b/include/dt-bindings/clock/imx7d-clock.h @@ -450,5 +450,7 @@ #define IMX7D_CLK_ARM 437 #define IMX7D_CKIL 438 #define IMX7D_OCOTP_CLK 439 -#define IMX7D_CLK_END 440 +#define IMX7D_NAND_RAWNAND_CLK 440 +#define IMX7D_NAND_USDHC_BUS_RAWNAND_CLK 441 +#define IMX7D_CLK_END 442 #endif /* __DT_BINDINGS_CLOCK_IMX7D_H */ -- git-series 0.9.1 -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply related [flat|nested] 26+ messages in thread
* Re: [PATCH v5 1/3] clk: imx7d: create clocks behind rawnand clock gate 2017-06-06 6:30 ` Stefan Agner (?) @ 2017-06-06 16:33 ` Fabio Estevam -1 siblings, 0 replies; 26+ messages in thread From: Fabio Estevam @ 2017-06-06 16:33 UTC (permalink / raw) To: Stefan Agner Cc: Shawn Guo, Sascha Hauer, Stephen Boyd, Dong Aisheng, David Woodhouse, Brian Norris, Boris Brezillon, Marek Vasut, Richard Weinberger, robh+dt, Mark Rutland, han.xu, Fabio Estevam, Lothar Waßmann, linux-mtd, devicetree, linux-arm-kernel, linux-clk, linux-kernel On Tue, Jun 6, 2017 at 3:30 AM, Stefan Agner <stefan@agner.ch> wrote: > The rawnand clock gate gates two clocks, NAND_USDHC_BUS_CLK_ROOT > and NAND_CLK_ROOT. However, the gate has been in the chain of the > latter only. This does not allow to use the NAND_USDHC_BUS_CLK_ROOT > only, e.g. as required by APBH-Bridge-DMA. > > Add new clocks which represent the clock after the gate, and use a > shared clock gate to correctly model the hardware. > > Signed-off-by: Stefan Agner <stefan@agner.ch> Tested-by: Fabio Estevam <fabio.estevam@nxp.com> ^ permalink raw reply [flat|nested] 26+ messages in thread
* [PATCH v5 1/3] clk: imx7d: create clocks behind rawnand clock gate @ 2017-06-06 16:33 ` Fabio Estevam 0 siblings, 0 replies; 26+ messages in thread From: Fabio Estevam @ 2017-06-06 16:33 UTC (permalink / raw) To: linux-arm-kernel On Tue, Jun 6, 2017 at 3:30 AM, Stefan Agner <stefan@agner.ch> wrote: > The rawnand clock gate gates two clocks, NAND_USDHC_BUS_CLK_ROOT > and NAND_CLK_ROOT. However, the gate has been in the chain of the > latter only. This does not allow to use the NAND_USDHC_BUS_CLK_ROOT > only, e.g. as required by APBH-Bridge-DMA. > > Add new clocks which represent the clock after the gate, and use a > shared clock gate to correctly model the hardware. > > Signed-off-by: Stefan Agner <stefan@agner.ch> Tested-by: Fabio Estevam <fabio.estevam@nxp.com> ^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH v5 1/3] clk: imx7d: create clocks behind rawnand clock gate @ 2017-06-06 16:33 ` Fabio Estevam 0 siblings, 0 replies; 26+ messages in thread From: Fabio Estevam @ 2017-06-06 16:33 UTC (permalink / raw) To: Stefan Agner Cc: Shawn Guo, Sascha Hauer, Stephen Boyd, Dong Aisheng, David Woodhouse, Brian Norris, Boris Brezillon, Marek Vasut, Richard Weinberger, robh+dt, Mark Rutland, han.xu, Fabio Estevam, Lothar Waßmann, linux-mtd, devicetree, linux-arm-kernel On Tue, Jun 6, 2017 at 3:30 AM, Stefan Agner <stefan@agner.ch> wrote: > The rawnand clock gate gates two clocks, NAND_USDHC_BUS_CLK_ROOT > and NAND_CLK_ROOT. However, the gate has been in the chain of the > latter only. This does not allow to use the NAND_USDHC_BUS_CLK_ROOT > only, e.g. as required by APBH-Bridge-DMA. > > Add new clocks which represent the clock after the gate, and use a > shared clock gate to correctly model the hardware. > > Signed-off-by: Stefan Agner <stefan@agner.ch> Tested-by: Fabio Estevam <fabio.estevam@nxp.com> ^ permalink raw reply [flat|nested] 26+ messages in thread
* [PATCH v5 2/3] ARM: dts: imx7: add GPMI NAND and APBH DMA 2017-06-06 6:30 ` Stefan Agner @ 2017-06-06 6:30 ` Stefan Agner -1 siblings, 0 replies; 26+ messages in thread From: Stefan Agner @ 2017-06-06 6:30 UTC (permalink / raw) To: shawnguo, kernel, sboyd Cc: aisheng.dong, dwmw2, computersforpeace, boris.brezillon, marek.vasut, richard, robh+dt, mark.rutland, han.xu, fabio.estevam, LW, linux-mtd, devicetree, linux-arm-kernel, linux-clk, linux-kernel, Stefan Agner Add i.MX 7 APBH DMA and GPMI NAND modules. Signed-off-by: Stefan Agner <stefan@agner.ch> --- arch/arm/boot/dts/imx7s.dtsi | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/arch/arm/boot/dts/imx7s.dtsi b/arch/arm/boot/dts/imx7s.dtsi index c4f12fd..d71acd8 100644 --- a/arch/arm/boot/dts/imx7s.dtsi +++ b/arch/arm/boot/dts/imx7s.dtsi @@ -995,5 +995,37 @@ status = "disabled"; }; }; + + dma_apbh: dma-apbh@33000000 { + compatible = "fsl,imx7d-dma-apbh", "fsl,imx28-dma-apbh"; + reg = <0x33000000 0x2000>; + interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3"; + #dma-cells = <1>; + dma-channels = <4>; + clocks = <&clks IMX7D_NAND_USDHC_BUS_RAWNAND_CLK>; + clock-names = "dma_apbh_bch", "dma_apbh_io"; + }; + + gpmi: gpmi-nand@33002000{ + compatible = "fsl,imx7d-gpmi-nand"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x33002000 0x2000>, <0x33004000 0x4000>; + reg-names = "gpmi-nand", "bch"; + interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "bch"; + clocks = <&clks IMX7D_NAND_RAWNAND_CLK>, + <&clks IMX7D_NAND_USDHC_BUS_RAWNAND_CLK>; + clock-names = "gpmi_io", "gpmi_bch_apb"; + dmas = <&dma_apbh 0>; + dma-names = "rx-tx"; + status = "disabled"; + assigned-clocks = <&clks IMX7D_NAND_ROOT_SRC>; + assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_500M_CLK>; + }; }; }; -- git-series 0.9.1 ^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PATCH v5 2/3] ARM: dts: imx7: add GPMI NAND and APBH DMA @ 2017-06-06 6:30 ` Stefan Agner 0 siblings, 0 replies; 26+ messages in thread From: Stefan Agner @ 2017-06-06 6:30 UTC (permalink / raw) To: linux-arm-kernel Add i.MX 7 APBH DMA and GPMI NAND modules. Signed-off-by: Stefan Agner <stefan@agner.ch> --- arch/arm/boot/dts/imx7s.dtsi | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/arch/arm/boot/dts/imx7s.dtsi b/arch/arm/boot/dts/imx7s.dtsi index c4f12fd..d71acd8 100644 --- a/arch/arm/boot/dts/imx7s.dtsi +++ b/arch/arm/boot/dts/imx7s.dtsi @@ -995,5 +995,37 @@ status = "disabled"; }; }; + + dma_apbh: dma-apbh at 33000000 { + compatible = "fsl,imx7d-dma-apbh", "fsl,imx28-dma-apbh"; + reg = <0x33000000 0x2000>; + interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3"; + #dma-cells = <1>; + dma-channels = <4>; + clocks = <&clks IMX7D_NAND_USDHC_BUS_RAWNAND_CLK>; + clock-names = "dma_apbh_bch", "dma_apbh_io"; + }; + + gpmi: gpmi-nand at 33002000{ + compatible = "fsl,imx7d-gpmi-nand"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x33002000 0x2000>, <0x33004000 0x4000>; + reg-names = "gpmi-nand", "bch"; + interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "bch"; + clocks = <&clks IMX7D_NAND_RAWNAND_CLK>, + <&clks IMX7D_NAND_USDHC_BUS_RAWNAND_CLK>; + clock-names = "gpmi_io", "gpmi_bch_apb"; + dmas = <&dma_apbh 0>; + dma-names = "rx-tx"; + status = "disabled"; + assigned-clocks = <&clks IMX7D_NAND_ROOT_SRC>; + assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_500M_CLK>; + }; }; }; -- git-series 0.9.1 ^ permalink raw reply related [flat|nested] 26+ messages in thread
* Re: [PATCH v5 2/3] ARM: dts: imx7: add GPMI NAND and APBH DMA @ 2017-06-06 16:34 ` Fabio Estevam 0 siblings, 0 replies; 26+ messages in thread From: Fabio Estevam @ 2017-06-06 16:34 UTC (permalink / raw) To: Stefan Agner Cc: Shawn Guo, Sascha Hauer, Stephen Boyd, Dong Aisheng, David Woodhouse, Brian Norris, Boris Brezillon, Marek Vasut, Richard Weinberger, robh+dt, Mark Rutland, han.xu, Fabio Estevam, Lothar Waßmann, linux-mtd, devicetree, linux-arm-kernel, linux-clk, linux-kernel On Tue, Jun 6, 2017 at 3:30 AM, Stefan Agner <stefan@agner.ch> wrote: > Add i.MX 7 APBH DMA and GPMI NAND modules. > > Signed-off-by: Stefan Agner <stefan@agner.ch> Tested on a imx7d-sdb: [ 1.303543] nand: device found, Manufacturer ID: 0xec, Chip ID: 0xd5 [ 1.309999] nand: Samsung NAND 2GiB 3,3V 8-bit [ 1.314467] nand: 2048 MiB, MLC, erase size: 256 KiB, page size: 2048, OOB size: 64 [ 1.346007] gpmi-nand 33002000.gpmi-nand: driver registered. Tested-by: Fabio Estevam <fabio.estevam@nxp.com> ^ permalink raw reply [flat|nested] 26+ messages in thread
* [PATCH v5 2/3] ARM: dts: imx7: add GPMI NAND and APBH DMA @ 2017-06-06 16:34 ` Fabio Estevam 0 siblings, 0 replies; 26+ messages in thread From: Fabio Estevam @ 2017-06-06 16:34 UTC (permalink / raw) To: linux-arm-kernel On Tue, Jun 6, 2017 at 3:30 AM, Stefan Agner <stefan@agner.ch> wrote: > Add i.MX 7 APBH DMA and GPMI NAND modules. > > Signed-off-by: Stefan Agner <stefan@agner.ch> Tested on a imx7d-sdb: [ 1.303543] nand: device found, Manufacturer ID: 0xec, Chip ID: 0xd5 [ 1.309999] nand: Samsung NAND 2GiB 3,3V 8-bit [ 1.314467] nand: 2048 MiB, MLC, erase size: 256 KiB, page size: 2048, OOB size: 64 [ 1.346007] gpmi-nand 33002000.gpmi-nand: driver registered. Tested-by: Fabio Estevam <fabio.estevam@nxp.com> ^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH v5 2/3] ARM: dts: imx7: add GPMI NAND and APBH DMA @ 2017-06-06 16:34 ` Fabio Estevam 0 siblings, 0 replies; 26+ messages in thread From: Fabio Estevam @ 2017-06-06 16:34 UTC (permalink / raw) To: Stefan Agner Cc: Shawn Guo, Sascha Hauer, Stephen Boyd, Dong Aisheng, David Woodhouse, Brian Norris, Boris Brezillon, Marek Vasut, Richard Weinberger, robh+dt-DgEjT+Ai2ygdnm+yROfE0A, Mark Rutland, han.xu-3arQi8VN3Tc, Fabio Estevam, Lothar Waßmann, linux-mtd-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, devicetree-u79uwXL29TY76Z2rM5mHXA, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r On Tue, Jun 6, 2017 at 3:30 AM, Stefan Agner <stefan-XLVq0VzYD2Y@public.gmane.org> wrote: > Add i.MX 7 APBH DMA and GPMI NAND modules. > > Signed-off-by: Stefan Agner <stefan-XLVq0VzYD2Y@public.gmane.org> Tested on a imx7d-sdb: [ 1.303543] nand: device found, Manufacturer ID: 0xec, Chip ID: 0xd5 [ 1.309999] nand: Samsung NAND 2GiB 3,3V 8-bit [ 1.314467] nand: 2048 MiB, MLC, erase size: 256 KiB, page size: 2048, OOB size: 64 [ 1.346007] gpmi-nand 33002000.gpmi-nand: driver registered. Tested-by: Fabio Estevam <fabio.estevam-3arQi8VN3Tc@public.gmane.org> -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH v5 2/3] ARM: dts: imx7: add GPMI NAND and APBH DMA @ 2017-06-07 15:33 ` Han Xu 0 siblings, 0 replies; 26+ messages in thread From: Han Xu @ 2017-06-07 15:33 UTC (permalink / raw) To: Stefan Agner, shawnguo, kernel, sboyd Cc: A.S. Dong, dwmw2, computersforpeace, boris.brezillon, marek.vasut, richard, robh+dt, mark.rutland, fabio.estevam, LW, linux-mtd, devicetree, linux-arm-kernel, linux-clk, linux-kernel On 06/06/2017 01:30 AM, Stefan Agner wrote: > Add i.MX 7 APBH DMA and GPMI NAND modules. > > Signed-off-by: Stefan Agner <stefan@agner.ch> > --- > arch/arm/boot/dts/imx7s.dtsi | 32 ++++++++++++++++++++++++++++++++ > 1 file changed, 32 insertions(+) > > diff --git a/arch/arm/boot/dts/imx7s.dtsi b/arch/arm/boot/dts/imx7s.dtsi > index c4f12fd..d71acd8 100644 > --- a/arch/arm/boot/dts/imx7s.dtsi > +++ b/arch/arm/boot/dts/imx7s.dtsi > @@ -995,5 +995,37 @@ > status = "disabled"; > }; > }; > + > + dma_apbh: dma-apbh@33000000 { > + compatible = "fsl,imx7d-dma-apbh", "fsl,imx28-dma-apbh"; > + reg = <0x33000000 0x2000>; > + interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3"; > + #dma-cells = <1>; > + dma-channels = <4>; > + clocks = <&clks IMX7D_NAND_USDHC_BUS_RAWNAND_CLK>; > + clock-names = "dma_apbh_bch", "dma_apbh_io"; please remove the clock names, I am good with all other changes. > + }; > + > + gpmi: gpmi-nand@33002000{ > + compatible = "fsl,imx7d-gpmi-nand"; > + #address-cells = <1>; > + #size-cells = <1>; > + reg = <0x33002000 0x2000>, <0x33004000 0x4000>; > + reg-names = "gpmi-nand", "bch"; > + interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-names = "bch"; > + clocks = <&clks IMX7D_NAND_RAWNAND_CLK>, > + <&clks IMX7D_NAND_USDHC_BUS_RAWNAND_CLK>; > + clock-names = "gpmi_io", "gpmi_bch_apb"; > + dmas = <&dma_apbh 0>; > + dma-names = "rx-tx"; > + status = "disabled"; > + assigned-clocks = <&clks IMX7D_NAND_ROOT_SRC>; > + assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_500M_CLK>; > + }; > }; > }; ^ permalink raw reply [flat|nested] 26+ messages in thread
* [PATCH v5 2/3] ARM: dts: imx7: add GPMI NAND and APBH DMA @ 2017-06-07 15:33 ` Han Xu 0 siblings, 0 replies; 26+ messages in thread From: Han Xu @ 2017-06-07 15:33 UTC (permalink / raw) To: linux-arm-kernel On 06/06/2017 01:30 AM, Stefan Agner wrote: > Add i.MX 7 APBH DMA and GPMI NAND modules. > > Signed-off-by: Stefan Agner <stefan@agner.ch> > --- > arch/arm/boot/dts/imx7s.dtsi | 32 ++++++++++++++++++++++++++++++++ > 1 file changed, 32 insertions(+) > > diff --git a/arch/arm/boot/dts/imx7s.dtsi b/arch/arm/boot/dts/imx7s.dtsi > index c4f12fd..d71acd8 100644 > --- a/arch/arm/boot/dts/imx7s.dtsi > +++ b/arch/arm/boot/dts/imx7s.dtsi > @@ -995,5 +995,37 @@ > status = "disabled"; > }; > }; > + > + dma_apbh: dma-apbh at 33000000 { > + compatible = "fsl,imx7d-dma-apbh", "fsl,imx28-dma-apbh"; > + reg = <0x33000000 0x2000>; > + interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3"; > + #dma-cells = <1>; > + dma-channels = <4>; > + clocks = <&clks IMX7D_NAND_USDHC_BUS_RAWNAND_CLK>; > + clock-names = "dma_apbh_bch", "dma_apbh_io"; please remove the clock names, I am good with all other changes. > + }; > + > + gpmi: gpmi-nand at 33002000{ > + compatible = "fsl,imx7d-gpmi-nand"; > + #address-cells = <1>; > + #size-cells = <1>; > + reg = <0x33002000 0x2000>, <0x33004000 0x4000>; > + reg-names = "gpmi-nand", "bch"; > + interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-names = "bch"; > + clocks = <&clks IMX7D_NAND_RAWNAND_CLK>, > + <&clks IMX7D_NAND_USDHC_BUS_RAWNAND_CLK>; > + clock-names = "gpmi_io", "gpmi_bch_apb"; > + dmas = <&dma_apbh 0>; > + dma-names = "rx-tx"; > + status = "disabled"; > + assigned-clocks = <&clks IMX7D_NAND_ROOT_SRC>; > + assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_500M_CLK>; > + }; > }; > }; ^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH v5 2/3] ARM: dts: imx7: add GPMI NAND and APBH DMA @ 2017-06-07 15:33 ` Han Xu 0 siblings, 0 replies; 26+ messages in thread From: Han Xu @ 2017-06-07 15:33 UTC (permalink / raw) To: Stefan Agner, shawnguo, kernel, sboyd Cc: A.S. Dong, dwmw2, computersforpeace, boris.brezillon, marek.vasut, richard, robh+dt, mark.rutland, fabio.estevam, LW, linux-mtd, devicetree, linux-arm-kernel, linux-clk, linux-kernel On 06/06/2017 01:30 AM, Stefan Agner wrote: > Add i.MX 7 APBH DMA and GPMI NAND modules. > > Signed-off-by: Stefan Agner <stefan@agner.ch> > --- > arch/arm/boot/dts/imx7s.dtsi | 32 ++++++++++++++++++++++++++++++++ > 1 file changed, 32 insertions(+) > > diff --git a/arch/arm/boot/dts/imx7s.dtsi b/arch/arm/boot/dts/imx7s.dtsi > index c4f12fd..d71acd8 100644 > --- a/arch/arm/boot/dts/imx7s.dtsi > +++ b/arch/arm/boot/dts/imx7s.dtsi > @@ -995,5 +995,37 @@ > status = "disabled"; > }; > }; > + > + dma_apbh: dma-apbh@33000000 { > + compatible = "fsl,imx7d-dma-apbh", "fsl,imx28-dma-apbh"; > + reg = <0x33000000 0x2000>; > + interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3"; > + #dma-cells = <1>; > + dma-channels = <4>; > + clocks = <&clks IMX7D_NAND_USDHC_BUS_RAWNAND_CLK>; > + clock-names = "dma_apbh_bch", "dma_apbh_io"; please remove the clock names, I am good with all other changes. > + }; > + > + gpmi: gpmi-nand@33002000{ > + compatible = "fsl,imx7d-gpmi-nand"; > + #address-cells = <1>; > + #size-cells = <1>; > + reg = <0x33002000 0x2000>, <0x33004000 0x4000>; > + reg-names = "gpmi-nand", "bch"; > + interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-names = "bch"; > + clocks = <&clks IMX7D_NAND_RAWNAND_CLK>, > + <&clks IMX7D_NAND_USDHC_BUS_RAWNAND_CLK>; > + clock-names = "gpmi_io", "gpmi_bch_apb"; > + dmas = <&dma_apbh 0>; > + dma-names = "rx-tx"; > + status = "disabled"; > + assigned-clocks = <&clks IMX7D_NAND_ROOT_SRC>; > + assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_500M_CLK>; > + }; > }; > }; ^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH v5 2/3] ARM: dts: imx7: add GPMI NAND and APBH DMA @ 2017-06-07 15:33 ` Han Xu 0 siblings, 0 replies; 26+ messages in thread From: Han Xu @ 2017-06-07 15:33 UTC (permalink / raw) To: Stefan Agner, shawnguo, kernel, sboyd Cc: A.S. Dong, dwmw2, computersforpeace, boris.brezillon, marek.vasut, richard, robh+dt, mark.rutland, fabio.estevam, LW, linux-mtd, devicetree, linux-arm-kernel, linux-clk, linux-kernel On 06/06/2017 01:30 AM, Stefan Agner wrote: > Add i.MX 7 APBH DMA and GPMI NAND modules. > > Signed-off-by: Stefan Agner <stefan@agner.ch> > --- > arch/arm/boot/dts/imx7s.dtsi | 32 ++++++++++++++++++++++++++++++++ > 1 file changed, 32 insertions(+) > > diff --git a/arch/arm/boot/dts/imx7s.dtsi b/arch/arm/boot/dts/imx7s.dtsi > index c4f12fd..d71acd8 100644 > --- a/arch/arm/boot/dts/imx7s.dtsi > +++ b/arch/arm/boot/dts/imx7s.dtsi > @@ -995,5 +995,37 @@ > status =3D "disabled"; > }; > }; > + > + dma_apbh: dma-apbh@33000000 { > + compatible =3D "fsl,imx7d-dma-apbh", "fsl,imx28-dma-apbh"; > + reg =3D <0x33000000 0x2000>; > + interrupts =3D <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-names =3D "gpmi0", "gpmi1", "gpmi2", "gpmi3"; > + #dma-cells =3D <1>; > + dma-channels =3D <4>; > + clocks =3D <&clks IMX7D_NAND_USDHC_BUS_RAWNAND_CLK>; > + clock-names =3D "dma_apbh_bch", "dma_apbh_io"; please remove the clock names, I am good with all other changes. > + }; > + > + gpmi: gpmi-nand@33002000{ > + compatible =3D "fsl,imx7d-gpmi-nand"; > + #address-cells =3D <1>; > + #size-cells =3D <1>; > + reg =3D <0x33002000 0x2000>, <0x33004000 0x4000>; > + reg-names =3D "gpmi-nand", "bch"; > + interrupts =3D <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-names =3D "bch"; > + clocks =3D <&clks IMX7D_NAND_RAWNAND_CLK>, > + <&clks IMX7D_NAND_USDHC_BUS_RAWNAND_CLK>; > + clock-names =3D "gpmi_io", "gpmi_bch_apb"; > + dmas =3D <&dma_apbh 0>; > + dma-names =3D "rx-tx"; > + status =3D "disabled"; > + assigned-clocks =3D <&clks IMX7D_NAND_ROOT_SRC>; > + assigned-clock-parents =3D <&clks IMX7D_PLL_ENET_MAIN_500M_CLK>; > + }; > }; > }; ^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH v5 2/3] ARM: dts: imx7: add GPMI NAND and APBH DMA @ 2017-06-07 15:33 ` Han Xu 0 siblings, 0 replies; 26+ messages in thread From: Han Xu @ 2017-06-07 15:33 UTC (permalink / raw) To: Stefan Agner, shawnguo-DgEjT+Ai2ygdnm+yROfE0A, kernel-bIcnvbaLZ9MEGnE8C9+IrQ, sboyd-sgV2jX0FEOL9JmXXK+q4OQ Cc: A.S. Dong, dwmw2-wEGCiKHe2LqWVfeAwA7xHQ, computersforpeace-Re5JQEeQqe8AvxtiuMwx3w, boris.brezillon-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8, marek.vasut-Re5JQEeQqe8AvxtiuMwx3w, richard-/L3Ra7n9ekc, robh+dt-DgEjT+Ai2ygdnm+yROfE0A, mark.rutland-5wv7dgnIgG8, fabio.estevam-KZfg59tc24xl57MIdRCFDg, LW-bxm8fMRDkQLDiMYJYoSAnRvVK+yQ3ZXh, linux-mtd-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, devicetree-u79uwXL29TY76Z2rM5mHXA, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, linux-clk-u79uwXL29TY76Z2rM5mHXA On 06/06/2017 01:30 AM, Stefan Agner wrote: > Add i.MX 7 APBH DMA and GPMI NAND modules. > > Signed-off-by: Stefan Agner <stefan-XLVq0VzYD2Y@public.gmane.org> > --- > arch/arm/boot/dts/imx7s.dtsi | 32 ++++++++++++++++++++++++++++++++ > 1 file changed, 32 insertions(+) > > diff --git a/arch/arm/boot/dts/imx7s.dtsi b/arch/arm/boot/dts/imx7s.dtsi > index c4f12fd..d71acd8 100644 > --- a/arch/arm/boot/dts/imx7s.dtsi > +++ b/arch/arm/boot/dts/imx7s.dtsi > @@ -995,5 +995,37 @@ > status = "disabled"; > }; > }; > + > + dma_apbh: dma-apbh@33000000 { > + compatible = "fsl,imx7d-dma-apbh", "fsl,imx28-dma-apbh"; > + reg = <0x33000000 0x2000>; > + interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3"; > + #dma-cells = <1>; > + dma-channels = <4>; > + clocks = <&clks IMX7D_NAND_USDHC_BUS_RAWNAND_CLK>; > + clock-names = "dma_apbh_bch", "dma_apbh_io"; please remove the clock names, I am good with all other changes. > + }; > + > + gpmi: gpmi-nand@33002000{ > + compatible = "fsl,imx7d-gpmi-nand"; > + #address-cells = <1>; > + #size-cells = <1>; > + reg = <0x33002000 0x2000>, <0x33004000 0x4000>; > + reg-names = "gpmi-nand", "bch"; > + interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-names = "bch"; > + clocks = <&clks IMX7D_NAND_RAWNAND_CLK>, > + <&clks IMX7D_NAND_USDHC_BUS_RAWNAND_CLK>; > + clock-names = "gpmi_io", "gpmi_bch_apb"; > + dmas = <&dma_apbh 0>; > + dma-names = "rx-tx"; > + status = "disabled"; > + assigned-clocks = <&clks IMX7D_NAND_ROOT_SRC>; > + assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_500M_CLK>; > + }; > }; > }; -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH v5 2/3] ARM: dts: imx7: add GPMI NAND and APBH DMA @ 2017-06-08 22:23 ` Stefan Agner 0 siblings, 0 replies; 26+ messages in thread From: Stefan Agner @ 2017-06-08 22:23 UTC (permalink / raw) To: Han Xu Cc: shawnguo, kernel, sboyd, A.S. Dong, dwmw2, computersforpeace, boris.brezillon, marek.vasut, richard, robh+dt, mark.rutland, fabio.estevam, LW@KARO-electronics.de, linux-mtd, devicetree, linux-arm-kernel, linux-clk, linux-kernel On 2017-06-07 08:33, Han Xu wrote: > On 06/06/2017 01:30 AM, Stefan Agner wrote: >> Add i.MX 7 APBH DMA and GPMI NAND modules. >> >> Signed-off-by: Stefan Agner <stefan@agner.ch> >> --- >> arch/arm/boot/dts/imx7s.dtsi | 32 ++++++++++++++++++++++++++++++++ >> 1 file changed, 32 insertions(+) >> >> diff --git a/arch/arm/boot/dts/imx7s.dtsi b/arch/arm/boot/dts/imx7s.dtsi >> index c4f12fd..d71acd8 100644 >> --- a/arch/arm/boot/dts/imx7s.dtsi >> +++ b/arch/arm/boot/dts/imx7s.dtsi >> @@ -995,5 +995,37 @@ >> status = "disabled"; >> }; >> }; >> + >> + dma_apbh: dma-apbh@33000000 { >> + compatible = "fsl,imx7d-dma-apbh", "fsl,imx28-dma-apbh"; >> + reg = <0x33000000 0x2000>; >> + interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; >> + interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3"; >> + #dma-cells = <1>; >> + dma-channels = <4>; >> + clocks = <&clks IMX7D_NAND_USDHC_BUS_RAWNAND_CLK>; >> + clock-names = "dma_apbh_bch", "dma_apbh_io"; > > please remove the clock names, I am good with all other changes. Oh missed that, will do and send v6. -- Stefan >> + }; >> + >> + gpmi: gpmi-nand@33002000{ >> + compatible = "fsl,imx7d-gpmi-nand"; >> + #address-cells = <1>; >> + #size-cells = <1>; >> + reg = <0x33002000 0x2000>, <0x33004000 0x4000>; >> + reg-names = "gpmi-nand", "bch"; >> + interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; >> + interrupt-names = "bch"; >> + clocks = <&clks IMX7D_NAND_RAWNAND_CLK>, >> + <&clks IMX7D_NAND_USDHC_BUS_RAWNAND_CLK>; >> + clock-names = "gpmi_io", "gpmi_bch_apb"; >> + dmas = <&dma_apbh 0>; >> + dma-names = "rx-tx"; >> + status = "disabled"; >> + assigned-clocks = <&clks IMX7D_NAND_ROOT_SRC>; >> + assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_500M_CLK>; >> + }; >> }; >> }; ^ permalink raw reply [flat|nested] 26+ messages in thread
* [PATCH v5 2/3] ARM: dts: imx7: add GPMI NAND and APBH DMA @ 2017-06-08 22:23 ` Stefan Agner 0 siblings, 0 replies; 26+ messages in thread From: Stefan Agner @ 2017-06-08 22:23 UTC (permalink / raw) To: linux-arm-kernel On 2017-06-07 08:33, Han Xu wrote: > On 06/06/2017 01:30 AM, Stefan Agner wrote: >> Add i.MX 7 APBH DMA and GPMI NAND modules. >> >> Signed-off-by: Stefan Agner <stefan@agner.ch> >> --- >> arch/arm/boot/dts/imx7s.dtsi | 32 ++++++++++++++++++++++++++++++++ >> 1 file changed, 32 insertions(+) >> >> diff --git a/arch/arm/boot/dts/imx7s.dtsi b/arch/arm/boot/dts/imx7s.dtsi >> index c4f12fd..d71acd8 100644 >> --- a/arch/arm/boot/dts/imx7s.dtsi >> +++ b/arch/arm/boot/dts/imx7s.dtsi >> @@ -995,5 +995,37 @@ >> status = "disabled"; >> }; >> }; >> + >> + dma_apbh: dma-apbh at 33000000 { >> + compatible = "fsl,imx7d-dma-apbh", "fsl,imx28-dma-apbh"; >> + reg = <0x33000000 0x2000>; >> + interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; >> + interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3"; >> + #dma-cells = <1>; >> + dma-channels = <4>; >> + clocks = <&clks IMX7D_NAND_USDHC_BUS_RAWNAND_CLK>; >> + clock-names = "dma_apbh_bch", "dma_apbh_io"; > > please remove the clock names, I am good with all other changes. Oh missed that, will do and send v6. -- Stefan >> + }; >> + >> + gpmi: gpmi-nand at 33002000{ >> + compatible = "fsl,imx7d-gpmi-nand"; >> + #address-cells = <1>; >> + #size-cells = <1>; >> + reg = <0x33002000 0x2000>, <0x33004000 0x4000>; >> + reg-names = "gpmi-nand", "bch"; >> + interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; >> + interrupt-names = "bch"; >> + clocks = <&clks IMX7D_NAND_RAWNAND_CLK>, >> + <&clks IMX7D_NAND_USDHC_BUS_RAWNAND_CLK>; >> + clock-names = "gpmi_io", "gpmi_bch_apb"; >> + dmas = <&dma_apbh 0>; >> + dma-names = "rx-tx"; >> + status = "disabled"; >> + assigned-clocks = <&clks IMX7D_NAND_ROOT_SRC>; >> + assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_500M_CLK>; >> + }; >> }; >> }; ^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH v5 2/3] ARM: dts: imx7: add GPMI NAND and APBH DMA @ 2017-06-08 22:23 ` Stefan Agner 0 siblings, 0 replies; 26+ messages in thread From: Stefan Agner @ 2017-06-08 22:23 UTC (permalink / raw) To: Han Xu Cc: shawnguo-DgEjT+Ai2ygdnm+yROfE0A, kernel-bIcnvbaLZ9MEGnE8C9+IrQ, sboyd-sgV2jX0FEOL9JmXXK+q4OQ, A.S. Dong, dwmw2-wEGCiKHe2LqWVfeAwA7xHQ, computersforpeace-Re5JQEeQqe8AvxtiuMwx3w, boris.brezillon-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8, marek.vasut-Re5JQEeQqe8AvxtiuMwx3w, richard-/L3Ra7n9ekc, robh+dt-DgEjT+Ai2ygdnm+yROfE0A, mark.rutland-5wv7dgnIgG8, fabio.estevam-KZfg59tc24xl57MIdRCFDg, LW-bxm8fMRDkQLDiMYJYoSAnRvVK+yQ3ZXh@public.gmane.org, linux-mtd-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, devicetree-u79uwXL29TY76Z2rM5mHXA, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, linux-clk-u79uwXL29TY76Z2rM5mHXA, linux-kernel-u79uwXL29TY76Z2rM5mHXA On 2017-06-07 08:33, Han Xu wrote: > On 06/06/2017 01:30 AM, Stefan Agner wrote: >> Add i.MX 7 APBH DMA and GPMI NAND modules. >> >> Signed-off-by: Stefan Agner <stefan-XLVq0VzYD2Y@public.gmane.org> >> --- >> arch/arm/boot/dts/imx7s.dtsi | 32 ++++++++++++++++++++++++++++++++ >> 1 file changed, 32 insertions(+) >> >> diff --git a/arch/arm/boot/dts/imx7s.dtsi b/arch/arm/boot/dts/imx7s.dtsi >> index c4f12fd..d71acd8 100644 >> --- a/arch/arm/boot/dts/imx7s.dtsi >> +++ b/arch/arm/boot/dts/imx7s.dtsi >> @@ -995,5 +995,37 @@ >> status = "disabled"; >> }; >> }; >> + >> + dma_apbh: dma-apbh@33000000 { >> + compatible = "fsl,imx7d-dma-apbh", "fsl,imx28-dma-apbh"; >> + reg = <0x33000000 0x2000>; >> + interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; >> + interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3"; >> + #dma-cells = <1>; >> + dma-channels = <4>; >> + clocks = <&clks IMX7D_NAND_USDHC_BUS_RAWNAND_CLK>; >> + clock-names = "dma_apbh_bch", "dma_apbh_io"; > > please remove the clock names, I am good with all other changes. Oh missed that, will do and send v6. -- Stefan >> + }; >> + >> + gpmi: gpmi-nand@33002000{ >> + compatible = "fsl,imx7d-gpmi-nand"; >> + #address-cells = <1>; >> + #size-cells = <1>; >> + reg = <0x33002000 0x2000>, <0x33004000 0x4000>; >> + reg-names = "gpmi-nand", "bch"; >> + interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; >> + interrupt-names = "bch"; >> + clocks = <&clks IMX7D_NAND_RAWNAND_CLK>, >> + <&clks IMX7D_NAND_USDHC_BUS_RAWNAND_CLK>; >> + clock-names = "gpmi_io", "gpmi_bch_apb"; >> + dmas = <&dma_apbh 0>; >> + dma-names = "rx-tx"; >> + status = "disabled"; >> + assigned-clocks = <&clks IMX7D_NAND_ROOT_SRC>; >> + assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_500M_CLK>; >> + }; >> }; >> }; -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply [flat|nested] 26+ messages in thread
* [PATCH v5 3/3] ARM: dts: imx7-colibri: add NAND support 2017-06-06 6:30 ` Stefan Agner @ 2017-06-06 6:30 ` Stefan Agner -1 siblings, 0 replies; 26+ messages in thread From: Stefan Agner @ 2017-06-06 6:30 UTC (permalink / raw) To: shawnguo, kernel, sboyd Cc: aisheng.dong, dwmw2, computersforpeace, boris.brezillon, marek.vasut, richard, robh+dt, mark.rutland, han.xu, fabio.estevam, LW, linux-mtd, devicetree, linux-arm-kernel, linux-clk, linux-kernel, Stefan Agner The Colibri iMX7 modules come with 512MB on-module SLC NAND flash populated. Make use of it by enabling the GPMI controller. Signed-off-by: Stefan Agner <stefan@agner.ch> --- arch/arm/boot/dts/imx7-colibri.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm/boot/dts/imx7-colibri.dtsi b/arch/arm/boot/dts/imx7-colibri.dtsi index 2d87489..ad4ce19 100644 --- a/arch/arm/boot/dts/imx7-colibri.dtsi +++ b/arch/arm/boot/dts/imx7-colibri.dtsi @@ -106,6 +106,15 @@ fsl,magic-packet; }; +&gpmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpmi_nand>; + fsl,use-minimum-ecc; + nand-on-flash-bbt; + nand-ecc-mode = "hw"; + status = "okay"; +}; + &i2c1 { clock-frequency = <100000>; pinctrl-names = "default"; -- git-series 0.9.1 ^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PATCH v5 3/3] ARM: dts: imx7-colibri: add NAND support @ 2017-06-06 6:30 ` Stefan Agner 0 siblings, 0 replies; 26+ messages in thread From: Stefan Agner @ 2017-06-06 6:30 UTC (permalink / raw) To: linux-arm-kernel The Colibri iMX7 modules come with 512MB on-module SLC NAND flash populated. Make use of it by enabling the GPMI controller. Signed-off-by: Stefan Agner <stefan@agner.ch> --- arch/arm/boot/dts/imx7-colibri.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm/boot/dts/imx7-colibri.dtsi b/arch/arm/boot/dts/imx7-colibri.dtsi index 2d87489..ad4ce19 100644 --- a/arch/arm/boot/dts/imx7-colibri.dtsi +++ b/arch/arm/boot/dts/imx7-colibri.dtsi @@ -106,6 +106,15 @@ fsl,magic-packet; }; +&gpmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpmi_nand>; + fsl,use-minimum-ecc; + nand-on-flash-bbt; + nand-ecc-mode = "hw"; + status = "okay"; +}; + &i2c1 { clock-frequency = <100000>; pinctrl-names = "default"; -- git-series 0.9.1 ^ permalink raw reply related [flat|nested] 26+ messages in thread
* Re: [PATCH v5 3/3] ARM: dts: imx7-colibri: add NAND support @ 2017-06-06 16:35 ` Fabio Estevam 0 siblings, 0 replies; 26+ messages in thread From: Fabio Estevam @ 2017-06-06 16:35 UTC (permalink / raw) To: Stefan Agner Cc: Shawn Guo, Sascha Hauer, Stephen Boyd, Dong Aisheng, David Woodhouse, Brian Norris, Boris Brezillon, Marek Vasut, Richard Weinberger, robh+dt, Mark Rutland, han.xu, Fabio Estevam, Lothar Waßmann, linux-mtd, devicetree, linux-arm-kernel, linux-clk, linux-kernel On Tue, Jun 6, 2017 at 3:30 AM, Stefan Agner <stefan@agner.ch> wrote: > The Colibri iMX7 modules come with 512MB on-module SLC NAND flash > populated. Make use of it by enabling the GPMI controller. > > Signed-off-by: Stefan Agner <stefan@agner.ch> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com> ^ permalink raw reply [flat|nested] 26+ messages in thread
* [PATCH v5 3/3] ARM: dts: imx7-colibri: add NAND support @ 2017-06-06 16:35 ` Fabio Estevam 0 siblings, 0 replies; 26+ messages in thread From: Fabio Estevam @ 2017-06-06 16:35 UTC (permalink / raw) To: linux-arm-kernel On Tue, Jun 6, 2017 at 3:30 AM, Stefan Agner <stefan@agner.ch> wrote: > The Colibri iMX7 modules come with 512MB on-module SLC NAND flash > populated. Make use of it by enabling the GPMI controller. > > Signed-off-by: Stefan Agner <stefan@agner.ch> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com> ^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH v5 3/3] ARM: dts: imx7-colibri: add NAND support @ 2017-06-06 16:35 ` Fabio Estevam 0 siblings, 0 replies; 26+ messages in thread From: Fabio Estevam @ 2017-06-06 16:35 UTC (permalink / raw) To: Stefan Agner Cc: Shawn Guo, Sascha Hauer, Stephen Boyd, Dong Aisheng, David Woodhouse, Brian Norris, Boris Brezillon, Marek Vasut, Richard Weinberger, robh+dt-DgEjT+Ai2ygdnm+yROfE0A, Mark Rutland, han.xu-3arQi8VN3Tc, Fabio Estevam, Lothar Waßmann, linux-mtd-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, devicetree-u79uwXL29TY76Z2rM5mHXA, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r On Tue, Jun 6, 2017 at 3:30 AM, Stefan Agner <stefan-XLVq0VzYD2Y@public.gmane.org> wrote: > The Colibri iMX7 modules come with 512MB on-module SLC NAND flash > populated. Make use of it by enabling the GPMI controller. > > Signed-off-by: Stefan Agner <stefan-XLVq0VzYD2Y@public.gmane.org> Reviewed-by: Fabio Estevam <fabio.estevam-3arQi8VN3Tc@public.gmane.org> -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html ^ permalink raw reply [flat|nested] 26+ messages in thread
end of thread, other threads:[~2017-06-08 22:24 UTC | newest] Thread overview: 26+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2017-06-06 6:30 [PATCH v5 0/3] ARM: dts: imx7: add NAND support Stefan Agner 2017-06-06 6:30 ` Stefan Agner 2017-06-06 6:30 ` [PATCH v5 1/3] clk: imx7d: create clocks behind rawnand clock gate Stefan Agner 2017-06-06 6:30 ` Stefan Agner 2017-06-06 6:30 ` Stefan Agner 2017-06-06 16:33 ` Fabio Estevam 2017-06-06 16:33 ` Fabio Estevam 2017-06-06 16:33 ` Fabio Estevam 2017-06-06 6:30 ` [PATCH v5 2/3] ARM: dts: imx7: add GPMI NAND and APBH DMA Stefan Agner 2017-06-06 6:30 ` Stefan Agner 2017-06-06 16:34 ` Fabio Estevam 2017-06-06 16:34 ` Fabio Estevam 2017-06-06 16:34 ` Fabio Estevam 2017-06-07 15:33 ` Han Xu 2017-06-07 15:33 ` Han Xu 2017-06-07 15:33 ` Han Xu 2017-06-07 15:33 ` Han Xu 2017-06-07 15:33 ` Han Xu 2017-06-08 22:23 ` Stefan Agner 2017-06-08 22:23 ` Stefan Agner 2017-06-08 22:23 ` Stefan Agner 2017-06-06 6:30 ` [PATCH v5 3/3] ARM: dts: imx7-colibri: add NAND support Stefan Agner 2017-06-06 6:30 ` Stefan Agner 2017-06-06 16:35 ` Fabio Estevam 2017-06-06 16:35 ` Fabio Estevam 2017-06-06 16:35 ` Fabio Estevam
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