* [PATCH v4] hw: m25p80: add tests for write protect (WP# and SRWD bit)
@ 2022-06-24 18:30 Iris Chen
2022-06-27 9:44 ` Cédric Le Goater
0 siblings, 1 reply; 2+ messages in thread
From: Iris Chen @ 2022-06-24 18:30 UTC (permalink / raw)
Cc: irischenlj, pdel, qemu-devel, qemu-arm, clg, patrick, alistair,
kwolf, hreitz, peter.maydell, andrew, joel, thuth, lvivier,
pbonzini, qemu-block
Signed-off-by: Iris Chen <irischenlj@fb.com>
---
Adding Signed Off By tag -- sorry I missed that !
tests/qtest/aspeed_smc-test.c | 62 +++++++++++++++++++++++++++++++++++
1 file changed, 62 insertions(+)
diff --git a/tests/qtest/aspeed_smc-test.c b/tests/qtest/aspeed_smc-test.c
index ec233315e6..7786addfb8 100644
--- a/tests/qtest/aspeed_smc-test.c
+++ b/tests/qtest/aspeed_smc-test.c
@@ -56,7 +56,9 @@ enum {
BULK_ERASE = 0xc7,
READ = 0x03,
PP = 0x02,
+ WRSR = 0x1,
WREN = 0x6,
+ SRWD = 0x80,
RESET_ENABLE = 0x66,
RESET_MEMORY = 0x99,
EN_4BYTE_ADDR = 0xB7,
@@ -390,6 +392,64 @@ static void test_read_status_reg(void)
flash_reset();
}
+static void test_status_reg_write_protection(void)
+{
+ uint8_t r;
+
+ spi_conf(CONF_ENABLE_W0);
+
+ /* default case: WP# is high and SRWD is low -> status register writable */
+ spi_ctrl_start_user();
+ writeb(ASPEED_FLASH_BASE, WREN);
+ /* test ability to write SRWD */
+ writeb(ASPEED_FLASH_BASE, WRSR);
+ writeb(ASPEED_FLASH_BASE, SRWD);
+ writeb(ASPEED_FLASH_BASE, RDSR);
+ r = readb(ASPEED_FLASH_BASE);
+ spi_ctrl_stop_user();
+ g_assert_cmphex(r & SRWD, ==, SRWD);
+
+ /* WP# high and SRWD high -> status register writable */
+ spi_ctrl_start_user();
+ writeb(ASPEED_FLASH_BASE, WREN);
+ /* test ability to write SRWD */
+ writeb(ASPEED_FLASH_BASE, WRSR);
+ writeb(ASPEED_FLASH_BASE, 0);
+ writeb(ASPEED_FLASH_BASE, RDSR);
+ r = readb(ASPEED_FLASH_BASE);
+ spi_ctrl_stop_user();
+ g_assert_cmphex(r & SRWD, ==, 0);
+
+ /* WP# low and SRWD low -> status register writable */
+ qtest_set_irq_in(global_qtest,
+ "/machine/soc/fmc/ssi.0/child[0]", "WP#", 0, 0);
+ spi_ctrl_start_user();
+ writeb(ASPEED_FLASH_BASE, WREN);
+ /* test ability to write SRWD */
+ writeb(ASPEED_FLASH_BASE, WRSR);
+ writeb(ASPEED_FLASH_BASE, SRWD);
+ writeb(ASPEED_FLASH_BASE, RDSR);
+ r = readb(ASPEED_FLASH_BASE);
+ spi_ctrl_stop_user();
+ g_assert_cmphex(r & SRWD, ==, SRWD);
+
+ /* WP# low and SRWD high -> status register NOT writable */
+ spi_ctrl_start_user();
+ writeb(ASPEED_FLASH_BASE, WREN);
+ /* test ability to write SRWD */
+ writeb(ASPEED_FLASH_BASE, WRSR);
+ writeb(ASPEED_FLASH_BASE, 0);
+ writeb(ASPEED_FLASH_BASE, RDSR);
+ r = readb(ASPEED_FLASH_BASE);
+ spi_ctrl_stop_user();
+ /* write is not successful */
+ g_assert_cmphex(r & SRWD, ==, SRWD);
+
+ qtest_set_irq_in(global_qtest,
+ "/machine/soc/fmc/ssi.0/child[0]", "WP#", 0, 1);
+ flash_reset();
+}
+
static char tmp_path[] = "/tmp/qtest.m25p80.XXXXXX";
int main(int argc, char **argv)
@@ -416,6 +476,8 @@ int main(int argc, char **argv)
qtest_add_func("/ast2400/smc/read_page_mem", test_read_page_mem);
qtest_add_func("/ast2400/smc/write_page_mem", test_write_page_mem);
qtest_add_func("/ast2400/smc/read_status_reg", test_read_status_reg);
+ qtest_add_func("/ast2400/smc/status_reg_write_protection",
+ test_status_reg_write_protection);
ret = g_test_run();
--
2.30.2
^ permalink raw reply related [flat|nested] 2+ messages in thread
* Re: [PATCH v4] hw: m25p80: add tests for write protect (WP# and SRWD bit)
2022-06-24 18:30 [PATCH v4] hw: m25p80: add tests for write protect (WP# and SRWD bit) Iris Chen
@ 2022-06-27 9:44 ` Cédric Le Goater
0 siblings, 0 replies; 2+ messages in thread
From: Cédric Le Goater @ 2022-06-27 9:44 UTC (permalink / raw)
To: Iris Chen
Cc: pdel, qemu-devel, qemu-arm, patrick, alistair, kwolf, hreitz,
peter.maydell, andrew, joel, thuth, lvivier, pbonzini,
qemu-block
On 6/24/22 20:30, Iris Chen wrote:
> Signed-off-by: Iris Chen <irischenlj@fb.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Thanks,
C.
> ---
> Adding Signed Off By tag -- sorry I missed that !
>
> tests/qtest/aspeed_smc-test.c | 62 +++++++++++++++++++++++++++++++++++
> 1 file changed, 62 insertions(+)
>
> diff --git a/tests/qtest/aspeed_smc-test.c b/tests/qtest/aspeed_smc-test.c
> index ec233315e6..7786addfb8 100644
> --- a/tests/qtest/aspeed_smc-test.c
> +++ b/tests/qtest/aspeed_smc-test.c
> @@ -56,7 +56,9 @@ enum {
> BULK_ERASE = 0xc7,
> READ = 0x03,
> PP = 0x02,
> + WRSR = 0x1,
> WREN = 0x6,
> + SRWD = 0x80,
> RESET_ENABLE = 0x66,
> RESET_MEMORY = 0x99,
> EN_4BYTE_ADDR = 0xB7,
> @@ -390,6 +392,64 @@ static void test_read_status_reg(void)
> flash_reset();
> }
>
> +static void test_status_reg_write_protection(void)
> +{
> + uint8_t r;
> +
> + spi_conf(CONF_ENABLE_W0);
> +
> + /* default case: WP# is high and SRWD is low -> status register writable */
> + spi_ctrl_start_user();
> + writeb(ASPEED_FLASH_BASE, WREN);
> + /* test ability to write SRWD */
> + writeb(ASPEED_FLASH_BASE, WRSR);
> + writeb(ASPEED_FLASH_BASE, SRWD);
> + writeb(ASPEED_FLASH_BASE, RDSR);
> + r = readb(ASPEED_FLASH_BASE);
> + spi_ctrl_stop_user();
> + g_assert_cmphex(r & SRWD, ==, SRWD);
> +
> + /* WP# high and SRWD high -> status register writable */
> + spi_ctrl_start_user();
> + writeb(ASPEED_FLASH_BASE, WREN);
> + /* test ability to write SRWD */
> + writeb(ASPEED_FLASH_BASE, WRSR);
> + writeb(ASPEED_FLASH_BASE, 0);
> + writeb(ASPEED_FLASH_BASE, RDSR);
> + r = readb(ASPEED_FLASH_BASE);
> + spi_ctrl_stop_user();
> + g_assert_cmphex(r & SRWD, ==, 0);
> +
> + /* WP# low and SRWD low -> status register writable */
> + qtest_set_irq_in(global_qtest,
> + "/machine/soc/fmc/ssi.0/child[0]", "WP#", 0, 0);
> + spi_ctrl_start_user();
> + writeb(ASPEED_FLASH_BASE, WREN);
> + /* test ability to write SRWD */
> + writeb(ASPEED_FLASH_BASE, WRSR);
> + writeb(ASPEED_FLASH_BASE, SRWD);
> + writeb(ASPEED_FLASH_BASE, RDSR);
> + r = readb(ASPEED_FLASH_BASE);
> + spi_ctrl_stop_user();
> + g_assert_cmphex(r & SRWD, ==, SRWD);
> +
> + /* WP# low and SRWD high -> status register NOT writable */
> + spi_ctrl_start_user();
> + writeb(ASPEED_FLASH_BASE, WREN);
> + /* test ability to write SRWD */
> + writeb(ASPEED_FLASH_BASE, WRSR);
> + writeb(ASPEED_FLASH_BASE, 0);
> + writeb(ASPEED_FLASH_BASE, RDSR);
> + r = readb(ASPEED_FLASH_BASE);
> + spi_ctrl_stop_user();
> + /* write is not successful */
> + g_assert_cmphex(r & SRWD, ==, SRWD);
> +
> + qtest_set_irq_in(global_qtest,
> + "/machine/soc/fmc/ssi.0/child[0]", "WP#", 0, 1);
> + flash_reset();
> +}
> +
> static char tmp_path[] = "/tmp/qtest.m25p80.XXXXXX";
>
> int main(int argc, char **argv)
> @@ -416,6 +476,8 @@ int main(int argc, char **argv)
> qtest_add_func("/ast2400/smc/read_page_mem", test_read_page_mem);
> qtest_add_func("/ast2400/smc/write_page_mem", test_write_page_mem);
> qtest_add_func("/ast2400/smc/read_status_reg", test_read_status_reg);
> + qtest_add_func("/ast2400/smc/status_reg_write_protection",
> + test_status_reg_write_protection);
>
> ret = g_test_run();
>
^ permalink raw reply [flat|nested] 2+ messages in thread
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2022-06-24 18:30 [PATCH v4] hw: m25p80: add tests for write protect (WP# and SRWD bit) Iris Chen
2022-06-27 9:44 ` Cédric Le Goater
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