[PATCH 0/3] arm64: dts: qcom: Fix PMU and timer interrupt properties

[PATCH 0/3] arm64: dts: qcom: Fix PMU and timer interrupt properties

[Sai Prakash Ranjan]

Fix PMU interrupt polarity for SM8250 and SM8350 SoCs and the timer
interrupt property for SM8250 SoC.

Sai Prakash Ranjan (3):
  arm64: dts: qcom: sm8250: Fix level triggered PMU interrupt polarity
  arm64: dts: qcom: sm8350: Fix level triggered PMU interrupt polarity
  arm64: dts: qcom: sm8250: Fix timer interrupt to specify EL2 physical
    timer

 arch/arm64/boot/dts/qcom/sm8250.dtsi | 4 ++--
 arch/arm64/boot/dts/qcom/sm8350.dtsi | 2 +-
 2 files changed, 3 insertions(+), 3 deletions(-)


base-commit: d79b47c59576a51d8e288a6b98b75ccf4afb8acd
-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation

[PATCH 1/3] arm64: dts: qcom: sm8250: Fix level triggered PMU interrupt polarity

[Sai Prakash Ranjan]

As per interrupt documentation for SM8250 SoC, the polarity
for level triggered PMU interrupt is low, fix this.

Fixes: 60378f1a171e ("arm64: dts: qcom: sm8250: Add sm8250 dts file")
Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
---
 arch/arm64/boot/dts/qcom/sm8250.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi
index 947e1accae3a..1864c459a563 100644
--- a/arch/arm64/boot/dts/qcom/sm8250.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi
@@ -279,7 +279,7 @@ mmcx_reg: mmcx-reg {
 
 	pmu {
 		compatible = "arm,armv8-pmuv3";
-		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
 	};
 
 	psci {
-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation

[PATCH 2/3] arm64: dts: qcom: sm8350: Fix level triggered PMU interrupt polarity

[Sai Prakash Ranjan]

As per interrupt documentation for SM8350 SoC, the polarity
for level triggered PMU interrupt is low, fix this.

Fixes: b7e8f433a673 ("arm64: dts: qcom: Add basic devicetree support for SM8350 SoC")
Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
---
 arch/arm64/boot/dts/qcom/sm8350.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi
index 5ef460458f5c..e8bf3f95c674 100644
--- a/arch/arm64/boot/dts/qcom/sm8350.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi
@@ -153,7 +153,7 @@ memory@80000000 {
 
 	pmu {
 		compatible = "arm,armv8-pmuv3";
-		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
+		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
 	};
 
 	psci {
-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation

[PATCH 3/3] arm64: dts: qcom: sm8250: Fix timer interrupt to specify EL2 physical timer

[Sai Prakash Ranjan]

ARM architected timer interrupts DT property specifies EL2/HYP
physical interrupt and not EL2/HYP virtual interrupt for the 4th
interrupt property. As per interrupt documentation for SM8250 SoC,
the EL2/HYP physical timer interrupt is 10 and EL2/HYP virtual timer
interrupt is 12, so fix the 4th timer interrupt to be EL2 physical
timer interrupt (10 in this case).

Fixes: 60378f1a171e ("arm64: dts: qcom: sm8250: Add sm8250 dts file")
Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
---
 arch/arm64/boot/dts/qcom/sm8250.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi
index 1864c459a563..3232ac6253bb 100644
--- a/arch/arm64/boot/dts/qcom/sm8250.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi
@@ -3754,7 +3754,7 @@ timer {
 				(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
 			     <GIC_PPI 11
 				(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
-			     <GIC_PPI 12
+			     <GIC_PPI 10
 				(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
 	};
 
-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation

Re: [PATCH 0/3] arm64: dts: qcom: Fix PMU and timer interrupt properties

[patchwork-bot+linux-arm-msm]

Hello:

This series was applied to qcom/linux.git (refs/heads/for-next):

On Tue, 16 Feb 2021 15:17:46 +0530 you wrote:
> Fix PMU interrupt polarity for SM8250 and SM8350 SoCs and the timer
> interrupt property for SM8250 SoC.
> 
> Sai Prakash Ranjan (3):
>   arm64: dts: qcom: sm8250: Fix level triggered PMU interrupt polarity
>   arm64: dts: qcom: sm8350: Fix level triggered PMU interrupt polarity
>   arm64: dts: qcom: sm8250: Fix timer interrupt to specify EL2 physical
>     timer
> 
> [...]

Here is the summary with links:
  - [1/3] arm64: dts: qcom: sm8250: Fix level triggered PMU interrupt polarity
    https://git.kernel.org/qcom/c/7c735d4d11d3
  - [2/3] arm64: dts: qcom: sm8350: Fix level triggered PMU interrupt polarity
    https://git.kernel.org/qcom/c/5bf90503f1d6
  - [3/3] arm64: dts: qcom: sm8250: Fix timer interrupt to specify EL2 physical timer
    https://git.kernel.org/qcom/c/621d0639fbb2

You are awesome, thank you!
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