* [RFC PATCH 00/34] Compile accel/tcg once (partially)
@ 2024-01-19 14:39 Anton Johansson via
2024-01-19 14:39 ` [RFC PATCH 01/34] target: [PAGE_VARY] Use PAGE_VARY for all softmmu targets Anton Johansson via
` (33 more replies)
0 siblings, 34 replies; 83+ messages in thread
From: Anton Johansson via @ 2024-01-19 14:39 UTC (permalink / raw)
To: qemu-devel; +Cc: ale, richard.henderson, philmd
Based on an older version of rth/tcg-next and some patches by me, Philippe,
and Richard (most of which have since been merged), base branch here
https://gitlab.com/AntonJohansson/qemu/-/tree/feature/accel-tcg-once-base
Rebase is in the works, but should not affect the larger parts of this
patchset that I'm looking for feedback on.
This patchset moves forward with the single binary/compile once work and
tries to compile translation units in accel/tcg/ once for system mode.
The following files are compiled once in this patchset
cputlb.c
tcg-all.c
tcg-runtime.c
tcg-runtime-gvec.c
tb-maint.c
plugin-gen.c
translate-all.c
and debuginfo.c is also moved to common_ss as it doesn't contain any
target specifics. Work still remains for
cpu-exec.c (TARGET_I386 ifdefs)
translator.c (tswap(), ldl_p() and friends)
Brackets [...] in patch names are temporary and indicate patches that
"belong" together and can be split out easier.
Major changes which I'm looking for feedback on:
- [PAGE_VARY] patches:
Switches to variable page sizes as a default for all system
mode targets, meaning TARGET_PAGE_* and TLB_* become target
independent.
- "Uninline cpu_mmu_index()"/"Uninline cpu_get_tb_cpu_state()":
Uninlines cpu_mmu_index() (used by cputlb.c) and
cpu_get_tb_cpu_state() (used by translate-all.c) so they can be
called from accel/tcg without pulling in target specifics.
- "Wrap target macros in functions":
Introduces wrapper functions in cpu-target.c around target
macros that I'm not sure how to deal with.
Anton Johansson (34):
target: [PAGE_VARY] Use PAGE_VARY for all softmmu targets
target: [PAGE_VARY] Move TARGET_PAGE_BITS_MIN to TargetPageBits
exec: [PAGE_VARY] Move TARGET_PAGE_BITS_VARY to common header
exec: [PAGE_VARY] Unpoison TARGET_PAGE_* macros for system mode
target/tricore: [VADDR] Use target_ulong for EA
exec: [VADDR] Move vaddr defines to separate file
hw/core: [VADDR] Include vaddr.h from cpu.h
target: [VADDR] Use vaddr in gen_intermediate_code
exec: [VADDR] Use vaddr in DisasContextBase for virtual addresses
exec: [VADDR] typedef abi_ptr to vaddr
[IGNORE] Squash of header code shuffling
target: Uninline cpu_mmu_index()
target: Uninline cpu_get_tb_cpu_state()
exec: [CPUTLB] Move PAGE_* macros to common header
exec: [CPUTLB] Move TLB_*/tlb_*() to common header
exec: [CPUTLB] Move cpu_*()/cpu_env() to common header
hw/core: [CPUTLB] Move target specifics to end of TCGCPUOps
accel/stubs: [CPUTLB] Move xen.h stubs to xen-stub.c
accel/tcg: [CPUTLB] Use TCGContext.addr_type instead of
TARGET_LONG_BITS
accel/tcg: [CPUTLB] Use TCGContext.guest_mo for memory ordering
accel/tcg: [CPUTLB] Use tcg_ctx->tlb_dyn_max_bits
accel/tcg: [CPUTLB] Move CPU_TLB_DYN_[DEFAULT|MIN]* to cputlb.c
tcg: [CPUTLB] Add `mo_te` field to TCGContext
accel/tcg: [CPUTLB] Set mo_te in TCGContext
accel/tcg: [CPUTLB] Use tcg_ctx->mo_te instead of MO_TE
Wrap target macros in functions
accel/tcg: Make translate-all.c target independent
accel/tcg: Make plugin-gen.c target independent
accel/tcg: Make tb-maint.c target indpendent
accel/tcg: Make tcg-all.c target indpendent
accel/tcg: Make tcg-runtime-gvec.c target independent
accel/tcg: Make tcg-runtime.c target independent
accel/tcg: Make translator.c (partially) target independent
accel/tcg: Compile (a few files) once for system-mode
accel/tcg/internal-target.h | 11 +-
accel/tcg/tb-hash.h | 4 +-
hw/s390x/s390-virtio-hcall.h | 2 +
include/exec/cpu-all.h | 156 +-------------
include/exec/cpu-common.h | 185 ++++++++++++++++-
include/exec/cpu-defs.h | 7 +-
include/exec/cpu_ldst-target.h | 52 +++++
include/exec/cpu_ldst.h | 95 +++------
include/exec/exec-all.h | 347 +------------------------------
include/exec/exec-common.h | 367 +++++++++++++++++++++++++++++++++
include/exec/memory-internal.h | 2 +-
include/exec/page-vary.h | 1 +
include/exec/poison.h | 2 +
include/exec/ram_addr.h | 3 +-
include/exec/translator.h | 8 +-
include/exec/vaddr.h | 18 ++
include/hw/core/cpu.h | 11 +-
include/hw/core/tcg-cpu-ops.h | 32 +--
include/qemu/plugin-memory.h | 1 -
include/sysemu/xen.h | 27 ---
include/tcg/tcg.h | 1 +
target/alpha/cpu-param.h | 6 +
target/alpha/cpu.h | 20 --
target/arm/cpu-param.h | 2 +-
target/arm/cpu.h | 16 --
target/avr/cpu-param.h | 6 +
target/avr/cpu.h | 24 ---
target/cris/cpu-param.h | 7 +
target/cris/cpu.h | 14 --
target/hexagon/cpu.h | 21 --
target/hppa/cpu-param.h | 6 +
target/hppa/cpu.h | 55 -----
target/i386/cpu-param.h | 6 +
target/i386/cpu.h | 16 --
target/loongarch/cpu-param.h | 5 +
target/loongarch/cpu.h | 23 ---
target/m68k/cpu-param.h | 6 +
target/m68k/cpu.h | 20 --
target/microblaze/cpu-param.h | 6 +-
target/microblaze/cpu.h | 23 ---
target/mips/cpu-param.h | 2 +-
target/mips/cpu.h | 23 +--
target/mips/tcg/translate.h | 3 +-
target/nios2/cpu-param.h | 5 +-
target/nios2/cpu.h | 18 --
target/openrisc/cpu-param.h | 8 +-
target/openrisc/cpu.h | 22 --
target/ppc/cpu-param.h | 6 +
target/ppc/cpu.h | 21 --
target/riscv/cpu-param.h | 7 +
target/riscv/cpu.h | 5 -
target/rx/cpu-param.h | 8 +-
target/rx/cpu.h | 14 --
target/s390x/cpu-param.h | 8 +-
target/s390x/cpu.h | 53 -----
target/sh4/cpu-param.h | 4 +-
target/sh4/cpu.h | 25 ---
target/sparc/cpu-param.h | 17 +-
target/sparc/cpu.h | 63 ------
target/tricore/cpu-param.h | 8 +-
target/tricore/cpu.h | 17 --
target/xtensa/cpu-param.h | 8 +-
target/xtensa/cpu.h | 73 -------
accel/stubs/xen-stub.c | 12 ++
accel/tcg/cpu-exec.c | 1 +
accel/tcg/cputlb.c | 51 +++--
accel/tcg/plugin-gen.c | 15 +-
accel/tcg/tb-maint.c | 47 +++--
accel/tcg/tcg-all.c | 25 +--
accel/tcg/tcg-runtime-gvec.c | 2 +-
accel/tcg/tcg-runtime.c | 2 +-
accel/tcg/translate-all.c | 40 ++--
accel/tcg/translator.c | 16 +-
cpu-target.c | 62 ++++++
page-vary-common.c | 1 +
page-vary-target.c | 4 +-
plugins/core.c | 1 +
target/alpha/cpu.c | 19 ++
target/alpha/translate.c | 2 +-
target/arm/cpu.c | 6 +
target/arm/tcg/translate.c | 6 +-
target/avr/cpu.c | 23 +++
target/avr/translate.c | 2 +-
target/cris/cpu.c | 14 ++
target/cris/translate.c | 2 +-
target/hexagon/cpu.c | 21 ++
target/hexagon/translate.c | 5 +-
target/hppa/cpu.c | 59 ++++++
target/hppa/translate.c | 2 +-
target/i386/cpu.c | 16 ++
target/i386/tcg/translate.c | 2 +-
target/loongarch/cpu.c | 23 +++
target/loongarch/translate.c | 2 +-
target/m68k/cpu.c | 21 ++
target/m68k/translate.c | 4 +-
target/microblaze/cpu.c | 23 +++
target/microblaze/translate.c | 2 +-
target/mips/cpu.c | 23 +++
target/mips/tcg/translate.c | 14 +-
target/nios2/cpu.c | 18 ++
target/nios2/translate.c | 2 +-
target/openrisc/cpu.c | 22 ++
target/openrisc/translate.c | 2 +-
target/ppc/cpu.c | 20 ++
target/ppc/translate.c | 2 +-
target/riscv/cpu_helper.c | 2 +-
target/riscv/translate.c | 2 +-
target/rx/cpu.c | 14 ++
target/rx/translate.c | 2 +-
target/s390x/cpu.c | 55 +++++
target/s390x/tcg/translate.c | 2 +-
target/sh4/cpu.c | 28 +++
target/sh4/translate.c | 2 +-
target/sparc/cpu.c | 63 ++++++
target/sparc/gdbstub.c | 3 +
target/sparc/translate.c | 2 +-
target/tricore/cpu.c | 17 ++
target/tricore/op_helper.c | 8 +-
target/tricore/translate.c | 2 +-
target/xtensa/cpu.c | 72 +++++++
target/xtensa/translate.c | 2 +-
accel/tcg/meson.build | 57 +++--
122 files changed, 1656 insertions(+), 1345 deletions(-)
create mode 100644 include/exec/cpu_ldst-target.h
create mode 100644 include/exec/exec-common.h
create mode 100644 include/exec/vaddr.h
--
2.43.0
^ permalink raw reply [flat|nested] 83+ messages in thread
* [RFC PATCH 01/34] target: [PAGE_VARY] Use PAGE_VARY for all softmmu targets
2024-01-19 14:39 [RFC PATCH 00/34] Compile accel/tcg once (partially) Anton Johansson via
@ 2024-01-19 14:39 ` Anton Johansson via
2024-01-19 16:05 ` Philippe Mathieu-Daudé
2024-01-19 14:39 ` [RFC PATCH 02/34] target: [PAGE_VARY] Move TARGET_PAGE_BITS_MIN to TargetPageBits Anton Johansson via
` (32 subsequent siblings)
33 siblings, 1 reply; 83+ messages in thread
From: Anton Johansson via @ 2024-01-19 14:39 UTC (permalink / raw)
To: qemu-devel; +Cc: ale, richard.henderson, philmd
Allows for future commits to use TargetPageBits to access page bits and
mask, thus making TARGET_PAGE_* independent of softmmu target.
In the future, this will also be important fo allowing heterogeneous CPUs
on the same board.
Signed-off-by: Anton Johansson <anjo@rev.ng>
---
target/alpha/cpu-param.h | 6 ++++++
target/avr/cpu-param.h | 6 ++++++
target/cris/cpu-param.h | 7 +++++++
target/hppa/cpu-param.h | 6 ++++++
target/i386/cpu-param.h | 6 ++++++
target/loongarch/cpu-param.h | 5 +++++
target/m68k/cpu-param.h | 6 ++++++
target/microblaze/cpu-param.h | 6 ++++--
target/nios2/cpu-param.h | 5 ++++-
target/openrisc/cpu-param.h | 8 +++++++-
target/ppc/cpu-param.h | 6 ++++++
target/riscv/cpu-param.h | 7 +++++++
target/rx/cpu-param.h | 8 +++++++-
target/s390x/cpu-param.h | 8 +++++++-
target/sh4/cpu-param.h | 4 +++-
target/sparc/cpu-param.h | 17 +++++++++++++++--
target/tricore/cpu-param.h | 8 +++++++-
target/xtensa/cpu-param.h | 8 +++++---
18 files changed, 114 insertions(+), 13 deletions(-)
diff --git a/target/alpha/cpu-param.h b/target/alpha/cpu-param.h
index 68c46f7998..dc9da45bdf 100644
--- a/target/alpha/cpu-param.h
+++ b/target/alpha/cpu-param.h
@@ -9,7 +9,13 @@
#define ALPHA_CPU_PARAM_H
#define TARGET_LONG_BITS 64
+
+#ifdef CONFIG_USER_ONLY
#define TARGET_PAGE_BITS 13
+#else
+#define TARGET_PAGE_BITS_VARY
+#define TARGET_PAGE_BITS_MIN 13
+#endif
/* ??? EV4 has 34 phys addr bits, EV5 has 40, EV6 has 44. */
#define TARGET_PHYS_ADDR_SPACE_BITS 44
diff --git a/target/avr/cpu-param.h b/target/avr/cpu-param.h
index 9a92bc74fc..87142069fe 100644
--- a/target/avr/cpu-param.h
+++ b/target/avr/cpu-param.h
@@ -28,7 +28,13 @@
* should be implemented as a device and not memory
* 2. SRAM starts at the address 0x0100
*/
+#ifdef CONFIG_USER_ONLY
#define TARGET_PAGE_BITS 8
+#else
+#define TARGET_PAGE_BITS_VARY
+#define TARGET_PAGE_BITS_MIN 8
+#endif
+
#define TARGET_PHYS_ADDR_SPACE_BITS 24
#define TARGET_VIRT_ADDR_SPACE_BITS 24
diff --git a/target/cris/cpu-param.h b/target/cris/cpu-param.h
index b31b742c0d..9c66ca9e66 100644
--- a/target/cris/cpu-param.h
+++ b/target/cris/cpu-param.h
@@ -9,7 +9,14 @@
#define CRIS_CPU_PARAM_H
#define TARGET_LONG_BITS 32
+
+#ifdef CONFIG_USER_ONLY
#define TARGET_PAGE_BITS 13
+#else
+#define TARGET_PAGE_BITS_VARY
+#define TARGET_PAGE_BITS_MIN 13
+#endif
+
#define TARGET_PHYS_ADDR_SPACE_BITS 32
#define TARGET_VIRT_ADDR_SPACE_BITS 32
diff --git a/target/hppa/cpu-param.h b/target/hppa/cpu-param.h
index c2791ae5f2..781dbc17d3 100644
--- a/target/hppa/cpu-param.h
+++ b/target/hppa/cpu-param.h
@@ -28,6 +28,12 @@
# define TARGET_VIRT_ADDR_SPACE_BITS 64
# define TARGET_PHYS_ADDR_SPACE_BITS 32
#endif
+
+#ifdef CONFIG_USER_ONLY
#define TARGET_PAGE_BITS 12
+#else
+#define TARGET_PAGE_BITS_VARY
+#define TARGET_PAGE_BITS_MIN 12
+#endif
#endif
diff --git a/target/i386/cpu-param.h b/target/i386/cpu-param.h
index 911b4cd51b..d09d0eb2ed 100644
--- a/target/i386/cpu-param.h
+++ b/target/i386/cpu-param.h
@@ -22,6 +22,12 @@
# define TARGET_PHYS_ADDR_SPACE_BITS 36
# define TARGET_VIRT_ADDR_SPACE_BITS 32
#endif
+
+#ifdef CONFIG_USER_ONLY
#define TARGET_PAGE_BITS 12
+#else
+#define TARGET_PAGE_BITS_VARY
+#define TARGET_PAGE_BITS_MIN 12
+#endif
#endif
diff --git a/target/loongarch/cpu-param.h b/target/loongarch/cpu-param.h
index 1265dc7cb5..f537c53ec4 100644
--- a/target/loongarch/cpu-param.h
+++ b/target/loongarch/cpu-param.h
@@ -12,6 +12,11 @@
#define TARGET_PHYS_ADDR_SPACE_BITS 48
#define TARGET_VIRT_ADDR_SPACE_BITS 48
+#ifdef CONFIG_USER_ONLY
#define TARGET_PAGE_BITS 14
+#else
+#define TARGET_PAGE_BITS_VARY
+#define TARGET_PAGE_BITS_MIN 14
+#endif
#endif
diff --git a/target/m68k/cpu-param.h b/target/m68k/cpu-param.h
index 39dcbcece8..92706969c7 100644
--- a/target/m68k/cpu-param.h
+++ b/target/m68k/cpu-param.h
@@ -14,7 +14,13 @@
* and m68k linux uses 4k pages
* use the smallest one
*/
+#ifdef CONFIG_USER_ONLY
#define TARGET_PAGE_BITS 12
+#else
+#define TARGET_PAGE_BITS_VARY
+#define TARGET_PAGE_BITS_MIN 12
+#endif
+
#define TARGET_PHYS_ADDR_SPACE_BITS 32
#define TARGET_VIRT_ADDR_SPACE_BITS 32
diff --git a/target/microblaze/cpu-param.h b/target/microblaze/cpu-param.h
index 9770b0eb52..51987d330d 100644
--- a/target/microblaze/cpu-param.h
+++ b/target/microblaze/cpu-param.h
@@ -20,13 +20,15 @@
#define TARGET_LONG_BITS 32
#define TARGET_PHYS_ADDR_SPACE_BITS 32
#define TARGET_VIRT_ADDR_SPACE_BITS 32
+/* FIXME: MB uses variable pages down to 1K but linux only uses 4k. */
+#define TARGET_PAGE_BITS 12
#else
#define TARGET_LONG_BITS 64
#define TARGET_PHYS_ADDR_SPACE_BITS 64
#define TARGET_VIRT_ADDR_SPACE_BITS 64
+#define TARGET_PAGE_BITS_VARY
+#define TARGET_PAGE_BITS_MIN 12
#endif
-/* FIXME: MB uses variable pages down to 1K but linux only uses 4k. */
-#define TARGET_PAGE_BITS 12
#endif
diff --git a/target/nios2/cpu-param.h b/target/nios2/cpu-param.h
index 767bba4b7b..40af6aef68 100644
--- a/target/nios2/cpu-param.h
+++ b/target/nios2/cpu-param.h
@@ -9,12 +9,15 @@
#define NIOS2_CPU_PARAM_H
#define TARGET_LONG_BITS 32
-#define TARGET_PAGE_BITS 12
+
#define TARGET_PHYS_ADDR_SPACE_BITS 32
#ifdef CONFIG_USER_ONLY
# define TARGET_VIRT_ADDR_SPACE_BITS 31
+# define TARGET_PAGE_BITS 12
#else
# define TARGET_VIRT_ADDR_SPACE_BITS 32
+# define TARGET_PAGE_BITS_VARY
+# define TARGET_PAGE_BITS_MIN 12
#endif
#endif
diff --git a/target/openrisc/cpu-param.h b/target/openrisc/cpu-param.h
index 3f08207485..10c52edf76 100644
--- a/target/openrisc/cpu-param.h
+++ b/target/openrisc/cpu-param.h
@@ -9,8 +9,14 @@
#define OPENRISC_CPU_PARAM_H
#define TARGET_LONG_BITS 32
-#define TARGET_PAGE_BITS 13
#define TARGET_PHYS_ADDR_SPACE_BITS 32
#define TARGET_VIRT_ADDR_SPACE_BITS 32
+#ifdef CONFIG_USER_ONLY
+#define TARGET_PAGE_BITS 13
+#else
+#define TARGET_PAGE_BITS_VARY
+#define TARGET_PAGE_BITS_MIN 13
+#endif
+
#endif
diff --git a/target/ppc/cpu-param.h b/target/ppc/cpu-param.h
index 0a0416e0a8..597dd39a6b 100644
--- a/target/ppc/cpu-param.h
+++ b/target/ppc/cpu-param.h
@@ -31,6 +31,12 @@
# define TARGET_PHYS_ADDR_SPACE_BITS 36
# define TARGET_VIRT_ADDR_SPACE_BITS 32
#endif
+
+#ifdef CONFIG_USER_ONLY
#define TARGET_PAGE_BITS 12
+#else
+#define TARGET_PAGE_BITS_VARY
+#define TARGET_PAGE_BITS_MIN 12
+#endif
#endif
diff --git a/target/riscv/cpu-param.h b/target/riscv/cpu-param.h
index b2a9396dec..80ba169e2b 100644
--- a/target/riscv/cpu-param.h
+++ b/target/riscv/cpu-param.h
@@ -17,7 +17,14 @@
# define TARGET_PHYS_ADDR_SPACE_BITS 34 /* 22-bit PPN */
# define TARGET_VIRT_ADDR_SPACE_BITS 32 /* sv32 */
#endif
+
+#ifdef CONFIG_USER_ONLY
#define TARGET_PAGE_BITS 12 /* 4 KiB Pages */
+#else
+#define TARGET_PAGE_BITS_VARY
+#define TARGET_PAGE_BITS_MIN 12 /* 4 KiB Pages */
+#endif
+
/*
* The current MMU Modes are:
* - U mode 0b000
diff --git a/target/rx/cpu-param.h b/target/rx/cpu-param.h
index 521d669bdf..f05a28456a 100644
--- a/target/rx/cpu-param.h
+++ b/target/rx/cpu-param.h
@@ -20,9 +20,15 @@
#define RX_CPU_PARAM_H
#define TARGET_LONG_BITS 32
-#define TARGET_PAGE_BITS 12
#define TARGET_PHYS_ADDR_SPACE_BITS 32
#define TARGET_VIRT_ADDR_SPACE_BITS 32
+#ifdef CONFIG_USER_ONLY
+#define TARGET_PAGE_BITS 12
+#else
+#define TARGET_PAGE_BITS_VARY
+#define TARGET_PAGE_BITS_MIN 12
+#endif
+
#endif
diff --git a/target/s390x/cpu-param.h b/target/s390x/cpu-param.h
index 84ca08626b..23d4345812 100644
--- a/target/s390x/cpu-param.h
+++ b/target/s390x/cpu-param.h
@@ -9,8 +9,14 @@
#define S390_CPU_PARAM_H
#define TARGET_LONG_BITS 64
-#define TARGET_PAGE_BITS 12
#define TARGET_PHYS_ADDR_SPACE_BITS 64
#define TARGET_VIRT_ADDR_SPACE_BITS 64
+#ifdef CONFIG_USER_ONLY
+#define TARGET_PAGE_BITS 12
+#else
+#define TARGET_PAGE_BITS_VARY
+#define TARGET_PAGE_BITS_MIN 12
+#endif
+
#endif
diff --git a/target/sh4/cpu-param.h b/target/sh4/cpu-param.h
index a7cdb7edb6..03354f1342 100644
--- a/target/sh4/cpu-param.h
+++ b/target/sh4/cpu-param.h
@@ -9,12 +9,14 @@
#define SH4_CPU_PARAM_H
#define TARGET_LONG_BITS 32
-#define TARGET_PAGE_BITS 12 /* 4k */
#define TARGET_PHYS_ADDR_SPACE_BITS 32
#ifdef CONFIG_USER_ONLY
# define TARGET_VIRT_ADDR_SPACE_BITS 31
+# define TARGET_PAGE_BITS 12 /* 4k */
#else
# define TARGET_VIRT_ADDR_SPACE_BITS 32
+# define TARGET_PAGE_BITS_VARY
+# define TARGET_PAGE_BITS_MIN 12 /* 4k */
#endif
#endif
diff --git a/target/sparc/cpu-param.h b/target/sparc/cpu-param.h
index cb11980404..19b53ebea6 100644
--- a/target/sparc/cpu-param.h
+++ b/target/sparc/cpu-param.h
@@ -9,7 +9,6 @@
#ifdef TARGET_SPARC64
# define TARGET_LONG_BITS 64
-# define TARGET_PAGE_BITS 13 /* 8k */
# define TARGET_PHYS_ADDR_SPACE_BITS 41
# ifdef TARGET_ABI32
# define TARGET_VIRT_ADDR_SPACE_BITS 32
@@ -18,9 +17,23 @@
# endif
#else
# define TARGET_LONG_BITS 32
-# define TARGET_PAGE_BITS 12 /* 4k */
# define TARGET_PHYS_ADDR_SPACE_BITS 36
# define TARGET_VIRT_ADDR_SPACE_BITS 32
#endif
+#ifdef CONFIG_USER_ONLY
+# ifdef TARGET_SPARC64
+# define TARGET_PAGE_BITS 13 /* 8k */
+# else
+# define TARGET_PAGE_BITS 12 /* 4k */
+# endif
+#else
+# define TARGET_PAGE_BITS_VARY
+# ifdef TARGET_SPARC64
+# define TARGET_PAGE_BITS_MIN 13 /* 8k */
+# else
+# define TARGET_PAGE_BITS_MIN 12 /* 4k */
+# endif
+#endif
+
#endif
diff --git a/target/tricore/cpu-param.h b/target/tricore/cpu-param.h
index e29d551dd6..6eff65ac54 100644
--- a/target/tricore/cpu-param.h
+++ b/target/tricore/cpu-param.h
@@ -9,8 +9,14 @@
#define TRICORE_CPU_PARAM_H
#define TARGET_LONG_BITS 32
-#define TARGET_PAGE_BITS 14
#define TARGET_PHYS_ADDR_SPACE_BITS 32
#define TARGET_VIRT_ADDR_SPACE_BITS 32
+#ifdef CONFIG_USER_ONLY
+# define TARGET_PAGE_BITS 14
+#else
+# define TARGET_PAGE_BITS_VARY
+# define TARGET_PAGE_BITS_MIN 14
+#endif
+
#endif
diff --git a/target/xtensa/cpu-param.h b/target/xtensa/cpu-param.h
index b1da0555de..1c18855626 100644
--- a/target/xtensa/cpu-param.h
+++ b/target/xtensa/cpu-param.h
@@ -9,12 +9,14 @@
#define XTENSA_CPU_PARAM_H
#define TARGET_LONG_BITS 32
-#define TARGET_PAGE_BITS 12
#define TARGET_PHYS_ADDR_SPACE_BITS 32
#ifdef CONFIG_USER_ONLY
-#define TARGET_VIRT_ADDR_SPACE_BITS 30
+# define TARGET_VIRT_ADDR_SPACE_BITS 30
+# define TARGET_PAGE_BITS 12
#else
-#define TARGET_VIRT_ADDR_SPACE_BITS 32
+# define TARGET_VIRT_ADDR_SPACE_BITS 32
+# define TARGET_PAGE_BITS_VARY
+# define TARGET_PAGE_BITS_MIN 12
#endif
#endif
--
2.43.0
^ permalink raw reply related [flat|nested] 83+ messages in thread
* [RFC PATCH 02/34] target: [PAGE_VARY] Move TARGET_PAGE_BITS_MIN to TargetPageBits
2024-01-19 14:39 [RFC PATCH 00/34] Compile accel/tcg once (partially) Anton Johansson via
2024-01-19 14:39 ` [RFC PATCH 01/34] target: [PAGE_VARY] Use PAGE_VARY for all softmmu targets Anton Johansson via
@ 2024-01-19 14:39 ` Anton Johansson via
2024-01-23 16:33 ` Richard Henderson
2024-01-19 14:39 ` [RFC PATCH 03/34] exec: [PAGE_VARY] Move TARGET_PAGE_BITS_VARY to common header Anton Johansson via
` (31 subsequent siblings)
33 siblings, 1 reply; 83+ messages in thread
From: Anton Johansson via @ 2024-01-19 14:39 UTC (permalink / raw)
To: qemu-devel; +Cc: ale, richard.henderson, philmd
TARGET_PAGE_BITS_MIN is now defined as target_page.bits_min when
PAGE_VARY is used, similar to other TARGET_PAGE_* macros. We still pick
whatever minimum the target specifies, however in a heterogeneous
context we would want the maximum of all target_page.bits_min.
This also makes TLB_* macros target independent, and the static assert
checking for TLB_* flag overlap is moved to a runtime assert in
tlb_init().
[NOTE: I'm not happy with adding the TARGET_PAGE_BITS_MIN_SPECIFIC
macro, maybe we can remove it and use MachineClass->minimum_page_bits
instead? Other ideas?]
Signed-off-by: Anton Johansson <anjo@rev.ng>
---
include/exec/cpu-all.h | 10 +++++-----
include/exec/cpu-defs.h | 4 ++--
include/exec/page-vary.h | 1 +
target/alpha/cpu-param.h | 2 +-
target/arm/cpu-param.h | 2 +-
target/avr/cpu-param.h | 2 +-
target/cris/cpu-param.h | 2 +-
target/hppa/cpu-param.h | 2 +-
target/i386/cpu-param.h | 2 +-
target/loongarch/cpu-param.h | 2 +-
target/m68k/cpu-param.h | 2 +-
target/microblaze/cpu-param.h | 2 +-
target/mips/cpu-param.h | 2 +-
target/nios2/cpu-param.h | 2 +-
target/openrisc/cpu-param.h | 2 +-
target/ppc/cpu-param.h | 2 +-
target/riscv/cpu-param.h | 2 +-
target/rx/cpu-param.h | 2 +-
target/s390x/cpu-param.h | 2 +-
target/sh4/cpu-param.h | 2 +-
target/sparc/cpu-param.h | 4 ++--
target/tricore/cpu-param.h | 2 +-
target/xtensa/cpu-param.h | 2 +-
accel/tcg/cputlb.c | 3 +++
page-vary-common.c | 1 +
page-vary-target.c | 4 ++--
target/arm/tcg/translate.c | 4 ++--
27 files changed, 37 insertions(+), 32 deletions(-)
diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h
index 5340907cfd..a1e4dee6a2 100644
--- a/include/exec/cpu-all.h
+++ b/include/exec/cpu-all.h
@@ -155,12 +155,15 @@ static inline void stl_phys_notdirty(AddressSpace *as, hwaddr addr, uint32_t val
# include "exec/page-vary.h"
extern const TargetPageBits target_page;
#ifdef CONFIG_DEBUG_TCG
+#define TARGET_PAGE_BITS_MIN ({ assert(target_page.decided); \
+ target_page.bits_min; })
#define TARGET_PAGE_BITS ({ assert(target_page.decided); target_page.bits; })
#define TARGET_PAGE_MASK ({ assert(target_page.decided); \
(target_long)target_page.mask; })
#else
-#define TARGET_PAGE_BITS target_page.bits
-#define TARGET_PAGE_MASK ((target_long)target_page.mask)
+#define TARGET_PAGE_BITS_MIN target_page.bits_min
+#define TARGET_PAGE_BITS target_page.bits
+#define TARGET_PAGE_MASK ((target_long)target_page.mask)
#endif
#define TARGET_PAGE_SIZE (-(int)TARGET_PAGE_MASK)
#else
@@ -380,9 +383,6 @@ CPUArchState *cpu_copy(CPUArchState *env);
#define TLB_SLOW_FLAGS_MASK (TLB_BSWAP | TLB_WATCHPOINT)
-/* The two sets of flags must not overlap. */
-QEMU_BUILD_BUG_ON(TLB_FLAGS_MASK & TLB_SLOW_FLAGS_MASK);
-
/**
* tlb_hit_page: return true if page aligned @addr is a hit against the
* TLB entry @tlb_addr
diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h
index 3915438b83..e8ccbe4bef 100644
--- a/include/exec/cpu-defs.h
+++ b/include/exec/cpu-defs.h
@@ -44,8 +44,8 @@
#endif
#ifndef TARGET_PAGE_BITS
# ifdef TARGET_PAGE_BITS_VARY
-# ifndef TARGET_PAGE_BITS_MIN
-# error TARGET_PAGE_BITS_MIN must be defined in cpu-param.h
+# ifndef TARGET_PAGE_BITS_MIN_SPECIFIC
+# error TARGET_PAGE_BITS_MIN_SPECIFIC must be defined in cpu-param.h
# endif
# else
# error TARGET_PAGE_BITS must be defined in cpu-param.h
diff --git a/include/exec/page-vary.h b/include/exec/page-vary.h
index 54ddde308a..add1282a7c 100644
--- a/include/exec/page-vary.h
+++ b/include/exec/page-vary.h
@@ -22,6 +22,7 @@
typedef struct {
bool decided;
+ int bits_min;
int bits;
uint64_t mask;
} TargetPageBits;
diff --git a/target/alpha/cpu-param.h b/target/alpha/cpu-param.h
index dc9da45bdf..7001b130d6 100644
--- a/target/alpha/cpu-param.h
+++ b/target/alpha/cpu-param.h
@@ -14,7 +14,7 @@
#define TARGET_PAGE_BITS 13
#else
#define TARGET_PAGE_BITS_VARY
-#define TARGET_PAGE_BITS_MIN 13
+#define TARGET_PAGE_BITS_MIN_SPECIFIC 13
#endif
/* ??? EV4 has 34 phys addr bits, EV5 has 40, EV6 has 44. */
diff --git a/target/arm/cpu-param.h b/target/arm/cpu-param.h
index f9b462a98f..442feb5380 100644
--- a/target/arm/cpu-param.h
+++ b/target/arm/cpu-param.h
@@ -29,7 +29,7 @@
* have to support 1K tiny pages.
*/
# define TARGET_PAGE_BITS_VARY
-# define TARGET_PAGE_BITS_MIN 10
+# define TARGET_PAGE_BITS_MIN_SPECIFIC 10
#endif
diff --git a/target/avr/cpu-param.h b/target/avr/cpu-param.h
index 87142069fe..e9b011a50d 100644
--- a/target/avr/cpu-param.h
+++ b/target/avr/cpu-param.h
@@ -32,7 +32,7 @@
#define TARGET_PAGE_BITS 8
#else
#define TARGET_PAGE_BITS_VARY
-#define TARGET_PAGE_BITS_MIN 8
+#define TARGET_PAGE_BITS_MIN_SPECIFIC 8
#endif
#define TARGET_PHYS_ADDR_SPACE_BITS 24
diff --git a/target/cris/cpu-param.h b/target/cris/cpu-param.h
index 9c66ca9e66..2c939a2beb 100644
--- a/target/cris/cpu-param.h
+++ b/target/cris/cpu-param.h
@@ -14,7 +14,7 @@
#define TARGET_PAGE_BITS 13
#else
#define TARGET_PAGE_BITS_VARY
-#define TARGET_PAGE_BITS_MIN 13
+#define TARGET_PAGE_BITS_MIN_SPECIFIC 13
#endif
#define TARGET_PHYS_ADDR_SPACE_BITS 32
diff --git a/target/hppa/cpu-param.h b/target/hppa/cpu-param.h
index 781dbc17d3..5e413b7b76 100644
--- a/target/hppa/cpu-param.h
+++ b/target/hppa/cpu-param.h
@@ -33,7 +33,7 @@
#define TARGET_PAGE_BITS 12
#else
#define TARGET_PAGE_BITS_VARY
-#define TARGET_PAGE_BITS_MIN 12
+#define TARGET_PAGE_BITS_MIN_SPECIFIC 12
#endif
#endif
diff --git a/target/i386/cpu-param.h b/target/i386/cpu-param.h
index d09d0eb2ed..a497e842d8 100644
--- a/target/i386/cpu-param.h
+++ b/target/i386/cpu-param.h
@@ -27,7 +27,7 @@
#define TARGET_PAGE_BITS 12
#else
#define TARGET_PAGE_BITS_VARY
-#define TARGET_PAGE_BITS_MIN 12
+#define TARGET_PAGE_BITS_MIN_SPECIFIC 12
#endif
#endif
diff --git a/target/loongarch/cpu-param.h b/target/loongarch/cpu-param.h
index f537c53ec4..a447a03a76 100644
--- a/target/loongarch/cpu-param.h
+++ b/target/loongarch/cpu-param.h
@@ -16,7 +16,7 @@
#define TARGET_PAGE_BITS 14
#else
#define TARGET_PAGE_BITS_VARY
-#define TARGET_PAGE_BITS_MIN 14
+#define TARGET_PAGE_BITS_MIN_SPECIFIC 14
#endif
#endif
diff --git a/target/m68k/cpu-param.h b/target/m68k/cpu-param.h
index 92706969c7..650a1f94c7 100644
--- a/target/m68k/cpu-param.h
+++ b/target/m68k/cpu-param.h
@@ -18,7 +18,7 @@
#define TARGET_PAGE_BITS 12
#else
#define TARGET_PAGE_BITS_VARY
-#define TARGET_PAGE_BITS_MIN 12
+#define TARGET_PAGE_BITS_MIN_SPECIFIC 12
#endif
#define TARGET_PHYS_ADDR_SPACE_BITS 32
diff --git a/target/microblaze/cpu-param.h b/target/microblaze/cpu-param.h
index 51987d330d..4bfd825999 100644
--- a/target/microblaze/cpu-param.h
+++ b/target/microblaze/cpu-param.h
@@ -27,7 +27,7 @@
#define TARGET_PHYS_ADDR_SPACE_BITS 64
#define TARGET_VIRT_ADDR_SPACE_BITS 64
#define TARGET_PAGE_BITS_VARY
-#define TARGET_PAGE_BITS_MIN 12
+#define TARGET_PAGE_BITS_MIN_SPECIFIC 12
#endif
diff --git a/target/mips/cpu-param.h b/target/mips/cpu-param.h
index 594c91a156..1f4fb03b66 100644
--- a/target/mips/cpu-param.h
+++ b/target/mips/cpu-param.h
@@ -27,7 +27,7 @@
#define TARGET_PAGE_BITS 12
#else
#define TARGET_PAGE_BITS_VARY
-#define TARGET_PAGE_BITS_MIN 12
+#define TARGET_PAGE_BITS_MIN_SPECIFIC 12
#endif
#endif
diff --git a/target/nios2/cpu-param.h b/target/nios2/cpu-param.h
index 40af6aef68..759c89abea 100644
--- a/target/nios2/cpu-param.h
+++ b/target/nios2/cpu-param.h
@@ -17,7 +17,7 @@
#else
# define TARGET_VIRT_ADDR_SPACE_BITS 32
# define TARGET_PAGE_BITS_VARY
-# define TARGET_PAGE_BITS_MIN 12
+# define TARGET_PAGE_BITS_MIN_SPECIFIC 12
#endif
#endif
diff --git a/target/openrisc/cpu-param.h b/target/openrisc/cpu-param.h
index 10c52edf76..b20dbd7c8b 100644
--- a/target/openrisc/cpu-param.h
+++ b/target/openrisc/cpu-param.h
@@ -16,7 +16,7 @@
#define TARGET_PAGE_BITS 13
#else
#define TARGET_PAGE_BITS_VARY
-#define TARGET_PAGE_BITS_MIN 13
+#define TARGET_PAGE_BITS_MIN_SPECIFIC 13
#endif
#endif
diff --git a/target/ppc/cpu-param.h b/target/ppc/cpu-param.h
index 597dd39a6b..c712131b5d 100644
--- a/target/ppc/cpu-param.h
+++ b/target/ppc/cpu-param.h
@@ -36,7 +36,7 @@
#define TARGET_PAGE_BITS 12
#else
#define TARGET_PAGE_BITS_VARY
-#define TARGET_PAGE_BITS_MIN 12
+#define TARGET_PAGE_BITS_MIN_SPECIFIC 12
#endif
#endif
diff --git a/target/riscv/cpu-param.h b/target/riscv/cpu-param.h
index 80ba169e2b..889d2b14fe 100644
--- a/target/riscv/cpu-param.h
+++ b/target/riscv/cpu-param.h
@@ -22,7 +22,7 @@
#define TARGET_PAGE_BITS 12 /* 4 KiB Pages */
#else
#define TARGET_PAGE_BITS_VARY
-#define TARGET_PAGE_BITS_MIN 12 /* 4 KiB Pages */
+#define TARGET_PAGE_BITS_MIN_SPECIFIC 12 /* 4 KiB Pages */
#endif
/*
diff --git a/target/rx/cpu-param.h b/target/rx/cpu-param.h
index f05a28456a..5b5fb658e6 100644
--- a/target/rx/cpu-param.h
+++ b/target/rx/cpu-param.h
@@ -28,7 +28,7 @@
#define TARGET_PAGE_BITS 12
#else
#define TARGET_PAGE_BITS_VARY
-#define TARGET_PAGE_BITS_MIN 12
+#define TARGET_PAGE_BITS_MIN_SPECIFIC 12
#endif
#endif
diff --git a/target/s390x/cpu-param.h b/target/s390x/cpu-param.h
index 23d4345812..b8a9cf96b4 100644
--- a/target/s390x/cpu-param.h
+++ b/target/s390x/cpu-param.h
@@ -16,7 +16,7 @@
#define TARGET_PAGE_BITS 12
#else
#define TARGET_PAGE_BITS_VARY
-#define TARGET_PAGE_BITS_MIN 12
+#define TARGET_PAGE_BITS_MIN_SPECIFIC 12
#endif
#endif
diff --git a/target/sh4/cpu-param.h b/target/sh4/cpu-param.h
index 03354f1342..42c747c333 100644
--- a/target/sh4/cpu-param.h
+++ b/target/sh4/cpu-param.h
@@ -16,7 +16,7 @@
#else
# define TARGET_VIRT_ADDR_SPACE_BITS 32
# define TARGET_PAGE_BITS_VARY
-# define TARGET_PAGE_BITS_MIN 12 /* 4k */
+# define TARGET_PAGE_BITS_MIN_SPECIFIC 12 /* 4k */
#endif
#endif
diff --git a/target/sparc/cpu-param.h b/target/sparc/cpu-param.h
index 19b53ebea6..538a8db77a 100644
--- a/target/sparc/cpu-param.h
+++ b/target/sparc/cpu-param.h
@@ -30,9 +30,9 @@
#else
# define TARGET_PAGE_BITS_VARY
# ifdef TARGET_SPARC64
-# define TARGET_PAGE_BITS_MIN 13 /* 8k */
+# define TARGET_PAGE_BITS_MIN_SPECIFIC 13 /* 8k */
# else
-# define TARGET_PAGE_BITS_MIN 12 /* 4k */
+# define TARGET_PAGE_BITS_MIN_SPECIFIC 12 /* 4k */
# endif
#endif
diff --git a/target/tricore/cpu-param.h b/target/tricore/cpu-param.h
index 6eff65ac54..bddfb57530 100644
--- a/target/tricore/cpu-param.h
+++ b/target/tricore/cpu-param.h
@@ -16,7 +16,7 @@
# define TARGET_PAGE_BITS 14
#else
# define TARGET_PAGE_BITS_VARY
-# define TARGET_PAGE_BITS_MIN 14
+# define TARGET_PAGE_BITS_MIN_SPECIFIC 14
#endif
#endif
diff --git a/target/xtensa/cpu-param.h b/target/xtensa/cpu-param.h
index 1c18855626..9689581e3b 100644
--- a/target/xtensa/cpu-param.h
+++ b/target/xtensa/cpu-param.h
@@ -16,7 +16,7 @@
#else
# define TARGET_VIRT_ADDR_SPACE_BITS 32
# define TARGET_PAGE_BITS_VARY
-# define TARGET_PAGE_BITS_MIN 12
+# define TARGET_PAGE_BITS_MIN_SPECIFIC 12
#endif
#endif
diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
index b8c5e345b8..449c86301e 100644
--- a/accel/tcg/cputlb.c
+++ b/accel/tcg/cputlb.c
@@ -278,6 +278,9 @@ void tlb_init(CPUState *cpu)
int64_t now = get_clock_realtime();
int i;
+ /* The two sets of flags must not overlap. */
+ assert((TLB_FLAGS_MASK & TLB_SLOW_FLAGS_MASK) == 0);
+
qemu_spin_init(&cpu->neg.tlb.c.lock);
/* All tlbs are initialized flushed. */
diff --git a/page-vary-common.c b/page-vary-common.c
index ab77672dd4..ecd4e30c94 100644
--- a/page-vary-common.c
+++ b/page-vary-common.c
@@ -48,6 +48,7 @@ void finalize_target_page_bits_common(int min)
if (target_page.bits == 0) {
target_page.bits = min;
}
+ target_page.bits_min = min;
target_page.mask = -1ull << target_page.bits;
target_page.decided = true;
}
diff --git a/page-vary-target.c b/page-vary-target.c
index 343b4adb95..87dae60d5e 100644
--- a/page-vary-target.c
+++ b/page-vary-target.c
@@ -26,7 +26,7 @@
bool set_preferred_target_page_bits(int bits)
{
#ifdef TARGET_PAGE_BITS_VARY
- assert(bits >= TARGET_PAGE_BITS_MIN);
+ assert(bits >= TARGET_PAGE_BITS_MIN_SPECIFIC);
return set_preferred_target_page_bits_common(bits);
#else
return true;
@@ -36,6 +36,6 @@ bool set_preferred_target_page_bits(int bits)
void finalize_target_page_bits(void)
{
#ifdef TARGET_PAGE_BITS_VARY
- finalize_target_page_bits_common(TARGET_PAGE_BITS_MIN);
+ finalize_target_page_bits_common(TARGET_PAGE_BITS_MIN_SPECIFIC);
#endif
}
diff --git a/target/arm/tcg/translate.c b/target/arm/tcg/translate.c
index 48927fbb8c..bdcb8a6555 100644
--- a/target/arm/tcg/translate.c
+++ b/target/arm/tcg/translate.c
@@ -902,8 +902,8 @@ MemOp pow2_align(unsigned i)
static const MemOp mop_align[] = {
0, MO_ALIGN_2, MO_ALIGN_4, MO_ALIGN_8, MO_ALIGN_16,
/*
- * FIXME: TARGET_PAGE_BITS_MIN affects TLB_FLAGS_MASK such
- * that 256-bit alignment (MO_ALIGN_32) cannot be supported:
+ * FIXME: TARGET_PAGE_BITS_MIN_SPECIFIC affects TLB_FLAGS_MASK
+ * such that 256-bit alignment (MO_ALIGN_32) cannot be supported:
* see get_alignment_bits(). Enforce only 128-bit alignment for now.
*/
MO_ALIGN_16
--
2.43.0
^ permalink raw reply related [flat|nested] 83+ messages in thread
* [RFC PATCH 03/34] exec: [PAGE_VARY] Move TARGET_PAGE_BITS_VARY to common header
2024-01-19 14:39 [RFC PATCH 00/34] Compile accel/tcg once (partially) Anton Johansson via
2024-01-19 14:39 ` [RFC PATCH 01/34] target: [PAGE_VARY] Use PAGE_VARY for all softmmu targets Anton Johansson via
2024-01-19 14:39 ` [RFC PATCH 02/34] target: [PAGE_VARY] Move TARGET_PAGE_BITS_MIN to TargetPageBits Anton Johansson via
@ 2024-01-19 14:39 ` Anton Johansson via
2024-01-23 22:20 ` Richard Henderson
2024-01-19 14:39 ` [RFC PATCH 04/34] exec: [PAGE_VARY] Unpoison TARGET_PAGE_* macros for system mode Anton Johansson via
` (30 subsequent siblings)
33 siblings, 1 reply; 83+ messages in thread
From: Anton Johansson via @ 2024-01-19 14:39 UTC (permalink / raw)
To: qemu-devel; +Cc: ale, richard.henderson, philmd
We need to be able access the variable TARGET_PAGE_* macros in a
target-independent manner.
Signed-off-by: Anton Johansson <anjo@rev.ng>
---
include/exec/cpu-all.h | 29 ++++++++++-------------------
include/exec/cpu-common.h | 25 +++++++++++++++++++++++++
2 files changed, 35 insertions(+), 19 deletions(-)
diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h
index a1e4dee6a2..83165b1ce4 100644
--- a/include/exec/cpu-all.h
+++ b/include/exec/cpu-all.h
@@ -149,30 +149,21 @@ static inline void stl_phys_notdirty(AddressSpace *as, hwaddr addr, uint32_t val
#include "exec/memory_ldst_phys.h.inc"
#endif
-/* page related stuff */
-
-#ifdef TARGET_PAGE_BITS_VARY
-# include "exec/page-vary.h"
-extern const TargetPageBits target_page;
-#ifdef CONFIG_DEBUG_TCG
-#define TARGET_PAGE_BITS_MIN ({ assert(target_page.decided); \
- target_page.bits_min; })
-#define TARGET_PAGE_BITS ({ assert(target_page.decided); target_page.bits; })
-#define TARGET_PAGE_MASK ({ assert(target_page.decided); \
- (target_long)target_page.mask; })
-#else
-#define TARGET_PAGE_BITS_MIN target_page.bits_min
-#define TARGET_PAGE_BITS target_page.bits
-#define TARGET_PAGE_MASK ((target_long)target_page.mask)
-#endif
-#define TARGET_PAGE_SIZE (-(int)TARGET_PAGE_MASK)
-#else
+/* Non-variable page size macros */
+#ifndef TARGET_PAGE_BITS_VARY
#define TARGET_PAGE_BITS_MIN TARGET_PAGE_BITS
#define TARGET_PAGE_SIZE (1 << TARGET_PAGE_BITS)
#define TARGET_PAGE_MASK ((target_long)-1 << TARGET_PAGE_BITS)
+#define TARGET_PAGE_ALIGN(addr) ROUND_UP((addr), TARGET_PAGE_SIZE)
#endif
-#define TARGET_PAGE_ALIGN(addr) ROUND_UP((addr), TARGET_PAGE_SIZE)
+/*
+ * Check that softmmu targets are using variable page sizes, we need this
+ * for the TARGET_PAGE_* macros to be target independent.
+ */
+#if !defined(CONFIG_USER_ONLY) && !defined(TARGET_PAGE_BITS_VARY)
+# error Need to use TARGET_PAGE_BITS_VARY on system mode
+#endif
/* same as PROT_xxx */
#define PAGE_READ 0x0001
diff --git a/include/exec/cpu-common.h b/include/exec/cpu-common.h
index 605b160a7e..df53252d51 100644
--- a/include/exec/cpu-common.h
+++ b/include/exec/cpu-common.h
@@ -26,6 +26,31 @@ typedef uint64_t vaddr;
#define VADDR_PRIX PRIX64
#define VADDR_MAX UINT64_MAX
+/**
+ * Variable page size macros
+ *
+ * TARGET_PAGE_BITS_VARY is assumed for softmmu targets so
+ * these macros are target independent. This is checked in
+ * cpu-all.h.
+ */
+#ifndef CONFIG_USER_ONLY
+# include "exec/page-vary.h"
+extern const TargetPageBits target_page;
+#ifdef CONFIG_DEBUG_TCG
+#define TARGET_PAGE_BITS_MIN ({ assert(target_page.decided); \
+ target_page.bits_min; })
+#define TARGET_PAGE_BITS ({ assert(target_page.decided); target_page.bits; })
+#define TARGET_PAGE_MASK ({ assert(target_page.decided); \
+ (int)target_page.mask; })
+#else
+#define TARGET_PAGE_BITS_MIN target_page.bits_min
+#define TARGET_PAGE_BITS target_page.bits
+#define TARGET_PAGE_MASK ((int)target_page.mask)
+#endif
+#define TARGET_PAGE_SIZE (-(int)TARGET_PAGE_MASK)
+#define TARGET_PAGE_ALIGN(addr) ROUND_UP((addr), TARGET_PAGE_SIZE)
+#endif
+
void cpu_exec_init_all(void);
void cpu_exec_step_atomic(CPUState *cpu);
--
2.43.0
^ permalink raw reply related [flat|nested] 83+ messages in thread
* [RFC PATCH 04/34] exec: [PAGE_VARY] Unpoison TARGET_PAGE_* macros for system mode
2024-01-19 14:39 [RFC PATCH 00/34] Compile accel/tcg once (partially) Anton Johansson via
` (2 preceding siblings ...)
2024-01-19 14:39 ` [RFC PATCH 03/34] exec: [PAGE_VARY] Move TARGET_PAGE_BITS_VARY to common header Anton Johansson via
@ 2024-01-19 14:39 ` Anton Johansson via
2024-01-23 22:20 ` Richard Henderson
2024-01-19 14:39 ` [RFC PATCH 05/34] target/tricore: [VADDR] Use target_ulong for EA Anton Johansson via
` (29 subsequent siblings)
33 siblings, 1 reply; 83+ messages in thread
From: Anton Johansson via @ 2024-01-19 14:39 UTC (permalink / raw)
To: qemu-devel; +Cc: ale, richard.henderson, philmd
TARGET_PAGE_* are now target-independent for softmmu targets, and can
safely be accessed common code.
Signed-off-by: Anton Johansson <anjo@rev.ng>
---
include/exec/poison.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/include/exec/poison.h b/include/exec/poison.h
index 1ea5633eb3..6d87954a91 100644
--- a/include/exec/poison.h
+++ b/include/exec/poison.h
@@ -46,10 +46,12 @@
#pragma GCC poison TARGET_FMT_ld
#pragma GCC poison TARGET_FMT_lu
+#ifdef CONFIG_USER_ONLY
#pragma GCC poison TARGET_PAGE_SIZE
#pragma GCC poison TARGET_PAGE_MASK
#pragma GCC poison TARGET_PAGE_BITS
#pragma GCC poison TARGET_PAGE_ALIGN
+#endif
#pragma GCC poison CPU_INTERRUPT_HARD
#pragma GCC poison CPU_INTERRUPT_EXITTB
--
2.43.0
^ permalink raw reply related [flat|nested] 83+ messages in thread
* [RFC PATCH 05/34] target/tricore: [VADDR] Use target_ulong for EA
2024-01-19 14:39 [RFC PATCH 00/34] Compile accel/tcg once (partially) Anton Johansson via
` (3 preceding siblings ...)
2024-01-19 14:39 ` [RFC PATCH 04/34] exec: [PAGE_VARY] Unpoison TARGET_PAGE_* macros for system mode Anton Johansson via
@ 2024-01-19 14:39 ` Anton Johansson via
2024-01-23 22:29 ` Richard Henderson
2024-01-27 8:26 ` Richard Henderson
2024-01-19 14:39 ` [RFC PATCH 06/34] exec: [VADDR] Move vaddr defines to separate file Anton Johansson via
` (28 subsequent siblings)
33 siblings, 2 replies; 83+ messages in thread
From: Anton Johansson via @ 2024-01-19 14:39 UTC (permalink / raw)
To: qemu-devel; +Cc: ale, richard.henderson, philmd
Prepares target for typedef'ing abi_ptr to vaddr. Fixes sign extension
bug that would result from abi_ptr being unsigned in the future.
Necessary to make memory access function signatures target agnostic.
Signed-off-by: Anton Johansson <anjo@rev.ng>
---
target/tricore/op_helper.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/target/tricore/op_helper.c b/target/tricore/op_helper.c
index 89be1ed648..f57bb39d1f 100644
--- a/target/tricore/op_helper.c
+++ b/target/tricore/op_helper.c
@@ -2395,7 +2395,7 @@ static bool cdc_zero(target_ulong *psw)
return count == 0;
}
-static void save_context_upper(CPUTriCoreState *env, int ea)
+static void save_context_upper(CPUTriCoreState *env, target_ulong ea)
{
cpu_stl_data(env, ea, env->PCXI);
cpu_stl_data(env, ea+4, psw_read(env));
@@ -2415,7 +2415,7 @@ static void save_context_upper(CPUTriCoreState *env, int ea)
cpu_stl_data(env, ea+60, env->gpr_d[15]);
}
-static void save_context_lower(CPUTriCoreState *env, int ea)
+static void save_context_lower(CPUTriCoreState *env, target_ulong ea)
{
cpu_stl_data(env, ea, env->PCXI);
cpu_stl_data(env, ea+4, env->gpr_a[11]);
@@ -2435,7 +2435,7 @@ static void save_context_lower(CPUTriCoreState *env, int ea)
cpu_stl_data(env, ea+60, env->gpr_d[7]);
}
-static void restore_context_upper(CPUTriCoreState *env, int ea,
+static void restore_context_upper(CPUTriCoreState *env, target_ulong ea,
target_ulong *new_PCXI, target_ulong *new_PSW)
{
*new_PCXI = cpu_ldl_data(env, ea);
@@ -2456,7 +2456,7 @@ static void restore_context_upper(CPUTriCoreState *env, int ea,
env->gpr_d[15] = cpu_ldl_data(env, ea+60);
}
-static void restore_context_lower(CPUTriCoreState *env, int ea,
+static void restore_context_lower(CPUTriCoreState *env, target_ulong ea,
target_ulong *ra, target_ulong *pcxi)
{
*pcxi = cpu_ldl_data(env, ea);
--
2.43.0
^ permalink raw reply related [flat|nested] 83+ messages in thread
* [RFC PATCH 06/34] exec: [VADDR] Move vaddr defines to separate file
2024-01-19 14:39 [RFC PATCH 00/34] Compile accel/tcg once (partially) Anton Johansson via
` (4 preceding siblings ...)
2024-01-19 14:39 ` [RFC PATCH 05/34] target/tricore: [VADDR] Use target_ulong for EA Anton Johansson via
@ 2024-01-19 14:39 ` Anton Johansson via
2024-01-23 22:33 ` Richard Henderson
2024-01-27 8:36 ` Richard Henderson
2024-01-19 14:39 ` [RFC PATCH 07/34] hw/core: [VADDR] Include vaddr.h from cpu.h Anton Johansson via
` (27 subsequent siblings)
33 siblings, 2 replies; 83+ messages in thread
From: Anton Johansson via @ 2024-01-19 14:39 UTC (permalink / raw)
To: qemu-devel; +Cc: ale, richard.henderson, philmd
Needed to work around circular includes. vaddr is currently defined in
cpu-common.h and needed by hw/core/cpu.h, but cpu-common.h also need
cpu.h to know the size of the CPUState.
[Maybe we can instead move parts of cpu-common.h w. hw/core/cpu.h to
sort out the circular inclusion.]
Signed-off-by: Anton Johansson <anjo@rev.ng>
---
include/exec/cpu-common.h | 12 ------------
include/exec/vaddr.h | 18 ++++++++++++++++++
2 files changed, 18 insertions(+), 12 deletions(-)
create mode 100644 include/exec/vaddr.h
diff --git a/include/exec/cpu-common.h b/include/exec/cpu-common.h
index df53252d51..c071f1a003 100644
--- a/include/exec/cpu-common.h
+++ b/include/exec/cpu-common.h
@@ -14,18 +14,6 @@
#define EXCP_YIELD 0x10004 /* cpu wants to yield timeslice to another */
#define EXCP_ATOMIC 0x10005 /* stop-the-world and emulate atomic */
-/**
- * vaddr:
- * Type wide enough to contain any #target_ulong virtual address.
- */
-typedef uint64_t vaddr;
-#define VADDR_PRId PRId64
-#define VADDR_PRIu PRIu64
-#define VADDR_PRIo PRIo64
-#define VADDR_PRIx PRIx64
-#define VADDR_PRIX PRIX64
-#define VADDR_MAX UINT64_MAX
-
/**
* Variable page size macros
*
diff --git a/include/exec/vaddr.h b/include/exec/vaddr.h
new file mode 100644
index 0000000000..db48bb16bc
--- /dev/null
+++ b/include/exec/vaddr.h
@@ -0,0 +1,18 @@
+/* Define vaddr if it exists. */
+
+#ifndef VADDR_H
+#define VADDR_H
+
+/**
+ * vaddr:
+ * Type wide enough to contain any #target_ulong virtual address.
+ */
+typedef uint64_t vaddr;
+#define VADDR_PRId PRId64
+#define VADDR_PRIu PRIu64
+#define VADDR_PRIo PRIo64
+#define VADDR_PRIx PRIx64
+#define VADDR_PRIX PRIX64
+#define VADDR_MAX UINT64_MAX
+
+#endif
--
2.43.0
^ permalink raw reply related [flat|nested] 83+ messages in thread
* [RFC PATCH 07/34] hw/core: [VADDR] Include vaddr.h from cpu.h
2024-01-19 14:39 [RFC PATCH 00/34] Compile accel/tcg once (partially) Anton Johansson via
` (5 preceding siblings ...)
2024-01-19 14:39 ` [RFC PATCH 06/34] exec: [VADDR] Move vaddr defines to separate file Anton Johansson via
@ 2024-01-19 14:39 ` Anton Johansson via
2024-01-23 22:57 ` Richard Henderson
2024-01-27 8:48 ` Richard Henderson
2024-01-19 14:39 ` [RFC PATCH 08/34] target: [VADDR] Use vaddr in gen_intermediate_code Anton Johansson via
` (26 subsequent siblings)
33 siblings, 2 replies; 83+ messages in thread
From: Anton Johansson via @ 2024-01-19 14:39 UTC (permalink / raw)
To: qemu-devel; +Cc: ale, richard.henderson, philmd
cpu-common.h is only needed for vaddr
Signed-off-by: Anton Johansson <anjo@rev.ng>
---
include/hw/core/cpu.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index f25d53ee90..57d100c203 100644
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cpu.h
@@ -22,8 +22,8 @@
#include "hw/qdev-core.h"
#include "disas/dis-asm.h"
-#include "exec/cpu-common.h"
#include "exec/hwaddr.h"
+#include "exec/vaddr.h"
#include "exec/memattrs.h"
#include "exec/tlb-common.h"
#include "qapi/qapi-types-run-state.h"
--
2.43.0
^ permalink raw reply related [flat|nested] 83+ messages in thread
* [RFC PATCH 08/34] target: [VADDR] Use vaddr in gen_intermediate_code
2024-01-19 14:39 [RFC PATCH 00/34] Compile accel/tcg once (partially) Anton Johansson via
` (6 preceding siblings ...)
2024-01-19 14:39 ` [RFC PATCH 07/34] hw/core: [VADDR] Include vaddr.h from cpu.h Anton Johansson via
@ 2024-01-19 14:39 ` Anton Johansson via
2024-01-23 23:13 ` Richard Henderson
2024-01-27 9:05 ` Richard Henderson
2024-01-19 14:39 ` [RFC PATCH 09/34] exec: [VADDR] Use vaddr in DisasContextBase for virtual addresses Anton Johansson via
` (25 subsequent siblings)
33 siblings, 2 replies; 83+ messages in thread
From: Anton Johansson via @ 2024-01-19 14:39 UTC (permalink / raw)
To: qemu-devel; +Cc: ale, richard.henderson, philmd
Makes gen_intermediate_code() signature target agnostic so the function
can be called from accel/tcg/translate-all.c without target specifics.
Signed-off-by: Anton Johansson <anjo@rev.ng>
---
include/exec/translator.h | 2 +-
target/alpha/translate.c | 2 +-
target/arm/tcg/translate.c | 2 +-
target/avr/translate.c | 2 +-
target/cris/translate.c | 2 +-
target/hexagon/translate.c | 2 +-
target/hppa/translate.c | 2 +-
target/i386/tcg/translate.c | 2 +-
target/loongarch/translate.c | 2 +-
target/m68k/translate.c | 2 +-
target/microblaze/translate.c | 2 +-
target/mips/tcg/translate.c | 2 +-
target/nios2/translate.c | 2 +-
target/openrisc/translate.c | 2 +-
target/ppc/translate.c | 2 +-
target/riscv/translate.c | 2 +-
target/rx/translate.c | 2 +-
target/s390x/tcg/translate.c | 2 +-
target/sh4/translate.c | 2 +-
target/sparc/translate.c | 2 +-
target/tricore/translate.c | 2 +-
target/xtensa/translate.c | 2 +-
22 files changed, 22 insertions(+), 22 deletions(-)
diff --git a/include/exec/translator.h b/include/exec/translator.h
index 4e17c4f401..2ab8f58bea 100644
--- a/include/exec/translator.h
+++ b/include/exec/translator.h
@@ -33,7 +33,7 @@
* the target-specific DisasContext, and then invoke translator_loop.
*/
void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb, int *max_insns,
- target_ulong pc, void *host_pc);
+ vaddr pc, void *host_pc);
/**
* DisasJumpType:
diff --git a/target/alpha/translate.c b/target/alpha/translate.c
index 32333081d8..134eb7225b 100644
--- a/target/alpha/translate.c
+++ b/target/alpha/translate.c
@@ -2971,7 +2971,7 @@ static const TranslatorOps alpha_tr_ops = {
};
void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb, int *max_insns,
- target_ulong pc, void *host_pc)
+ vaddr pc, void *host_pc)
{
DisasContext dc;
translator_loop(cpu, tb, max_insns, pc, host_pc, &alpha_tr_ops, &dc.base);
diff --git a/target/arm/tcg/translate.c b/target/arm/tcg/translate.c
index bdcb8a6555..0877cb1ce5 100644
--- a/target/arm/tcg/translate.c
+++ b/target/arm/tcg/translate.c
@@ -9682,7 +9682,7 @@ static const TranslatorOps thumb_translator_ops = {
/* generate intermediate code for basic block 'tb'. */
void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb, int *max_insns,
- target_ulong pc, void *host_pc)
+ vaddr pc, void *host_pc)
{
DisasContext dc = { };
const TranslatorOps *ops = &arm_translator_ops;
diff --git a/target/avr/translate.c b/target/avr/translate.c
index cdffa04519..e5dd057799 100644
--- a/target/avr/translate.c
+++ b/target/avr/translate.c
@@ -2805,7 +2805,7 @@ static const TranslatorOps avr_tr_ops = {
};
void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns,
- target_ulong pc, void *host_pc)
+ vaddr pc, void *host_pc)
{
DisasContext dc = { };
translator_loop(cs, tb, max_insns, pc, host_pc, &avr_tr_ops, &dc.base);
diff --git a/target/cris/translate.c b/target/cris/translate.c
index b3974ba0bb..ee1402a9a3 100644
--- a/target/cris/translate.c
+++ b/target/cris/translate.c
@@ -3172,7 +3172,7 @@ static const TranslatorOps cris_tr_ops = {
};
void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns,
- target_ulong pc, void *host_pc)
+ vaddr pc, void *host_pc)
{
DisasContext dc;
translator_loop(cs, tb, max_insns, pc, host_pc, &cris_tr_ops, &dc.base);
diff --git a/target/hexagon/translate.c b/target/hexagon/translate.c
index 663b7bbc3a..2ef6a89622 100644
--- a/target/hexagon/translate.c
+++ b/target/hexagon/translate.c
@@ -1154,7 +1154,7 @@ static const TranslatorOps hexagon_tr_ops = {
};
void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns,
- target_ulong pc, void *host_pc)
+ vaddr pc, void *host_pc)
{
DisasContext ctx;
diff --git a/target/hppa/translate.c b/target/hppa/translate.c
index 902cd642ae..f22ec3aeb3 100644
--- a/target/hppa/translate.c
+++ b/target/hppa/translate.c
@@ -4273,7 +4273,7 @@ static const TranslatorOps hppa_tr_ops = {
};
void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns,
- target_ulong pc, void *host_pc)
+ vaddr pc, void *host_pc)
{
DisasContext ctx;
translator_loop(cs, tb, max_insns, pc, host_pc, &hppa_tr_ops, &ctx.base);
diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c
index c6894d66b1..c97d1e3da8 100644
--- a/target/i386/tcg/translate.c
+++ b/target/i386/tcg/translate.c
@@ -7084,7 +7084,7 @@ static const TranslatorOps i386_tr_ops = {
/* generate intermediate code for basic block 'tb'. */
void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb, int *max_insns,
- target_ulong pc, void *host_pc)
+ vaddr pc, void *host_pc)
{
DisasContext dc;
diff --git a/target/loongarch/translate.c b/target/loongarch/translate.c
index a75fed1d98..d80a9a3d86 100644
--- a/target/loongarch/translate.c
+++ b/target/loongarch/translate.c
@@ -326,7 +326,7 @@ static const TranslatorOps loongarch_tr_ops = {
};
void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns,
- target_ulong pc, void *host_pc)
+ vaddr pc, void *host_pc)
{
DisasContext ctx;
diff --git a/target/m68k/translate.c b/target/m68k/translate.c
index d22df2a8dc..3408385fa1 100644
--- a/target/m68k/translate.c
+++ b/target/m68k/translate.c
@@ -6105,7 +6105,7 @@ static const TranslatorOps m68k_tr_ops = {
};
void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb, int *max_insns,
- target_ulong pc, void *host_pc)
+ vaddr pc, void *host_pc)
{
DisasContext dc;
translator_loop(cpu, tb, max_insns, pc, host_pc, &m68k_tr_ops, &dc.base);
diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c
index 49bfb4a0ea..2e628647d1 100644
--- a/target/microblaze/translate.c
+++ b/target/microblaze/translate.c
@@ -1792,7 +1792,7 @@ static const TranslatorOps mb_tr_ops = {
};
void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb, int *max_insns,
- target_ulong pc, void *host_pc)
+ vaddr pc, void *host_pc)
{
DisasContext dc;
translator_loop(cpu, tb, max_insns, pc, host_pc, &mb_tr_ops, &dc.base);
diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c
index adbdcb1472..2cc4945793 100644
--- a/target/mips/tcg/translate.c
+++ b/target/mips/tcg/translate.c
@@ -15555,7 +15555,7 @@ static const TranslatorOps mips_tr_ops = {
};
void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns,
- target_ulong pc, void *host_pc)
+ vaddr pc, void *host_pc)
{
DisasContext ctx;
diff --git a/target/nios2/translate.c b/target/nios2/translate.c
index e806623594..3078372b36 100644
--- a/target/nios2/translate.c
+++ b/target/nios2/translate.c
@@ -1036,7 +1036,7 @@ static const TranslatorOps nios2_tr_ops = {
};
void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns,
- target_ulong pc, void *host_pc)
+ vaddr pc, void *host_pc)
{
DisasContext dc;
translator_loop(cs, tb, max_insns, pc, host_pc, &nios2_tr_ops, &dc.base);
diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c
index ecff4412b7..d4cbc5eaea 100644
--- a/target/openrisc/translate.c
+++ b/target/openrisc/translate.c
@@ -1658,7 +1658,7 @@ static const TranslatorOps openrisc_tr_ops = {
};
void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns,
- target_ulong pc, void *host_pc)
+ vaddr pc, void *host_pc)
{
DisasContext ctx;
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 329da4d518..049f636927 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -7518,7 +7518,7 @@ static const TranslatorOps ppc_tr_ops = {
};
void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns,
- target_ulong pc, void *host_pc)
+ vaddr pc, void *host_pc)
{
DisasContext ctx;
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index f0be79bb16..6341e4aab0 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -1286,7 +1286,7 @@ static const TranslatorOps riscv_tr_ops = {
};
void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns,
- target_ulong pc, void *host_pc)
+ vaddr pc, void *host_pc)
{
DisasContext ctx;
diff --git a/target/rx/translate.c b/target/rx/translate.c
index f8860830ae..dd3b396946 100644
--- a/target/rx/translate.c
+++ b/target/rx/translate.c
@@ -2271,7 +2271,7 @@ static const TranslatorOps rx_tr_ops = {
};
void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns,
- target_ulong pc, void *host_pc)
+ vaddr pc, void *host_pc)
{
DisasContext dc;
diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c
index 4bae1509f5..f35999ffc0 100644
--- a/target/s390x/tcg/translate.c
+++ b/target/s390x/tcg/translate.c
@@ -6528,7 +6528,7 @@ static const TranslatorOps s390x_tr_ops = {
};
void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns,
- target_ulong pc, void *host_pc)
+ vaddr pc, void *host_pc)
{
DisasContext dc;
diff --git a/target/sh4/translate.c b/target/sh4/translate.c
index cbd8dfc02f..a48aef2cbe 100644
--- a/target/sh4/translate.c
+++ b/target/sh4/translate.c
@@ -2300,7 +2300,7 @@ static const TranslatorOps sh4_tr_ops = {
};
void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns,
- target_ulong pc, void *host_pc)
+ vaddr pc, void *host_pc)
{
DisasContext ctx;
diff --git a/target/sparc/translate.c b/target/sparc/translate.c
index f92ff80ac8..28cd3510e1 100644
--- a/target/sparc/translate.c
+++ b/target/sparc/translate.c
@@ -5709,7 +5709,7 @@ static const TranslatorOps sparc_tr_ops = {
};
void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns,
- target_ulong pc, void *host_pc)
+ vaddr pc, void *host_pc)
{
DisasContext dc = {};
diff --git a/target/tricore/translate.c b/target/tricore/translate.c
index 1b625629bb..b26aa8098f 100644
--- a/target/tricore/translate.c
+++ b/target/tricore/translate.c
@@ -8448,7 +8448,7 @@ static const TranslatorOps tricore_tr_ops = {
void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns,
- target_ulong pc, void *host_pc)
+ vaddr pc, void *host_pc)
{
DisasContext ctx;
translator_loop(cs, tb, max_insns, pc, host_pc,
diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c
index 54bee7ddba..47f321a720 100644
--- a/target/xtensa/translate.c
+++ b/target/xtensa/translate.c
@@ -1256,7 +1256,7 @@ static const TranslatorOps xtensa_translator_ops = {
};
void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb, int *max_insns,
- target_ulong pc, void *host_pc)
+ vaddr pc, void *host_pc)
{
DisasContext dc = {};
translator_loop(cpu, tb, max_insns, pc, host_pc,
--
2.43.0
^ permalink raw reply related [flat|nested] 83+ messages in thread
* [RFC PATCH 09/34] exec: [VADDR] Use vaddr in DisasContextBase for virtual addresses
2024-01-19 14:39 [RFC PATCH 00/34] Compile accel/tcg once (partially) Anton Johansson via
` (7 preceding siblings ...)
2024-01-19 14:39 ` [RFC PATCH 08/34] target: [VADDR] Use vaddr in gen_intermediate_code Anton Johansson via
@ 2024-01-19 14:39 ` Anton Johansson via
2024-01-23 23:22 ` Richard Henderson
2024-01-27 9:33 ` Richard Henderson
2024-01-19 14:40 ` [RFC PATCH 10/34] exec: [VADDR] typedef abi_ptr to vaddr Anton Johansson via
` (24 subsequent siblings)
33 siblings, 2 replies; 83+ messages in thread
From: Anton Johansson via @ 2024-01-19 14:39 UTC (permalink / raw)
To: qemu-devel; +Cc: ale, richard.henderson, philmd
Updates target/ QEMU_LOG macros to use VADDR_PRIx for printing updated
DisasContextBase fields.
Signed-off-by: Anton Johansson <anjo@rev.ng>
---
include/exec/translator.h | 6 +++---
target/mips/tcg/translate.h | 3 ++-
target/hexagon/translate.c | 3 ++-
target/m68k/translate.c | 2 +-
target/mips/tcg/translate.c | 12 ++++++------
5 files changed, 14 insertions(+), 12 deletions(-)
diff --git a/include/exec/translator.h b/include/exec/translator.h
index 2ab8f58bea..c4b46ec8aa 100644
--- a/include/exec/translator.h
+++ b/include/exec/translator.h
@@ -77,8 +77,8 @@ typedef enum DisasJumpType {
*/
typedef struct DisasContextBase {
TranslationBlock *tb;
- target_ulong pc_first;
- target_ulong pc_next;
+ vaddr pc_first;
+ vaddr pc_next;
DisasJumpType is_jmp;
int num_insns;
int max_insns;
@@ -231,7 +231,7 @@ void translator_fake_ldb(uint8_t insn8, abi_ptr pc);
* Translators can use this to enforce the rule that only single-insn
* translation blocks are allowed to cross page boundaries.
*/
-static inline bool is_same_page(const DisasContextBase *db, target_ulong addr)
+static inline bool is_same_page(const DisasContextBase *db, vaddr addr)
{
return ((addr ^ db->pc_first) & TARGET_PAGE_MASK) == 0;
}
diff --git a/target/mips/tcg/translate.h b/target/mips/tcg/translate.h
index cffcfeab8c..93a78b8121 100644
--- a/target/mips/tcg/translate.h
+++ b/target/mips/tcg/translate.h
@@ -202,7 +202,8 @@ extern TCGv bcond;
do { \
if (MIPS_DEBUG_DISAS) { \
qemu_log_mask(CPU_LOG_TB_IN_ASM, \
- TARGET_FMT_lx ": %08x Invalid %s %03x %03x %03x\n", \
+ "%016" VADDR_PRIx \
+ ": %08x Invalid %s %03x %03x %03x\n", \
ctx->base.pc_next, ctx->opcode, op, \
ctx->opcode >> 26, ctx->opcode & 0x3F, \
((ctx->opcode >> 16) & 0x1F)); \
diff --git a/target/hexagon/translate.c b/target/hexagon/translate.c
index 2ef6a89622..7988e54f7d 100644
--- a/target/hexagon/translate.c
+++ b/target/hexagon/translate.c
@@ -234,7 +234,8 @@ static int read_packet_words(CPUHexagonState *env, DisasContext *ctx,
g_assert(ctx->base.num_insns == 1);
}
- HEX_DEBUG_LOG("decode_packet: pc = 0x%x\n", ctx->base.pc_next);
+ HEX_DEBUG_LOG("decode_packet: pc = 0x%" VADDR_PRIx "\n",
+ ctx->base.pc_next);
HEX_DEBUG_LOG(" words = { ");
for (int i = 0; i < nwords; i++) {
HEX_DEBUG_LOG("0x%x, ", words[i]);
diff --git a/target/m68k/translate.c b/target/m68k/translate.c
index 3408385fa1..a51fdef32a 100644
--- a/target/m68k/translate.c
+++ b/target/m68k/translate.c
@@ -1474,7 +1474,7 @@ DISAS_INSN(undef)
* for the 680x0 series, as well as those that are implemented
* but actually illegal for CPU32 or pre-68020.
*/
- qemu_log_mask(LOG_UNIMP, "Illegal instruction: %04x @ %08x\n",
+ qemu_log_mask(LOG_UNIMP, "Illegal instruction: %04x @ %" VADDR_PRIx "\n",
insn, s->base.pc_next);
gen_exception(s, s->base.pc_next, EXCP_ILLEGAL);
}
diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c
index 2cc4945793..c5a7378dee 100644
--- a/target/mips/tcg/translate.c
+++ b/target/mips/tcg/translate.c
@@ -4585,8 +4585,8 @@ static void gen_compute_branch(DisasContext *ctx, uint32_t opc,
if (ctx->hflags & MIPS_HFLAG_BMASK) {
#ifdef MIPS_DEBUG_DISAS
- LOG_DISAS("Branch in delay / forbidden slot at PC 0x"
- TARGET_FMT_lx "\n", ctx->base.pc_next);
+ LOG_DISAS("Branch in delay / forbidden slot at PC 0x%016"
+ VADDR_PRIx "\n", ctx->base.pc_next);
#endif
gen_reserved_instruction(ctx);
goto out;
@@ -9061,8 +9061,8 @@ static void gen_compute_branch1_r6(DisasContext *ctx, uint32_t op,
if (ctx->hflags & MIPS_HFLAG_BMASK) {
#ifdef MIPS_DEBUG_DISAS
- LOG_DISAS("Branch in delay / forbidden slot at PC 0x" TARGET_FMT_lx
- "\n", ctx->base.pc_next);
+ LOG_DISAS("Branch in delay / forbidden slot at PC 0x%016"
+ VADDR_PRIx "\n", ctx->base.pc_next);
#endif
gen_reserved_instruction(ctx);
return;
@@ -11275,8 +11275,8 @@ static void gen_compute_compact_branch(DisasContext *ctx, uint32_t opc,
if (ctx->hflags & MIPS_HFLAG_BMASK) {
#ifdef MIPS_DEBUG_DISAS
- LOG_DISAS("Branch in delay / forbidden slot at PC 0x" TARGET_FMT_lx
- "\n", ctx->base.pc_next);
+ LOG_DISAS("Branch in delay / forbidden slot at PC 0x%016"
+ VADDR_PRIx "\n", ctx->base.pc_next);
#endif
gen_reserved_instruction(ctx);
return;
--
2.43.0
^ permalink raw reply related [flat|nested] 83+ messages in thread
* [RFC PATCH 10/34] exec: [VADDR] typedef abi_ptr to vaddr
2024-01-19 14:39 [RFC PATCH 00/34] Compile accel/tcg once (partially) Anton Johansson via
` (8 preceding siblings ...)
2024-01-19 14:39 ` [RFC PATCH 09/34] exec: [VADDR] Use vaddr in DisasContextBase for virtual addresses Anton Johansson via
@ 2024-01-19 14:40 ` Anton Johansson via
2024-01-23 23:29 ` Richard Henderson
2024-01-27 9:42 ` Richard Henderson
2024-01-19 14:40 ` [RFC PATCH 11/34] [IGNORE] Squash of header code shuffling Anton Johansson via
` (23 subsequent siblings)
33 siblings, 2 replies; 83+ messages in thread
From: Anton Johansson via @ 2024-01-19 14:40 UTC (permalink / raw)
To: qemu-devel; +Cc: ale, richard.henderson, philmd
Signed-off-by: Anton Johansson <anjo@rev.ng>
---
include/exec/cpu_ldst.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/include/exec/cpu_ldst.h b/include/exec/cpu_ldst.h
index 6061e33ac9..eb8f3f0595 100644
--- a/include/exec/cpu_ldst.h
+++ b/include/exec/cpu_ldst.h
@@ -121,8 +121,8 @@ static inline bool guest_range_valid_untagged(abi_ulong start, abi_ulong len)
h2g_nocheck(x); \
})
#else
-typedef target_ulong abi_ptr;
-#define TARGET_ABI_FMT_ptr TARGET_FMT_lx
+typedef vaddr abi_ptr;
+#define TARGET_ABI_FMT_ptr VADDR_PRIx
#endif
uint32_t cpu_ldub_data(CPUArchState *env, abi_ptr ptr);
--
2.43.0
^ permalink raw reply related [flat|nested] 83+ messages in thread
* [RFC PATCH 11/34] [IGNORE] Squash of header code shuffling
2024-01-19 14:39 [RFC PATCH 00/34] Compile accel/tcg once (partially) Anton Johansson via
` (9 preceding siblings ...)
2024-01-19 14:40 ` [RFC PATCH 10/34] exec: [VADDR] typedef abi_ptr to vaddr Anton Johansson via
@ 2024-01-19 14:40 ` Anton Johansson via
2024-01-19 14:40 ` [RFC PATCH 12/34] target: Uninline cpu_mmu_index() Anton Johansson via
` (22 subsequent siblings)
33 siblings, 0 replies; 83+ messages in thread
From: Anton Johansson via @ 2024-01-19 14:40 UTC (permalink / raw)
To: qemu-devel; +Cc: ale, richard.henderson, philmd
This commit squashes header changes that are likely to change during
rebase. Code is moved from common to specific headers, or vice versa
to ensure that no target-specific code is pulled by accel/tcg via
headers.
Signed-off-by: Anton Johansson <anjo@rev.ng>
---
accel/tcg/tb-hash.h | 4 +-
hw/s390x/s390-virtio-hcall.h | 2 +
include/exec/cpu-all.h | 1 +
include/exec/cpu-common.h | 2 +
include/exec/cpu_ldst-target.h | 52 +++++
include/exec/cpu_ldst.h | 60 ++----
include/exec/exec-all.h | 347 +------------------------------
include/exec/exec-common.h | 367 +++++++++++++++++++++++++++++++++
include/exec/memory-internal.h | 2 +-
include/exec/ram_addr.h | 3 +-
include/qemu/plugin-memory.h | 1 -
accel/tcg/cpu-exec.c | 1 +
plugins/core.c | 1 +
target/arm/cpu.c | 1 +
target/sparc/gdbstub.c | 3 +
15 files changed, 459 insertions(+), 388 deletions(-)
create mode 100644 include/exec/cpu_ldst-target.h
create mode 100644 include/exec/exec-common.h
diff --git a/accel/tcg/tb-hash.h b/accel/tcg/tb-hash.h
index a0c61f25cd..2569810365 100644
--- a/accel/tcg/tb-hash.h
+++ b/accel/tcg/tb-hash.h
@@ -20,8 +20,8 @@
#ifndef EXEC_TB_HASH_H
#define EXEC_TB_HASH_H
-#include "exec/cpu-defs.h"
-#include "exec/exec-all.h"
+#include "exec/exec-common.h"
+#include "exec/translation-block.h"
#include "qemu/xxhash.h"
#include "tb-jmp-cache.h"
diff --git a/hw/s390x/s390-virtio-hcall.h b/hw/s390x/s390-virtio-hcall.h
index 9800c4b351..0e48dbf71f 100644
--- a/hw/s390x/s390-virtio-hcall.h
+++ b/hw/s390x/s390-virtio-hcall.h
@@ -12,6 +12,8 @@
#ifndef HW_S390_VIRTIO_HCALL_H
#define HW_S390_VIRTIO_HCALL_H
+#include "qemu/osdep.h"
+#include "cpu.h"
#include "standard-headers/asm-s390/virtio-ccw.h"
/* The only thing that we need from the old kvm_virtio.h file */
diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h
index 83165b1ce4..483e762f05 100644
--- a/include/exec/cpu-all.h
+++ b/include/exec/cpu-all.h
@@ -20,6 +20,7 @@
#define CPU_ALL_H
#include "exec/cpu-common.h"
+#include "exec/cpu-defs.h"
#include "exec/memory.h"
#include "exec/tswap.h"
#include "qemu/thread.h"
diff --git a/include/exec/cpu-common.h b/include/exec/cpu-common.h
index c071f1a003..2eb6589764 100644
--- a/include/exec/cpu-common.h
+++ b/include/exec/cpu-common.h
@@ -3,6 +3,8 @@
/* CPU interfaces that are target independent. */
+#include "qemu/osdep.h"
+#include "hw/core/cpu.h"
#ifndef CONFIG_USER_ONLY
#include "exec/hwaddr.h"
#endif
diff --git a/include/exec/cpu_ldst-target.h b/include/exec/cpu_ldst-target.h
new file mode 100644
index 0000000000..4fdec4a3ff
--- /dev/null
+++ b/include/exec/cpu_ldst-target.h
@@ -0,0 +1,52 @@
+#ifndef CPU_LDST_SPECIFIC_H
+#define CPU_LDST_SPECIFIC_H
+
+#include "cpu-param.h"
+
+#if TARGET_BIG_ENDIAN
+# define cpu_lduw_data cpu_lduw_be_data
+# define cpu_ldsw_data cpu_ldsw_be_data
+# define cpu_ldl_data cpu_ldl_be_data
+# define cpu_ldq_data cpu_ldq_be_data
+# define cpu_lduw_data_ra cpu_lduw_be_data_ra
+# define cpu_ldsw_data_ra cpu_ldsw_be_data_ra
+# define cpu_ldl_data_ra cpu_ldl_be_data_ra
+# define cpu_ldq_data_ra cpu_ldq_be_data_ra
+# define cpu_lduw_mmuidx_ra cpu_lduw_be_mmuidx_ra
+# define cpu_ldsw_mmuidx_ra cpu_ldsw_be_mmuidx_ra
+# define cpu_ldl_mmuidx_ra cpu_ldl_be_mmuidx_ra
+# define cpu_ldq_mmuidx_ra cpu_ldq_be_mmuidx_ra
+# define cpu_stw_data cpu_stw_be_data
+# define cpu_stl_data cpu_stl_be_data
+# define cpu_stq_data cpu_stq_be_data
+# define cpu_stw_data_ra cpu_stw_be_data_ra
+# define cpu_stl_data_ra cpu_stl_be_data_ra
+# define cpu_stq_data_ra cpu_stq_be_data_ra
+# define cpu_stw_mmuidx_ra cpu_stw_be_mmuidx_ra
+# define cpu_stl_mmuidx_ra cpu_stl_be_mmuidx_ra
+# define cpu_stq_mmuidx_ra cpu_stq_be_mmuidx_ra
+#else
+# define cpu_lduw_data cpu_lduw_le_data
+# define cpu_ldsw_data cpu_ldsw_le_data
+# define cpu_ldl_data cpu_ldl_le_data
+# define cpu_ldq_data cpu_ldq_le_data
+# define cpu_lduw_data_ra cpu_lduw_le_data_ra
+# define cpu_ldsw_data_ra cpu_ldsw_le_data_ra
+# define cpu_ldl_data_ra cpu_ldl_le_data_ra
+# define cpu_ldq_data_ra cpu_ldq_le_data_ra
+# define cpu_lduw_mmuidx_ra cpu_lduw_le_mmuidx_ra
+# define cpu_ldsw_mmuidx_ra cpu_ldsw_le_mmuidx_ra
+# define cpu_ldl_mmuidx_ra cpu_ldl_le_mmuidx_ra
+# define cpu_ldq_mmuidx_ra cpu_ldq_le_mmuidx_ra
+# define cpu_stw_data cpu_stw_le_data
+# define cpu_stl_data cpu_stl_le_data
+# define cpu_stq_data cpu_stq_le_data
+# define cpu_stw_data_ra cpu_stw_le_data_ra
+# define cpu_stl_data_ra cpu_stl_le_data_ra
+# define cpu_stq_data_ra cpu_stq_le_data_ra
+# define cpu_stw_mmuidx_ra cpu_stw_le_mmuidx_ra
+# define cpu_stl_mmuidx_ra cpu_stl_le_mmuidx_ra
+# define cpu_stq_mmuidx_ra cpu_stq_le_mmuidx_ra
+#endif
+
+#endif
diff --git a/include/exec/cpu_ldst.h b/include/exec/cpu_ldst.h
index eb8f3f0595..24fe322d72 100644
--- a/include/exec/cpu_ldst.h
+++ b/include/exec/cpu_ldst.h
@@ -64,7 +64,21 @@
#include "exec/memopidx.h"
#include "qemu/int128.h"
+#if defined(CONFIG_USER_ONLY)
#include "cpu.h"
+#include "exec/cpu-all.h"
+#include "exec/user/abitypes.h"
+#include "exec/user/guest-base.h"
+#else
+#include "qemu/typedefs.h"
+#include "exec/cpu-common.h"
+#include "exec/tlb-common.h"
+#include "tcg/tcg.h"
+#endif
+
+#ifdef NEED_CPU_H
+#include "cpu_ldst-target.h"
+#endif
#if defined(CONFIG_USER_ONLY)
/* sparc32plus has 64bit long but 32bit space address
@@ -378,52 +392,6 @@ static inline CPUTLBEntry *tlb_entry(CPUState *cpu, uintptr_t mmu_idx,
#endif /* defined(CONFIG_USER_ONLY) */
-#if TARGET_BIG_ENDIAN
-# define cpu_lduw_data cpu_lduw_be_data
-# define cpu_ldsw_data cpu_ldsw_be_data
-# define cpu_ldl_data cpu_ldl_be_data
-# define cpu_ldq_data cpu_ldq_be_data
-# define cpu_lduw_data_ra cpu_lduw_be_data_ra
-# define cpu_ldsw_data_ra cpu_ldsw_be_data_ra
-# define cpu_ldl_data_ra cpu_ldl_be_data_ra
-# define cpu_ldq_data_ra cpu_ldq_be_data_ra
-# define cpu_lduw_mmuidx_ra cpu_lduw_be_mmuidx_ra
-# define cpu_ldsw_mmuidx_ra cpu_ldsw_be_mmuidx_ra
-# define cpu_ldl_mmuidx_ra cpu_ldl_be_mmuidx_ra
-# define cpu_ldq_mmuidx_ra cpu_ldq_be_mmuidx_ra
-# define cpu_stw_data cpu_stw_be_data
-# define cpu_stl_data cpu_stl_be_data
-# define cpu_stq_data cpu_stq_be_data
-# define cpu_stw_data_ra cpu_stw_be_data_ra
-# define cpu_stl_data_ra cpu_stl_be_data_ra
-# define cpu_stq_data_ra cpu_stq_be_data_ra
-# define cpu_stw_mmuidx_ra cpu_stw_be_mmuidx_ra
-# define cpu_stl_mmuidx_ra cpu_stl_be_mmuidx_ra
-# define cpu_stq_mmuidx_ra cpu_stq_be_mmuidx_ra
-#else
-# define cpu_lduw_data cpu_lduw_le_data
-# define cpu_ldsw_data cpu_ldsw_le_data
-# define cpu_ldl_data cpu_ldl_le_data
-# define cpu_ldq_data cpu_ldq_le_data
-# define cpu_lduw_data_ra cpu_lduw_le_data_ra
-# define cpu_ldsw_data_ra cpu_ldsw_le_data_ra
-# define cpu_ldl_data_ra cpu_ldl_le_data_ra
-# define cpu_ldq_data_ra cpu_ldq_le_data_ra
-# define cpu_lduw_mmuidx_ra cpu_lduw_le_mmuidx_ra
-# define cpu_ldsw_mmuidx_ra cpu_ldsw_le_mmuidx_ra
-# define cpu_ldl_mmuidx_ra cpu_ldl_le_mmuidx_ra
-# define cpu_ldq_mmuidx_ra cpu_ldq_le_mmuidx_ra
-# define cpu_stw_data cpu_stw_le_data
-# define cpu_stl_data cpu_stl_le_data
-# define cpu_stq_data cpu_stq_le_data
-# define cpu_stw_data_ra cpu_stw_le_data_ra
-# define cpu_stl_data_ra cpu_stl_le_data_ra
-# define cpu_stq_data_ra cpu_stq_le_data_ra
-# define cpu_stw_mmuidx_ra cpu_stw_le_mmuidx_ra
-# define cpu_stl_mmuidx_ra cpu_stl_le_mmuidx_ra
-# define cpu_stq_mmuidx_ra cpu_stq_le_mmuidx_ra
-#endif
-
uint8_t cpu_ldb_code_mmu(CPUArchState *env, abi_ptr addr,
MemOpIdx oi, uintptr_t ra);
uint16_t cpu_ldw_code_mmu(CPUArchState *env, abi_ptr addr,
diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
index ee90ef122b..8410521893 100644
--- a/include/exec/exec-all.h
+++ b/include/exec/exec-all.h
@@ -20,352 +20,25 @@
#ifndef EXEC_ALL_H
#define EXEC_ALL_H
+#if defined(CONFIG_USER_ONLY)
#include "cpu.h"
+#endif
+#include "exec/exec-common.h"
#if defined(CONFIG_USER_ONLY)
#include "exec/cpu_ldst.h"
#endif
#include "exec/translation-block.h"
#include "qemu/clang-tsa.h"
-
-/**
- * cpu_loop_exit_requested:
- * @cpu: The CPU state to be tested
- *
- * Indicate if somebody asked for a return of the CPU to the main loop
- * (e.g., via cpu_exit() or cpu_interrupt()).
- *
- * This is helpful for architectures that support interruptible
- * instructions. After writing back all state to registers/memory, this
- * call can be used to check if it makes sense to return to the main loop
- * or to continue executing the interruptible instruction.
- */
-static inline bool cpu_loop_exit_requested(CPUState *cpu)
-{
- return (int32_t)qatomic_read(&cpu->neg.icount_decr.u32) < 0;
-}
-
-#if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG)
-/* cputlb.c */
-/**
- * tlb_init - initialize a CPU's TLB
- * @cpu: CPU whose TLB should be initialized
- */
-void tlb_init(CPUState *cpu);
-/**
- * tlb_destroy - destroy a CPU's TLB
- * @cpu: CPU whose TLB should be destroyed
- */
-void tlb_destroy(CPUState *cpu);
-/**
- * tlb_flush_page:
- * @cpu: CPU whose TLB should be flushed
- * @addr: virtual address of page to be flushed
- *
- * Flush one page from the TLB of the specified CPU, for all
- * MMU indexes.
- */
-void tlb_flush_page(CPUState *cpu, vaddr addr);
-/**
- * tlb_flush_page_all_cpus:
- * @cpu: src CPU of the flush
- * @addr: virtual address of page to be flushed
- *
- * Flush one page from the TLB of the specified CPU, for all
- * MMU indexes.
- */
-void tlb_flush_page_all_cpus(CPUState *src, vaddr addr);
-/**
- * tlb_flush_page_all_cpus_synced:
- * @cpu: src CPU of the flush
- * @addr: virtual address of page to be flushed
- *
- * Flush one page from the TLB of the specified CPU, for all MMU
- * indexes like tlb_flush_page_all_cpus except the source vCPUs work
- * is scheduled as safe work meaning all flushes will be complete once
- * the source vCPUs safe work is complete. This will depend on when
- * the guests translation ends the TB.
- */
-void tlb_flush_page_all_cpus_synced(CPUState *src, vaddr addr);
-/**
- * tlb_flush:
- * @cpu: CPU whose TLB should be flushed
- *
- * Flush the entire TLB for the specified CPU. Most CPU architectures
- * allow the implementation to drop entries from the TLB at any time
- * so this is generally safe. If more selective flushing is required
- * use one of the other functions for efficiency.
- */
-void tlb_flush(CPUState *cpu);
-/**
- * tlb_flush_all_cpus:
- * @cpu: src CPU of the flush
- */
-void tlb_flush_all_cpus(CPUState *src_cpu);
-/**
- * tlb_flush_all_cpus_synced:
- * @cpu: src CPU of the flush
- *
- * Like tlb_flush_all_cpus except this except the source vCPUs work is
- * scheduled as safe work meaning all flushes will be complete once
- * the source vCPUs safe work is complete. This will depend on when
- * the guests translation ends the TB.
- */
-void tlb_flush_all_cpus_synced(CPUState *src_cpu);
-/**
- * tlb_flush_page_by_mmuidx:
- * @cpu: CPU whose TLB should be flushed
- * @addr: virtual address of page to be flushed
- * @idxmap: bitmap of MMU indexes to flush
- *
- * Flush one page from the TLB of the specified CPU, for the specified
- * MMU indexes.
- */
-void tlb_flush_page_by_mmuidx(CPUState *cpu, vaddr addr,
- uint16_t idxmap);
-/**
- * tlb_flush_page_by_mmuidx_all_cpus:
- * @cpu: Originating CPU of the flush
- * @addr: virtual address of page to be flushed
- * @idxmap: bitmap of MMU indexes to flush
- *
- * Flush one page from the TLB of all CPUs, for the specified
- * MMU indexes.
- */
-void tlb_flush_page_by_mmuidx_all_cpus(CPUState *cpu, vaddr addr,
- uint16_t idxmap);
-/**
- * tlb_flush_page_by_mmuidx_all_cpus_synced:
- * @cpu: Originating CPU of the flush
- * @addr: virtual address of page to be flushed
- * @idxmap: bitmap of MMU indexes to flush
- *
- * Flush one page from the TLB of all CPUs, for the specified MMU
- * indexes like tlb_flush_page_by_mmuidx_all_cpus except the source
- * vCPUs work is scheduled as safe work meaning all flushes will be
- * complete once the source vCPUs safe work is complete. This will
- * depend on when the guests translation ends the TB.
- */
-void tlb_flush_page_by_mmuidx_all_cpus_synced(CPUState *cpu, vaddr addr,
- uint16_t idxmap);
-/**
- * tlb_flush_by_mmuidx:
- * @cpu: CPU whose TLB should be flushed
- * @wait: If true ensure synchronisation by exiting the cpu_loop
- * @idxmap: bitmap of MMU indexes to flush
- *
- * Flush all entries from the TLB of the specified CPU, for the specified
- * MMU indexes.
- */
-void tlb_flush_by_mmuidx(CPUState *cpu, uint16_t idxmap);
-/**
- * tlb_flush_by_mmuidx_all_cpus:
- * @cpu: Originating CPU of the flush
- * @idxmap: bitmap of MMU indexes to flush
- *
- * Flush all entries from all TLBs of all CPUs, for the specified
- * MMU indexes.
- */
-void tlb_flush_by_mmuidx_all_cpus(CPUState *cpu, uint16_t idxmap);
-/**
- * tlb_flush_by_mmuidx_all_cpus_synced:
- * @cpu: Originating CPU of the flush
- * @idxmap: bitmap of MMU indexes to flush
- *
- * Flush all entries from all TLBs of all CPUs, for the specified
- * MMU indexes like tlb_flush_by_mmuidx_all_cpus except except the source
- * vCPUs work is scheduled as safe work meaning all flushes will be
- * complete once the source vCPUs safe work is complete. This will
- * depend on when the guests translation ends the TB.
- */
-void tlb_flush_by_mmuidx_all_cpus_synced(CPUState *cpu, uint16_t idxmap);
-
-/**
- * tlb_flush_page_bits_by_mmuidx
- * @cpu: CPU whose TLB should be flushed
- * @addr: virtual address of page to be flushed
- * @idxmap: bitmap of mmu indexes to flush
- * @bits: number of significant bits in address
- *
- * Similar to tlb_flush_page_mask, but with a bitmap of indexes.
- */
-void tlb_flush_page_bits_by_mmuidx(CPUState *cpu, vaddr addr,
- uint16_t idxmap, unsigned bits);
-
-/* Similarly, with broadcast and syncing. */
-void tlb_flush_page_bits_by_mmuidx_all_cpus(CPUState *cpu, vaddr addr,
- uint16_t idxmap, unsigned bits);
-void tlb_flush_page_bits_by_mmuidx_all_cpus_synced
- (CPUState *cpu, vaddr addr, uint16_t idxmap, unsigned bits);
-
-/**
- * tlb_flush_range_by_mmuidx
- * @cpu: CPU whose TLB should be flushed
- * @addr: virtual address of the start of the range to be flushed
- * @len: length of range to be flushed
- * @idxmap: bitmap of mmu indexes to flush
- * @bits: number of significant bits in address
- *
- * For each mmuidx in @idxmap, flush all pages within [@addr,@addr+@len),
- * comparing only the low @bits worth of each virtual page.
- */
-void tlb_flush_range_by_mmuidx(CPUState *cpu, vaddr addr,
- vaddr len, uint16_t idxmap,
- unsigned bits);
-
-/* Similarly, with broadcast and syncing. */
-void tlb_flush_range_by_mmuidx_all_cpus(CPUState *cpu, vaddr addr,
- vaddr len, uint16_t idxmap,
- unsigned bits);
-void tlb_flush_range_by_mmuidx_all_cpus_synced(CPUState *cpu,
- vaddr addr,
- vaddr len,
- uint16_t idxmap,
- unsigned bits);
-
-/**
- * tlb_set_page_full:
- * @cpu: CPU context
- * @mmu_idx: mmu index of the tlb to modify
- * @addr: virtual address of the entry to add
- * @full: the details of the tlb entry
- *
- * Add an entry to @cpu tlb index @mmu_idx. All of the fields of
- * @full must be filled, except for xlat_section, and constitute
- * the complete description of the translated page.
- *
- * This is generally called by the target tlb_fill function after
- * having performed a successful page table walk to find the physical
- * address and attributes for the translation.
- *
- * At most one entry for a given virtual address is permitted. Only a
- * single TARGET_PAGE_SIZE region is mapped; @full->lg_page_size is only
- * used by tlb_flush_page.
- */
-void tlb_set_page_full(CPUState *cpu, int mmu_idx, vaddr addr,
- CPUTLBEntryFull *full);
-
-/**
- * tlb_set_page_with_attrs:
- * @cpu: CPU to add this TLB entry for
- * @addr: virtual address of page to add entry for
- * @paddr: physical address of the page
- * @attrs: memory transaction attributes
- * @prot: access permissions (PAGE_READ/PAGE_WRITE/PAGE_EXEC bits)
- * @mmu_idx: MMU index to insert TLB entry for
- * @size: size of the page in bytes
- *
- * Add an entry to this CPU's TLB (a mapping from virtual address
- * @addr to physical address @paddr) with the specified memory
- * transaction attributes. This is generally called by the target CPU
- * specific code after it has been called through the tlb_fill()
- * entry point and performed a successful page table walk to find
- * the physical address and attributes for the virtual address
- * which provoked the TLB miss.
- *
- * At most one entry for a given virtual address is permitted. Only a
- * single TARGET_PAGE_SIZE region is mapped; the supplied @size is only
- * used by tlb_flush_page.
- */
-void tlb_set_page_with_attrs(CPUState *cpu, vaddr addr,
- hwaddr paddr, MemTxAttrs attrs,
- int prot, int mmu_idx, vaddr size);
-/* tlb_set_page:
+/*
+ * All the code in this header is target independent.
*
- * This function is equivalent to calling tlb_set_page_with_attrs()
- * with an @attrs argument of MEMTXATTRS_UNSPECIFIED. It's provided
- * as a convenience for CPUs which don't use memory transaction attributes.
+ * We only have this cpu.h include here since a lot of
+ * compilation units rely on getting cpu.h from exec-all.h.
*/
-void tlb_set_page(CPUState *cpu, vaddr addr,
- hwaddr paddr, int prot,
- int mmu_idx, vaddr size);
-#else
-static inline void tlb_init(CPUState *cpu)
-{
-}
-static inline void tlb_destroy(CPUState *cpu)
-{
-}
-static inline void tlb_flush_page(CPUState *cpu, vaddr addr)
-{
-}
-static inline void tlb_flush_page_all_cpus(CPUState *src, vaddr addr)
-{
-}
-static inline void tlb_flush_page_all_cpus_synced(CPUState *src, vaddr addr)
-{
-}
-static inline void tlb_flush(CPUState *cpu)
-{
-}
-static inline void tlb_flush_all_cpus(CPUState *src_cpu)
-{
-}
-static inline void tlb_flush_all_cpus_synced(CPUState *src_cpu)
-{
-}
-static inline void tlb_flush_page_by_mmuidx(CPUState *cpu,
- vaddr addr, uint16_t idxmap)
-{
-}
-
-static inline void tlb_flush_by_mmuidx(CPUState *cpu, uint16_t idxmap)
-{
-}
-static inline void tlb_flush_page_by_mmuidx_all_cpus(CPUState *cpu,
- vaddr addr,
- uint16_t idxmap)
-{
-}
-static inline void tlb_flush_page_by_mmuidx_all_cpus_synced(CPUState *cpu,
- vaddr addr,
- uint16_t idxmap)
-{
-}
-static inline void tlb_flush_by_mmuidx_all_cpus(CPUState *cpu, uint16_t idxmap)
-{
-}
-
-static inline void tlb_flush_by_mmuidx_all_cpus_synced(CPUState *cpu,
- uint16_t idxmap)
-{
-}
-static inline void tlb_flush_page_bits_by_mmuidx(CPUState *cpu,
- vaddr addr,
- uint16_t idxmap,
- unsigned bits)
-{
-}
-static inline void tlb_flush_page_bits_by_mmuidx_all_cpus(CPUState *cpu,
- vaddr addr,
- uint16_t idxmap,
- unsigned bits)
-{
-}
-static inline void
-tlb_flush_page_bits_by_mmuidx_all_cpus_synced(CPUState *cpu, vaddr addr,
- uint16_t idxmap, unsigned bits)
-{
-}
-static inline void tlb_flush_range_by_mmuidx(CPUState *cpu, vaddr addr,
- vaddr len, uint16_t idxmap,
- unsigned bits)
-{
-}
-static inline void tlb_flush_range_by_mmuidx_all_cpus(CPUState *cpu,
- vaddr addr,
- vaddr len,
- uint16_t idxmap,
- unsigned bits)
-{
-}
-static inline void tlb_flush_range_by_mmuidx_all_cpus_synced(CPUState *cpu,
- vaddr addr,
- vaddr len,
- uint16_t idxmap,
- unsigned bits)
-{
-}
+#if defined(NEED_CPU_H)
+#include "cpu.h"
#endif
+
/**
* probe_access:
* @env: CPUArchState
diff --git a/include/exec/exec-common.h b/include/exec/exec-common.h
new file mode 100644
index 0000000000..82c7216c39
--- /dev/null
+++ b/include/exec/exec-common.h
@@ -0,0 +1,367 @@
+/*
+ * target-independent internal execution defines for qemu
+ *
+ * Copyright (c) 2003 Fabrice Bellard
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2.1 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef EXEC_COMMON_H
+#define EXEC_COMMON_H
+
+#include "qemu/osdep.h"
+#include "hw/core/cpu.h"
+
+/**
+ * cpu_loop_exit_requested:
+ * @cpu: The CPU state to be tested
+ *
+ * Indicate if somebody asked for a return of the CPU to the main loop
+ * (e.g., via cpu_exit() or cpu_interrupt()).
+ *
+ * This is helpful for architectures that support interruptible
+ * instructions. After writing back all state to registers/memory, this
+ * call can be used to check if it makes sense to return to the main loop
+ * or to continue executing the interruptible instruction.
+ */
+static inline bool cpu_loop_exit_requested(CPUState *cpu)
+{
+ return (int32_t)qatomic_read(&cpu->neg.icount_decr.u32) < 0;
+}
+
+#if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG)
+/* cputlb.c */
+/**
+ * tlb_init - initialize a CPU's TLB
+ * @cpu: CPU whose TLB should be initialized
+ */
+void tlb_init(CPUState *cpu);
+/**
+ * tlb_destroy - destroy a CPU's TLB
+ * @cpu: CPU whose TLB should be destroyed
+ */
+void tlb_destroy(CPUState *cpu);
+/**
+ * tlb_flush_page:
+ * @cpu: CPU whose TLB should be flushed
+ * @addr: virtual address of page to be flushed
+ *
+ * Flush one page from the TLB of the specified CPU, for all
+ * MMU indexes.
+ */
+void tlb_flush_page(CPUState *cpu, vaddr addr);
+/**
+ * tlb_flush_page_all_cpus:
+ * @cpu: src CPU of the flush
+ * @addr: virtual address of page to be flushed
+ *
+ * Flush one page from the TLB of the specified CPU, for all
+ * MMU indexes.
+ */
+void tlb_flush_page_all_cpus(CPUState *src, vaddr addr);
+/**
+ * tlb_flush_page_all_cpus_synced:
+ * @cpu: src CPU of the flush
+ * @addr: virtual address of page to be flushed
+ *
+ * Flush one page from the TLB of the specified CPU, for all MMU
+ * indexes like tlb_flush_page_all_cpus except the source vCPUs work
+ * is scheduled as safe work meaning all flushes will be complete once
+ * the source vCPUs safe work is complete. This will depend on when
+ * the guests translation ends the TB.
+ */
+void tlb_flush_page_all_cpus_synced(CPUState *src, vaddr addr);
+/**
+ * tlb_flush:
+ * @cpu: CPU whose TLB should be flushed
+ *
+ * Flush the entire TLB for the specified CPU. Most CPU architectures
+ * allow the implementation to drop entries from the TLB at any time
+ * so this is generally safe. If more selective flushing is required
+ * use one of the other functions for efficiency.
+ */
+void tlb_flush(CPUState *cpu);
+/**
+ * tlb_flush_all_cpus:
+ * @cpu: src CPU of the flush
+ */
+void tlb_flush_all_cpus(CPUState *src_cpu);
+/**
+ * tlb_flush_all_cpus_synced:
+ * @cpu: src CPU of the flush
+ *
+ * Like tlb_flush_all_cpus except this except the source vCPUs work is
+ * scheduled as safe work meaning all flushes will be complete once
+ * the source vCPUs safe work is complete. This will depend on when
+ * the guests translation ends the TB.
+ */
+void tlb_flush_all_cpus_synced(CPUState *src_cpu);
+/**
+ * tlb_flush_page_by_mmuidx:
+ * @cpu: CPU whose TLB should be flushed
+ * @addr: virtual address of page to be flushed
+ * @idxmap: bitmap of MMU indexes to flush
+ *
+ * Flush one page from the TLB of the specified CPU, for the specified
+ * MMU indexes.
+ */
+void tlb_flush_page_by_mmuidx(CPUState *cpu, vaddr addr,
+ uint16_t idxmap);
+/**
+ * tlb_flush_page_by_mmuidx_all_cpus:
+ * @cpu: Originating CPU of the flush
+ * @addr: virtual address of page to be flushed
+ * @idxmap: bitmap of MMU indexes to flush
+ *
+ * Flush one page from the TLB of all CPUs, for the specified
+ * MMU indexes.
+ */
+void tlb_flush_page_by_mmuidx_all_cpus(CPUState *cpu, vaddr addr,
+ uint16_t idxmap);
+/**
+ * tlb_flush_page_by_mmuidx_all_cpus_synced:
+ * @cpu: Originating CPU of the flush
+ * @addr: virtual address of page to be flushed
+ * @idxmap: bitmap of MMU indexes to flush
+ *
+ * Flush one page from the TLB of all CPUs, for the specified MMU
+ * indexes like tlb_flush_page_by_mmuidx_all_cpus except the source
+ * vCPUs work is scheduled as safe work meaning all flushes will be
+ * complete once the source vCPUs safe work is complete. This will
+ * depend on when the guests translation ends the TB.
+ */
+void tlb_flush_page_by_mmuidx_all_cpus_synced(CPUState *cpu, vaddr addr,
+ uint16_t idxmap);
+/**
+ * tlb_flush_by_mmuidx:
+ * @cpu: CPU whose TLB should be flushed
+ * @wait: If true ensure synchronisation by exiting the cpu_loop
+ * @idxmap: bitmap of MMU indexes to flush
+ *
+ * Flush all entries from the TLB of the specified CPU, for the specified
+ * MMU indexes.
+ */
+void tlb_flush_by_mmuidx(CPUState *cpu, uint16_t idxmap);
+/**
+ * tlb_flush_by_mmuidx_all_cpus:
+ * @cpu: Originating CPU of the flush
+ * @idxmap: bitmap of MMU indexes to flush
+ *
+ * Flush all entries from all TLBs of all CPUs, for the specified
+ * MMU indexes.
+ */
+void tlb_flush_by_mmuidx_all_cpus(CPUState *cpu, uint16_t idxmap);
+/**
+ * tlb_flush_by_mmuidx_all_cpus_synced:
+ * @cpu: Originating CPU of the flush
+ * @idxmap: bitmap of MMU indexes to flush
+ *
+ * Flush all entries from all TLBs of all CPUs, for the specified
+ * MMU indexes like tlb_flush_by_mmuidx_all_cpus except except the source
+ * vCPUs work is scheduled as safe work meaning all flushes will be
+ * complete once the source vCPUs safe work is complete. This will
+ * depend on when the guests translation ends the TB.
+ */
+void tlb_flush_by_mmuidx_all_cpus_synced(CPUState *cpu, uint16_t idxmap);
+
+/**
+ * tlb_flush_page_bits_by_mmuidx
+ * @cpu: CPU whose TLB should be flushed
+ * @addr: virtual address of page to be flushed
+ * @idxmap: bitmap of mmu indexes to flush
+ * @bits: number of significant bits in address
+ *
+ * Similar to tlb_flush_page_mask, but with a bitmap of indexes.
+ */
+void tlb_flush_page_bits_by_mmuidx(CPUState *cpu, vaddr addr,
+ uint16_t idxmap, unsigned bits);
+
+/* Similarly, with broadcast and syncing. */
+void tlb_flush_page_bits_by_mmuidx_all_cpus(CPUState *cpu, vaddr addr,
+ uint16_t idxmap, unsigned bits);
+void tlb_flush_page_bits_by_mmuidx_all_cpus_synced
+ (CPUState *cpu, vaddr addr, uint16_t idxmap, unsigned bits);
+
+/**
+ * tlb_flush_range_by_mmuidx
+ * @cpu: CPU whose TLB should be flushed
+ * @addr: virtual address of the start of the range to be flushed
+ * @len: length of range to be flushed
+ * @idxmap: bitmap of mmu indexes to flush
+ * @bits: number of significant bits in address
+ *
+ * For each mmuidx in @idxmap, flush all pages within [@addr,@addr+@len),
+ * comparing only the low @bits worth of each virtual page.
+ */
+void tlb_flush_range_by_mmuidx(CPUState *cpu, vaddr addr,
+ vaddr len, uint16_t idxmap,
+ unsigned bits);
+
+/* Similarly, with broadcast and syncing. */
+void tlb_flush_range_by_mmuidx_all_cpus(CPUState *cpu, vaddr addr,
+ vaddr len, uint16_t idxmap,
+ unsigned bits);
+void tlb_flush_range_by_mmuidx_all_cpus_synced(CPUState *cpu,
+ vaddr addr,
+ vaddr len,
+ uint16_t idxmap,
+ unsigned bits);
+
+/**
+ * tlb_set_page_full:
+ * @cpu: CPU context
+ * @mmu_idx: mmu index of the tlb to modify
+ * @addr: virtual address of the entry to add
+ * @full: the details of the tlb entry
+ *
+ * Add an entry to @cpu tlb index @mmu_idx. All of the fields of
+ * @full must be filled, except for xlat_section, and constitute
+ * the complete description of the translated page.
+ *
+ * This is generally called by the target tlb_fill function after
+ * having performed a successful page table walk to find the physical
+ * address and attributes for the translation.
+ *
+ * At most one entry for a given virtual address is permitted. Only a
+ * single TARGET_PAGE_SIZE region is mapped; @full->lg_page_size is only
+ * used by tlb_flush_page.
+ */
+void tlb_set_page_full(CPUState *cpu, int mmu_idx, vaddr addr,
+ CPUTLBEntryFull *full);
+
+/**
+ * tlb_set_page_with_attrs:
+ * @cpu: CPU to add this TLB entry for
+ * @addr: virtual address of page to add entry for
+ * @paddr: physical address of the page
+ * @attrs: memory transaction attributes
+ * @prot: access permissions (PAGE_READ/PAGE_WRITE/PAGE_EXEC bits)
+ * @mmu_idx: MMU index to insert TLB entry for
+ * @size: size of the page in bytes
+ *
+ * Add an entry to this CPU's TLB (a mapping from virtual address
+ * @addr to physical address @paddr) with the specified memory
+ * transaction attributes. This is generally called by the target CPU
+ * specific code after it has been called through the tlb_fill()
+ * entry point and performed a successful page table walk to find
+ * the physical address and attributes for the virtual address
+ * which provoked the TLB miss.
+ *
+ * At most one entry for a given virtual address is permitted. Only a
+ * single TARGET_PAGE_SIZE region is mapped; the supplied @size is only
+ * used by tlb_flush_page.
+ */
+void tlb_set_page_with_attrs(CPUState *cpu, vaddr addr,
+ hwaddr paddr, MemTxAttrs attrs,
+ int prot, int mmu_idx, vaddr size);
+/**
+ * tlb_set_page:
+ *
+ * This function is equivalent to calling tlb_set_page_with_attrs()
+ * with an @attrs argument of MEMTXATTRS_UNSPECIFIED. It's provided
+ * as a convenience for CPUs which don't use memory transaction attributes.
+ */
+void tlb_set_page(CPUState *cpu, vaddr addr,
+ hwaddr paddr, int prot,
+ int mmu_idx, vaddr size);
+#else
+static inline void tlb_init(CPUState *cpu)
+{
+}
+static inline void tlb_destroy(CPUState *cpu)
+{
+}
+static inline void tlb_flush_page(CPUState *cpu, vaddr addr)
+{
+}
+static inline void tlb_flush_page_all_cpus(CPUState *src, vaddr addr)
+{
+}
+static inline void tlb_flush_page_all_cpus_synced(CPUState *src, vaddr addr)
+{
+}
+static inline void tlb_flush(CPUState *cpu)
+{
+}
+static inline void tlb_flush_all_cpus(CPUState *src_cpu)
+{
+}
+static inline void tlb_flush_all_cpus_synced(CPUState *src_cpu)
+{
+}
+static inline void tlb_flush_page_by_mmuidx(CPUState *cpu,
+ vaddr addr, uint16_t idxmap)
+{
+}
+
+static inline void tlb_flush_by_mmuidx(CPUState *cpu, uint16_t idxmap)
+{
+}
+static inline void tlb_flush_page_by_mmuidx_all_cpus(CPUState *cpu,
+ vaddr addr,
+ uint16_t idxmap)
+{
+}
+static inline void tlb_flush_page_by_mmuidx_all_cpus_synced(CPUState *cpu,
+ vaddr addr,
+ uint16_t idxmap)
+{
+}
+static inline void tlb_flush_by_mmuidx_all_cpus(CPUState *cpu, uint16_t idxmap)
+{
+}
+
+static inline void tlb_flush_by_mmuidx_all_cpus_synced(CPUState *cpu,
+ uint16_t idxmap)
+{
+}
+static inline void tlb_flush_page_bits_by_mmuidx(CPUState *cpu,
+ vaddr addr,
+ uint16_t idxmap,
+ unsigned bits)
+{
+}
+static inline void tlb_flush_page_bits_by_mmuidx_all_cpus(CPUState *cpu,
+ vaddr addr,
+ uint16_t idxmap,
+ unsigned bits)
+{
+}
+static inline void
+tlb_flush_page_bits_by_mmuidx_all_cpus_synced(CPUState *cpu, vaddr addr,
+ uint16_t idxmap, unsigned bits)
+{
+}
+static inline void tlb_flush_range_by_mmuidx(CPUState *cpu, vaddr addr,
+ vaddr len, uint16_t idxmap,
+ unsigned bits)
+{
+}
+static inline void tlb_flush_range_by_mmuidx_all_cpus(CPUState *cpu,
+ vaddr addr,
+ vaddr len,
+ uint16_t idxmap,
+ unsigned bits)
+{
+}
+static inline void tlb_flush_range_by_mmuidx_all_cpus_synced(CPUState *cpu,
+ vaddr addr,
+ vaddr len,
+ uint16_t idxmap,
+ unsigned bits)
+{
+}
+#endif
+
+#endif /* EXEC_COMMON_H */
diff --git a/include/exec/memory-internal.h b/include/exec/memory-internal.h
index 100c1237ac..ef9816d0c1 100644
--- a/include/exec/memory-internal.h
+++ b/include/exec/memory-internal.h
@@ -20,7 +20,7 @@
#ifndef MEMORY_INTERNAL_H
#define MEMORY_INTERNAL_H
-#include "cpu.h"
+#include "exec/memory.h"
#ifndef CONFIG_USER_ONLY
static inline AddressSpaceDispatch *flatview_to_dispatch(FlatView *fv)
diff --git a/include/exec/ram_addr.h b/include/exec/ram_addr.h
index 9f2e3893f5..765290a2f4 100644
--- a/include/exec/ram_addr.h
+++ b/include/exec/ram_addr.h
@@ -20,11 +20,12 @@
#define RAM_ADDR_H
#ifndef CONFIG_USER_ONLY
-#include "cpu.h"
#include "sysemu/xen.h"
#include "sysemu/tcg.h"
#include "exec/ramlist.h"
#include "exec/ramblock.h"
+#include "exec/memory.h"
+#include "qemu/bitmap.h"
extern uint64_t total_dirty_pages;
diff --git a/include/qemu/plugin-memory.h b/include/qemu/plugin-memory.h
index 71c1123308..6065ec7aaf 100644
--- a/include/qemu/plugin-memory.h
+++ b/include/qemu/plugin-memory.h
@@ -9,7 +9,6 @@
#ifndef PLUGIN_MEMORY_H
#define PLUGIN_MEMORY_H
-#include "exec/cpu-defs.h"
#include "exec/hwaddr.h"
struct qemu_plugin_hwaddr {
diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c
index fd0fc08f76..88de0eb000 100644
--- a/accel/tcg/cpu-exec.c
+++ b/accel/tcg/cpu-exec.c
@@ -34,6 +34,7 @@
#include "hw/i386/apic.h"
#endif
#include "sysemu/cpus.h"
+#include "cpu.h"
#include "exec/cpu-all.h"
#include "sysemu/cpu-timers.h"
#include "exec/replay-core.h"
diff --git a/plugins/core.c b/plugins/core.c
index 3c4e26c7ed..987b5300c7 100644
--- a/plugins/core.c
+++ b/plugins/core.c
@@ -24,6 +24,7 @@
#include "exec/cpu-common.h"
#include "exec/exec-all.h"
+#include "exec/cpu-defs.h"
#include "exec/tb-flush.h"
#include "tcg/tcg.h"
#include "tcg/tcg-op.h"
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 831295d7cd..374ef523da 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -32,6 +32,7 @@
#endif /* CONFIG_TCG */
#include "internals.h"
#include "exec/exec-all.h"
+#include "exec/cpu-all.h"
#include "hw/qdev-properties.h"
#if !defined(CONFIG_USER_ONLY)
#include "hw/loader.h"
diff --git a/target/sparc/gdbstub.c b/target/sparc/gdbstub.c
index a1c8fdc4d5..b3eb8d035f 100644
--- a/target/sparc/gdbstub.c
+++ b/target/sparc/gdbstub.c
@@ -20,6 +20,9 @@
#include "qemu/osdep.h"
#include "cpu.h"
#include "gdbstub/helpers.h"
+#if defined(TARGET_ABI32) && defined(CONFIG_USER_ONLY)
+#include "exec/user/abitypes.h"
+#endif
#ifdef TARGET_ABI32
#define gdb_get_rega(buf, val) gdb_get_reg32(buf, val)
--
2.43.0
^ permalink raw reply related [flat|nested] 83+ messages in thread
* [RFC PATCH 12/34] target: Uninline cpu_mmu_index()
2024-01-19 14:39 [RFC PATCH 00/34] Compile accel/tcg once (partially) Anton Johansson via
` (10 preceding siblings ...)
2024-01-19 14:40 ` [RFC PATCH 11/34] [IGNORE] Squash of header code shuffling Anton Johansson via
@ 2024-01-19 14:40 ` Anton Johansson via
2024-01-23 23:40 ` Richard Henderson
2024-01-27 10:10 ` Richard Henderson
2024-01-19 14:40 ` [RFC PATCH 13/34] target: Uninline cpu_get_tb_cpu_state() Anton Johansson via
` (21 subsequent siblings)
33 siblings, 2 replies; 83+ messages in thread
From: Anton Johansson via @ 2024-01-19 14:40 UTC (permalink / raw)
To: qemu-devel; +Cc: ale, richard.henderson, philmd
Uninlines the target-defined cpu_mmu_index() function by moving its
definition to target/*/cpu.c. This allows for compiling memory access
functions in accel/tcg/cputlb.c without having to know target specifics.
Signed-off-by: Anton Johansson <anjo@rev.ng>
---
include/exec/cpu-common.h | 10 ++++++++++
target/alpha/cpu.h | 9 ---------
target/arm/cpu.h | 13 -------------
target/avr/cpu.h | 6 ------
target/cris/cpu.h | 4 ----
target/hexagon/cpu.h | 9 ---------
target/hppa/cpu.h | 12 ------------
target/i386/cpu.h | 7 -------
target/loongarch/cpu.h | 12 ------------
target/m68k/cpu.h | 4 ----
target/microblaze/cpu.h | 15 ---------------
target/mips/cpu.h | 14 +-------------
target/nios2/cpu.h | 6 ------
target/openrisc/cpu.h | 12 ------------
target/ppc/cpu.h | 8 --------
target/riscv/cpu.h | 2 --
target/rx/cpu.h | 5 -----
target/s390x/cpu.h | 31 -------------------------------
target/sh4/cpu.h | 10 ----------
target/sparc/cpu.h | 28 ----------------------------
target/tricore/cpu.h | 5 -----
target/xtensa/cpu.h | 5 -----
target/alpha/cpu.c | 8 ++++++++
target/arm/cpu.c | 5 +++++
target/avr/cpu.c | 5 +++++
target/cris/cpu.c | 4 ++++
target/hexagon/cpu.c | 9 +++++++++
target/hppa/cpu.c | 12 ++++++++++++
target/i386/cpu.c | 7 +++++++
target/loongarch/cpu.c | 12 ++++++++++++
target/m68k/cpu.c | 5 +++++
target/microblaze/cpu.c | 16 ++++++++++++++++
target/mips/cpu.c | 14 ++++++++++++++
target/nios2/cpu.c | 6 ++++++
target/openrisc/cpu.c | 12 ++++++++++++
target/ppc/cpu.c | 9 +++++++++
target/riscv/cpu_helper.c | 2 +-
target/rx/cpu.c | 5 +++++
target/s390x/cpu.c | 31 +++++++++++++++++++++++++++++++
target/sh4/cpu.c | 13 +++++++++++++
target/sparc/cpu.c | 28 ++++++++++++++++++++++++++++
target/tricore/cpu.c | 5 +++++
target/xtensa/cpu.c | 4 ++++
43 files changed, 222 insertions(+), 217 deletions(-)
diff --git a/include/exec/cpu-common.h b/include/exec/cpu-common.h
index 2eb6589764..12952c481c 100644
--- a/include/exec/cpu-common.h
+++ b/include/exec/cpu-common.h
@@ -60,6 +60,16 @@ void cpu_list_lock(void);
void cpu_list_unlock(void);
unsigned int cpu_list_generation_id_get(void);
+/**
+ * cpu_mmu_index:
+ * @env: The cpu environment
+ * @ifetch: True for code access, false for data access.
+ *
+ * Return the core mmu index for the current translation regime.
+ * This function is used by generic TCG code paths.
+ */
+int cpu_mmu_index(CPUArchState *env, bool ifetch);
+
void tcg_flush_softmmu_tlb(CPUState *cs);
void tcg_flush_jmp_cache(CPUState *cs);
diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h
index e2a467ec17..e93186d50e 100644
--- a/target/alpha/cpu.h
+++ b/target/alpha/cpu.h
@@ -380,15 +380,6 @@ enum {
#define TB_FLAG_UNALIGN (1u << 1)
-static inline int cpu_mmu_index(CPUAlphaState *env, bool ifetch)
-{
- int ret = env->flags & ENV_FLAG_PS_USER ? MMU_USER_IDX : MMU_KERNEL_IDX;
- if (env->flags & ENV_FLAG_PAL_MODE) {
- ret = MMU_KERNEL_IDX;
- }
- return ret;
-}
-
enum {
IR_V0 = 0,
IR_T0 = 1,
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 51963b6545..3dfca8f3ae 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -3167,19 +3167,6 @@ FIELD(TBFLAG_A64, NAA, 30, 1)
#define EX_TBFLAG_M32(IN, WHICH) FIELD_EX32(IN.flags2, TBFLAG_M32, WHICH)
#define EX_TBFLAG_AM32(IN, WHICH) FIELD_EX32(IN.flags2, TBFLAG_AM32, WHICH)
-/**
- * cpu_mmu_index:
- * @env: The cpu environment
- * @ifetch: True for code access, false for data access.
- *
- * Return the core mmu index for the current translation regime.
- * This function is used by generic TCG code paths.
- */
-static inline int cpu_mmu_index(CPUARMState *env, bool ifetch)
-{
- return EX_TBFLAG_ANY(env->hflags, MMUIDX);
-}
-
/**
* sve_vq
* @env: the cpu context
diff --git a/target/avr/cpu.h b/target/avr/cpu.h
index 4ce22d8e4f..581ba54aae 100644
--- a/target/avr/cpu.h
+++ b/target/avr/cpu.h
@@ -172,12 +172,6 @@ static inline void set_avr_feature(CPUAVRState *env, int feature)
}
#define cpu_list avr_cpu_list
-#define cpu_mmu_index avr_cpu_mmu_index
-
-static inline int avr_cpu_mmu_index(CPUAVRState *env, bool ifetch)
-{
- return ifetch ? MMU_CODE_IDX : MMU_DATA_IDX;
-}
void avr_cpu_tcg_init(void);
diff --git a/target/cris/cpu.h b/target/cris/cpu.h
index 676b8e93ca..9587a2a229 100644
--- a/target/cris/cpu.h
+++ b/target/cris/cpu.h
@@ -248,10 +248,6 @@ enum {
/* MMU modes definitions */
#define MMU_USER_IDX 1
-static inline int cpu_mmu_index (CPUCRISState *env, bool ifetch)
-{
- return !!(env->pregs[PR_CCS] & U_FLAG);
-}
/* Support function regs. */
#define SFR_RW_GC_CFG 0][0
diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h
index 10cd1efd57..562b5c7095 100644
--- a/target/hexagon/cpu.h
+++ b/target/hexagon/cpu.h
@@ -165,15 +165,6 @@ static inline void cpu_get_tb_cpu_state(CPUHexagonState *env, vaddr *pc,
*flags = hex_flags;
}
-static inline int cpu_mmu_index(CPUHexagonState *env, bool ifetch)
-{
-#ifdef CONFIG_USER_ONLY
- return MMU_USER_IDX;
-#else
-#error System mode not supported on Hexagon yet
-#endif
-}
-
typedef HexagonCPU ArchCPU;
void hexagon_translate_init(void);
diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h
index 7557f884b5..3da91d41d4 100644
--- a/target/hppa/cpu.h
+++ b/target/hppa/cpu.h
@@ -237,18 +237,6 @@ struct ArchCPU {
#include "exec/cpu-all.h"
-static inline int cpu_mmu_index(CPUHPPAState *env, bool ifetch)
-{
-#ifdef CONFIG_USER_ONLY
- return MMU_USER_IDX;
-#else
- if (env->psw & (ifetch ? PSW_C : PSW_D)) {
- return PRIV_TO_MMU_IDX(env->iaoq_f & 3);
- }
- return MMU_PHYS_IDX; /* mmu disabled */
-#endif
-}
-
void hppa_translate_init(void);
#define CPU_RESOLVING_TYPE TYPE_HPPA_CPU
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index e1b41c29f0..7de2bad701 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -2259,13 +2259,6 @@ uint64_t cpu_get_tsc(CPUX86State *env);
#define MMU_NESTED_IDX 3
#define MMU_PHYS_IDX 4
-static inline int cpu_mmu_index(CPUX86State *env, bool ifetch)
-{
- return (env->hflags & HF_CPL_MASK) == 3 ? MMU_USER_IDX :
- (!(env->hflags & HF_SMAP_MASK) || (env->eflags & AC_MASK))
- ? MMU_KNOSMAP_IDX : MMU_KSMAP_IDX;
-}
-
static inline int cpu_mmu_index_kernel(CPUX86State *env)
{
return !(env->hflags & HF_SMAP_MASK) ? MMU_KNOSMAP_IDX :
diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h
index 3b5ec51928..d85103c28d 100644
--- a/target/loongarch/cpu.h
+++ b/target/loongarch/cpu.h
@@ -415,18 +415,6 @@ struct LoongArchCPUClass {
#define MMU_IDX_USER MMU_PLV_USER
#define MMU_IDX_DA 4
-static inline int cpu_mmu_index(CPULoongArchState *env, bool ifetch)
-{
-#ifdef CONFIG_USER_ONLY
- return MMU_IDX_USER;
-#else
- if (FIELD_EX64(env->CSR_CRMD, CSR_CRMD, PG)) {
- return FIELD_EX64(env->CSR_CRMD, CSR_CRMD, PLV);
- }
- return MMU_IDX_DA;
-#endif
-}
-
static inline bool is_la64(CPULoongArchState *env)
{
return FIELD_EX32(env->cpucfg[1], CPUCFG1, ARCH) == CPUCFG1_ARCH_LA64;
diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h
index 20afb0c94d..da13111fd8 100644
--- a/target/m68k/cpu.h
+++ b/target/m68k/cpu.h
@@ -572,10 +572,6 @@ enum {
/* MMU modes definitions */
#define MMU_KERNEL_IDX 0
#define MMU_USER_IDX 1
-static inline int cpu_mmu_index (CPUM68KState *env, bool ifetch)
-{
- return (env->sr & SR_S) == 0 ? 1 : 0;
-}
bool m68k_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
MMUAccessType access_type, int mmu_idx,
diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h
index e43c49d4af..8f8b4f55d4 100644
--- a/target/microblaze/cpu.h
+++ b/target/microblaze/cpu.h
@@ -423,21 +423,6 @@ void mb_cpu_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr,
MemTxResult response, uintptr_t retaddr);
#endif
-static inline int cpu_mmu_index(CPUMBState *env, bool ifetch)
-{
- MicroBlazeCPU *cpu = env_archcpu(env);
-
- /* Are we in nommu mode?. */
- if (!(env->msr & MSR_VM) || !cpu->cfg.use_mmu) {
- return MMU_NOMMU_IDX;
- }
-
- if (env->msr & MSR_UM) {
- return MMU_USER_IDX;
- }
- return MMU_KERNEL_IDX;
-}
-
#ifndef CONFIG_USER_ONLY
extern const VMStateDescription vmstate_mb_cpu;
#endif
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index 67f8e8b988..49915af09d 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -1233,19 +1233,7 @@ uint32_t cpu_rddsp(uint32_t mask_num, CPUMIPSState *env);
*/
#define MMU_USER_IDX 2
-static inline int hflags_mmu_index(uint32_t hflags)
-{
- if (hflags & MIPS_HFLAG_ERL) {
- return 3; /* ERL */
- } else {
- return hflags & MIPS_HFLAG_KSU;
- }
-}
-
-static inline int cpu_mmu_index(CPUMIPSState *env, bool ifetch)
-{
- return hflags_mmu_index(env->hflags);
-}
+int hflags_mmu_index(uint32_t hflags);
#include "exec/cpu-all.h"
diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h
index 70b6377a4f..c1d4fc6542 100644
--- a/target/nios2/cpu.h
+++ b/target/nios2/cpu.h
@@ -279,12 +279,6 @@ void do_nios2_semihosting(CPUNios2State *env);
#define MMU_SUPERVISOR_IDX 0
#define MMU_USER_IDX 1
-static inline int cpu_mmu_index(CPUNios2State *env, bool ifetch)
-{
- return (env->ctrl[CR_STATUS] & CR_STATUS_U) ? MMU_USER_IDX :
- MMU_SUPERVISOR_IDX;
-}
-
#ifndef CONFIG_USER_ONLY
hwaddr nios2_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
bool nios2_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h
index 334997e9a1..d57f820743 100644
--- a/target/openrisc/cpu.h
+++ b/target/openrisc/cpu.h
@@ -376,18 +376,6 @@ static inline void cpu_get_tb_cpu_state(CPUOpenRISCState *env, vaddr *pc,
| (env->sr & (SR_SM | SR_DME | SR_IME | SR_OVE));
}
-static inline int cpu_mmu_index(CPUOpenRISCState *env, bool ifetch)
-{
- int ret = MMU_NOMMU_IDX; /* mmu is disabled */
-
- if (env->sr & (ifetch ? SR_IME : SR_DME)) {
- /* The mmu is enabled; test supervisor state. */
- ret = env->sr & SR_SM ? MMU_SUPERVISOR_IDX : MMU_USER_IDX;
- }
-
- return ret;
-}
-
static inline uint32_t cpu_get_sr(const CPUOpenRISCState *env)
{
return (env->sr
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index f5027616fa..faba987dc0 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -1483,14 +1483,6 @@ int ppc_dcr_write(ppc_dcr_t *dcr_env, int dcrn, uint32_t val);
/* MMU modes definitions */
#define MMU_USER_IDX 0
-static inline int cpu_mmu_index(CPUPPCState *env, bool ifetch)
-{
-#ifdef CONFIG_USER_ONLY
- return MMU_USER_IDX;
-#else
- return (env->hflags >> (ifetch ? HFLAGS_IMMU_IDX : HFLAGS_DMMU_IDX)) & 7;
-#endif
-}
/* Compatibility modes */
#if defined(TARGET_PPC64)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index ef9cf21c0c..9b0590c7d9 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -434,7 +434,6 @@ target_ulong riscv_cpu_get_geilen(CPURISCVState *env);
void riscv_cpu_set_geilen(CPURISCVState *env, target_ulong geilen);
bool riscv_cpu_vector_enabled(CPURISCVState *env);
void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable);
-int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch);
G_NORETURN void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
MMUAccessType access_type,
int mmu_idx, uintptr_t retaddr);
@@ -446,7 +445,6 @@ void riscv_cpu_list(void);
void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp);
#define cpu_list riscv_cpu_list
-#define cpu_mmu_index riscv_cpu_mmu_index
#ifndef CONFIG_USER_ONLY
void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
diff --git a/target/rx/cpu.h b/target/rx/cpu.h
index f66754eb8a..3f5b501acf 100644
--- a/target/rx/cpu.h
+++ b/target/rx/cpu.h
@@ -151,11 +151,6 @@ static inline void cpu_get_tb_cpu_state(CPURXState *env, vaddr *pc,
*flags = FIELD_DP32(*flags, PSW, U, env->psw_u);
}
-static inline int cpu_mmu_index(CPURXState *env, bool ifetch)
-{
- return 0;
-}
-
static inline uint32_t rx_cpu_pack_psw(CPURXState *env)
{
uint32_t psw = 0;
diff --git a/target/s390x/cpu.h b/target/s390x/cpu.h
index 7bea7075e1..5c646cafaa 100644
--- a/target/s390x/cpu.h
+++ b/target/s390x/cpu.h
@@ -348,37 +348,6 @@ extern const VMStateDescription vmstate_s390_cpu;
#define MMU_HOME_IDX 2
#define MMU_REAL_IDX 3
-static inline int cpu_mmu_index(CPUS390XState *env, bool ifetch)
-{
-#ifdef CONFIG_USER_ONLY
- return MMU_USER_IDX;
-#else
- if (!(env->psw.mask & PSW_MASK_DAT)) {
- return MMU_REAL_IDX;
- }
-
- if (ifetch) {
- if ((env->psw.mask & PSW_MASK_ASC) == PSW_ASC_HOME) {
- return MMU_HOME_IDX;
- }
- return MMU_PRIMARY_IDX;
- }
-
- switch (env->psw.mask & PSW_MASK_ASC) {
- case PSW_ASC_PRIMARY:
- return MMU_PRIMARY_IDX;
- case PSW_ASC_SECONDARY:
- return MMU_SECONDARY_IDX;
- case PSW_ASC_HOME:
- return MMU_HOME_IDX;
- case PSW_ASC_ACCREG:
- /* Fallthrough: access register mode is not yet supported */
- default:
- abort();
- }
-#endif
-}
-
static inline void cpu_get_tb_cpu_state(CPUS390XState *env, vaddr *pc,
uint64_t *cs_base, uint32_t *flags)
{
diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h
index f75a235973..218ba24333 100644
--- a/target/sh4/cpu.h
+++ b/target/sh4/cpu.h
@@ -260,16 +260,6 @@ void cpu_load_tlb(CPUSH4State * env);
/* MMU modes definitions */
#define MMU_USER_IDX 1
-static inline int cpu_mmu_index (CPUSH4State *env, bool ifetch)
-{
- /* The instruction in a RTE delay slot is fetched in privileged
- mode, but executed in user mode. */
- if (ifetch && (env->flags & TB_FLAG_DELAY_SLOT_RTE)) {
- return 0;
- } else {
- return (env->sr & (1u << SR_MD)) == 0 ? 1 : 0;
- }
-}
#include "exec/cpu-all.h"
diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h
index b3a98f1d74..bd24cd578c 100644
--- a/target/sparc/cpu.h
+++ b/target/sparc/cpu.h
@@ -692,34 +692,6 @@ static inline int cpu_supervisor_mode(CPUSPARCState *env1)
}
#endif
-static inline int cpu_mmu_index(CPUSPARCState *env, bool ifetch)
-{
-#if defined(CONFIG_USER_ONLY)
- return MMU_USER_IDX;
-#elif !defined(TARGET_SPARC64)
- if ((env->mmuregs[0] & MMU_E) == 0) { /* MMU disabled */
- return MMU_PHYS_IDX;
- } else {
- return env->psrs;
- }
-#else
- /* IMMU or DMMU disabled. */
- if (ifetch
- ? (env->lsu & IMMU_E) == 0 || (env->pstate & PS_RED) != 0
- : (env->lsu & DMMU_E) == 0) {
- return MMU_PHYS_IDX;
- } else if (cpu_hypervisor_mode(env)) {
- return MMU_PHYS_IDX;
- } else if (env->tl > 0) {
- return MMU_NUCLEUS_IDX;
- } else if (cpu_supervisor_mode(env)) {
- return MMU_KERNEL_IDX;
- } else {
- return MMU_USER_IDX;
- }
-#endif
-}
-
static inline int cpu_interrupts_enabled(CPUSPARCState *env1)
{
#if !defined (TARGET_SPARC64)
diff --git a/target/tricore/cpu.h b/target/tricore/cpu.h
index 217937bbf6..9454b0adcd 100644
--- a/target/tricore/cpu.h
+++ b/target/tricore/cpu.h
@@ -371,11 +371,6 @@ void tricore_cpu_list(void);
#define cpu_list tricore_cpu_list
-static inline int cpu_mmu_index(CPUTriCoreState *env, bool ifetch)
-{
- return 0;
-}
-
#include "exec/cpu-all.h"
FIELD(TB_FLAGS, PRIV, 0, 2)
diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h
index c6bbef1e5d..89d6b690af 100644
--- a/target/xtensa/cpu.h
+++ b/target/xtensa/cpu.h
@@ -700,11 +700,6 @@ static inline uint32_t xtensa_replicate_windowstart(CPUXtensaState *env)
/* MMU modes definitions */
#define MMU_USER_IDX 3
-static inline int cpu_mmu_index(CPUXtensaState *env, bool ifetch)
-{
- return xtensa_get_cring(env);
-}
-
#define XTENSA_TBFLAG_RING_MASK 0x3
#define XTENSA_TBFLAG_EXCM 0x4
#define XTENSA_TBFLAG_LITBASE 0x8
diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c
index 51b7d8d1bf..2559ce38ee 100644
--- a/target/alpha/cpu.c
+++ b/target/alpha/cpu.c
@@ -25,6 +25,14 @@
#include "cpu.h"
#include "exec/exec-all.h"
+int cpu_mmu_index(CPUAlphaState *env, bool ifetch)
+{
+ int ret = env->flags & ENV_FLAG_PS_USER ? MMU_USER_IDX : MMU_KERNEL_IDX;
+ if (env->flags & ENV_FLAG_PAL_MODE) {
+ ret = MMU_KERNEL_IDX;
+ }
+ return ret;
+}
static void alpha_cpu_set_pc(CPUState *cs, vaddr value)
{
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 374ef523da..6f640b0e78 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -49,6 +49,11 @@
#include "fpu/softfloat.h"
#include "cpregs.h"
+int cpu_mmu_index(CPUARMState *env, bool ifetch)
+{
+ return EX_TBFLAG_ANY(env->hflags, MMUIDX);
+}
+
static void arm_cpu_set_pc(CPUState *cs, vaddr value)
{
ARMCPU *cpu = ARM_CPU(cs);
diff --git a/target/avr/cpu.c b/target/avr/cpu.c
index 14d8b9d1f0..38263d07dd 100644
--- a/target/avr/cpu.c
+++ b/target/avr/cpu.c
@@ -26,6 +26,11 @@
#include "disas/dis-asm.h"
#include "tcg/debug-assert.h"
+int cpu_mmu_index(CPUAVRState *env, bool ifetch)
+{
+ return ifetch ? MMU_CODE_IDX : MMU_DATA_IDX;
+}
+
static void avr_cpu_set_pc(CPUState *cs, vaddr value)
{
AVRCPU *cpu = AVR_CPU(cs);
diff --git a/target/cris/cpu.c b/target/cris/cpu.c
index be4a44c218..553742a068 100644
--- a/target/cris/cpu.c
+++ b/target/cris/cpu.c
@@ -27,6 +27,10 @@
#include "cpu.h"
#include "mmu.h"
+int cpu_mmu_index(CPUCRISState *env, bool ifetch)
+{
+ return !!(env->pregs[PR_CCS] & U_FLAG);
+}
static void cris_cpu_set_pc(CPUState *cs, vaddr value)
{
diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c
index 1adc11b713..bf7c901705 100644
--- a/target/hexagon/cpu.c
+++ b/target/hexagon/cpu.c
@@ -26,6 +26,15 @@
#include "tcg/tcg.h"
#include "exec/gdbstub.h"
+int cpu_mmu_index(CPUHexagonState *env, bool ifetch)
+{
+#ifdef CONFIG_USER_ONLY
+ return MMU_USER_IDX;
+#else
+#error System mode not supported on Hexagon yet
+#endif
+}
+
static void hexagon_v67_cpu_init(Object *obj) { }
static void hexagon_v68_cpu_init(Object *obj) { }
static void hexagon_v69_cpu_init(Object *obj) { }
diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c
index 1644297bf8..22f031758e 100644
--- a/target/hppa/cpu.c
+++ b/target/hppa/cpu.c
@@ -28,6 +28,18 @@
#include "fpu/softfloat.h"
#include "tcg/tcg.h"
+int cpu_mmu_index(CPUHPPAState *env, bool ifetch)
+{
+#ifdef CONFIG_USER_ONLY
+ return MMU_USER_IDX;
+#else
+ if (env->psw & (ifetch ? PSW_C : PSW_D)) {
+ return PRIV_TO_MMU_IDX(env->iaoq_f & 3);
+ }
+ return MMU_PHYS_IDX; /* mmu disabled */
+#endif
+}
+
static void hppa_cpu_set_pc(CPUState *cs, vaddr value)
{
HPPACPU *cpu = HPPA_CPU(cs);
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 66ab092628..3327ecf6db 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -45,6 +45,13 @@
#include "disas/capstone.h"
#include "cpu-internal.h"
+int cpu_mmu_index(CPUX86State *env, bool ifetch)
+{
+ return (env->hflags & HF_CPL_MASK) == 3 ? MMU_USER_IDX :
+ (!(env->hflags & HF_SMAP_MASK) || (env->eflags & AC_MASK))
+ ? MMU_KNOSMAP_IDX : MMU_KSMAP_IDX;
+}
+
static void x86_cpu_realizefn(DeviceState *dev, Error **errp);
/* Helpers for building CPUID[2] descriptors: */
diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
index e70773c22e..c6c2760e46 100644
--- a/target/loongarch/cpu.c
+++ b/target/loongarch/cpu.c
@@ -20,6 +20,18 @@
#include "sysemu/reset.h"
#include "tcg/tcg.h"
+int cpu_mmu_index(CPULoongArchState *env, bool ifetch)
+{
+#ifdef CONFIG_USER_ONLY
+ return MMU_IDX_USER;
+#else
+ if (FIELD_EX64(env->CSR_CRMD, CSR_CRMD, PG)) {
+ return FIELD_EX64(env->CSR_CRMD, CSR_CRMD, PLV);
+ }
+ return MMU_IDX_DA;
+#endif
+}
+
const char * const regnames[32] = {
"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
"r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c
index 538d9473c2..74da87f07e 100644
--- a/target/m68k/cpu.c
+++ b/target/m68k/cpu.c
@@ -24,6 +24,11 @@
#include "migration/vmstate.h"
#include "fpu/softfloat.h"
+int cpu_mmu_index(CPUM68KState *env, bool ifetch)
+{
+ return (env->sr & SR_S) == 0 ? 1 : 0;
+}
+
static void m68k_cpu_set_pc(CPUState *cs, vaddr value)
{
M68kCPU *cpu = M68K_CPU(cs);
diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c
index bbb3335cad..f8891de41e 100644
--- a/target/microblaze/cpu.c
+++ b/target/microblaze/cpu.c
@@ -32,6 +32,22 @@
#include "fpu/softfloat-helpers.h"
#include "tcg/tcg.h"
+int cpu_mmu_index(CPUMBState *env, bool ifetch)
+{
+ MicroBlazeCPU *cpu = env_archcpu(env);
+
+ /* Are we in nommu mode?. */
+ if (!(env->msr & MSR_VM) || !cpu->cfg.use_mmu) {
+ return MMU_NOMMU_IDX;
+ }
+
+ if (env->msr & MSR_UM) {
+ return MMU_USER_IDX;
+ }
+ return MMU_KERNEL_IDX;
+}
+
+
static const struct {
const char *name;
uint8_t version_id;
diff --git a/target/mips/cpu.c b/target/mips/cpu.c
index a0023edd43..1b5994e9a7 100644
--- a/target/mips/cpu.c
+++ b/target/mips/cpu.c
@@ -35,6 +35,20 @@
#include "semihosting/semihost.h"
#include "fpu_helper.h"
+int hflags_mmu_index(uint32_t hflags)
+{
+ if (hflags & MIPS_HFLAG_ERL) {
+ return 3; /* ERL */
+ } else {
+ return hflags & MIPS_HFLAG_KSU;
+ }
+}
+
+int cpu_mmu_index(CPUMIPSState *env, bool ifetch)
+{
+ return hflags_mmu_index(env->hflags);
+}
+
const char regnames[32][3] = {
"r0", "at", "v0", "v1", "a0", "a1", "a2", "a3",
"t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c
index 15e499f828..887a9bf786 100644
--- a/target/nios2/cpu.c
+++ b/target/nios2/cpu.c
@@ -26,6 +26,12 @@
#include "gdbstub/helpers.h"
#include "hw/qdev-properties.h"
+int cpu_mmu_index(CPUNios2State *env, bool ifetch)
+{
+ return (env->ctrl[CR_STATUS] & CR_STATUS_U) ? MMU_USER_IDX :
+ MMU_SUPERVISOR_IDX;
+}
+
static void nios2_cpu_set_pc(CPUState *cs, vaddr value)
{
Nios2CPU *cpu = NIOS2_CPU(cs);
diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c
index f5a3d5273b..5938d66da3 100644
--- a/target/openrisc/cpu.c
+++ b/target/openrisc/cpu.c
@@ -25,6 +25,18 @@
#include "fpu/softfloat-helpers.h"
#include "tcg/tcg.h"
+int cpu_mmu_index(CPUOpenRISCState *env, bool ifetch)
+{
+ int ret = MMU_NOMMU_IDX; /* mmu is disabled */
+
+ if (env->sr & (ifetch ? SR_IME : SR_DME)) {
+ /* The mmu is enabled; test supervisor state. */
+ ret = env->sr & SR_SM ? MMU_SUPERVISOR_IDX : MMU_USER_IDX;
+ }
+
+ return ret;
+}
+
static void openrisc_cpu_set_pc(CPUState *cs, vaddr value)
{
OpenRISCCPU *cpu = OPENRISC_CPU(cs);
diff --git a/target/ppc/cpu.c b/target/ppc/cpu.c
index e3ad8e0c27..53f1d5c370 100644
--- a/target/ppc/cpu.c
+++ b/target/ppc/cpu.c
@@ -27,6 +27,15 @@
#include "helper_regs.h"
#include "sysemu/tcg.h"
+int cpu_mmu_index(CPUPPCState *env, bool ifetch)
+{
+#ifdef CONFIG_USER_ONLY
+ return MMU_USER_IDX;
+#else
+ return (env->hflags >> (ifetch ? HFLAGS_IMMU_IDX : HFLAGS_DMMU_IDX)) & 7;
+#endif
+}
+
target_ulong cpu_read_xer(const CPUPPCState *env)
{
if (is_isa300(env)) {
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 3a02079290..537a56ed27 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -33,7 +33,7 @@
#include "debug.h"
#include "tcg/oversized-guest.h"
-int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch)
+int cpu_mmu_index(CPURISCVState *env, bool ifetch)
{
#ifdef CONFIG_USER_ONLY
return 0;
diff --git a/target/rx/cpu.c b/target/rx/cpu.c
index 4d0d3a0c8c..1ce1da0a6b 100644
--- a/target/rx/cpu.c
+++ b/target/rx/cpu.c
@@ -26,6 +26,11 @@
#include "fpu/softfloat.h"
#include "tcg/debug-assert.h"
+int cpu_mmu_index(CPURXState *env, bool ifetch)
+{
+ return 0;
+}
+
static void rx_cpu_set_pc(CPUState *cs, vaddr value)
{
RXCPU *cpu = RX_CPU(cs);
diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c
index 4f7599d72c..aa574807f1 100644
--- a/target/s390x/cpu.c
+++ b/target/s390x/cpu.c
@@ -41,6 +41,37 @@
#define CR0_RESET 0xE0UL
#define CR14_RESET 0xC2000000UL;
+int cpu_mmu_index(CPUS390XState *env, bool ifetch)
+{
+#ifdef CONFIG_USER_ONLY
+ return MMU_USER_IDX;
+#else
+ if (!(env->psw.mask & PSW_MASK_DAT)) {
+ return MMU_REAL_IDX;
+ }
+
+ if (ifetch) {
+ if ((env->psw.mask & PSW_MASK_ASC) == PSW_ASC_HOME) {
+ return MMU_HOME_IDX;
+ }
+ return MMU_PRIMARY_IDX;
+ }
+
+ switch (env->psw.mask & PSW_MASK_ASC) {
+ case PSW_ASC_PRIMARY:
+ return MMU_PRIMARY_IDX;
+ case PSW_ASC_SECONDARY:
+ return MMU_SECONDARY_IDX;
+ case PSW_ASC_HOME:
+ return MMU_HOME_IDX;
+ case PSW_ASC_ACCREG:
+ /* Fallthrough: access register mode is not yet supported */
+ default:
+ abort();
+ }
+#endif
+}
+
#ifndef CONFIG_USER_ONLY
static bool is_early_exception_psw(uint64_t mask, uint64_t addr)
{
diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c
index 788e41fea6..6bffe52c04 100644
--- a/target/sh4/cpu.c
+++ b/target/sh4/cpu.c
@@ -28,6 +28,19 @@
#include "fpu/softfloat-helpers.h"
#include "tcg/tcg.h"
+int cpu_mmu_index(CPUSH4State *env, bool ifetch)
+{
+ /*
+ * The instruction in a RTE delay slot is fetched in privileged
+ * mode, but executed in user mode.
+ */
+ if (ifetch && (env->flags & TB_FLAG_DELAY_SLOT_RTE)) {
+ return 0;
+ } else {
+ return (env->sr & (1u << SR_MD)) == 0 ? 1 : 0;
+ }
+}
+
static void superh_cpu_set_pc(CPUState *cs, vaddr value)
{
SuperHCPU *cpu = SUPERH_CPU(cs);
diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c
index 8ba96ae225..256ba2be88 100644
--- a/target/sparc/cpu.c
+++ b/target/sparc/cpu.c
@@ -29,6 +29,34 @@
//#define DEBUG_FEATURES
+int cpu_mmu_index(CPUSPARCState *env, bool ifetch)
+{
+#if defined(CONFIG_USER_ONLY)
+ return MMU_USER_IDX;
+#elif !defined(TARGET_SPARC64)
+ if ((env->mmuregs[0] & MMU_E) == 0) { /* MMU disabled */
+ return MMU_PHYS_IDX;
+ } else {
+ return env->psrs;
+ }
+#else
+ /* IMMU or DMMU disabled. */
+ if (ifetch
+ ? (env->lsu & IMMU_E) == 0 || (env->pstate & PS_RED) != 0
+ : (env->lsu & DMMU_E) == 0) {
+ return MMU_PHYS_IDX;
+ } else if (cpu_hypervisor_mode(env)) {
+ return MMU_PHYS_IDX;
+ } else if (env->tl > 0) {
+ return MMU_NUCLEUS_IDX;
+ } else if (cpu_supervisor_mode(env)) {
+ return MMU_KERNEL_IDX;
+ } else {
+ return MMU_USER_IDX;
+ }
+#endif
+}
+
static void sparc_cpu_reset_hold(Object *obj)
{
CPUState *s = CPU(obj);
diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c
index d1477622e6..a81f37e3e4 100644
--- a/target/tricore/cpu.c
+++ b/target/tricore/cpu.c
@@ -24,6 +24,11 @@
#include "qemu/error-report.h"
#include "tcg/debug-assert.h"
+int cpu_mmu_index(CPUTriCoreState *env, bool ifetch)
+{
+ return 0;
+}
+
static inline void set_feature(CPUTriCoreState *env, int feature)
{
env->features |= 1ULL << feature;
diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c
index ea1dae7390..769b3c9305 100644
--- a/target/xtensa/cpu.c
+++ b/target/xtensa/cpu.c
@@ -39,6 +39,10 @@
#include "exec/memory.h"
#endif
+int cpu_mmu_index(CPUXtensaState *env, bool ifetch)
+{
+ return xtensa_get_cring(env);
+}
static void xtensa_cpu_set_pc(CPUState *cs, vaddr value)
{
--
2.43.0
^ permalink raw reply related [flat|nested] 83+ messages in thread
* [RFC PATCH 13/34] target: Uninline cpu_get_tb_cpu_state()
2024-01-19 14:39 [RFC PATCH 00/34] Compile accel/tcg once (partially) Anton Johansson via
` (11 preceding siblings ...)
2024-01-19 14:40 ` [RFC PATCH 12/34] target: Uninline cpu_mmu_index() Anton Johansson via
@ 2024-01-19 14:40 ` Anton Johansson via
2024-01-23 23:53 ` Richard Henderson
2024-01-27 11:21 ` Richard Henderson
2024-01-19 14:40 ` [RFC PATCH 14/34] exec: [CPUTLB] Move PAGE_* macros to common header Anton Johansson via
` (20 subsequent siblings)
33 siblings, 2 replies; 83+ messages in thread
From: Anton Johansson via @ 2024-01-19 14:40 UTC (permalink / raw)
To: qemu-devel; +Cc: ale, richard.henderson, philmd
Required to compile accel/tcg/translate-all.c once for softmmu targets.
The function gets quite big for some targets so uninlining makes sense.
Signed-off-by: Anton Johansson <anjo@rev.ng>
---
include/exec/cpu-common.h | 4 +++
target/alpha/cpu.h | 11 -------
target/arm/cpu.h | 3 --
target/avr/cpu.h | 18 -----------
target/cris/cpu.h | 10 ------
target/hexagon/cpu.h | 12 -------
target/hppa/cpu.h | 43 -------------------------
target/i386/cpu.h | 9 ------
target/loongarch/cpu.h | 11 -------
target/m68k/cpu.h | 16 ---------
target/microblaze/cpu.h | 8 -----
target/mips/cpu.h | 9 ------
target/nios2/cpu.h | 12 -------
target/openrisc/cpu.h | 10 ------
target/ppc/cpu.h | 13 --------
target/riscv/cpu.h | 3 --
target/rx/cpu.h | 9 ------
target/s390x/cpu.h | 22 -------------
target/sh4/cpu.h | 15 ---------
target/sparc/cpu.h | 35 --------------------
target/tricore/cpu.h | 12 -------
target/xtensa/cpu.h | 68 ---------------------------------------
target/alpha/cpu.c | 11 +++++++
target/avr/cpu.c | 18 +++++++++++
target/cris/cpu.c | 10 ++++++
target/hexagon/cpu.c | 12 +++++++
target/hppa/cpu.c | 47 +++++++++++++++++++++++++++
target/i386/cpu.c | 9 ++++++
target/loongarch/cpu.c | 11 +++++++
target/m68k/cpu.c | 16 +++++++++
target/microblaze/cpu.c | 7 ++++
target/mips/cpu.c | 9 ++++++
target/nios2/cpu.c | 12 +++++++
target/openrisc/cpu.c | 10 ++++++
target/ppc/cpu.c | 11 +++++++
target/rx/cpu.c | 9 ++++++
target/s390x/cpu.c | 24 ++++++++++++++
target/sh4/cpu.c | 15 +++++++++
target/sparc/cpu.c | 35 ++++++++++++++++++++
target/tricore/cpu.c | 12 +++++++
target/xtensa/cpu.c | 68 +++++++++++++++++++++++++++++++++++++++
41 files changed, 350 insertions(+), 349 deletions(-)
diff --git a/include/exec/cpu-common.h b/include/exec/cpu-common.h
index 12952c481c..b5dae4a9d6 100644
--- a/include/exec/cpu-common.h
+++ b/include/exec/cpu-common.h
@@ -70,6 +70,10 @@ unsigned int cpu_list_generation_id_get(void);
*/
int cpu_mmu_index(CPUArchState *env, bool ifetch);
+void cpu_get_tb_cpu_state(CPUArchState *env, vaddr *pc,
+ uint64_t *cs_base, uint32_t *pflags);
+
+
void tcg_flush_softmmu_tlb(CPUState *cs);
void tcg_flush_jmp_cache(CPUState *cs);
diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h
index e93186d50e..09937b32a2 100644
--- a/target/alpha/cpu.h
+++ b/target/alpha/cpu.h
@@ -452,17 +452,6 @@ void alpha_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
MemTxResult response, uintptr_t retaddr);
#endif
-static inline void cpu_get_tb_cpu_state(CPUAlphaState *env, vaddr *pc,
- uint64_t *cs_base, uint32_t *pflags)
-{
- *pc = env->pc;
- *cs_base = 0;
- *pflags = env->flags & ENV_FLAG_TB_MASK;
-#ifdef CONFIG_USER_ONLY
- *pflags |= TB_FLAG_UNALIGN * !env_cpu(env)->prctl_unalign_sigbus;
-#endif
-}
-
#ifdef CONFIG_USER_ONLY
/* Copied from linux ieee_swcr_to_fpcr. */
static inline uint64_t alpha_ieee_swcr_to_fpcr(uint64_t swcr)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 3dfca8f3ae..9732c836b2 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -3212,9 +3212,6 @@ static inline bool arm_cpu_bswap_data(CPUARMState *env)
}
#endif
-void cpu_get_tb_cpu_state(CPUARMState *env, vaddr *pc,
- uint64_t *cs_base, uint32_t *flags);
-
enum {
QEMU_PSCI_CONDUIT_DISABLED = 0,
QEMU_PSCI_CONDUIT_SMC = 1,
diff --git a/target/avr/cpu.h b/target/avr/cpu.h
index 581ba54aae..e454f3ac3c 100644
--- a/target/avr/cpu.h
+++ b/target/avr/cpu.h
@@ -183,24 +183,6 @@ enum {
TB_FLAGS_SKIP = 2,
};
-static inline void cpu_get_tb_cpu_state(CPUAVRState *env, vaddr *pc,
- uint64_t *cs_base, uint32_t *pflags)
-{
- uint32_t flags = 0;
-
- *pc = env->pc_w * 2;
- *cs_base = 0;
-
- if (env->fullacc) {
- flags |= TB_FLAGS_FULL_ACCESS;
- }
- if (env->skip) {
- flags |= TB_FLAGS_SKIP;
- }
-
- *pflags = flags;
-}
-
static inline int cpu_interrupts_enabled(CPUAVRState *env)
{
return env->sregI != 0;
diff --git a/target/cris/cpu.h b/target/cris/cpu.h
index 9587a2a229..1312a719b7 100644
--- a/target/cris/cpu.h
+++ b/target/cris/cpu.h
@@ -261,16 +261,6 @@ enum {
#include "exec/cpu-all.h"
-static inline void cpu_get_tb_cpu_state(CPUCRISState *env, vaddr *pc,
- uint64_t *cs_base, uint32_t *flags)
-{
- *pc = env->pc;
- *cs_base = 0;
- *flags = env->dslot |
- (env->pregs[PR_CCS] & (S_FLAG | P_FLAG | U_FLAG
- | X_FLAG | PFIX_FLAG));
-}
-
#define cpu_list cris_cpu_list
void cris_cpu_list(void);
diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h
index 562b5c7095..8e0b7704ef 100644
--- a/target/hexagon/cpu.h
+++ b/target/hexagon/cpu.h
@@ -153,18 +153,6 @@ struct ArchCPU {
FIELD(TB_FLAGS, IS_TIGHT_LOOP, 0, 1)
-static inline void cpu_get_tb_cpu_state(CPUHexagonState *env, vaddr *pc,
- uint64_t *cs_base, uint32_t *flags)
-{
- uint32_t hex_flags = 0;
- *pc = env->gpr[HEX_REG_PC];
- *cs_base = 0;
- if (*pc == env->gpr[HEX_REG_SA0]) {
- hex_flags = FIELD_DP32(hex_flags, TB_FLAGS, IS_TIGHT_LOOP, 1);
- }
- *flags = hex_flags;
-}
-
typedef HexagonCPU ArchCPU;
void hexagon_translate_init(void);
diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h
index 3da91d41d4..088692db90 100644
--- a/target/hppa/cpu.h
+++ b/target/hppa/cpu.h
@@ -267,49 +267,6 @@ static inline target_ulong hppa_form_gva(CPUHPPAState *env, uint64_t spc,
#define TB_FLAG_PRIV_SHIFT 8
#define TB_FLAG_UNALIGN 0x400
-static inline void cpu_get_tb_cpu_state(CPUHPPAState *env, vaddr *pc,
- uint64_t *cs_base, uint32_t *pflags)
-{
- uint32_t flags = env->psw_n * PSW_N;
-
- /* TB lookup assumes that PC contains the complete virtual address.
- If we leave space+offset separate, we'll get ITLB misses to an
- incomplete virtual address. This also means that we must separate
- out current cpu privilege from the low bits of IAOQ_F. */
-#ifdef CONFIG_USER_ONLY
- *pc = env->iaoq_f & -4;
- *cs_base = env->iaoq_b & -4;
- flags |= TB_FLAG_UNALIGN * !env_cpu(env)->prctl_unalign_sigbus;
-#else
- /* ??? E, T, H, L, B, P bits need to be here, when implemented. */
- flags |= env->psw & (PSW_W | PSW_C | PSW_D);
- flags |= (env->iaoq_f & 3) << TB_FLAG_PRIV_SHIFT;
-
- *pc = (env->psw & PSW_C
- ? hppa_form_gva_psw(env->psw, env->iasq_f, env->iaoq_f & -4)
- : env->iaoq_f & -4);
- *cs_base = env->iasq_f;
-
- /* Insert a difference between IAOQ_B and IAOQ_F within the otherwise zero
- low 32-bits of CS_BASE. This will succeed for all direct branches,
- which is the primary case we care about -- using goto_tb within a page.
- Failure is indicated by a zero difference. */
- if (env->iasq_f == env->iasq_b) {
- target_sreg diff = env->iaoq_b - env->iaoq_f;
- if (TARGET_REGISTER_BITS == 32 || diff == (int32_t)diff) {
- *cs_base |= (uint32_t)diff;
- }
- }
- if ((env->sr[4] == env->sr[5])
- & (env->sr[4] == env->sr[6])
- & (env->sr[4] == env->sr[7])) {
- flags |= TB_FLAG_SR_SAME;
- }
-#endif
-
- *pflags = flags;
-}
-
target_ureg cpu_hppa_get_psw(CPUHPPAState *env);
void cpu_hppa_put_psw(CPUHPPAState *env, target_ureg);
void cpu_hppa_loaded_fr0(CPUHPPAState *env);
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index 7de2bad701..5e938fdac3 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -2278,15 +2278,6 @@ static inline int cpu_mmu_index_kernel(CPUX86State *env)
#include "hw/i386/apic.h"
#endif
-static inline void cpu_get_tb_cpu_state(CPUX86State *env, vaddr *pc,
- uint64_t *cs_base, uint32_t *flags)
-{
- *cs_base = env->segs[R_CS].base;
- *pc = *cs_base + env->eip;
- *flags = env->hflags |
- (env->eflags & (IOPL_MASK | TF_MASK | RF_MASK | VM_MASK | AC_MASK));
-}
-
void do_cpu_init(X86CPU *cpu);
#define MCE_INJECT_BROADCAST 1
diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h
index d85103c28d..ce9bdedbf0 100644
--- a/target/loongarch/cpu.h
+++ b/target/loongarch/cpu.h
@@ -449,17 +449,6 @@ static inline void set_pc(CPULoongArchState *env, uint64_t value)
#define HW_FLAGS_EUEN_SXE 0x08
#define HW_FLAGS_VA32 0x20
-static inline void cpu_get_tb_cpu_state(CPULoongArchState *env, vaddr *pc,
- uint64_t *cs_base, uint32_t *flags)
-{
- *pc = env->pc;
- *cs_base = 0;
- *flags = env->CSR_CRMD & (R_CSR_CRMD_PLV_MASK | R_CSR_CRMD_PG_MASK);
- *flags |= FIELD_EX64(env->CSR_EUEN, CSR_EUEN, FPE) * HW_FLAGS_EUEN_FPE;
- *flags |= FIELD_EX64(env->CSR_EUEN, CSR_EUEN, SXE) * HW_FLAGS_EUEN_SXE;
- *flags |= is_va32(env) * HW_FLAGS_VA32;
-}
-
void loongarch_cpu_list(void);
#define cpu_list loongarch_cpu_list
diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h
index da13111fd8..21c37e2267 100644
--- a/target/m68k/cpu.h
+++ b/target/m68k/cpu.h
@@ -596,22 +596,6 @@ void m68k_cpu_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr,
#define TB_FLAGS_TRACE 16
#define TB_FLAGS_TRACE_BIT (1 << TB_FLAGS_TRACE)
-static inline void cpu_get_tb_cpu_state(CPUM68KState *env, vaddr *pc,
- uint64_t *cs_base, uint32_t *flags)
-{
- *pc = env->pc;
- *cs_base = 0;
- *flags = (env->macsr >> 4) & TB_FLAGS_MACSR;
- if (env->sr & SR_S) {
- *flags |= TB_FLAGS_MSR_S;
- *flags |= (env->sfc << (TB_FLAGS_SFC_S_BIT - 2)) & TB_FLAGS_SFC_S;
- *flags |= (env->dfc << (TB_FLAGS_DFC_S_BIT - 2)) & TB_FLAGS_DFC_S;
- }
- if (M68K_SR_TRACE(env->sr) == M68K_SR_TRACE_ANY_INS) {
- *flags |= TB_FLAGS_TRACE;
- }
-}
-
void dump_mmu(CPUM68KState *env);
#endif
diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h
index 8f8b4f55d4..bdbbf2751b 100644
--- a/target/microblaze/cpu.h
+++ b/target/microblaze/cpu.h
@@ -404,14 +404,6 @@ void mb_tcg_init(void);
/* Ensure there is no overlap between the two masks. */
QEMU_BUILD_BUG_ON(MSR_TB_MASK & IFLAGS_TB_MASK);
-static inline void cpu_get_tb_cpu_state(CPUMBState *env, vaddr *pc,
- uint64_t *cs_base, uint32_t *flags)
-{
- *pc = env->pc;
- *flags = (env->iflags & IFLAGS_TB_MASK) | (env->msr & MSR_TB_MASK);
- *cs_base = (*flags & IMM_FLAG ? env->imm : 0);
-}
-
#if !defined(CONFIG_USER_ONLY)
bool mb_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
MMUAccessType access_type, int mmu_idx,
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index 49915af09d..6d9f95be18 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -1344,15 +1344,6 @@ void itc_reconfigure(struct MIPSITUState *tag);
/* helper.c */
target_ulong exception_resume_pc(CPUMIPSState *env);
-static inline void cpu_get_tb_cpu_state(CPUMIPSState *env, vaddr *pc,
- uint64_t *cs_base, uint32_t *flags)
-{
- *pc = env->active_tc.PC;
- *cs_base = 0;
- *flags = env->hflags & (MIPS_HFLAG_TMASK | MIPS_HFLAG_BMASK |
- MIPS_HFLAG_HWRENA_ULR);
-}
-
/**
* mips_cpu_create_with_clock:
* @typename: a MIPS CPU type.
diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h
index c1d4fc6542..890d91d901 100644
--- a/target/nios2/cpu.h
+++ b/target/nios2/cpu.h
@@ -295,16 +295,4 @@ FIELD(TBFLAGS, CRS0, 0, 1) /* Set if CRS == 0. */
FIELD(TBFLAGS, U, 1, 1) /* Overlaps CR_STATUS_U */
FIELD(TBFLAGS, R0_0, 2, 1) /* Set if R0 == 0. */
-static inline void cpu_get_tb_cpu_state(CPUNios2State *env, vaddr *pc,
- uint64_t *cs_base, uint32_t *flags)
-{
- unsigned crs = FIELD_EX32(env->ctrl[CR_STATUS], CR_STATUS, CRS);
-
- *pc = env->pc;
- *cs_base = 0;
- *flags = (env->ctrl[CR_STATUS] & CR_STATUS_U)
- | (crs ? 0 : R_TBFLAGS_CRS0_MASK)
- | (env->regs[0] ? 0 : R_TBFLAGS_R0_0_MASK);
-}
-
#endif /* NIOS2_CPU_H */
diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h
index d57f820743..bfa3d6fba6 100644
--- a/target/openrisc/cpu.h
+++ b/target/openrisc/cpu.h
@@ -366,16 +366,6 @@ static inline void cpu_set_gpr(CPUOpenRISCState *env, int i, uint32_t val)
env->shadow_gpr[0][i] = val;
}
-static inline void cpu_get_tb_cpu_state(CPUOpenRISCState *env, vaddr *pc,
- uint64_t *cs_base, uint32_t *flags)
-{
- *pc = env->pc;
- *cs_base = 0;
- *flags = (env->dflag ? TB_FLAGS_DFLAG : 0)
- | (cpu_get_gpr(env, 0) ? 0 : TB_FLAGS_R0_0)
- | (env->sr & (SR_SM | SR_DME | SR_IME | SR_OVE));
-}
-
static inline uint32_t cpu_get_sr(const CPUOpenRISCState *env)
{
return (env->sr
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index faba987dc0..46eeb78c33 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -2511,19 +2511,6 @@ void cpu_write_xer(CPUPPCState *env, target_ulong xer);
*/
#define is_book3s_arch2x(ctx) (!!((ctx)->insns_flags & PPC_SEGMENT_64B))
-#ifdef CONFIG_DEBUG_TCG
-void cpu_get_tb_cpu_state(CPUPPCState *env, vaddr *pc,
- uint64_t *cs_base, uint32_t *flags);
-#else
-static inline void cpu_get_tb_cpu_state(CPUPPCState *env, vaddr *pc,
- uint64_t *cs_base, uint32_t *flags)
-{
- *pc = env->nip;
- *cs_base = 0;
- *flags = env->hflags;
-}
-#endif
-
G_NORETURN void raise_exception(CPUPPCState *env, uint32_t exception);
G_NORETURN void raise_exception_ra(CPUPPCState *env, uint32_t exception,
uintptr_t raddr);
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 9b0590c7d9..58ed6700de 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -627,9 +627,6 @@ static inline uint32_t vext_get_vlmax(RISCVCPU *cpu, target_ulong vtype)
return cpu->cfg.vlen >> (sew + 3 - lmul);
}
-void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc,
- uint64_t *cs_base, uint32_t *pflags);
-
void riscv_cpu_update_mask(CPURISCVState *env);
RISCVException riscv_csrrw(CPURISCVState *env, int csrno,
diff --git a/target/rx/cpu.h b/target/rx/cpu.h
index 3f5b501acf..33290e2c47 100644
--- a/target/rx/cpu.h
+++ b/target/rx/cpu.h
@@ -142,15 +142,6 @@ void rx_cpu_unpack_psw(CPURXState *env, uint32_t psw, int rte);
#define RX_CPU_IRQ 0
#define RX_CPU_FIR 1
-static inline void cpu_get_tb_cpu_state(CPURXState *env, vaddr *pc,
- uint64_t *cs_base, uint32_t *flags)
-{
- *pc = env->pc;
- *cs_base = 0;
- *flags = FIELD_DP32(0, PSW, PM, env->psw_pm);
- *flags = FIELD_DP32(*flags, PSW, U, env->psw_u);
-}
-
static inline uint32_t rx_cpu_pack_psw(CPURXState *env)
{
uint32_t psw = 0;
diff --git a/target/s390x/cpu.h b/target/s390x/cpu.h
index 5c646cafaa..eeb10d10bd 100644
--- a/target/s390x/cpu.h
+++ b/target/s390x/cpu.h
@@ -348,28 +348,6 @@ extern const VMStateDescription vmstate_s390_cpu;
#define MMU_HOME_IDX 2
#define MMU_REAL_IDX 3
-static inline void cpu_get_tb_cpu_state(CPUS390XState *env, vaddr *pc,
- uint64_t *cs_base, uint32_t *flags)
-{
- if (env->psw.addr & 1) {
- /*
- * Instructions must be at even addresses.
- * This needs to be checked before address translation.
- */
- env->int_pgm_ilen = 2; /* see s390_cpu_tlb_fill() */
- tcg_s390_program_interrupt(env, PGM_SPECIFICATION, 0);
- }
- *pc = env->psw.addr;
- *cs_base = env->ex_value;
- *flags = (env->psw.mask >> FLAG_MASK_PSW_SHIFT) & FLAG_MASK_PSW;
- if (env->cregs[0] & CR0_AFP) {
- *flags |= FLAG_MASK_AFP;
- }
- if (env->cregs[0] & CR0_VECTOR) {
- *flags |= FLAG_MASK_VECTOR;
- }
-}
-
/* PER bits from control register 9 */
#define PER_CR9_EVENT_BRANCH 0x80000000
#define PER_CR9_EVENT_IFETCH 0x40000000
diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h
index 218ba24333..818810769f 100644
--- a/target/sh4/cpu.h
+++ b/target/sh4/cpu.h
@@ -357,19 +357,4 @@ static inline void cpu_write_sr(CPUSH4State *env, target_ulong sr)
env->sr = sr & ~((1u << SR_M) | (1u << SR_Q) | (1u << SR_T));
}
-static inline void cpu_get_tb_cpu_state(CPUSH4State *env, vaddr *pc,
- uint64_t *cs_base, uint32_t *flags)
-{
- *pc = env->pc;
- /* For a gUSA region, notice the end of the region. */
- *cs_base = env->flags & TB_FLAG_GUSA_MASK ? env->gregs[0] : 0;
- *flags = env->flags
- | (env->fpscr & TB_FLAG_FPSCR_MASK)
- | (env->sr & TB_FLAG_SR_MASK)
- | (env->movcal_backup ? TB_FLAG_PENDING_MOVCA : 0); /* Bit 3 */
-#ifdef CONFIG_USER_ONLY
- *flags |= TB_FLAG_UNALIGN * !env_cpu(env)->prctl_unalign_sigbus;
-#endif
-}
-
#endif /* SH4_CPU_H */
diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h
index bd24cd578c..33338f8846 100644
--- a/target/sparc/cpu.h
+++ b/target/sparc/cpu.h
@@ -733,41 +733,6 @@ trap_state* cpu_tsptr(CPUSPARCState* env);
#define TB_FLAG_HYPER (1 << 7)
#define TB_FLAG_ASI_SHIFT 24
-static inline void cpu_get_tb_cpu_state(CPUSPARCState *env, vaddr *pc,
- uint64_t *cs_base, uint32_t *pflags)
-{
- uint32_t flags;
- *pc = env->pc;
- *cs_base = env->npc;
- flags = cpu_mmu_index(env, false);
-#ifndef CONFIG_USER_ONLY
- if (cpu_supervisor_mode(env)) {
- flags |= TB_FLAG_SUPER;
- }
-#endif
-#ifdef TARGET_SPARC64
-#ifndef CONFIG_USER_ONLY
- if (cpu_hypervisor_mode(env)) {
- flags |= TB_FLAG_HYPER;
- }
-#endif
- if (env->pstate & PS_AM) {
- flags |= TB_FLAG_AM_ENABLED;
- }
- if ((env->def.features & CPU_FEATURE_FLOAT)
- && (env->pstate & PS_PEF)
- && (env->fprs & FPRS_FEF)) {
- flags |= TB_FLAG_FPU_ENABLED;
- }
- flags |= env->asi << TB_FLAG_ASI_SHIFT;
-#else
- if ((env->def.features & CPU_FEATURE_FLOAT) && env->psref) {
- flags |= TB_FLAG_FPU_ENABLED;
- }
-#endif
- *pflags = flags;
-}
-
static inline bool tb_fpu_enabled(int tb_flags)
{
#if defined(CONFIG_USER_ONLY)
diff --git a/target/tricore/cpu.h b/target/tricore/cpu.h
index 9454b0adcd..43604f00ca 100644
--- a/target/tricore/cpu.h
+++ b/target/tricore/cpu.h
@@ -378,18 +378,6 @@ FIELD(TB_FLAGS, PRIV, 0, 2)
void cpu_state_reset(CPUTriCoreState *s);
void tricore_tcg_init(void);
-static inline void cpu_get_tb_cpu_state(CPUTriCoreState *env, vaddr *pc,
- uint64_t *cs_base, uint32_t *flags)
-{
- uint32_t new_flags = 0;
- *pc = env->PC;
- *cs_base = 0;
-
- new_flags |= FIELD_DP32(new_flags, TB_FLAGS, PRIV,
- extract32(env->PSW, 10, 2));
- *flags = new_flags;
-}
-
#define TRICORE_CPU_TYPE_SUFFIX "-" TYPE_TRICORE_CPU
#define TRICORE_CPU_TYPE_NAME(model) model TRICORE_CPU_TYPE_SUFFIX
#define CPU_RESOLVING_TYPE TYPE_TRICORE_CPU
diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h
index 89d6b690af..0c51d2b0ec 100644
--- a/target/xtensa/cpu.h
+++ b/target/xtensa/cpu.h
@@ -721,74 +721,6 @@ static inline uint32_t xtensa_replicate_windowstart(CPUXtensaState *env)
#include "exec/cpu-all.h"
-static inline void cpu_get_tb_cpu_state(CPUXtensaState *env, vaddr *pc,
- uint64_t *cs_base, uint32_t *flags)
-{
- *pc = env->pc;
- *cs_base = 0;
- *flags = 0;
- *flags |= xtensa_get_ring(env);
- if (env->sregs[PS] & PS_EXCM) {
- *flags |= XTENSA_TBFLAG_EXCM;
- } else if (xtensa_option_enabled(env->config, XTENSA_OPTION_LOOP)) {
- target_ulong lend_dist =
- env->sregs[LEND] - (env->pc & -(1u << TARGET_PAGE_BITS));
-
- /*
- * 0 in the csbase_lend field means that there may not be a loopback
- * for any instruction that starts inside this page. Any other value
- * means that an instruction that ends at this offset from the page
- * start may loop back and will need loopback code to be generated.
- *
- * lend_dist is 0 when LEND points to the start of the page, but
- * no instruction that starts inside this page may end at offset 0,
- * so it's still correct.
- *
- * When an instruction ends at a page boundary it may only start in
- * the previous page. lend_dist will be encoded as TARGET_PAGE_SIZE
- * for the TB that contains this instruction.
- */
- if (lend_dist < (1u << TARGET_PAGE_BITS) + env->config->max_insn_size) {
- target_ulong lbeg_off = env->sregs[LEND] - env->sregs[LBEG];
-
- *cs_base = lend_dist;
- if (lbeg_off < 256) {
- *cs_base |= lbeg_off << XTENSA_CSBASE_LBEG_OFF_SHIFT;
- }
- }
- }
- if (xtensa_option_enabled(env->config, XTENSA_OPTION_EXTENDED_L32R) &&
- (env->sregs[LITBASE] & 1)) {
- *flags |= XTENSA_TBFLAG_LITBASE;
- }
- if (xtensa_option_enabled(env->config, XTENSA_OPTION_DEBUG)) {
- if (xtensa_get_cintlevel(env) < env->config->debug_level) {
- *flags |= XTENSA_TBFLAG_DEBUG;
- }
- if (xtensa_get_cintlevel(env) < env->sregs[ICOUNTLEVEL]) {
- *flags |= XTENSA_TBFLAG_ICOUNT;
- }
- }
- if (xtensa_option_enabled(env->config, XTENSA_OPTION_COPROCESSOR)) {
- *flags |= env->sregs[CPENABLE] << XTENSA_TBFLAG_CPENABLE_SHIFT;
- }
- if (xtensa_option_enabled(env->config, XTENSA_OPTION_WINDOWED_REGISTER) &&
- (env->sregs[PS] & (PS_WOE | PS_EXCM)) == PS_WOE) {
- uint32_t windowstart = xtensa_replicate_windowstart(env) >>
- (env->sregs[WINDOW_BASE] + 1);
- uint32_t w = ctz32(windowstart | 0x8);
-
- *flags |= (w << XTENSA_TBFLAG_WINDOW_SHIFT) | XTENSA_TBFLAG_CWOE;
- *flags |= extract32(env->sregs[PS], PS_CALLINC_SHIFT,
- PS_CALLINC_LEN) << XTENSA_TBFLAG_CALLINC_SHIFT;
- } else {
- *flags |= 3 << XTENSA_TBFLAG_WINDOW_SHIFT;
- }
- if (env->yield_needed) {
- *flags |= XTENSA_TBFLAG_YIELD;
- }
-}
-
XtensaCPU *xtensa_cpu_create_with_clock(const char *cpu_type,
Clock *cpu_refclk);
diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c
index 2559ce38ee..5e468d4605 100644
--- a/target/alpha/cpu.c
+++ b/target/alpha/cpu.c
@@ -34,6 +34,17 @@ int cpu_mmu_index(CPUAlphaState *env, bool ifetch)
return ret;
}
+void cpu_get_tb_cpu_state(CPUAlphaState *env, vaddr *pc,
+ uint64_t *cs_base, uint32_t *pflags)
+{
+ *pc = env->pc;
+ *cs_base = 0;
+ *pflags = env->flags & ENV_FLAG_TB_MASK;
+#ifdef CONFIG_USER_ONLY
+ *pflags |= TB_FLAG_UNALIGN * !env_cpu(env)->prctl_unalign_sigbus;
+#endif
+}
+
static void alpha_cpu_set_pc(CPUState *cs, vaddr value)
{
AlphaCPU *cpu = ALPHA_CPU(cs);
diff --git a/target/avr/cpu.c b/target/avr/cpu.c
index 38263d07dd..351e127fea 100644
--- a/target/avr/cpu.c
+++ b/target/avr/cpu.c
@@ -31,6 +31,24 @@ int cpu_mmu_index(CPUAVRState *env, bool ifetch)
return ifetch ? MMU_CODE_IDX : MMU_DATA_IDX;
}
+void cpu_get_tb_cpu_state(CPUAVRState *env, vaddr *pc,
+ uint64_t *cs_base, uint32_t *pflags)
+{
+ uint32_t flags = 0;
+
+ *pc = env->pc_w * 2;
+ *cs_base = 0;
+
+ if (env->fullacc) {
+ flags |= TB_FLAGS_FULL_ACCESS;
+ }
+ if (env->skip) {
+ flags |= TB_FLAGS_SKIP;
+ }
+
+ *pflags = flags;
+}
+
static void avr_cpu_set_pc(CPUState *cs, vaddr value)
{
AVRCPU *cpu = AVR_CPU(cs);
diff --git a/target/cris/cpu.c b/target/cris/cpu.c
index 553742a068..8880e94a8e 100644
--- a/target/cris/cpu.c
+++ b/target/cris/cpu.c
@@ -32,6 +32,16 @@ int cpu_mmu_index(CPUCRISState *env, bool ifetch)
return !!(env->pregs[PR_CCS] & U_FLAG);
}
+void cpu_get_tb_cpu_state(CPUCRISState *env, vaddr *pc,
+ uint64_t *cs_base, uint32_t *flags)
+{
+ *pc = env->pc;
+ *cs_base = 0;
+ *flags = env->dslot |
+ (env->pregs[PR_CCS] & (S_FLAG | P_FLAG | U_FLAG
+ | X_FLAG | PFIX_FLAG));
+}
+
static void cris_cpu_set_pc(CPUState *cs, vaddr value)
{
CRISCPU *cpu = CRIS_CPU(cs);
diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c
index bf7c901705..68b6e1a31f 100644
--- a/target/hexagon/cpu.c
+++ b/target/hexagon/cpu.c
@@ -35,6 +35,18 @@ int cpu_mmu_index(CPUHexagonState *env, bool ifetch)
#endif
}
+void cpu_get_tb_cpu_state(CPUHexagonState *env, vaddr *pc,
+ uint64_t *cs_base, uint32_t *flags)
+{
+ uint32_t hex_flags = 0;
+ *pc = env->gpr[HEX_REG_PC];
+ *cs_base = 0;
+ if (*pc == env->gpr[HEX_REG_SA0]) {
+ hex_flags = FIELD_DP32(hex_flags, TB_FLAGS, IS_TIGHT_LOOP, 1);
+ }
+ *flags = hex_flags;
+}
+
static void hexagon_v67_cpu_init(Object *obj) { }
static void hexagon_v68_cpu_init(Object *obj) { }
static void hexagon_v69_cpu_init(Object *obj) { }
diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c
index 22f031758e..0103e0429b 100644
--- a/target/hppa/cpu.c
+++ b/target/hppa/cpu.c
@@ -40,6 +40,53 @@ int cpu_mmu_index(CPUHPPAState *env, bool ifetch)
#endif
}
+void cpu_get_tb_cpu_state(CPUHPPAState *env, vaddr *pc,
+ uint64_t *cs_base, uint32_t *pflags)
+{
+ uint32_t flags = env->psw_n * PSW_N;
+
+ /*
+ * TB lookup assumes that PC contains the complete virtual address.
+ * If we leave space+offset separate, we'll get ITLB misses to an
+ * incomplete virtual address. This also means that we must separate
+ * out current cpu privilege from the low bits of IAOQ_F.
+ */
+#ifdef CONFIG_USER_ONLY
+ *pc = env->iaoq_f & -4;
+ *cs_base = env->iaoq_b & -4;
+ flags |= TB_FLAG_UNALIGN * !env_cpu(env)->prctl_unalign_sigbus;
+#else
+ /* ??? E, T, H, L, B, P bits need to be here, when implemented. */
+ flags |= env->psw & (PSW_W | PSW_C | PSW_D);
+ flags |= (env->iaoq_f & 3) << TB_FLAG_PRIV_SHIFT;
+
+ *pc = (env->psw & PSW_C
+ ? hppa_form_gva_psw(env->psw, env->iasq_f, env->iaoq_f & -4)
+ : env->iaoq_f & -4);
+ *cs_base = env->iasq_f;
+
+ /*
+ * Insert a difference between IAOQ_B and IAOQ_F within the otherwise zero
+ * low 32-bits of CS_BASE. This will succeed for all direct branches,
+ * which is the primary case we care about -- using goto_tb within a page.
+ * Failure is indicated by a zero difference.
+ */
+ if (env->iasq_f == env->iasq_b) {
+ target_sreg diff = env->iaoq_b - env->iaoq_f;
+ if (TARGET_REGISTER_BITS == 32 || diff == (int32_t)diff) {
+ *cs_base |= (uint32_t)diff;
+ }
+ }
+ if ((env->sr[4] == env->sr[5])
+ & (env->sr[4] == env->sr[6])
+ & (env->sr[4] == env->sr[7])) {
+ flags |= TB_FLAG_SR_SAME;
+ }
+#endif
+
+ *pflags = flags;
+}
+
static void hppa_cpu_set_pc(CPUState *cs, vaddr value)
{
HPPACPU *cpu = HPPA_CPU(cs);
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 3327ecf6db..7baf74fb9a 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -52,6 +52,15 @@ int cpu_mmu_index(CPUX86State *env, bool ifetch)
? MMU_KNOSMAP_IDX : MMU_KSMAP_IDX;
}
+void cpu_get_tb_cpu_state(CPUX86State *env, vaddr *pc,
+ uint64_t *cs_base, uint32_t *flags)
+{
+ *cs_base = env->segs[R_CS].base;
+ *pc = *cs_base + env->eip;
+ *flags = env->hflags |
+ (env->eflags & (IOPL_MASK | TF_MASK | RF_MASK | VM_MASK | AC_MASK));
+}
+
static void x86_cpu_realizefn(DeviceState *dev, Error **errp);
/* Helpers for building CPUID[2] descriptors: */
diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
index c6c2760e46..cc53a7e51a 100644
--- a/target/loongarch/cpu.c
+++ b/target/loongarch/cpu.c
@@ -32,6 +32,17 @@ int cpu_mmu_index(CPULoongArchState *env, bool ifetch)
#endif
}
+void cpu_get_tb_cpu_state(CPULoongArchState *env, vaddr *pc,
+ uint64_t *cs_base, uint32_t *flags)
+{
+ *pc = env->pc;
+ *cs_base = 0;
+ *flags = env->CSR_CRMD & (R_CSR_CRMD_PLV_MASK | R_CSR_CRMD_PG_MASK);
+ *flags |= FIELD_EX64(env->CSR_EUEN, CSR_EUEN, FPE) * HW_FLAGS_EUEN_FPE;
+ *flags |= FIELD_EX64(env->CSR_EUEN, CSR_EUEN, SXE) * HW_FLAGS_EUEN_SXE;
+ *flags |= is_va32(env) * HW_FLAGS_VA32;
+}
+
const char * const regnames[32] = {
"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
"r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c
index 74da87f07e..9c664cb9a8 100644
--- a/target/m68k/cpu.c
+++ b/target/m68k/cpu.c
@@ -29,6 +29,22 @@ int cpu_mmu_index(CPUM68KState *env, bool ifetch)
return (env->sr & SR_S) == 0 ? 1 : 0;
}
+void cpu_get_tb_cpu_state(CPUM68KState *env, vaddr *pc,
+ uint64_t *cs_base, uint32_t *flags)
+{
+ *pc = env->pc;
+ *cs_base = 0;
+ *flags = (env->macsr >> 4) & TB_FLAGS_MACSR;
+ if (env->sr & SR_S) {
+ *flags |= TB_FLAGS_MSR_S;
+ *flags |= (env->sfc << (TB_FLAGS_SFC_S_BIT - 2)) & TB_FLAGS_SFC_S;
+ *flags |= (env->dfc << (TB_FLAGS_DFC_S_BIT - 2)) & TB_FLAGS_DFC_S;
+ }
+ if (M68K_SR_TRACE(env->sr) == M68K_SR_TRACE_ANY_INS) {
+ *flags |= TB_FLAGS_TRACE;
+ }
+}
+
static void m68k_cpu_set_pc(CPUState *cs, vaddr value)
{
M68kCPU *cpu = M68K_CPU(cs);
diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c
index f8891de41e..4c270e941f 100644
--- a/target/microblaze/cpu.c
+++ b/target/microblaze/cpu.c
@@ -47,6 +47,13 @@ int cpu_mmu_index(CPUMBState *env, bool ifetch)
return MMU_KERNEL_IDX;
}
+void cpu_get_tb_cpu_state(CPUMBState *env, vaddr *pc,
+ uint64_t *cs_base, uint32_t *flags)
+{
+ *pc = env->pc;
+ *flags = (env->iflags & IFLAGS_TB_MASK) | (env->msr & MSR_TB_MASK);
+ *cs_base = (*flags & IMM_FLAG ? env->imm : 0);
+}
static const struct {
const char *name;
diff --git a/target/mips/cpu.c b/target/mips/cpu.c
index 1b5994e9a7..fe93acf28f 100644
--- a/target/mips/cpu.c
+++ b/target/mips/cpu.c
@@ -49,6 +49,15 @@ int cpu_mmu_index(CPUMIPSState *env, bool ifetch)
return hflags_mmu_index(env->hflags);
}
+void cpu_get_tb_cpu_state(CPUMIPSState *env, vaddr *pc,
+ uint64_t *cs_base, uint32_t *flags)
+{
+ *pc = env->active_tc.PC;
+ *cs_base = 0;
+ *flags = env->hflags & (MIPS_HFLAG_TMASK | MIPS_HFLAG_BMASK |
+ MIPS_HFLAG_HWRENA_ULR);
+}
+
const char regnames[32][3] = {
"r0", "at", "v0", "v1", "a0", "a1", "a2", "a3",
"t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c
index 887a9bf786..868d75b165 100644
--- a/target/nios2/cpu.c
+++ b/target/nios2/cpu.c
@@ -32,6 +32,18 @@ int cpu_mmu_index(CPUNios2State *env, bool ifetch)
MMU_SUPERVISOR_IDX;
}
+void cpu_get_tb_cpu_state(CPUNios2State *env, vaddr *pc,
+ uint64_t *cs_base, uint32_t *flags)
+{
+ unsigned crs = FIELD_EX32(env->ctrl[CR_STATUS], CR_STATUS, CRS);
+
+ *pc = env->pc;
+ *cs_base = 0;
+ *flags = (env->ctrl[CR_STATUS] & CR_STATUS_U)
+ | (crs ? 0 : R_TBFLAGS_CRS0_MASK)
+ | (env->regs[0] ? 0 : R_TBFLAGS_R0_0_MASK);
+}
+
static void nios2_cpu_set_pc(CPUState *cs, vaddr value)
{
Nios2CPU *cpu = NIOS2_CPU(cs);
diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c
index 5938d66da3..36d97d249d 100644
--- a/target/openrisc/cpu.c
+++ b/target/openrisc/cpu.c
@@ -37,6 +37,16 @@ int cpu_mmu_index(CPUOpenRISCState *env, bool ifetch)
return ret;
}
+void cpu_get_tb_cpu_state(CPUOpenRISCState *env, vaddr *pc,
+ uint64_t *cs_base, uint32_t *flags)
+{
+ *pc = env->pc;
+ *cs_base = 0;
+ *flags = (env->dflag ? TB_FLAGS_DFLAG : 0)
+ | (cpu_get_gpr(env, 0) ? 0 : TB_FLAGS_R0_0)
+ | (env->sr & (SR_SM | SR_DME | SR_IME | SR_OVE));
+}
+
static void openrisc_cpu_set_pc(CPUState *cs, vaddr value)
{
OpenRISCCPU *cpu = OPENRISC_CPU(cs);
diff --git a/target/ppc/cpu.c b/target/ppc/cpu.c
index 53f1d5c370..046732857b 100644
--- a/target/ppc/cpu.c
+++ b/target/ppc/cpu.c
@@ -36,6 +36,17 @@ int cpu_mmu_index(CPUPPCState *env, bool ifetch)
#endif
}
+/* debug version defined in helper_hregs */
+#ifndef CONFIG_DEBUG_TCG
+void cpu_get_tb_cpu_state(CPUPPCState *env, vaddr *pc,
+ uint64_t *cs_base, uint32_t *flags)
+{
+ *pc = env->nip;
+ *cs_base = 0;
+ *flags = env->hflags;
+}
+#endif
+
target_ulong cpu_read_xer(const CPUPPCState *env)
{
if (is_isa300(env)) {
diff --git a/target/rx/cpu.c b/target/rx/cpu.c
index 1ce1da0a6b..688a70b707 100644
--- a/target/rx/cpu.c
+++ b/target/rx/cpu.c
@@ -31,6 +31,15 @@ int cpu_mmu_index(CPURXState *env, bool ifetch)
return 0;
}
+void cpu_get_tb_cpu_state(CPURXState *env, vaddr *pc,
+ uint64_t *cs_base, uint32_t *flags)
+{
+ *pc = env->pc;
+ *cs_base = 0;
+ *flags = FIELD_DP32(0, PSW, PM, env->psw_pm);
+ *flags = FIELD_DP32(*flags, PSW, U, env->psw_u);
+}
+
static void rx_cpu_set_pc(CPUState *cs, vaddr value)
{
RXCPU *cpu = RX_CPU(cs);
diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c
index aa574807f1..51c707ea12 100644
--- a/target/s390x/cpu.c
+++ b/target/s390x/cpu.c
@@ -72,6 +72,30 @@ int cpu_mmu_index(CPUS390XState *env, bool ifetch)
#endif
}
+void cpu_get_tb_cpu_state(CPUS390XState *env, vaddr *pc,
+ uint64_t *cs_base, uint32_t *flags)
+{
+ if (env->psw.addr & 1) {
+ /*
+ * Instructions must be at even addresses.
+ * This needs to be checked before address translation.
+ */
+ env->int_pgm_ilen = 2; /* see s390_cpu_tlb_fill() */
+#ifdef CONFIG_TCG
+ tcg_s390_program_interrupt(env, PGM_SPECIFICATION, 0);
+#endif
+ }
+ *pc = env->psw.addr;
+ *cs_base = env->ex_value;
+ *flags = (env->psw.mask >> FLAG_MASK_PSW_SHIFT) & FLAG_MASK_PSW;
+ if (env->cregs[0] & CR0_AFP) {
+ *flags |= FLAG_MASK_AFP;
+ }
+ if (env->cregs[0] & CR0_VECTOR) {
+ *flags |= FLAG_MASK_VECTOR;
+ }
+}
+
#ifndef CONFIG_USER_ONLY
static bool is_early_exception_psw(uint64_t mask, uint64_t addr)
{
diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c
index 6bffe52c04..ea7f13612e 100644
--- a/target/sh4/cpu.c
+++ b/target/sh4/cpu.c
@@ -41,6 +41,21 @@ int cpu_mmu_index(CPUSH4State *env, bool ifetch)
}
}
+void cpu_get_tb_cpu_state(CPUSH4State *env, vaddr *pc,
+ uint64_t *cs_base, uint32_t *flags)
+{
+ *pc = env->pc;
+ /* For a gUSA region, notice the end of the region. */
+ *cs_base = env->flags & TB_FLAG_GUSA_MASK ? env->gregs[0] : 0;
+ *flags = env->flags
+ | (env->fpscr & TB_FLAG_FPSCR_MASK)
+ | (env->sr & TB_FLAG_SR_MASK)
+ | (env->movcal_backup ? TB_FLAG_PENDING_MOVCA : 0); /* Bit 3 */
+#ifdef CONFIG_USER_ONLY
+ *flags |= TB_FLAG_UNALIGN * !env_cpu(env)->prctl_unalign_sigbus;
+#endif
+}
+
static void superh_cpu_set_pc(CPUState *cs, vaddr value)
{
SuperHCPU *cpu = SUPERH_CPU(cs);
diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c
index 256ba2be88..a6af3fd9ee 100644
--- a/target/sparc/cpu.c
+++ b/target/sparc/cpu.c
@@ -57,6 +57,41 @@ int cpu_mmu_index(CPUSPARCState *env, bool ifetch)
#endif
}
+void cpu_get_tb_cpu_state(CPUSPARCState *env, vaddr *pc,
+ uint64_t *cs_base, uint32_t *pflags)
+{
+ uint32_t flags;
+ *pc = env->pc;
+ *cs_base = env->npc;
+ flags = cpu_mmu_index(env, false);
+#ifndef CONFIG_USER_ONLY
+ if (cpu_supervisor_mode(env)) {
+ flags |= TB_FLAG_SUPER;
+ }
+#endif
+#ifdef TARGET_SPARC64
+#ifndef CONFIG_USER_ONLY
+ if (cpu_hypervisor_mode(env)) {
+ flags |= TB_FLAG_HYPER;
+ }
+#endif
+ if (env->pstate & PS_AM) {
+ flags |= TB_FLAG_AM_ENABLED;
+ }
+ if ((env->def.features & CPU_FEATURE_FLOAT)
+ && (env->pstate & PS_PEF)
+ && (env->fprs & FPRS_FEF)) {
+ flags |= TB_FLAG_FPU_ENABLED;
+ }
+ flags |= env->asi << TB_FLAG_ASI_SHIFT;
+#else
+ if ((env->def.features & CPU_FEATURE_FLOAT) && env->psref) {
+ flags |= TB_FLAG_FPU_ENABLED;
+ }
+#endif
+ *pflags = flags;
+}
+
static void sparc_cpu_reset_hold(Object *obj)
{
CPUState *s = CPU(obj);
diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c
index a81f37e3e4..f8bf10569a 100644
--- a/target/tricore/cpu.c
+++ b/target/tricore/cpu.c
@@ -29,6 +29,18 @@ int cpu_mmu_index(CPUTriCoreState *env, bool ifetch)
return 0;
}
+void cpu_get_tb_cpu_state(CPUTriCoreState *env, vaddr *pc,
+ uint64_t *cs_base, uint32_t *flags)
+{
+ uint32_t new_flags = 0;
+ *pc = env->PC;
+ *cs_base = 0;
+
+ new_flags |= FIELD_DP32(new_flags, TB_FLAGS, PRIV,
+ extract32(env->PSW, 10, 2));
+ *flags = new_flags;
+}
+
static inline void set_feature(CPUTriCoreState *env, int feature)
{
env->features |= 1ULL << feature;
diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c
index 769b3c9305..2c76ba86cd 100644
--- a/target/xtensa/cpu.c
+++ b/target/xtensa/cpu.c
@@ -44,6 +44,74 @@ int cpu_mmu_index(CPUXtensaState *env, bool ifetch)
return xtensa_get_cring(env);
}
+void cpu_get_tb_cpu_state(CPUXtensaState *env, vaddr *pc,
+ uint64_t *cs_base, uint32_t *flags)
+{
+ *pc = env->pc;
+ *cs_base = 0;
+ *flags = 0;
+ *flags |= xtensa_get_ring(env);
+ if (env->sregs[PS] & PS_EXCM) {
+ *flags |= XTENSA_TBFLAG_EXCM;
+ } else if (xtensa_option_enabled(env->config, XTENSA_OPTION_LOOP)) {
+ target_ulong lend_dist =
+ env->sregs[LEND] - (env->pc & -(1u << TARGET_PAGE_BITS));
+
+ /*
+ * 0 in the csbase_lend field means that there may not be a loopback
+ * for any instruction that starts inside this page. Any other value
+ * means that an instruction that ends at this offset from the page
+ * start may loop back and will need loopback code to be generated.
+ *
+ * lend_dist is 0 when LEND points to the start of the page, but
+ * no instruction that starts inside this page may end at offset 0,
+ * so it's still correct.
+ *
+ * When an instruction ends at a page boundary it may only start in
+ * the previous page. lend_dist will be encoded as TARGET_PAGE_SIZE
+ * for the TB that contains this instruction.
+ */
+ if (lend_dist < (1u << TARGET_PAGE_BITS) + env->config->max_insn_size) {
+ target_ulong lbeg_off = env->sregs[LEND] - env->sregs[LBEG];
+
+ *cs_base = lend_dist;
+ if (lbeg_off < 256) {
+ *cs_base |= lbeg_off << XTENSA_CSBASE_LBEG_OFF_SHIFT;
+ }
+ }
+ }
+ if (xtensa_option_enabled(env->config, XTENSA_OPTION_EXTENDED_L32R) &&
+ (env->sregs[LITBASE] & 1)) {
+ *flags |= XTENSA_TBFLAG_LITBASE;
+ }
+ if (xtensa_option_enabled(env->config, XTENSA_OPTION_DEBUG)) {
+ if (xtensa_get_cintlevel(env) < env->config->debug_level) {
+ *flags |= XTENSA_TBFLAG_DEBUG;
+ }
+ if (xtensa_get_cintlevel(env) < env->sregs[ICOUNTLEVEL]) {
+ *flags |= XTENSA_TBFLAG_ICOUNT;
+ }
+ }
+ if (xtensa_option_enabled(env->config, XTENSA_OPTION_COPROCESSOR)) {
+ *flags |= env->sregs[CPENABLE] << XTENSA_TBFLAG_CPENABLE_SHIFT;
+ }
+ if (xtensa_option_enabled(env->config, XTENSA_OPTION_WINDOWED_REGISTER) &&
+ (env->sregs[PS] & (PS_WOE | PS_EXCM)) == PS_WOE) {
+ uint32_t windowstart = xtensa_replicate_windowstart(env) >>
+ (env->sregs[WINDOW_BASE] + 1);
+ uint32_t w = ctz32(windowstart | 0x8);
+
+ *flags |= (w << XTENSA_TBFLAG_WINDOW_SHIFT) | XTENSA_TBFLAG_CWOE;
+ *flags |= extract32(env->sregs[PS], PS_CALLINC_SHIFT,
+ PS_CALLINC_LEN) << XTENSA_TBFLAG_CALLINC_SHIFT;
+ } else {
+ *flags |= 3 << XTENSA_TBFLAG_WINDOW_SHIFT;
+ }
+ if (env->yield_needed) {
+ *flags |= XTENSA_TBFLAG_YIELD;
+ }
+}
+
static void xtensa_cpu_set_pc(CPUState *cs, vaddr value)
{
XtensaCPU *cpu = XTENSA_CPU(cs);
--
2.43.0
^ permalink raw reply related [flat|nested] 83+ messages in thread
* [RFC PATCH 14/34] exec: [CPUTLB] Move PAGE_* macros to common header
2024-01-19 14:39 [RFC PATCH 00/34] Compile accel/tcg once (partially) Anton Johansson via
` (12 preceding siblings ...)
2024-01-19 14:40 ` [RFC PATCH 13/34] target: Uninline cpu_get_tb_cpu_state() Anton Johansson via
@ 2024-01-19 14:40 ` Anton Johansson via
2024-01-23 23:54 ` Richard Henderson
2024-01-19 14:40 ` [RFC PATCH 15/34] exec: [CPUTLB] Move TLB_*/tlb_*() " Anton Johansson via
` (19 subsequent siblings)
33 siblings, 1 reply; 83+ messages in thread
From: Anton Johansson via @ 2024-01-19 14:40 UTC (permalink / raw)
To: qemu-devel; +Cc: ale, richard.henderson, philmd
These don't vary across targets and are used in soon-to-be common code
(cputlb.c).
Signed-off-by: Anton Johansson <anjo@rev.ng>
---
include/exec/cpu-all.h | 24 ------------------------
include/exec/cpu-common.h | 30 ++++++++++++++++++++++++++++++
2 files changed, 30 insertions(+), 24 deletions(-)
diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h
index 483e762f05..219544bad8 100644
--- a/include/exec/cpu-all.h
+++ b/include/exec/cpu-all.h
@@ -166,34 +166,10 @@ static inline void stl_phys_notdirty(AddressSpace *as, hwaddr addr, uint32_t val
# error Need to use TARGET_PAGE_BITS_VARY on system mode
#endif
-/* same as PROT_xxx */
-#define PAGE_READ 0x0001
-#define PAGE_WRITE 0x0002
-#define PAGE_EXEC 0x0004
-#define PAGE_BITS (PAGE_READ | PAGE_WRITE | PAGE_EXEC)
-#define PAGE_VALID 0x0008
-/*
- * Original state of the write flag (used when tracking self-modifying code)
- */
-#define PAGE_WRITE_ORG 0x0010
-/*
- * Invalidate the TLB entry immediately, helpful for s390x
- * Low-Address-Protection. Used with PAGE_WRITE in tlb_set_page_with_attrs()
- */
-#define PAGE_WRITE_INV 0x0020
-/* For use with page_set_flags: page is being replaced; target_data cleared. */
-#define PAGE_RESET 0x0040
-/* For linux-user, indicates that the page is MAP_ANON. */
-#define PAGE_ANON 0x0080
-
#if defined(CONFIG_BSD) && defined(CONFIG_USER_ONLY)
/* FIXME: Code that sets/uses this is broken and needs to go away. */
#define PAGE_RESERVED 0x0100
#endif
-/* Target-specific bits that will be used via page_get_flags(). */
-#define PAGE_TARGET_1 0x0200
-#define PAGE_TARGET_2 0x0400
-
/*
* For linux-user, indicates that the page is mapped with the same semantics
* in both guest and host.
diff --git a/include/exec/cpu-common.h b/include/exec/cpu-common.h
index b5dae4a9d6..63bc0ad150 100644
--- a/include/exec/cpu-common.h
+++ b/include/exec/cpu-common.h
@@ -234,4 +234,34 @@ G_NORETURN void cpu_loop_exit_atomic(CPUState *cpu, uintptr_t pc);
G_NORETURN void cpu_loop_exit(CPUState *cpu);
G_NORETURN void cpu_loop_exit_restore(CPUState *cpu, uintptr_t pc);
+/* same as PROT_xxx */
+#define PAGE_READ 0x0001
+#define PAGE_WRITE 0x0002
+#define PAGE_EXEC 0x0004
+#define PAGE_BITS (PAGE_READ | PAGE_WRITE | PAGE_EXEC)
+#define PAGE_VALID 0x0008
+/*
+ * Original state of the write flag (used when tracking self-modifying code)
+ */
+#define PAGE_WRITE_ORG 0x0010
+/*
+ * Invalidate the TLB entry immediately, helpful for s390x
+ * Low-Address-Protection. Used with PAGE_WRITE in tlb_set_page_with_attrs()
+ */
+#define PAGE_WRITE_INV 0x0020
+/* For use with page_set_flags: page is being replaced; target_data cleared. */
+#define PAGE_RESET 0x0040
+/* For linux-user, indicates that the page is MAP_ANON. */
+#define PAGE_ANON 0x0080
+
+/* Target-specific bits that will be used via page_get_flags(). */
+#define PAGE_TARGET_1 0x0200
+#define PAGE_TARGET_2 0x0400
+
+/*
+ * For linux-user, indicates that the page is mapped with the same semantics
+ * in both guest and host.
+ */
+#define PAGE_PASSTHROUGH 0x0800
+
#endif /* CPU_COMMON_H */
--
2.43.0
^ permalink raw reply related [flat|nested] 83+ messages in thread
* [RFC PATCH 15/34] exec: [CPUTLB] Move TLB_*/tlb_*() to common header
2024-01-19 14:39 [RFC PATCH 00/34] Compile accel/tcg once (partially) Anton Johansson via
` (13 preceding siblings ...)
2024-01-19 14:40 ` [RFC PATCH 14/34] exec: [CPUTLB] Move PAGE_* macros to common header Anton Johansson via
@ 2024-01-19 14:40 ` Anton Johansson via
2024-01-24 0:09 ` Richard Henderson
2024-01-19 14:40 ` [RFC PATCH 16/34] exec: [CPUTLB] Move cpu_*()/cpu_env() " Anton Johansson via
` (18 subsequent siblings)
33 siblings, 1 reply; 83+ messages in thread
From: Anton Johansson via @ 2024-01-19 14:40 UTC (permalink / raw)
To: qemu-devel; +Cc: ale, richard.henderson, philmd
TLB_* macros and tlb_*() functions are target independent, move to cpu-common.h.
Signed-off-by: Anton Johansson <anjo@rev.ng>
---
include/exec/cpu-all.h | 81 --------------------------------------
include/exec/cpu-common.h | 83 +++++++++++++++++++++++++++++++++++++++
2 files changed, 83 insertions(+), 81 deletions(-)
diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h
index 219544bad8..968fbd4d16 100644
--- a/include/exec/cpu-all.h
+++ b/include/exec/cpu-all.h
@@ -295,87 +295,6 @@ CPUArchState *cpu_copy(CPUArchState *env);
| CPU_INTERRUPT_TGT_EXT_3 \
| CPU_INTERRUPT_TGT_EXT_4)
-#ifdef CONFIG_USER_ONLY
-
-/*
- * Allow some level of source compatibility with softmmu. We do not
- * support any of the more exotic features, so only invalid pages may
- * be signaled by probe_access_flags().
- */
-#define TLB_INVALID_MASK (1 << (TARGET_PAGE_BITS_MIN - 1))
-#define TLB_MMIO (1 << (TARGET_PAGE_BITS_MIN - 2))
-#define TLB_WATCHPOINT 0
-
-#else
-
-/*
- * Flags stored in the low bits of the TLB virtual address.
- * These are defined so that fast path ram access is all zeros.
- * The flags all must be between TARGET_PAGE_BITS and
- * maximum address alignment bit.
- *
- * Use TARGET_PAGE_BITS_MIN so that these bits are constant
- * when TARGET_PAGE_BITS_VARY is in effect.
- *
- * The count, if not the placement of these bits is known
- * to tcg/tcg-op-ldst.c, check_max_alignment().
- */
-/* Zero if TLB entry is valid. */
-#define TLB_INVALID_MASK (1 << (TARGET_PAGE_BITS_MIN - 1))
-/* Set if TLB entry references a clean RAM page. The iotlb entry will
- contain the page physical address. */
-#define TLB_NOTDIRTY (1 << (TARGET_PAGE_BITS_MIN - 2))
-/* Set if TLB entry is an IO callback. */
-#define TLB_MMIO (1 << (TARGET_PAGE_BITS_MIN - 3))
-/* Set if TLB entry writes ignored. */
-#define TLB_DISCARD_WRITE (1 << (TARGET_PAGE_BITS_MIN - 4))
-/* Set if the slow path must be used; more flags in CPUTLBEntryFull. */
-#define TLB_FORCE_SLOW (1 << (TARGET_PAGE_BITS_MIN - 5))
-
-/*
- * Use this mask to check interception with an alignment mask
- * in a TCG backend.
- */
-#define TLB_FLAGS_MASK \
- (TLB_INVALID_MASK | TLB_NOTDIRTY | TLB_MMIO \
- | TLB_FORCE_SLOW | TLB_DISCARD_WRITE)
-
-/*
- * Flags stored in CPUTLBEntryFull.slow_flags[x].
- * TLB_FORCE_SLOW must be set in CPUTLBEntry.addr_idx[x].
- */
-/* Set if TLB entry requires byte swap. */
-#define TLB_BSWAP (1 << 0)
-/* Set if TLB entry contains a watchpoint. */
-#define TLB_WATCHPOINT (1 << 1)
-
-#define TLB_SLOW_FLAGS_MASK (TLB_BSWAP | TLB_WATCHPOINT)
-
-/**
- * tlb_hit_page: return true if page aligned @addr is a hit against the
- * TLB entry @tlb_addr
- *
- * @addr: virtual address to test (must be page aligned)
- * @tlb_addr: TLB entry address (a CPUTLBEntry addr_read/write/code value)
- */
-static inline bool tlb_hit_page(uint64_t tlb_addr, vaddr addr)
-{
- return addr == (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK));
-}
-
-/**
- * tlb_hit: return true if @addr is a hit against the TLB entry @tlb_addr
- *
- * @addr: virtual address to test (need not be page aligned)
- * @tlb_addr: TLB entry address (a CPUTLBEntry addr_read/write/code value)
- */
-static inline bool tlb_hit(uint64_t tlb_addr, vaddr addr)
-{
- return tlb_hit_page(tlb_addr, addr & TARGET_PAGE_MASK);
-}
-
-#endif /* !CONFIG_USER_ONLY */
-
/* accel/tcg/cpu-exec.c */
int cpu_exec(CPUState *cpu);
diff --git a/include/exec/cpu-common.h b/include/exec/cpu-common.h
index 63bc0ad150..d3c8b2cf55 100644
--- a/include/exec/cpu-common.h
+++ b/include/exec/cpu-common.h
@@ -41,6 +41,89 @@ extern const TargetPageBits target_page;
#define TARGET_PAGE_ALIGN(addr) ROUND_UP((addr), TARGET_PAGE_SIZE)
#endif
+#ifdef CONFIG_USER_ONLY
+
+/*
+ * Allow some level of source compatibility with softmmu. We do not
+ * support any of the more exotic features, so only invalid pages may
+ * be signaled by probe_access_flags().
+ */
+#define TLB_INVALID_MASK (1 << (TARGET_PAGE_BITS_MIN - 1))
+#define TLB_MMIO (1 << (TARGET_PAGE_BITS_MIN - 2))
+#define TLB_WATCHPOINT 0
+
+#else
+
+/*
+ * Flags stored in the low bits of the TLB virtual address.
+ * These are defined so that fast path ram access is all zeros.
+ * The flags all must be between TARGET_PAGE_BITS and
+ * maximum address alignment bit.
+ *
+ * Use TARGET_PAGE_BITS_MIN so that these bits are constant
+ * when TARGET_PAGE_BITS_VARY is in effect.
+ *
+ * The count, if not the placement of these bits is known
+ * to tcg/tcg-op-ldst.c, check_max_alignment().
+ */
+/* Zero if TLB entry is valid. */
+#define TLB_INVALID_MASK (1 << (TARGET_PAGE_BITS_MIN - 1))
+/*
+ * Set if TLB entry references a clean RAM page. The iotlb entry will
+ * contain the page physical address.
+ */
+#define TLB_NOTDIRTY (1 << (TARGET_PAGE_BITS_MIN - 2))
+/* Set if TLB entry is an IO callback. */
+#define TLB_MMIO (1 << (TARGET_PAGE_BITS_MIN - 3))
+/* Set if TLB entry writes ignored. */
+#define TLB_DISCARD_WRITE (1 << (TARGET_PAGE_BITS_MIN - 4))
+/* Set if the slow path must be used; more flags in CPUTLBEntryFull. */
+#define TLB_FORCE_SLOW (1 << (TARGET_PAGE_BITS_MIN - 5))
+
+/*
+ * Use this mask to check interception with an alignment mask
+ * in a TCG backend.
+ */
+#define TLB_FLAGS_MASK \
+ (TLB_INVALID_MASK | TLB_NOTDIRTY | TLB_MMIO \
+ | TLB_FORCE_SLOW | TLB_DISCARD_WRITE)
+
+/*
+ * Flags stored in CPUTLBEntryFull.slow_flags[x].
+ * TLB_FORCE_SLOW must be set in CPUTLBEntry.addr_idx[x].
+ */
+/* Set if TLB entry requires byte swap. */
+#define TLB_BSWAP (1 << 0)
+/* Set if TLB entry contains a watchpoint. */
+#define TLB_WATCHPOINT (1 << 1)
+
+#define TLB_SLOW_FLAGS_MASK (TLB_BSWAP | TLB_WATCHPOINT)
+
+/**
+ * tlb_hit_page: return true if page aligned @addr is a hit against the
+ * TLB entry @tlb_addr
+ *
+ * @addr: virtual address to test (must be page aligned)
+ * @tlb_addr: TLB entry address (a CPUTLBEntry addr_read/write/code value)
+ */
+static inline bool tlb_hit_page(uint64_t tlb_addr, vaddr addr)
+{
+ return addr == (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK));
+}
+
+/**
+ * tlb_hit: return true if @addr is a hit against the TLB entry @tlb_addr
+ *
+ * @addr: virtual address to test (need not be page aligned)
+ * @tlb_addr: TLB entry address (a CPUTLBEntry addr_read/write/code value)
+ */
+static inline bool tlb_hit(uint64_t tlb_addr, vaddr addr)
+{
+ return tlb_hit_page(tlb_addr, addr & TARGET_PAGE_MASK);
+}
+
+#endif /* !CONFIG_USER_ONLY */
+
void cpu_exec_init_all(void);
void cpu_exec_step_atomic(CPUState *cpu);
--
2.43.0
^ permalink raw reply related [flat|nested] 83+ messages in thread
* [RFC PATCH 16/34] exec: [CPUTLB] Move cpu_*()/cpu_env() to common header
2024-01-19 14:39 [RFC PATCH 00/34] Compile accel/tcg once (partially) Anton Johansson via
` (14 preceding siblings ...)
2024-01-19 14:40 ` [RFC PATCH 15/34] exec: [CPUTLB] Move TLB_*/tlb_*() " Anton Johansson via
@ 2024-01-19 14:40 ` Anton Johansson via
2024-01-24 0:15 ` Richard Henderson
2024-01-27 22:14 ` Richard Henderson
2024-01-19 14:40 ` [RFC PATCH 17/34] hw/core: [CPUTLB] Move target specifics to end of TCGCPUOps Anton Johansson via
` (17 subsequent siblings)
33 siblings, 2 replies; 83+ messages in thread
From: Anton Johansson via @ 2024-01-19 14:40 UTC (permalink / raw)
To: qemu-devel; +Cc: ale, richard.henderson, philmd
Functions are target independent.
Signed-off-by: Anton Johansson <anjo@rev.ng>
---
include/exec/cpu-all.h | 25 -------------------------
include/exec/cpu-common.h | 25 +++++++++++++++++++++++++
2 files changed, 25 insertions(+), 25 deletions(-)
diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h
index 968fbd4d16..4778976c4b 100644
--- a/include/exec/cpu-all.h
+++ b/include/exec/cpu-all.h
@@ -295,33 +295,8 @@ CPUArchState *cpu_copy(CPUArchState *env);
| CPU_INTERRUPT_TGT_EXT_3 \
| CPU_INTERRUPT_TGT_EXT_4)
-/* accel/tcg/cpu-exec.c */
-int cpu_exec(CPUState *cpu);
-
/* Validate correct placement of CPUArchState. */
QEMU_BUILD_BUG_ON(offsetof(ArchCPU, parent_obj) != 0);
QEMU_BUILD_BUG_ON(offsetof(ArchCPU, env) != sizeof(CPUState));
-/**
- * env_archcpu(env)
- * @env: The architecture environment
- *
- * Return the ArchCPU associated with the environment.
- */
-static inline ArchCPU *env_archcpu(CPUArchState *env)
-{
- return (void *)env - sizeof(CPUState);
-}
-
-/**
- * env_cpu(env)
- * @env: The architecture environment
- *
- * Return the CPUState associated with the environment.
- */
-static inline CPUState *env_cpu(CPUArchState *env)
-{
- return (void *)env - sizeof(CPUState);
-}
-
#endif /* CPU_ALL_H */
diff --git a/include/exec/cpu-common.h b/include/exec/cpu-common.h
index d3c8b2cf55..25e50aaa37 100644
--- a/include/exec/cpu-common.h
+++ b/include/exec/cpu-common.h
@@ -347,4 +347,29 @@ G_NORETURN void cpu_loop_exit_restore(CPUState *cpu, uintptr_t pc);
*/
#define PAGE_PASSTHROUGH 0x0800
+/* accel/tcg/cpu-exec.c */
+int cpu_exec(CPUState *cpu);
+
+/**
+ * env_archcpu(env)
+ * @env: The architecture environment
+ *
+ * Return the ArchCPU associated with the environment.
+ */
+static inline ArchCPU *env_archcpu(CPUArchState *env)
+{
+ return (void *)env - sizeof(CPUState);
+}
+
+/**
+ * env_cpu(env)
+ * @env: The architecture environment
+ *
+ * Return the CPUState associated with the environment.
+ */
+static inline CPUState *env_cpu(CPUArchState *env)
+{
+ return (void *)env - sizeof(CPUState);
+}
+
#endif /* CPU_COMMON_H */
--
2.43.0
^ permalink raw reply related [flat|nested] 83+ messages in thread
* [RFC PATCH 17/34] hw/core: [CPUTLB] Move target specifics to end of TCGCPUOps
2024-01-19 14:39 [RFC PATCH 00/34] Compile accel/tcg once (partially) Anton Johansson via
` (15 preceding siblings ...)
2024-01-19 14:40 ` [RFC PATCH 16/34] exec: [CPUTLB] Move cpu_*()/cpu_env() " Anton Johansson via
@ 2024-01-19 14:40 ` Anton Johansson via
2024-01-24 0:43 ` Richard Henderson
2024-01-19 14:40 ` [RFC PATCH 18/34] accel/stubs: [CPUTLB] Move xen.h stubs to xen-stub.c Anton Johansson via
` (16 subsequent siblings)
33 siblings, 1 reply; 83+ messages in thread
From: Anton Johansson via @ 2024-01-19 14:40 UTC (permalink / raw)
To: qemu-devel; +Cc: ale, richard.henderson, philmd
TCGCPUOps contains an extra function pointer when included with
NEED_CPU_H, these are moved from the middle to the end of the struct. As
such offsets to target independent function pointers don't vary in
target specific and independent code.
[Move target specfic fields to separate struct?]
Signed-off-by: Anton Johansson <anjo@rev.ng>
---
include/hw/core/tcg-cpu-ops.h | 32 +++++++++++++++++---------------
1 file changed, 17 insertions(+), 15 deletions(-)
diff --git a/include/hw/core/tcg-cpu-ops.h b/include/hw/core/tcg-cpu-ops.h
index 479713a36e..feb849051f 100644
--- a/include/hw/core/tcg-cpu-ops.h
+++ b/include/hw/core/tcg-cpu-ops.h
@@ -49,21 +49,6 @@ struct TCGCPUOps {
/** @debug_excp_handler: Callback for handling debug exceptions */
void (*debug_excp_handler)(CPUState *cpu);
-#ifdef NEED_CPU_H
-#if defined(CONFIG_USER_ONLY) && defined(TARGET_I386)
- /**
- * @fake_user_interrupt: Callback for 'fake exception' handling.
- *
- * Simulate 'fake exception' which will be handled outside the
- * cpu execution loop (hack for x86 user mode).
- */
- void (*fake_user_interrupt)(CPUState *cpu);
-#else
- /**
- * @do_interrupt: Callback for interrupt handling.
- */
- void (*do_interrupt)(CPUState *cpu);
-#endif /* !CONFIG_USER_ONLY || !TARGET_I386 */
#ifdef CONFIG_USER_ONLY
/**
* record_sigsegv:
@@ -171,8 +156,25 @@ struct TCGCPUOps {
bool (*io_recompile_replay_branch)(CPUState *cpu,
const TranslationBlock *tb);
#endif /* !CONFIG_USER_ONLY */
+
+#ifdef NEED_CPU_H
+#if defined(CONFIG_USER_ONLY) && defined(TARGET_I386)
+ /**
+ * @fake_user_interrupt: Callback for 'fake exception' handling.
+ *
+ * Simulate 'fake exception' which will be handled outside the
+ * cpu execution loop (hack for x86 user mode).
+ */
+ void (*fake_user_interrupt)(CPUState *cpu);
+#else
+ /**
+ * @do_interrupt: Callback for interrupt handling.
+ */
+ void (*do_interrupt)(CPUState *cpu);
+#endif /* !CONFIG_USER_ONLY || !TARGET_I386 */
#endif /* NEED_CPU_H */
+
};
#if defined(CONFIG_USER_ONLY)
--
2.43.0
^ permalink raw reply related [flat|nested] 83+ messages in thread
* [RFC PATCH 18/34] accel/stubs: [CPUTLB] Move xen.h stubs to xen-stub.c
2024-01-19 14:39 [RFC PATCH 00/34] Compile accel/tcg once (partially) Anton Johansson via
` (16 preceding siblings ...)
2024-01-19 14:40 ` [RFC PATCH 17/34] hw/core: [CPUTLB] Move target specifics to end of TCGCPUOps Anton Johansson via
@ 2024-01-19 14:40 ` Anton Johansson via
2024-01-24 1:04 ` Richard Henderson
2024-01-19 14:40 ` [RFC PATCH 19/34] accel/tcg: [CPUTLB] Use TCGContext.addr_type instead of TARGET_LONG_BITS Anton Johansson via
` (15 subsequent siblings)
33 siblings, 1 reply; 83+ messages in thread
From: Anton Johansson via @ 2024-01-19 14:40 UTC (permalink / raw)
To: qemu-devel; +Cc: ale, richard.henderson, philmd
Makes xen.h header independent of softmmu target. Note:
CONFIG_XEN_IS_POSSIBLE is only used define stubs in xen.h and optimize
xen_enabled().
Required by cpu_physical_memory_set_dirty_range() in ram_addr.h.
Signed-off-by: Anton Johansson <anjo@rev.ng>
---
include/sysemu/xen.h | 27 ---------------------------
accel/stubs/xen-stub.c | 12 ++++++++++++
2 files changed, 12 insertions(+), 27 deletions(-)
diff --git a/include/sysemu/xen.h b/include/sysemu/xen.h
index bc13ad5692..838bb5a003 100644
--- a/include/sysemu/xen.h
+++ b/include/sysemu/xen.h
@@ -12,16 +12,6 @@
#include "exec/cpu-common.h"
-#ifdef NEED_CPU_H
-# ifdef CONFIG_XEN
-# define CONFIG_XEN_IS_POSSIBLE
-# endif
-#else
-# define CONFIG_XEN_IS_POSSIBLE
-#endif
-
-#ifdef CONFIG_XEN_IS_POSSIBLE
-
extern bool xen_allowed;
#define xen_enabled() (xen_allowed)
@@ -32,21 +22,4 @@ void xen_ram_alloc(ram_addr_t ram_addr, ram_addr_t size,
struct MemoryRegion *mr, Error **errp);
#endif
-#else /* !CONFIG_XEN_IS_POSSIBLE */
-
-#define xen_enabled() 0
-#ifndef CONFIG_USER_ONLY
-static inline void xen_hvm_modified_memory(ram_addr_t start, ram_addr_t length)
-{
- /* nothing */
-}
-static inline void xen_ram_alloc(ram_addr_t ram_addr, ram_addr_t size,
- MemoryRegion *mr, Error **errp)
-{
- g_assert_not_reached();
-}
-#endif
-
-#endif /* CONFIG_XEN_IS_POSSIBLE */
-
#endif
diff --git a/accel/stubs/xen-stub.c b/accel/stubs/xen-stub.c
index 7054965c48..73cfa2d291 100644
--- a/accel/stubs/xen-stub.c
+++ b/accel/stubs/xen-stub.c
@@ -14,3 +14,15 @@ bool xen_allowed;
void qmp_xen_set_global_dirty_log(bool enable, Error **errp)
{
}
+
+#ifndef CONFIG_USER_ONLY
+void xen_hvm_modified_memory(ram_addr_t start, ram_addr_t length)
+{
+ /* nothing */
+}
+void xen_ram_alloc(ram_addr_t ram_addr, ram_addr_t size,
+ MemoryRegion *mr, Error **errp)
+{
+ g_assert_not_reached();
+}
+#endif
--
2.43.0
^ permalink raw reply related [flat|nested] 83+ messages in thread
* [RFC PATCH 19/34] accel/tcg: [CPUTLB] Use TCGContext.addr_type instead of TARGET_LONG_BITS
2024-01-19 14:39 [RFC PATCH 00/34] Compile accel/tcg once (partially) Anton Johansson via
` (17 preceding siblings ...)
2024-01-19 14:40 ` [RFC PATCH 18/34] accel/stubs: [CPUTLB] Move xen.h stubs to xen-stub.c Anton Johansson via
@ 2024-01-19 14:40 ` Anton Johansson via
2024-01-24 1:18 ` Richard Henderson
2024-01-19 14:40 ` [RFC PATCH 20/34] accel/tcg: [CPUTLB] Use TCGContext.guest_mo for memory ordering Anton Johansson via
` (14 subsequent siblings)
33 siblings, 1 reply; 83+ messages in thread
From: Anton Johansson via @ 2024-01-19 14:40 UTC (permalink / raw)
To: qemu-devel; +Cc: ale, richard.henderson, philmd
[NOTE: We could also use target_long_bits(), which is introduced later]
Signed-off-by: Anton Johansson <anjo@rev.ng>
---
include/exec/cpu_ldst.h | 31 ++++++++++++++++---------------
accel/tcg/cputlb.c | 34 ++++++++++++++++++++--------------
2 files changed, 36 insertions(+), 29 deletions(-)
diff --git a/include/exec/cpu_ldst.h b/include/exec/cpu_ldst.h
index 24fe322d72..553e0119f9 100644
--- a/include/exec/cpu_ldst.h
+++ b/include/exec/cpu_ldst.h
@@ -340,7 +340,7 @@ static inline void clear_helper_retaddr(void)
#else
-#include "tcg/oversized-guest.h"
+#include "tcg-target-reg-bits.h"
static inline uint64_t tlb_read_idx(const CPUTLBEntry *entry,
MMUAccessType access_type)
@@ -353,20 +353,21 @@ static inline uint64_t tlb_read_idx(const CPUTLBEntry *entry,
QEMU_BUILD_BUG_ON(offsetof(CPUTLBEntry, addr_code) !=
MMU_INST_FETCH * sizeof(uint64_t));
-#if TARGET_LONG_BITS == 32
- /* Use qatomic_read, in case of addr_write; only care about low bits. */
- const uint32_t *ptr = (uint32_t *)&entry->addr_idx[access_type];
- ptr += HOST_BIG_ENDIAN;
- return qatomic_read(ptr);
-#else
- const uint64_t *ptr = &entry->addr_idx[access_type];
-# if TCG_OVERSIZED_GUEST
- return *ptr;
-# else
- /* ofs might correspond to .addr_write, so use qatomic_read */
- return qatomic_read(ptr);
-# endif
-#endif
+ if (tcg_ctx->addr_type == TCG_TYPE_I32) {
+ /* Use qatomic_read, in case of addr_write; only care about low bits. */
+ const uint32_t *ptr = (uint32_t *)&entry->addr_idx[access_type];
+ ptr += HOST_BIG_ENDIAN;
+ return qatomic_read(ptr);
+ } else {
+ const uint64_t *ptr = &entry->addr_idx[access_type];
+ if (TCG_TARGET_REG_BITS == 32) {
+ /* Oversized guest */
+ return *ptr;
+ } else {
+ /* ofs might correspond to .addr_write, so use qatomic_read */
+ return qatomic_read(ptr);
+ }
+ }
}
static inline uint64_t tlb_addr_write(const CPUTLBEntry *entry)
diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
index 449c86301e..967d5da6d4 100644
--- a/accel/tcg/cputlb.c
+++ b/accel/tcg/cputlb.c
@@ -41,7 +41,7 @@
#include "qemu/plugin-memory.h"
#endif
#include "tcg/tcg-ldst.h"
-#include "tcg/oversized-guest.h"
+#include "tcg-target-reg-bits.h"
/* DEBUG defines, enable DEBUG_TLB_LOG to log to the CPU_LOG_MMU target */
/* #define DEBUG_TLB */
@@ -815,12 +815,13 @@ void tlb_flush_range_by_mmuidx(CPUState *cpu, vaddr addr,
unsigned bits)
{
TLBFlushRangeData d;
+ const unsigned long_bits = (tcg_ctx->addr_type == TCG_TYPE_I32) ? 32 : 64;
/*
* If all bits are significant, and len is small,
* this devolves to tlb_flush_page.
*/
- if (bits >= TARGET_LONG_BITS && len <= TARGET_PAGE_SIZE) {
+ if (bits >= long_bits && len <= TARGET_PAGE_SIZE) {
tlb_flush_page_by_mmuidx(cpu, addr, idxmap);
return;
}
@@ -858,12 +859,13 @@ void tlb_flush_range_by_mmuidx_all_cpus(CPUState *src_cpu,
{
TLBFlushRangeData d;
CPUState *dst_cpu;
+ const unsigned long_bits = (tcg_ctx->addr_type == TCG_TYPE_I32) ? 32 : 64;
/*
* If all bits are significant, and len is small,
* this devolves to tlb_flush_page.
*/
- if (bits >= TARGET_LONG_BITS && len <= TARGET_PAGE_SIZE) {
+ if (bits >= long_bits && len <= TARGET_PAGE_SIZE) {
tlb_flush_page_by_mmuidx_all_cpus(src_cpu, addr, idxmap);
return;
}
@@ -908,12 +910,13 @@ void tlb_flush_range_by_mmuidx_all_cpus_synced(CPUState *src_cpu,
{
TLBFlushRangeData d, *p;
CPUState *dst_cpu;
+ const unsigned long_bits = (tcg_ctx->addr_type == TCG_TYPE_I32) ? 32 : 64;
/*
* If all bits are significant, and len is small,
* this devolves to tlb_flush_page.
*/
- if (bits >= TARGET_LONG_BITS && len <= TARGET_PAGE_SIZE) {
+ if (bits >= long_bits && len <= TARGET_PAGE_SIZE) {
tlb_flush_page_by_mmuidx_all_cpus_synced(src_cpu, addr, idxmap);
return;
}
@@ -995,16 +998,19 @@ static void tlb_reset_dirty_range_locked(CPUTLBEntry *tlb_entry,
addr &= TARGET_PAGE_MASK;
addr += tlb_entry->addend;
if ((addr - start) < length) {
-#if TARGET_LONG_BITS == 32
- uint32_t *ptr_write = (uint32_t *)&tlb_entry->addr_write;
- ptr_write += HOST_BIG_ENDIAN;
- qatomic_set(ptr_write, *ptr_write | TLB_NOTDIRTY);
-#elif TCG_OVERSIZED_GUEST
- tlb_entry->addr_write |= TLB_NOTDIRTY;
-#else
- qatomic_set(&tlb_entry->addr_write,
- tlb_entry->addr_write | TLB_NOTDIRTY);
-#endif
+ if (tcg_ctx->addr_type == TCG_TYPE_I32) {
+ /* 32-bit */
+ uint32_t *ptr_write = (uint32_t *)&tlb_entry->addr_write;
+ ptr_write += HOST_BIG_ENDIAN;
+ qatomic_set(ptr_write, *ptr_write | TLB_NOTDIRTY);
+ } else if (TCG_TARGET_REG_BITS == 32) {
+ /* Oversized guest */
+ tlb_entry->addr_write |= TLB_NOTDIRTY;
+ } else {
+ /* 64-bit */
+ qatomic_set(&tlb_entry->addr_write,
+ tlb_entry->addr_write | TLB_NOTDIRTY);
+ }
}
}
}
--
2.43.0
^ permalink raw reply related [flat|nested] 83+ messages in thread
* [RFC PATCH 20/34] accel/tcg: [CPUTLB] Use TCGContext.guest_mo for memory ordering
2024-01-19 14:39 [RFC PATCH 00/34] Compile accel/tcg once (partially) Anton Johansson via
` (18 preceding siblings ...)
2024-01-19 14:40 ` [RFC PATCH 19/34] accel/tcg: [CPUTLB] Use TCGContext.addr_type instead of TARGET_LONG_BITS Anton Johansson via
@ 2024-01-19 14:40 ` Anton Johansson via
2024-01-24 1:21 ` Richard Henderson
2024-01-19 14:40 ` [RFC PATCH 21/34] accel/tcg: [CPUTLB] Use tcg_ctx->tlb_dyn_max_bits Anton Johansson via
` (13 subsequent siblings)
33 siblings, 1 reply; 83+ messages in thread
From: Anton Johansson via @ 2024-01-19 14:40 UTC (permalink / raw)
To: qemu-devel; +Cc: ale, richard.henderson, philmd
Signed-off-by: Anton Johansson <anjo@rev.ng>
---
accel/tcg/internal-target.h | 11 ++++-------
1 file changed, 4 insertions(+), 7 deletions(-)
diff --git a/accel/tcg/internal-target.h b/accel/tcg/internal-target.h
index 4e36cf858e..3bcd1bbc84 100644
--- a/accel/tcg/internal-target.h
+++ b/accel/tcg/internal-target.h
@@ -9,8 +9,9 @@
#ifndef ACCEL_TCG_INTERNAL_TARGET_H
#define ACCEL_TCG_INTERNAL_TARGET_H
-#include "exec/exec-all.h"
+#include "exec/exec-common.h"
#include "exec/translate-all.h"
+#include "tcg/tcg.h"
/*
* Access to the various translations structures need to be serialised
@@ -108,12 +109,8 @@ extern bool one_insn_per_tb;
*
* This is a macro so that it's constant even without optimization.
*/
-#ifdef TCG_GUEST_DEFAULT_MO
-# define tcg_req_mo(type) \
- ((type) & TCG_GUEST_DEFAULT_MO & ~TCG_TARGET_DEFAULT_MO)
-#else
-# define tcg_req_mo(type) ((type) & ~TCG_TARGET_DEFAULT_MO)
-#endif
+#define tcg_req_mo(type) \
+ ((type) & tcg_ctx->guest_mo & ~TCG_TARGET_DEFAULT_MO)
/**
* cpu_req_mo:
--
2.43.0
^ permalink raw reply related [flat|nested] 83+ messages in thread
* [RFC PATCH 21/34] accel/tcg: [CPUTLB] Use tcg_ctx->tlb_dyn_max_bits
2024-01-19 14:39 [RFC PATCH 00/34] Compile accel/tcg once (partially) Anton Johansson via
` (19 preceding siblings ...)
2024-01-19 14:40 ` [RFC PATCH 20/34] accel/tcg: [CPUTLB] Use TCGContext.guest_mo for memory ordering Anton Johansson via
@ 2024-01-19 14:40 ` Anton Johansson via
2024-01-24 1:23 ` Richard Henderson
2024-01-19 14:40 ` [RFC PATCH 22/34] accel/tcg: [CPUTLB] Move CPU_TLB_DYN_[DEFAULT|MIN]* to cputlb.c Anton Johansson via
` (12 subsequent siblings)
33 siblings, 1 reply; 83+ messages in thread
From: Anton Johansson via @ 2024-01-19 14:40 UTC (permalink / raw)
To: qemu-devel; +Cc: ale, richard.henderson, philmd
CPU_TLB_DYN_MAX_BITS depends on TARGET_VIRT_ADDR_SPACE_BITS on 64-bit
hosts, and is not yet target independent.
Signed-off-by: Anton Johansson <anjo@rev.ng>
---
accel/tcg/cputlb.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
index 967d5da6d4..42be5b6289 100644
--- a/accel/tcg/cputlb.c
+++ b/accel/tcg/cputlb.c
@@ -172,7 +172,7 @@ static void tlb_mmu_resize_locked(CPUTLBDesc *desc, CPUTLBDescFast *fast,
rate = desc->window_max_entries * 100 / old_size;
if (rate > 70) {
- new_size = MIN(old_size << 1, 1 << CPU_TLB_DYN_MAX_BITS);
+ new_size = MIN(old_size << 1, 1 << tcg_ctx->tlb_dyn_max_bits);
} else if (rate < 30 && window_expired) {
size_t ceil = pow2ceil(desc->window_max_entries);
size_t expected_rate = desc->window_max_entries * 100 / ceil;
--
2.43.0
^ permalink raw reply related [flat|nested] 83+ messages in thread
* [RFC PATCH 22/34] accel/tcg: [CPUTLB] Move CPU_TLB_DYN_[DEFAULT|MIN]* to cputlb.c
2024-01-19 14:39 [RFC PATCH 00/34] Compile accel/tcg once (partially) Anton Johansson via
` (20 preceding siblings ...)
2024-01-19 14:40 ` [RFC PATCH 21/34] accel/tcg: [CPUTLB] Use tcg_ctx->tlb_dyn_max_bits Anton Johansson via
@ 2024-01-19 14:40 ` Anton Johansson via
2024-01-24 1:24 ` Richard Henderson
2024-01-19 14:40 ` [RFC PATCH 23/34] tcg: [CPUTLB] Add `mo_te` field to TCGContext Anton Johansson via
` (11 subsequent siblings)
33 siblings, 1 reply; 83+ messages in thread
From: Anton Johansson via @ 2024-01-19 14:40 UTC (permalink / raw)
To: qemu-devel; +Cc: ale, richard.henderson, philmd
These macros are only used for softmmu targets and only used in
cputlb.c, move definitions there.
Signed-off-by: Anton Johansson <anjo@rev.ng>
---
include/exec/cpu-defs.h | 3 ---
accel/tcg/cputlb.c | 3 +++
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h
index e8ccbe4bef..4b369e39b0 100644
--- a/include/exec/cpu-defs.h
+++ b/include/exec/cpu-defs.h
@@ -55,9 +55,6 @@
#include "exec/target_long.h"
#if defined(CONFIG_SOFTMMU) && defined(CONFIG_TCG)
-#define CPU_TLB_DYN_MIN_BITS 6
-#define CPU_TLB_DYN_DEFAULT_BITS 8
-
# if HOST_LONG_BITS == 32
/* Make sure we do not require a double-word shift for the TLB load */
# define CPU_TLB_DYN_MAX_BITS (32 - TARGET_PAGE_BITS)
diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
index 42be5b6289..a75a52d141 100644
--- a/accel/tcg/cputlb.c
+++ b/accel/tcg/cputlb.c
@@ -43,6 +43,9 @@
#include "tcg/tcg-ldst.h"
#include "tcg-target-reg-bits.h"
+#define CPU_TLB_DYN_MIN_BITS 6
+#define CPU_TLB_DYN_DEFAULT_BITS 8
+
/* DEBUG defines, enable DEBUG_TLB_LOG to log to the CPU_LOG_MMU target */
/* #define DEBUG_TLB */
/* #define DEBUG_TLB_LOG */
--
2.43.0
^ permalink raw reply related [flat|nested] 83+ messages in thread
* [RFC PATCH 23/34] tcg: [CPUTLB] Add `mo_te` field to TCGContext
2024-01-19 14:39 [RFC PATCH 00/34] Compile accel/tcg once (partially) Anton Johansson via
` (21 preceding siblings ...)
2024-01-19 14:40 ` [RFC PATCH 22/34] accel/tcg: [CPUTLB] Move CPU_TLB_DYN_[DEFAULT|MIN]* to cputlb.c Anton Johansson via
@ 2024-01-19 14:40 ` Anton Johansson via
2024-01-24 1:50 ` Richard Henderson
2024-01-19 14:40 ` [RFC PATCH 24/34] accel/tcg: [CPUTLB] Set mo_te in TCGContext Anton Johansson via
` (10 subsequent siblings)
33 siblings, 1 reply; 83+ messages in thread
From: Anton Johansson via @ 2024-01-19 14:40 UTC (permalink / raw)
To: qemu-devel; +Cc: ale, richard.henderson, philmd
Required by cpu_ldub_code() and friends in cputlb.c to access the MO_TE
MemOp in a target-independent way.
Signed-off-by: Anton Johansson <anjo@rev.ng>
---
include/tcg/tcg.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h
index 7743868dc9..4ca626aeae 100644
--- a/include/tcg/tcg.h
+++ b/include/tcg/tcg.h
@@ -489,6 +489,7 @@ struct TCGContext {
TCGType addr_type; /* TCG_TYPE_I32 or TCG_TYPE_I64 */
#ifdef CONFIG_SOFTMMU
+ MemOp mo_te;
int page_mask;
uint8_t page_bits;
uint8_t tlb_dyn_max_bits;
--
2.43.0
^ permalink raw reply related [flat|nested] 83+ messages in thread
* [RFC PATCH 24/34] accel/tcg: [CPUTLB] Set mo_te in TCGContext
2024-01-19 14:39 [RFC PATCH 00/34] Compile accel/tcg once (partially) Anton Johansson via
` (22 preceding siblings ...)
2024-01-19 14:40 ` [RFC PATCH 23/34] tcg: [CPUTLB] Add `mo_te` field to TCGContext Anton Johansson via
@ 2024-01-19 14:40 ` Anton Johansson via
2024-01-19 14:40 ` [RFC PATCH 25/34] accel/tcg: [CPUTLB] Use tcg_ctx->mo_te instead of MO_TE Anton Johansson via
` (9 subsequent siblings)
33 siblings, 0 replies; 83+ messages in thread
From: Anton Johansson via @ 2024-01-19 14:40 UTC (permalink / raw)
To: qemu-devel; +Cc: ale, richard.henderson, philmd
Initializes mo_te field of TCGContext to the target endian memory order
MO_TE, so it can be used within cputlb.c.
Signed-off-by: Anton Johansson <anjo@rev.ng>
---
accel/tcg/translate-all.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c
index 8cb6ad3511..9c981d1750 100644
--- a/accel/tcg/translate-all.c
+++ b/accel/tcg/translate-all.c
@@ -47,12 +47,13 @@
#include "exec/translate-all.h"
#include "exec/translator.h"
#include "exec/tb-flush.h"
+#include "exec/log.h"
+#include "exec/memop.h"
#include "qemu/bitmap.h"
#include "qemu/qemu-print.h"
#include "qemu/main-loop.h"
#include "qemu/cacheinfo.h"
#include "qemu/timer.h"
-#include "exec/log.h"
#include "sysemu/cpus.h"
#include "sysemu/cpu-timers.h"
#include "sysemu/tcg.h"
@@ -342,6 +343,7 @@ TranslationBlock *tb_gen_code(CPUState *cpu,
tcg_ctx->gen_tb = tb;
tcg_ctx->addr_type = TARGET_LONG_BITS == 32 ? TCG_TYPE_I32 : TCG_TYPE_I64;
#ifdef CONFIG_SOFTMMU
+ tcg_ctx->mo_te = MO_TE;
tcg_ctx->page_bits = TARGET_PAGE_BITS;
tcg_ctx->page_mask = TARGET_PAGE_MASK;
tcg_ctx->tlb_dyn_max_bits = CPU_TLB_DYN_MAX_BITS;
--
2.43.0
^ permalink raw reply related [flat|nested] 83+ messages in thread
* [RFC PATCH 25/34] accel/tcg: [CPUTLB] Use tcg_ctx->mo_te instead of MO_TE
2024-01-19 14:39 [RFC PATCH 00/34] Compile accel/tcg once (partially) Anton Johansson via
` (23 preceding siblings ...)
2024-01-19 14:40 ` [RFC PATCH 24/34] accel/tcg: [CPUTLB] Set mo_te in TCGContext Anton Johansson via
@ 2024-01-19 14:40 ` Anton Johansson via
2024-01-19 14:40 ` [RFC PATCH 26/34] Wrap target macros in functions Anton Johansson via
` (8 subsequent siblings)
33 siblings, 0 replies; 83+ messages in thread
From: Anton Johansson via @ 2024-01-19 14:40 UTC (permalink / raw)
To: qemu-devel; +Cc: ale, richard.henderson, philmd
Makes *_code() memory access functions target independent.
Signed-off-by: Anton Johansson <anjo@rev.ng>
---
accel/tcg/cputlb.c | 9 ++++++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
index a75a52d141..bfbbfd0fdb 100644
--- a/accel/tcg/cputlb.c
+++ b/accel/tcg/cputlb.c
@@ -2988,19 +2988,22 @@ uint32_t cpu_ldub_code(CPUArchState *env, abi_ptr addr)
uint32_t cpu_lduw_code(CPUArchState *env, abi_ptr addr)
{
- MemOpIdx oi = make_memop_idx(MO_TEUW, cpu_mmu_index(env, true));
+ MemOpIdx oi = make_memop_idx(tcg_ctx->mo_te | MO_UW,
+ cpu_mmu_index(env, true));
return do_ld2_mmu(env_cpu(env), addr, oi, 0, MMU_INST_FETCH);
}
uint32_t cpu_ldl_code(CPUArchState *env, abi_ptr addr)
{
- MemOpIdx oi = make_memop_idx(MO_TEUL, cpu_mmu_index(env, true));
+ MemOpIdx oi = make_memop_idx(tcg_ctx->mo_te | MO_UL,
+ cpu_mmu_index(env, true));
return do_ld4_mmu(env_cpu(env), addr, oi, 0, MMU_INST_FETCH);
}
uint64_t cpu_ldq_code(CPUArchState *env, abi_ptr addr)
{
- MemOpIdx oi = make_memop_idx(MO_TEUQ, cpu_mmu_index(env, true));
+ MemOpIdx oi = make_memop_idx(tcg_ctx->mo_te | MO_UQ,
+ cpu_mmu_index(env, true));
return do_ld8_mmu(env_cpu(env), addr, oi, 0, MMU_INST_FETCH);
}
--
2.43.0
^ permalink raw reply related [flat|nested] 83+ messages in thread
* [RFC PATCH 26/34] Wrap target macros in functions
2024-01-19 14:39 [RFC PATCH 00/34] Compile accel/tcg once (partially) Anton Johansson via
` (24 preceding siblings ...)
2024-01-19 14:40 ` [RFC PATCH 25/34] accel/tcg: [CPUTLB] Use tcg_ctx->mo_te instead of MO_TE Anton Johansson via
@ 2024-01-19 14:40 ` Anton Johansson via
2024-01-23 11:50 ` Philippe Mathieu-Daudé
2024-01-19 14:40 ` [RFC PATCH 27/34] accel/tcg: Make translate-all.c target independent Anton Johansson via
` (7 subsequent siblings)
33 siblings, 1 reply; 83+ messages in thread
From: Anton Johansson via @ 2024-01-19 14:40 UTC (permalink / raw)
To: qemu-devel; +Cc: ale, richard.henderson, philmd
Adds wrapper functions around common target specific macros required by
accel/tcg.
Signed-off-by: Anton Johansson <anjo@rev.ng>
---
include/hw/core/cpu.h | 9 +++++++
cpu-target.c | 62 +++++++++++++++++++++++++++++++++++++++++++
2 files changed, 71 insertions(+)
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index 57d100c203..a2d65c1d7a 100644
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cpu.h
@@ -26,6 +26,7 @@
#include "exec/vaddr.h"
#include "exec/memattrs.h"
#include "exec/tlb-common.h"
+#include "exec/memop.h"
#include "qapi/qapi-types-run-state.h"
#include "qemu/bitmap.h"
#include "qemu/rcu_queue.h"
@@ -1164,6 +1165,14 @@ void cpu_exec_unrealizefn(CPUState *cpu);
* what you are doing!
*/
bool target_words_bigendian(void);
+bool target_supports_mttcg(void);
+bool target_has_precise_smc(void);
+int target_long_bits(void);
+int target_phys_addr_space_bits(void);
+uint8_t target_insn_start_words(void);
+uint8_t target_default_memory_order(void);
+uint8_t target_tlb_dyn_max_bits(void);
+MemOp target_endian_memory_order(void);
const char *target_name(void);
diff --git a/cpu-target.c b/cpu-target.c
index 1a8e730bed..6b67af7a51 100644
--- a/cpu-target.c
+++ b/cpu-target.c
@@ -39,10 +39,13 @@
#include "exec/tb-flush.h"
#include "exec/translate-all.h"
#include "exec/log.h"
+#include "exec/cpu-defs.h"
#include "hw/core/accel-cpu.h"
#include "trace/trace-root.h"
#include "qemu/accel.h"
#include "qemu/plugin.h"
+#include "tcg/tcg-mo.h"
+#include "tcg/insn-start-words.h"
uintptr_t qemu_host_page_size;
intptr_t qemu_host_page_mask;
@@ -416,6 +419,65 @@ bool target_words_bigendian(void)
return TARGET_BIG_ENDIAN;
}
+bool target_supports_mttcg(void)
+{
+#ifdef TARGET_SUPPORTS_MTTCG
+# ifndef TCG_GUEST_DEFAULT_MO
+# error "TARGET_SUPPORTS_MTTCG without TCG_GUEST_DEFAULT_MO"
+# endif
+ return true;
+#else
+ return false;
+#endif
+}
+
+bool target_has_precise_smc(void)
+{
+#ifdef TARGET_HAS_PRECISE_SMC
+ return true;
+#else
+ return false;
+#endif
+}
+
+int target_long_bits(void)
+{
+ return TARGET_LONG_BITS;
+}
+
+int target_phys_addr_space_bits(void)
+{
+ return TARGET_PHYS_ADDR_SPACE_BITS;
+}
+
+uint8_t target_insn_start_words(void)
+{
+ return TARGET_INSN_START_WORDS;
+}
+
+uint8_t target_default_memory_order(void)
+{
+#ifdef TCG_GUEST_DEFAULT_MO
+ return TCG_GUEST_DEFAULT_MO;
+#else
+ return TCG_MO_ALL;
+#endif
+}
+
+MemOp target_endian_memory_order(void)
+{
+ return MO_TE;
+}
+
+uint8_t target_tlb_dyn_max_bits(void)
+{
+#if defined(CONFIG_SOFTMMU) && defined(CONFIG_TCG)
+ return CPU_TLB_DYN_MAX_BITS;
+#else
+ return 0;
+#endif
+}
+
const char *target_name(void)
{
return TARGET_NAME;
--
2.43.0
^ permalink raw reply related [flat|nested] 83+ messages in thread
* [RFC PATCH 27/34] accel/tcg: Make translate-all.c target independent
2024-01-19 14:39 [RFC PATCH 00/34] Compile accel/tcg once (partially) Anton Johansson via
` (25 preceding siblings ...)
2024-01-19 14:40 ` [RFC PATCH 26/34] Wrap target macros in functions Anton Johansson via
@ 2024-01-19 14:40 ` Anton Johansson via
2024-01-24 2:53 ` Richard Henderson
2024-01-19 14:40 ` [RFC PATCH 28/34] accel/tcg: Make plugin-gen.c " Anton Johansson via
` (6 subsequent siblings)
33 siblings, 1 reply; 83+ messages in thread
From: Anton Johansson via @ 2024-01-19 14:40 UTC (permalink / raw)
To: qemu-devel; +Cc: ale, richard.henderson, philmd
Makes translate-all.c independent of softmmu target by switching
TARGET_LONG_BITS -> target_long_bits()
TARGET_INSN_START_WORDS -> tcg_ctx->insn_start_words,
target_insn_start_words(),
TCG_GUEST_DEFAULT_MO -> target_default_memory_order()
MO_TE -> target_endian_memory_order()
Signed-off-by: Anton Johansson <anjo@rev.ng>
---
accel/tcg/translate-all.c | 38 ++++++++++++++++++--------------------
1 file changed, 18 insertions(+), 20 deletions(-)
diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c
index 9c981d1750..a3ae0c6910 100644
--- a/accel/tcg/translate-all.c
+++ b/accel/tcg/translate-all.c
@@ -65,7 +65,6 @@
#include "internal-common.h"
#include "internal-target.h"
#include "perf.h"
-#include "tcg/insn-start-words.h"
TBContext tb_ctx;
@@ -106,7 +105,7 @@ static int64_t decode_sleb128(const uint8_t **pp)
val |= (int64_t)(byte & 0x7f) << shift;
shift += 7;
} while (byte & 0x80);
- if (shift < TARGET_LONG_BITS && (byte & 0x40)) {
+ if (shift < target_long_bits() && (byte & 0x40)) {
val |= -(int64_t)1 << shift;
}
@@ -117,7 +116,7 @@ static int64_t decode_sleb128(const uint8_t **pp)
/* Encode the data collected about the instructions while compiling TB.
Place the data at BLOCK, and return the number of bytes consumed.
- The logical table consists of TARGET_INSN_START_WORDS target_ulong's,
+ The logical table consists of tcg_ctx->insn_start_words target_ulong's,
which come from the target's insn_start data, followed by a uintptr_t
which comes from the host pc of the end of the code implementing the insn.
@@ -128,6 +127,7 @@ static int64_t decode_sleb128(const uint8_t **pp)
static int encode_search(TranslationBlock *tb, uint8_t *block)
{
+ const uint8_t insn_start_words = tcg_ctx->insn_start_words;
uint8_t *highwater = tcg_ctx->code_gen_highwater;
uint64_t *insn_data = tcg_ctx->gen_insn_data;
uint16_t *insn_end_off = tcg_ctx->gen_insn_end_off;
@@ -137,13 +137,13 @@ static int encode_search(TranslationBlock *tb, uint8_t *block)
for (i = 0, n = tb->icount; i < n; ++i) {
uint64_t prev, curr;
- for (j = 0; j < TARGET_INSN_START_WORDS; ++j) {
+ for (j = 0; j < insn_start_words; ++j) {
if (i == 0) {
prev = (!(tb_cflags(tb) & CF_PCREL) && j == 0 ? tb->pc : 0);
} else {
- prev = insn_data[(i - 1) * TARGET_INSN_START_WORDS + j];
+ prev = insn_data[(i - 1) * insn_start_words + j];
}
- curr = insn_data[i * TARGET_INSN_START_WORDS + j];
+ curr = insn_data[i * insn_start_words + j];
p = encode_sleb128(p, curr - prev);
}
prev = (i == 0 ? 0 : insn_end_off[i - 1]);
@@ -165,6 +165,7 @@ static int encode_search(TranslationBlock *tb, uint8_t *block)
static int cpu_unwind_data_from_tb(TranslationBlock *tb, uintptr_t host_pc,
uint64_t *data)
{
+ const uint8_t insn_start_words = tcg_ctx->insn_start_words;
uintptr_t iter_pc = (uintptr_t)tb->tc.ptr;
const uint8_t *p = tb->tc.ptr + tb->tc.size;
int i, j, num_insns = tb->icount;
@@ -175,7 +176,7 @@ static int cpu_unwind_data_from_tb(TranslationBlock *tb, uintptr_t host_pc,
return -1;
}
- memset(data, 0, sizeof(uint64_t) * TARGET_INSN_START_WORDS);
+ memset(data, 0, sizeof(uint64_t) * insn_start_words);
if (!(tb_cflags(tb) & CF_PCREL)) {
data[0] = tb->pc;
}
@@ -185,7 +186,7 @@ static int cpu_unwind_data_from_tb(TranslationBlock *tb, uintptr_t host_pc,
* at which the end of the insn exceeds host_pc.
*/
for (i = 0; i < num_insns; ++i) {
- for (j = 0; j < TARGET_INSN_START_WORDS; ++j) {
+ for (j = 0; j < insn_start_words; ++j) {
data[j] += decode_sleb128(&p);
}
iter_pc += decode_sleb128(&p);
@@ -203,7 +204,7 @@ static int cpu_unwind_data_from_tb(TranslationBlock *tb, uintptr_t host_pc,
void cpu_restore_state_from_tb(CPUState *cpu, TranslationBlock *tb,
uintptr_t host_pc)
{
- uint64_t data[TARGET_INSN_START_WORDS];
+ uint64_t data[tcg_ctx->insn_start_words];
int insns_left = cpu_unwind_data_from_tb(tb, host_pc, data);
if (insns_left < 0) {
@@ -341,19 +342,15 @@ TranslationBlock *tb_gen_code(CPUState *cpu,
}
tcg_ctx->gen_tb = tb;
- tcg_ctx->addr_type = TARGET_LONG_BITS == 32 ? TCG_TYPE_I32 : TCG_TYPE_I64;
+ tcg_ctx->addr_type = target_long_bits() == 32 ? TCG_TYPE_I32 : TCG_TYPE_I64;
#ifdef CONFIG_SOFTMMU
- tcg_ctx->mo_te = MO_TE;
+ tcg_ctx->mo_te = target_endian_memory_order();
tcg_ctx->page_bits = TARGET_PAGE_BITS;
tcg_ctx->page_mask = TARGET_PAGE_MASK;
- tcg_ctx->tlb_dyn_max_bits = CPU_TLB_DYN_MAX_BITS;
-#endif
- tcg_ctx->insn_start_words = TARGET_INSN_START_WORDS;
-#ifdef TCG_GUEST_DEFAULT_MO
- tcg_ctx->guest_mo = TCG_GUEST_DEFAULT_MO;
-#else
- tcg_ctx->guest_mo = TCG_MO_ALL;
+ tcg_ctx->tlb_dyn_max_bits = target_tlb_dyn_max_bits();
#endif
+ tcg_ctx->insn_start_words = target_insn_start_words();
+ tcg_ctx->guest_mo = target_default_memory_order();
restart_translate:
trace_translate_block(tb, pc, tb->tc.ptr);
@@ -441,6 +438,7 @@ TranslationBlock *tb_gen_code(CPUState *cpu,
qemu_log_in_addr_range(pc)) {
FILE *logfile = qemu_log_trylock();
if (logfile) {
+ const uint8_t insn_start_words = tcg_ctx->insn_start_words;
int code_size, data_size;
const tcg_target_ulong *rx_data_gen_ptr;
size_t chunk_start;
@@ -460,7 +458,7 @@ TranslationBlock *tb_gen_code(CPUState *cpu,
fprintf(logfile, "OUT: [size=%d]\n", gen_code_size);
fprintf(logfile,
" -- guest addr 0x%016" PRIx64 " + tb prologue\n",
- tcg_ctx->gen_insn_data[insn * TARGET_INSN_START_WORDS]);
+ tcg_ctx->gen_insn_data[insn * insn_start_words]);
chunk_start = tcg_ctx->gen_insn_end_off[insn];
disas(logfile, tb->tc.ptr, chunk_start);
@@ -473,7 +471,7 @@ TranslationBlock *tb_gen_code(CPUState *cpu,
size_t chunk_end = tcg_ctx->gen_insn_end_off[insn];
if (chunk_end > chunk_start) {
fprintf(logfile, " -- guest addr 0x%016" PRIx64 "\n",
- tcg_ctx->gen_insn_data[insn * TARGET_INSN_START_WORDS]);
+ tcg_ctx->gen_insn_data[insn * insn_start_words]);
disas(logfile, tb->tc.ptr + chunk_start,
chunk_end - chunk_start);
chunk_start = chunk_end;
--
2.43.0
^ permalink raw reply related [flat|nested] 83+ messages in thread
* [RFC PATCH 28/34] accel/tcg: Make plugin-gen.c target independent
2024-01-19 14:39 [RFC PATCH 00/34] Compile accel/tcg once (partially) Anton Johansson via
` (26 preceding siblings ...)
2024-01-19 14:40 ` [RFC PATCH 27/34] accel/tcg: Make translate-all.c target independent Anton Johansson via
@ 2024-01-19 14:40 ` Anton Johansson via
2024-01-24 3:02 ` Richard Henderson
2024-01-19 14:40 ` [RFC PATCH 29/34] accel/tcg: Make tb-maint.c target indpendent Anton Johansson via
` (5 subsequent siblings)
33 siblings, 1 reply; 83+ messages in thread
From: Anton Johansson via @ 2024-01-19 14:40 UTC (permalink / raw)
To: qemu-devel; +Cc: ale, richard.henderson, philmd
Switches computation of offsets into CPUState to use that the offset
between CPUState and CPUArchState is guaranteed to be sizeof(CPUState).
Signed-off-by: Anton Johansson <anjo@rev.ng>
---
accel/tcg/plugin-gen.c | 15 +++++++--------
1 file changed, 7 insertions(+), 8 deletions(-)
diff --git a/accel/tcg/plugin-gen.c b/accel/tcg/plugin-gen.c
index d31c9993ea..ce7635958f 100644
--- a/accel/tcg/plugin-gen.c
+++ b/accel/tcg/plugin-gen.c
@@ -43,10 +43,9 @@
* CPU's index into a TCG temp, since the first callback did it already.
*/
#include "qemu/osdep.h"
-#include "cpu.h"
#include "tcg/tcg.h"
#include "tcg/tcg-temp-internal.h"
-#include "tcg/tcg-op.h"
+#include "tcg/tcg-op-common.h"
#include "exec/exec-all.h"
#include "exec/plugin-gen.h"
#include "exec/translator.h"
@@ -104,8 +103,8 @@ static void gen_empty_udata_cb(void)
TCGv_ptr udata = tcg_temp_ebb_new_ptr();
tcg_gen_movi_ptr(udata, 0);
- tcg_gen_ld_i32(cpu_index, tcg_env,
- -offsetof(ArchCPU, env) + offsetof(CPUState, cpu_index));
+ tcg_gen_ld_i32(cpu_index, tcg_env, offsetof(CPUState, cpu_index) -
+ sizeof(CPUState));
gen_helper_plugin_vcpu_udata_cb(cpu_index, udata);
tcg_temp_free_ptr(udata);
@@ -138,8 +137,8 @@ static void gen_empty_mem_cb(TCGv_i64 addr, uint32_t info)
tcg_gen_movi_i32(meminfo, info);
tcg_gen_movi_ptr(udata, 0);
- tcg_gen_ld_i32(cpu_index, tcg_env,
- -offsetof(ArchCPU, env) + offsetof(CPUState, cpu_index));
+ tcg_gen_ld_i32(cpu_index, tcg_env, offsetof(CPUState, cpu_index) -
+ sizeof(CPUState));
gen_helper_plugin_vcpu_mem_cb(cpu_index, meminfo, addr, udata);
@@ -158,7 +157,7 @@ static void gen_empty_mem_helper(void)
tcg_gen_movi_ptr(ptr, 0);
tcg_gen_st_ptr(ptr, tcg_env, offsetof(CPUState, plugin_mem_cbs) -
- offsetof(ArchCPU, env));
+ sizeof(CPUState));
tcg_temp_free_ptr(ptr);
}
@@ -582,7 +581,7 @@ void plugin_gen_disable_mem_helpers(void)
return;
}
tcg_gen_st_ptr(tcg_constant_ptr(NULL), tcg_env,
- offsetof(CPUState, plugin_mem_cbs) - offsetof(ArchCPU, env));
+ offsetof(CPUState, plugin_mem_cbs) - sizeof(CPUState));
}
static void plugin_gen_tb_udata(const struct qemu_plugin_tb *ptb,
--
2.43.0
^ permalink raw reply related [flat|nested] 83+ messages in thread
* [RFC PATCH 29/34] accel/tcg: Make tb-maint.c target indpendent
2024-01-19 14:39 [RFC PATCH 00/34] Compile accel/tcg once (partially) Anton Johansson via
` (27 preceding siblings ...)
2024-01-19 14:40 ` [RFC PATCH 28/34] accel/tcg: Make plugin-gen.c " Anton Johansson via
@ 2024-01-19 14:40 ` Anton Johansson via
2024-01-24 3:10 ` Richard Henderson
2024-01-19 14:40 ` [RFC PATCH 30/34] accel/tcg: Make tcg-all.c " Anton Johansson via
` (4 subsequent siblings)
33 siblings, 1 reply; 83+ messages in thread
From: Anton Johansson via @ 2024-01-19 14:40 UTC (permalink / raw)
To: qemu-devel; +Cc: ale, richard.henderson, philmd
Uses target_has_precise_smc() and target_phys_addr_space_bits() to turn
ifdefs into runtime branches.
Signed-off-by: Anton Johansson <anjo@rev.ng>
---
accel/tcg/tb-maint.c | 47 +++++++++++++++++++++++---------------------
1 file changed, 25 insertions(+), 22 deletions(-)
diff --git a/accel/tcg/tb-maint.c b/accel/tcg/tb-maint.c
index b194f8f065..fdc3a30d0d 100644
--- a/accel/tcg/tb-maint.c
+++ b/accel/tcg/tb-maint.c
@@ -148,14 +148,6 @@ static PageForEachNext foreach_tb_next(PageForEachNext tb,
}
#else
-/*
- * In system mode we want L1_MAP to be based on ram offsets.
- */
-#if HOST_LONG_BITS < TARGET_PHYS_ADDR_SPACE_BITS
-# define L1_MAP_ADDR_SPACE_BITS HOST_LONG_BITS
-#else
-# define L1_MAP_ADDR_SPACE_BITS TARGET_PHYS_ADDR_SPACE_BITS
-#endif
/* Size of the L2 (and L3, etc) page tables. */
#define V_L2_BITS 10
@@ -186,17 +178,28 @@ struct PageDesc {
void page_table_config_init(void)
{
+ int target_phys_addr_bits = target_phys_addr_space_bits();
+ uint32_t l1_map_addr_space_bits;
uint32_t v_l1_bits;
+ /*
+ * In system mode we want L1_MAP to be based on ram offsets.
+ */
+ if (HOST_LONG_BITS < target_phys_addr_bits) {
+ l1_map_addr_space_bits = HOST_LONG_BITS;
+ } else {
+ l1_map_addr_space_bits = target_phys_addr_bits;
+ }
+
assert(TARGET_PAGE_BITS);
/* The bits remaining after N lower levels of page tables. */
- v_l1_bits = (L1_MAP_ADDR_SPACE_BITS - TARGET_PAGE_BITS) % V_L2_BITS;
+ v_l1_bits = (l1_map_addr_space_bits - TARGET_PAGE_BITS) % V_L2_BITS;
if (v_l1_bits < V_L1_MIN_BITS) {
v_l1_bits += V_L2_BITS;
}
v_l1_size = 1 << v_l1_bits;
- v_l1_shift = L1_MAP_ADDR_SPACE_BITS - TARGET_PAGE_BITS - v_l1_bits;
+ v_l1_shift = l1_map_addr_space_bits - TARGET_PAGE_BITS - v_l1_bits;
v_l2_levels = v_l1_shift / V_L2_BITS - 1;
assert(v_l1_bits <= V_L1_MAX_BITS);
@@ -1045,14 +1048,15 @@ bool tb_invalidate_phys_page_unwind(tb_page_addr_t addr, uintptr_t pc)
TranslationBlock *tb;
PageForEachNext n;
tb_page_addr_t last;
+ const bool has_precise_smc = target_has_precise_smc();
/*
* Without precise smc semantics, or when outside of a TB,
* we can skip to invalidate.
*/
-#ifndef TARGET_HAS_PRECISE_SMC
- pc = 0;
-#endif
+ if (!has_precise_smc) {
+ pc = 0;
+ }
if (!pc) {
tb_invalidate_phys_page(addr);
return false;
@@ -1102,10 +1106,13 @@ tb_invalidate_phys_page_range__locked(struct page_collection *pages,
{
TranslationBlock *tb;
PageForEachNext n;
-#ifdef TARGET_HAS_PRECISE_SMC
+ const bool has_precise_smc = target_has_precise_smc();
bool current_tb_modified = false;
- TranslationBlock *current_tb = retaddr ? tcg_tb_lookup(retaddr) : NULL;
-#endif /* TARGET_HAS_PRECISE_SMC */
+ TranslationBlock *current_tb = NULL;
+
+ if (has_precise_smc && retaddr) {
+ current_tb = tcg_tb_lookup(retaddr);
+ }
/* Range may not cross a page. */
tcg_debug_assert(((start ^ last) & TARGET_PAGE_MASK) == 0);
@@ -1127,8 +1134,7 @@ tb_invalidate_phys_page_range__locked(struct page_collection *pages,
tb_last = tb_start + (tb_last & ~TARGET_PAGE_MASK);
}
if (!(tb_last < start || tb_start > last)) {
-#ifdef TARGET_HAS_PRECISE_SMC
- if (current_tb == tb &&
+ if (has_precise_smc && current_tb == tb &&
(tb_cflags(current_tb) & CF_COUNT_MASK) != 1) {
/*
* If we are modifying the current TB, we must stop
@@ -1140,7 +1146,6 @@ tb_invalidate_phys_page_range__locked(struct page_collection *pages,
current_tb_modified = true;
cpu_restore_state_from_tb(current_cpu, current_tb, retaddr);
}
-#endif /* TARGET_HAS_PRECISE_SMC */
tb_phys_invalidate__locked(tb);
}
}
@@ -1150,15 +1155,13 @@ tb_invalidate_phys_page_range__locked(struct page_collection *pages,
tlb_unprotect_code(start);
}
-#ifdef TARGET_HAS_PRECISE_SMC
- if (current_tb_modified) {
+ if (has_precise_smc && current_tb_modified) {
page_collection_unlock(pages);
/* Force execution of one insn next time. */
current_cpu->cflags_next_tb = 1 | CF_NOIRQ | curr_cflags(current_cpu);
mmap_unlock();
cpu_loop_exit_noexc(current_cpu);
}
-#endif
}
/*
--
2.43.0
^ permalink raw reply related [flat|nested] 83+ messages in thread
* [RFC PATCH 30/34] accel/tcg: Make tcg-all.c target indpendent
2024-01-19 14:39 [RFC PATCH 00/34] Compile accel/tcg once (partially) Anton Johansson via
` (28 preceding siblings ...)
2024-01-19 14:40 ` [RFC PATCH 29/34] accel/tcg: Make tb-maint.c target indpendent Anton Johansson via
@ 2024-01-19 14:40 ` Anton Johansson via
2024-01-23 11:45 ` Philippe Mathieu-Daudé
2024-01-24 3:13 ` Richard Henderson
2024-01-19 14:40 ` [RFC PATCH 31/34] accel/tcg: Make tcg-runtime-gvec.c target independent Anton Johansson via
` (3 subsequent siblings)
33 siblings, 2 replies; 83+ messages in thread
From: Anton Johansson via @ 2024-01-19 14:40 UTC (permalink / raw)
To: qemu-devel; +Cc: ale, richard.henderson, philmd
Uses target_supports_mttcg() and target_long_bits() to turn ifdefs into
runtime branches.
Signed-off-by: Anton Johansson <anjo@rev.ng>
---
accel/tcg/tcg-all.c | 25 +++++++++----------------
1 file changed, 9 insertions(+), 16 deletions(-)
diff --git a/accel/tcg/tcg-all.c b/accel/tcg/tcg-all.c
index a40e0aee37..b8e920e3a8 100644
--- a/accel/tcg/tcg-all.c
+++ b/accel/tcg/tcg-all.c
@@ -28,7 +28,6 @@
#include "exec/replay-core.h"
#include "sysemu/cpu-timers.h"
#include "tcg/tcg.h"
-#include "tcg/oversized-guest.h"
#include "qapi/error.h"
#include "qemu/error-report.h"
#include "qemu/accel.h"
@@ -67,20 +66,13 @@ DECLARE_INSTANCE_CHECKER(TCGState, TCG_STATE,
* there is one remaining limitation to check:
* - The guest can't be oversized (e.g. 64 bit guest on 32 bit host)
*/
-
static bool default_mttcg_enabled(void)
{
- if (icount_enabled() || TCG_OVERSIZED_GUEST) {
+ const bool oversized_guest = target_long_bits() > TCG_TARGET_REG_BITS;
+ if (icount_enabled() || oversized_guest) {
return false;
}
-#ifdef TARGET_SUPPORTS_MTTCG
-# ifndef TCG_GUEST_DEFAULT_MO
-# error "TARGET_SUPPORTS_MTTCG without TCG_GUEST_DEFAULT_MO"
-# endif
- return true;
-#else
- return false;
-#endif
+ return target_supports_mttcg();
}
static void tcg_accel_instance_init(Object *obj)
@@ -137,17 +129,18 @@ static char *tcg_get_thread(Object *obj, Error **errp)
static void tcg_set_thread(Object *obj, const char *value, Error **errp)
{
TCGState *s = TCG_STATE(obj);
+ const bool oversized_guest = target_long_bits() > TCG_TARGET_REG_BITS;
if (strcmp(value, "multi") == 0) {
- if (TCG_OVERSIZED_GUEST) {
+ if (oversized_guest) {
error_setg(errp, "No MTTCG when guest word size > hosts");
} else if (icount_enabled()) {
error_setg(errp, "No MTTCG when icount is enabled");
} else {
-#ifndef TARGET_SUPPORTS_MTTCG
- warn_report("Guest not yet converted to MTTCG - "
- "you may get unexpected results");
-#endif
+ if (target_supports_mttcg()) {
+ warn_report("Guest not yet converted to MTTCG - "
+ "you may get unexpected results");
+ }
s->mttcg_enabled = true;
}
} else if (strcmp(value, "single") == 0) {
--
2.43.0
^ permalink raw reply related [flat|nested] 83+ messages in thread
* [RFC PATCH 31/34] accel/tcg: Make tcg-runtime-gvec.c target independent
2024-01-19 14:39 [RFC PATCH 00/34] Compile accel/tcg once (partially) Anton Johansson via
` (29 preceding siblings ...)
2024-01-19 14:40 ` [RFC PATCH 30/34] accel/tcg: Make tcg-all.c " Anton Johansson via
@ 2024-01-19 14:40 ` Anton Johansson via
2024-01-24 3:15 ` Richard Henderson
2024-01-19 14:40 ` [RFC PATCH 32/34] accel/tcg: Make tcg-runtime.c " Anton Johansson via
` (2 subsequent siblings)
33 siblings, 1 reply; 83+ messages in thread
From: Anton Johansson via @ 2024-01-19 14:40 UTC (permalink / raw)
To: qemu-devel; +Cc: ale, richard.henderson, philmd
Only depends on cpu.h.
Signed-off-by: Anton Johansson <anjo@rev.ng>
---
accel/tcg/tcg-runtime-gvec.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/accel/tcg/tcg-runtime-gvec.c b/accel/tcg/tcg-runtime-gvec.c
index afca89baa1..52f983dd4c 100644
--- a/accel/tcg/tcg-runtime-gvec.c
+++ b/accel/tcg/tcg-runtime-gvec.c
@@ -19,7 +19,7 @@
#include "qemu/osdep.h"
#include "qemu/host-utils.h"
-#include "cpu.h"
+#include "qemu/bitops.h"
#include "exec/helper-proto-common.h"
#include "tcg/tcg-gvec-desc.h"
--
2.43.0
^ permalink raw reply related [flat|nested] 83+ messages in thread
* [RFC PATCH 32/34] accel/tcg: Make tcg-runtime.c target independent
2024-01-19 14:39 [RFC PATCH 00/34] Compile accel/tcg once (partially) Anton Johansson via
` (30 preceding siblings ...)
2024-01-19 14:40 ` [RFC PATCH 31/34] accel/tcg: Make tcg-runtime-gvec.c target independent Anton Johansson via
@ 2024-01-19 14:40 ` Anton Johansson via
2024-01-24 3:16 ` Richard Henderson
2024-01-19 14:40 ` [RFC PATCH 33/34] accel/tcg: Make translator.c (partially) " Anton Johansson via
2024-01-19 14:40 ` [RFC PATCH 34/34] accel/tcg: Compile (a few files) once for system-mode Anton Johansson via
33 siblings, 1 reply; 83+ messages in thread
From: Anton Johansson via @ 2024-01-19 14:40 UTC (permalink / raw)
To: qemu-devel; +Cc: ale, richard.henderson, philmd
Only depends on cpu.h.
Signed-off-by: Anton Johansson <anjo@rev.ng>
---
accel/tcg/tcg-runtime.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/accel/tcg/tcg-runtime.c b/accel/tcg/tcg-runtime.c
index 9fa539ad3d..fd78a10fe2 100644
--- a/accel/tcg/tcg-runtime.c
+++ b/accel/tcg/tcg-runtime.c
@@ -23,7 +23,7 @@
*/
#include "qemu/osdep.h"
#include "qemu/host-utils.h"
-#include "cpu.h"
+#include "qemu/atomic.h"
#include "exec/helper-proto-common.h"
#include "exec/cpu_ldst.h"
#include "exec/exec-all.h"
--
2.43.0
^ permalink raw reply related [flat|nested] 83+ messages in thread
* [RFC PATCH 33/34] accel/tcg: Make translator.c (partially) target independent
2024-01-19 14:39 [RFC PATCH 00/34] Compile accel/tcg once (partially) Anton Johansson via
` (31 preceding siblings ...)
2024-01-19 14:40 ` [RFC PATCH 32/34] accel/tcg: Make tcg-runtime.c " Anton Johansson via
@ 2024-01-19 14:40 ` Anton Johansson via
2024-01-24 3:30 ` Richard Henderson
2024-01-19 14:40 ` [RFC PATCH 34/34] accel/tcg: Compile (a few files) once for system-mode Anton Johansson via
33 siblings, 1 reply; 83+ messages in thread
From: Anton Johansson via @ 2024-01-19 14:40 UTC (permalink / raw)
To: qemu-devel; +Cc: ale, richard.henderson, philmd
Make CPUState offset calculations target independent by using that
CPUState and CPUArchState are statically guaranteed to lie next to each
other in memory.
Signed-off-by: Anton Johansson <anjo@rev.ng>
---
accel/tcg/translator.c | 16 ++++++++--------
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/accel/tcg/translator.c b/accel/tcg/translator.c
index 65219b52eb..43303577d7 100644
--- a/accel/tcg/translator.c
+++ b/accel/tcg/translator.c
@@ -19,8 +19,8 @@
static void gen_io_start(void)
{
tcg_gen_st_i32(tcg_constant_i32(1), tcg_env,
- offsetof(ArchCPU, parent_obj.neg.can_do_io) -
- offsetof(ArchCPU, env));
+ offsetof(CPUState, neg.can_do_io) -
+ sizeof(CPUState));
}
bool translator_io_start(DisasContextBase *db)
@@ -53,8 +53,8 @@ static TCGOp *gen_tb_start(uint32_t cflags)
TCGOp *icount_start_insn = NULL;
tcg_gen_ld_i32(count, tcg_env,
- offsetof(ArchCPU, parent_obj.neg.icount_decr.u32)
- - offsetof(ArchCPU, env));
+ offsetof(CPUState, neg.icount_decr.u32) -
+ sizeof(CPUState));
if (cflags & CF_USE_ICOUNT) {
/*
@@ -82,8 +82,8 @@ static TCGOp *gen_tb_start(uint32_t cflags)
if (cflags & CF_USE_ICOUNT) {
tcg_gen_st16_i32(count, tcg_env,
- offsetof(ArchCPU, parent_obj.neg.icount_decr.u16.low)
- - offsetof(ArchCPU, env));
+ offsetof(CPUState, neg.icount_decr.u16.low) -
+ sizeof(CPUState));
/*
* cpu->can_do_io is cleared automatically here at the beginning of
* each translation block. The cost is minimal and only paid for
@@ -92,8 +92,8 @@ static TCGOp *gen_tb_start(uint32_t cflags)
* go with gen_io_start().
*/
tcg_gen_st_i32(tcg_constant_i32(0), tcg_env,
- offsetof(ArchCPU, parent_obj.neg.can_do_io) -
- offsetof(ArchCPU, env));
+ offsetof(CPUState, neg.can_do_io) -
+ sizeof(CPUState));
}
return icount_start_insn;
--
2.43.0
^ permalink raw reply related [flat|nested] 83+ messages in thread
* [RFC PATCH 34/34] accel/tcg: Compile (a few files) once for system-mode
2024-01-19 14:39 [RFC PATCH 00/34] Compile accel/tcg once (partially) Anton Johansson via
` (32 preceding siblings ...)
2024-01-19 14:40 ` [RFC PATCH 33/34] accel/tcg: Make translator.c (partially) " Anton Johansson via
@ 2024-01-19 14:40 ` Anton Johansson via
33 siblings, 0 replies; 83+ messages in thread
From: Anton Johansson via @ 2024-01-19 14:40 UTC (permalink / raw)
To: qemu-devel; +Cc: ale, richard.henderson, philmd
Build a common static library for a few softmmu files.
Signed-off-by: Anton Johansson <anjo@rev.ng>
---
accel/tcg/meson.build | 57 ++++++++++++++++++++++++++++++++++---------
1 file changed, 45 insertions(+), 12 deletions(-)
diff --git a/accel/tcg/meson.build b/accel/tcg/meson.build
index 8783edd06e..420050bdbf 100644
--- a/accel/tcg/meson.build
+++ b/accel/tcg/meson.build
@@ -1,28 +1,61 @@
-tcg_ss = ss.source_set()
+tcg_specific_ss = ss.source_set()
+tcg_user_ss = ss.source_set()
common_ss.add(when: 'CONFIG_TCG', if_true: files(
'cpu-exec-common.c',
))
-tcg_ss.add(files(
- 'tcg-all.c',
+common_ss.add(when: libdw, if_true: files('debuginfo.c'))
+
+tcg_specific_ss.add(files(
'cpu-exec.c',
+ 'translator.c',
+))
+
+tcg_user_ss.add(files(
+ 'user-exec.c',
+ 'translate-all.c',
'tb-maint.c',
'tcg-runtime-gvec.c',
'tcg-runtime.c',
- 'translate-all.c',
- 'translator.c',
+ 'tcg-all.c',
))
-tcg_ss.add(when: 'CONFIG_USER_ONLY', if_true: files('user-exec.c'))
-tcg_ss.add(when: 'CONFIG_SYSTEM_ONLY', if_false: files('user-exec-stub.c'))
if get_option('plugins')
- tcg_ss.add(files('plugin-gen.c'))
+ tcg_user_ss.add(files('plugin-gen.c'))
endif
-tcg_ss.add(when: libdw, if_true: files('debuginfo.c'))
-tcg_ss.add(when: 'CONFIG_LINUX', if_true: files('perf.c'))
-specific_ss.add_all(when: 'CONFIG_TCG', if_true: tcg_ss)
+tcg_specific_ss.add_all(when: 'CONFIG_USER_ONLY', if_true: tcg_user_ss)
+tcg_specific_ss.add(when: 'CONFIG_SYSTEM_ONLY', if_false: files(
+ 'user-exec-stub.c'
+))
+tcg_specific_ss.add(when: 'CONFIG_LINUX', if_true: files('perf.c'))
+specific_ss.add_all(when: 'CONFIG_TCG', if_true: tcg_specific_ss)
-specific_ss.add(when: ['CONFIG_SYSTEM_ONLY', 'CONFIG_TCG'], if_true: files(
+have_tcg = get_option('tcg').allowed()
+tcg_softmmu_ss = ss.source_set()
+tcg_softmmu_ss.add(files(
'cputlb.c',
+ 'translate-all.c',
+ 'tb-maint.c',
+ 'tcg-runtime-gvec.c',
+ 'tcg-runtime.c',
+ 'tcg-all.c',
))
+if get_option('plugins')
+ tcg_softmmu_ss.add(files('plugin-gen.c'))
+endif
+tcg_softmmu_ss = tcg_softmmu_ss.apply(config_targetos, strict: false)
+
+libacceltcg_softmmu = static_library('acceltcg_softmmu',
+ tcg_softmmu_ss.sources() + genh,
+ name_suffix: 'fa',
+ c_args: '-DCONFIG_SOFTMMU',
+ build_by_default: have_system and
+ have_tcg)
+
+if not get_option('tcg').allowed()
+ subdir_done()
+endif
+tcg_softmmu = declare_dependency(link_with: libacceltcg_softmmu,
+ dependencies: tcg_softmmu_ss.dependencies())
+system_ss.add(when: 'CONFIG_SYSTEM_ONLY', if_true: tcg_softmmu)
system_ss.add(when: ['CONFIG_TCG'], if_true: files(
'icount-common.c',
--
2.43.0
^ permalink raw reply related [flat|nested] 83+ messages in thread
* Re: [RFC PATCH 01/34] target: [PAGE_VARY] Use PAGE_VARY for all softmmu targets
2024-01-19 14:39 ` [RFC PATCH 01/34] target: [PAGE_VARY] Use PAGE_VARY for all softmmu targets Anton Johansson via
@ 2024-01-19 16:05 ` Philippe Mathieu-Daudé
2024-01-23 12:09 ` Anton Johansson via
0 siblings, 1 reply; 83+ messages in thread
From: Philippe Mathieu-Daudé @ 2024-01-19 16:05 UTC (permalink / raw)
To: Anton Johansson, qemu-devel; +Cc: ale, richard.henderson
On 19/1/24 15:39, Anton Johansson wrote:
> Allows for future commits to use TargetPageBits to access page bits and
> mask, thus making TARGET_PAGE_* independent of softmmu target.
>
> In the future, this will also be important fo allowing heterogeneous CPUs
> on the same board.
Yeah I carry an almost similar patch :)
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> Signed-off-by: Anton Johansson <anjo@rev.ng>
> ---
> target/alpha/cpu-param.h | 6 ++++++
> target/avr/cpu-param.h | 6 ++++++
> target/cris/cpu-param.h | 7 +++++++
> target/hppa/cpu-param.h | 6 ++++++
> target/i386/cpu-param.h | 6 ++++++
> target/loongarch/cpu-param.h | 5 +++++
> target/m68k/cpu-param.h | 6 ++++++
> target/microblaze/cpu-param.h | 6 ++++--
> target/nios2/cpu-param.h | 5 ++++-
> target/openrisc/cpu-param.h | 8 +++++++-
> target/ppc/cpu-param.h | 6 ++++++
> target/riscv/cpu-param.h | 7 +++++++
> target/rx/cpu-param.h | 8 +++++++-
> target/s390x/cpu-param.h | 8 +++++++-
> target/sh4/cpu-param.h | 4 +++-
> target/sparc/cpu-param.h | 17 +++++++++++++++--
> target/tricore/cpu-param.h | 8 +++++++-
> target/xtensa/cpu-param.h | 8 +++++---
> 18 files changed, 114 insertions(+), 13 deletions(-)
^ permalink raw reply [flat|nested] 83+ messages in thread
* Re: [RFC PATCH 30/34] accel/tcg: Make tcg-all.c target indpendent
2024-01-19 14:40 ` [RFC PATCH 30/34] accel/tcg: Make tcg-all.c " Anton Johansson via
@ 2024-01-23 11:45 ` Philippe Mathieu-Daudé
2024-01-23 12:03 ` Anton Johansson via
2024-01-24 3:13 ` Richard Henderson
1 sibling, 1 reply; 83+ messages in thread
From: Philippe Mathieu-Daudé @ 2024-01-23 11:45 UTC (permalink / raw)
To: Anton Johansson, qemu-devel; +Cc: ale, richard.henderson
Hi Anton,
On 19/1/24 15:40, Anton Johansson wrote:
> Uses target_supports_mttcg() and target_long_bits() to turn ifdefs into
> runtime branches.
>
> Signed-off-by: Anton Johansson <anjo@rev.ng>
> ---
> accel/tcg/tcg-all.c | 25 +++++++++----------------
> 1 file changed, 9 insertions(+), 16 deletions(-)
> static void tcg_accel_instance_init(Object *obj)
> @@ -137,17 +129,18 @@ static char *tcg_get_thread(Object *obj, Error **errp)
> static void tcg_set_thread(Object *obj, const char *value, Error **errp)
> {
> TCGState *s = TCG_STATE(obj);
> + const bool oversized_guest = target_long_bits() > TCG_TARGET_REG_BITS;
>
> if (strcmp(value, "multi") == 0) {
> - if (TCG_OVERSIZED_GUEST) {
> + if (oversized_guest) {
> error_setg(errp, "No MTTCG when guest word size > hosts");
> } else if (icount_enabled()) {
> error_setg(errp, "No MTTCG when icount is enabled");
> } else {
> -#ifndef TARGET_SUPPORTS_MTTCG
> - warn_report("Guest not yet converted to MTTCG - "
> - "you may get unexpected results");
> -#endif
> + if (target_supports_mttcg()) {
I started smth similar but then realized this call has to be per target,
so put my work on hold. My plan is to have a single common tcg
accelerator framework, having target-specific code handled by vcpu
dispatchers. Is your plan to have each target link its own tcg?
> + warn_report("Guest not yet converted to MTTCG - "
> + "you may get unexpected results");
> + }
> s->mttcg_enabled = true;
> }
> } else if (strcmp(value, "single") == 0) {
^ permalink raw reply [flat|nested] 83+ messages in thread
* Re: [RFC PATCH 26/34] Wrap target macros in functions
2024-01-19 14:40 ` [RFC PATCH 26/34] Wrap target macros in functions Anton Johansson via
@ 2024-01-23 11:50 ` Philippe Mathieu-Daudé
2024-01-23 12:12 ` Anton Johansson via
0 siblings, 1 reply; 83+ messages in thread
From: Philippe Mathieu-Daudé @ 2024-01-23 11:50 UTC (permalink / raw)
To: Anton Johansson, qemu-devel; +Cc: ale, richard.henderson
Hi Anton,
On 19/1/24 15:40, Anton Johansson wrote:
> Adds wrapper functions around common target specific macros required by
> accel/tcg.
>
> Signed-off-by: Anton Johansson <anjo@rev.ng>
> ---
> include/hw/core/cpu.h | 9 +++++++
> cpu-target.c | 62 +++++++++++++++++++++++++++++++++++++++++++
> 2 files changed, 71 insertions(+)
>
> diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
> index 57d100c203..a2d65c1d7a 100644
> --- a/include/hw/core/cpu.h
> +++ b/include/hw/core/cpu.h
> @@ -26,6 +26,7 @@
> #include "exec/vaddr.h"
> #include "exec/memattrs.h"
> #include "exec/tlb-common.h"
> +#include "exec/memop.h"
> #include "qapi/qapi-types-run-state.h"
> #include "qemu/bitmap.h"
> #include "qemu/rcu_queue.h"
> @@ -1164,6 +1165,14 @@ void cpu_exec_unrealizefn(CPUState *cpu);
> * what you are doing!
> */
> bool target_words_bigendian(void);
> +bool target_supports_mttcg(void);
> +bool target_has_precise_smc(void);
> +int target_long_bits(void);
> +int target_phys_addr_space_bits(void);
> +uint8_t target_insn_start_words(void);
> +uint8_t target_default_memory_order(void);
> +uint8_t target_tlb_dyn_max_bits(void);
> +MemOp target_endian_memory_order(void);
None of these helpers take argument. I don't understand
how they can be called in heterogeneous context.
> const char *target_name(void);
>
> diff --git a/cpu-target.c b/cpu-target.c
> index 1a8e730bed..6b67af7a51 100644
> --- a/cpu-target.c
> +++ b/cpu-target.c
> @@ -39,10 +39,13 @@
> #include "exec/tb-flush.h"
> #include "exec/translate-all.h"
> #include "exec/log.h"
> +#include "exec/cpu-defs.h"
> #include "hw/core/accel-cpu.h"
> #include "trace/trace-root.h"
> #include "qemu/accel.h"
> #include "qemu/plugin.h"
> +#include "tcg/tcg-mo.h"
> +#include "tcg/insn-start-words.h"
>
> uintptr_t qemu_host_page_size;
> intptr_t qemu_host_page_mask;
> @@ -416,6 +419,65 @@ bool target_words_bigendian(void)
> return TARGET_BIG_ENDIAN;
> }
>
> +bool target_supports_mttcg(void)
> +{
> +#ifdef TARGET_SUPPORTS_MTTCG
> +# ifndef TCG_GUEST_DEFAULT_MO
> +# error "TARGET_SUPPORTS_MTTCG without TCG_GUEST_DEFAULT_MO"
> +# endif
> + return true;
> +#else
> + return false;
> +#endif
> +}
> +
> +bool target_has_precise_smc(void)
> +{
> +#ifdef TARGET_HAS_PRECISE_SMC
> + return true;
> +#else
> + return false;
> +#endif
> +}
> +
> +int target_long_bits(void)
> +{
> + return TARGET_LONG_BITS;
> +}
> +
> +int target_phys_addr_space_bits(void)
> +{
> + return TARGET_PHYS_ADDR_SPACE_BITS;
> +}
> +
> +uint8_t target_insn_start_words(void)
> +{
> + return TARGET_INSN_START_WORDS;
> +}
> +
> +uint8_t target_default_memory_order(void)
> +{
> +#ifdef TCG_GUEST_DEFAULT_MO
> + return TCG_GUEST_DEFAULT_MO;
> +#else
> + return TCG_MO_ALL;
> +#endif
> +}
> +
> +MemOp target_endian_memory_order(void)
> +{
> + return MO_TE;
> +}
> +
> +uint8_t target_tlb_dyn_max_bits(void)
> +{
> +#if defined(CONFIG_SOFTMMU) && defined(CONFIG_TCG)
> + return CPU_TLB_DYN_MAX_BITS;
> +#else
> + return 0;
> +#endif
> +}
> +
> const char *target_name(void)
> {
> return TARGET_NAME;
^ permalink raw reply [flat|nested] 83+ messages in thread
* Re: [RFC PATCH 30/34] accel/tcg: Make tcg-all.c target indpendent
2024-01-23 11:45 ` Philippe Mathieu-Daudé
@ 2024-01-23 12:03 ` Anton Johansson via
0 siblings, 0 replies; 83+ messages in thread
From: Anton Johansson via @ 2024-01-23 12:03 UTC (permalink / raw)
To: Philippe Mathieu-Daudé; +Cc: qemu-devel, ale, richard.henderson
On 23/01/24, Philippe Mathieu-Daudé wrote:
> Hi Anton,
>
> On 19/1/24 15:40, Anton Johansson wrote:
> > Uses target_supports_mttcg() and target_long_bits() to turn ifdefs into
> > runtime branches.
> >
> > Signed-off-by: Anton Johansson <anjo@rev.ng>
> > ---
> > accel/tcg/tcg-all.c | 25 +++++++++----------------
> > 1 file changed, 9 insertions(+), 16 deletions(-)
>
>
> > static void tcg_accel_instance_init(Object *obj)
> > @@ -137,17 +129,18 @@ static char *tcg_get_thread(Object *obj, Error **errp)
> > static void tcg_set_thread(Object *obj, const char *value, Error **errp)
> > {
> > TCGState *s = TCG_STATE(obj);
> > + const bool oversized_guest = target_long_bits() > TCG_TARGET_REG_BITS;
> > if (strcmp(value, "multi") == 0) {
> > - if (TCG_OVERSIZED_GUEST) {
> > + if (oversized_guest) {
> > error_setg(errp, "No MTTCG when guest word size > hosts");
> > } else if (icount_enabled()) {
> > error_setg(errp, "No MTTCG when icount is enabled");
> > } else {
> > -#ifndef TARGET_SUPPORTS_MTTCG
> > - warn_report("Guest not yet converted to MTTCG - "
> > - "you may get unexpected results");
> > -#endif
> > + if (target_supports_mttcg()) {
>
> I started smth similar but then realized this call has to be per target,
> so put my work on hold. My plan is to have a single common tcg
> accelerator framework, having target-specific code handled by vcpu
> dispatchers. Is your plan to have each target link its own tcg?
Yes I was leaning towards one tcg per target, but hadn't put much
thought into it. I think your approach is better. This patchset was
primarily focused on getting accl/tcg/ to compile once, with
heterogeneous stuff coming down the line. IMO it becomes a bit easier to
see what target-specific information we really need.
What do you think of a simple TargetConfig struct for information such
as target_supports_mttcg() and the other functions introduced in
cpu-target.c? We probably need dispatcher for other stuff but I think we
can get quite far with struct.
^ permalink raw reply [flat|nested] 83+ messages in thread
* Re: [RFC PATCH 01/34] target: [PAGE_VARY] Use PAGE_VARY for all softmmu targets
2024-01-19 16:05 ` Philippe Mathieu-Daudé
@ 2024-01-23 12:09 ` Anton Johansson via
0 siblings, 0 replies; 83+ messages in thread
From: Anton Johansson via @ 2024-01-23 12:09 UTC (permalink / raw)
To: Philippe Mathieu-Daudé; +Cc: qemu-devel, ale, richard.henderson
On 19/01/24, Philippe Mathieu-Daudé wrote:
> On 19/1/24 15:39, Anton Johansson wrote:
> > Allows for future commits to use TargetPageBits to access page bits and
> > mask, thus making TARGET_PAGE_* independent of softmmu target.
> >
> > In the future, this will also be important fo allowing heterogeneous CPUs
> > on the same board.
>
> Yeah I carry an almost similar patch :)
>
> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Suspected there might be some overlap with this patchset:) Do you have
branch I could rebase on to remove conflicts?
^ permalink raw reply [flat|nested] 83+ messages in thread
* Re: [RFC PATCH 26/34] Wrap target macros in functions
2024-01-23 11:50 ` Philippe Mathieu-Daudé
@ 2024-01-23 12:12 ` Anton Johansson via
2024-01-24 2:50 ` Richard Henderson
0 siblings, 1 reply; 83+ messages in thread
From: Anton Johansson via @ 2024-01-23 12:12 UTC (permalink / raw)
To: Philippe Mathieu-Daudé; +Cc: qemu-devel, ale, richard.henderson
On 23/01/24, Philippe Mathieu-Daudé wrote:
> Hi Anton,
>
> On 19/1/24 15:40, Anton Johansson wrote:
> > Adds wrapper functions around common target specific macros required by
> > accel/tcg.
> >
> > Signed-off-by: Anton Johansson <anjo@rev.ng>
> > ---
> > include/hw/core/cpu.h | 9 +++++++
> > cpu-target.c | 62 +++++++++++++++++++++++++++++++++++++++++++
> > 2 files changed, 71 insertions(+)
> >
> > diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
> > index 57d100c203..a2d65c1d7a 100644
> > --- a/include/hw/core/cpu.h
> > +++ b/include/hw/core/cpu.h
> > @@ -26,6 +26,7 @@
> > #include "exec/vaddr.h"
> > #include "exec/memattrs.h"
> > #include "exec/tlb-common.h"
> > +#include "exec/memop.h"
> > #include "qapi/qapi-types-run-state.h"
> > #include "qemu/bitmap.h"
> > #include "qemu/rcu_queue.h"
> > @@ -1164,6 +1165,14 @@ void cpu_exec_unrealizefn(CPUState *cpu);
> > * what you are doing!
> > */
> > bool target_words_bigendian(void);
> > +bool target_supports_mttcg(void);
> > +bool target_has_precise_smc(void);
> > +int target_long_bits(void);
> > +int target_phys_addr_space_bits(void);
> > +uint8_t target_insn_start_words(void);
> > +uint8_t target_default_memory_order(void);
> > +uint8_t target_tlb_dyn_max_bits(void);
> > +MemOp target_endian_memory_order(void);
>
> None of these helpers take argument. I don't understand
> how they can be called in heterogeneous context.
No you're right, I was focused mostly on getting accel/tcg to compile
with hetrogeneous being a goal downt the line.
I like the idea of moving these fields to a struct filled out per
target, but dispatching would also work.
^ permalink raw reply [flat|nested] 83+ messages in thread
* Re: [RFC PATCH 02/34] target: [PAGE_VARY] Move TARGET_PAGE_BITS_MIN to TargetPageBits
2024-01-19 14:39 ` [RFC PATCH 02/34] target: [PAGE_VARY] Move TARGET_PAGE_BITS_MIN to TargetPageBits Anton Johansson via
@ 2024-01-23 16:33 ` Richard Henderson
0 siblings, 0 replies; 83+ messages in thread
From: Richard Henderson @ 2024-01-23 16:33 UTC (permalink / raw)
To: Anton Johansson, qemu-devel; +Cc: ale, philmd
On 1/20/24 00:39, Anton Johansson wrote:
> TARGET_PAGE_BITS_MIN is now defined as target_page.bits_min when
> PAGE_VARY is used, similar to other TARGET_PAGE_* macros. We still pick
> whatever minimum the target specifies, however in a heterogeneous
> context we would want the maximum of all target_page.bits_min.
Do we? Or do we need to reject different minimums as incompatible?
r~
^ permalink raw reply [flat|nested] 83+ messages in thread
* Re: [RFC PATCH 03/34] exec: [PAGE_VARY] Move TARGET_PAGE_BITS_VARY to common header
2024-01-19 14:39 ` [RFC PATCH 03/34] exec: [PAGE_VARY] Move TARGET_PAGE_BITS_VARY to common header Anton Johansson via
@ 2024-01-23 22:20 ` Richard Henderson
0 siblings, 0 replies; 83+ messages in thread
From: Richard Henderson @ 2024-01-23 22:20 UTC (permalink / raw)
To: Anton Johansson, qemu-devel; +Cc: ale, philmd
On 1/20/24 00:39, Anton Johansson wrote:
> We need to be able access the variable TARGET_PAGE_* macros in a
> target-independent manner.
>
> Signed-off-by: Anton Johansson <anjo@rev.ng>
I think you should pull all of these macros into a separate header.
The split here is a bit confusing.
r~
^ permalink raw reply [flat|nested] 83+ messages in thread
* Re: [RFC PATCH 04/34] exec: [PAGE_VARY] Unpoison TARGET_PAGE_* macros for system mode
2024-01-19 14:39 ` [RFC PATCH 04/34] exec: [PAGE_VARY] Unpoison TARGET_PAGE_* macros for system mode Anton Johansson via
@ 2024-01-23 22:20 ` Richard Henderson
0 siblings, 0 replies; 83+ messages in thread
From: Richard Henderson @ 2024-01-23 22:20 UTC (permalink / raw)
To: Anton Johansson, qemu-devel; +Cc: ale, philmd
On 1/20/24 00:39, Anton Johansson wrote:
> TARGET_PAGE_* are now target-independent for softmmu targets, and can
> safely be accessed common code.
>
> Signed-off-by: Anton Johansson <anjo@rev.ng>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 83+ messages in thread
* Re: [RFC PATCH 05/34] target/tricore: [VADDR] Use target_ulong for EA
2024-01-19 14:39 ` [RFC PATCH 05/34] target/tricore: [VADDR] Use target_ulong for EA Anton Johansson via
@ 2024-01-23 22:29 ` Richard Henderson
2024-01-27 8:26 ` Richard Henderson
1 sibling, 0 replies; 83+ messages in thread
From: Richard Henderson @ 2024-01-23 22:29 UTC (permalink / raw)
To: Anton Johansson, qemu-devel; +Cc: ale, philmd
On 1/20/24 00:39, Anton Johansson wrote:
> Prepares target for typedef'ing abi_ptr to vaddr. Fixes sign extension
> bug that would result from abi_ptr being unsigned in the future.
>
> Necessary to make memory access function signatures target agnostic.
>
> Signed-off-by: Anton Johansson<anjo@rev.ng>
> ---
> target/tricore/op_helper.c | 8 ++++----
> 1 file changed, 4 insertions(+), 4 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 83+ messages in thread
* Re: [RFC PATCH 06/34] exec: [VADDR] Move vaddr defines to separate file
2024-01-19 14:39 ` [RFC PATCH 06/34] exec: [VADDR] Move vaddr defines to separate file Anton Johansson via
@ 2024-01-23 22:33 ` Richard Henderson
2024-01-27 8:36 ` Richard Henderson
1 sibling, 0 replies; 83+ messages in thread
From: Richard Henderson @ 2024-01-23 22:33 UTC (permalink / raw)
To: Anton Johansson, qemu-devel; +Cc: ale, philmd
On 1/20/24 00:39, Anton Johansson wrote:
> +++ b/include/exec/vaddr.h
> @@ -0,0 +1,18 @@
> +/* Define vaddr if it exists. */
s/if it exists//
Need a license line here. Otherwise.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 83+ messages in thread
* Re: [RFC PATCH 07/34] hw/core: [VADDR] Include vaddr.h from cpu.h
2024-01-19 14:39 ` [RFC PATCH 07/34] hw/core: [VADDR] Include vaddr.h from cpu.h Anton Johansson via
@ 2024-01-23 22:57 ` Richard Henderson
2024-01-27 8:48 ` Richard Henderson
1 sibling, 0 replies; 83+ messages in thread
From: Richard Henderson @ 2024-01-23 22:57 UTC (permalink / raw)
To: Anton Johansson, qemu-devel; +Cc: ale, philmd
On 1/20/24 00:39, Anton Johansson wrote:
> cpu-common.h is only needed for vaddr
>
> Signed-off-by: Anton Johansson <anjo@rev.ng>
> ---
> include/hw/core/cpu.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 83+ messages in thread
* Re: [RFC PATCH 08/34] target: [VADDR] Use vaddr in gen_intermediate_code
2024-01-19 14:39 ` [RFC PATCH 08/34] target: [VADDR] Use vaddr in gen_intermediate_code Anton Johansson via
@ 2024-01-23 23:13 ` Richard Henderson
2024-01-27 9:05 ` Richard Henderson
1 sibling, 0 replies; 83+ messages in thread
From: Richard Henderson @ 2024-01-23 23:13 UTC (permalink / raw)
To: Anton Johansson, qemu-devel; +Cc: ale, philmd
On 1/20/24 00:39, Anton Johansson wrote:
> Makes gen_intermediate_code() signature target agnostic so the function
> can be called from accel/tcg/translate-all.c without target specifics.
>
> Signed-off-by: Anton Johansson<anjo@rev.ng>
> ---
> include/exec/translator.h | 2 +-
> target/alpha/translate.c | 2 +-
> target/arm/tcg/translate.c | 2 +-
> target/avr/translate.c | 2 +-
> target/cris/translate.c | 2 +-
> target/hexagon/translate.c | 2 +-
> target/hppa/translate.c | 2 +-
> target/i386/tcg/translate.c | 2 +-
> target/loongarch/translate.c | 2 +-
> target/m68k/translate.c | 2 +-
> target/microblaze/translate.c | 2 +-
> target/mips/tcg/translate.c | 2 +-
> target/nios2/translate.c | 2 +-
> target/openrisc/translate.c | 2 +-
> target/ppc/translate.c | 2 +-
> target/riscv/translate.c | 2 +-
> target/rx/translate.c | 2 +-
> target/s390x/tcg/translate.c | 2 +-
> target/sh4/translate.c | 2 +-
> target/sparc/translate.c | 2 +-
> target/tricore/translate.c | 2 +-
> target/xtensa/translate.c | 2 +-
> 22 files changed, 22 insertions(+), 22 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 83+ messages in thread
* Re: [RFC PATCH 09/34] exec: [VADDR] Use vaddr in DisasContextBase for virtual addresses
2024-01-19 14:39 ` [RFC PATCH 09/34] exec: [VADDR] Use vaddr in DisasContextBase for virtual addresses Anton Johansson via
@ 2024-01-23 23:22 ` Richard Henderson
2024-01-27 9:33 ` Richard Henderson
1 sibling, 0 replies; 83+ messages in thread
From: Richard Henderson @ 2024-01-23 23:22 UTC (permalink / raw)
To: Anton Johansson, qemu-devel; +Cc: ale, philmd
On 1/20/24 00:39, Anton Johansson wrote:
> Updates target/ QEMU_LOG macros to use VADDR_PRIx for printing updated
> DisasContextBase fields.
>
> Signed-off-by: Anton Johansson<anjo@rev.ng>
> ---
> include/exec/translator.h | 6 +++---
> target/mips/tcg/translate.h | 3 ++-
> target/hexagon/translate.c | 3 ++-
> target/m68k/translate.c | 2 +-
> target/mips/tcg/translate.c | 12 ++++++------
> 5 files changed, 14 insertions(+), 12 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 83+ messages in thread
* Re: [RFC PATCH 10/34] exec: [VADDR] typedef abi_ptr to vaddr
2024-01-19 14:40 ` [RFC PATCH 10/34] exec: [VADDR] typedef abi_ptr to vaddr Anton Johansson via
@ 2024-01-23 23:29 ` Richard Henderson
2024-01-27 9:42 ` Richard Henderson
1 sibling, 0 replies; 83+ messages in thread
From: Richard Henderson @ 2024-01-23 23:29 UTC (permalink / raw)
To: Anton Johansson, qemu-devel; +Cc: ale, philmd
On 1/20/24 00:40, Anton Johansson wrote:
> Signed-off-by: Anton Johansson <anjo@rev.ng>
> ---
> include/exec/cpu_ldst.h | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/include/exec/cpu_ldst.h b/include/exec/cpu_ldst.h
> index 6061e33ac9..eb8f3f0595 100644
> --- a/include/exec/cpu_ldst.h
> +++ b/include/exec/cpu_ldst.h
> @@ -121,8 +121,8 @@ static inline bool guest_range_valid_untagged(abi_ulong start, abi_ulong len)
> h2g_nocheck(x); \
> })
> #else
> -typedef target_ulong abi_ptr;
> -#define TARGET_ABI_FMT_ptr TARGET_FMT_lx
> +typedef vaddr abi_ptr;
> +#define TARGET_ABI_FMT_ptr VADDR_PRIx
> #endif
>
> uint32_t cpu_ldub_data(CPUArchState *env, abi_ptr ptr);
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 83+ messages in thread
* Re: [RFC PATCH 12/34] target: Uninline cpu_mmu_index()
2024-01-19 14:40 ` [RFC PATCH 12/34] target: Uninline cpu_mmu_index() Anton Johansson via
@ 2024-01-23 23:40 ` Richard Henderson
2024-01-27 10:10 ` Richard Henderson
1 sibling, 0 replies; 83+ messages in thread
From: Richard Henderson @ 2024-01-23 23:40 UTC (permalink / raw)
To: Anton Johansson, qemu-devel; +Cc: ale, philmd
On 1/20/24 00:40, Anton Johansson wrote:
> --- a/target/mips/cpu.h
> +++ b/target/mips/cpu.h
> @@ -1233,19 +1233,7 @@ uint32_t cpu_rddsp(uint32_t mask_num, CPUMIPSState *env);
> */
> #define MMU_USER_IDX 2
>
> -static inline int hflags_mmu_index(uint32_t hflags)
> -{
> - if (hflags & MIPS_HFLAG_ERL) {
> - return 3; /* ERL */
> - } else {
> - return hflags & MIPS_HFLAG_KSU;
> - }
> -}
Unrelated. All you need to move is...
> -
> -static inline int cpu_mmu_index(CPUMIPSState *env, bool ifetch)
> -{
> - return hflags_mmu_index(env->hflags);
> -}
... this.
Otherwise,
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 83+ messages in thread
* Re: [RFC PATCH 13/34] target: Uninline cpu_get_tb_cpu_state()
2024-01-19 14:40 ` [RFC PATCH 13/34] target: Uninline cpu_get_tb_cpu_state() Anton Johansson via
@ 2024-01-23 23:53 ` Richard Henderson
2024-01-27 11:21 ` Richard Henderson
1 sibling, 0 replies; 83+ messages in thread
From: Richard Henderson @ 2024-01-23 23:53 UTC (permalink / raw)
To: Anton Johansson, qemu-devel; +Cc: ale, philmd
On 1/20/24 00:40, Anton Johansson wrote:
> Required to compile accel/tcg/translate-all.c once for softmmu targets.
> The function gets quite big for some targets so uninlining makes sense.
>
> Signed-off-by: Anton Johansson<anjo@rev.ng>
> ---
> include/exec/cpu-common.h | 4 +++
> target/alpha/cpu.h | 11 -------
> target/arm/cpu.h | 3 --
> target/avr/cpu.h | 18 -----------
> target/cris/cpu.h | 10 ------
> target/hexagon/cpu.h | 12 -------
> target/hppa/cpu.h | 43 -------------------------
> target/i386/cpu.h | 9 ------
> target/loongarch/cpu.h | 11 -------
> target/m68k/cpu.h | 16 ---------
> target/microblaze/cpu.h | 8 -----
> target/mips/cpu.h | 9 ------
> target/nios2/cpu.h | 12 -------
> target/openrisc/cpu.h | 10 ------
> target/ppc/cpu.h | 13 --------
> target/riscv/cpu.h | 3 --
> target/rx/cpu.h | 9 ------
> target/s390x/cpu.h | 22 -------------
> target/sh4/cpu.h | 15 ---------
> target/sparc/cpu.h | 35 --------------------
> target/tricore/cpu.h | 12 -------
> target/xtensa/cpu.h | 68 ---------------------------------------
> target/alpha/cpu.c | 11 +++++++
> target/avr/cpu.c | 18 +++++++++++
> target/cris/cpu.c | 10 ++++++
> target/hexagon/cpu.c | 12 +++++++
> target/hppa/cpu.c | 47 +++++++++++++++++++++++++++
> target/i386/cpu.c | 9 ++++++
> target/loongarch/cpu.c | 11 +++++++
> target/m68k/cpu.c | 16 +++++++++
> target/microblaze/cpu.c | 7 ++++
> target/mips/cpu.c | 9 ++++++
> target/nios2/cpu.c | 12 +++++++
> target/openrisc/cpu.c | 10 ++++++
> target/ppc/cpu.c | 11 +++++++
> target/rx/cpu.c | 9 ++++++
> target/s390x/cpu.c | 24 ++++++++++++++
> target/sh4/cpu.c | 15 +++++++++
> target/sparc/cpu.c | 35 ++++++++++++++++++++
> target/tricore/cpu.c | 12 +++++++
> target/xtensa/cpu.c | 68 +++++++++++++++++++++++++++++++++++++++
> 41 files changed, 350 insertions(+), 349 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 83+ messages in thread
* Re: [RFC PATCH 14/34] exec: [CPUTLB] Move PAGE_* macros to common header
2024-01-19 14:40 ` [RFC PATCH 14/34] exec: [CPUTLB] Move PAGE_* macros to common header Anton Johansson via
@ 2024-01-23 23:54 ` Richard Henderson
2024-01-27 7:53 ` Richard Henderson
0 siblings, 1 reply; 83+ messages in thread
From: Richard Henderson @ 2024-01-23 23:54 UTC (permalink / raw)
To: Anton Johansson, qemu-devel; +Cc: ale, philmd
On 1/20/24 00:40, Anton Johansson wrote:
> These don't vary across targets and are used in soon-to-be common code
> (cputlb.c).
>
> Signed-off-by: Anton Johansson<anjo@rev.ng>
> ---
> include/exec/cpu-all.h | 24 ------------------------
> include/exec/cpu-common.h | 30 ++++++++++++++++++++++++++++++
> 2 files changed, 30 insertions(+), 24 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 83+ messages in thread
* Re: [RFC PATCH 15/34] exec: [CPUTLB] Move TLB_*/tlb_*() to common header
2024-01-19 14:40 ` [RFC PATCH 15/34] exec: [CPUTLB] Move TLB_*/tlb_*() " Anton Johansson via
@ 2024-01-24 0:09 ` Richard Henderson
0 siblings, 0 replies; 83+ messages in thread
From: Richard Henderson @ 2024-01-24 0:09 UTC (permalink / raw)
To: Anton Johansson, qemu-devel; +Cc: ale, philmd
On 1/20/24 00:40, Anton Johansson wrote:
> TLB_* macros and tlb_*() functions are target independent, move to cpu-common.h.
>
> Signed-off-by: Anton Johansson<anjo@rev.ng>
> ---
> include/exec/cpu-all.h | 81 --------------------------------------
> include/exec/cpu-common.h | 83 +++++++++++++++++++++++++++++++++++++++
> 2 files changed, 83 insertions(+), 81 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 83+ messages in thread
* Re: [RFC PATCH 16/34] exec: [CPUTLB] Move cpu_*()/cpu_env() to common header
2024-01-19 14:40 ` [RFC PATCH 16/34] exec: [CPUTLB] Move cpu_*()/cpu_env() " Anton Johansson via
@ 2024-01-24 0:15 ` Richard Henderson
2024-01-27 22:14 ` Richard Henderson
1 sibling, 0 replies; 83+ messages in thread
From: Richard Henderson @ 2024-01-24 0:15 UTC (permalink / raw)
To: Anton Johansson, qemu-devel; +Cc: ale, philmd
On 1/20/24 00:40, Anton Johansson wrote:
> Functions are target independent.
>
> Signed-off-by: Anton Johansson<anjo@rev.ng>
> ---
> include/exec/cpu-all.h | 25 -------------------------
> include/exec/cpu-common.h | 25 +++++++++++++++++++++++++
> 2 files changed, 25 insertions(+), 25 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 83+ messages in thread
* Re: [RFC PATCH 17/34] hw/core: [CPUTLB] Move target specifics to end of TCGCPUOps
2024-01-19 14:40 ` [RFC PATCH 17/34] hw/core: [CPUTLB] Move target specifics to end of TCGCPUOps Anton Johansson via
@ 2024-01-24 0:43 ` Richard Henderson
2024-01-28 0:37 ` Richard Henderson
0 siblings, 1 reply; 83+ messages in thread
From: Richard Henderson @ 2024-01-24 0:43 UTC (permalink / raw)
To: Anton Johansson, qemu-devel; +Cc: ale, philmd
On 1/20/24 00:40, Anton Johansson wrote:
> TCGCPUOps contains an extra function pointer when included with
> NEED_CPU_H, these are moved from the middle to the end of the struct. As
> such offsets to target independent function pointers don't vary in
> target specific and independent code.
>
> [Move target specfic fields to separate struct?]
>
> Signed-off-by: Anton Johansson <anjo@rev.ng>
Or make these unconditional. Move fake_user_interrupt into the CONFIG_USER_ONLY block and
do_interrupt into the system block.
r~
^ permalink raw reply [flat|nested] 83+ messages in thread
* Re: [RFC PATCH 18/34] accel/stubs: [CPUTLB] Move xen.h stubs to xen-stub.c
2024-01-19 14:40 ` [RFC PATCH 18/34] accel/stubs: [CPUTLB] Move xen.h stubs to xen-stub.c Anton Johansson via
@ 2024-01-24 1:04 ` Richard Henderson
0 siblings, 0 replies; 83+ messages in thread
From: Richard Henderson @ 2024-01-24 1:04 UTC (permalink / raw)
To: Anton Johansson, qemu-devel; +Cc: ale, philmd
On 1/20/24 00:40, Anton Johansson wrote:
> --- a/accel/stubs/xen-stub.c
> +++ b/accel/stubs/xen-stub.c
> @@ -14,3 +14,15 @@ bool xen_allowed;
> void qmp_xen_set_global_dirty_log(bool enable, Error **errp)
> {
> }
> +
> +#ifndef CONFIG_USER_ONLY
> +void xen_hvm_modified_memory(ram_addr_t start, ram_addr_t length)
No need for ifdef here, since this file is in system_stubs_ss.
Otherwise,
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 83+ messages in thread
* Re: [RFC PATCH 19/34] accel/tcg: [CPUTLB] Use TCGContext.addr_type instead of TARGET_LONG_BITS
2024-01-19 14:40 ` [RFC PATCH 19/34] accel/tcg: [CPUTLB] Use TCGContext.addr_type instead of TARGET_LONG_BITS Anton Johansson via
@ 2024-01-24 1:18 ` Richard Henderson
0 siblings, 0 replies; 83+ messages in thread
From: Richard Henderson @ 2024-01-24 1:18 UTC (permalink / raw)
To: Anton Johansson, qemu-devel; +Cc: ale, philmd
On 1/20/24 00:40, Anton Johansson wrote:
> @@ -815,12 +815,13 @@ void tlb_flush_range_by_mmuidx(CPUState *cpu, vaddr addr,
> unsigned bits)
> {
> TLBFlushRangeData d;
> + const unsigned long_bits = (tcg_ctx->addr_type == TCG_TYPE_I32) ? 32 : 64;
No, this value isn't initialized at the correct time.
We are out of scope here.
r~
^ permalink raw reply [flat|nested] 83+ messages in thread
* Re: [RFC PATCH 20/34] accel/tcg: [CPUTLB] Use TCGContext.guest_mo for memory ordering
2024-01-19 14:40 ` [RFC PATCH 20/34] accel/tcg: [CPUTLB] Use TCGContext.guest_mo for memory ordering Anton Johansson via
@ 2024-01-24 1:21 ` Richard Henderson
0 siblings, 0 replies; 83+ messages in thread
From: Richard Henderson @ 2024-01-24 1:21 UTC (permalink / raw)
To: Anton Johansson, qemu-devel; +Cc: ale, philmd
On 1/20/24 00:40, Anton Johansson wrote:
> +#define tcg_req_mo(type) \
> + ((type) & tcg_ctx->guest_mo & ~TCG_TARGET_DEFAULT_MO)
Again, no, value is out of scope.
r~
^ permalink raw reply [flat|nested] 83+ messages in thread
* Re: [RFC PATCH 21/34] accel/tcg: [CPUTLB] Use tcg_ctx->tlb_dyn_max_bits
2024-01-19 14:40 ` [RFC PATCH 21/34] accel/tcg: [CPUTLB] Use tcg_ctx->tlb_dyn_max_bits Anton Johansson via
@ 2024-01-24 1:23 ` Richard Henderson
0 siblings, 0 replies; 83+ messages in thread
From: Richard Henderson @ 2024-01-24 1:23 UTC (permalink / raw)
To: Anton Johansson, qemu-devel; +Cc: ale, philmd
On 1/20/24 00:40, Anton Johansson wrote:
> @@ -172,7 +172,7 @@ static void tlb_mmu_resize_locked(CPUTLBDesc *desc, CPUTLBDescFast *fast,
> rate = desc->window_max_entries * 100 / old_size;
>
> if (rate > 70) {
> - new_size = MIN(old_size << 1, 1 << CPU_TLB_DYN_MAX_BITS);
> + new_size = MIN(old_size << 1, 1 << tcg_ctx->tlb_dyn_max_bits);
Out of scope.
r~
^ permalink raw reply [flat|nested] 83+ messages in thread
* Re: [RFC PATCH 22/34] accel/tcg: [CPUTLB] Move CPU_TLB_DYN_[DEFAULT|MIN]* to cputlb.c
2024-01-19 14:40 ` [RFC PATCH 22/34] accel/tcg: [CPUTLB] Move CPU_TLB_DYN_[DEFAULT|MIN]* to cputlb.c Anton Johansson via
@ 2024-01-24 1:24 ` Richard Henderson
0 siblings, 0 replies; 83+ messages in thread
From: Richard Henderson @ 2024-01-24 1:24 UTC (permalink / raw)
To: Anton Johansson, qemu-devel; +Cc: ale, philmd
On 1/20/24 00:40, Anton Johansson wrote:
> These macros are only used for softmmu targets and only used in
> cputlb.c, move definitions there.
>
> Signed-off-by: Anton Johansson<anjo@rev.ng>
> ---
> include/exec/cpu-defs.h | 3 ---
> accel/tcg/cputlb.c | 3 +++
> 2 files changed, 3 insertions(+), 3 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 83+ messages in thread
* Re: [RFC PATCH 23/34] tcg: [CPUTLB] Add `mo_te` field to TCGContext
2024-01-19 14:40 ` [RFC PATCH 23/34] tcg: [CPUTLB] Add `mo_te` field to TCGContext Anton Johansson via
@ 2024-01-24 1:50 ` Richard Henderson
0 siblings, 0 replies; 83+ messages in thread
From: Richard Henderson @ 2024-01-24 1:50 UTC (permalink / raw)
To: Anton Johansson, qemu-devel; +Cc: ale, philmd
On 1/20/24 00:40, Anton Johansson wrote:
> Required by cpu_ldub_code() and friends in cputlb.c to access the MO_TE
> MemOp in a target-independent way.
>
> Signed-off-by: Anton Johansson <anjo@rev.ng>
> ---
> include/tcg/tcg.h | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h
> index 7743868dc9..4ca626aeae 100644
> --- a/include/tcg/tcg.h
> +++ b/include/tcg/tcg.h
> @@ -489,6 +489,7 @@ struct TCGContext {
> TCGType addr_type; /* TCG_TYPE_I32 or TCG_TYPE_I64 */
>
> #ifdef CONFIG_SOFTMMU
> + MemOp mo_te;
> int page_mask;
> uint8_t page_bits;
> uint8_t tlb_dyn_max_bits;
Not the correct scope for this.
r~
^ permalink raw reply [flat|nested] 83+ messages in thread
* Re: [RFC PATCH 26/34] Wrap target macros in functions
2024-01-23 12:12 ` Anton Johansson via
@ 2024-01-24 2:50 ` Richard Henderson
0 siblings, 0 replies; 83+ messages in thread
From: Richard Henderson @ 2024-01-24 2:50 UTC (permalink / raw)
To: Anton Johansson, Philippe Mathieu-Daudé; +Cc: qemu-devel, ale
On 1/23/24 22:12, Anton Johansson wrote:
> On 23/01/24, Philippe Mathieu-Daudé wrote:
>> Hi Anton,
>>
>> On 19/1/24 15:40, Anton Johansson wrote:
>>> Adds wrapper functions around common target specific macros required by
>>> accel/tcg.
>>>
>>> Signed-off-by: Anton Johansson <anjo@rev.ng>
>>> ---
>>> include/hw/core/cpu.h | 9 +++++++
>>> cpu-target.c | 62 +++++++++++++++++++++++++++++++++++++++++++
>>> 2 files changed, 71 insertions(+)
>>>
>>> diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
>>> index 57d100c203..a2d65c1d7a 100644
>>> --- a/include/hw/core/cpu.h
>>> +++ b/include/hw/core/cpu.h
>>> @@ -26,6 +26,7 @@
>>> #include "exec/vaddr.h"
>>> #include "exec/memattrs.h"
>>> #include "exec/tlb-common.h"
>>> +#include "exec/memop.h"
>>> #include "qapi/qapi-types-run-state.h"
>>> #include "qemu/bitmap.h"
>>> #include "qemu/rcu_queue.h"
>>> @@ -1164,6 +1165,14 @@ void cpu_exec_unrealizefn(CPUState *cpu);
>>> * what you are doing!
>>> */
>>> bool target_words_bigendian(void);
>>> +bool target_supports_mttcg(void);
>>> +bool target_has_precise_smc(void);
>>> +int target_long_bits(void);
>>> +int target_phys_addr_space_bits(void);
>>> +uint8_t target_insn_start_words(void);
>>> +uint8_t target_default_memory_order(void);
>>> +uint8_t target_tlb_dyn_max_bits(void);
>>> +MemOp target_endian_memory_order(void);
>>
>> None of these helpers take argument. I don't understand
>> how they can be called in heterogeneous context.
>
> No you're right, I was focused mostly on getting accel/tcg to compile
> with hetrogeneous being a goal downt the line.
>
> I like the idea of moving these fields to a struct filled out per
> target, but dispatching would also work.
All of the bits that you're referencing in TCGContext, outside of compilation, should be
treated the same way. Like Phil, I'd prefer to move these once and get the API right.
r~
^ permalink raw reply [flat|nested] 83+ messages in thread
* Re: [RFC PATCH 27/34] accel/tcg: Make translate-all.c target independent
2024-01-19 14:40 ` [RFC PATCH 27/34] accel/tcg: Make translate-all.c target independent Anton Johansson via
@ 2024-01-24 2:53 ` Richard Henderson
0 siblings, 0 replies; 83+ messages in thread
From: Richard Henderson @ 2024-01-24 2:53 UTC (permalink / raw)
To: Anton Johansson, qemu-devel; +Cc: ale, philmd
On 1/20/24 00:40, Anton Johansson wrote:
> Makes translate-all.c independent of softmmu target by switching
>
> TARGET_LONG_BITS -> target_long_bits()
>
> TARGET_INSN_START_WORDS -> tcg_ctx->insn_start_words,
> target_insn_start_words(),
>
> TCG_GUEST_DEFAULT_MO -> target_default_memory_order()
>
> MO_TE -> target_endian_memory_order()
>
> Signed-off-by: Anton Johansson <anjo@rev.ng>
> ---
> accel/tcg/translate-all.c | 38 ++++++++++++++++++--------------------
> 1 file changed, 18 insertions(+), 20 deletions(-)
>
> diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c
> index 9c981d1750..a3ae0c6910 100644
> --- a/accel/tcg/translate-all.c
> +++ b/accel/tcg/translate-all.c
> @@ -65,7 +65,6 @@
> #include "internal-common.h"
> #include "internal-target.h"
> #include "perf.h"
> -#include "tcg/insn-start-words.h"
>
> TBContext tb_ctx;
>
> @@ -106,7 +105,7 @@ static int64_t decode_sleb128(const uint8_t **pp)
> val |= (int64_t)(byte & 0x7f) << shift;
> shift += 7;
> } while (byte & 0x80);
> - if (shift < TARGET_LONG_BITS && (byte & 0x40)) {
> + if (shift < target_long_bits() && (byte & 0x40)) {
You just make TARGET_PAGE_SIZE etc target independent, right?
So you don't need this? Or is this because of user-only still.
> static int encode_search(TranslationBlock *tb, uint8_t *block)
> {
> + const uint8_t insn_start_words = tcg_ctx->insn_start_words;
Ok, because we're still inside the compilation context.
> static int cpu_unwind_data_from_tb(TranslationBlock *tb, uintptr_t host_pc,
> uint64_t *data)
> {
> + const uint8_t insn_start_words = tcg_ctx->insn_start_words;
Not ok, because we're outside of the compilation context.
r~
^ permalink raw reply [flat|nested] 83+ messages in thread
* Re: [RFC PATCH 28/34] accel/tcg: Make plugin-gen.c target independent
2024-01-19 14:40 ` [RFC PATCH 28/34] accel/tcg: Make plugin-gen.c " Anton Johansson via
@ 2024-01-24 3:02 ` Richard Henderson
0 siblings, 0 replies; 83+ messages in thread
From: Richard Henderson @ 2024-01-24 3:02 UTC (permalink / raw)
To: Anton Johansson, qemu-devel; +Cc: ale, philmd
On 1/20/24 00:40, Anton Johansson wrote:
> Switches computation of offsets into CPUState to use that the offset
> between CPUState and CPUArchState is guaranteed to be sizeof(CPUState).
>
> Signed-off-by: Anton Johansson<anjo@rev.ng>
> ---
> accel/tcg/plugin-gen.c | 15 +++++++--------
> 1 file changed, 7 insertions(+), 8 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 83+ messages in thread
* Re: [RFC PATCH 29/34] accel/tcg: Make tb-maint.c target indpendent
2024-01-19 14:40 ` [RFC PATCH 29/34] accel/tcg: Make tb-maint.c target indpendent Anton Johansson via
@ 2024-01-24 3:10 ` Richard Henderson
0 siblings, 0 replies; 83+ messages in thread
From: Richard Henderson @ 2024-01-24 3:10 UTC (permalink / raw)
To: Anton Johansson, qemu-devel; +Cc: ale, philmd
On 1/20/24 00:40, Anton Johansson wrote:
> Uses target_has_precise_smc() and target_phys_addr_space_bits() to turn
> ifdefs into runtime branches.
>
> Signed-off-by: Anton Johansson <anjo@rev.ng>
> ---
> accel/tcg/tb-maint.c | 47 +++++++++++++++++++++++---------------------
> 1 file changed, 25 insertions(+), 22 deletions(-)
>
> diff --git a/accel/tcg/tb-maint.c b/accel/tcg/tb-maint.c
> index b194f8f065..fdc3a30d0d 100644
> --- a/accel/tcg/tb-maint.c
> +++ b/accel/tcg/tb-maint.c
> @@ -148,14 +148,6 @@ static PageForEachNext foreach_tb_next(PageForEachNext tb,
> }
>
> #else
> -/*
> - * In system mode we want L1_MAP to be based on ram offsets.
> - */
> -#if HOST_LONG_BITS < TARGET_PHYS_ADDR_SPACE_BITS
> -# define L1_MAP_ADDR_SPACE_BITS HOST_LONG_BITS
> -#else
> -# define L1_MAP_ADDR_SPACE_BITS TARGET_PHYS_ADDR_SPACE_BITS
> -#endif
I'm not keen on this. We can make this target independent in several ways:
(1) Use fixed constants that cover all 64 phys addr bits,
(2) Use a different data structure entirely (e.g. IntervalTree).
Preserving the existing data structure, using variables, seems like a poor choice.
> @@ -1045,14 +1048,15 @@ bool tb_invalidate_phys_page_unwind(tb_page_addr_t addr, uintptr_t pc)
> TranslationBlock *tb;
> PageForEachNext n;
> tb_page_addr_t last;
> + const bool has_precise_smc = target_has_precise_smc();
>
> /*
> * Without precise smc semantics, or when outside of a TB,
> * we can skip to invalidate.
> */
> -#ifndef TARGET_HAS_PRECISE_SMC
> - pc = 0;
> -#endif
> + if (!has_precise_smc) {
> + pc = 0;
> + }
Ok to this part. Split it out.
r~
^ permalink raw reply [flat|nested] 83+ messages in thread
* Re: [RFC PATCH 30/34] accel/tcg: Make tcg-all.c target indpendent
2024-01-19 14:40 ` [RFC PATCH 30/34] accel/tcg: Make tcg-all.c " Anton Johansson via
2024-01-23 11:45 ` Philippe Mathieu-Daudé
@ 2024-01-24 3:13 ` Richard Henderson
1 sibling, 0 replies; 83+ messages in thread
From: Richard Henderson @ 2024-01-24 3:13 UTC (permalink / raw)
To: Anton Johansson, qemu-devel; +Cc: ale, philmd
On 1/20/24 00:40, Anton Johansson wrote:
> Uses target_supports_mttcg() and target_long_bits() to turn ifdefs into
> runtime branches.
>
> Signed-off-by: Anton Johansson <anjo@rev.ng>
> ---
> accel/tcg/tcg-all.c | 25 +++++++++----------------
> 1 file changed, 9 insertions(+), 16 deletions(-)
>
> diff --git a/accel/tcg/tcg-all.c b/accel/tcg/tcg-all.c
> index a40e0aee37..b8e920e3a8 100644
> --- a/accel/tcg/tcg-all.c
> +++ b/accel/tcg/tcg-all.c
> @@ -28,7 +28,6 @@
> #include "exec/replay-core.h"
> #include "sysemu/cpu-timers.h"
> #include "tcg/tcg.h"
> -#include "tcg/oversized-guest.h"
> #include "qapi/error.h"
> #include "qemu/error-report.h"
> #include "qemu/accel.h"
> @@ -67,20 +66,13 @@ DECLARE_INSTANCE_CHECKER(TCGState, TCG_STATE,
> * there is one remaining limitation to check:
> * - The guest can't be oversized (e.g. 64 bit guest on 32 bit host)
> */
> -
> static bool default_mttcg_enabled(void)
> {
> - if (icount_enabled() || TCG_OVERSIZED_GUEST) {
> + const bool oversized_guest = target_long_bits() > TCG_TARGET_REG_BITS;
> + if (icount_enabled() || oversized_guest) {
> return false;
> }
> -#ifdef TARGET_SUPPORTS_MTTCG
> -# ifndef TCG_GUEST_DEFAULT_MO
> -# error "TARGET_SUPPORTS_MTTCG without TCG_GUEST_DEFAULT_MO"
> -# endif
> - return true;
> -#else
> - return false;
> -#endif
> + return target_supports_mttcg();
> }
>
> static void tcg_accel_instance_init(Object *obj)
> @@ -137,17 +129,18 @@ static char *tcg_get_thread(Object *obj, Error **errp)
> static void tcg_set_thread(Object *obj, const char *value, Error **errp)
> {
> TCGState *s = TCG_STATE(obj);
> + const bool oversized_guest = target_long_bits() > TCG_TARGET_REG_BITS;
>
> if (strcmp(value, "multi") == 0) {
> - if (TCG_OVERSIZED_GUEST) {
> + if (oversized_guest) {
> error_setg(errp, "No MTTCG when guest word size > hosts");
> } else if (icount_enabled()) {
> error_setg(errp, "No MTTCG when icount is enabled");
> } else {
> -#ifndef TARGET_SUPPORTS_MTTCG
> - warn_report("Guest not yet converted to MTTCG - "
> - "you may get unexpected results");
> -#endif
> + if (target_supports_mttcg()) {
> + warn_report("Guest not yet converted to MTTCG - "
> + "you may get unexpected results");
> + }
> s->mttcg_enabled = true;
> }
> } else if (strcmp(value, "single") == 0) {
All of this happens at startup. Are you sure you're going to have determined these values
early enough for heterogeneous mode? I guess for the moment you don't care, because
they're all constants supplied by functions.
Acked-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 83+ messages in thread
* Re: [RFC PATCH 31/34] accel/tcg: Make tcg-runtime-gvec.c target independent
2024-01-19 14:40 ` [RFC PATCH 31/34] accel/tcg: Make tcg-runtime-gvec.c target independent Anton Johansson via
@ 2024-01-24 3:15 ` Richard Henderson
0 siblings, 0 replies; 83+ messages in thread
From: Richard Henderson @ 2024-01-24 3:15 UTC (permalink / raw)
To: Anton Johansson, qemu-devel; +Cc: ale, philmd
On 1/20/24 00:40, Anton Johansson wrote:
> Only depends on cpu.h.
s/Only/Doesn't/ ?
Anyway,
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 83+ messages in thread
* Re: [RFC PATCH 32/34] accel/tcg: Make tcg-runtime.c target independent
2024-01-19 14:40 ` [RFC PATCH 32/34] accel/tcg: Make tcg-runtime.c " Anton Johansson via
@ 2024-01-24 3:16 ` Richard Henderson
0 siblings, 0 replies; 83+ messages in thread
From: Richard Henderson @ 2024-01-24 3:16 UTC (permalink / raw)
To: Anton Johansson, qemu-devel; +Cc: ale, philmd
On 1/20/24 00:40, Anton Johansson wrote:
> Only depends on cpu.h.
Likewise,
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
>
> Signed-off-by: Anton Johansson <anjo@rev.ng>
> ---
> accel/tcg/tcg-runtime.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/accel/tcg/tcg-runtime.c b/accel/tcg/tcg-runtime.c
> index 9fa539ad3d..fd78a10fe2 100644
> --- a/accel/tcg/tcg-runtime.c
> +++ b/accel/tcg/tcg-runtime.c
> @@ -23,7 +23,7 @@
> */
> #include "qemu/osdep.h"
> #include "qemu/host-utils.h"
> -#include "cpu.h"
> +#include "qemu/atomic.h"
> #include "exec/helper-proto-common.h"
> #include "exec/cpu_ldst.h"
> #include "exec/exec-all.h"
^ permalink raw reply [flat|nested] 83+ messages in thread
* Re: [RFC PATCH 33/34] accel/tcg: Make translator.c (partially) target independent
2024-01-19 14:40 ` [RFC PATCH 33/34] accel/tcg: Make translator.c (partially) " Anton Johansson via
@ 2024-01-24 3:30 ` Richard Henderson
0 siblings, 0 replies; 83+ messages in thread
From: Richard Henderson @ 2024-01-24 3:30 UTC (permalink / raw)
To: Anton Johansson, qemu-devel; +Cc: ale, philmd
On 1/20/24 00:40, Anton Johansson wrote:
> Make CPUState offset calculations target independent by using that
> CPUState and CPUArchState are statically guaranteed to lie next to each
> other in memory.
>
> Signed-off-by: Anton Johansson<anjo@rev.ng>
> ---
> accel/tcg/translator.c | 16 ++++++++--------
> 1 file changed, 8 insertions(+), 8 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 83+ messages in thread
* Re: [RFC PATCH 14/34] exec: [CPUTLB] Move PAGE_* macros to common header
2024-01-23 23:54 ` Richard Henderson
@ 2024-01-27 7:53 ` Richard Henderson
0 siblings, 0 replies; 83+ messages in thread
From: Richard Henderson @ 2024-01-27 7:53 UTC (permalink / raw)
To: Anton Johansson, qemu-devel; +Cc: ale, philmd
On 1/24/24 09:54, Richard Henderson wrote:
> On 1/20/24 00:40, Anton Johansson wrote:
>> These don't vary across targets and are used in soon-to-be common code
>> (cputlb.c).
>>
>> Signed-off-by: Anton Johansson<anjo@rev.ng>
>> ---
>> include/exec/cpu-all.h | 24 ------------------------
>> include/exec/cpu-common.h | 30 ++++++++++++++++++++++++++++++
>> 2 files changed, 30 insertions(+), 24 deletions(-)
>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Queued, thanks.
r~
^ permalink raw reply [flat|nested] 83+ messages in thread
* Re: [RFC PATCH 05/34] target/tricore: [VADDR] Use target_ulong for EA
2024-01-19 14:39 ` [RFC PATCH 05/34] target/tricore: [VADDR] Use target_ulong for EA Anton Johansson via
2024-01-23 22:29 ` Richard Henderson
@ 2024-01-27 8:26 ` Richard Henderson
1 sibling, 0 replies; 83+ messages in thread
From: Richard Henderson @ 2024-01-27 8:26 UTC (permalink / raw)
To: Anton Johansson, qemu-devel; +Cc: ale, philmd
On 1/20/24 00:39, Anton Johansson wrote:
> Prepares target for typedef'ing abi_ptr to vaddr. Fixes sign extension
> bug that would result from abi_ptr being unsigned in the future.
>
> Necessary to make memory access function signatures target agnostic.
>
> Signed-off-by: Anton Johansson <anjo@rev.ng>
> ---
> target/tricore/op_helper.c | 8 ++++----
> 1 file changed, 4 insertions(+), 4 deletions(-)
This has been fixed on master since
commit ceada000846b0cd81c578b1da9f76d0c59536654
Author: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Date: Wed Sep 13 12:53:26 2023 +0200
target/tricore: Change effective address (ea) to target_ulong
I'm confused about the branch on which you're working...
r~
>
> diff --git a/target/tricore/op_helper.c b/target/tricore/op_helper.c
> index 89be1ed648..f57bb39d1f 100644
> --- a/target/tricore/op_helper.c
> +++ b/target/tricore/op_helper.c
> @@ -2395,7 +2395,7 @@ static bool cdc_zero(target_ulong *psw)
> return count == 0;
> }
>
> -static void save_context_upper(CPUTriCoreState *env, int ea)
> +static void save_context_upper(CPUTriCoreState *env, target_ulong ea)
> {
> cpu_stl_data(env, ea, env->PCXI);
> cpu_stl_data(env, ea+4, psw_read(env));
> @@ -2415,7 +2415,7 @@ static void save_context_upper(CPUTriCoreState *env, int ea)
> cpu_stl_data(env, ea+60, env->gpr_d[15]);
> }
>
> -static void save_context_lower(CPUTriCoreState *env, int ea)
> +static void save_context_lower(CPUTriCoreState *env, target_ulong ea)
> {
> cpu_stl_data(env, ea, env->PCXI);
> cpu_stl_data(env, ea+4, env->gpr_a[11]);
> @@ -2435,7 +2435,7 @@ static void save_context_lower(CPUTriCoreState *env, int ea)
> cpu_stl_data(env, ea+60, env->gpr_d[7]);
> }
>
> -static void restore_context_upper(CPUTriCoreState *env, int ea,
> +static void restore_context_upper(CPUTriCoreState *env, target_ulong ea,
> target_ulong *new_PCXI, target_ulong *new_PSW)
> {
> *new_PCXI = cpu_ldl_data(env, ea);
> @@ -2456,7 +2456,7 @@ static void restore_context_upper(CPUTriCoreState *env, int ea,
> env->gpr_d[15] = cpu_ldl_data(env, ea+60);
> }
>
> -static void restore_context_lower(CPUTriCoreState *env, int ea,
> +static void restore_context_lower(CPUTriCoreState *env, target_ulong ea,
> target_ulong *ra, target_ulong *pcxi)
> {
> *pcxi = cpu_ldl_data(env, ea);
^ permalink raw reply [flat|nested] 83+ messages in thread
* Re: [RFC PATCH 06/34] exec: [VADDR] Move vaddr defines to separate file
2024-01-19 14:39 ` [RFC PATCH 06/34] exec: [VADDR] Move vaddr defines to separate file Anton Johansson via
2024-01-23 22:33 ` Richard Henderson
@ 2024-01-27 8:36 ` Richard Henderson
2024-01-27 8:45 ` Richard Henderson
1 sibling, 1 reply; 83+ messages in thread
From: Richard Henderson @ 2024-01-27 8:36 UTC (permalink / raw)
To: Anton Johansson, qemu-devel; +Cc: ale, philmd
On 1/20/24 00:39, Anton Johansson wrote:
> --- a/include/exec/cpu-common.h
> +++ b/include/exec/cpu-common.h
> @@ -14,18 +14,6 @@
> #define EXCP_YIELD 0x10004 /* cpu wants to yield timeslice to another */
> #define EXCP_ATOMIC 0x10005 /* stop-the-world and emulate atomic */
>
> -/**
> - * vaddr:
> - * Type wide enough to contain any #target_ulong virtual address.
> - */
> -typedef uint64_t vaddr;
> -#define VADDR_PRId PRId64
> -#define VADDR_PRIu PRIu64
> -#define VADDR_PRIo PRIo64
> -#define VADDR_PRIx PRIx64
> -#define VADDR_PRIX PRIX64
> -#define VADDR_MAX UINT64_MAX
> -
> /**
> * Variable page size macros
> *
This patch does not compile standalone, because the new header isn't included here.
r~
^ permalink raw reply [flat|nested] 83+ messages in thread
* Re: [RFC PATCH 06/34] exec: [VADDR] Move vaddr defines to separate file
2024-01-27 8:36 ` Richard Henderson
@ 2024-01-27 8:45 ` Richard Henderson
0 siblings, 0 replies; 83+ messages in thread
From: Richard Henderson @ 2024-01-27 8:45 UTC (permalink / raw)
To: Anton Johansson, qemu-devel; +Cc: ale, philmd
On 1/27/24 18:36, Richard Henderson wrote:
> On 1/20/24 00:39, Anton Johansson wrote:
>> --- a/include/exec/cpu-common.h
>> +++ b/include/exec/cpu-common.h
>> @@ -14,18 +14,6 @@
>> #define EXCP_YIELD 0x10004 /* cpu wants to yield timeslice to another */
>> #define EXCP_ATOMIC 0x10005 /* stop-the-world and emulate atomic */
>> -/**
>> - * vaddr:
>> - * Type wide enough to contain any #target_ulong virtual address.
>> - */
>> -typedef uint64_t vaddr;
>> -#define VADDR_PRId PRId64
>> -#define VADDR_PRIu PRIu64
>> -#define VADDR_PRIo PRIo64
>> -#define VADDR_PRIx PRIx64
>> -#define VADDR_PRIX PRIX64
>> -#define VADDR_MAX UINT64_MAX
>> -
>> /**
>> * Variable page size macros
>> *
>
> This patch does not compile standalone, because the new header isn't included here.
Queued with fixes.
r~
^ permalink raw reply [flat|nested] 83+ messages in thread
* Re: [RFC PATCH 07/34] hw/core: [VADDR] Include vaddr.h from cpu.h
2024-01-19 14:39 ` [RFC PATCH 07/34] hw/core: [VADDR] Include vaddr.h from cpu.h Anton Johansson via
2024-01-23 22:57 ` Richard Henderson
@ 2024-01-27 8:48 ` Richard Henderson
1 sibling, 0 replies; 83+ messages in thread
From: Richard Henderson @ 2024-01-27 8:48 UTC (permalink / raw)
To: Anton Johansson, qemu-devel; +Cc: ale, philmd
On 1/20/24 00:39, Anton Johansson wrote:
> cpu-common.h is only needed for vaddr
>
> Signed-off-by: Anton Johansson <anjo@rev.ng>
> ---
> include/hw/core/cpu.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
Queued, thanks.
r~
^ permalink raw reply [flat|nested] 83+ messages in thread
* Re: [RFC PATCH 08/34] target: [VADDR] Use vaddr in gen_intermediate_code
2024-01-19 14:39 ` [RFC PATCH 08/34] target: [VADDR] Use vaddr in gen_intermediate_code Anton Johansson via
2024-01-23 23:13 ` Richard Henderson
@ 2024-01-27 9:05 ` Richard Henderson
1 sibling, 0 replies; 83+ messages in thread
From: Richard Henderson @ 2024-01-27 9:05 UTC (permalink / raw)
To: Anton Johansson, qemu-devel; +Cc: ale, philmd
On 1/20/24 00:39, Anton Johansson wrote:
> Makes gen_intermediate_code() signature target agnostic so the function
> can be called from accel/tcg/translate-all.c without target specifics.
>
> Signed-off-by: Anton Johansson<anjo@rev.ng>
> ---
> include/exec/translator.h | 2 +-
> target/alpha/translate.c | 2 +-
> target/arm/tcg/translate.c | 2 +-
> target/avr/translate.c | 2 +-
> target/cris/translate.c | 2 +-
> target/hexagon/translate.c | 2 +-
> target/hppa/translate.c | 2 +-
> target/i386/tcg/translate.c | 2 +-
> target/loongarch/translate.c | 2 +-
> target/m68k/translate.c | 2 +-
> target/microblaze/translate.c | 2 +-
> target/mips/tcg/translate.c | 2 +-
> target/nios2/translate.c | 2 +-
> target/openrisc/translate.c | 2 +-
> target/ppc/translate.c | 2 +-
> target/riscv/translate.c | 2 +-
> target/rx/translate.c | 2 +-
> target/s390x/tcg/translate.c | 2 +-
> target/sh4/translate.c | 2 +-
> target/sparc/translate.c | 2 +-
> target/tricore/translate.c | 2 +-
> target/xtensa/translate.c | 2 +-
> 22 files changed, 22 insertions(+), 22 deletions(-)
Queued, thanks.
r~
^ permalink raw reply [flat|nested] 83+ messages in thread
* Re: [RFC PATCH 09/34] exec: [VADDR] Use vaddr in DisasContextBase for virtual addresses
2024-01-19 14:39 ` [RFC PATCH 09/34] exec: [VADDR] Use vaddr in DisasContextBase for virtual addresses Anton Johansson via
2024-01-23 23:22 ` Richard Henderson
@ 2024-01-27 9:33 ` Richard Henderson
1 sibling, 0 replies; 83+ messages in thread
From: Richard Henderson @ 2024-01-27 9:33 UTC (permalink / raw)
To: Anton Johansson, qemu-devel; +Cc: ale, philmd
On 1/20/24 00:39, Anton Johansson wrote:
> Updates target/ QEMU_LOG macros to use VADDR_PRIx for printing updated
> DisasContextBase fields.
>
> Signed-off-by: Anton Johansson <anjo@rev.ng>
> ---
> include/exec/translator.h | 6 +++---
> target/mips/tcg/translate.h | 3 ++-
> target/hexagon/translate.c | 3 ++-
> target/m68k/translate.c | 2 +-
> target/mips/tcg/translate.c | 12 ++++++------
> 5 files changed, 14 insertions(+), 12 deletions(-)
Queued, thanks.
r~
^ permalink raw reply [flat|nested] 83+ messages in thread
* Re: [RFC PATCH 10/34] exec: [VADDR] typedef abi_ptr to vaddr
2024-01-19 14:40 ` [RFC PATCH 10/34] exec: [VADDR] typedef abi_ptr to vaddr Anton Johansson via
2024-01-23 23:29 ` Richard Henderson
@ 2024-01-27 9:42 ` Richard Henderson
1 sibling, 0 replies; 83+ messages in thread
From: Richard Henderson @ 2024-01-27 9:42 UTC (permalink / raw)
To: Anton Johansson, qemu-devel; +Cc: ale, philmd
On 1/20/24 00:40, Anton Johansson wrote:
> Signed-off-by: Anton Johansson <anjo@rev.ng>
> ---
> include/exec/cpu_ldst.h | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/include/exec/cpu_ldst.h b/include/exec/cpu_ldst.h
> index 6061e33ac9..eb8f3f0595 100644
> --- a/include/exec/cpu_ldst.h
> +++ b/include/exec/cpu_ldst.h
> @@ -121,8 +121,8 @@ static inline bool guest_range_valid_untagged(abi_ulong start, abi_ulong len)
> h2g_nocheck(x); \
> })
> #else
> -typedef target_ulong abi_ptr;
> -#define TARGET_ABI_FMT_ptr TARGET_FMT_lx
> +typedef vaddr abi_ptr;
> +#define TARGET_ABI_FMT_ptr VADDR_PRIx
> #endif
>
> uint32_t cpu_ldub_data(CPUArchState *env, abi_ptr ptr);
Queued, thanks.
r~
^ permalink raw reply [flat|nested] 83+ messages in thread
* Re: [RFC PATCH 12/34] target: Uninline cpu_mmu_index()
2024-01-19 14:40 ` [RFC PATCH 12/34] target: Uninline cpu_mmu_index() Anton Johansson via
2024-01-23 23:40 ` Richard Henderson
@ 2024-01-27 10:10 ` Richard Henderson
1 sibling, 0 replies; 83+ messages in thread
From: Richard Henderson @ 2024-01-27 10:10 UTC (permalink / raw)
To: Anton Johansson, qemu-devel; +Cc: ale, philmd
On 1/20/24 00:40, Anton Johansson wrote:
> Uninlines the target-defined cpu_mmu_index() function by moving its
> definition to target/*/cpu.c. This allows for compiling memory access
> functions in accel/tcg/cputlb.c without having to know target specifics.
>
> Signed-off-by: Anton Johansson<anjo@rev.ng>
> ---
Queued, thanks.
r~
^ permalink raw reply [flat|nested] 83+ messages in thread
* Re: [RFC PATCH 13/34] target: Uninline cpu_get_tb_cpu_state()
2024-01-19 14:40 ` [RFC PATCH 13/34] target: Uninline cpu_get_tb_cpu_state() Anton Johansson via
2024-01-23 23:53 ` Richard Henderson
@ 2024-01-27 11:21 ` Richard Henderson
1 sibling, 0 replies; 83+ messages in thread
From: Richard Henderson @ 2024-01-27 11:21 UTC (permalink / raw)
To: Anton Johansson, qemu-devel; +Cc: ale, philmd
On 1/20/24 00:40, Anton Johansson wrote:
> Required to compile accel/tcg/translate-all.c once for softmmu targets.
> The function gets quite big for some targets so uninlining makes sense.
>
> Signed-off-by: Anton Johansson<anjo@rev.ng>
> ---
Queued, thanks.
r~
^ permalink raw reply [flat|nested] 83+ messages in thread
* Re: [RFC PATCH 16/34] exec: [CPUTLB] Move cpu_*()/cpu_env() to common header
2024-01-19 14:40 ` [RFC PATCH 16/34] exec: [CPUTLB] Move cpu_*()/cpu_env() " Anton Johansson via
2024-01-24 0:15 ` Richard Henderson
@ 2024-01-27 22:14 ` Richard Henderson
2024-01-28 0:15 ` Richard Henderson
1 sibling, 1 reply; 83+ messages in thread
From: Richard Henderson @ 2024-01-27 22:14 UTC (permalink / raw)
To: Anton Johansson, qemu-devel; +Cc: ale, philmd
On 1/20/24 00:40, Anton Johansson wrote:
> --- a/include/exec/cpu-common.h
> +++ b/include/exec/cpu-common.h
> @@ -347,4 +347,29 @@ G_NORETURN void cpu_loop_exit_restore(CPUState *cpu, uintptr_t pc);
> */
> #define PAGE_PASSTHROUGH 0x0800
>
> +/* accel/tcg/cpu-exec.c */
> +int cpu_exec(CPUState *cpu);
> +
> +/**
> + * env_archcpu(env)
> + * @env: The architecture environment
> + *
> + * Return the ArchCPU associated with the environment.
> + */
> +static inline ArchCPU *env_archcpu(CPUArchState *env)
> +{
> + return (void *)env - sizeof(CPUState);
> +}
> +
> +/**
> + * env_cpu(env)
> + * @env: The architecture environment
> + *
> + * Return the CPUState associated with the environment.
> + */
> +static inline CPUState *env_cpu(CPUArchState *env)
> +{
> + return (void *)env - sizeof(CPUState);
> +}
> +
> #endif /* CPU_COMMON_H */
Missing include of hw/core/cpu.h, as far as I can see?
r~
^ permalink raw reply [flat|nested] 83+ messages in thread
* Re: [RFC PATCH 16/34] exec: [CPUTLB] Move cpu_*()/cpu_env() to common header
2024-01-27 22:14 ` Richard Henderson
@ 2024-01-28 0:15 ` Richard Henderson
0 siblings, 0 replies; 83+ messages in thread
From: Richard Henderson @ 2024-01-28 0:15 UTC (permalink / raw)
To: Anton Johansson, qemu-devel; +Cc: ale, philmd
On 1/28/24 08:14, Richard Henderson wrote:
> On 1/20/24 00:40, Anton Johansson wrote:
>> --- a/include/exec/cpu-common.h
>> +++ b/include/exec/cpu-common.h
>> @@ -347,4 +347,29 @@ G_NORETURN void cpu_loop_exit_restore(CPUState *cpu, uintptr_t pc);
>> */
>> #define PAGE_PASSTHROUGH 0x0800
>> +/* accel/tcg/cpu-exec.c */
>> +int cpu_exec(CPUState *cpu);
>> +
>> +/**
>> + * env_archcpu(env)
>> + * @env: The architecture environment
>> + *
>> + * Return the ArchCPU associated with the environment.
>> + */
>> +static inline ArchCPU *env_archcpu(CPUArchState *env)
>> +{
>> + return (void *)env - sizeof(CPUState);
>> +}
>> +
>> +/**
>> + * env_cpu(env)
>> + * @env: The architecture environment
>> + *
>> + * Return the CPUState associated with the environment.
>> + */
>> +static inline CPUState *env_cpu(CPUArchState *env)
>> +{
>> + return (void *)env - sizeof(CPUState);
>> +}
>> +
>> #endif /* CPU_COMMON_H */
>
> Missing include of hw/core/cpu.h, as far as I can see?
Queued, with this fix.
r~
^ permalink raw reply [flat|nested] 83+ messages in thread
* Re: [RFC PATCH 17/34] hw/core: [CPUTLB] Move target specifics to end of TCGCPUOps
2024-01-24 0:43 ` Richard Henderson
@ 2024-01-28 0:37 ` Richard Henderson
0 siblings, 0 replies; 83+ messages in thread
From: Richard Henderson @ 2024-01-28 0:37 UTC (permalink / raw)
To: Anton Johansson, qemu-devel; +Cc: ale, philmd
On 1/24/24 10:43, Richard Henderson wrote:
> On 1/20/24 00:40, Anton Johansson wrote:
>> TCGCPUOps contains an extra function pointer when included with
>> NEED_CPU_H, these are moved from the middle to the end of the struct. As
>> such offsets to target independent function pointers don't vary in
>> target specific and independent code.
>>
>> [Move target specfic fields to separate struct?]
>>
>> Signed-off-by: Anton Johansson <anjo@rev.ng>
>
> Or make these unconditional. Move fake_user_interrupt into the CONFIG_USER_ONLY block and
> do_interrupt into the system block.
I have split the patch in two, made fake_user_interrupt unconditional, and queued.
r~
^ permalink raw reply [flat|nested] 83+ messages in thread
end of thread, other threads:[~2024-01-28 0:38 UTC | newest]
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2024-01-19 14:39 [RFC PATCH 00/34] Compile accel/tcg once (partially) Anton Johansson via
2024-01-19 14:39 ` [RFC PATCH 01/34] target: [PAGE_VARY] Use PAGE_VARY for all softmmu targets Anton Johansson via
2024-01-19 16:05 ` Philippe Mathieu-Daudé
2024-01-23 12:09 ` Anton Johansson via
2024-01-19 14:39 ` [RFC PATCH 02/34] target: [PAGE_VARY] Move TARGET_PAGE_BITS_MIN to TargetPageBits Anton Johansson via
2024-01-23 16:33 ` Richard Henderson
2024-01-19 14:39 ` [RFC PATCH 03/34] exec: [PAGE_VARY] Move TARGET_PAGE_BITS_VARY to common header Anton Johansson via
2024-01-23 22:20 ` Richard Henderson
2024-01-19 14:39 ` [RFC PATCH 04/34] exec: [PAGE_VARY] Unpoison TARGET_PAGE_* macros for system mode Anton Johansson via
2024-01-23 22:20 ` Richard Henderson
2024-01-19 14:39 ` [RFC PATCH 05/34] target/tricore: [VADDR] Use target_ulong for EA Anton Johansson via
2024-01-23 22:29 ` Richard Henderson
2024-01-27 8:26 ` Richard Henderson
2024-01-19 14:39 ` [RFC PATCH 06/34] exec: [VADDR] Move vaddr defines to separate file Anton Johansson via
2024-01-23 22:33 ` Richard Henderson
2024-01-27 8:36 ` Richard Henderson
2024-01-27 8:45 ` Richard Henderson
2024-01-19 14:39 ` [RFC PATCH 07/34] hw/core: [VADDR] Include vaddr.h from cpu.h Anton Johansson via
2024-01-23 22:57 ` Richard Henderson
2024-01-27 8:48 ` Richard Henderson
2024-01-19 14:39 ` [RFC PATCH 08/34] target: [VADDR] Use vaddr in gen_intermediate_code Anton Johansson via
2024-01-23 23:13 ` Richard Henderson
2024-01-27 9:05 ` Richard Henderson
2024-01-19 14:39 ` [RFC PATCH 09/34] exec: [VADDR] Use vaddr in DisasContextBase for virtual addresses Anton Johansson via
2024-01-23 23:22 ` Richard Henderson
2024-01-27 9:33 ` Richard Henderson
2024-01-19 14:40 ` [RFC PATCH 10/34] exec: [VADDR] typedef abi_ptr to vaddr Anton Johansson via
2024-01-23 23:29 ` Richard Henderson
2024-01-27 9:42 ` Richard Henderson
2024-01-19 14:40 ` [RFC PATCH 11/34] [IGNORE] Squash of header code shuffling Anton Johansson via
2024-01-19 14:40 ` [RFC PATCH 12/34] target: Uninline cpu_mmu_index() Anton Johansson via
2024-01-23 23:40 ` Richard Henderson
2024-01-27 10:10 ` Richard Henderson
2024-01-19 14:40 ` [RFC PATCH 13/34] target: Uninline cpu_get_tb_cpu_state() Anton Johansson via
2024-01-23 23:53 ` Richard Henderson
2024-01-27 11:21 ` Richard Henderson
2024-01-19 14:40 ` [RFC PATCH 14/34] exec: [CPUTLB] Move PAGE_* macros to common header Anton Johansson via
2024-01-23 23:54 ` Richard Henderson
2024-01-27 7:53 ` Richard Henderson
2024-01-19 14:40 ` [RFC PATCH 15/34] exec: [CPUTLB] Move TLB_*/tlb_*() " Anton Johansson via
2024-01-24 0:09 ` Richard Henderson
2024-01-19 14:40 ` [RFC PATCH 16/34] exec: [CPUTLB] Move cpu_*()/cpu_env() " Anton Johansson via
2024-01-24 0:15 ` Richard Henderson
2024-01-27 22:14 ` Richard Henderson
2024-01-28 0:15 ` Richard Henderson
2024-01-19 14:40 ` [RFC PATCH 17/34] hw/core: [CPUTLB] Move target specifics to end of TCGCPUOps Anton Johansson via
2024-01-24 0:43 ` Richard Henderson
2024-01-28 0:37 ` Richard Henderson
2024-01-19 14:40 ` [RFC PATCH 18/34] accel/stubs: [CPUTLB] Move xen.h stubs to xen-stub.c Anton Johansson via
2024-01-24 1:04 ` Richard Henderson
2024-01-19 14:40 ` [RFC PATCH 19/34] accel/tcg: [CPUTLB] Use TCGContext.addr_type instead of TARGET_LONG_BITS Anton Johansson via
2024-01-24 1:18 ` Richard Henderson
2024-01-19 14:40 ` [RFC PATCH 20/34] accel/tcg: [CPUTLB] Use TCGContext.guest_mo for memory ordering Anton Johansson via
2024-01-24 1:21 ` Richard Henderson
2024-01-19 14:40 ` [RFC PATCH 21/34] accel/tcg: [CPUTLB] Use tcg_ctx->tlb_dyn_max_bits Anton Johansson via
2024-01-24 1:23 ` Richard Henderson
2024-01-19 14:40 ` [RFC PATCH 22/34] accel/tcg: [CPUTLB] Move CPU_TLB_DYN_[DEFAULT|MIN]* to cputlb.c Anton Johansson via
2024-01-24 1:24 ` Richard Henderson
2024-01-19 14:40 ` [RFC PATCH 23/34] tcg: [CPUTLB] Add `mo_te` field to TCGContext Anton Johansson via
2024-01-24 1:50 ` Richard Henderson
2024-01-19 14:40 ` [RFC PATCH 24/34] accel/tcg: [CPUTLB] Set mo_te in TCGContext Anton Johansson via
2024-01-19 14:40 ` [RFC PATCH 25/34] accel/tcg: [CPUTLB] Use tcg_ctx->mo_te instead of MO_TE Anton Johansson via
2024-01-19 14:40 ` [RFC PATCH 26/34] Wrap target macros in functions Anton Johansson via
2024-01-23 11:50 ` Philippe Mathieu-Daudé
2024-01-23 12:12 ` Anton Johansson via
2024-01-24 2:50 ` Richard Henderson
2024-01-19 14:40 ` [RFC PATCH 27/34] accel/tcg: Make translate-all.c target independent Anton Johansson via
2024-01-24 2:53 ` Richard Henderson
2024-01-19 14:40 ` [RFC PATCH 28/34] accel/tcg: Make plugin-gen.c " Anton Johansson via
2024-01-24 3:02 ` Richard Henderson
2024-01-19 14:40 ` [RFC PATCH 29/34] accel/tcg: Make tb-maint.c target indpendent Anton Johansson via
2024-01-24 3:10 ` Richard Henderson
2024-01-19 14:40 ` [RFC PATCH 30/34] accel/tcg: Make tcg-all.c " Anton Johansson via
2024-01-23 11:45 ` Philippe Mathieu-Daudé
2024-01-23 12:03 ` Anton Johansson via
2024-01-24 3:13 ` Richard Henderson
2024-01-19 14:40 ` [RFC PATCH 31/34] accel/tcg: Make tcg-runtime-gvec.c target independent Anton Johansson via
2024-01-24 3:15 ` Richard Henderson
2024-01-19 14:40 ` [RFC PATCH 32/34] accel/tcg: Make tcg-runtime.c " Anton Johansson via
2024-01-24 3:16 ` Richard Henderson
2024-01-19 14:40 ` [RFC PATCH 33/34] accel/tcg: Make translator.c (partially) " Anton Johansson via
2024-01-24 3:30 ` Richard Henderson
2024-01-19 14:40 ` [RFC PATCH 34/34] accel/tcg: Compile (a few files) once for system-mode Anton Johansson via
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