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From: Richard Henderson <richard.henderson@linaro.org>
To: liweiwei <liweiwei@iscas.ac.cn>,
	palmer@dabbelt.com, alistair.francis@wdc.com,
	bin.meng@windriver.com, qemu-riscv@nongnu.org,
	qemu-devel@nongnu.org
Cc: wangjunqiang@iscas.ac.cn, lazyparser@gmail.com,
	luruibo2000@163.com, lustrew@foxmail.com
Subject: Re: [RFC 1/6] target/riscv: rvk: add flag support for Zbk[bcx]
Date: Tue, 2 Nov 2021 10:18:38 -0400	[thread overview]
Message-ID: <97624133-30f2-fdc4-4f3c-0cc843f0768c@linaro.org> (raw)
In-Reply-To: <20211102031128.17296-2-liweiwei@iscas.ac.cn>

On 11/1/21 11:11 PM, liweiwei wrote:
> +++ b/target/riscv/cpu.c
> @@ -472,15 +472,15 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
>               error_setg(errp,
>                          "I and E extensions are incompatible");
>                          return;
> -       }
> +        }
>   
>           if (!cpu->cfg.ext_i && !cpu->cfg.ext_e) {
>               error_setg(errp,
>                          "Either I or E extension must be set");
>                          return;
> -       }
> +        }
>   
> -       if (cpu->cfg.ext_g && !(cpu->cfg.ext_i & cpu->cfg.ext_m &
> +        if (cpu->cfg.ext_g && !(cpu->cfg.ext_i & cpu->cfg.ext_m &
>                                  cpu->cfg.ext_a & cpu->cfg.ext_f &
>                                  cpu->cfg.ext_d)) {
>               warn_report("Setting G will also set IMAFD");

This re-indentation should not be happening.


> +    DEFINE_PROP_BOOL("x-zbkb", RISCVCPU, cfg.ext_zbkb, false),
> +    DEFINE_PROP_BOOL("x-zbkc", RISCVCPU, cfg.ext_zbkc, false),
> +    DEFINE_PROP_BOOL("x-zbkx", RISCVCPU, cfg.ext_zbkx, false),

The properties cannot be exposed until the end.

>          bool ext_zbb;
>          bool ext_zbc;
>          bool ext_zbs;
> +        bool ext_zbkb;
> +        bool ext_zbkc;
> +        bool ext_zbkx;

Better to keep them alphabetical: zbk* < zbs.


r~


WARNING: multiple messages have this Message-ID (diff)
From: Richard Henderson <richard.henderson@linaro.org>
To: liweiwei <liweiwei@iscas.ac.cn>,
	palmer@dabbelt.com, alistair.francis@wdc.com,
	bin.meng@windriver.com, qemu-riscv@nongnu.org,
	qemu-devel@nongnu.org
Cc: wangjunqiang@iscas.ac.cn, lazyparser@gmail.com,
	lustrew@foxmail.com, luruibo2000@163.com
Subject: Re: [RFC 1/6] target/riscv: rvk: add flag support for Zbk[bcx]
Date: Tue, 2 Nov 2021 10:18:38 -0400	[thread overview]
Message-ID: <97624133-30f2-fdc4-4f3c-0cc843f0768c@linaro.org> (raw)
In-Reply-To: <20211102031128.17296-2-liweiwei@iscas.ac.cn>

On 11/1/21 11:11 PM, liweiwei wrote:
> +++ b/target/riscv/cpu.c
> @@ -472,15 +472,15 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
>               error_setg(errp,
>                          "I and E extensions are incompatible");
>                          return;
> -       }
> +        }
>   
>           if (!cpu->cfg.ext_i && !cpu->cfg.ext_e) {
>               error_setg(errp,
>                          "Either I or E extension must be set");
>                          return;
> -       }
> +        }
>   
> -       if (cpu->cfg.ext_g && !(cpu->cfg.ext_i & cpu->cfg.ext_m &
> +        if (cpu->cfg.ext_g && !(cpu->cfg.ext_i & cpu->cfg.ext_m &
>                                  cpu->cfg.ext_a & cpu->cfg.ext_f &
>                                  cpu->cfg.ext_d)) {
>               warn_report("Setting G will also set IMAFD");

This re-indentation should not be happening.


> +    DEFINE_PROP_BOOL("x-zbkb", RISCVCPU, cfg.ext_zbkb, false),
> +    DEFINE_PROP_BOOL("x-zbkc", RISCVCPU, cfg.ext_zbkc, false),
> +    DEFINE_PROP_BOOL("x-zbkx", RISCVCPU, cfg.ext_zbkx, false),

The properties cannot be exposed until the end.

>          bool ext_zbb;
>          bool ext_zbc;
>          bool ext_zbs;
> +        bool ext_zbkb;
> +        bool ext_zbkc;
> +        bool ext_zbkx;

Better to keep them alphabetical: zbk* < zbs.


r~


  reply	other threads:[~2021-11-02 14:38 UTC|newest]

Thread overview: 34+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-11-02  3:11 [RFC 0/6] support subsets of scalar crypto extension liweiwei
2021-11-02  3:11 ` liweiwei
2021-11-02  3:11 ` [RFC 1/6] target/riscv: rvk: add flag support for Zbk[bcx] liweiwei
2021-11-02  3:11   ` liweiwei
2021-11-02 14:18   ` Richard Henderson [this message]
2021-11-02 14:18     ` Richard Henderson
2021-11-02 15:00     ` liweiwei
2021-11-02 15:00       ` liweiwei
2021-11-02  3:11 ` [RFC 2/6] target/riscv: rvk: add implementation of instructions for Zbk* - reuse partial instructions of Zbb/Zbc extensions - add brev8 packh, unzip, zip, etc liweiwei
2021-11-02  3:11   ` liweiwei
2021-11-02 15:44   ` Richard Henderson
2021-11-02 15:44     ` Richard Henderson
2021-11-03  0:56     ` liweiwei
2021-11-03  0:56       ` liweiwei
2021-11-02  3:11 ` [RFC 3/6] target/riscv: rvk: add flag support for Zk/Zkn/Zknd/Zknd/Zkne/Zknh/Zks/Zksed/Zksh/Zkr liweiwei
2021-11-02  3:11   ` liweiwei
2021-11-02 17:56   ` Richard Henderson
2021-11-02 17:56     ` Richard Henderson
2021-11-03  1:06     ` liweiwei
2021-11-03  1:06       ` liweiwei
2021-11-03  1:21       ` Richard Henderson
2021-11-03  1:21         ` Richard Henderson
2021-11-03  7:22         ` liweiwei
2021-11-03  7:22           ` liweiwei
2021-11-02  3:11 ` [RFC 4/6] target/riscv: rvk: add implementation of instructions for Zk* liweiwei
2021-11-02  3:11   ` liweiwei
2021-11-02 18:56   ` Richard Henderson
2021-11-02 18:56     ` Richard Henderson
2021-11-03  1:08     ` liweiwei
2021-11-03  1:08       ` liweiwei
2021-11-02  3:11 ` [RFC 5/6] target/riscv: rvk: add CSR support for Zkr: - add SEED CSR - add USEED, SSEED fields for MSECCFG CSR liweiwei
2021-11-02  3:11   ` liweiwei
2021-11-02  3:11 ` [RFC 6/6] disas/riscv.c: rvk: add disas support for Zbk* and Zk* instructions liweiwei
2021-11-02  3:11   ` liweiwei

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