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* [PATCH] clk: rockchip: fix wrong clock definitions for rk3328
@ 2019-03-10 12:00 ` Jonas Karlman
  0 siblings, 0 replies; 9+ messages in thread
From: Jonas Karlman @ 2019-03-10 12:00 UTC (permalink / raw)
  To: linux-clk, linux-rockchip, linux-arm-kernel
  Cc: Michael Turquette, Stephen Boyd, Heiko Stuebner, linux-kernel,
	Jonas Karlman

This patch fixes definition of several clock gate and select register
that is wrong for rk3328 referring to the TRM and vendor kernel.
Also use correct number of softrst registers.

Fix clock definition for:
- clk_crypto
- aclk_h265
- pclk_h265
- aclk_h264
- hclk_h264
- aclk_axisram
- aclk_gmac
- aclk_usb3otg

Fixes: fe3511ad8a1c ("clk: rockchip: add clock controller for rk3328")
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
---
 drivers/clk/rockchip/clk-rk3328.c | 18 +++++++++---------
 1 file changed, 9 insertions(+), 9 deletions(-)

diff --git a/drivers/clk/rockchip/clk-rk3328.c b/drivers/clk/rockchip/clk-rk3328.c
index faa94adb2a37..5f6b6bcc2149 100644
--- a/drivers/clk/rockchip/clk-rk3328.c
+++ b/drivers/clk/rockchip/clk-rk3328.c
@@ -458,7 +458,7 @@ static struct rockchip_clk_branch rk3328_clk_branches[] __initdata = {
 			RK3328_CLKSEL_CON(35), 15, 1, MFLAGS, 8, 7, DFLAGS,
 			RK3328_CLKGATE_CON(2), 12, GFLAGS),
 	COMPOSITE(SCLK_CRYPTO, "clk_crypto", mux_2plls_p, 0,
-			RK3328_CLKSEL_CON(20), 7, 1, MFLAGS, 0, 7, DFLAGS,
+			RK3328_CLKSEL_CON(20), 7, 1, MFLAGS, 0, 5, DFLAGS,
 			RK3328_CLKGATE_CON(2), 4, GFLAGS),
 	COMPOSITE_NOMUX(SCLK_TSADC, "clk_tsadc", "clk_24m", 0,
 			RK3328_CLKSEL_CON(22), 0, 10, DFLAGS,
@@ -550,15 +550,15 @@ static struct rockchip_clk_branch rk3328_clk_branches[] __initdata = {
 	GATE(0, "hclk_rkvenc_niu", "hclk_rkvenc", 0,
 			RK3328_CLKGATE_CON(25), 1, GFLAGS),
 	GATE(ACLK_H265, "aclk_h265", "aclk_rkvenc", 0,
-			RK3328_CLKGATE_CON(25), 0, GFLAGS),
+			RK3328_CLKGATE_CON(25), 2, GFLAGS),
 	GATE(PCLK_H265, "pclk_h265", "hclk_rkvenc", 0,
-			RK3328_CLKGATE_CON(25), 1, GFLAGS),
+			RK3328_CLKGATE_CON(25), 3, GFLAGS),
 	GATE(ACLK_H264, "aclk_h264", "aclk_rkvenc", 0,
-			RK3328_CLKGATE_CON(25), 0, GFLAGS),
+			RK3328_CLKGATE_CON(25), 4, GFLAGS),
 	GATE(HCLK_H264, "hclk_h264", "hclk_rkvenc", 0,
-			RK3328_CLKGATE_CON(25), 1, GFLAGS),
+			RK3328_CLKGATE_CON(25), 5, GFLAGS),
 	GATE(ACLK_AXISRAM, "aclk_axisram", "aclk_rkvenc", CLK_IGNORE_UNUSED,
-			RK3328_CLKGATE_CON(25), 0, GFLAGS),
+			RK3328_CLKGATE_CON(25), 6, GFLAGS),
 
 	COMPOSITE(SCLK_VENC_CORE, "sclk_venc_core", mux_4plls_p, 0,
 			RK3328_CLKSEL_CON(51), 14, 2, MFLAGS, 8, 5, DFLAGS,
@@ -663,7 +663,7 @@ static struct rockchip_clk_branch rk3328_clk_branches[] __initdata = {
 
 	/* PD_GMAC */
 	COMPOSITE(ACLK_GMAC, "aclk_gmac", mux_2plls_hdmiphy_p, 0,
-			RK3328_CLKSEL_CON(35), 6, 2, MFLAGS, 0, 5, DFLAGS,
+			RK3328_CLKSEL_CON(25), 6, 2, MFLAGS, 0, 5, DFLAGS,
 			RK3328_CLKGATE_CON(3), 2, GFLAGS),
 	COMPOSITE_NOMUX(PCLK_GMAC, "pclk_gmac", "aclk_gmac", 0,
 			RK3328_CLKSEL_CON(25), 8, 3, DFLAGS,
@@ -733,7 +733,7 @@ static struct rockchip_clk_branch rk3328_clk_branches[] __initdata = {
 
 	/* PD_PERI */
 	GATE(0, "aclk_peri_noc", "aclk_peri", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(19), 11, GFLAGS),
-	GATE(ACLK_USB3OTG, "aclk_usb3otg", "aclk_peri", 0, RK3328_CLKGATE_CON(19), 4, GFLAGS),
+	GATE(ACLK_USB3OTG, "aclk_usb3otg", "aclk_peri", 0, RK3328_CLKGATE_CON(19), 14, GFLAGS),
 
 	GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_peri", 0, RK3328_CLKGATE_CON(19), 0, GFLAGS),
 	GATE(HCLK_SDIO, "hclk_sdio", "hclk_peri", 0, RK3328_CLKGATE_CON(19), 1, GFLAGS),
@@ -913,7 +913,7 @@ static void __init rk3328_clk_init(struct device_node *np)
 				     &rk3328_cpuclk_data, rk3328_cpuclk_rates,
 				     ARRAY_SIZE(rk3328_cpuclk_rates));
 
-	rockchip_register_softrst(np, 11, reg_base + RK3328_SOFTRST_CON(0),
+	rockchip_register_softrst(np, 12, reg_base + RK3328_SOFTRST_CON(0),
 				  ROCKCHIP_SOFTRST_HIWORD_MASK);
 
 	rockchip_register_restart_notifier(ctx, RK3328_GLB_SRST_FST, NULL);
-- 
2.17.1


^ permalink raw reply related	[flat|nested] 9+ messages in thread
* [PATCH] clk: rockchip: fix wrong clock definitions for rk3328
@ 2019-03-10 12:00 ` Jonas Karlman
  0 siblings, 0 replies; 9+ messages in thread
From: Jonas Karlman @ 2019-03-10 12:00 UTC (permalink / raw)
  To: linux-clk-u79uwXL29TY76Z2rM5mHXA,
	linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
	linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
  Cc: Stephen Boyd, Michael Turquette, Jonas Karlman, Heiko Stuebner,
	linux-kernel-u79uwXL29TY76Z2rM5mHXA

This patch fixes definition of several clock gate and select register
that is wrong for rk3328 referring to the TRM and vendor kernel.
Also use correct number of softrst registers.

Fix clock definition for:
- clk_crypto
- aclk_h265
- pclk_h265
- aclk_h264
- hclk_h264
- aclk_axisram
- aclk_gmac
- aclk_usb3otg

Fixes: fe3511ad8a1c ("clk: rockchip: add clock controller for rk3328")
Signed-off-by: Jonas Karlman <jonas-uIzNG4q0ceqzQB+pC5nmwQ@public.gmane.org>
---
 drivers/clk/rockchip/clk-rk3328.c | 18 +++++++++---------
 1 file changed, 9 insertions(+), 9 deletions(-)

diff --git a/drivers/clk/rockchip/clk-rk3328.c b/drivers/clk/rockchip/clk-rk3328.c
index faa94adb2a37..5f6b6bcc2149 100644
--- a/drivers/clk/rockchip/clk-rk3328.c
+++ b/drivers/clk/rockchip/clk-rk3328.c
@@ -458,7 +458,7 @@ static struct rockchip_clk_branch rk3328_clk_branches[] __initdata = {
 			RK3328_CLKSEL_CON(35), 15, 1, MFLAGS, 8, 7, DFLAGS,
 			RK3328_CLKGATE_CON(2), 12, GFLAGS),
 	COMPOSITE(SCLK_CRYPTO, "clk_crypto", mux_2plls_p, 0,
-			RK3328_CLKSEL_CON(20), 7, 1, MFLAGS, 0, 7, DFLAGS,
+			RK3328_CLKSEL_CON(20), 7, 1, MFLAGS, 0, 5, DFLAGS,
 			RK3328_CLKGATE_CON(2), 4, GFLAGS),
 	COMPOSITE_NOMUX(SCLK_TSADC, "clk_tsadc", "clk_24m", 0,
 			RK3328_CLKSEL_CON(22), 0, 10, DFLAGS,
@@ -550,15 +550,15 @@ static struct rockchip_clk_branch rk3328_clk_branches[] __initdata = {
 	GATE(0, "hclk_rkvenc_niu", "hclk_rkvenc", 0,
 			RK3328_CLKGATE_CON(25), 1, GFLAGS),
 	GATE(ACLK_H265, "aclk_h265", "aclk_rkvenc", 0,
-			RK3328_CLKGATE_CON(25), 0, GFLAGS),
+			RK3328_CLKGATE_CON(25), 2, GFLAGS),
 	GATE(PCLK_H265, "pclk_h265", "hclk_rkvenc", 0,
-			RK3328_CLKGATE_CON(25), 1, GFLAGS),
+			RK3328_CLKGATE_CON(25), 3, GFLAGS),
 	GATE(ACLK_H264, "aclk_h264", "aclk_rkvenc", 0,
-			RK3328_CLKGATE_CON(25), 0, GFLAGS),
+			RK3328_CLKGATE_CON(25), 4, GFLAGS),
 	GATE(HCLK_H264, "hclk_h264", "hclk_rkvenc", 0,
-			RK3328_CLKGATE_CON(25), 1, GFLAGS),
+			RK3328_CLKGATE_CON(25), 5, GFLAGS),
 	GATE(ACLK_AXISRAM, "aclk_axisram", "aclk_rkvenc", CLK_IGNORE_UNUSED,
-			RK3328_CLKGATE_CON(25), 0, GFLAGS),
+			RK3328_CLKGATE_CON(25), 6, GFLAGS),
 
 	COMPOSITE(SCLK_VENC_CORE, "sclk_venc_core", mux_4plls_p, 0,
 			RK3328_CLKSEL_CON(51), 14, 2, MFLAGS, 8, 5, DFLAGS,
@@ -663,7 +663,7 @@ static struct rockchip_clk_branch rk3328_clk_branches[] __initdata = {
 
 	/* PD_GMAC */
 	COMPOSITE(ACLK_GMAC, "aclk_gmac", mux_2plls_hdmiphy_p, 0,
-			RK3328_CLKSEL_CON(35), 6, 2, MFLAGS, 0, 5, DFLAGS,
+			RK3328_CLKSEL_CON(25), 6, 2, MFLAGS, 0, 5, DFLAGS,
 			RK3328_CLKGATE_CON(3), 2, GFLAGS),
 	COMPOSITE_NOMUX(PCLK_GMAC, "pclk_gmac", "aclk_gmac", 0,
 			RK3328_CLKSEL_CON(25), 8, 3, DFLAGS,
@@ -733,7 +733,7 @@ static struct rockchip_clk_branch rk3328_clk_branches[] __initdata = {
 
 	/* PD_PERI */
 	GATE(0, "aclk_peri_noc", "aclk_peri", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(19), 11, GFLAGS),
-	GATE(ACLK_USB3OTG, "aclk_usb3otg", "aclk_peri", 0, RK3328_CLKGATE_CON(19), 4, GFLAGS),
+	GATE(ACLK_USB3OTG, "aclk_usb3otg", "aclk_peri", 0, RK3328_CLKGATE_CON(19), 14, GFLAGS),
 
 	GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_peri", 0, RK3328_CLKGATE_CON(19), 0, GFLAGS),
 	GATE(HCLK_SDIO, "hclk_sdio", "hclk_peri", 0, RK3328_CLKGATE_CON(19), 1, GFLAGS),
@@ -913,7 +913,7 @@ static void __init rk3328_clk_init(struct device_node *np)
 				     &rk3328_cpuclk_data, rk3328_cpuclk_rates,
 				     ARRAY_SIZE(rk3328_cpuclk_rates));
 
-	rockchip_register_softrst(np, 11, reg_base + RK3328_SOFTRST_CON(0),
+	rockchip_register_softrst(np, 12, reg_base + RK3328_SOFTRST_CON(0),
 				  ROCKCHIP_SOFTRST_HIWORD_MASK);
 
 	rockchip_register_restart_notifier(ctx, RK3328_GLB_SRST_FST, NULL);
-- 
2.17.1

^ permalink raw reply related	[flat|nested] 9+ messages in thread
* [PATCH] clk: rockchip: fix wrong clock definitions for rk3328
@ 2019-03-10 12:00 ` Jonas Karlman
  0 siblings, 0 replies; 9+ messages in thread
From: Jonas Karlman @ 2019-03-10 12:00 UTC (permalink / raw)
  To: linux-clk, linux-rockchip, linux-arm-kernel
  Cc: Stephen Boyd, Michael Turquette, Jonas Karlman, Heiko Stuebner,
	linux-kernel

This patch fixes definition of several clock gate and select register
that is wrong for rk3328 referring to the TRM and vendor kernel.
Also use correct number of softrst registers.

Fix clock definition for:
- clk_crypto
- aclk_h265
- pclk_h265
- aclk_h264
- hclk_h264
- aclk_axisram
- aclk_gmac
- aclk_usb3otg

Fixes: fe3511ad8a1c ("clk: rockchip: add clock controller for rk3328")
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
---
 drivers/clk/rockchip/clk-rk3328.c | 18 +++++++++---------
 1 file changed, 9 insertions(+), 9 deletions(-)

diff --git a/drivers/clk/rockchip/clk-rk3328.c b/drivers/clk/rockchip/clk-rk3328.c
index faa94adb2a37..5f6b6bcc2149 100644
--- a/drivers/clk/rockchip/clk-rk3328.c
+++ b/drivers/clk/rockchip/clk-rk3328.c
@@ -458,7 +458,7 @@ static struct rockchip_clk_branch rk3328_clk_branches[] __initdata = {
 			RK3328_CLKSEL_CON(35), 15, 1, MFLAGS, 8, 7, DFLAGS,
 			RK3328_CLKGATE_CON(2), 12, GFLAGS),
 	COMPOSITE(SCLK_CRYPTO, "clk_crypto", mux_2plls_p, 0,
-			RK3328_CLKSEL_CON(20), 7, 1, MFLAGS, 0, 7, DFLAGS,
+			RK3328_CLKSEL_CON(20), 7, 1, MFLAGS, 0, 5, DFLAGS,
 			RK3328_CLKGATE_CON(2), 4, GFLAGS),
 	COMPOSITE_NOMUX(SCLK_TSADC, "clk_tsadc", "clk_24m", 0,
 			RK3328_CLKSEL_CON(22), 0, 10, DFLAGS,
@@ -550,15 +550,15 @@ static struct rockchip_clk_branch rk3328_clk_branches[] __initdata = {
 	GATE(0, "hclk_rkvenc_niu", "hclk_rkvenc", 0,
 			RK3328_CLKGATE_CON(25), 1, GFLAGS),
 	GATE(ACLK_H265, "aclk_h265", "aclk_rkvenc", 0,
-			RK3328_CLKGATE_CON(25), 0, GFLAGS),
+			RK3328_CLKGATE_CON(25), 2, GFLAGS),
 	GATE(PCLK_H265, "pclk_h265", "hclk_rkvenc", 0,
-			RK3328_CLKGATE_CON(25), 1, GFLAGS),
+			RK3328_CLKGATE_CON(25), 3, GFLAGS),
 	GATE(ACLK_H264, "aclk_h264", "aclk_rkvenc", 0,
-			RK3328_CLKGATE_CON(25), 0, GFLAGS),
+			RK3328_CLKGATE_CON(25), 4, GFLAGS),
 	GATE(HCLK_H264, "hclk_h264", "hclk_rkvenc", 0,
-			RK3328_CLKGATE_CON(25), 1, GFLAGS),
+			RK3328_CLKGATE_CON(25), 5, GFLAGS),
 	GATE(ACLK_AXISRAM, "aclk_axisram", "aclk_rkvenc", CLK_IGNORE_UNUSED,
-			RK3328_CLKGATE_CON(25), 0, GFLAGS),
+			RK3328_CLKGATE_CON(25), 6, GFLAGS),
 
 	COMPOSITE(SCLK_VENC_CORE, "sclk_venc_core", mux_4plls_p, 0,
 			RK3328_CLKSEL_CON(51), 14, 2, MFLAGS, 8, 5, DFLAGS,
@@ -663,7 +663,7 @@ static struct rockchip_clk_branch rk3328_clk_branches[] __initdata = {
 
 	/* PD_GMAC */
 	COMPOSITE(ACLK_GMAC, "aclk_gmac", mux_2plls_hdmiphy_p, 0,
-			RK3328_CLKSEL_CON(35), 6, 2, MFLAGS, 0, 5, DFLAGS,
+			RK3328_CLKSEL_CON(25), 6, 2, MFLAGS, 0, 5, DFLAGS,
 			RK3328_CLKGATE_CON(3), 2, GFLAGS),
 	COMPOSITE_NOMUX(PCLK_GMAC, "pclk_gmac", "aclk_gmac", 0,
 			RK3328_CLKSEL_CON(25), 8, 3, DFLAGS,
@@ -733,7 +733,7 @@ static struct rockchip_clk_branch rk3328_clk_branches[] __initdata = {
 
 	/* PD_PERI */
 	GATE(0, "aclk_peri_noc", "aclk_peri", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(19), 11, GFLAGS),
-	GATE(ACLK_USB3OTG, "aclk_usb3otg", "aclk_peri", 0, RK3328_CLKGATE_CON(19), 4, GFLAGS),
+	GATE(ACLK_USB3OTG, "aclk_usb3otg", "aclk_peri", 0, RK3328_CLKGATE_CON(19), 14, GFLAGS),
 
 	GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_peri", 0, RK3328_CLKGATE_CON(19), 0, GFLAGS),
 	GATE(HCLK_SDIO, "hclk_sdio", "hclk_peri", 0, RK3328_CLKGATE_CON(19), 1, GFLAGS),
@@ -913,7 +913,7 @@ static void __init rk3328_clk_init(struct device_node *np)
 				     &rk3328_cpuclk_data, rk3328_cpuclk_rates,
 				     ARRAY_SIZE(rk3328_cpuclk_rates));
 
-	rockchip_register_softrst(np, 11, reg_base + RK3328_SOFTRST_CON(0),
+	rockchip_register_softrst(np, 12, reg_base + RK3328_SOFTRST_CON(0),
 				  ROCKCHIP_SOFTRST_HIWORD_MASK);
 
 	rockchip_register_restart_notifier(ctx, RK3328_GLB_SRST_FST, NULL);
-- 
2.17.1


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^ permalink raw reply related	[flat|nested] 9+ messages in thread
* Re: [PATCH] clk: rockchip: fix wrong clock definitions for rk3328
  2019-03-10 12:00 ` Jonas Karlman
  (?)
@ 2019-03-10 16:46   ` Peter Geis
  -1 siblings, 0 replies; 9+ messages in thread
From: Peter Geis @ 2019-03-10 16:46 UTC (permalink / raw)
  To: Jonas Karlman, linux-clk, linux-rockchip, linux-arm-kernel
  Cc: Stephen Boyd, Michael Turquette, Heiko Stuebner, linux-kernel

On 3/10/2019 8:00 AM, Jonas Karlman wrote:
> This patch fixes definition of several clock gate and select register
> that is wrong for rk3328 referring to the TRM and vendor kernel.
> Also use correct number of softrst registers.
> 
> Fix clock definition for:
> - clk_crypto
> - aclk_h265
> - pclk_h265
> - aclk_h264
> - hclk_h264
> - aclk_axisram
> - aclk_gmac
> - aclk_usb3otg
> 
> Fixes: fe3511ad8a1c ("clk: rockchip: add clock controller for rk3328")
> Signed-off-by: Jonas Karlman <jonas@kwiboo.se>

Tested on the rk3328-roc-cc.

Tested-by: Peter Geis <pgwipeout@gmail.com>

> ---
>   drivers/clk/rockchip/clk-rk3328.c | 18 +++++++++---------
>   1 file changed, 9 insertions(+), 9 deletions(-)
> 
> diff --git a/drivers/clk/rockchip/clk-rk3328.c b/drivers/clk/rockchip/clk-rk3328.c
> index faa94adb2a37..5f6b6bcc2149 100644
> --- a/drivers/clk/rockchip/clk-rk3328.c
> +++ b/drivers/clk/rockchip/clk-rk3328.c
> @@ -458,7 +458,7 @@ static struct rockchip_clk_branch rk3328_clk_branches[] __initdata = {
>   			RK3328_CLKSEL_CON(35), 15, 1, MFLAGS, 8, 7, DFLAGS,
>   			RK3328_CLKGATE_CON(2), 12, GFLAGS),
>   	COMPOSITE(SCLK_CRYPTO, "clk_crypto", mux_2plls_p, 0,
> -			RK3328_CLKSEL_CON(20), 7, 1, MFLAGS, 0, 7, DFLAGS,
> +			RK3328_CLKSEL_CON(20), 7, 1, MFLAGS, 0, 5, DFLAGS,
>   			RK3328_CLKGATE_CON(2), 4, GFLAGS),
>   	COMPOSITE_NOMUX(SCLK_TSADC, "clk_tsadc", "clk_24m", 0,
>   			RK3328_CLKSEL_CON(22), 0, 10, DFLAGS,
> @@ -550,15 +550,15 @@ static struct rockchip_clk_branch rk3328_clk_branches[] __initdata = {
>   	GATE(0, "hclk_rkvenc_niu", "hclk_rkvenc", 0,
>   			RK3328_CLKGATE_CON(25), 1, GFLAGS),
>   	GATE(ACLK_H265, "aclk_h265", "aclk_rkvenc", 0,
> -			RK3328_CLKGATE_CON(25), 0, GFLAGS),
> +			RK3328_CLKGATE_CON(25), 2, GFLAGS),
>   	GATE(PCLK_H265, "pclk_h265", "hclk_rkvenc", 0,
> -			RK3328_CLKGATE_CON(25), 1, GFLAGS),
> +			RK3328_CLKGATE_CON(25), 3, GFLAGS),
>   	GATE(ACLK_H264, "aclk_h264", "aclk_rkvenc", 0,
> -			RK3328_CLKGATE_CON(25), 0, GFLAGS),
> +			RK3328_CLKGATE_CON(25), 4, GFLAGS),
>   	GATE(HCLK_H264, "hclk_h264", "hclk_rkvenc", 0,
> -			RK3328_CLKGATE_CON(25), 1, GFLAGS),
> +			RK3328_CLKGATE_CON(25), 5, GFLAGS),
>   	GATE(ACLK_AXISRAM, "aclk_axisram", "aclk_rkvenc", CLK_IGNORE_UNUSED,
> -			RK3328_CLKGATE_CON(25), 0, GFLAGS),
> +			RK3328_CLKGATE_CON(25), 6, GFLAGS),
>   
>   	COMPOSITE(SCLK_VENC_CORE, "sclk_venc_core", mux_4plls_p, 0,
>   			RK3328_CLKSEL_CON(51), 14, 2, MFLAGS, 8, 5, DFLAGS,
> @@ -663,7 +663,7 @@ static struct rockchip_clk_branch rk3328_clk_branches[] __initdata = {
>   
>   	/* PD_GMAC */
>   	COMPOSITE(ACLK_GMAC, "aclk_gmac", mux_2plls_hdmiphy_p, 0,
> -			RK3328_CLKSEL_CON(35), 6, 2, MFLAGS, 0, 5, DFLAGS,
> +			RK3328_CLKSEL_CON(25), 6, 2, MFLAGS, 0, 5, DFLAGS,
>   			RK3328_CLKGATE_CON(3), 2, GFLAGS),
>   	COMPOSITE_NOMUX(PCLK_GMAC, "pclk_gmac", "aclk_gmac", 0,
>   			RK3328_CLKSEL_CON(25), 8, 3, DFLAGS,
> @@ -733,7 +733,7 @@ static struct rockchip_clk_branch rk3328_clk_branches[] __initdata = {
>   
>   	/* PD_PERI */
>   	GATE(0, "aclk_peri_noc", "aclk_peri", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(19), 11, GFLAGS),
> -	GATE(ACLK_USB3OTG, "aclk_usb3otg", "aclk_peri", 0, RK3328_CLKGATE_CON(19), 4, GFLAGS),
> +	GATE(ACLK_USB3OTG, "aclk_usb3otg", "aclk_peri", 0, RK3328_CLKGATE_CON(19), 14, GFLAGS),
>   
>   	GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_peri", 0, RK3328_CLKGATE_CON(19), 0, GFLAGS),
>   	GATE(HCLK_SDIO, "hclk_sdio", "hclk_peri", 0, RK3328_CLKGATE_CON(19), 1, GFLAGS),
> @@ -913,7 +913,7 @@ static void __init rk3328_clk_init(struct device_node *np)
>   				     &rk3328_cpuclk_data, rk3328_cpuclk_rates,
>   				     ARRAY_SIZE(rk3328_cpuclk_rates));
>   
> -	rockchip_register_softrst(np, 11, reg_base + RK3328_SOFTRST_CON(0),
> +	rockchip_register_softrst(np, 12, reg_base + RK3328_SOFTRST_CON(0),
>   				  ROCKCHIP_SOFTRST_HIWORD_MASK);
>   
>   	rockchip_register_restart_notifier(ctx, RK3328_GLB_SRST_FST, NULL);
> 

^ permalink raw reply	[flat|nested] 9+ messages in thread
* Re: [PATCH] clk: rockchip: fix wrong clock definitions for rk3328
@ 2019-03-10 16:46   ` Peter Geis
  0 siblings, 0 replies; 9+ messages in thread
From: Peter Geis @ 2019-03-10 16:46 UTC (permalink / raw)
  To: Jonas Karlman, linux-clk, linux-rockchip, linux-arm-kernel
  Cc: Stephen Boyd, Michael Turquette, Heiko Stuebner, linux-kernel

On 3/10/2019 8:00 AM, Jonas Karlman wrote:
> This patch fixes definition of several clock gate and select register
> that is wrong for rk3328 referring to the TRM and vendor kernel.
> Also use correct number of softrst registers.
> 
> Fix clock definition for:
> - clk_crypto
> - aclk_h265
> - pclk_h265
> - aclk_h264
> - hclk_h264
> - aclk_axisram
> - aclk_gmac
> - aclk_usb3otg
> 
> Fixes: fe3511ad8a1c ("clk: rockchip: add clock controller for rk3328")
> Signed-off-by: Jonas Karlman <jonas@kwiboo.se>

Tested on the rk3328-roc-cc.

Tested-by: Peter Geis <pgwipeout@gmail.com>

> ---
>   drivers/clk/rockchip/clk-rk3328.c | 18 +++++++++---------
>   1 file changed, 9 insertions(+), 9 deletions(-)
> 
> diff --git a/drivers/clk/rockchip/clk-rk3328.c b/drivers/clk/rockchip/clk-rk3328.c
> index faa94adb2a37..5f6b6bcc2149 100644
> --- a/drivers/clk/rockchip/clk-rk3328.c
> +++ b/drivers/clk/rockchip/clk-rk3328.c
> @@ -458,7 +458,7 @@ static struct rockchip_clk_branch rk3328_clk_branches[] __initdata = {
>   			RK3328_CLKSEL_CON(35), 15, 1, MFLAGS, 8, 7, DFLAGS,
>   			RK3328_CLKGATE_CON(2), 12, GFLAGS),
>   	COMPOSITE(SCLK_CRYPTO, "clk_crypto", mux_2plls_p, 0,
> -			RK3328_CLKSEL_CON(20), 7, 1, MFLAGS, 0, 7, DFLAGS,
> +			RK3328_CLKSEL_CON(20), 7, 1, MFLAGS, 0, 5, DFLAGS,
>   			RK3328_CLKGATE_CON(2), 4, GFLAGS),
>   	COMPOSITE_NOMUX(SCLK_TSADC, "clk_tsadc", "clk_24m", 0,
>   			RK3328_CLKSEL_CON(22), 0, 10, DFLAGS,
> @@ -550,15 +550,15 @@ static struct rockchip_clk_branch rk3328_clk_branches[] __initdata = {
>   	GATE(0, "hclk_rkvenc_niu", "hclk_rkvenc", 0,
>   			RK3328_CLKGATE_CON(25), 1, GFLAGS),
>   	GATE(ACLK_H265, "aclk_h265", "aclk_rkvenc", 0,
> -			RK3328_CLKGATE_CON(25), 0, GFLAGS),
> +			RK3328_CLKGATE_CON(25), 2, GFLAGS),
>   	GATE(PCLK_H265, "pclk_h265", "hclk_rkvenc", 0,
> -			RK3328_CLKGATE_CON(25), 1, GFLAGS),
> +			RK3328_CLKGATE_CON(25), 3, GFLAGS),
>   	GATE(ACLK_H264, "aclk_h264", "aclk_rkvenc", 0,
> -			RK3328_CLKGATE_CON(25), 0, GFLAGS),
> +			RK3328_CLKGATE_CON(25), 4, GFLAGS),
>   	GATE(HCLK_H264, "hclk_h264", "hclk_rkvenc", 0,
> -			RK3328_CLKGATE_CON(25), 1, GFLAGS),
> +			RK3328_CLKGATE_CON(25), 5, GFLAGS),
>   	GATE(ACLK_AXISRAM, "aclk_axisram", "aclk_rkvenc", CLK_IGNORE_UNUSED,
> -			RK3328_CLKGATE_CON(25), 0, GFLAGS),
> +			RK3328_CLKGATE_CON(25), 6, GFLAGS),
>   
>   	COMPOSITE(SCLK_VENC_CORE, "sclk_venc_core", mux_4plls_p, 0,
>   			RK3328_CLKSEL_CON(51), 14, 2, MFLAGS, 8, 5, DFLAGS,
> @@ -663,7 +663,7 @@ static struct rockchip_clk_branch rk3328_clk_branches[] __initdata = {
>   
>   	/* PD_GMAC */
>   	COMPOSITE(ACLK_GMAC, "aclk_gmac", mux_2plls_hdmiphy_p, 0,
> -			RK3328_CLKSEL_CON(35), 6, 2, MFLAGS, 0, 5, DFLAGS,
> +			RK3328_CLKSEL_CON(25), 6, 2, MFLAGS, 0, 5, DFLAGS,
>   			RK3328_CLKGATE_CON(3), 2, GFLAGS),
>   	COMPOSITE_NOMUX(PCLK_GMAC, "pclk_gmac", "aclk_gmac", 0,
>   			RK3328_CLKSEL_CON(25), 8, 3, DFLAGS,
> @@ -733,7 +733,7 @@ static struct rockchip_clk_branch rk3328_clk_branches[] __initdata = {
>   
>   	/* PD_PERI */
>   	GATE(0, "aclk_peri_noc", "aclk_peri", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(19), 11, GFLAGS),
> -	GATE(ACLK_USB3OTG, "aclk_usb3otg", "aclk_peri", 0, RK3328_CLKGATE_CON(19), 4, GFLAGS),
> +	GATE(ACLK_USB3OTG, "aclk_usb3otg", "aclk_peri", 0, RK3328_CLKGATE_CON(19), 14, GFLAGS),
>   
>   	GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_peri", 0, RK3328_CLKGATE_CON(19), 0, GFLAGS),
>   	GATE(HCLK_SDIO, "hclk_sdio", "hclk_peri", 0, RK3328_CLKGATE_CON(19), 1, GFLAGS),
> @@ -913,7 +913,7 @@ static void __init rk3328_clk_init(struct device_node *np)
>   				     &rk3328_cpuclk_data, rk3328_cpuclk_rates,
>   				     ARRAY_SIZE(rk3328_cpuclk_rates));
>   
> -	rockchip_register_softrst(np, 11, reg_base + RK3328_SOFTRST_CON(0),
> +	rockchip_register_softrst(np, 12, reg_base + RK3328_SOFTRST_CON(0),
>   				  ROCKCHIP_SOFTRST_HIWORD_MASK);
>   
>   	rockchip_register_restart_notifier(ctx, RK3328_GLB_SRST_FST, NULL);
> 

^ permalink raw reply	[flat|nested] 9+ messages in thread
* Re: [PATCH] clk: rockchip: fix wrong clock definitions for rk3328
@ 2019-03-10 16:46   ` Peter Geis
  0 siblings, 0 replies; 9+ messages in thread
From: Peter Geis @ 2019-03-10 16:46 UTC (permalink / raw)
  To: Jonas Karlman, linux-clk, linux-rockchip, linux-arm-kernel
  Cc: Stephen Boyd, Michael Turquette, Heiko Stuebner, linux-kernel

On 3/10/2019 8:00 AM, Jonas Karlman wrote:
> This patch fixes definition of several clock gate and select register
> that is wrong for rk3328 referring to the TRM and vendor kernel.
> Also use correct number of softrst registers.
> 
> Fix clock definition for:
> - clk_crypto
> - aclk_h265
> - pclk_h265
> - aclk_h264
> - hclk_h264
> - aclk_axisram
> - aclk_gmac
> - aclk_usb3otg
> 
> Fixes: fe3511ad8a1c ("clk: rockchip: add clock controller for rk3328")
> Signed-off-by: Jonas Karlman <jonas@kwiboo.se>

Tested on the rk3328-roc-cc.

Tested-by: Peter Geis <pgwipeout@gmail.com>

> ---
>   drivers/clk/rockchip/clk-rk3328.c | 18 +++++++++---------
>   1 file changed, 9 insertions(+), 9 deletions(-)
> 
> diff --git a/drivers/clk/rockchip/clk-rk3328.c b/drivers/clk/rockchip/clk-rk3328.c
> index faa94adb2a37..5f6b6bcc2149 100644
> --- a/drivers/clk/rockchip/clk-rk3328.c
> +++ b/drivers/clk/rockchip/clk-rk3328.c
> @@ -458,7 +458,7 @@ static struct rockchip_clk_branch rk3328_clk_branches[] __initdata = {
>   			RK3328_CLKSEL_CON(35), 15, 1, MFLAGS, 8, 7, DFLAGS,
>   			RK3328_CLKGATE_CON(2), 12, GFLAGS),
>   	COMPOSITE(SCLK_CRYPTO, "clk_crypto", mux_2plls_p, 0,
> -			RK3328_CLKSEL_CON(20), 7, 1, MFLAGS, 0, 7, DFLAGS,
> +			RK3328_CLKSEL_CON(20), 7, 1, MFLAGS, 0, 5, DFLAGS,
>   			RK3328_CLKGATE_CON(2), 4, GFLAGS),
>   	COMPOSITE_NOMUX(SCLK_TSADC, "clk_tsadc", "clk_24m", 0,
>   			RK3328_CLKSEL_CON(22), 0, 10, DFLAGS,
> @@ -550,15 +550,15 @@ static struct rockchip_clk_branch rk3328_clk_branches[] __initdata = {
>   	GATE(0, "hclk_rkvenc_niu", "hclk_rkvenc", 0,
>   			RK3328_CLKGATE_CON(25), 1, GFLAGS),
>   	GATE(ACLK_H265, "aclk_h265", "aclk_rkvenc", 0,
> -			RK3328_CLKGATE_CON(25), 0, GFLAGS),
> +			RK3328_CLKGATE_CON(25), 2, GFLAGS),
>   	GATE(PCLK_H265, "pclk_h265", "hclk_rkvenc", 0,
> -			RK3328_CLKGATE_CON(25), 1, GFLAGS),
> +			RK3328_CLKGATE_CON(25), 3, GFLAGS),
>   	GATE(ACLK_H264, "aclk_h264", "aclk_rkvenc", 0,
> -			RK3328_CLKGATE_CON(25), 0, GFLAGS),
> +			RK3328_CLKGATE_CON(25), 4, GFLAGS),
>   	GATE(HCLK_H264, "hclk_h264", "hclk_rkvenc", 0,
> -			RK3328_CLKGATE_CON(25), 1, GFLAGS),
> +			RK3328_CLKGATE_CON(25), 5, GFLAGS),
>   	GATE(ACLK_AXISRAM, "aclk_axisram", "aclk_rkvenc", CLK_IGNORE_UNUSED,
> -			RK3328_CLKGATE_CON(25), 0, GFLAGS),
> +			RK3328_CLKGATE_CON(25), 6, GFLAGS),
>   
>   	COMPOSITE(SCLK_VENC_CORE, "sclk_venc_core", mux_4plls_p, 0,
>   			RK3328_CLKSEL_CON(51), 14, 2, MFLAGS, 8, 5, DFLAGS,
> @@ -663,7 +663,7 @@ static struct rockchip_clk_branch rk3328_clk_branches[] __initdata = {
>   
>   	/* PD_GMAC */
>   	COMPOSITE(ACLK_GMAC, "aclk_gmac", mux_2plls_hdmiphy_p, 0,
> -			RK3328_CLKSEL_CON(35), 6, 2, MFLAGS, 0, 5, DFLAGS,
> +			RK3328_CLKSEL_CON(25), 6, 2, MFLAGS, 0, 5, DFLAGS,
>   			RK3328_CLKGATE_CON(3), 2, GFLAGS),
>   	COMPOSITE_NOMUX(PCLK_GMAC, "pclk_gmac", "aclk_gmac", 0,
>   			RK3328_CLKSEL_CON(25), 8, 3, DFLAGS,
> @@ -733,7 +733,7 @@ static struct rockchip_clk_branch rk3328_clk_branches[] __initdata = {
>   
>   	/* PD_PERI */
>   	GATE(0, "aclk_peri_noc", "aclk_peri", CLK_IGNORE_UNUSED, RK3328_CLKGATE_CON(19), 11, GFLAGS),
> -	GATE(ACLK_USB3OTG, "aclk_usb3otg", "aclk_peri", 0, RK3328_CLKGATE_CON(19), 4, GFLAGS),
> +	GATE(ACLK_USB3OTG, "aclk_usb3otg", "aclk_peri", 0, RK3328_CLKGATE_CON(19), 14, GFLAGS),
>   
>   	GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_peri", 0, RK3328_CLKGATE_CON(19), 0, GFLAGS),
>   	GATE(HCLK_SDIO, "hclk_sdio", "hclk_peri", 0, RK3328_CLKGATE_CON(19), 1, GFLAGS),
> @@ -913,7 +913,7 @@ static void __init rk3328_clk_init(struct device_node *np)
>   				     &rk3328_cpuclk_data, rk3328_cpuclk_rates,
>   				     ARRAY_SIZE(rk3328_cpuclk_rates));
>   
> -	rockchip_register_softrst(np, 11, reg_base + RK3328_SOFTRST_CON(0),
> +	rockchip_register_softrst(np, 12, reg_base + RK3328_SOFTRST_CON(0),
>   				  ROCKCHIP_SOFTRST_HIWORD_MASK);
>   
>   	rockchip_register_restart_notifier(ctx, RK3328_GLB_SRST_FST, NULL);
> 

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 9+ messages in thread
* Re: [PATCH] clk: rockchip: fix wrong clock definitions for rk3328
@ 2019-03-12 10:50   ` Heiko Stuebner
  0 siblings, 0 replies; 9+ messages in thread
From: Heiko Stuebner @ 2019-03-12 10:50 UTC (permalink / raw)
  To: Jonas Karlman
  Cc: linux-clk, linux-rockchip, linux-arm-kernel, Michael Turquette,
	Stephen Boyd, linux-kernel

Am Sonntag, 10. März 2019, 13:00:45 CET schrieb Jonas Karlman:
> This patch fixes definition of several clock gate and select register
> that is wrong for rk3328 referring to the TRM and vendor kernel.
> Also use correct number of softrst registers.
> 
> Fix clock definition for:
> - clk_crypto
> - aclk_h265
> - pclk_h265
> - aclk_h264
> - hclk_h264
> - aclk_axisram
> - aclk_gmac
> - aclk_usb3otg
> 
> Fixes: fe3511ad8a1c ("clk: rockchip: add clock controller for rk3328")
> Signed-off-by: Jonas Karlman <jonas@kwiboo.se>

applied for 5.2 after checking the TRM

Thanks for fixing this
Heiko



^ permalink raw reply	[flat|nested] 9+ messages in thread
* Re: [PATCH] clk: rockchip: fix wrong clock definitions for rk3328
@ 2019-03-12 10:50   ` Heiko Stuebner
  0 siblings, 0 replies; 9+ messages in thread
From: Heiko Stuebner @ 2019-03-12 10:50 UTC (permalink / raw)
  To: Jonas Karlman
  Cc: Stephen Boyd, Michael Turquette,
	linux-kernel-u79uwXL29TY76Z2rM5mHXA,
	linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
	linux-clk-u79uwXL29TY76Z2rM5mHXA,
	linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r

Am Sonntag, 10. März 2019, 13:00:45 CET schrieb Jonas Karlman:
> This patch fixes definition of several clock gate and select register
> that is wrong for rk3328 referring to the TRM and vendor kernel.
> Also use correct number of softrst registers.
> 
> Fix clock definition for:
> - clk_crypto
> - aclk_h265
> - pclk_h265
> - aclk_h264
> - hclk_h264
> - aclk_axisram
> - aclk_gmac
> - aclk_usb3otg
> 
> Fixes: fe3511ad8a1c ("clk: rockchip: add clock controller for rk3328")
> Signed-off-by: Jonas Karlman <jonas-uIzNG4q0ceqzQB+pC5nmwQ@public.gmane.org>

applied for 5.2 after checking the TRM

Thanks for fixing this
Heiko

^ permalink raw reply	[flat|nested] 9+ messages in thread
* Re: [PATCH] clk: rockchip: fix wrong clock definitions for rk3328
@ 2019-03-12 10:50   ` Heiko Stuebner
  0 siblings, 0 replies; 9+ messages in thread
From: Heiko Stuebner @ 2019-03-12 10:50 UTC (permalink / raw)
  To: Jonas Karlman
  Cc: Stephen Boyd, Michael Turquette, linux-kernel, linux-rockchip,
	linux-clk, linux-arm-kernel

Am Sonntag, 10. März 2019, 13:00:45 CET schrieb Jonas Karlman:
> This patch fixes definition of several clock gate and select register
> that is wrong for rk3328 referring to the TRM and vendor kernel.
> Also use correct number of softrst registers.
> 
> Fix clock definition for:
> - clk_crypto
> - aclk_h265
> - pclk_h265
> - aclk_h264
> - hclk_h264
> - aclk_axisram
> - aclk_gmac
> - aclk_usb3otg
> 
> Fixes: fe3511ad8a1c ("clk: rockchip: add clock controller for rk3328")
> Signed-off-by: Jonas Karlman <jonas@kwiboo.se>

applied for 5.2 after checking the TRM

Thanks for fixing this
Heiko



_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 9+ messages in thread
end of thread, other threads:[~2019-03-12 10:50 UTC | newest]

Thread overview: 9+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-03-10 12:00 [PATCH] clk: rockchip: fix wrong clock definitions for rk3328 Jonas Karlman
2019-03-10 12:00 ` Jonas Karlman
2019-03-10 12:00 ` Jonas Karlman
2019-03-10 16:46 ` Peter Geis
2019-03-10 16:46   ` Peter Geis
2019-03-10 16:46   ` Peter Geis
2019-03-12 10:50 ` Heiko Stuebner
2019-03-12 10:50   ` Heiko Stuebner
2019-03-12 10:50   ` Heiko Stuebner

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