* [RFC PATCH v2 0/7] Introduce STM32 system bus
@ 2022-12-22 10:04 ` Gatien Chevallier
0 siblings, 0 replies; 18+ messages in thread
From: Gatien Chevallier @ 2022-12-22 10:04 UTC (permalink / raw)
To: alexandre.torgue, robh+dt, Oleksii_Moisieiev, linus.walleij, gregkh
Cc: linux-stm32, linux-arm-kernel, linux-kernel, loic.pallardy,
devicetree, mark.rutland, arnd, gatien.chevallier
Document STM32 System Bus. This bus is intended to control firewall
access for the peripherals connected to it.
For every peripheral, the bus checks the firewall registers to see
if the peripheral is configured as non-secure. If the peripheral
is configured as secure, the node is marked populated, so the
device won't be probed.
This is useful as a firewall configuration sanity check and avoid
platform crashes in case peripherals are incorrectly configured.
The STM32 System Bus implements the feature-domain-controller
bindings. It is used by peripherals to reference a domain
controller, in this case the firewall feature domain.
The bus uses the ID referenced by the feature-domains property to
know where to look in the firewall to get the security configuration
for the peripheral. This allows a device tree description rather
than a hardcoded peripheral table in the bus driver.
On STM32MP13/15 platforms, the firewall bus is represented by the
ETZPC node, which is responsible for the securing / MCU isolating
the capable peripherals.
STM32MP13/15 device trees are updated in this series to implement
the bus. All peripherals that are securable or MCU isolation capable
by the ETZPC are connected to the bus.
Changes in V2:
- Corrected YAMLS errors highlighted by Rob's robot
- Re-ordered Signed-off-by tags in two patches
Gatien Chevallier (6):
dt-bindings: bus: add STM32 System Bus
dt-bindings: bus: add STM32MP15 ETZPC firewall bus bindings
dt-bindings: bus: add STM32MP13 ETZPC firewall bus bindings
bus: stm32_sys_bus: add support for STM32MP15 and STM32MP13 system bus
ARM: dts: stm32: add ETZPC as a system bus for STM32MP15x boards
ARM: dts: stm32: add ETZPC as a system bus for STM32MP13x boards
Oleksii Moisieiev (1):
dt-bindings: Document common device controller bindings
.../devicetree/bindings/bus/st,sys-bus.yaml | 88 +
.../feature-domain-controller.yaml | 84 +
MAINTAINERS | 6 +
arch/arm/boot/dts/stm32mp131.dtsi | 242 +-
arch/arm/boot/dts/stm32mp151.dtsi | 2737 +++++++++--------
drivers/bus/Kconfig | 9 +
drivers/bus/Makefile | 1 +
drivers/bus/stm32_sys_bus.c | 180 ++
include/dt-bindings/bus/stm32mp13_sys_bus.h | 60 +
include/dt-bindings/bus/stm32mp15_sys_bus.h | 98 +
10 files changed, 2062 insertions(+), 1443 deletions(-)
create mode 100644 Documentation/devicetree/bindings/bus/st,sys-bus.yaml
create mode 100644 Documentation/devicetree/bindings/feature-controllers/feature-domain-controller.yaml
create mode 100644 drivers/bus/stm32_sys_bus.c
create mode 100644 include/dt-bindings/bus/stm32mp13_sys_bus.h
create mode 100644 include/dt-bindings/bus/stm32mp15_sys_bus.h
--
2.25.1
^ permalink raw reply [flat|nested] 18+ messages in thread
* [RFC PATCH v2 0/7] Introduce STM32 system bus
@ 2022-12-22 10:04 ` Gatien Chevallier
0 siblings, 0 replies; 18+ messages in thread
From: Gatien Chevallier @ 2022-12-22 10:04 UTC (permalink / raw)
To: alexandre.torgue, robh+dt, Oleksii_Moisieiev, linus.walleij, gregkh
Cc: linux-stm32, linux-arm-kernel, linux-kernel, loic.pallardy,
devicetree, mark.rutland, arnd, gatien.chevallier
Document STM32 System Bus. This bus is intended to control firewall
access for the peripherals connected to it.
For every peripheral, the bus checks the firewall registers to see
if the peripheral is configured as non-secure. If the peripheral
is configured as secure, the node is marked populated, so the
device won't be probed.
This is useful as a firewall configuration sanity check and avoid
platform crashes in case peripherals are incorrectly configured.
The STM32 System Bus implements the feature-domain-controller
bindings. It is used by peripherals to reference a domain
controller, in this case the firewall feature domain.
The bus uses the ID referenced by the feature-domains property to
know where to look in the firewall to get the security configuration
for the peripheral. This allows a device tree description rather
than a hardcoded peripheral table in the bus driver.
On STM32MP13/15 platforms, the firewall bus is represented by the
ETZPC node, which is responsible for the securing / MCU isolating
the capable peripherals.
STM32MP13/15 device trees are updated in this series to implement
the bus. All peripherals that are securable or MCU isolation capable
by the ETZPC are connected to the bus.
Changes in V2:
- Corrected YAMLS errors highlighted by Rob's robot
- Re-ordered Signed-off-by tags in two patches
Gatien Chevallier (6):
dt-bindings: bus: add STM32 System Bus
dt-bindings: bus: add STM32MP15 ETZPC firewall bus bindings
dt-bindings: bus: add STM32MP13 ETZPC firewall bus bindings
bus: stm32_sys_bus: add support for STM32MP15 and STM32MP13 system bus
ARM: dts: stm32: add ETZPC as a system bus for STM32MP15x boards
ARM: dts: stm32: add ETZPC as a system bus for STM32MP13x boards
Oleksii Moisieiev (1):
dt-bindings: Document common device controller bindings
.../devicetree/bindings/bus/st,sys-bus.yaml | 88 +
.../feature-domain-controller.yaml | 84 +
MAINTAINERS | 6 +
arch/arm/boot/dts/stm32mp131.dtsi | 242 +-
arch/arm/boot/dts/stm32mp151.dtsi | 2737 +++++++++--------
drivers/bus/Kconfig | 9 +
drivers/bus/Makefile | 1 +
drivers/bus/stm32_sys_bus.c | 180 ++
include/dt-bindings/bus/stm32mp13_sys_bus.h | 60 +
include/dt-bindings/bus/stm32mp15_sys_bus.h | 98 +
10 files changed, 2062 insertions(+), 1443 deletions(-)
create mode 100644 Documentation/devicetree/bindings/bus/st,sys-bus.yaml
create mode 100644 Documentation/devicetree/bindings/feature-controllers/feature-domain-controller.yaml
create mode 100644 drivers/bus/stm32_sys_bus.c
create mode 100644 include/dt-bindings/bus/stm32mp13_sys_bus.h
create mode 100644 include/dt-bindings/bus/stm32mp15_sys_bus.h
--
2.25.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 18+ messages in thread
* [RFC PATCH v2 1/7] dt-bindings: Document common device controller bindings
2022-12-22 10:04 ` Gatien Chevallier
@ 2022-12-22 10:04 ` Gatien Chevallier
-1 siblings, 0 replies; 18+ messages in thread
From: Gatien Chevallier @ 2022-12-22 10:04 UTC (permalink / raw)
To: alexandre.torgue, robh+dt, Oleksii_Moisieiev, linus.walleij, gregkh
Cc: linux-stm32, linux-arm-kernel, linux-kernel, loic.pallardy,
devicetree, mark.rutland, arnd, gatien.chevallier,
Oleksii Moisieiev
From: Oleksii Moisieiev <Oleksii_Moisieiev@epam.com>
Introducing of the common device controller bindings for the controller
provider and consumer devices. Those bindings are intended to allow
divided system on chip into muliple domains, that can be used to
configure hardware permissions.
Signed-off-by: Oleksii Moisieiev <oleksii_moisieiev@epam.com>
---
.../feature-domain-controller.yaml | 84 +++++++++++++++++++
1 file changed, 84 insertions(+)
create mode 100644 Documentation/devicetree/bindings/feature-controllers/feature-domain-controller.yaml
diff --git a/Documentation/devicetree/bindings/feature-controllers/feature-domain-controller.yaml b/Documentation/devicetree/bindings/feature-controllers/feature-domain-controller.yaml
new file mode 100644
index 000000000000..90a7c38c833c
--- /dev/null
+++ b/Documentation/devicetree/bindings/feature-controllers/feature-domain-controller.yaml
@@ -0,0 +1,84 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/feature-controllers/feature-domain-controller.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Generic Domain Controller bindings
+
+maintainers:
+ - Oleksii Moisieiev <oleksii_moisieiev@epam.com>
+
+description: |+
+ Common Feature Domains Controller bindings properties
+
+ Domain controllers allow to divided system on chip into multiple feature
+ domains that can be used to select by who hardware blocks could be accessed.
+ A feature domain could be a cluster of CPUs (or coprocessors), a range of
+ addresses or a group of hardware blocks.
+
+ This device tree bindings can be used to bind feature domain consumer devices
+ with their feature domains provided by feature-domains controllers.
+ Feature omain controller provider can be represened by any node in the
+ device tree and can provide one or more configuration parameters, needed to
+ control parameters of the consumer device. A consumer node can refer to the
+ provider by phandle and a set of phandle arguments, specified by
+ '#feature-domain-cells' property in the device controller provider node.
+
+ Device controllers are typically used to set the permissions of the hardware
+ block. The contents of the feature-domains configuration properties are
+ defined by the binding for the individual feature-domains controller device.
+
+ Each node can be a consumer for the several providers. The first
+ configuration of 'feature-domains' or the one named 'default' is applied
+ before probing the device itself.
+
+# always select the core schema
+select: true
+
+properties:
+ '#feature-domain-cells':
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description:
+ Number of cells in a feature-domains controller specifier;
+ Can be any value as specified by device tree binding documentation
+ of a particular provider.
+
+ feature-domain-controller:
+ description:
+ Indicates that the node is feature-domain-controller provider.
+
+ feature-domain-names:
+ $ref: '/schemas/types.yaml#/definitions/string-array'
+ description:
+ A list of feature-domains names, sorted in the same order as
+ feature-domains entries. Consumer drivers will use feature-domain-names
+ to match with existing feature-domains entries.
+
+ feature-domains:
+ $ref: "/schemas/types.yaml#/definitions/phandle-array"
+ description:
+ A list of feature-domains controller specifiers, as defined by the
+ bindings of the feature-domain-controller provider.
+
+additionalProperties: true
+
+examples:
+ - |
+ ctrl0: ctrl@100 {
+ feature-domain-controller;
+ reg = <0x100 0x10>;
+ #feature-domain-cells = <2>;
+ };
+
+ ctrl1: ctrl@110 {
+ feature-domain-controller;
+ reg = <0x110 0x10>;
+ #feature-domain-cells = <3>;
+ };
+
+ foo@0 {
+ reg = <0x0 0x1>;
+ feature-domains = <&ctrl0 1 2>, <&ctrl1 3 4 5>;
+ feature-domain-names = "default", "unbind";
+ };
--
2.25.1
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [RFC PATCH v2 1/7] dt-bindings: Document common device controller bindings
@ 2022-12-22 10:04 ` Gatien Chevallier
0 siblings, 0 replies; 18+ messages in thread
From: Gatien Chevallier @ 2022-12-22 10:04 UTC (permalink / raw)
To: alexandre.torgue, robh+dt, Oleksii_Moisieiev, linus.walleij, gregkh
Cc: linux-stm32, linux-arm-kernel, linux-kernel, loic.pallardy,
devicetree, mark.rutland, arnd, gatien.chevallier,
Oleksii Moisieiev
From: Oleksii Moisieiev <Oleksii_Moisieiev@epam.com>
Introducing of the common device controller bindings for the controller
provider and consumer devices. Those bindings are intended to allow
divided system on chip into muliple domains, that can be used to
configure hardware permissions.
Signed-off-by: Oleksii Moisieiev <oleksii_moisieiev@epam.com>
---
.../feature-domain-controller.yaml | 84 +++++++++++++++++++
1 file changed, 84 insertions(+)
create mode 100644 Documentation/devicetree/bindings/feature-controllers/feature-domain-controller.yaml
diff --git a/Documentation/devicetree/bindings/feature-controllers/feature-domain-controller.yaml b/Documentation/devicetree/bindings/feature-controllers/feature-domain-controller.yaml
new file mode 100644
index 000000000000..90a7c38c833c
--- /dev/null
+++ b/Documentation/devicetree/bindings/feature-controllers/feature-domain-controller.yaml
@@ -0,0 +1,84 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/feature-controllers/feature-domain-controller.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Generic Domain Controller bindings
+
+maintainers:
+ - Oleksii Moisieiev <oleksii_moisieiev@epam.com>
+
+description: |+
+ Common Feature Domains Controller bindings properties
+
+ Domain controllers allow to divided system on chip into multiple feature
+ domains that can be used to select by who hardware blocks could be accessed.
+ A feature domain could be a cluster of CPUs (or coprocessors), a range of
+ addresses or a group of hardware blocks.
+
+ This device tree bindings can be used to bind feature domain consumer devices
+ with their feature domains provided by feature-domains controllers.
+ Feature omain controller provider can be represened by any node in the
+ device tree and can provide one or more configuration parameters, needed to
+ control parameters of the consumer device. A consumer node can refer to the
+ provider by phandle and a set of phandle arguments, specified by
+ '#feature-domain-cells' property in the device controller provider node.
+
+ Device controllers are typically used to set the permissions of the hardware
+ block. The contents of the feature-domains configuration properties are
+ defined by the binding for the individual feature-domains controller device.
+
+ Each node can be a consumer for the several providers. The first
+ configuration of 'feature-domains' or the one named 'default' is applied
+ before probing the device itself.
+
+# always select the core schema
+select: true
+
+properties:
+ '#feature-domain-cells':
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description:
+ Number of cells in a feature-domains controller specifier;
+ Can be any value as specified by device tree binding documentation
+ of a particular provider.
+
+ feature-domain-controller:
+ description:
+ Indicates that the node is feature-domain-controller provider.
+
+ feature-domain-names:
+ $ref: '/schemas/types.yaml#/definitions/string-array'
+ description:
+ A list of feature-domains names, sorted in the same order as
+ feature-domains entries. Consumer drivers will use feature-domain-names
+ to match with existing feature-domains entries.
+
+ feature-domains:
+ $ref: "/schemas/types.yaml#/definitions/phandle-array"
+ description:
+ A list of feature-domains controller specifiers, as defined by the
+ bindings of the feature-domain-controller provider.
+
+additionalProperties: true
+
+examples:
+ - |
+ ctrl0: ctrl@100 {
+ feature-domain-controller;
+ reg = <0x100 0x10>;
+ #feature-domain-cells = <2>;
+ };
+
+ ctrl1: ctrl@110 {
+ feature-domain-controller;
+ reg = <0x110 0x10>;
+ #feature-domain-cells = <3>;
+ };
+
+ foo@0 {
+ reg = <0x0 0x1>;
+ feature-domains = <&ctrl0 1 2>, <&ctrl1 3 4 5>;
+ feature-domain-names = "default", "unbind";
+ };
--
2.25.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [RFC PATCH v2 2/7] dt-bindings: bus: add STM32 System Bus
2022-12-22 10:04 ` Gatien Chevallier
@ 2022-12-22 10:04 ` Gatien Chevallier
-1 siblings, 0 replies; 18+ messages in thread
From: Gatien Chevallier @ 2022-12-22 10:04 UTC (permalink / raw)
To: alexandre.torgue, robh+dt, Oleksii_Moisieiev, linus.walleij, gregkh
Cc: linux-stm32, linux-arm-kernel, linux-kernel, loic.pallardy,
devicetree, mark.rutland, arnd, gatien.chevallier
Document STM32 System Bus. This bus is intended to control firewall
access for the peripherals connected to it.
Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Loic PALLARDY <loic.pallardy@st.com>
---
Changes in V2:
- Corrected errors highlighted by Rob's robot
- Re-ordered Signed-off-by tags
.../devicetree/bindings/bus/st,sys-bus.yaml | 88 +++++++++++++++++++
1 file changed, 88 insertions(+)
create mode 100644 Documentation/devicetree/bindings/bus/st,sys-bus.yaml
diff --git a/Documentation/devicetree/bindings/bus/st,sys-bus.yaml b/Documentation/devicetree/bindings/bus/st,sys-bus.yaml
new file mode 100644
index 000000000000..d246fbdd6dea
--- /dev/null
+++ b/Documentation/devicetree/bindings/bus/st,sys-bus.yaml
@@ -0,0 +1,88 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/bus/st,sys-bus.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: STM32 System Bus
+
+description: |
+ The STM32 System Bus is an internal bus to which some internal peripherals
+ are connected. STM32 System Bus integrates a firewall controlling access to each
+ device. This bus prevents non-accessible devices to be probed.
+
+ To see which peripherals are securable, please check the SoC reference manual.
+
+maintainers:
+ - Gatien Chevallier <gatien.chevallier@foss.st.com>
+
+allOf:
+ - $ref: /schemas/feature-controllers/feature-domain-controller.yaml#
+
+properties:
+ compatible:
+ enum:
+ - st,stm32mp13-sys-bus
+ - st,stm32mp15-sys-bus
+
+ reg:
+ maxItems: 1
+
+ "#address-cells":
+ const: 1
+
+ "#size-cells":
+ const: 1
+
+ '#feature-domain-cells':
+ minimum: 1
+
+ ranges: true
+
+ feature-domain-controller: true
+
+patternProperties:
+ "^.*@[0-9a-f]+$":
+ description: Devices attached to system bus
+ type: object
+ properties:
+ feature-domains:
+ $ref: /schemas/feature-controllers/feature-domain-controller.yaml#/properties/feature-domains
+
+required:
+ - compatible
+ - reg
+ - "#address-cells"
+ - "#size-cells"
+ - feature-domain-controller
+ - '#feature-domain-cells'
+ - ranges
+
+additionalProperties: false
+
+examples:
+ - |
+ // In this example,
+ // - the foo1 device refers to etzpc as his domain controller.
+ // - same goes for foo2.
+ // Access rights are verified before creating devices.
+
+ etzpc: etzpc@5c007000 {
+ compatible = "st,stm32mp15-sys-bus";
+ reg = <0x5c007000 0x400>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ feature-domain-controller;
+ #feature-domain-cells = <1>;
+
+ foo1: foo@1000000 {
+ reg = <0x0 0x1000000>;
+ feature-domains = <&etzpc 0>;
+ };
+
+ foo2: foo@2000000 {
+ reg = <0x0 0x2000000>;
+ feature-domains = <&etzpc 0>;
+ };
+ };
--
2.25.1
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [RFC PATCH v2 2/7] dt-bindings: bus: add STM32 System Bus
@ 2022-12-22 10:04 ` Gatien Chevallier
0 siblings, 0 replies; 18+ messages in thread
From: Gatien Chevallier @ 2022-12-22 10:04 UTC (permalink / raw)
To: alexandre.torgue, robh+dt, Oleksii_Moisieiev, linus.walleij, gregkh
Cc: linux-stm32, linux-arm-kernel, linux-kernel, loic.pallardy,
devicetree, mark.rutland, arnd, gatien.chevallier
Document STM32 System Bus. This bus is intended to control firewall
access for the peripherals connected to it.
Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Loic PALLARDY <loic.pallardy@st.com>
---
Changes in V2:
- Corrected errors highlighted by Rob's robot
- Re-ordered Signed-off-by tags
.../devicetree/bindings/bus/st,sys-bus.yaml | 88 +++++++++++++++++++
1 file changed, 88 insertions(+)
create mode 100644 Documentation/devicetree/bindings/bus/st,sys-bus.yaml
diff --git a/Documentation/devicetree/bindings/bus/st,sys-bus.yaml b/Documentation/devicetree/bindings/bus/st,sys-bus.yaml
new file mode 100644
index 000000000000..d246fbdd6dea
--- /dev/null
+++ b/Documentation/devicetree/bindings/bus/st,sys-bus.yaml
@@ -0,0 +1,88 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/bus/st,sys-bus.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: STM32 System Bus
+
+description: |
+ The STM32 System Bus is an internal bus to which some internal peripherals
+ are connected. STM32 System Bus integrates a firewall controlling access to each
+ device. This bus prevents non-accessible devices to be probed.
+
+ To see which peripherals are securable, please check the SoC reference manual.
+
+maintainers:
+ - Gatien Chevallier <gatien.chevallier@foss.st.com>
+
+allOf:
+ - $ref: /schemas/feature-controllers/feature-domain-controller.yaml#
+
+properties:
+ compatible:
+ enum:
+ - st,stm32mp13-sys-bus
+ - st,stm32mp15-sys-bus
+
+ reg:
+ maxItems: 1
+
+ "#address-cells":
+ const: 1
+
+ "#size-cells":
+ const: 1
+
+ '#feature-domain-cells':
+ minimum: 1
+
+ ranges: true
+
+ feature-domain-controller: true
+
+patternProperties:
+ "^.*@[0-9a-f]+$":
+ description: Devices attached to system bus
+ type: object
+ properties:
+ feature-domains:
+ $ref: /schemas/feature-controllers/feature-domain-controller.yaml#/properties/feature-domains
+
+required:
+ - compatible
+ - reg
+ - "#address-cells"
+ - "#size-cells"
+ - feature-domain-controller
+ - '#feature-domain-cells'
+ - ranges
+
+additionalProperties: false
+
+examples:
+ - |
+ // In this example,
+ // - the foo1 device refers to etzpc as his domain controller.
+ // - same goes for foo2.
+ // Access rights are verified before creating devices.
+
+ etzpc: etzpc@5c007000 {
+ compatible = "st,stm32mp15-sys-bus";
+ reg = <0x5c007000 0x400>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ feature-domain-controller;
+ #feature-domain-cells = <1>;
+
+ foo1: foo@1000000 {
+ reg = <0x0 0x1000000>;
+ feature-domains = <&etzpc 0>;
+ };
+
+ foo2: foo@2000000 {
+ reg = <0x0 0x2000000>;
+ feature-domains = <&etzpc 0>;
+ };
+ };
--
2.25.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [RFC PATCH v2 3/7] dt-bindings: bus: add STM32MP15 ETZPC firewall bus bindings
2022-12-22 10:04 ` Gatien Chevallier
@ 2022-12-22 10:05 ` Gatien Chevallier
-1 siblings, 0 replies; 18+ messages in thread
From: Gatien Chevallier @ 2022-12-22 10:05 UTC (permalink / raw)
To: alexandre.torgue, robh+dt, Oleksii_Moisieiev, linus.walleij, gregkh
Cc: linux-stm32, linux-arm-kernel, linux-kernel, loic.pallardy,
devicetree, mark.rutland, arnd, gatien.chevallier
Adds the list of peripherals IDs under firewall bus on STM32MP15.
Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
---
include/dt-bindings/bus/stm32mp15_sys_bus.h | 98 +++++++++++++++++++++
1 file changed, 98 insertions(+)
create mode 100644 include/dt-bindings/bus/stm32mp15_sys_bus.h
diff --git a/include/dt-bindings/bus/stm32mp15_sys_bus.h b/include/dt-bindings/bus/stm32mp15_sys_bus.h
new file mode 100644
index 000000000000..97eacc7b5f16
--- /dev/null
+++ b/include/dt-bindings/bus/stm32mp15_sys_bus.h
@@ -0,0 +1,98 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (C) STMicroelectronics 2022 - All Rights Reserved
+ */
+#ifndef _DT_BINDINGS_BUS_STM32MP15_SYS_BUS_H
+#define _DT_BINDINGS_BUS_STM32MP15_SYS_BUS_H
+
+/* ETZPC IDs */
+#define STM32MP1_ETZPC_STGENC_ID 0
+#define STM32MP1_ETZPC_BKPSRAM_ID 1
+#define STM32MP1_ETZPC_IWDG1_ID 2
+#define STM32MP1_ETZPC_USART1_ID 3
+#define STM32MP1_ETZPC_SPI6_ID 4
+#define STM32MP1_ETZPC_I2C4_ID 5
+/* ID 6 reserved */
+#define STM32MP1_ETZPC_RNG1_ID 7
+#define STM32MP1_ETZPC_HASH1_ID 8
+#define STM32MP1_ETZPC_CRYP1_ID 9
+#define STM32MP1_ETZPC_DDRCTRL_ID 10
+#define STM32MP1_ETZPC_DDRPHYC_ID 11
+#define STM32MP1_ETZPC_I2C6_ID 12
+/* IDs 13-15 reserved */
+#define STM32MP1_ETZPC_TIM2_ID 16
+#define STM32MP1_ETZPC_TIM3_ID 17
+#define STM32MP1_ETZPC_TIM4_ID 18
+#define STM32MP1_ETZPC_TIM5_ID 19
+#define STM32MP1_ETZPC_TIM6_ID 20
+#define STM32MP1_ETZPC_TIM7_ID 21
+#define STM32MP1_ETZPC_TIM12_ID 22
+#define STM32MP1_ETZPC_TIM13_ID 23
+#define STM32MP1_ETZPC_TIM14_ID 24
+#define STM32MP1_ETZPC_LPTIM1_ID 25
+#define STM32MP1_ETZPC_WWDG1_ID 26
+#define STM32MP1_ETZPC_SPI2_ID 27
+#define STM32MP1_ETZPC_SPI3_ID 28
+#define STM32MP1_ETZPC_SPDIFRX_ID 29
+#define STM32MP1_ETZPC_USART2_ID 30
+#define STM32MP1_ETZPC_USART3_ID 31
+#define STM32MP1_ETZPC_UART4_ID 32
+#define STM32MP1_ETZPC_UART5_ID 33
+#define STM32MP1_ETZPC_I2C1_ID 34
+#define STM32MP1_ETZPC_I2C2_ID 35
+#define STM32MP1_ETZPC_I2C3_ID 36
+#define STM32MP1_ETZPC_I2C5_ID 37
+#define STM32MP1_ETZPC_CEC_ID 38
+#define STM32MP1_ETZPC_DAC_ID 39
+#define STM32MP1_ETZPC_UART7_ID 40
+#define STM32MP1_ETZPC_UART8_ID 41
+/* IDs 42-43 reserved */
+#define STM32MP1_ETZPC_MDIOS_ID 44
+/* IDs 45-47 reserved */
+#define STM32MP1_ETZPC_TIM1_ID 48
+#define STM32MP1_ETZPC_TIM8_ID 49
+/* ID 50 reserved */
+#define STM32MP1_ETZPC_USART6_ID 51
+#define STM32MP1_ETZPC_SPI1_ID 52
+#define STM32MP1_ETZPC_SPI4_ID 53
+#define STM32MP1_ETZPC_TIM15_ID 54
+#define STM32MP1_ETZPC_TIM16_ID 55
+#define STM32MP1_ETZPC_TIM17_ID 56
+#define STM32MP1_ETZPC_SPI5_ID 57
+#define STM32MP1_ETZPC_SAI1_ID 58
+#define STM32MP1_ETZPC_SAI2_ID 59
+#define STM32MP1_ETZPC_SAI3_ID 60
+#define STM32MP1_ETZPC_DFSDM_ID 61
+#define STM32MP1_ETZPC_TT_FDCAN_ID 62
+/* IDs 63 reserved */
+#define STM32MP1_ETZPC_LPTIM2_ID 64
+#define STM32MP1_ETZPC_LPTIM3_ID 65
+#define STM32MP1_ETZPC_LPTIM4_ID 66
+#define STM32MP1_ETZPC_LPTIM5_ID 67
+#define STM32MP1_ETZPC_SAI4_ID 68
+#define STM32MP1_ETZPC_VREFBUF_ID 69
+#define STM32MP1_ETZPC_DCMI_ID 70
+#define STM32MP1_ETZPC_CRC2_ID 71
+#define STM32MP1_ETZPC_ADC_ID 72
+#define STM32MP1_ETZPC_HASH2_ID 73
+#define STM32MP1_ETZPC_RNG2_ID 74
+#define STM32MP1_ETZPC_CRYP2_ID 75
+/* IDs 76-79 reserved */
+#define STM32MP1_ETZPC_SRAM1_ID 80
+#define STM32MP1_ETZPC_SRAM2_ID 81
+#define STM32MP1_ETZPC_SRAM3_ID 82
+#define STM32MP1_ETZPC_SRAM4_ID 83
+#define STM32MP1_ETZPC_RETRAM_ID 84
+#define STM32MP1_ETZPC_OTG_ID 85
+#define STM32MP1_ETZPC_SDMMC3_ID 86
+#define STM32MP1_ETZPC_DLYBSD3_ID 87
+#define STM32MP1_ETZPC_DMA1_ID 88
+#define STM32MP1_ETZPC_DMA2_ID 89
+#define STM32MP1_ETZPC_DMAMUX_ID 90
+#define STM32MP1_ETZPC_FMC_ID 91
+#define STM32MP1_ETZPC_QSPI_ID 92
+#define STM32MP1_ETZPC_DLYBQ_ID 93
+#define STM32MP1_ETZPC_ETH_ID 94
+/* ID 95 reserved */
+
+#endif /* _DT_BINDINGS_BUS_STM32MP15_SYS_BUS_H */
--
2.25.1
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [RFC PATCH v2 3/7] dt-bindings: bus: add STM32MP15 ETZPC firewall bus bindings
@ 2022-12-22 10:05 ` Gatien Chevallier
0 siblings, 0 replies; 18+ messages in thread
From: Gatien Chevallier @ 2022-12-22 10:05 UTC (permalink / raw)
To: alexandre.torgue, robh+dt, Oleksii_Moisieiev, linus.walleij, gregkh
Cc: linux-stm32, linux-arm-kernel, linux-kernel, loic.pallardy,
devicetree, mark.rutland, arnd, gatien.chevallier
Adds the list of peripherals IDs under firewall bus on STM32MP15.
Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
---
include/dt-bindings/bus/stm32mp15_sys_bus.h | 98 +++++++++++++++++++++
1 file changed, 98 insertions(+)
create mode 100644 include/dt-bindings/bus/stm32mp15_sys_bus.h
diff --git a/include/dt-bindings/bus/stm32mp15_sys_bus.h b/include/dt-bindings/bus/stm32mp15_sys_bus.h
new file mode 100644
index 000000000000..97eacc7b5f16
--- /dev/null
+++ b/include/dt-bindings/bus/stm32mp15_sys_bus.h
@@ -0,0 +1,98 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (C) STMicroelectronics 2022 - All Rights Reserved
+ */
+#ifndef _DT_BINDINGS_BUS_STM32MP15_SYS_BUS_H
+#define _DT_BINDINGS_BUS_STM32MP15_SYS_BUS_H
+
+/* ETZPC IDs */
+#define STM32MP1_ETZPC_STGENC_ID 0
+#define STM32MP1_ETZPC_BKPSRAM_ID 1
+#define STM32MP1_ETZPC_IWDG1_ID 2
+#define STM32MP1_ETZPC_USART1_ID 3
+#define STM32MP1_ETZPC_SPI6_ID 4
+#define STM32MP1_ETZPC_I2C4_ID 5
+/* ID 6 reserved */
+#define STM32MP1_ETZPC_RNG1_ID 7
+#define STM32MP1_ETZPC_HASH1_ID 8
+#define STM32MP1_ETZPC_CRYP1_ID 9
+#define STM32MP1_ETZPC_DDRCTRL_ID 10
+#define STM32MP1_ETZPC_DDRPHYC_ID 11
+#define STM32MP1_ETZPC_I2C6_ID 12
+/* IDs 13-15 reserved */
+#define STM32MP1_ETZPC_TIM2_ID 16
+#define STM32MP1_ETZPC_TIM3_ID 17
+#define STM32MP1_ETZPC_TIM4_ID 18
+#define STM32MP1_ETZPC_TIM5_ID 19
+#define STM32MP1_ETZPC_TIM6_ID 20
+#define STM32MP1_ETZPC_TIM7_ID 21
+#define STM32MP1_ETZPC_TIM12_ID 22
+#define STM32MP1_ETZPC_TIM13_ID 23
+#define STM32MP1_ETZPC_TIM14_ID 24
+#define STM32MP1_ETZPC_LPTIM1_ID 25
+#define STM32MP1_ETZPC_WWDG1_ID 26
+#define STM32MP1_ETZPC_SPI2_ID 27
+#define STM32MP1_ETZPC_SPI3_ID 28
+#define STM32MP1_ETZPC_SPDIFRX_ID 29
+#define STM32MP1_ETZPC_USART2_ID 30
+#define STM32MP1_ETZPC_USART3_ID 31
+#define STM32MP1_ETZPC_UART4_ID 32
+#define STM32MP1_ETZPC_UART5_ID 33
+#define STM32MP1_ETZPC_I2C1_ID 34
+#define STM32MP1_ETZPC_I2C2_ID 35
+#define STM32MP1_ETZPC_I2C3_ID 36
+#define STM32MP1_ETZPC_I2C5_ID 37
+#define STM32MP1_ETZPC_CEC_ID 38
+#define STM32MP1_ETZPC_DAC_ID 39
+#define STM32MP1_ETZPC_UART7_ID 40
+#define STM32MP1_ETZPC_UART8_ID 41
+/* IDs 42-43 reserved */
+#define STM32MP1_ETZPC_MDIOS_ID 44
+/* IDs 45-47 reserved */
+#define STM32MP1_ETZPC_TIM1_ID 48
+#define STM32MP1_ETZPC_TIM8_ID 49
+/* ID 50 reserved */
+#define STM32MP1_ETZPC_USART6_ID 51
+#define STM32MP1_ETZPC_SPI1_ID 52
+#define STM32MP1_ETZPC_SPI4_ID 53
+#define STM32MP1_ETZPC_TIM15_ID 54
+#define STM32MP1_ETZPC_TIM16_ID 55
+#define STM32MP1_ETZPC_TIM17_ID 56
+#define STM32MP1_ETZPC_SPI5_ID 57
+#define STM32MP1_ETZPC_SAI1_ID 58
+#define STM32MP1_ETZPC_SAI2_ID 59
+#define STM32MP1_ETZPC_SAI3_ID 60
+#define STM32MP1_ETZPC_DFSDM_ID 61
+#define STM32MP1_ETZPC_TT_FDCAN_ID 62
+/* IDs 63 reserved */
+#define STM32MP1_ETZPC_LPTIM2_ID 64
+#define STM32MP1_ETZPC_LPTIM3_ID 65
+#define STM32MP1_ETZPC_LPTIM4_ID 66
+#define STM32MP1_ETZPC_LPTIM5_ID 67
+#define STM32MP1_ETZPC_SAI4_ID 68
+#define STM32MP1_ETZPC_VREFBUF_ID 69
+#define STM32MP1_ETZPC_DCMI_ID 70
+#define STM32MP1_ETZPC_CRC2_ID 71
+#define STM32MP1_ETZPC_ADC_ID 72
+#define STM32MP1_ETZPC_HASH2_ID 73
+#define STM32MP1_ETZPC_RNG2_ID 74
+#define STM32MP1_ETZPC_CRYP2_ID 75
+/* IDs 76-79 reserved */
+#define STM32MP1_ETZPC_SRAM1_ID 80
+#define STM32MP1_ETZPC_SRAM2_ID 81
+#define STM32MP1_ETZPC_SRAM3_ID 82
+#define STM32MP1_ETZPC_SRAM4_ID 83
+#define STM32MP1_ETZPC_RETRAM_ID 84
+#define STM32MP1_ETZPC_OTG_ID 85
+#define STM32MP1_ETZPC_SDMMC3_ID 86
+#define STM32MP1_ETZPC_DLYBSD3_ID 87
+#define STM32MP1_ETZPC_DMA1_ID 88
+#define STM32MP1_ETZPC_DMA2_ID 89
+#define STM32MP1_ETZPC_DMAMUX_ID 90
+#define STM32MP1_ETZPC_FMC_ID 91
+#define STM32MP1_ETZPC_QSPI_ID 92
+#define STM32MP1_ETZPC_DLYBQ_ID 93
+#define STM32MP1_ETZPC_ETH_ID 94
+/* ID 95 reserved */
+
+#endif /* _DT_BINDINGS_BUS_STM32MP15_SYS_BUS_H */
--
2.25.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [RFC PATCH v2 4/7] dt-bindings: bus: add STM32MP13 ETZPC firewall bus bindings
2022-12-22 10:04 ` Gatien Chevallier
@ 2022-12-22 10:05 ` Gatien Chevallier
-1 siblings, 0 replies; 18+ messages in thread
From: Gatien Chevallier @ 2022-12-22 10:05 UTC (permalink / raw)
To: alexandre.torgue, robh+dt, Oleksii_Moisieiev, linus.walleij, gregkh
Cc: linux-stm32, linux-arm-kernel, linux-kernel, loic.pallardy,
devicetree, mark.rutland, arnd, gatien.chevallier
Adds the list of peripherals IDs under firewall bus on STM32MP13.
Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
---
include/dt-bindings/bus/stm32mp13_sys_bus.h | 60 +++++++++++++++++++++
1 file changed, 60 insertions(+)
create mode 100644 include/dt-bindings/bus/stm32mp13_sys_bus.h
diff --git a/include/dt-bindings/bus/stm32mp13_sys_bus.h b/include/dt-bindings/bus/stm32mp13_sys_bus.h
new file mode 100644
index 000000000000..1160de87bc4a
--- /dev/null
+++ b/include/dt-bindings/bus/stm32mp13_sys_bus.h
@@ -0,0 +1,60 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (C) STMicroelectronics 2022 - All Rights Reserved
+ */
+#ifndef _DT_BINDINGS_BUS_STM32MP13_SYS_BUS_H
+#define _DT_BINDINGS_BUS_STM32MP13_SYS_BUS_H
+
+/* ETZPC IDs */
+#define STM32MP1_ETZPC_VREFBUF_ID 0
+#define STM32MP1_ETZPC_LPTIM2_ID 1
+#define STM32MP1_ETZPC_LPTIM3_ID 2
+#define STM32MP1_ETZPC_LTDC_ID 3
+#define STM32MP1_ETZPC_DCMIPP_ID 4
+#define STM32MP1_ETZPC_USBPHYCTRL_ID 5
+#define STM32MP1_ETZPC_DDRCTRLPHY_ID 6
+/* IDs 7-11 reserved */
+#define STM32MP1_ETZPC_IWDG1_ID 12
+#define STM32MP1_ETZPC_STGENC_ID 13
+/* IDs 14-15 reserved */
+#define STM32MP1_ETZPC_USART1_ID 16
+#define STM32MP1_ETZPC_USART2_ID 17
+#define STM32MP1_ETZPC_SPI4_ID 18
+#define STM32MP1_ETZPC_SPI5_ID 19
+#define STM32MP1_ETZPC_I2C3_ID 20
+#define STM32MP1_ETZPC_I2C4_ID 21
+#define STM32MP1_ETZPC_I2C5_ID 22
+#define STM32MP1_ETZPC_TIM12_ID 23
+#define STM32MP1_ETZPC_TIM13_ID 24
+#define STM32MP1_ETZPC_TIM14_ID 25
+#define STM32MP1_ETZPC_TIM15_ID 26
+#define STM32MP1_ETZPC_TIM16_ID 27
+#define STM32MP1_ETZPC_TIM17_ID 28
+/* IDs 29-31 reserved */
+#define STM32MP1_ETZPC_ADC1_ID 32
+#define STM32MP1_ETZPC_ADC2_ID 33
+#define STM32MP1_ETZPC_OTG_ID 34
+/* IDs 35-39 reserved */
+#define STM32MP1_ETZPC_TSC_ID 37
+#define STM32MP1_ETZPC_RNG_ID 40
+#define STM32MP1_ETZPC_HASH_ID 41
+#define STM32MP1_ETZPC_CRYP_ID 42
+#define STM32MP1_ETZPC_SAES_ID 43
+#define STM32MP1_ETZPC_PKA_ID 44
+#define STM32MP1_ETZPC_BKPSRAM_ID 45
+/* IDs 46-47 reserved */
+#define STM32MP1_ETZPC_ETH1_ID 48
+#define STM32MP1_ETZPC_ETH2_ID 49
+#define STM32MP1_ETZPC_SDMMC1_ID 50
+#define STM32MP1_ETZPC_SDMMC2_ID 51
+/* ID 52 reserved */
+#define STM32MP1_ETZPC_MCE_ID 53
+#define STM32MP1_ETZPC_FMC_ID 54
+#define STM32MP1_ETZPC_QSPI_ID 55
+/* IDs 56-59 reserved */
+#define STM32MP1_ETZPC_SRAM1_ID 60
+#define STM32MP1_ETZPC_SRAM2_ID 61
+#define STM32MP1_ETZPC_SRAM3_ID 62
+/* ID 63 reserved */
+
+#endif /* _DT_BINDINGS_BUS_STM32MP13_SYS_BUS_H */
--
2.25.1
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [RFC PATCH v2 4/7] dt-bindings: bus: add STM32MP13 ETZPC firewall bus bindings
@ 2022-12-22 10:05 ` Gatien Chevallier
0 siblings, 0 replies; 18+ messages in thread
From: Gatien Chevallier @ 2022-12-22 10:05 UTC (permalink / raw)
To: alexandre.torgue, robh+dt, Oleksii_Moisieiev, linus.walleij, gregkh
Cc: linux-stm32, linux-arm-kernel, linux-kernel, loic.pallardy,
devicetree, mark.rutland, arnd, gatien.chevallier
Adds the list of peripherals IDs under firewall bus on STM32MP13.
Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
---
include/dt-bindings/bus/stm32mp13_sys_bus.h | 60 +++++++++++++++++++++
1 file changed, 60 insertions(+)
create mode 100644 include/dt-bindings/bus/stm32mp13_sys_bus.h
diff --git a/include/dt-bindings/bus/stm32mp13_sys_bus.h b/include/dt-bindings/bus/stm32mp13_sys_bus.h
new file mode 100644
index 000000000000..1160de87bc4a
--- /dev/null
+++ b/include/dt-bindings/bus/stm32mp13_sys_bus.h
@@ -0,0 +1,60 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (C) STMicroelectronics 2022 - All Rights Reserved
+ */
+#ifndef _DT_BINDINGS_BUS_STM32MP13_SYS_BUS_H
+#define _DT_BINDINGS_BUS_STM32MP13_SYS_BUS_H
+
+/* ETZPC IDs */
+#define STM32MP1_ETZPC_VREFBUF_ID 0
+#define STM32MP1_ETZPC_LPTIM2_ID 1
+#define STM32MP1_ETZPC_LPTIM3_ID 2
+#define STM32MP1_ETZPC_LTDC_ID 3
+#define STM32MP1_ETZPC_DCMIPP_ID 4
+#define STM32MP1_ETZPC_USBPHYCTRL_ID 5
+#define STM32MP1_ETZPC_DDRCTRLPHY_ID 6
+/* IDs 7-11 reserved */
+#define STM32MP1_ETZPC_IWDG1_ID 12
+#define STM32MP1_ETZPC_STGENC_ID 13
+/* IDs 14-15 reserved */
+#define STM32MP1_ETZPC_USART1_ID 16
+#define STM32MP1_ETZPC_USART2_ID 17
+#define STM32MP1_ETZPC_SPI4_ID 18
+#define STM32MP1_ETZPC_SPI5_ID 19
+#define STM32MP1_ETZPC_I2C3_ID 20
+#define STM32MP1_ETZPC_I2C4_ID 21
+#define STM32MP1_ETZPC_I2C5_ID 22
+#define STM32MP1_ETZPC_TIM12_ID 23
+#define STM32MP1_ETZPC_TIM13_ID 24
+#define STM32MP1_ETZPC_TIM14_ID 25
+#define STM32MP1_ETZPC_TIM15_ID 26
+#define STM32MP1_ETZPC_TIM16_ID 27
+#define STM32MP1_ETZPC_TIM17_ID 28
+/* IDs 29-31 reserved */
+#define STM32MP1_ETZPC_ADC1_ID 32
+#define STM32MP1_ETZPC_ADC2_ID 33
+#define STM32MP1_ETZPC_OTG_ID 34
+/* IDs 35-39 reserved */
+#define STM32MP1_ETZPC_TSC_ID 37
+#define STM32MP1_ETZPC_RNG_ID 40
+#define STM32MP1_ETZPC_HASH_ID 41
+#define STM32MP1_ETZPC_CRYP_ID 42
+#define STM32MP1_ETZPC_SAES_ID 43
+#define STM32MP1_ETZPC_PKA_ID 44
+#define STM32MP1_ETZPC_BKPSRAM_ID 45
+/* IDs 46-47 reserved */
+#define STM32MP1_ETZPC_ETH1_ID 48
+#define STM32MP1_ETZPC_ETH2_ID 49
+#define STM32MP1_ETZPC_SDMMC1_ID 50
+#define STM32MP1_ETZPC_SDMMC2_ID 51
+/* ID 52 reserved */
+#define STM32MP1_ETZPC_MCE_ID 53
+#define STM32MP1_ETZPC_FMC_ID 54
+#define STM32MP1_ETZPC_QSPI_ID 55
+/* IDs 56-59 reserved */
+#define STM32MP1_ETZPC_SRAM1_ID 60
+#define STM32MP1_ETZPC_SRAM2_ID 61
+#define STM32MP1_ETZPC_SRAM3_ID 62
+/* ID 63 reserved */
+
+#endif /* _DT_BINDINGS_BUS_STM32MP13_SYS_BUS_H */
--
2.25.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 18+ messages in thread
* Re: [RFC PATCH v2 0/7] Introduce STM32 system bus
2022-12-22 10:04 ` Gatien Chevallier
@ 2022-12-22 16:39 ` Greg KH
-1 siblings, 0 replies; 18+ messages in thread
From: Greg KH @ 2022-12-22 16:39 UTC (permalink / raw)
To: Gatien Chevallier
Cc: alexandre.torgue, robh+dt, Oleksii_Moisieiev, linus.walleij,
linux-stm32, linux-arm-kernel, linux-kernel, loic.pallardy,
devicetree, mark.rutland, arnd
On Thu, Dec 22, 2022 at 11:04:57AM +0100, Gatien Chevallier wrote:
> Document STM32 System Bus. This bus is intended to control firewall
> access for the peripherals connected to it.
Why is this an "RFC"? That usually means "I have more work to do on it,
but I'll send it out now anyway". What work is left?
And for most code, I know I don't review "RFC" changes as there are too
many "real" patches being submitted where people think their code is
ready to be merged. Other reviewers might think otherwise, but be aware
of this...
thanks,
greg k-h
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [RFC PATCH v2 0/7] Introduce STM32 system bus
@ 2022-12-22 16:39 ` Greg KH
0 siblings, 0 replies; 18+ messages in thread
From: Greg KH @ 2022-12-22 16:39 UTC (permalink / raw)
To: Gatien Chevallier
Cc: alexandre.torgue, robh+dt, Oleksii_Moisieiev, linus.walleij,
linux-stm32, linux-arm-kernel, linux-kernel, loic.pallardy,
devicetree, mark.rutland, arnd
On Thu, Dec 22, 2022 at 11:04:57AM +0100, Gatien Chevallier wrote:
> Document STM32 System Bus. This bus is intended to control firewall
> access for the peripherals connected to it.
Why is this an "RFC"? That usually means "I have more work to do on it,
but I'll send it out now anyway". What work is left?
And for most code, I know I don't review "RFC" changes as there are too
many "real" patches being submitted where people think their code is
ready to be merged. Other reviewers might think otherwise, but be aware
of this...
thanks,
greg k-h
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [RFC PATCH v2 1/7] dt-bindings: Document common device controller bindings
2022-12-22 10:04 ` Gatien Chevallier
@ 2022-12-23 10:08 ` Krzysztof Kozlowski
-1 siblings, 0 replies; 18+ messages in thread
From: Krzysztof Kozlowski @ 2022-12-23 10:08 UTC (permalink / raw)
To: Gatien Chevallier, alexandre.torgue, robh+dt, Oleksii_Moisieiev,
linus.walleij, gregkh
Cc: linux-stm32, linux-arm-kernel, linux-kernel, loic.pallardy,
devicetree, mark.rutland, arnd
On 22/12/2022 11:04, Gatien Chevallier wrote:
> From: Oleksii Moisieiev <Oleksii_Moisieiev@epam.com>
>
> Introducing of the common device controller bindings for the controller
> provider and consumer devices. Those bindings are intended to allow
> divided system on chip into muliple domains, that can be used to
> configure hardware permissions.
>
> Signed-off-by: Oleksii Moisieiev <oleksii_moisieiev@epam.com>
It seems you sent it after my feedback but I do not see my feedback
implemented here (missing SoB, this patch should not be here, not cc-ing
all maintainers, etc.). If you sent it before reading feedback, please
sent a v3 with the feedback implemented.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [RFC PATCH v2 1/7] dt-bindings: Document common device controller bindings
@ 2022-12-23 10:08 ` Krzysztof Kozlowski
0 siblings, 0 replies; 18+ messages in thread
From: Krzysztof Kozlowski @ 2022-12-23 10:08 UTC (permalink / raw)
To: Gatien Chevallier, alexandre.torgue, robh+dt, Oleksii_Moisieiev,
linus.walleij, gregkh
Cc: linux-stm32, linux-arm-kernel, linux-kernel, loic.pallardy,
devicetree, mark.rutland, arnd
On 22/12/2022 11:04, Gatien Chevallier wrote:
> From: Oleksii Moisieiev <Oleksii_Moisieiev@epam.com>
>
> Introducing of the common device controller bindings for the controller
> provider and consumer devices. Those bindings are intended to allow
> divided system on chip into muliple domains, that can be used to
> configure hardware permissions.
>
> Signed-off-by: Oleksii Moisieiev <oleksii_moisieiev@epam.com>
It seems you sent it after my feedback but I do not see my feedback
implemented here (missing SoB, this patch should not be here, not cc-ing
all maintainers, etc.). If you sent it before reading feedback, please
sent a v3 with the feedback implemented.
Best regards,
Krzysztof
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [RFC PATCH v2 0/7] Introduce STM32 system bus
2022-12-22 16:39 ` Greg KH
@ 2023-01-03 9:45 ` Gatien CHEVALLIER
-1 siblings, 0 replies; 18+ messages in thread
From: Gatien CHEVALLIER @ 2023-01-03 9:45 UTC (permalink / raw)
To: Greg KH
Cc: alexandre.torgue, robh+dt, Oleksii_Moisieiev, linus.walleij,
linux-stm32, linux-arm-kernel, linux-kernel, loic.pallardy,
devicetree, mark.rutland, arnd
Hello Greg,
I've put the "RFC" tag on the the patch set as it is based on bindings
that are currently under review. It has been submitted with the idea to
support the bindings proposed by Oleksii. Apart from this and the
comments made by Krzysztof, there is indeed no more "work" planned on
this change.
Should the "RFC" tag be omitted for the next version?
Best regards,
Gatien
On 12/22/22 17:39, Greg KH wrote:
> On Thu, Dec 22, 2022 at 11:04:57AM +0100, Gatien Chevallier wrote:
>> Document STM32 System Bus. This bus is intended to control firewall
>> access for the peripherals connected to it.
>
> Why is this an "RFC"? That usually means "I have more work to do on it,
> but I'll send it out now anyway". What work is left?
>
> And for most code, I know I don't review "RFC" changes as there are too
> many "real" patches being submitted where people think their code is
> ready to be merged. Other reviewers might think otherwise, but be aware
> of this...
>
> thanks,
>
> greg k-h
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [RFC PATCH v2 0/7] Introduce STM32 system bus
@ 2023-01-03 9:45 ` Gatien CHEVALLIER
0 siblings, 0 replies; 18+ messages in thread
From: Gatien CHEVALLIER @ 2023-01-03 9:45 UTC (permalink / raw)
To: Greg KH
Cc: alexandre.torgue, robh+dt, Oleksii_Moisieiev, linus.walleij,
linux-stm32, linux-arm-kernel, linux-kernel, loic.pallardy,
devicetree, mark.rutland, arnd
Hello Greg,
I've put the "RFC" tag on the the patch set as it is based on bindings
that are currently under review. It has been submitted with the idea to
support the bindings proposed by Oleksii. Apart from this and the
comments made by Krzysztof, there is indeed no more "work" planned on
this change.
Should the "RFC" tag be omitted for the next version?
Best regards,
Gatien
On 12/22/22 17:39, Greg KH wrote:
> On Thu, Dec 22, 2022 at 11:04:57AM +0100, Gatien Chevallier wrote:
>> Document STM32 System Bus. This bus is intended to control firewall
>> access for the peripherals connected to it.
>
> Why is this an "RFC"? That usually means "I have more work to do on it,
> but I'll send it out now anyway". What work is left?
>
> And for most code, I know I don't review "RFC" changes as there are too
> many "real" patches being submitted where people think their code is
> ready to be merged. Other reviewers might think otherwise, but be aware
> of this...
>
> thanks,
>
> greg k-h
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [RFC PATCH v2 0/7] Introduce STM32 system bus
2023-01-03 9:45 ` Gatien CHEVALLIER
@ 2023-01-04 6:10 ` Greg KH
-1 siblings, 0 replies; 18+ messages in thread
From: Greg KH @ 2023-01-04 6:10 UTC (permalink / raw)
To: Gatien CHEVALLIER
Cc: alexandre.torgue, robh+dt, Oleksii_Moisieiev, linus.walleij,
linux-stm32, linux-arm-kernel, linux-kernel, loic.pallardy,
devicetree, mark.rutland, arnd
On Tue, Jan 03, 2023 at 10:45:15AM +0100, Gatien CHEVALLIER wrote:
> Hello Greg,
>
> I've put the "RFC" tag on the the patch set as it is based on bindings that
> are currently under review. It has been submitted with the idea to support
> the bindings proposed by Oleksii. Apart from this and the comments made by
> Krzysztof, there is indeed no more "work" planned on this change.
>
> Should the "RFC" tag be omitted for the next version?
If you feel it is ready to be merged, yes, then please remove it,
otherwise it's obviously not ready and will not be merged :)
thanks,
greg k-h
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [RFC PATCH v2 0/7] Introduce STM32 system bus
@ 2023-01-04 6:10 ` Greg KH
0 siblings, 0 replies; 18+ messages in thread
From: Greg KH @ 2023-01-04 6:10 UTC (permalink / raw)
To: Gatien CHEVALLIER
Cc: alexandre.torgue, robh+dt, Oleksii_Moisieiev, linus.walleij,
linux-stm32, linux-arm-kernel, linux-kernel, loic.pallardy,
devicetree, mark.rutland, arnd
On Tue, Jan 03, 2023 at 10:45:15AM +0100, Gatien CHEVALLIER wrote:
> Hello Greg,
>
> I've put the "RFC" tag on the the patch set as it is based on bindings that
> are currently under review. It has been submitted with the idea to support
> the bindings proposed by Oleksii. Apart from this and the comments made by
> Krzysztof, there is indeed no more "work" planned on this change.
>
> Should the "RFC" tag be omitted for the next version?
If you feel it is ready to be merged, yes, then please remove it,
otherwise it's obviously not ready and will not be merged :)
thanks,
greg k-h
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 18+ messages in thread
end of thread, other threads:[~2023-01-04 6:12 UTC | newest]
Thread overview: 18+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-12-22 10:04 [RFC PATCH v2 0/7] Introduce STM32 system bus Gatien Chevallier
2022-12-22 10:04 ` Gatien Chevallier
2022-12-22 10:04 ` [RFC PATCH v2 1/7] dt-bindings: Document common device controller bindings Gatien Chevallier
2022-12-22 10:04 ` Gatien Chevallier
2022-12-23 10:08 ` Krzysztof Kozlowski
2022-12-23 10:08 ` Krzysztof Kozlowski
2022-12-22 10:04 ` [RFC PATCH v2 2/7] dt-bindings: bus: add STM32 System Bus Gatien Chevallier
2022-12-22 10:04 ` Gatien Chevallier
2022-12-22 10:05 ` [RFC PATCH v2 3/7] dt-bindings: bus: add STM32MP15 ETZPC firewall bus bindings Gatien Chevallier
2022-12-22 10:05 ` Gatien Chevallier
2022-12-22 10:05 ` [RFC PATCH v2 4/7] dt-bindings: bus: add STM32MP13 " Gatien Chevallier
2022-12-22 10:05 ` Gatien Chevallier
2022-12-22 16:39 ` [RFC PATCH v2 0/7] Introduce STM32 system bus Greg KH
2022-12-22 16:39 ` Greg KH
2023-01-03 9:45 ` Gatien CHEVALLIER
2023-01-03 9:45 ` Gatien CHEVALLIER
2023-01-04 6:10 ` Greg KH
2023-01-04 6:10 ` Greg KH
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.