From: Atish Patra <Atish.Patra@wdc.com> To: Paul Walmsley <paul.walmsley@sifive.com>, Anup Patel <Anup.Patel@wdc.com> Cc: "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>, Albert Ou <aou@eecs.berkeley.edu>, Alexios Zavras <alexios.zavras@intel.com>, Allison Randal <allison@lohutok.net>, Daniel Lezcano <daniel.lezcano@linaro.org>, "devicetree@vger.kernel.org" <devicetree@vger.kernel.org>, Enrico Weigelt <info@metux.net>, Greg Kroah-Hartman <gregkh@linuxfoundation.org>, Johan Hovold <johan@kernel.org>, "linux-riscv@lists.infradead.org" <linux-riscv@lists.infradead.org>, Mark Rutland <mark.rutland@arm.com>, Palmer Dabbelt <palmer@sifive.com>, Rob Herring <robh+dt@kernel.org>, Thomas Gleixner <tglx@linutronix.de> Subject: Re: [PATCH v2 2/5] RISC-V: Add riscv_isa reprensenting ISA features common across CPUs Date: Wed, 31 Jul 2019 06:27:53 +0000 [thread overview] Message-ID: <99D22117-E146-44BE-93B5-5D25367931C7@wdc.com> (raw) In-Reply-To: <alpine.DEB.2.21.9999.1907302117420.15340@viisi.sifive.com> On 7/30/19, 9:23 PM, "Paul Walmsley" <paul.walmsley@sifive.com> wrote: On Tue, 30 Jul 2019, Atish Patra wrote: > From: Anup Patel <anup.patel@wdc.com> > > This patch adds riscv_isa integer to represent ISA features common > across all CPUs. The riscv_isa is not same as elf_hwcap because > elf_hwcap will only have ISA features relevant for user-space apps > whereas riscv_isa will have ISA features relevant to both kernel > and user-space apps. > > One of the use case is KVM hypervisor where riscv_isa will be used > to do following operations: > > 1. Check whether hypervisor extension is available > 2. Find ISA features that need to be virtualized (e.g. floating > point support, vector extension, etc.) > > Signed-off-by: Anup Patel <anup.patel@wdc.com> > Signed-off-by: Atish Patra <atish.patra@wdc.com> > --- > arch/riscv/include/asm/hwcap.h | 25 +++++++++++++++++++++ > arch/riscv/kernel/cpufeature.c | 41 +++++++++++++++++++++++++++++++--- > 2 files changed, 63 insertions(+), 3 deletions(-) > > diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h > index 7ecb7c6a57b1..e069f60ad5d2 100644 > --- a/arch/riscv/include/asm/hwcap.h > +++ b/arch/riscv/include/asm/hwcap.h > @@ -22,5 +22,30 @@ enum { > }; > > extern unsigned long elf_hwcap; > + > +#define RISCV_ISA_EXT_A (1UL << ('A' - 'A')) Are these uppercase variants still needed if we define the ISA string to be all lowercase, per our recent discussion? Argh. Sorry. We have been carrying this patch so long that I completely forgot about the case sensitive usage here. > +#define RISCV_ISA_EXT_a RISCV_ISA_EXT_A > +#define RISCV_ISA_EXT_C (1UL << ('C' - 'A')) > +#define RISCV_ISA_EXT_c RISCV_ISA_EXT_C > +#define RISCV_ISA_EXT_D (1UL << ('D' - 'A')) > +#define RISCV_ISA_EXT_d RISCV_ISA_EXT_D > +#define RISCV_ISA_EXT_F (1UL << ('F' - 'A')) > +#define RISCV_ISA_EXT_f RISCV_ISA_EXT_F > +#define RISCV_ISA_EXT_H (1UL << ('H' - 'A')) > +#define RISCV_ISA_EXT_h RISCV_ISA_EXT_H > +#define RISCV_ISA_EXT_I (1UL << ('I' - 'A')) > +#define RISCV_ISA_EXT_i RISCV_ISA_EXT_I > +#define RISCV_ISA_EXT_M (1UL << ('M' - 'A')) > +#define RISCV_ISA_EXT_m RISCV_ISA_EXT_M > +#define RISCV_ISA_EXT_S (1UL << ('S' - 'A')) > +#define RISCV_ISA_EXT_s RISCV_ISA_EXT_S > +#define RISCV_ISA_EXT_U (1UL << ('U' - 'A')) > +#define RISCV_ISA_EXT_u RISCV_ISA_EXT_U > + > +extern unsigned long riscv_isa; > + > +#define riscv_isa_extension_available(ext_char) \ > + (riscv_isa & RISCV_ISA_EXT_##ext_char) > + > #endif > #endif > diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c > index b1ade9a49347..177529d48d87 100644 > --- a/arch/riscv/kernel/cpufeature.c > +++ b/arch/riscv/kernel/cpufeature.c [ ... ] > @@ -43,8 +49,22 @@ void riscv_fill_hwcap(void) > continue; > } > > - for (i = 0; i < strlen(isa); ++i) > + i = 0; > + isa_len = strlen(isa); > +#if defined(CONFIG_32BIT) > + if (strncasecmp(isa, "rv32", 4) != 0) strcmp()? > + i += 4; > +#elif defined(CONFIG_64BIT) > + if (strncasecmp(isa, "rv64", 4) != 0) And again here? > + i += 4; > +#endif > + for (; i < isa_len; ++i) { > this_hwcap |= isa2hwcap[(unsigned char)(isa[i])]; > + if ('a' <= isa[i] && isa[i] <= 'z') > + this_isa |= (1UL << (isa[i] - 'a')); > + if ('A' <= isa[i] && isa[i] <= 'Z') > + this_isa |= (1UL << (isa[i] - 'A')); Are these uppercase variants still needed? Nope. Same as above comment. Apologies for forgetting about these usages. I will send a v3 removing them. Regards, Atish - Paul
WARNING: multiple messages have this Message-ID (diff)
From: Atish Patra <Atish.Patra@wdc.com> To: Paul Walmsley <paul.walmsley@sifive.com>, Anup Patel <Anup.Patel@wdc.com> Cc: Mark Rutland <mark.rutland@arm.com>, "devicetree@vger.kernel.org" <devicetree@vger.kernel.org>, Albert Ou <aou@eecs.berkeley.edu>, Greg Kroah-Hartman <gregkh@linuxfoundation.org>, Daniel Lezcano <daniel.lezcano@linaro.org>, "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>, Johan Hovold <johan@kernel.org>, Alexios Zavras <alexios.zavras@intel.com>, Rob Herring <robh+dt@kernel.org>, Palmer Dabbelt <palmer@sifive.com>, "linux-riscv@lists.infradead.org" <linux-riscv@lists.infradead.org>, Enrico Weigelt <info@metux.net>, Thomas Gleixner <tglx@linutronix.de>, Allison Randal <allison@lohutok.net> Subject: Re: [PATCH v2 2/5] RISC-V: Add riscv_isa reprensenting ISA features common across CPUs Date: Wed, 31 Jul 2019 06:27:53 +0000 [thread overview] Message-ID: <99D22117-E146-44BE-93B5-5D25367931C7@wdc.com> (raw) In-Reply-To: <alpine.DEB.2.21.9999.1907302117420.15340@viisi.sifive.com> On 7/30/19, 9:23 PM, "Paul Walmsley" <paul.walmsley@sifive.com> wrote: On Tue, 30 Jul 2019, Atish Patra wrote: > From: Anup Patel <anup.patel@wdc.com> > > This patch adds riscv_isa integer to represent ISA features common > across all CPUs. The riscv_isa is not same as elf_hwcap because > elf_hwcap will only have ISA features relevant for user-space apps > whereas riscv_isa will have ISA features relevant to both kernel > and user-space apps. > > One of the use case is KVM hypervisor where riscv_isa will be used > to do following operations: > > 1. Check whether hypervisor extension is available > 2. Find ISA features that need to be virtualized (e.g. floating > point support, vector extension, etc.) > > Signed-off-by: Anup Patel <anup.patel@wdc.com> > Signed-off-by: Atish Patra <atish.patra@wdc.com> > --- > arch/riscv/include/asm/hwcap.h | 25 +++++++++++++++++++++ > arch/riscv/kernel/cpufeature.c | 41 +++++++++++++++++++++++++++++++--- > 2 files changed, 63 insertions(+), 3 deletions(-) > > diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h > index 7ecb7c6a57b1..e069f60ad5d2 100644 > --- a/arch/riscv/include/asm/hwcap.h > +++ b/arch/riscv/include/asm/hwcap.h > @@ -22,5 +22,30 @@ enum { > }; > > extern unsigned long elf_hwcap; > + > +#define RISCV_ISA_EXT_A (1UL << ('A' - 'A')) Are these uppercase variants still needed if we define the ISA string to be all lowercase, per our recent discussion? Argh. Sorry. We have been carrying this patch so long that I completely forgot about the case sensitive usage here. > +#define RISCV_ISA_EXT_a RISCV_ISA_EXT_A > +#define RISCV_ISA_EXT_C (1UL << ('C' - 'A')) > +#define RISCV_ISA_EXT_c RISCV_ISA_EXT_C > +#define RISCV_ISA_EXT_D (1UL << ('D' - 'A')) > +#define RISCV_ISA_EXT_d RISCV_ISA_EXT_D > +#define RISCV_ISA_EXT_F (1UL << ('F' - 'A')) > +#define RISCV_ISA_EXT_f RISCV_ISA_EXT_F > +#define RISCV_ISA_EXT_H (1UL << ('H' - 'A')) > +#define RISCV_ISA_EXT_h RISCV_ISA_EXT_H > +#define RISCV_ISA_EXT_I (1UL << ('I' - 'A')) > +#define RISCV_ISA_EXT_i RISCV_ISA_EXT_I > +#define RISCV_ISA_EXT_M (1UL << ('M' - 'A')) > +#define RISCV_ISA_EXT_m RISCV_ISA_EXT_M > +#define RISCV_ISA_EXT_S (1UL << ('S' - 'A')) > +#define RISCV_ISA_EXT_s RISCV_ISA_EXT_S > +#define RISCV_ISA_EXT_U (1UL << ('U' - 'A')) > +#define RISCV_ISA_EXT_u RISCV_ISA_EXT_U > + > +extern unsigned long riscv_isa; > + > +#define riscv_isa_extension_available(ext_char) \ > + (riscv_isa & RISCV_ISA_EXT_##ext_char) > + > #endif > #endif > diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c > index b1ade9a49347..177529d48d87 100644 > --- a/arch/riscv/kernel/cpufeature.c > +++ b/arch/riscv/kernel/cpufeature.c [ ... ] > @@ -43,8 +49,22 @@ void riscv_fill_hwcap(void) > continue; > } > > - for (i = 0; i < strlen(isa); ++i) > + i = 0; > + isa_len = strlen(isa); > +#if defined(CONFIG_32BIT) > + if (strncasecmp(isa, "rv32", 4) != 0) strcmp()? > + i += 4; > +#elif defined(CONFIG_64BIT) > + if (strncasecmp(isa, "rv64", 4) != 0) And again here? > + i += 4; > +#endif > + for (; i < isa_len; ++i) { > this_hwcap |= isa2hwcap[(unsigned char)(isa[i])]; > + if ('a' <= isa[i] && isa[i] <= 'z') > + this_isa |= (1UL << (isa[i] - 'a')); > + if ('A' <= isa[i] && isa[i] <= 'Z') > + this_isa |= (1UL << (isa[i] - 'A')); Are these uppercase variants still needed? Nope. Same as above comment. Apologies for forgetting about these usages. I will send a v3 removing them. Regards, Atish - Paul _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2019-07-31 6:28 UTC|newest] Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top 2019-07-31 1:24 [PATCH v2 0/5] Miscellaneous fixes Atish Patra 2019-07-31 1:24 ` Atish Patra 2019-07-31 1:24 ` [PATCH v2 1/5] RISC-V: Remove per cpu clocksource Atish Patra 2019-07-31 1:24 ` Atish Patra 2019-08-16 15:09 ` Daniel Lezcano 2019-08-16 15:09 ` Daniel Lezcano 2019-08-16 18:55 ` Atish Patra 2019-08-16 18:55 ` Atish Patra 2019-08-26 23:48 ` Palmer Dabbelt 2019-08-26 23:48 ` Palmer Dabbelt 2019-08-26 23:48 ` Palmer Dabbelt 2019-07-31 1:24 ` [PATCH v2 2/5] RISC-V: Add riscv_isa reprensenting ISA features common across CPUs Atish Patra 2019-07-31 1:24 ` Atish Patra 2019-07-31 1:24 ` Atish Patra 2019-07-31 4:23 ` Paul Walmsley 2019-07-31 4:23 ` Paul Walmsley 2019-07-31 6:27 ` Atish Patra [this message] 2019-07-31 6:27 ` Atish Patra 2019-07-31 1:24 ` [PATCH v2 3/5] RISC-V: Fix unsupported isa string info Atish Patra 2019-07-31 1:24 ` Atish Patra 2019-07-31 1:24 ` Atish Patra 2019-07-31 1:24 ` [PATCH v2 4/5] RISC-V: Export few kernel symbols Atish Patra 2019-07-31 1:24 ` Atish Patra 2019-07-31 1:24 ` [PATCH v2 5/5] dt-bindings: Update the isa string description Atish Patra 2019-07-31 1:24 ` Atish Patra 2019-07-31 4:52 ` Paul Walmsley 2019-07-31 4:52 ` Paul Walmsley 2019-07-31 4:52 ` Paul Walmsley 2019-07-31 6:43 ` Atish Patra 2019-07-31 6:43 ` Atish Patra
Reply instructions: You may reply publicly to this message via plain-text email using any one of the following methods: * Save the following mbox file, import it into your mail client, and reply-to-all from there: mbox Avoid top-posting and favor interleaved quoting: https://en.wikipedia.org/wiki/Posting_style#Interleaved_style * Reply using the --to, --cc, and --in-reply-to switches of git-send-email(1): git send-email \ --in-reply-to=99D22117-E146-44BE-93B5-5D25367931C7@wdc.com \ --to=atish.patra@wdc.com \ --cc=Anup.Patel@wdc.com \ --cc=alexios.zavras@intel.com \ --cc=allison@lohutok.net \ --cc=aou@eecs.berkeley.edu \ --cc=daniel.lezcano@linaro.org \ --cc=devicetree@vger.kernel.org \ --cc=gregkh@linuxfoundation.org \ --cc=info@metux.net \ --cc=johan@kernel.org \ --cc=linux-kernel@vger.kernel.org \ --cc=linux-riscv@lists.infradead.org \ --cc=mark.rutland@arm.com \ --cc=palmer@sifive.com \ --cc=paul.walmsley@sifive.com \ --cc=robh+dt@kernel.org \ --cc=tglx@linutronix.de \ /path/to/YOUR_REPLY https://kernel.org/pub/software/scm/git/docs/git-send-email.html * If your mail client supports setting the In-Reply-To header via mailto: links, try the mailto: linkBe sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.