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From: Jan Beulich <JBeulich@suse.com>
To: "xen-devel@lists.xenproject.org" <xen-devel@lists.xenproject.org>
Cc: Andrew Cooper <andrew.cooper3@citrix.com>, Wei Liu <wl@xen.org>,
	RogerPau Monne <roger.pau@citrix.com>
Subject: [Xen-devel] [PATCH v9 13/23] x86emul: support remaining AVX512_VBMI2 insns
Date: Mon, 1 Jul 2019 11:23:13 +0000	[thread overview]
Message-ID: <9c4d708b-4ae9-5341-2c4b-bfeada164422@suse.com> (raw)
In-Reply-To: <f69ca82f-e2db-e85e-ff98-2060a8dc28a5@suse.com>

As in a few cases before, since the insns here and in particular their
memory access patterns follow the usual scheme, I didn't think it was
necessary to add a contrived test specifically for them, beyond the
Disp8 scaling one.

Signed-off-by: Jan Beulich <jbeulich@suse.com>
Acked-by: Andrew Cooper <andrew.cooper3@citrix.com>
---
v7: Re-base over change earlier in the series.
v6: New.

--- a/tools/tests/x86_emulator/evex-disp8.c
+++ b/tools/tests/x86_emulator/evex-disp8.c
@@ -558,6 +558,14 @@ static const struct test avx512_vbmi_all
  static const struct test avx512_vbmi2_all[] = {
      INSN(pcompress, 66, 0f38, 63, vl, bw, el),
      INSN(pexpand,   66, 0f38, 62, vl, bw, el),
+    INSN(pshld,     66, 0f3a, 71, vl, dq, vl),
+    INSN(pshldv,    66, 0f38, 71, vl, dq, vl),
+    INSN(pshldvw,   66, 0f38, 70, vl,  w, vl),
+    INSN(pshldw,    66, 0f3a, 70, vl,  w, vl),
+    INSN(pshrd,     66, 0f3a, 73, vl, dq, vl),
+    INSN(pshrdv,    66, 0f38, 73, vl, dq, vl),
+    INSN(pshrdvw,   66, 0f38, 72, vl,  w, vl),
+    INSN(pshrdw,    66, 0f3a, 72, vl,  w, vl),
  };
  
  static const struct test avx512_vpopcntdq_all[] = {
--- a/xen/arch/x86/x86_emulate/x86_emulate.c
+++ b/xen/arch/x86/x86_emulate/x86_emulate.c
@@ -487,6 +487,7 @@ static const struct ext0f38_table {
      [0x62] = { .simd_size = simd_packed_int, .two_op = 1, .d8s = d8s_bw },
      [0x63] = { .simd_size = simd_packed_int, .to_mem = 1, .two_op = 1, .d8s = d8s_bw },
      [0x64 ... 0x66] = { .simd_size = simd_packed_int, .d8s = d8s_vl },
+    [0x70 ... 0x73] = { .simd_size = simd_packed_int, .d8s = d8s_vl },
      [0x75 ... 0x76] = { .simd_size = simd_packed_int, .d8s = d8s_vl },
      [0x77] = { .simd_size = simd_packed_fp, .d8s = d8s_vl },
      [0x78] = { .simd_size = simd_other, .two_op = 1 },
@@ -611,6 +612,7 @@ static const struct ext0f3a_table {
      [0x6a ... 0x6b] = { .simd_size = simd_scalar_opc, .four_op = 1 },
      [0x6c ... 0x6d] = { .simd_size = simd_packed_fp, .four_op = 1 },
      [0x6e ... 0x6f] = { .simd_size = simd_scalar_opc, .four_op = 1 },
+    [0x70 ... 0x73] = { .simd_size = simd_packed_int, .d8s = d8s_vl },
      [0x78 ... 0x79] = { .simd_size = simd_packed_fp, .four_op = 1 },
      [0x7a ... 0x7b] = { .simd_size = simd_scalar_opc, .four_op = 1 },
      [0x7c ... 0x7d] = { .simd_size = simd_packed_fp, .four_op = 1 },
@@ -8969,6 +8971,16 @@ x86_emulate(
          }
          goto simd_zmm;
  
+    case X86EMUL_OPC_EVEX_66(0x0f38, 0x70): /* vpshldvw [xyz]mm/mem,[xyz]mm,[xyz]mm{k} */
+    case X86EMUL_OPC_EVEX_66(0x0f38, 0x72): /* vpshrdvw [xyz]mm/mem,[xyz]mm,[xyz]mm{k} */
+        generate_exception_if(!evex.w, EXC_UD);
+        elem_bytes = 2;
+        /* fall through */
+    case X86EMUL_OPC_EVEX_66(0x0f38, 0x71): /* vpshldv{d,q} [xyz]mm/mem,[xyz]mm,[xyz]mm{k} */
+    case X86EMUL_OPC_EVEX_66(0x0f38, 0x73): /* vpshrdv{d,q} [xyz]mm/mem,[xyz]mm,[xyz]mm{k} */
+        host_and_vcpu_must_have(avx512_vbmi2);
+        goto avx512f_no_sae;
+
      case X86EMUL_OPC_EVEX_66(0x0f38, 0x75): /* vpermi2{b,w} [xyz]mm/mem,[xyz]mm,[xyz]mm{k} */
      case X86EMUL_OPC_EVEX_66(0x0f38, 0x7d): /* vpermt2{b,w} [xyz]mm/mem,[xyz]mm,[xyz]mm{k} */
      case X86EMUL_OPC_EVEX_66(0x0f38, 0x8d): /* vperm{b,w} [xyz]mm/mem,[xyz]mm,[xyz]mm{k} */
@@ -10281,6 +10293,16 @@ x86_emulate(
          avx512_vlen_check(true);
          goto simd_imm8_zmm;
  
+    case X86EMUL_OPC_EVEX_66(0x0f3a, 0x70): /* vpshldw $imm8,[xyz]mm/mem,[xyz]mm,[xyz]mm{k} */
+    case X86EMUL_OPC_EVEX_66(0x0f3a, 0x72): /* vpshrdw $imm8,[xyz]mm/mem,[xyz]mm,[xyz]mm{k} */
+        generate_exception_if(!evex.w, EXC_UD);
+        elem_bytes = 2;
+        /* fall through */
+    case X86EMUL_OPC_EVEX_66(0x0f3a, 0x71): /* vpshld{d,q} $imm8,[xyz]mm/mem,[xyz]mm,[xyz]mm{k} */
+    case X86EMUL_OPC_EVEX_66(0x0f3a, 0x73): /* vpshrd{d,q} $imm8,[xyz]mm/mem,[xyz]mm,[xyz]mm{k} */
+        host_and_vcpu_must_have(avx512_vbmi2);
+        goto avx512f_imm8_no_sae;
+
      case X86EMUL_OPC(0x0f3a, 0xcc):     /* sha1rnds4 $imm8,xmm/m128,xmm */
          host_and_vcpu_must_have(sha);
          op_bytes = 16;

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  parent reply	other threads:[~2019-07-01 11:24 UTC|newest]

Thread overview: 46+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-07-01 11:13 [Xen-devel] [PATCH v9 00/23] x86emul: remaining AVX512 support Jan Beulich
2019-07-01 11:16 ` [Xen-devel] [PATCH v9 01/23] x86emul: support AVX512{F, _VBMI2} compress/expand insns Jan Beulich
2019-07-04 13:12   ` Andrew Cooper
2019-07-01 11:17 ` [Xen-devel] [PATCH v9 02/23] x86emul: support remaining misc AVX512{F, BW} insns Jan Beulich
2019-07-01 11:17 ` [Xen-devel] [PATCH v9 03/23] x86emul: prepare for AVX512F S/G insns Jan Beulich
2019-07-04 13:50   ` Andrew Cooper
2019-07-01 11:18 ` [Xen-devel] [PATCH v9 04/23] x86emul: test harness adjustments " Jan Beulich
2019-07-04 13:52   ` Andrew Cooper
2019-07-01 11:18 ` [Xen-devel] [PATCH v9 05/23] x86emul: support AVX512F gather insns Jan Beulich
2019-07-04 14:10   ` Andrew Cooper
2019-07-04 14:16     ` Andrew Cooper
2019-07-04 14:25       ` Jan Beulich
2019-07-04 18:26         ` Andrew Cooper
2019-07-04 14:22     ` Jan Beulich
2019-07-04 18:40       ` Andrew Cooper
2019-07-01 11:19 ` [Xen-devel] [PATCH v9 06/23] x86emul: add high register S/G test cases Jan Beulich
2019-07-01 11:20 ` [Xen-devel] [PATCH v9 07/23] x86emul: support AVX512F scatter insns Jan Beulich
2019-07-04 14:19   ` Andrew Cooper
2019-07-01 11:20 ` [Xen-devel] [PATCH v9 08/23] x86emul: support AVX512PF insns Jan Beulich
2019-07-04 14:44   ` Andrew Cooper
2019-07-04 14:50     ` Jan Beulich
2019-07-04 18:29       ` Andrew Cooper
2019-07-01 11:21 ` [Xen-devel] [PATCH v9 09/23] x86emul: support AVX512CD insns Jan Beulich
2019-07-01 11:21 ` [Xen-devel] [PATCH v9 10/23] x86emul: complete support of AVX512_VBMI insns Jan Beulich
2019-07-01 11:22 ` [Xen-devel] [PATCH v9 11/23] x86emul: support of AVX512* population count insns Jan Beulich
2019-07-04 14:47   ` Andrew Cooper
2019-07-04 14:54     ` Jan Beulich
2019-07-04 18:38       ` Andrew Cooper
2019-07-05  8:10         ` Jan Beulich
2019-07-01 11:22 ` [Xen-devel] [PATCH v9 12/23] x86emul: support of AVX512_IFMA insns Jan Beulich
2019-07-01 11:23 ` Jan Beulich [this message]
2019-07-01 11:23 ` [Xen-devel] [PATCH v9 14/23] x86emul: support AVX512_4FMAPS insns Jan Beulich
2019-07-04 14:49   ` Andrew Cooper
2019-07-01 11:24 ` [Xen-devel] [PATCH v9 15/23] x86emul: support AVX512_4VNNIW insns Jan Beulich
2019-07-01 11:24 ` [Xen-devel] [PATCH v9 16/23] x86emul: support AVX512_VNNI insns Jan Beulich
2019-07-04 14:50   ` Andrew Cooper
2019-07-01 11:25 ` [Xen-devel] [PATCH v9 17/23] x86emul: support VPCLMULQDQ insns Jan Beulich
2019-07-01 11:25 ` [Xen-devel] [PATCH v9 18/23] x86emul: support VAES insns Jan Beulich
2019-07-01 11:26 ` [Xen-devel] [PATCH v9 19/23] x86emul: support GFNI insns Jan Beulich
2019-07-04 15:10   ` Andrew Cooper
2019-07-01 11:26 ` [Xen-devel] [PATCH v9 20/23] x86emul: restore ordering within main switch statement Jan Beulich
2019-07-01 11:27 ` [Xen-devel] [PATCH v9 21/23] x86emul: add an AES/VAES test case to the harness Jan Beulich
2019-07-01 11:28 ` [Xen-devel] [PATCH v9 22/23] x86emul: add a SHA " Jan Beulich
2019-07-01 11:28 ` [Xen-devel] [PATCH v9 23/23] x86emul: support VPCLMULQDQ insns Jan Beulich
2019-07-03 16:05 ` [Xen-devel] [PATCH v9 00/23] x86emul: remaining AVX512 support Jan Beulich
2019-07-03 16:06 ` [Xen-devel] [PATCH v9 23/23] x86emul: add a PCLMUL/VPCLMUL test case to the harness Jan Beulich

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