[PATCH 00/24] DC Patches 06 Jun 2019

[PATCH 00/24] DC Patches 06 Jun 2019

[Bhawanpreet Lakha]

Summary Of Changes
*Rework CRTC color management
*Add underflow asserts
*i2c fix
*gamma fixes

Anthony Koo (1):
  drm/amd/display: fix issue with eDP not detected on driver load

Aric Cyr (3):
  drm/amd/display: 3.2.33
  drm/amd/display: 3.2.34
  drm/amd/display: 3.2.35

Charlene Liu (2):
  drm/amd/display: add some math functions for dcn_calc_math
  drm/amd/display: add audio related regs

Chris Park (1):
  drm/amd/display: Clean up scdc_test_data struct

Derek Lai (1):
  drm/amd/display: add i2c_hw_Status check to make sure as HW I2c in use

Dmytro Laktyushkin (1):
  drm/amd/display: move vmid determination logic out of dc

Eric Bernstein (1):
  drm/amd/display: Dont aser if DP_DPHY_INTERNAL_CTRL

Harmanprit Tatla (1):
  drm/amd/display: Gamma logic limitations causing unintended use of RAM
    over ROM.

Jordan Lazare (1):
  drm/amd/display: Remove superflous error message

Krunoslav Kovac (1):
  drm/amd/display: fix gamma logic breaking driver unload

Nicholas Kazlauskas (2):
  drm/amd/display: Copy stream updates onto streams
  drm/amd/display: Rework CRTC color management

Samson Tam (1):
  drm/amd/display: set link->dongle_max_pix_clk to 0 on a disconnect

SivapiriyanKumarasamy (1):
  drm/amd/display: S3 Resume time increase after decoupling DPMS from
    fast boot

Su Sung Chung (1):
  drm/amd/display: make clk_mgr call enable_pme_wa

Tao.Huang (1):
  drm/amd/display: fix resource saving missing when power state switch

Thomas Lim (1):
  drm/amd/display: Add Underflow Asserts to dc

Wesley Chalmers (3):
  drm/amd/display: Update link rate from DPCD 10
  drm/amd/display: Use macro for invalid OPP ID
  drm/amd/display: Use stream opp_id instead of hubp

abdoulaye berthe (1):
  drm/amd/display: Do not grant POST_LT_ADJ when TPS4 is used

 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c |  32 +-
 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h |  10 +-
 .../amd/display/amdgpu_dm/amdgpu_dm_color.c   | 473 ++++++++++++------
 drivers/gpu/drm/amd/display/dc/Makefile       |   4 +-
 .../drm/amd/display/dc/calcs/dcn_calc_math.c  |  20 +
 .../drm/amd/display/dc/calcs/dcn_calc_math.h  |   3 +
 .../display/dc/clk_mgr/dcn10/rv1_clk_mgr.c    |  14 +
 drivers/gpu/drm/amd/display/dc/core/dc.c      |  82 ++-
 drivers/gpu/drm/amd/display/dc/core/dc_link.c |  51 +-
 .../gpu/drm/amd/display/dc/core/dc_link_ddc.c |  14 +-
 .../gpu/drm/amd/display/dc/core/dc_link_dp.c  |  65 +--
 .../drm/amd/display/dc/core/dc_vm_helper.c    | 123 -----
 drivers/gpu/drm/amd/display/dc/dc.h           |   4 +-
 drivers/gpu/drm/amd/display/dc/dc_hw_types.h  |   6 +
 .../gpu/drm/amd/display/dc/dce/dce_audio.c    |   4 +-
 .../gpu/drm/amd/display/dc/dce/dce_audio.h    |   7 +
 .../gpu/drm/amd/display/dc/dce/dce_i2c_hw.c   |  65 ++-
 .../gpu/drm/amd/display/dc/dce/dce_i2c_hw.h   |   5 +
 .../display/dc/dce110/dce110_hw_sequencer.c   |  60 +--
 .../gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c |   7 +-
 .../amd/display/dc/dcn10/dcn10_hw_sequencer.c |  41 +-
 .../amd/display/dc/dcn10/dcn10_hw_sequencer.h |   2 +
 .../amd/display/dc/dcn10/dcn10_link_encoder.c |   4 +-
 .../drm/amd/display/dc/dcn10/dcn10_resource.c |   4 +-
 .../drm/amd/display/dc/dml/dml_inline_defs.h  |   8 +
 drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h  |   5 +-
 drivers/gpu/drm/amd/display/dc/inc/hw/vmid.h  |   1 +
 .../gpu/drm/amd/display/dc/inc/hw_sequencer.h |   1 +
 .../gpu/drm/amd/display/dc/inc/vm_helper.h    |  16 +-
 .../amd/display/modules/color/color_gamma.c   |   5 +-
 30 files changed, 715 insertions(+), 421 deletions(-)
 delete mode 100644 drivers/gpu/drm/amd/display/dc/core/dc_vm_helper.c

-- 
2.17.1

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[PATCH 01/24] drm/amd/display: fix resource saving missing when power state switch

[Bhawanpreet Lakha]

From: "Tao.Huang" <Tao.Huang@amd.com>

Signed-off-by: Tao.Huang <Tao.Huang@amd.com>
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
---
 drivers/gpu/drm/amd/display/dc/core/dc.c | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
index d89a29bd8785..0bff546d3727 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -1930,6 +1930,12 @@ void dc_set_power_state(
 	enum dc_acpi_cm_power_state power_state)
 {
 	struct kref refcount;
+	struct display_mode_lib *dml = kzalloc(sizeof(struct display_mode_lib),
+						GFP_KERNEL);
+
+	ASSERT(dml);
+	if (!dml)
+		return;
 
 	switch (power_state) {
 	case DC_ACPI_CM_POWER_STATE_D0:
@@ -1946,15 +1952,20 @@ void dc_set_power_state(
 
 		/* Preserve refcount */
 		refcount = dc->current_state->refcount;
+		/* Preserve display mode lib */
+		memcpy(dml, &dc->current_state->bw_ctx.dml, sizeof(struct display_mode_lib));
+
 		dc_resource_state_destruct(dc->current_state);
 		memset(dc->current_state, 0,
 				sizeof(*dc->current_state));
 
 		dc->current_state->refcount = refcount;
+		dc->current_state->bw_ctx.dml = *dml;
 
 		break;
 	}
 
+	kfree(dml);
 }
 
 void dc_resume(struct dc *dc)
-- 
2.17.1

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[PATCH 02/24] drm/amd/display: Update link rate from DPCD 10

[Bhawanpreet Lakha]

From: Wesley Chalmers <Wesley.Chalmers@amd.com>

[WHY]
Some panels return a link rate of 0 (unknown) in DPCD 0. In this case,
an appropriate mode cannot be set, and certain panels will show
corruption as they are forced to use a mode they do not support.

[HOW]
Read DPCD 10 in the case where supported link rate from DPCD 0 is
unknown, and pass that value on to the reported link rate.
This re-introduces behaviour present in previous versions that appears
to have been accidentally removed.

Signed-off-by: Wesley Chalmers <Wesley.Chalmers@amd.com>
Reviewed-by: Anthony Koo <Anthony.Koo@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
---
 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 9 ++++++---
 1 file changed, 6 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
index 65d6caedbd82..2d519e5fc3ea 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
@@ -1624,8 +1624,7 @@ static bool decide_edp_link_settings(struct dc_link *link, struct dc_link_settin
 	uint32_t link_bw;
 
 	if (link->dpcd_caps.dpcd_rev.raw < DPCD_REV_14 ||
-			link->dpcd_caps.edp_supported_link_rates_count == 0 ||
-			link->dc->config.optimize_edp_link_rate == false) {
+			link->dpcd_caps.edp_supported_link_rates_count == 0) {
 		*link_setting = link->verified_link_cap;
 		return true;
 	}
@@ -2609,7 +2608,8 @@ void detect_edp_sink_caps(struct dc_link *link)
 	memset(supported_link_rates, 0, sizeof(supported_link_rates));
 
 	if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_14 &&
-			link->dc->config.optimize_edp_link_rate) {
+			(link->dc->config.optimize_edp_link_rate ||
+			link->reported_link_cap.link_rate == LINK_RATE_UNKNOWN)) {
 		// Read DPCD 00010h - 0001Fh 16 bytes at one shot
 		core_link_read_dpcd(link, DP_SUPPORTED_LINK_RATES,
 							supported_link_rates, sizeof(supported_link_rates));
@@ -2624,6 +2624,9 @@ void detect_edp_sink_caps(struct dc_link *link)
 				link_rate = linkRateInKHzToLinkRateMultiplier(link_rate_in_khz);
 				link->dpcd_caps.edp_supported_link_rates[link->dpcd_caps.edp_supported_link_rates_count] = link_rate;
 				link->dpcd_caps.edp_supported_link_rates_count++;
+
+				if (link->reported_link_cap.link_rate < link_rate)
+					link->reported_link_cap.link_rate = link_rate;
 			}
 		}
 	}
-- 
2.17.1

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[PATCH 03/24] drm/amd/display: Copy stream updates onto streams

[Bhawanpreet Lakha]

From: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>

[Why]
Almost every function in DC that works with stream state expects that
the current state on the stream is the one that it should be writing
out. These functions are typically triggered by specifying a particular
stream update - but the actual contents of the stream update itself
are ignored, leaving it to the DM to actually update the stream state
itself.

The problem with doing this in DM is a matter of timing. On Linux
most of this is incorrectly done in atomic check, when we actually want
it to be done during atomic commit tail while access to DC is locked.

To give an example, a commit requesting to modify color management
state for DM could come in, be rejected, but still have modified
the actual system state for the stream since it's shared memory. The
next time color management gets programmed it'll use the rejected
color management info - which might not even still be around if it's
a custom transfer function.

So a reasonable place to perform this is within DC itself and this is
the model that's currently in use for surface updates. DC can even
compare the current system state to the incoming surface update to
determine update level, something that can't currnetly be done with the
framework for stream updates.

[How]
Duplicate the framework used for surface updates for stream updates
as well. Copy all the updates after checking the update type.

Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Reviewed-by: Harry Wentland <Harry.Wentland@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
---
 drivers/gpu/drm/amd/display/dc/core/dc.c | 69 ++++++++++++++++++++++++
 1 file changed, 69 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 0bff546d3727..45b542b5d920 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -1607,6 +1607,73 @@ static void copy_surface_update_to_plane(
 			*srf_update->coeff_reduction_factor;
 }
 
+static void copy_stream_update_to_stream(struct dc *dc,
+					 struct dc_state *context,
+					 struct dc_stream_state *stream,
+					 const struct dc_stream_update *update)
+{
+	if (update == NULL || stream == NULL)
+		return;
+
+	if (update->src.height && update->src.width)
+		stream->src = update->src;
+
+	if (update->dst.height && update->dst.width)
+		stream->dst = update->dst;
+
+	if (update->out_transfer_func &&
+	    stream->out_transfer_func != update->out_transfer_func) {
+		stream->out_transfer_func->sdr_ref_white_level =
+			update->out_transfer_func->sdr_ref_white_level;
+		stream->out_transfer_func->tf = update->out_transfer_func->tf;
+		stream->out_transfer_func->type =
+			update->out_transfer_func->type;
+		memcpy(&stream->out_transfer_func->tf_pts,
+		       &update->out_transfer_func->tf_pts,
+		       sizeof(struct dc_transfer_func_distributed_points));
+	}
+
+	if (update->hdr_static_metadata)
+		stream->hdr_static_metadata = *update->hdr_static_metadata;
+
+	if (update->abm_level)
+		stream->abm_level = *update->abm_level;
+
+	if (update->periodic_interrupt0)
+		stream->periodic_interrupt0 = *update->periodic_interrupt0;
+
+	if (update->periodic_interrupt1)
+		stream->periodic_interrupt1 = *update->periodic_interrupt1;
+
+	if (update->gamut_remap)
+		stream->gamut_remap_matrix = *update->gamut_remap;
+
+	/* Note: this being updated after mode set is currently not a use case
+	 * however if it arises OCSC would need to be reprogrammed at the
+	 * minimum
+	 */
+	if (update->output_color_space)
+		stream->output_color_space = *update->output_color_space;
+
+	if (update->output_csc_transform)
+		stream->csc_color_matrix = *update->output_csc_transform;
+
+	if (update->vrr_infopacket)
+		stream->vrr_infopacket = *update->vrr_infopacket;
+
+	if (update->dpms_off)
+		stream->dpms_off = *update->dpms_off;
+
+	if (update->vsc_infopacket)
+		stream->vsc_infopacket = *update->vsc_infopacket;
+
+	if (update->vsp_infopacket)
+		stream->vsp_infopacket = *update->vsp_infopacket;
+
+	if (update->dither_option)
+		stream->dither_option = *update->dither_option;
+}
+
 static void commit_planes_do_stream_update(struct dc *dc,
 		struct dc_stream_state *stream,
 		struct dc_stream_update *stream_update,
@@ -1857,6 +1924,8 @@ void dc_commit_updates_for_stream(struct dc *dc,
 		}
 	}
 
+	copy_stream_update_to_stream(dc, context, stream, stream_update);
+
 	commit_planes_for_stream(
 				dc,
 				srf_updates,
-- 
2.17.1

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[PATCH 04/24] drm/amd/display: add some math functions for dcn_calc_math

[Bhawanpreet Lakha]

From: Charlene Liu <charlene.liu@amd.com>

Implement floor, ceil, and fabs

Signed-off-by: Charlene Liu <charlene.liu@amd.com>
Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
---
 .../drm/amd/display/dc/calcs/dcn_calc_math.c  | 20 +++++++++++++++++++
 .../drm/amd/display/dc/calcs/dcn_calc_math.h  |  3 +++
 .../drm/amd/display/dc/dml/dml_inline_defs.h  |  8 ++++++++
 3 files changed, 31 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_math.c b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_math.c
index 7600a4a4abc7..07d18e78de49 100644
--- a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_math.c
+++ b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_math.c
@@ -73,6 +73,17 @@ float dcn_bw_floor2(const float arg, const float significance)
 		return 0;
 	return ((int) (arg / significance)) * significance;
 }
+float dcn_bw_floor(const float arg)
+{
+	return ((int) (arg));
+}
+
+float dcn_bw_ceil(const float arg)
+{
+	float flr = dcn_bw_floor2(arg, 1);
+
+	return flr + 0.00001 >= arg ? arg : flr + 1;
+}
 
 float dcn_bw_ceil2(const float arg, const float significance)
 {
@@ -109,6 +120,15 @@ float dcn_bw_pow(float a, float exp)
 	}
 }
 
+double dcn_bw_fabs(double a)
+{
+	if (a > 0)
+		return (a);
+	else
+		return (-a);
+}
+
+
 float dcn_bw_log(float a, float b)
 {
 	int * const exp_ptr = (int *)(&a);
diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_math.h b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_math.h
index f46ab0e24ca1..45a07eeffbb6 100644
--- a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_math.h
+++ b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_math.h
@@ -31,10 +31,13 @@ float dcn_bw_min2(const float arg1, const float arg2);
 unsigned int dcn_bw_max(const unsigned int arg1, const unsigned int arg2);
 float dcn_bw_max2(const float arg1, const float arg2);
 float dcn_bw_floor2(const float arg, const float significance);
+float dcn_bw_floor(const float arg);
 float dcn_bw_ceil2(const float arg, const float significance);
+float dcn_bw_ceil(const float arg);
 float dcn_bw_max3(float v1, float v2, float v3);
 float dcn_bw_max5(float v1, float v2, float v3, float v4, float v5);
 float dcn_bw_pow(float a, float exp);
 float dcn_bw_log(float a, float b);
+double dcn_bw_fabs(double a);
 
 #endif /* _DCN_CALC_MATH_H_ */
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dml_inline_defs.h b/drivers/gpu/drm/amd/display/dc/dml/dml_inline_defs.h
index e8ce08567cd8..eca140da13d8 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dml_inline_defs.h
+++ b/drivers/gpu/drm/amd/display/dc/dml/dml_inline_defs.h
@@ -129,4 +129,12 @@ static inline unsigned int dml_round_to_multiple(unsigned int num,
 	else
 		return (num - remainder);
 }
+static inline double dml_abs(double a)
+{
+	if (a > 0)
+		return a;
+	else
+		return (a*(-1));
+}
+
 #endif
-- 
2.17.1

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[PATCH 05/24] drm/amd/display: 3.2.33

[Bhawanpreet Lakha]

From: Aric Cyr <aric.cyr@amd.com>

Signed-off-by: Aric Cyr <aric.cyr@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
---
 drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index 7ec6884acee4..3f22212437ca 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -39,7 +39,7 @@
 #include "inc/hw/dmcu.h"
 #include "dml/display_mode_lib.h"
 
-#define DC_VER "3.2.32"
+#define DC_VER "3.2.33"
 
 #define MAX_SURFACES 3
 #define MAX_PLANES 6
-- 
2.17.1

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[PATCH 06/24] drm/amd/display: Dont aser if DP_DPHY_INTERNAL_CTRL

[Bhawanpreet Lakha]

From: Eric Bernstein <eric.bernstein@amd.com>

No need to assert just return

Signed-off-by: Eric Bernstein <eric.bernstein@amd.com>
Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
---
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c
index 3396e499090d..9427a461bb26 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c
@@ -229,7 +229,9 @@ static void setup_panel_mode(
 {
 	uint32_t value;
 
-	ASSERT(REG(DP_DPHY_INTERNAL_CTRL));
+	if (!REG(DP_DPHY_INTERNAL_CTRL))
+		return;
+
 	value = REG_READ(DP_DPHY_INTERNAL_CTRL);
 
 	switch (panel_mode) {
-- 
2.17.1

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[PATCH 07/24] drm/amd/display: add i2c_hw_Status check to make sure as HW I2c in use

[Bhawanpreet Lakha]

From: Derek Lai <Derek.Lai@amd.com>

1. Add i2c_hw_Status check to make sure when HW i2c is in use.
2. Don't reset HW engine in is_hw_busy() and instead do this in
process_transaction() because SW i2c does not check if hw i2c is in use

Signed-off-by: Derek Lai <Derek.Lai@amd.com>
Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
---
 .../gpu/drm/amd/display/dc/dce/dce_i2c_hw.c   | 65 +++++++++++--------
 .../gpu/drm/amd/display/dc/dce/dce_i2c_hw.h   |  5 ++
 2 files changed, 43 insertions(+), 27 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c b/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c
index 526aab438374..7f2460caa2a6 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c
@@ -149,6 +149,36 @@ static void process_channel_reply(
 	}
 }
 
+static bool is_engine_available(struct dce_i2c_hw *dce_i2c_hw)
+{
+	unsigned int arbitrate;
+	unsigned int i2c_hw_status;
+
+	REG_GET(HW_STATUS, DC_I2C_DDC1_HW_STATUS, &i2c_hw_status);
+	if (i2c_hw_status == DC_I2C_STATUS__DC_I2C_STATUS_USED_BY_HW)
+		return false;
+
+	REG_GET(DC_I2C_ARBITRATION, DC_I2C_REG_RW_CNTL_STATUS, &arbitrate);
+	if (arbitrate == DC_I2C_REG_RW_CNTL_STATUS_DMCU_ONLY)
+		return false;
+
+	return true;
+}
+
+static bool is_hw_busy(struct dce_i2c_hw *dce_i2c_hw)
+{
+	uint32_t i2c_sw_status = 0;
+
+	REG_GET(DC_I2C_SW_STATUS, DC_I2C_SW_STATUS, &i2c_sw_status);
+	if (i2c_sw_status == DC_I2C_STATUS__DC_I2C_STATUS_IDLE)
+		return false;
+
+	if (is_engine_available(dce_i2c_hw))
+		return false;
+
+	return true;
+}
+
 static bool process_transaction(
 	struct dce_i2c_hw *dce_i2c_hw,
 	struct i2c_request_transaction_data *request)
@@ -159,6 +189,11 @@ static bool process_transaction(
 	bool last_transaction = false;
 	uint32_t value = 0;
 
+	if (is_hw_busy(dce_i2c_hw)) {
+		request->status = I2C_CHANNEL_OPERATION_ENGINE_BUSY;
+		return false;
+	}
+
 	last_transaction = ((dce_i2c_hw->transaction_count == 3) ||
 			(request->action == DCE_I2C_TRANSACTION_ACTION_I2C_WRITE) ||
 			(request->action & DCE_I2C_TRANSACTION_ACTION_I2C_READ));
@@ -294,27 +329,12 @@ static bool setup_engine(
 	 * Enable restart of SW I2C that was interrupted by HW
 	 * disable queuing of software while I2C is in use by HW
 	 */
-	REG_UPDATE_2(DC_I2C_ARBITRATION,
-		     DC_I2C_NO_QUEUED_SW_GO, 0,
-		     DC_I2C_SW_PRIORITY, DC_I2C_ARBITRATION__DC_I2C_SW_PRIORITY_NORMAL);
+	REG_UPDATE(DC_I2C_ARBITRATION,
+			DC_I2C_NO_QUEUED_SW_GO, 0);
 
 	return true;
 }
 
-static bool is_hw_busy(struct dce_i2c_hw *dce_i2c_hw)
-{
-	uint32_t i2c_sw_status = 0;
-
-	REG_GET(DC_I2C_SW_STATUS, DC_I2C_SW_STATUS, &i2c_sw_status);
-	if (i2c_sw_status == DC_I2C_STATUS__DC_I2C_STATUS_IDLE)
-		return false;
-
-	reset_hw_engine(dce_i2c_hw);
-
-	REG_GET(DC_I2C_SW_STATUS, DC_I2C_SW_STATUS, &i2c_sw_status);
-	return i2c_sw_status != DC_I2C_STATUS__DC_I2C_STATUS_IDLE;
-}
-
 static void release_engine(
 	struct dce_i2c_hw *dce_i2c_hw)
 {
@@ -349,16 +369,6 @@ static void release_engine(
 
 }
 
-static bool is_engine_available(struct dce_i2c_hw *dce_i2c_hw)
-{
-	unsigned int arbitrate;
-
-	REG_GET(DC_I2C_ARBITRATION, DC_I2C_REG_RW_CNTL_STATUS, &arbitrate);
-	if (arbitrate == DC_I2C_REG_RW_CNTL_STATUS_DMCU_ONLY)
-		return false;
-	return true;
-}
-
 struct dce_i2c_hw *acquire_i2c_hw_engine(
 	struct resource_pool *pool,
 	struct ddc *ddc)
@@ -456,6 +466,7 @@ static void submit_channel_request_hw(
 		request->status = I2C_CHANNEL_OPERATION_ENGINE_BUSY;
 		return;
 	}
+	reset_hw_engine(dce_i2c_hw);
 
 	execute_transaction(dce_i2c_hw);
 
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h b/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h
index f718e3d396f2..a633632f625b 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h
@@ -84,6 +84,7 @@ enum {
 #define I2C_HW_ENGINE_COMMON_REG_LIST(id)\
 	SRI(SETUP, DC_I2C_DDC, id),\
 	SRI(SPEED, DC_I2C_DDC, id),\
+	SRI(HW_STATUS, DC_I2C_DDC, id),\
 	SR(DC_I2C_ARBITRATION),\
 	SR(DC_I2C_CONTROL),\
 	SR(DC_I2C_SW_STATUS),\
@@ -105,6 +106,7 @@ enum {
 	I2C_SF(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_DATA_DRIVE_SEL, mask_sh),\
 	I2C_SF(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_INTRA_TRANSACTION_DELAY, mask_sh),\
 	I2C_SF(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_INTRA_BYTE_DELAY, mask_sh),\
+	I2C_SF(DC_I2C_DDC1_HW_STATUS, DC_I2C_DDC1_HW_STATUS, mask_sh),\
 	I2C_SF(DC_I2C_ARBITRATION, DC_I2C_SW_USE_I2C_REG_REQ, mask_sh),\
 	I2C_SF(DC_I2C_ARBITRATION, DC_I2C_SW_DONE_USING_I2C_REG, mask_sh),\
 	I2C_SF(DC_I2C_ARBITRATION, DC_I2C_NO_QUEUED_SW_GO, mask_sh),\
@@ -146,6 +148,7 @@ struct dce_i2c_shift {
 	uint8_t DC_I2C_DDC1_DATA_DRIVE_SEL;
 	uint8_t DC_I2C_DDC1_INTRA_TRANSACTION_DELAY;
 	uint8_t DC_I2C_DDC1_INTRA_BYTE_DELAY;
+	uint8_t DC_I2C_DDC1_HW_STATUS;
 	uint8_t DC_I2C_SW_DONE_USING_I2C_REG;
 	uint8_t DC_I2C_SW_USE_I2C_REG_REQ;
 	uint8_t DC_I2C_NO_QUEUED_SW_GO;
@@ -185,6 +188,7 @@ struct dce_i2c_mask {
 	uint32_t DC_I2C_DDC1_DATA_DRIVE_SEL;
 	uint32_t DC_I2C_DDC1_INTRA_TRANSACTION_DELAY;
 	uint32_t DC_I2C_DDC1_INTRA_BYTE_DELAY;
+	uint32_t DC_I2C_DDC1_HW_STATUS;
 	uint32_t DC_I2C_SW_DONE_USING_I2C_REG;
 	uint32_t DC_I2C_SW_USE_I2C_REG_REQ;
 	uint32_t DC_I2C_NO_QUEUED_SW_GO;
@@ -219,6 +223,7 @@ struct dce_i2c_mask {
 struct dce_i2c_registers {
 	uint32_t SETUP;
 	uint32_t SPEED;
+	uint32_t HW_STATUS;
 	uint32_t DC_I2C_ARBITRATION;
 	uint32_t DC_I2C_CONTROL;
 	uint32_t DC_I2C_SW_STATUS;
-- 
2.17.1

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[PATCH 08/24] drm/amd/display: add audio related regs

[Bhawanpreet Lakha]

From: Charlene Liu <charlene.liu@amd.com>

Signed-off-by: Charlene Liu <charlene.liu@amd.com>
Reviewed-by: Chris Park <Chris.Park@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
---
 drivers/gpu/drm/amd/display/dc/dce/dce_audio.c | 4 +---
 drivers/gpu/drm/amd/display/dc/dce/dce_audio.h | 7 +++++++
 2 files changed, 8 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_audio.c b/drivers/gpu/drm/amd/display/dc/dce/dce_audio.c
index 7f6d724686f1..d43d5d924c19 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_audio.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_audio.c
@@ -22,7 +22,7 @@
  * Authors: AMD
  *
  */
-
+#include "../dc.h"
 #include "reg_helper.h"
 #include "dce_audio.h"
 #include "dce/dce_11_0_d.h"
@@ -841,8 +841,6 @@ void dce_aud_wall_dto_setup(
 		REG_UPDATE(DCCG_AUDIO_DTO_SOURCE,
 				DCCG_AUDIO_DTO_SEL, 1);
 
-		REG_UPDATE(DCCG_AUDIO_DTO_SOURCE,
-			DCCG_AUDIO_DTO_SEL, 1);
 			/* DCCG_AUDIO_DTO2_USE_512FBR_DTO, 1)
 			 * Select 512fs for DP TODO: web register definition
 			 * does not match register header file
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_audio.h b/drivers/gpu/drm/amd/display/dc/dce/dce_audio.h
index 0dc5ff137c7a..a0d5724aab31 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_audio.h
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_audio.h
@@ -49,6 +49,8 @@
 		SF(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_SOURCE_SEL, mask_sh),\
 		SF(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO_SEL, mask_sh),\
 		SF(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO2_USE_512FBR_DTO, mask_sh),\
+		SF(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_USE_512FBR_DTO, mask_sh),\
+		SF(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO1_USE_512FBR_DTO, mask_sh),\
 		SF(DCCG_AUDIO_DTO0_MODULE, DCCG_AUDIO_DTO0_MODULE, mask_sh),\
 		SF(DCCG_AUDIO_DTO0_PHASE, DCCG_AUDIO_DTO0_PHASE, mask_sh),\
 		SF(DCCG_AUDIO_DTO1_MODULE, DCCG_AUDIO_DTO1_MODULE, mask_sh),\
@@ -95,6 +97,8 @@ struct dce_audio_shift {
 	uint8_t DCCG_AUDIO_DTO1_MODULE;
 	uint8_t DCCG_AUDIO_DTO1_PHASE;
 	uint8_t DCCG_AUDIO_DTO2_USE_512FBR_DTO;
+	uint32_t DCCG_AUDIO_DTO0_USE_512FBR_DTO;
+	uint32_t DCCG_AUDIO_DTO1_USE_512FBR_DTO;
 };
 
 struct dce_aduio_mask {
@@ -112,6 +116,9 @@ struct dce_aduio_mask {
 	uint32_t DCCG_AUDIO_DTO1_MODULE;
 	uint32_t DCCG_AUDIO_DTO1_PHASE;
 	uint32_t DCCG_AUDIO_DTO2_USE_512FBR_DTO;
+	uint32_t DCCG_AUDIO_DTO0_USE_512FBR_DTO;
+	uint32_t DCCG_AUDIO_DTO1_USE_512FBR_DTO;
+
 };
 
 struct dce_audio {
-- 
2.17.1

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[PATCH 09/24] drm/amd/display: Use macro for invalid OPP ID

[Bhawanpreet Lakha]

From: Wesley Chalmers <Wesley.Chalmers@amd.com>

[WHY]
This is meant to make it clearer that 0xf is not a valid OPP ID, and
that code making use of OPP IDs should not accept this value.

Signed-off-by: Wesley Chalmers <Wesley.Chalmers@amd.com>
Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
---
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c         | 4 ++--
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 4 ++--
 drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h              | 2 ++
 3 files changed, 6 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c
index 54b219a710d8..aea2b63db137 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c
@@ -63,7 +63,7 @@ void hubp1_set_blank(struct hubp *hubp, bool blank)
 		}
 
 		hubp->mpcc_id = 0xf;
-		hubp->opp_id = 0xf;
+		hubp->opp_id = OPP_ID_INVALID;
 	}
 }
 
@@ -1226,7 +1226,7 @@ void dcn10_hubp_construct(
 	hubp1->hubp_shift = hubp_shift;
 	hubp1->hubp_mask = hubp_mask;
 	hubp1->base.inst = inst;
-	hubp1->base.opp_id = 0xf;
+	hubp1->base.opp_id = OPP_ID_INVALID;
 	hubp1->base.mpcc_id = 0xf;
 }
 
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index 821a280eb481..d9edf7f84cfa 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -1025,7 +1025,7 @@ static void dcn10_init_pipes(struct dc *dc, struct dc_state *context)
 		pipe_ctx->plane_res.dpp = dpp;
 		pipe_ctx->plane_res.mpcc_inst = dpp->inst;
 		hubp->mpcc_id = dpp->inst;
-		hubp->opp_id = 0xf;
+		hubp->opp_id = OPP_ID_INVALID;
 		hubp->power_gated = false;
 
 		dc->res_pool->opps[i]->mpc_tree_params.opp_id = dc->res_pool->opps[i]->inst;
@@ -2371,7 +2371,7 @@ static void dcn10_apply_ctx_for_surface(
 		if (pipe_ctx->plane_state && !old_pipe_ctx->plane_state) {
 			if (old_pipe_ctx->stream_res.tg == tg &&
 			    old_pipe_ctx->plane_res.hubp &&
-			    old_pipe_ctx->plane_res.hubp->opp_id != 0xf)
+			    old_pipe_ctx->plane_res.hubp->opp_id != OPP_ID_INVALID)
 				dcn10_disable_plane(dc, old_pipe_ctx);
 		}
 
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h b/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h
index 455df4999797..5420ad2da96f 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h
@@ -28,6 +28,8 @@
 
 #include "mem_input.h"
 
+#define OPP_ID_INVALID 0xf
+
 
 enum cursor_pitch {
 	CURSOR_PITCH_64_PIXELS = 0,
-- 
2.17.1

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[PATCH 10/24] drm/amd/display: Rework CRTC color management

[Bhawanpreet Lakha]

From: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>

[Why]
To prepare for the upcoming DRM plane color management properties
we need to correct a lot of wrong behavior and assumptions made for
CRTC color management.

The documentation added by this commit in amdgpu_dm_color explains
how the HW color pipeline works and its limitations with the DRM
interface.

The current implementation does the following wrong:
- Implicit sRGB DGM when no CRTC DGM is set
- Implicit sRGB RGM when no CRTC RGM is set
- No way to specify a non-linear DGM matrix that produces correct output
- No way to specify a correct RGM when a linear DGM is used

We had workarounds for passing kms_color tests but not all of the
behavior we had wrong was covered by these tests (especially when
it comes to non-linear DGM). Testing both DGM and RGM at the same time
isn't something kms_color tests well either.

[How]
The specifics for how color management works in AMDGPU and the new
behavior can be found by reading the documentation added to
amdgpu_dm_color.c from this patch.

All of the incorrect cases from the old implementation have been
addressed for the atomic interface, but there still a few TODOs for
the legacy one.

Note: this does cause regressions for kms_color@pipe-a-ctm-* over HDMI.

The result looks correct from visual inspection but the CRC no longer
matches. For reference, the test was previously doing the following:

linear degamma -> CTM -> sRGB regamma -> RGB to YUV (709) -> ...

Now the test is doing:

linear degamma -> CTM -> linear regamma -> RGB to YUV (709) -> ...

Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Reviewed-by: Sun peng Li <Sunpeng.Li@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
---
 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c |  32 +-
 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h |  10 +-
 .../amd/display/amdgpu_dm/amdgpu_dm_color.c   | 473 ++++++++++++------
 3 files changed, 356 insertions(+), 159 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 36ee8fe52f38..d267a9cc840f 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -2930,6 +2930,7 @@ static int fill_dc_plane_attributes(struct amdgpu_device *adev,
 				    struct drm_plane_state *plane_state,
 				    struct drm_crtc_state *crtc_state)
 {
+	struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(crtc_state);
 	const struct amdgpu_framebuffer *amdgpu_fb =
 		to_amdgpu_framebuffer(plane_state->fb);
 	struct dc_scaling_info scaling_info;
@@ -2974,13 +2975,11 @@ static int fill_dc_plane_attributes(struct amdgpu_device *adev,
 	 * Always set input transfer function, since plane state is refreshed
 	 * every time.
 	 */
-	ret = amdgpu_dm_set_degamma_lut(crtc_state, dc_plane_state);
-	if (ret) {
-		dc_transfer_func_release(dc_plane_state->in_transfer_func);
-		dc_plane_state->in_transfer_func = NULL;
-	}
+	ret = amdgpu_dm_update_plane_color_mgmt(dm_crtc_state, dc_plane_state);
+	if (ret)
+		return ret;
 
-	return ret;
+	return 0;
 }
 
 static void update_stream_scaling_settings(const struct drm_display_mode *mode,
@@ -3552,6 +3551,8 @@ dm_crtc_duplicate_state(struct drm_crtc *crtc)
 	state->vrr_supported = cur->vrr_supported;
 	state->freesync_config = cur->freesync_config;
 	state->crc_enabled = cur->crc_enabled;
+	state->cm_has_degamma = cur->cm_has_degamma;
+	state->cm_is_degamma_srgb = cur->cm_is_degamma_srgb;
 
 	/* TODO Duplicate dc_stream after objects are stream object is flattened */
 
@@ -5595,8 +5596,18 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
 			bundle->stream_update.dst = acrtc_state->stream->dst;
 		}
 
-		if (new_pcrtc_state->color_mgmt_changed)
-			bundle->stream_update.out_transfer_func = acrtc_state->stream->out_transfer_func;
+		if (new_pcrtc_state->color_mgmt_changed) {
+			/*
+			 * TODO: This isn't fully correct since we've actually
+			 * already modified the stream in place.
+			 */
+			bundle->stream_update.gamut_remap =
+				&acrtc_state->stream->gamut_remap_matrix;
+			bundle->stream_update.output_csc_transform =
+				&acrtc_state->stream->csc_color_matrix;
+			bundle->stream_update.out_transfer_func =
+				acrtc_state->stream->out_transfer_func;
+		}
 
 		acrtc_state->stream->abm_level = acrtc_state->abm_level;
 		if (acrtc_state->abm_level != dm_old_crtc_state->abm_level)
@@ -6426,10 +6437,9 @@ static int dm_update_crtc_state(struct amdgpu_display_manager *dm,
 	 */
 	if (dm_new_crtc_state->base.color_mgmt_changed ||
 	    drm_atomic_crtc_needs_modeset(new_crtc_state)) {
-		ret = amdgpu_dm_set_regamma_lut(dm_new_crtc_state);
+		ret = amdgpu_dm_update_crtc_color_mgmt(dm_new_crtc_state);
 		if (ret)
 			goto fail;
-		amdgpu_dm_set_ctm(dm_new_crtc_state);
 	}
 
 	/* Update Freesync settings. */
@@ -6732,6 +6742,8 @@ dm_determine_update_type_for_commit(struct amdgpu_display_manager *dm,
 						new_dm_plane_state->dc_state->in_transfer_func;
 				stream_update.gamut_remap =
 						&new_dm_crtc_state->stream->gamut_remap_matrix;
+				stream_update.output_csc_transform =
+						&new_dm_crtc_state->stream->csc_color_matrix;
 				stream_update.out_transfer_func =
 						new_dm_crtc_state->stream->out_transfer_func;
 			}
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
index 3395f2e4d564..5a0719418353 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
@@ -271,6 +271,9 @@ struct dm_crtc_state {
 	struct drm_crtc_state base;
 	struct dc_stream_state *stream;
 
+	bool cm_has_degamma;
+	bool cm_is_degamma_srgb;
+
 	int active_planes;
 	bool interrupts_enabled;
 
@@ -361,10 +364,9 @@ void amdgpu_dm_crtc_handle_crc_irq(struct drm_crtc *crtc);
 #define MAX_COLOR_LEGACY_LUT_ENTRIES 256
 
 void amdgpu_dm_init_color_mod(void);
-int amdgpu_dm_set_degamma_lut(struct drm_crtc_state *crtc_state,
-			      struct dc_plane_state *dc_plane_state);
-void amdgpu_dm_set_ctm(struct dm_crtc_state *crtc);
-int amdgpu_dm_set_regamma_lut(struct dm_crtc_state *crtc);
+int amdgpu_dm_update_crtc_color_mgmt(struct dm_crtc_state *crtc);
+int amdgpu_dm_update_plane_color_mgmt(struct dm_crtc_state *crtc,
+				      struct dc_plane_state *dc_plane_state);
 
 extern const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs;
 
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
index 7258c992a2bf..b43bb7f90e4e 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
@@ -27,6 +27,47 @@
 #include "amdgpu_dm.h"
 #include "dc.h"
 #include "modules/color/color_gamma.h"
+#include "basics/conversion.h"
+
+/*
+ * The DC interface to HW gives us the following color management blocks
+ * per pipe (surface):
+ *
+ * - Input gamma LUT (de-normalized)
+ * - Input CSC (normalized)
+ * - Surface degamma LUT (normalized)
+ * - Surface CSC (normalized)
+ * - Surface regamma LUT (normalized)
+ * - Output CSC (normalized)
+ *
+ * But these aren't a direct mapping to DRM color properties. The current DRM
+ * interface exposes CRTC degamma, CRTC CTM and CRTC regamma while our hardware
+ * is essentially giving:
+ *
+ * Plane CTM -> Plane degamma -> Plane CTM -> Plane regamma -> Plane CTM
+ *
+ * The input gamma LUT block isn't really applicable here since it operates
+ * on the actual input data itself rather than the HW fp representation. The
+ * input and output CSC blocks are technically available to use as part of
+ * the DC interface but are typically used internally by DC for conversions
+ * between color spaces. These could be blended together with user
+ * adjustments in the future but for now these should remain untouched.
+ *
+ * The pipe blending also happens after these blocks so we don't actually
+ * support any CRTC props with correct blending with multiple planes - but we
+ * can still support CRTC color management properties in DM in most single
+ * plane cases correctly with clever management of the DC interface in DM.
+ *
+ * As per DRM documentation, blocks should be in hardware bypass when their
+ * respective property is set to NULL. A linear DGM/RGM LUT should also
+ * considered as putting the respective block into bypass mode.
+ *
+ * This means that the following
+ * configuration is assumed to be the default:
+ *
+ * Plane DGM Bypass -> Plane CTM Bypass -> Plane RGM Bypass -> ...
+ * CRTC DGM Bypass -> CRTC CTM Bypass -> CRTC RGM Bypass
+ */
 
 #define MAX_DRM_LUT_VALUE 0xFFFF
 
@@ -41,6 +82,13 @@ void amdgpu_dm_init_color_mod(void)
 	setup_x_points_distribution();
 }
 
+/* Extracts the DRM lut and lut size from a blob. */
+static const struct drm_color_lut *
+__extract_blob_lut(const struct drm_property_blob *blob, uint32_t *size)
+{
+	*size = blob ? drm_color_lut_size(blob) : 0;
+	return blob ? (struct drm_color_lut *)blob->data : NULL;
+}
 
 /*
  * Return true if the given lut is a linear mapping of values, i.e. it acts
@@ -50,7 +98,7 @@ void amdgpu_dm_init_color_mod(void)
  * f(a) = (0xFF00/MAX_COLOR_LUT_ENTRIES-1)a; for integer a in
  *                                           [0, MAX_COLOR_LUT_ENTRIES)
  */
-static bool __is_lut_linear(struct drm_color_lut *lut, uint32_t size)
+static bool __is_lut_linear(const struct drm_color_lut *lut, uint32_t size)
 {
 	int i;
 	uint32_t expected;
@@ -75,9 +123,8 @@ static bool __is_lut_linear(struct drm_color_lut *lut, uint32_t size)
  * Convert the drm_color_lut to dc_gamma. The conversion depends on the size
  * of the lut - whether or not it's legacy.
  */
-static void __drm_lut_to_dc_gamma(struct drm_color_lut *lut,
-				  struct dc_gamma *gamma,
-				  bool is_legacy)
+static void __drm_lut_to_dc_gamma(const struct drm_color_lut *lut,
+				  struct dc_gamma *gamma, bool is_legacy)
 {
 	uint32_t r, g, b;
 	int i;
@@ -107,103 +154,16 @@ static void __drm_lut_to_dc_gamma(struct drm_color_lut *lut,
 	}
 }
 
-/**
- * amdgpu_dm_set_regamma_lut: Set regamma lut for the given CRTC.
- * @crtc: amdgpu_dm crtc state
- *
- * Update the underlying dc_stream_state's output transfer function (OTF) in
- * preparation for hardware commit. If no lut is specified by user, we default
- * to SRGB.
- *
- * RETURNS:
- * 0 on success, -ENOMEM if memory cannot be allocated to calculate the OTF.
- */
-int amdgpu_dm_set_regamma_lut(struct dm_crtc_state *crtc)
-{
-	struct drm_property_blob *blob = crtc->base.gamma_lut;
-	struct dc_stream_state *stream = crtc->stream;
-	struct amdgpu_device *adev = (struct amdgpu_device *)
-		crtc->base.state->dev->dev_private;
-	struct drm_color_lut *lut;
-	uint32_t lut_size;
-	struct dc_gamma *gamma = NULL;
-	enum dc_transfer_func_type old_type = stream->out_transfer_func->type;
-
-	bool ret;
-
-	if (!blob && adev->asic_type <= CHIP_RAVEN) {
-		/* By default, use the SRGB predefined curve.*/
-		stream->out_transfer_func->type = TF_TYPE_PREDEFINED;
-		stream->out_transfer_func->tf = TRANSFER_FUNCTION_SRGB;
-		return 0;
-	}
-
-	if (blob) {
-		lut = (struct drm_color_lut *)blob->data;
-		lut_size = blob->length / sizeof(struct drm_color_lut);
-
-		gamma = dc_create_gamma();
-		if (!gamma)
-			return -ENOMEM;
-
-		gamma->num_entries = lut_size;
-		if (gamma->num_entries == MAX_COLOR_LEGACY_LUT_ENTRIES)
-			gamma->type = GAMMA_RGB_256;
-		else if (gamma->num_entries == MAX_COLOR_LUT_ENTRIES)
-			gamma->type = GAMMA_CS_TFM_1D;
-		else {
-			/* Invalid lut size */
-			dc_gamma_release(&gamma);
-			return -EINVAL;
-		}
-
-		/* Convert drm_lut into dc_gamma */
-		__drm_lut_to_dc_gamma(lut, gamma, gamma->type == GAMMA_RGB_256);
-	}
-
-	/* predefined gamma ROM only exist for RAVEN and pre-RAVEN ASIC,
-	 * set canRomBeUsed accordingly
-	 */
-	stream->out_transfer_func->type = TF_TYPE_DISTRIBUTED_POINTS;
-	ret = mod_color_calculate_regamma_params(stream->out_transfer_func,
-			gamma, true, adev->asic_type <= CHIP_RAVEN, NULL);
-
-	if (gamma)
-		dc_gamma_release(&gamma);
-
-	if (!ret) {
-		stream->out_transfer_func->type = old_type;
-		DRM_ERROR("Out of memory when calculating regamma params\n");
-		return -ENOMEM;
-	}
-
-	return 0;
-}
-
-/**
- * amdgpu_dm_set_ctm: Set the color transform matrix for the given CRTC.
- * @crtc: amdgpu_dm crtc state
- *
- * Update the underlying dc_stream_state's gamut remap matrix in preparation
- * for hardware commit. If no matrix is specified by user, gamut remap will be
- * disabled.
+/*
+ * Converts a DRM CTM to a DC CSC float matrix.
+ * The matrix needs to be a 3x4 (12 entry) matrix.
  */
-void amdgpu_dm_set_ctm(struct dm_crtc_state *crtc)
+static void __drm_ctm_to_dc_matrix(const struct drm_color_ctm *ctm,
+				   struct fixed31_32 *matrix)
 {
-
-	struct drm_property_blob *blob = crtc->base.ctm;
-	struct dc_stream_state *stream = crtc->stream;
-	struct drm_color_ctm *ctm;
 	int64_t val;
 	int i;
 
-	if (!blob) {
-		stream->gamut_remap_matrix.enable_remap = false;
-		return;
-	}
-
-	stream->gamut_remap_matrix.enable_remap = true;
-	ctm = (struct drm_color_ctm *)blob->data;
 	/*
 	 * DRM gives a 3x3 matrix, but DC wants 3x4. Assuming we're operating
 	 * with homogeneous coordinates, augment the matrix with 0's.
@@ -215,83 +175,306 @@ void amdgpu_dm_set_ctm(struct dm_crtc_state *crtc)
 	for (i = 0; i < 12; i++) {
 		/* Skip 4th element */
 		if (i % 4 == 3) {
-			stream->gamut_remap_matrix.matrix[i] = dc_fixpt_zero;
+			matrix[i] = dc_fixpt_zero;
 			continue;
 		}
 
 		/* gamut_remap_matrix[i] = ctm[i - floor(i/4)] */
-		val = ctm->matrix[i - (i/4)];
+		val = ctm->matrix[i - (i / 4)];
 		/* If negative, convert to 2's complement. */
 		if (val & (1ULL << 63))
 			val = -(val & ~(1ULL << 63));
 
-		stream->gamut_remap_matrix.matrix[i].value = val;
+		matrix[i].value = val;
 	}
 }
 
+/* Calculates the legacy transfer function - only for sRGB input space. */
+static int __set_legacy_tf(struct dc_transfer_func *func,
+			   const struct drm_color_lut *lut, uint32_t lut_size,
+			   bool has_rom)
+{
+	struct dc_gamma *gamma = NULL;
+	bool res;
 
-/**
- * amdgpu_dm_set_degamma_lut: Set degamma lut for the given CRTC.
- * @crtc: amdgpu_dm crtc state
- *
- * Update the underlying dc_stream_state's input transfer function (ITF) in
- * preparation for hardware commit. If no lut is specified by user, we default
- * to SRGB degamma.
- *
- * We support degamma bypass, predefined SRGB, and custom degamma
- *
- * RETURNS:
- * 0 on success
- * -EINVAL if crtc_state has a degamma_lut of invalid size
- * -ENOMEM if gamma allocation fails
- */
-int amdgpu_dm_set_degamma_lut(struct drm_crtc_state *crtc_state,
-			      struct dc_plane_state *dc_plane_state)
+	ASSERT(lut && lut_size == MAX_COLOR_LEGACY_LUT_ENTRIES);
+
+	gamma = dc_create_gamma();
+	if (!gamma)
+		return -ENOMEM;
+
+	gamma->type = GAMMA_RGB_256;
+	gamma->num_entries = lut_size;
+	__drm_lut_to_dc_gamma(lut, gamma, true);
+
+	res = mod_color_calculate_regamma_params(func, gamma, true, has_rom,
+						 NULL);
+
+	return res ? 0 : -ENOMEM;
+}
+
+/* Calculates the output transfer function based on expected input space. */
+static int __set_output_tf(struct dc_transfer_func *func,
+			   const struct drm_color_lut *lut, uint32_t lut_size,
+			   bool has_rom)
 {
-	struct drm_property_blob *blob = crtc_state->degamma_lut;
-	struct drm_color_lut *lut;
-	uint32_t lut_size;
-	struct dc_gamma *gamma;
-	bool ret;
-
-	if (!blob) {
-		/* Default to SRGB */
-		dc_plane_state->in_transfer_func->type = TF_TYPE_PREDEFINED;
-		dc_plane_state->in_transfer_func->tf = TRANSFER_FUNCTION_SRGB;
-		return 0;
-	}
+	struct dc_gamma *gamma = NULL;
+	bool res;
 
-	lut = (struct drm_color_lut *)blob->data;
-	if (__is_lut_linear(lut, MAX_COLOR_LUT_ENTRIES)) {
-		dc_plane_state->in_transfer_func->type = TF_TYPE_BYPASS;
-		dc_plane_state->in_transfer_func->tf = TRANSFER_FUNCTION_LINEAR;
-		return 0;
-	}
+	ASSERT(lut && lut_size == MAX_COLOR_LUT_ENTRIES);
 
 	gamma = dc_create_gamma();
 	if (!gamma)
 		return -ENOMEM;
 
-	lut_size = blob->length / sizeof(struct drm_color_lut);
 	gamma->num_entries = lut_size;
-	if (gamma->num_entries == MAX_COLOR_LUT_ENTRIES)
+	__drm_lut_to_dc_gamma(lut, gamma, false);
+
+	if (func->tf == TRANSFER_FUNCTION_LINEAR) {
+		/*
+		 * Color module doesn't like calculating regamma params
+		 * on top of a linear input. But degamma params can be used
+		 * instead to simulate this.
+		 */
 		gamma->type = GAMMA_CUSTOM;
-	else {
-		dc_gamma_release(&gamma);
-		return -EINVAL;
+		res = mod_color_calculate_degamma_params(func, gamma, true);
+	} else {
+		/*
+		 * Assume sRGB. The actual mapping will depend on whether the
+		 * input was legacy or not.
+		 */
+		gamma->type = GAMMA_CS_TFM_1D;
+		res = mod_color_calculate_regamma_params(func, gamma, false,
+							 has_rom, NULL);
 	}
 
+	dc_gamma_release(&gamma);
+
+	return res ? 0 : -ENOMEM;
+}
+
+/* Caculates the input transfer function based on expected input space. */
+static int __set_input_tf(struct dc_transfer_func *func,
+			  const struct drm_color_lut *lut, uint32_t lut_size)
+{
+	struct dc_gamma *gamma = NULL;
+	bool res;
+
+	gamma = dc_create_gamma();
+	if (!gamma)
+		return -ENOMEM;
+
+	gamma->type = GAMMA_CUSTOM;
+	gamma->num_entries = lut_size;
+
 	__drm_lut_to_dc_gamma(lut, gamma, false);
 
-	dc_plane_state->in_transfer_func->type = TF_TYPE_DISTRIBUTED_POINTS;
-	ret = mod_color_calculate_degamma_params(dc_plane_state->in_transfer_func, gamma, true);
+	res = mod_color_calculate_degamma_params(func, gamma, true);
 	dc_gamma_release(&gamma);
-	if (!ret) {
-		dc_plane_state->in_transfer_func->type = TF_TYPE_BYPASS;
-		DRM_ERROR("Out of memory when calculating degamma params\n");
-		return -ENOMEM;
+
+	return res ? 0 : -ENOMEM;
+}
+
+/**
+ * amdgpu_dm_update_crtc_color_mgmt: Maps DRM color management to DC stream.
+ * @crtc: amdgpu_dm crtc state
+ *
+ * With no plane level color management properties we're free to use any
+ * of the HW blocks as long as the CRTC CTM always comes before the
+ * CRTC RGM and after the CRTC DGM.
+ *
+ * The CRTC RGM block will be placed in the RGM LUT block if it is non-linear.
+ * The CRTC DGM block will be placed in the DGM LUT block if it is non-linear.
+ * The CRTC CTM will be placed in the gamut remap block if it is non-linear.
+ *
+ * The RGM block is typically more fully featured and accurate across
+ * all ASICs - DCE can't support a custom non-linear CRTC DGM.
+ *
+ * For supporting both plane level color management and CRTC level color
+ * management at once we have to either restrict the usage of CRTC properties
+ * or blend adjustments together.
+ *
+ * Returns 0 on success.
+ */
+int amdgpu_dm_update_crtc_color_mgmt(struct dm_crtc_state *crtc)
+{
+	struct dc_stream_state *stream = crtc->stream;
+	struct amdgpu_device *adev =
+		(struct amdgpu_device *)crtc->base.state->dev->dev_private;
+	bool has_rom = adev->asic_type <= CHIP_RAVEN;
+	struct drm_color_ctm *ctm = NULL;
+	const struct drm_color_lut *degamma_lut, *regamma_lut;
+	uint32_t degamma_size, regamma_size;
+	bool has_regamma, has_degamma;
+	bool is_legacy;
+	int r;
+
+	degamma_lut = __extract_blob_lut(crtc->base.degamma_lut, &degamma_size);
+	if (degamma_lut && degamma_size != MAX_COLOR_LUT_ENTRIES)
+		return -EINVAL;
+
+	regamma_lut = __extract_blob_lut(crtc->base.gamma_lut, &regamma_size);
+	if (regamma_lut && regamma_size != MAX_COLOR_LUT_ENTRIES &&
+	    regamma_size != MAX_COLOR_LEGACY_LUT_ENTRIES)
+		return -EINVAL;
+
+	has_degamma =
+		degamma_lut && !__is_lut_linear(degamma_lut, degamma_size);
+
+	has_regamma =
+		regamma_lut && !__is_lut_linear(regamma_lut, regamma_size);
+
+	is_legacy = regamma_size == MAX_COLOR_LEGACY_LUT_ENTRIES;
+
+	/* Reset all adjustments. */
+	crtc->cm_has_degamma = false;
+	crtc->cm_is_degamma_srgb = false;
+
+	/* Setup regamma and degamma. */
+	if (is_legacy) {
+		/*
+		 * Legacy regamma forces us to use the sRGB RGM as a base.
+		 * This also means we can't use linear DGM since DGM needs
+		 * to use sRGB as a base as well, resulting in incorrect CRTC
+		 * DGM and CRTC CTM.
+		 *
+		 * TODO: Just map this to the standard regamma interface
+		 * instead since this isn't really right. One of the cases
+		 * where this setup currently fails is trying to do an
+		 * inverse color ramp in legacy userspace.
+		 */
+		crtc->cm_is_degamma_srgb = true;
+		stream->out_transfer_func->type = TF_TYPE_DISTRIBUTED_POINTS;
+		stream->out_transfer_func->tf = TRANSFER_FUNCTION_SRGB;
+
+		r = __set_legacy_tf(stream->out_transfer_func, regamma_lut,
+				    regamma_size, has_rom);
+		if (r)
+			return r;
+	} else if (has_regamma) {
+		/* CRTC RGM goes into RGM LUT. */
+		stream->out_transfer_func->type = TF_TYPE_DISTRIBUTED_POINTS;
+		stream->out_transfer_func->tf = TRANSFER_FUNCTION_LINEAR;
+
+		r = __set_output_tf(stream->out_transfer_func, regamma_lut,
+				    regamma_size, has_rom);
+		if (r)
+			return r;
+	} else {
+		/*
+		 * No CRTC RGM means we can just put the block into bypass
+		 * since we don't have any plane level adjustments using it.
+		 */
+		stream->out_transfer_func->type = TF_TYPE_BYPASS;
+		stream->out_transfer_func->tf = TRANSFER_FUNCTION_LINEAR;
+	}
+
+	/*
+	 * CRTC DGM goes into DGM LUT. It would be nice to place it
+	 * into the RGM since it's a more featured block but we'd
+	 * have to place the CTM in the OCSC in that case.
+	 */
+	crtc->cm_has_degamma = has_degamma;
+
+	/* Setup CRTC CTM. */
+	if (crtc->base.ctm) {
+		ctm = (struct drm_color_ctm *)crtc->base.ctm->data;
+
+		/*
+		 * Gamut remapping must be used for gamma correction
+		 * since it comes before the regamma correction.
+		 *
+		 * OCSC could be used for gamma correction, but we'd need to
+		 * blend the adjustments together with the required output
+		 * conversion matrix - so just use the gamut remap block
+		 * for now.
+		 */
+		__drm_ctm_to_dc_matrix(ctm, stream->gamut_remap_matrix.matrix);
+
+		stream->gamut_remap_matrix.enable_remap = true;
+		stream->csc_color_matrix.enable_adjustment = false;
+	} else {
+		/* Bypass CTM. */
+		stream->gamut_remap_matrix.enable_remap = false;
+		stream->csc_color_matrix.enable_adjustment = false;
 	}
 
 	return 0;
 }
 
+/**
+ * amdgpu_dm_update_plane_color_mgmt: Maps DRM color management to DC plane.
+ * @crtc: amdgpu_dm crtc state
+ * @ dc_plane_state: target DC surface
+ *
+ * Update the underlying dc_stream_state's input transfer function (ITF) in
+ * preparation for hardware commit. The transfer function used depends on
+ * the prepartion done on the stream for color management.
+ *
+ * Returns 0 on success.
+ */
+int amdgpu_dm_update_plane_color_mgmt(struct dm_crtc_state *crtc,
+				      struct dc_plane_state *dc_plane_state)
+{
+	const struct drm_color_lut *degamma_lut;
+	uint32_t degamma_size;
+	int r;
+
+	if (crtc->cm_has_degamma) {
+		degamma_lut = __extract_blob_lut(crtc->base.degamma_lut,
+						 &degamma_size);
+		ASSERT(degamma_size == MAX_COLOR_LUT_ENTRIES);
+
+		dc_plane_state->in_transfer_func->type =
+			TF_TYPE_DISTRIBUTED_POINTS;
+
+		/*
+		 * This case isn't fully correct, but also fairly
+		 * uncommon. This is userspace trying to use a
+		 * legacy gamma LUT + atomic degamma LUT
+		 * at the same time.
+		 *
+		 * Legacy gamma requires the input to be in linear
+		 * space, so that means we need to apply an sRGB
+		 * degamma. But color module also doesn't support
+		 * a user ramp in this case so the degamma will
+		 * be lost.
+		 *
+		 * Even if we did support it, it's still not right:
+		 *
+		 * Input -> CRTC DGM -> sRGB DGM -> CRTC CTM ->
+		 * sRGB RGM -> CRTC RGM -> Output
+		 *
+		 * The CSC will be done in the wrong space since
+		 * we're applying an sRGB DGM on top of the CRTC
+		 * DGM.
+		 *
+		 * TODO: Don't use the legacy gamma interface and just
+		 * map these to the atomic one instead.
+		 */
+		if (crtc->cm_is_degamma_srgb)
+			dc_plane_state->in_transfer_func->tf =
+				TRANSFER_FUNCTION_SRGB;
+		else
+			dc_plane_state->in_transfer_func->tf =
+				TRANSFER_FUNCTION_LINEAR;
+
+		r = __set_input_tf(dc_plane_state->in_transfer_func,
+				   degamma_lut, degamma_size);
+		if (r)
+			return r;
+	} else if (crtc->cm_is_degamma_srgb) {
+		/*
+		 * For legacy gamma support we need the regamma input
+		 * in linear space. Assume that the input is sRGB.
+		 */
+		dc_plane_state->in_transfer_func->type = TF_TYPE_PREDEFINED;
+		dc_plane_state->in_transfer_func->tf = TRANSFER_FUNCTION_SRGB;
+	} else {
+		/* ...Otherwise we can just bypass the DGM block. */
+		dc_plane_state->in_transfer_func->type = TF_TYPE_BYPASS;
+		dc_plane_state->in_transfer_func->tf = TRANSFER_FUNCTION_LINEAR;
+	}
+
+	return 0;
+}
-- 
2.17.1

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[PATCH 11/24] drm/amd/display: fix issue with eDP not detected on driver load

[Bhawanpreet Lakha]

From: Anthony Koo <Anthony.Koo@amd.com>

[Why]
HPD not going to be high if Panel VDD is off
And all AUX transaction will fail :(

[How]
1. Power on VDD before attempting detection if it isn't already on
2. Improve the robustness by having a retry mechanism on the
first DPCD read after VDD on. If a particular board always holds
HPD high incorrectly, the AUX access may fail, so we can retry
in those scenarios. This change would only improve logic
since it prevents AUX failure leading to bad resolution on internal
panel.
3. We should never need to re-detect internal panel, so logic
is re-arranged a bit to skip earlier.

Signed-off-by: Anthony Koo <Anthony.Koo@amd.com>
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
---
 drivers/gpu/drm/amd/display/dc/core/dc_link.c | 42 ++++++++++++++-----
 1 file changed, 32 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index c9e0b126777b..c5dc809f17d6 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -217,8 +217,11 @@ bool dc_link_detect_sink(struct dc_link *link, enum dc_connection_type *type)
 		return true;
 	}
 
-	if (link->connector_signal == SIGNAL_TYPE_EDP)
+	if (link->connector_signal == SIGNAL_TYPE_EDP) {
+		/*in case it is not on*/
+		link->dc->hwss.edp_power_control(link, true);
 		link->dc->hwss.edp_wait_for_hpd_ready(link, true);
+	}
 
 	/* todo: may need to lock gpio access */
 	hpd_pin = get_hpd_gpio(link->ctx->dc_bios, link->link_id, link->ctx->gpio_service);
@@ -520,11 +523,31 @@ static void read_edp_current_link_settings_on_detect(struct dc_link *link)
 	union lane_count_set lane_count_set = { {0} };
 	uint8_t link_bw_set;
 	uint8_t link_rate_set;
+	uint32_t read_dpcd_retry_cnt = 10;
+	enum dc_status status = DC_ERROR_UNEXPECTED;
+	int i;
 
 	// Read DPCD 00101h to find out the number of lanes currently set
-	core_link_read_dpcd(link, DP_LANE_COUNT_SET,
-			&lane_count_set.raw, sizeof(lane_count_set));
-	link->cur_link_settings.lane_count = lane_count_set.bits.LANE_COUNT_SET;
+	for (i = 0; i < read_dpcd_retry_cnt; i++) {
+		status = core_link_read_dpcd(
+				link,
+				DP_LANE_COUNT_SET,
+				&lane_count_set.raw,
+				sizeof(lane_count_set));
+		/* First DPCD read after VDD ON can fail if the particular board
+		 * does not have HPD pin wired correctly. So if DPCD read fails,
+		 * which it should never happen, retry a few times. Target worst
+		 * case scenario of 80 ms.
+		 */
+		if (status == DC_OK) {
+			link->cur_link_settings.lane_count = lane_count_set.bits.LANE_COUNT_SET;
+			break;
+		}
+
+		udelay(8000);
+	}
+
+	ASSERT(status == DC_OK);
 
 	// Read DPCD 00100h to find if standard link rates are set
 	core_link_read_dpcd(link, DP_LINK_BW_SET,
@@ -678,6 +701,11 @@ bool dc_link_detect(struct dc_link *link, enum dc_detect_reason reason)
 	if (dc_is_virtual_signal(link->connector_signal))
 		return false;
 
+	if ((link->connector_signal == SIGNAL_TYPE_LVDS ||
+			link->connector_signal == SIGNAL_TYPE_EDP) &&
+			link->local_sink)
+		return true;
+
 	if (false == dc_link_detect_sink(link, &new_connection_type)) {
 		BREAK_TO_DEBUGGER();
 		return false;
@@ -688,14 +716,8 @@ bool dc_link_detect(struct dc_link *link, enum dc_detect_reason reason)
 		 * up to date, especially if link was powered on by GOP.
 		 */
 		read_edp_current_link_settings_on_detect(link);
-		if (link->local_sink)
-			return true;
 	}
 
-	if (link->connector_signal == SIGNAL_TYPE_LVDS &&
-			link->local_sink)
-		return true;
-
 	prev_sink = link->local_sink;
 	if (prev_sink != NULL) {
 		dc_sink_retain(prev_sink);
-- 
2.17.1

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[PATCH 12/24] drm/amd/display: fix gamma logic breaking driver unload

[Bhawanpreet Lakha]

From: Krunoslav Kovac <Krunoslav.Kovac@amd.com>

Using this logic breaks driver unload, this is a temporary fix
a followup patch will properly fix this

Signed-off-by: Krunoslav Kovac <Krunoslav.Kovac@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
---
 drivers/gpu/drm/amd/display/modules/color/color_gamma.c | 6 ++----
 1 file changed, 2 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/modules/color/color_gamma.c b/drivers/gpu/drm/amd/display/modules/color/color_gamma.c
index 89a65e1d8317..8601d371776e 100644
--- a/drivers/gpu/drm/amd/display/modules/color/color_gamma.c
+++ b/drivers/gpu/drm/amd/display/modules/color/color_gamma.c
@@ -1569,15 +1569,13 @@ bool mod_color_calculate_regamma_params(struct dc_transfer_func *output_tf,
 			output_tf->tf == TRANSFER_FUNCTION_SRGB) {
 		if (ramp == NULL)
 			return true;
-		if ((ramp->is_identity && ramp->type != GAMMA_CS_TFM_1D) ||
-				(!mapUserRamp && ramp->type == GAMMA_RGB_256))
+		if (ramp->is_identity || (!mapUserRamp && ramp->type == GAMMA_RGB_256))
 			return true;
 	}
 
 	output_tf->type = TF_TYPE_DISTRIBUTED_POINTS;
 
-	if (ramp && ramp->type != GAMMA_CS_TFM_1D &&
-			(mapUserRamp || ramp->type != GAMMA_RGB_256)) {
+	if (ramp && (mapUserRamp || ramp->type != GAMMA_RGB_256)) {
 		rgb_user = kvcalloc(ramp->num_entries + _EXTRA_POINTS,
 			    sizeof(*rgb_user),
 			    GFP_KERNEL);
-- 
2.17.1

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[PATCH 13/24] drm/amd/display: 3.2.34

[Bhawanpreet Lakha]

From: Aric Cyr <aric.cyr@amd.com>

Signed-off-by: Aric Cyr <aric.cyr@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
---
 drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index 3f22212437ca..59a9e1ea806d 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -39,7 +39,7 @@
 #include "inc/hw/dmcu.h"
 #include "dml/display_mode_lib.h"
 
-#define DC_VER "3.2.33"
+#define DC_VER "3.2.34"
 
 #define MAX_SURFACES 3
 #define MAX_PLANES 6
-- 
2.17.1

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[PATCH 14/24] drm/amd/display: 3.2.35

[Bhawanpreet Lakha]

From: Aric Cyr <aric.cyr@amd.com>

Signed-off-by: Aric Cyr <aric.cyr@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
---
 drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index 59a9e1ea806d..c4bd9216dd61 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -39,7 +39,7 @@
 #include "inc/hw/dmcu.h"
 #include "dml/display_mode_lib.h"
 
-#define DC_VER "3.2.34"
+#define DC_VER "3.2.35"
 
 #define MAX_SURFACES 3
 #define MAX_PLANES 6
-- 
2.17.1

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[PATCH 15/24] drm/amd/display: Clean up scdc_test_data struct

[Bhawanpreet Lakha]

From: Chris Park <Chris.Park@amd.com>

These are no longer needed, Also added RESERVED bits.

Signed-off-by: Chris Park <Chris.Park@amd.com>
Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
---
 drivers/gpu/drm/amd/display/dc/core/dc_link.c     |  1 -
 drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c | 14 ++++++--------
 2 files changed, 6 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index c5dc809f17d6..9f32ddfde41e 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -3004,4 +3004,3 @@ const struct dc_link_settings *dc_link_get_link_cap(
 		return &link->preferred_link_setting;
 	return &link->verified_link_cap;
 }
-
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c
index f02092a0dc76..94064d8ce303 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c
@@ -91,6 +91,8 @@ union hdmi_scdc_status_flags_data {
 		uint8_t CH2_LOCKED:1;
 		uint8_t RESERVED:4;
 		uint8_t RESERVED2:8;
+		uint8_t RESERVED3:8;
+
 	} fields;
 };
 
@@ -107,14 +109,10 @@ union hdmi_scdc_ced_data {
 		uint8_t CH2_7HIGH:7;
 		uint8_t CH2_VALID:1;
 		uint8_t CHECKSUM:8;
-	} fields;
-};
-
-union hdmi_scdc_test_config_Data {
-	uint8_t byte;
-	struct {
-		uint8_t TEST_READ_REQUEST_DELAY:7;
-		uint8_t TEST_READ_REQUEST: 1;
+		uint8_t RESERVED:8;
+		uint8_t RESERVED2:8;
+		uint8_t RESERVED3:8;
+		uint8_t RESERVED4:4;
 	} fields;
 };
 
-- 
2.17.1

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[PATCH 16/24] drm/amd/display: Remove superflous error message

[Bhawanpreet Lakha]

From: Jordan Lazare <Jordan.Lazare@amd.com>

[Why]
VBios sometimes reports incorrect object type as encoder instead of
connector

[How]
Change error message to debug message

Signed-off-by: Jordan Lazare <Jordan.Lazare@amd.com>
Reviewed-by: Harry Wentland <Harry.Wentland@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
---
 drivers/gpu/drm/amd/display/dc/core/dc_link.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index 9f32ddfde41e..10807fa46ad6 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -1180,7 +1180,7 @@ static bool construct(
 	link->link_id = bios->funcs->get_connector_id(bios, init_params->connector_index);
 
 	if (link->link_id.type != OBJECT_TYPE_CONNECTOR) {
-		dm_error("%s: Invalid Connector ObjectID from Adapter Service for connector index:%d! type %d expected %d\n",
+		dm_output_to_console("%s: Invalid Connector ObjectID from Adapter Service for connector index:%d! type %d expected %d\n",
 			 __func__, init_params->connector_index,
 			 link->link_id.type, OBJECT_TYPE_CONNECTOR);
 		goto create_fail;
-- 
2.17.1

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[PATCH 17/24] drm/amd/display: move vmid determination logic out of dc

[Bhawanpreet Lakha]

From: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>

Currently vmid is decided internally inside dc. This makes it
difficult to use vmid use with external components.

This change moves vmid logic outside dc and allowing vmid to be
passed in as a parameter to DC.

Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
---
 drivers/gpu/drm/amd/display/dc/Makefile       |   4 +-
 .../drm/amd/display/dc/core/dc_vm_helper.c    | 123 ------------------
 drivers/gpu/drm/amd/display/dc/dc.h           |   1 +
 drivers/gpu/drm/amd/display/dc/dc_hw_types.h  |   2 +
 .../gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c |   3 +-
 .../amd/display/dc/dcn10/dcn10_hw_sequencer.c |   3 +-
 drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h  |   3 +-
 drivers/gpu/drm/amd/display/dc/inc/hw/vmid.h  |   1 +
 .../gpu/drm/amd/display/dc/inc/vm_helper.h    |  16 +--
 9 files changed, 13 insertions(+), 143 deletions(-)
 delete mode 100644 drivers/gpu/drm/amd/display/dc/core/dc_vm_helper.c

diff --git a/drivers/gpu/drm/amd/display/dc/Makefile b/drivers/gpu/drm/amd/display/dc/Makefile
index 6da4e4f844b2..f581d5394caa 100644
--- a/drivers/gpu/drm/amd/display/dc/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/Makefile
@@ -41,8 +41,8 @@ AMD_DC = $(addsuffix /Makefile, $(addprefix $(FULL_AMD_DISPLAY_PATH)/dc/,$(DC_LI
 include $(AMD_DC)
 
 DISPLAY_CORE = dc.o dc_link.o dc_resource.o dc_hw_sequencer.o dc_sink.o \
-dc_surface.o dc_link_hwss.o dc_link_dp.o dc_link_ddc.o dc_debug.o dc_stream.o \
-dc_vm_helper.o
+dc_surface.o dc_link_hwss.o dc_link_dp.o dc_link_ddc.o dc_debug.o dc_stream.o
+
 
 AMD_DISPLAY_CORE = $(addprefix $(AMDDALPATH)/dc/core/,$(DISPLAY_CORE))
 
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_vm_helper.c b/drivers/gpu/drm/amd/display/dc/core/dc_vm_helper.c
deleted file mode 100644
index 6ce87b682a32..000000000000
--- a/drivers/gpu/drm/amd/display/dc/core/dc_vm_helper.c
+++ /dev/null
@@ -1,123 +0,0 @@
-/*
- * Copyright 2018 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: AMD
- *
- */
-
-#include "vm_helper.h"
-
-static void mark_vmid_used(struct vm_helper *vm_helper, unsigned int pos, uint8_t hubp_idx)
-{
-	struct vmid_usage vmids = vm_helper->hubp_vmid_usage[hubp_idx];
-
-	vmids.vmid_usage[0] = vmids.vmid_usage[1];
-	vmids.vmid_usage[1] = 1 << pos;
-}
-
-static void add_ptb_to_table(struct vm_helper *vm_helper, unsigned int vmid, uint64_t ptb)
-{
-	vm_helper->ptb_assigned_to_vmid[vmid] = ptb;
-	vm_helper->num_vmids_available--;
-}
-
-static void clear_entry_from_vmid_table(struct vm_helper *vm_helper, unsigned int vmid)
-{
-	vm_helper->ptb_assigned_to_vmid[vmid] = 0;
-	vm_helper->num_vmids_available++;
-}
-
-static void evict_vmids(struct vm_helper *vm_helper)
-{
-	int i;
-	uint16_t ord = 0;
-
-	for (i = 0; i < vm_helper->num_vmid; i++)
-		ord |= vm_helper->hubp_vmid_usage[i].vmid_usage[0] | vm_helper->hubp_vmid_usage[i].vmid_usage[1];
-
-	// At this point any positions with value 0 are unused vmids, evict them
-	for (i = 1; i < vm_helper->num_vmid; i++) {
-		if (ord & (1u << i))
-			clear_entry_from_vmid_table(vm_helper, i);
-	}
-}
-
-// Return value of -1 indicates vmid table unitialized or ptb dne in the table
-static int get_existing_vmid_for_ptb(struct vm_helper *vm_helper, uint64_t ptb)
-{
-	int i;
-
-	for (i = 0; i < vm_helper->num_vmid; i++) {
-		if (vm_helper->ptb_assigned_to_vmid[i] == ptb)
-			return i;
-	}
-
-	return -1;
-}
-
-// Expected to be called only when there's an available vmid
-static int get_next_available_vmid(struct vm_helper *vm_helper)
-{
-	int i;
-
-	for (i = 1; i < vm_helper->num_vmid; i++) {
-		if (vm_helper->ptb_assigned_to_vmid[i] == 0)
-			return i;
-	}
-
-	return -1;
-}
-
-uint8_t get_vmid_for_ptb(struct vm_helper *vm_helper, int64_t ptb, uint8_t hubp_idx)
-{
-	unsigned int vmid = 0;
-	int vmid_exists = -1;
-
-	// Physical address gets vmid 0
-	if (ptb == 0)
-		return 0;
-
-	vmid_exists = get_existing_vmid_for_ptb(vm_helper, ptb);
-
-	if (vmid_exists != -1) {
-		mark_vmid_used(vm_helper, vmid_exists, hubp_idx);
-		vmid = vmid_exists;
-	} else {
-		if (vm_helper->num_vmids_available == 0)
-			evict_vmids(vm_helper);
-
-		vmid = get_next_available_vmid(vm_helper);
-		mark_vmid_used(vm_helper, vmid, hubp_idx);
-		add_ptb_to_table(vm_helper, vmid, ptb);
-	}
-
-	return vmid;
-}
-
-void init_vm_helper(struct vm_helper *vm_helper, unsigned int num_vmid, unsigned int num_hubp)
-{
-	vm_helper->num_vmid = num_vmid;
-	vm_helper->num_hubp = num_hubp;
-	vm_helper->num_vmids_available = num_vmid - 1;
-
-	memset(vm_helper->hubp_vmid_usage, 0, sizeof(vm_helper->hubp_vmid_usage[0]) * MAX_HUBP);
-	memset(vm_helper->ptb_assigned_to_vmid, 0, sizeof(vm_helper->ptb_assigned_to_vmid[0]) * MAX_VMID);
-}
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index c4bd9216dd61..ffd1fe5df99e 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -458,6 +458,7 @@ struct dc_callback_init {
 };
 
 struct dc *dc_create(const struct dc_init_data *init_params);
+int dc_get_vmid_use_vector(struct dc *dc);
 void dc_init_callbacks(struct dc *dc,
 		const struct dc_callback_init *init_params);
 void dc_destroy(struct dc **dc);
diff --git a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
index c91b8aad78c9..479c5f8352f9 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
@@ -99,6 +99,8 @@ struct dc_plane_address {
 	};
 
 	union large_integer page_table_base;
+
+	uint8_t vmid;
 };
 
 struct dc_size {
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c
index aea2b63db137..4cb7fe8b3903 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c
@@ -317,8 +317,7 @@ void hubp1_program_pixel_format(
 bool hubp1_program_surface_flip_and_addr(
 	struct hubp *hubp,
 	const struct dc_plane_address *address,
-	bool flip_immediate,
-	uint8_t vmid)
+	bool flip_immediate)
 {
 	struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
 
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index d9edf7f84cfa..be245d4fe5c2 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -1236,8 +1236,7 @@ static void dcn10_update_plane_addr(const struct dc *dc, struct pipe_ctx *pipe_c
 	pipe_ctx->plane_res.hubp->funcs->hubp_program_surface_flip_and_addr(
 			pipe_ctx->plane_res.hubp,
 			&plane_state->address,
-			plane_state->flip_immediate,
-			0);
+			plane_state->flip_immediate);
 
 	plane_state->status.requested_address = plane_state->address;
 
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h b/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h
index 5420ad2da96f..e4909d21b9f2 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h
@@ -80,8 +80,7 @@ struct hubp_funcs {
 	bool (*hubp_program_surface_flip_and_addr)(
 		struct hubp *hubp,
 		const struct dc_plane_address *address,
-		bool flip_immediate,
-		uint8_t vmid);
+		bool flip_immediate);
 
 	void (*hubp_program_pte_vm)(
 		struct hubp *hubp,
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/vmid.h b/drivers/gpu/drm/amd/display/dc/inc/hw/vmid.h
index 037beb0a2a27..76de0e4284e0 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/vmid.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/vmid.h
@@ -44,6 +44,7 @@ struct dcn_vmid_page_table_config {
 	uint64_t	page_table_end_addr;
 	enum dcn_hubbub_page_table_depth	depth;
 	enum dcn_hubbub_page_table_block_size	block_size;
+	uint64_t	page_table_base_addr;
 };
 
 #endif /* DAL_DC_INC_HW_VMID_H_ */
diff --git a/drivers/gpu/drm/amd/display/dc/inc/vm_helper.h b/drivers/gpu/drm/amd/display/dc/inc/vm_helper.h
index 193407f76a80..8bfcef0a3675 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/vm_helper.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/vm_helper.h
@@ -28,29 +28,21 @@
 
 #include "dc_types.h"
 
-#define MAX_VMID 16
 #define MAX_HUBP 6
 
 struct vmid_usage {
-	uint16_t vmid_usage[2];
+	int vmid_usage[2];
 };
 
 struct vm_helper {
 	unsigned int num_vmid;
-	unsigned int num_hubp;
-	unsigned int num_vmids_available;
-	uint64_t ptb_assigned_to_vmid[MAX_VMID];
 	struct vmid_usage hubp_vmid_usage[MAX_HUBP];
 };
 
-uint8_t get_vmid_for_ptb(
-		struct vm_helper *vm_helper,
-		int64_t ptb,
-		uint8_t pipe_idx);
+void vm_helper_mark_vmid_used(struct vm_helper *vm_helper, unsigned int pos, uint8_t hubp_idx);
 
-void init_vm_helper(
+void vm_helper_init(
 	struct vm_helper *vm_helper,
-	unsigned int num_vmid,
-	unsigned int num_hubp);
+	unsigned int num_vmid);
 
 #endif /* DC_INC_VM_HELPER_H_ */
-- 
2.17.1

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[PATCH 18/24] drm/amd/display: Add Underflow Asserts to dc

[Bhawanpreet Lakha]

From: Thomas Lim <Thomas.Lim@amd.com>

[Why]
For debugging underflow issues it can be useful to have asserts when the
underflow initially occurs.

[How]
Read the underflow status registers after actions that have a high risk
of causing underflow and assert that no underflow occurred. If underflow
occurred, clear the bit.

Signed-off-by: Thomas Lim <Thomas.Lim@amd.com>
Reviewed-by: Eric Yang <eric.yang2@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
---
 drivers/gpu/drm/amd/display/dc/dc.h           |  1 +
 .../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 32 ++++++++++++++++++-
 .../amd/display/dc/dcn10/dcn10_hw_sequencer.h |  2 ++
 .../drm/amd/display/dc/dcn10/dcn10_resource.c |  4 ++-
 .../gpu/drm/amd/display/dc/inc/hw_sequencer.h |  1 +
 5 files changed, 38 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index ffd1fe5df99e..9aa01bf8c64d 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -329,6 +329,7 @@ struct dc_debug_options {
 	int sr_exit_time_ns;
 	int sr_enter_plus_exit_time_ns;
 	int urgent_latency_ns;
+	uint32_t underflow_assert_delay_us;
 	int percent_of_ideal_drambw;
 	int dram_clock_change_latency_ns;
 	bool optimized_watermark;
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index be245d4fe5c2..f334756c1ce3 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -360,6 +360,23 @@ void dcn10_log_hw_state(struct dc *dc,
 	DTN_INFO_END();
 }
 
+bool dcn10_did_underflow_occur(struct dc *dc, struct pipe_ctx *pipe_ctx)
+{
+	struct hubp *hubp = pipe_ctx->plane_res.hubp;
+	struct timing_generator *tg = pipe_ctx->stream_res.tg;
+
+	if (tg->funcs->is_optc_underflow_occurred(tg)) {
+		tg->funcs->clear_optc_underflow(tg);
+		return true;
+	}
+
+	if (hubp->funcs->hubp_get_underflow_status(hubp)) {
+		hubp->funcs->hubp_clear_underflow(hubp);
+		return true;
+	}
+	return false;
+}
+
 static void enable_power_gating_plane(
 	struct dce_hwseq *hws,
 	bool enable)
@@ -2332,6 +2349,7 @@ static void dcn10_apply_ctx_for_surface(
 {
 	int i;
 	struct timing_generator *tg;
+	uint32_t underflow_check_delay_us;
 	bool removed_pipe[4] = { false };
 	bool interdependent_update = false;
 	struct pipe_ctx *top_pipe_to_program =
@@ -2346,11 +2364,22 @@ static void dcn10_apply_ctx_for_surface(
 	interdependent_update = top_pipe_to_program->plane_state &&
 		top_pipe_to_program->plane_state->update_flags.bits.full_update;
 
+	underflow_check_delay_us = dc->debug.underflow_assert_delay_us;
+
+	if (underflow_check_delay_us != 0xFFFFFFFF && dc->hwss.did_underflow_occur)
+		ASSERT(dc->hwss.did_underflow_occur(dc, top_pipe_to_program));
+
 	if (interdependent_update)
 		lock_all_pipes(dc, context, true);
 	else
 		dcn10_pipe_control_lock(dc, top_pipe_to_program, true);
 
+	if (underflow_check_delay_us != 0xFFFFFFFF)
+		udelay(underflow_check_delay_us);
+
+	if (underflow_check_delay_us != 0xFFFFFFFF && dc->hwss.did_underflow_occur)
+		ASSERT(dc->hwss.did_underflow_occur(dc, top_pipe_to_program));
+
 	if (num_planes == 0) {
 		/* OTG blank before remove all front end */
 		dc->hwss.blank_pixel_data(dc, top_pipe_to_program, true);
@@ -3022,7 +3051,8 @@ static const struct hw_sequencer_funcs dcn10_funcs = {
 	.disable_stream_gating = NULL,
 	.enable_stream_gating = NULL,
 	.setup_periodic_interrupt = dcn10_setup_periodic_interrupt,
-	.setup_vupdate_interrupt = dcn10_setup_vupdate_interrupt
+	.setup_vupdate_interrupt = dcn10_setup_vupdate_interrupt,
+	.did_underflow_occur = dcn10_did_underflow_occur
 };
 
 
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h
index ef94d6b15843..d3616b1948cc 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h
@@ -71,6 +71,8 @@ void dcn10_get_hdr_visual_confirm_color(
 		struct pipe_ctx *pipe_ctx,
 		struct tg_color *color);
 
+bool dcn10_did_underflow_occur(struct dc *dc, struct pipe_ctx *pipe_ctx);
+
 void update_dchubp_dpp(
 	struct dc *dc,
 	struct pipe_ctx *pipe_ctx,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
index f6004bc53dce..29fd3cb9422b 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
@@ -560,6 +560,7 @@ static const struct dc_debug_options debug_defaults_drv = {
 		.az_endpoint_mute_only = true,
 		.recovery_enabled = false, /*enable this by default after testing.*/
 		.max_downscale_src_width = 3840,
+		.underflow_assert_delay_us = 0xFFFFFFFF,
 };
 
 static const struct dc_debug_options debug_defaults_diags = {
@@ -569,7 +570,8 @@ static const struct dc_debug_options debug_defaults_diags = {
 		.clock_trace = true,
 		.disable_stutter = true,
 		.disable_pplib_clock_request = true,
-		.disable_pplib_wm_range = true
+		.disable_pplib_wm_range = true,
+		.underflow_assert_delay_us = 0xFFFFFFFF,
 };
 
 static void dcn10_dpp_destroy(struct dpp **dpp)
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
index eb1c12ed026a..dab0168cd5cb 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
@@ -240,6 +240,7 @@ struct hw_sequencer_funcs {
 
 	void (*setup_periodic_interrupt)(struct pipe_ctx *pipe_ctx, enum vline_select vline);
 	void (*setup_vupdate_interrupt)(struct pipe_ctx *pipe_ctx);
+	bool (*did_underflow_occur)(struct dc *dc, struct pipe_ctx *pipe_ctx);
 
 };
 
-- 
2.17.1

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[PATCH 19/24] drm/amd/display: Gamma logic limitations causing unintended use of RAM over ROM.

[Bhawanpreet Lakha]

From: Harmanprit Tatla <harmanprit.tatla@amd.com>

[Why]
Our existing logic in deciding whether to use RAM or ROM
depends on whether we are dealing with an identity gamma ramp.

[How]
In addition to the is_identity flag
a new is_logical_identity flag has been
added. The is_identity flag now denotes
whether the OS gamma is an RGB256 identity
and the new logical identity will inidicate
that the given gamma ramp regardless of its
type is identity.

Signed-off-by: Harmanprit Tatla <harmanprit.tatla@amd.com>
Reviewed-by: Krunoslav Kovac <Krunoslav.Kovac@amd.com>
Acked-by: Anthony Koo <Anthony.Koo@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
---
 drivers/gpu/drm/amd/display/dc/dc_hw_types.h            | 4 ++++
 drivers/gpu/drm/amd/display/modules/color/color_gamma.c | 3 ++-
 2 files changed, 6 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
index 479c5f8352f9..821d4f260764 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
@@ -453,7 +453,11 @@ struct dc_gamma {
 	/* private to DC core */
 	struct dc_context *ctx;
 
+	/* is_identity is used for RGB256 gamma identity which can also be programmed in INPUT_LUT.
+	 * is_logical_identity indicates the given gamma ramp regardless of type is identity.
+	 */
 	bool is_identity;
+	bool is_logical_identity;
 };
 
 /* Used by both ipp amd opp functions*/
diff --git a/drivers/gpu/drm/amd/display/modules/color/color_gamma.c b/drivers/gpu/drm/amd/display/modules/color/color_gamma.c
index 8601d371776e..3f413fb9f2ce 100644
--- a/drivers/gpu/drm/amd/display/modules/color/color_gamma.c
+++ b/drivers/gpu/drm/amd/display/modules/color/color_gamma.c
@@ -1569,7 +1569,8 @@ bool mod_color_calculate_regamma_params(struct dc_transfer_func *output_tf,
 			output_tf->tf == TRANSFER_FUNCTION_SRGB) {
 		if (ramp == NULL)
 			return true;
-		if (ramp->is_identity || (!mapUserRamp && ramp->type == GAMMA_RGB_256))
+		if ((ramp->is_logical_identity) ||
+				(!mapUserRamp && ramp->type == GAMMA_RGB_256))
 			return true;
 	}
 
-- 
2.17.1

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[PATCH 20/24] drm/amd/display: Use stream opp_id instead of hubp

[Bhawanpreet Lakha]

From: Wesley Chalmers <Wesley.Chalmers@amd.com>

[WHY]
By the time output csc matrix is being programmed, stream connection to
OPP has been established, but this information has not been relayed back
to HUBP.

Signed-off-by: Wesley Chalmers <Wesley.Chalmers@amd.com>
Reviewed-by: Anthony Koo <Anthony.Koo@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Acked-by: Krunoslav Kovac <Krunoslav.Kovac@amd.com>
---
 drivers/gpu/drm/amd/display/dc/core/dc.c                  | 2 +-
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 45b542b5d920..bf64a73f1482 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -457,7 +457,7 @@ bool dc_stream_program_csc_matrix(struct dc *dc, struct dc_stream_state *stream)
 					pipes,
 					stream->output_color_space,
 					stream->csc_color_matrix.matrix,
-					pipes->plane_res.hubp ? pipes->plane_res.hubp->opp_id : 0);
+					pipes->stream_res.opp->inst);
 			ret = true;
 		}
 	}
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index f334756c1ce3..d2352949c06e 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -2169,7 +2169,7 @@ void update_dchubp_dpp(
 				pipe_ctx,
 				pipe_ctx->stream->output_color_space,
 				pipe_ctx->stream->csc_color_matrix.matrix,
-				hubp->opp_id);
+				pipe_ctx->stream_res.opp->inst);
 	}
 
 	if (plane_state->update_flags.bits.full_update ||
-- 
2.17.1

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[PATCH 21/24] drm/amd/display: S3 Resume time increase after decoupling DPMS from fast boot

[Bhawanpreet Lakha]

From: SivapiriyanKumarasamy <sivapiriyan.kumarasamy@amd.com>

[Why]
We incorrectly began powering down the display at boot/resume whenever
fast boot was not possible. This should not be done in the case where there
exists a stream for the eDP since this implies that we want to turn it on.

[How]
Add check for eDP stream to decide whether to power off edp.

Signed-off-by: SivapiriyanKumarasamy <sivapiriyan.kumarasamy@amd.com>
Reviewed-by: Anthony Koo <Anthony.Koo@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Acked-by: Reza Amini <Reza.Amini@amd.com>
---
 .../display/dc/dce110/dce110_hw_sequencer.c   | 35 ++++++++++++++-----
 1 file changed, 26 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
index 3042741b165a..2a7ac452d458 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
@@ -1507,6 +1507,18 @@ static void disable_vga_and_power_gate_all_controllers(
 	}
 }
 
+
+static struct dc_stream_state *get_edp_stream(struct dc_state *context)
+{
+	int i;
+
+	for (i = 0; i < context->stream_count; i++) {
+		if (context->streams[i]->signal == SIGNAL_TYPE_EDP)
+			return context->streams[i];
+	}
+	return NULL;
+}
+
 static struct dc_link *get_edp_link(struct dc *dc)
 {
 	int i;
@@ -1550,12 +1562,16 @@ void dce110_enable_accelerated_mode(struct dc *dc, struct dc_state *context)
 	int i;
 	struct dc_link *edp_link_with_sink = get_edp_link_with_sink(dc, context);
 	struct dc_link *edp_link = get_edp_link(dc);
+	struct dc_stream_state *edp_stream = NULL;
 	bool can_apply_edp_fast_boot = false;
 	bool can_apply_seamless_boot = false;
+	bool keep_edp_vdd_on = false;
 
 	if (dc->hwss.init_pipes)
 		dc->hwss.init_pipes(dc, context);
 
+	edp_stream = get_edp_stream(context);
+
 	// Check fastboot support, disable on DCE8 because of blank screens
 	if (edp_link && dc->ctx->dce_version != DCE_VERSION_8_0 &&
 		    dc->ctx->dce_version != DCE_VERSION_8_1 &&
@@ -1563,15 +1579,16 @@ void dce110_enable_accelerated_mode(struct dc *dc, struct dc_state *context)
 
 		// enable fastboot if backend is enabled on eDP
 		if (edp_link->link_enc->funcs->is_dig_enabled(edp_link->link_enc)) {
-			/* Find eDP stream and set optimization flag */
-			for (i = 0; i < context->stream_count; i++) {
-				if (context->streams[i]->signal == SIGNAL_TYPE_EDP) {
-					context->streams[i]->apply_edp_fast_boot_optimization = true;
-					can_apply_edp_fast_boot = true;
-					break;
-				}
+			/* Set optimization flag on eDP stream*/
+			if (edp_stream) {
+				edp_stream->apply_edp_fast_boot_optimization = true;
+				can_apply_edp_fast_boot = true;
 			}
 		}
+
+		// We are trying to enable eDP, don't power down VDD
+		if (edp_stream)
+			keep_edp_vdd_on = true;
 	}
 
 	// Check seamless boot support
@@ -1586,14 +1603,14 @@ void dce110_enable_accelerated_mode(struct dc *dc, struct dc_state *context)
 	 * it should get turned off
 	 */
 	if (!can_apply_edp_fast_boot && !can_apply_seamless_boot) {
-		if (edp_link_with_sink) {
+		if (edp_link_with_sink && !keep_edp_vdd_on) {
 			/*turn off backlight before DP_blank and encoder powered down*/
 			dc->hwss.edp_backlight_control(edp_link_with_sink, false);
 		}
 		/*resume from S3, no vbios posting, no need to power down again*/
 		power_down_all_hw_blocks(dc);
 		disable_vga_and_power_gate_all_controllers(dc);
-		if (edp_link_with_sink)
+		if (edp_link_with_sink && !keep_edp_vdd_on)
 			dc->hwss.edp_power_control(edp_link_with_sink, false);
 	}
 	bios_set_scratch_acc_mode_change(dc->ctx->dc_bios);
-- 
2.17.1

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[PATCH 22/24] drm/amd/display: Do not grant POST_LT_ADJ when TPS4 is used

[Bhawanpreet Lakha]

From: abdoulaye berthe <abdoulaye.berthe@amd.com>

[Description]

The spec does not allow POST_LT_ADJ_GRANTED to be set when TPS4 is used.

Signed-off-by: abdoulaye berthe <abdoulaye.berthe@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
---
 .../gpu/drm/amd/display/dc/core/dc_link_dp.c  | 56 ++++++++++---------
 1 file changed, 31 insertions(+), 25 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
index 2d519e5fc3ea..a1187274dbed 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
@@ -89,6 +89,29 @@ static void dpcd_set_training_pattern(
 		dpcd_pattern.v1_4.TRAINING_PATTERN_SET);
 }
 
+static enum hw_dp_training_pattern get_supported_tp(struct dc_link *link)
+{
+	enum hw_dp_training_pattern highest_tp = HW_DP_TRAINING_PATTERN_2;
+	struct encoder_feature_support *features = &link->link_enc->features;
+	struct dpcd_caps *dpcd_caps = &link->dpcd_caps;
+
+	if (features->flags.bits.IS_TPS3_CAPABLE)
+		highest_tp = HW_DP_TRAINING_PATTERN_3;
+
+	if (features->flags.bits.IS_TPS4_CAPABLE)
+		highest_tp = HW_DP_TRAINING_PATTERN_4;
+
+	if (dpcd_caps->max_down_spread.bits.TPS4_SUPPORTED &&
+		highest_tp >= HW_DP_TRAINING_PATTERN_4)
+		return HW_DP_TRAINING_PATTERN_4;
+
+	if (dpcd_caps->max_ln_count.bits.TPS3_SUPPORTED &&
+		highest_tp >= HW_DP_TRAINING_PATTERN_3)
+		return HW_DP_TRAINING_PATTERN_3;
+
+	return HW_DP_TRAINING_PATTERN_2;
+}
+
 static void dpcd_set_link_settings(
 	struct dc_link *link,
 	const struct link_training_settings *lt_settings)
@@ -97,6 +120,7 @@ static void dpcd_set_link_settings(
 
 	union down_spread_ctrl downspread = { {0} };
 	union lane_count_set lane_count_set = { {0} };
+	enum hw_dp_training_pattern hw_tr_pattern;
 
 	downspread.raw = (uint8_t)
 	(lt_settings->link_settings.link_spread);
@@ -106,8 +130,13 @@ static void dpcd_set_link_settings(
 
 	lane_count_set.bits.ENHANCED_FRAMING = 1;
 
-	lane_count_set.bits.POST_LT_ADJ_REQ_GRANTED =
-		link->dpcd_caps.max_ln_count.bits.POST_LT_ADJ_REQ_SUPPORTED;
+	lane_count_set.bits.POST_LT_ADJ_REQ_GRANTED = 0;
+
+	hw_tr_pattern = get_supported_tp(link);
+	if (hw_tr_pattern != HW_DP_TRAINING_PATTERN_4) {
+		lane_count_set.bits.POST_LT_ADJ_REQ_GRANTED =
+				link->dpcd_caps.max_ln_count.bits.POST_LT_ADJ_REQ_SUPPORTED;
+	}
 
 	core_link_write_dpcd(link, DP_DOWNSPREAD_CTRL,
 	&downspread.raw, sizeof(downspread));
@@ -698,29 +727,6 @@ static bool perform_post_lt_adj_req_sequence(
 
 }
 
-static enum hw_dp_training_pattern get_supported_tp(struct dc_link *link)
-{
-	enum hw_dp_training_pattern highest_tp = HW_DP_TRAINING_PATTERN_2;
-	struct encoder_feature_support *features = &link->link_enc->features;
-	struct dpcd_caps *dpcd_caps = &link->dpcd_caps;
-
-	if (features->flags.bits.IS_TPS3_CAPABLE)
-		highest_tp = HW_DP_TRAINING_PATTERN_3;
-
-	if (features->flags.bits.IS_TPS4_CAPABLE)
-		highest_tp = HW_DP_TRAINING_PATTERN_4;
-
-	if (dpcd_caps->max_down_spread.bits.TPS4_SUPPORTED &&
-		highest_tp >= HW_DP_TRAINING_PATTERN_4)
-		return HW_DP_TRAINING_PATTERN_4;
-
-	if (dpcd_caps->max_ln_count.bits.TPS3_SUPPORTED &&
-		highest_tp >= HW_DP_TRAINING_PATTERN_3)
-		return HW_DP_TRAINING_PATTERN_3;
-
-	return HW_DP_TRAINING_PATTERN_2;
-}
-
 static enum link_training_result get_cr_failure(enum dc_lane_count ln_count,
 					union lane_status *dpcd_lane_status)
 {
-- 
2.17.1

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[PATCH 23/24] drm/amd/display: make clk_mgr call enable_pme_wa

[Bhawanpreet Lakha]

From: Su Sung Chung <Su.Chung@amd.com>

refactor a code so we will call clk_mgr's enable_pme_wa function so we
can use pme_wa for future asics. This way we don't need to worry about
different ASIC since clk_mgr already have that information

Signed-off-by: Su Sung Chung <Su.Chung@amd.com>
Reviewed-by: Eric Yang <eric.yang2@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
---
 .../display/dc/clk_mgr/dcn10/rv1_clk_mgr.c    | 14 +++++++++++
 .../display/dc/dce110/dce110_hw_sequencer.c   | 25 +++++--------------
 2 files changed, 20 insertions(+), 19 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c
index 31db9b55e11a..183ca39ce5a1 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c
@@ -215,9 +215,23 @@ static void rv1_update_clocks(struct clk_mgr *clk_mgr_base,
 	}
 }
 
+static void rv1_enable_pme_wa(struct clk_mgr *clk_mgr_base)
+{
+	struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
+	struct pp_smu_funcs_rv *pp_smu = NULL;
+
+	if (clk_mgr->pp_smu) {
+		pp_smu = &clk_mgr->pp_smu->rv_funcs;
+
+		if (pp_smu->set_pme_wa_enable)
+			pp_smu->set_pme_wa_enable(&pp_smu->pp_smu);
+	}
+}
+
 static struct clk_mgr_funcs rv1_clk_funcs = {
 	.get_dp_ref_clk_frequency = dce12_get_dp_ref_freq_khz,
 	.update_clocks = rv1_update_clocks,
+	.enable_pme_wa = rv1_enable_pme_wa,
 };
 
 static struct clk_mgr_internal_funcs rv1_clk_internal_funcs = {
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
index 2a7ac452d458..5a831410bc55 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
@@ -939,26 +939,12 @@ void hwss_edp_backlight_control(
 		edp_receiver_ready_T9(link);
 }
 
-// Static helper function which calls the correct function
-// based on pp_smu version
-static void set_pme_wa_enable_by_version(struct dc *dc)
-{
-	struct pp_smu_funcs *pp_smu = NULL;
-
-	if (dc->res_pool->pp_smu)
-		pp_smu = dc->res_pool->pp_smu;
-
-	if (pp_smu) {
-		if (pp_smu->ctx.ver == PP_SMU_VER_RV && pp_smu->rv_funcs.set_pme_wa_enable)
-			pp_smu->rv_funcs.set_pme_wa_enable(&(pp_smu->ctx));
-	}
-}
-
 void dce110_enable_audio_stream(struct pipe_ctx *pipe_ctx)
 {
 	/* notify audio driver for audio modes of monitor */
 	struct dc *core_dc = pipe_ctx->stream->ctx->dc;
 	struct pp_smu_funcs *pp_smu = NULL;
+	struct clk_mgr *clk_mgr = core_dc->clk_mgr;
 	unsigned int i, num_audio = 1;
 
 	if (pipe_ctx->stream_res.audio && pipe_ctx->stream_res.audio->enabled == true)
@@ -976,9 +962,9 @@ void dce110_enable_audio_stream(struct pipe_ctx *pipe_ctx)
 
 		pipe_ctx->stream_res.audio->funcs->az_enable(pipe_ctx->stream_res.audio);
 
-		if (num_audio >= 1 && pp_smu != NULL)
+		if (num_audio >= 1 && clk_mgr->funcs->enable_pme_wa)
 			/*this is the first audio. apply the PME w/a in order to wake AZ from D3*/
-			set_pme_wa_enable_by_version(core_dc);
+			clk_mgr->funcs->enable_pme_wa(clk_mgr);
 		/* un-mute audio */
 		/* TODO: audio should be per stream rather than per link */
 		pipe_ctx->stream_res.stream_enc->funcs->audio_mute_control(
@@ -992,6 +978,7 @@ void dce110_disable_audio_stream(struct pipe_ctx *pipe_ctx, int option)
 {
 	struct dc *dc = pipe_ctx->stream->ctx->dc;
 	struct pp_smu_funcs *pp_smu = NULL;
+	struct clk_mgr *clk_mgr = dc->clk_mgr;
 
 	if (pipe_ctx->stream_res.audio && pipe_ctx->stream_res.audio->enabled == false)
 		return;
@@ -1020,9 +1007,9 @@ void dce110_disable_audio_stream(struct pipe_ctx *pipe_ctx, int option)
 			update_audio_usage(&dc->current_state->res_ctx, dc->res_pool, pipe_ctx->stream_res.audio, false);
 			pipe_ctx->stream_res.audio = NULL;
 		}
-		if (pp_smu != NULL)
+		if (clk_mgr->funcs->enable_pme_wa)
 			/*this is the first audio. apply the PME w/a in order to wake AZ from D3*/
-			set_pme_wa_enable_by_version(dc);
+			clk_mgr->funcs->enable_pme_wa(clk_mgr);
 
 		/* TODO: notify audio driver for if audio modes list changed
 		 * add audio mode list change flag */
-- 
2.17.1

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[PATCH 24/24] drm/amd/display: set link->dongle_max_pix_clk to 0 on a disconnect

[Bhawanpreet Lakha]

From: Samson Tam <Samson.Tam@amd.com>

[Why]
Found issue in EDID Emulation where if we connect a display using
 a passive HDMI-DP dongle, disconnect it and then try to emulate
 a display using DP, we could not see 4K modes.  This was because
 on a disconnect, dongle_max_pix_clk was still set so when we
 emulate using DP, in dc_link_validate_mode_timing(), it would
 think we were still using a dongle and limit the modes we support.

[How]
In dc_link_detect(), set dongle_max_pix_clk to 0 when we detect
 a hotplug out ( if new_connection_type = dc_connection_none ).

Signed-off-by: Samson Tam <Samson.Tam@amd.com>
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
---
 drivers/gpu/drm/amd/display/dc/core/dc_link.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index 10807fa46ad6..202e092f8ecf 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -984,6 +984,12 @@ bool dc_link_detect(struct dc_link *link, enum dc_detect_reason reason)
 
 		link->type = dc_connection_none;
 		sink_caps.signal = SIGNAL_TYPE_NONE;
+		/* When we unplug a passive DP-HDMI dongle connection, dongle_max_pix_clk
+		 *  is not cleared. If we emulate a DP signal on this connection, it thinks
+		 *  the dongle is still there and limits the number of modes we can emulate.
+		 *  Clear dongle_max_pix_clk on disconnect to fix this
+		 */
+		link->dongle_max_pix_clk = 0;
 	}
 
 	LINK_INFO("link=%d, dc_sink_in=%p is now %s prev_sink=%p dpcd same=%d edid same=%d\n",
-- 
2.17.1

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Re: [PATCH 10/24] drm/amd/display: Rework CRTC color management

[Michel Dänzer]

On 2019-06-06 10:54 p.m., Bhawanpreet Lakha wrote:
> From: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
> 
> [Why]
> To prepare for the upcoming DRM plane color management properties
> we need to correct a lot of wrong behavior and assumptions made for
> CRTC color management.
> 
> The documentation added by this commit in amdgpu_dm_color explains
> how the HW color pipeline works and its limitations with the DRM
> interface.
> 
> The current implementation does the following wrong:
> - Implicit sRGB DGM when no CRTC DGM is set
> - Implicit sRGB RGM when no CRTC RGM is set
> - No way to specify a non-linear DGM matrix that produces correct output
> - No way to specify a correct RGM when a linear DGM is used
> 
> We had workarounds for passing kms_color tests but not all of the
> behavior we had wrong was covered by these tests (especially when
> it comes to non-linear DGM). Testing both DGM and RGM at the same time
> isn't something kms_color tests well either.
> 
> [How]
> The specifics for how color management works in AMDGPU and the new
> behavior can be found by reading the documentation added to
> amdgpu_dm_color.c from this patch.
> 
> All of the incorrect cases from the old implementation have been
> addressed for the atomic interface, but there still a few TODOs for
> the legacy one.
> 
> Note: this does cause regressions for kms_color@pipe-a-ctm-* over HDMI.
> 
> The result looks correct from visual inspection but the CRC no longer
> matches. For reference, the test was previously doing the following:
> 
> linear degamma -> CTM -> sRGB regamma -> RGB to YUV (709) -> ...
> 
> Now the test is doing:
> 
> linear degamma -> CTM -> linear regamma -> RGB to YUV (709) -> ...
> 
> Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
> Reviewed-by: Sun peng Li <Sunpeng.Li@amd.com>
> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>

Does this address https://bugs.freedesktop.org/110677 ? If so, can you
add a reference to the commit log?


-- 
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Libre software enthusiast             |             Mesa and X developer
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Re: [PATCH 10/24] drm/amd/display: Rework CRTC color management

[Kazlauskas, Nicholas]

On 6/7/19 3:58 AM, Michel Dänzer wrote:
> On 2019-06-06 10:54 p.m., Bhawanpreet Lakha wrote:
>> From: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
>>
>> [Why]
>> To prepare for the upcoming DRM plane color management properties
>> we need to correct a lot of wrong behavior and assumptions made for
>> CRTC color management.
>>
>> The documentation added by this commit in amdgpu_dm_color explains
>> how the HW color pipeline works and its limitations with the DRM
>> interface.
>>
>> The current implementation does the following wrong:
>> - Implicit sRGB DGM when no CRTC DGM is set
>> - Implicit sRGB RGM when no CRTC RGM is set
>> - No way to specify a non-linear DGM matrix that produces correct output
>> - No way to specify a correct RGM when a linear DGM is used
>>
>> We had workarounds for passing kms_color tests but not all of the
>> behavior we had wrong was covered by these tests (especially when
>> it comes to non-linear DGM). Testing both DGM and RGM at the same time
>> isn't something kms_color tests well either.
>>
>> [How]
>> The specifics for how color management works in AMDGPU and the new
>> behavior can be found by reading the documentation added to
>> amdgpu_dm_color.c from this patch.
>>
>> All of the incorrect cases from the old implementation have been
>> addressed for the atomic interface, but there still a few TODOs for
>> the legacy one.
>>
>> Note: this does cause regressions for kms_color@pipe-a-ctm-* over HDMI.
>>
>> The result looks correct from visual inspection but the CRC no longer
>> matches. For reference, the test was previously doing the following:
>>
>> linear degamma -> CTM -> sRGB regamma -> RGB to YUV (709) -> ...
>>
>> Now the test is doing:
>>
>> linear degamma -> CTM -> linear regamma -> RGB to YUV (709) -> ...
>>
>> Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
>> Reviewed-by: Sun peng Li <Sunpeng.Li@amd.com>
>> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
> 
> Does this address https://bugs.freedesktop.org/110677 ? If so, can you
> add a reference to the commit log?
> 
> 

It unfortunately does not. There are still some remaining issues with 
legacy gamma support that I intend to address at some point - which I 
left in this patch as TODOs.

Nicholas Kazlauskas
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Re: [PATCH 10/24] drm/amd/display: Rework CRTC color management

[Michel Dänzer]

On 2019-06-07 2:26 p.m., Kazlauskas, Nicholas wrote:
> On 6/7/19 3:58 AM, Michel Dänzer wrote:
>> On 2019-06-06 10:54 p.m., Bhawanpreet Lakha wrote:
>>> From: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
>>>
>>> [Why]
>>> To prepare for the upcoming DRM plane color management properties
>>> we need to correct a lot of wrong behavior and assumptions made for
>>> CRTC color management.
>>>
>>> The documentation added by this commit in amdgpu_dm_color explains
>>> how the HW color pipeline works and its limitations with the DRM
>>> interface.
>>>
>>> The current implementation does the following wrong:
>>> - Implicit sRGB DGM when no CRTC DGM is set
>>> - Implicit sRGB RGM when no CRTC RGM is set
>>> - No way to specify a non-linear DGM matrix that produces correct output
>>> - No way to specify a correct RGM when a linear DGM is used
>>>
>>> We had workarounds for passing kms_color tests but not all of the
>>> behavior we had wrong was covered by these tests (especially when
>>> it comes to non-linear DGM). Testing both DGM and RGM at the same time
>>> isn't something kms_color tests well either.
>>>
>>> [How]
>>> The specifics for how color management works in AMDGPU and the new
>>> behavior can be found by reading the documentation added to
>>> amdgpu_dm_color.c from this patch.
>>>
>>> All of the incorrect cases from the old implementation have been
>>> addressed for the atomic interface, but there still a few TODOs for
>>> the legacy one.
>>>
>>> Note: this does cause regressions for kms_color@pipe-a-ctm-* over HDMI.
>>>
>>> The result looks correct from visual inspection but the CRC no longer
>>> matches. For reference, the test was previously doing the following:
>>>
>>> linear degamma -> CTM -> sRGB regamma -> RGB to YUV (709) -> ...
>>>
>>> Now the test is doing:
>>>
>>> linear degamma -> CTM -> linear regamma -> RGB to YUV (709) -> ...
>>>
>>> Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
>>> Reviewed-by: Sun peng Li <Sunpeng.Li@amd.com>
>>> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
>>
>> Does this address https://bugs.freedesktop.org/110677 ? If so, can you
>> add a reference to the commit log?
> 
> It unfortunately does not. There are still some remaining issues with 
> legacy gamma support that I intend to address at some point - which I 
> left in this patch as TODOs.

Note that the bug reporter is using xf86-video-amdgpu, which no longer
uses legacy gamma with DC, unless I misunderstand what you mean by that.


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Re: [PATCH 10/24] drm/amd/display: Rework CRTC color management

[Kazlauskas, Nicholas]

On 6/7/19 11:51 AM, Michel Dänzer wrote:
> On 2019-06-07 2:26 p.m., Kazlauskas, Nicholas wrote:
>> On 6/7/19 3:58 AM, Michel Dänzer wrote:
>>> On 2019-06-06 10:54 p.m., Bhawanpreet Lakha wrote:
>>>> From: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
>>>>
>>>> [Why]
>>>> To prepare for the upcoming DRM plane color management properties
>>>> we need to correct a lot of wrong behavior and assumptions made for
>>>> CRTC color management.
>>>>
>>>> The documentation added by this commit in amdgpu_dm_color explains
>>>> how the HW color pipeline works and its limitations with the DRM
>>>> interface.
>>>>
>>>> The current implementation does the following wrong:
>>>> - Implicit sRGB DGM when no CRTC DGM is set
>>>> - Implicit sRGB RGM when no CRTC RGM is set
>>>> - No way to specify a non-linear DGM matrix that produces correct output
>>>> - No way to specify a correct RGM when a linear DGM is used
>>>>
>>>> We had workarounds for passing kms_color tests but not all of the
>>>> behavior we had wrong was covered by these tests (especially when
>>>> it comes to non-linear DGM). Testing both DGM and RGM at the same time
>>>> isn't something kms_color tests well either.
>>>>
>>>> [How]
>>>> The specifics for how color management works in AMDGPU and the new
>>>> behavior can be found by reading the documentation added to
>>>> amdgpu_dm_color.c from this patch.
>>>>
>>>> All of the incorrect cases from the old implementation have been
>>>> addressed for the atomic interface, but there still a few TODOs for
>>>> the legacy one.
>>>>
>>>> Note: this does cause regressions for kms_color@pipe-a-ctm-* over HDMI.
>>>>
>>>> The result looks correct from visual inspection but the CRC no longer
>>>> matches. For reference, the test was previously doing the following:
>>>>
>>>> linear degamma -> CTM -> sRGB regamma -> RGB to YUV (709) -> ...
>>>>
>>>> Now the test is doing:
>>>>
>>>> linear degamma -> CTM -> linear regamma -> RGB to YUV (709) -> ...
>>>>
>>>> Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
>>>> Reviewed-by: Sun peng Li <Sunpeng.Li@amd.com>
>>>> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
>>>
>>> Does this address https://bugs.freedesktop.org/110677 ? If so, can you
>>> add a reference to the commit log?
>>
>> It unfortunately does not. There are still some remaining issues with
>> legacy gamma support that I intend to address at some point - which I
>> left in this patch as TODOs.
> 
> Note that the bug reporter is using xf86-video-amdgpu, which no longer
> uses legacy gamma with DC, unless I misunderstand what you mean by that.
> 
> 

While it can use the full LUT, my guess is that we were still getting 
256 entries in DM/DC, which we interpret as legacy at the moment.

FWIW I did actually tried reproducing the issue after applying the patch 
during development and it gave me the same results before and after for 
that specific issue.

Nicholas Kazlauskas
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Re: [PATCH 08/24] drm/amd/display: add audio related regs

[Dave Airlie]

On Fri, 7 Jun 2019 at 06:55, Bhawanpreet Lakha
<Bhawanpreet.Lakha@amd.com> wrote:
>
> From: Charlene Liu <charlene.liu@amd.com>
>
> Signed-off-by: Charlene Liu <charlene.liu@amd.com>
> Reviewed-by: Chris Park <Chris.Park@amd.com>
> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
> ---
>  drivers/gpu/drm/amd/display/dc/dce/dce_audio.c | 4 +---
>  drivers/gpu/drm/amd/display/dc/dce/dce_audio.h | 7 +++++++
>  2 files changed, 8 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_audio.c b/drivers/gpu/drm/amd/display/dc/dce/dce_audio.c
> index 7f6d724686f1..d43d5d924c19 100644
> --- a/drivers/gpu/drm/amd/display/dc/dce/dce_audio.c
> +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_audio.c
> @@ -22,7 +22,7 @@
>   * Authors: AMD
>   *
>   */
> -
> +#include "../dc.h"

Is this include needed? just seems wierd to have added it with no mention.

Dave.
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Re: [PATCH 08/24] drm/amd/display: add audio related regs

[Lakha, Bhawanpreet]

Thanks for catching that, it was left in by mistake when trying to fix 
some compile issues. I will push a patch to remove it


Bhawan

On 2019-06-25 12:15 a.m., Dave Airlie wrote:
> On Fri, 7 Jun 2019 at 06:55, Bhawanpreet Lakha
> <Bhawanpreet.Lakha@amd.com> wrote:
>> From: Charlene Liu <charlene.liu@amd.com>
>>
>> Signed-off-by: Charlene Liu <charlene.liu@amd.com>
>> Reviewed-by: Chris Park <Chris.Park@amd.com>
>> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
>> ---
>>   drivers/gpu/drm/amd/display/dc/dce/dce_audio.c | 4 +---
>>   drivers/gpu/drm/amd/display/dc/dce/dce_audio.h | 7 +++++++
>>   2 files changed, 8 insertions(+), 3 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_audio.c b/drivers/gpu/drm/amd/display/dc/dce/dce_audio.c
>> index 7f6d724686f1..d43d5d924c19 100644
>> --- a/drivers/gpu/drm/amd/display/dc/dce/dce_audio.c
>> +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_audio.c
>> @@ -22,7 +22,7 @@
>>    * Authors: AMD
>>    *
>>    */
>> -
>> +#include "../dc.h"
> Is this include needed? just seems wierd to have added it with no mention.
>
> Dave.
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