[PATCH RESEND 0/7] Add GPLL0 as clock provider for the Qualcomm's IPQ mailbox controller

[PATCH RESEND 0/7] Add GPLL0 as clock provider for the Qualcomm's IPQ mailbox controller

[Kathiravan Thirumoorthy]

Currently mailbox controller takes the XO and APSS PLL as the input. It
can take the GPLL0 also as an input. This patch series adds the same and
fixes the issue caused by this.

Once the cpufreq driver is up, it tries to bump up the cpu frequency
above 800MHz, while doing so system is going to unusable state. Reason
being, with the GPLL0 included as clock source, clock framework tries to
achieve the required rate with the possible parent and since GPLL0 carries
the CLK_SET_RATE_PARENT flag, clock rate of the GPLL0 is getting
changed, causing the issue.

First half of the series, removes the CLK_SET_RATE_PARENT flag from the
PLL clocks since the PLL clock rates shouldn't be changed. Another
half, add the necessary support to include the GPLL0 as clock provider
for mailbox and accomodate the changes in APSS clock driver.

This is also the preparatory series to enable the CPUFreq on IPQ5332
SoC. Dynamic scaling of CPUFreq is not supported on IPQ5332, so to
switch between the frequencies we need to park the APSS PLL in safe
source, here it is GPLL0 and then shutdown and bring up the APSS PLL in
the desired rate.

For IPQ5332 SoC, this series depends on the below patch
https://lore.kernel.org/linux-arm-msm/1693474133-10467-1-git-send-email-quic_varada@quicinc.com/

Signed-off-by: Kathiravan Thirumoorthy <quic_kathirav@quicinc.com>
---
Kathiravan Thirumoorthy (7):
      clk: qcom: ipq8074: drop the CLK_SET_RATE_PARENT flag from PLL clocks
      clk: qcom: ipq6018: drop the CLK_SET_RATE_PARENT flag from PLL clocks
      clk: qcom: ipq9574: drop the CLK_SET_RATE_PARENT flag from GPLL clocks
      clk: qcom: ipq5332: drop the CLK_SET_RATE_PARENT flag from GPLL clocks
      dt-bindings: mailbox: qcom: add one more clock provider for IPQ mailbox
      clk: qcom: apss-ipq6018: add the GPLL0 clock also as clock provider
      arm64: dts: qcom: include the GPLL0 as clock provider for IPQ mailbox

 .../devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml         | 2 ++
 arch/arm64/boot/dts/qcom/ipq5332.dtsi                              | 4 ++--
 arch/arm64/boot/dts/qcom/ipq6018.dtsi                              | 4 ++--
 arch/arm64/boot/dts/qcom/ipq8074.dtsi                              | 4 ++--
 arch/arm64/boot/dts/qcom/ipq9574.dtsi                              | 4 ++--
 drivers/clk/qcom/apss-ipq6018.c                                    | 3 +++
 drivers/clk/qcom/gcc-ipq5332.c                                     | 2 --
 drivers/clk/qcom/gcc-ipq6018.c                                     | 7 -------
 drivers/clk/qcom/gcc-ipq8074.c                                     | 7 -------
 drivers/clk/qcom/gcc-ipq9574.c                                     | 4 ----
 10 files changed, 13 insertions(+), 28 deletions(-)
---
base-commit: a47fc304d2b678db1a5d760a7d644dac9b067752
change-id: 20230904-gpll_cleanup-8b3e8b058c8b

Best regards,
-- 
Kathiravan Thirumoorthy <quic_kathirav@quicinc.com>

[PATCH RESEND 1/7] clk: qcom: ipq8074: drop the CLK_SET_RATE_PARENT flag from PLL clocks

[Kathiravan Thirumoorthy]

GPLL, UBI32 PLL, NSS crypto PLL clock rates are fixed and shouldn't
be scaled based on the request from dependent clocks. Doing so will
result in the unexpected behaviour. So drop the CLK_SET_RATE_PARENT flag
from the PLL clocks.

Fixes: b8e7e519625f ("clk: qcom: ipq8074: add remaining PLL’s")
Signed-off-by: Kathiravan Thirumoorthy <quic_kathirav@quicinc.com>
---
 drivers/clk/qcom/gcc-ipq8074.c | 7 -------
 1 file changed, 7 deletions(-)

diff --git a/drivers/clk/qcom/gcc-ipq8074.c b/drivers/clk/qcom/gcc-ipq8074.c
index 63ac2ced76bb..cfe2f2606cfe 100644
--- a/drivers/clk/qcom/gcc-ipq8074.c
+++ b/drivers/clk/qcom/gcc-ipq8074.c
@@ -75,7 +75,6 @@ static struct clk_fixed_factor gpll0_out_main_div2 = {
 				&gpll0_main.clkr.hw },
 		.num_parents = 1,
 		.ops = &clk_fixed_factor_ops,
-		.flags = CLK_SET_RATE_PARENT,
 	},
 };
 
@@ -121,7 +120,6 @@ static struct clk_alpha_pll_postdiv gpll2 = {
 				&gpll2_main.clkr.hw },
 		.num_parents = 1,
 		.ops = &clk_alpha_pll_postdiv_ro_ops,
-		.flags = CLK_SET_RATE_PARENT,
 	},
 };
 
@@ -154,7 +152,6 @@ static struct clk_alpha_pll_postdiv gpll4 = {
 				&gpll4_main.clkr.hw },
 		.num_parents = 1,
 		.ops = &clk_alpha_pll_postdiv_ro_ops,
-		.flags = CLK_SET_RATE_PARENT,
 	},
 };
 
@@ -188,7 +185,6 @@ static struct clk_alpha_pll_postdiv gpll6 = {
 				&gpll6_main.clkr.hw },
 		.num_parents = 1,
 		.ops = &clk_alpha_pll_postdiv_ro_ops,
-		.flags = CLK_SET_RATE_PARENT,
 	},
 };
 
@@ -201,7 +197,6 @@ static struct clk_fixed_factor gpll6_out_main_div2 = {
 				&gpll6_main.clkr.hw },
 		.num_parents = 1,
 		.ops = &clk_fixed_factor_ops,
-		.flags = CLK_SET_RATE_PARENT,
 	},
 };
 
@@ -234,7 +229,6 @@ static struct clk_alpha_pll_postdiv ubi32_pll = {
 				&ubi32_pll_main.clkr.hw },
 		.num_parents = 1,
 		.ops = &clk_alpha_pll_postdiv_ro_ops,
-		.flags = CLK_SET_RATE_PARENT,
 	},
 };
 
@@ -266,7 +260,6 @@ static struct clk_alpha_pll_postdiv nss_crypto_pll = {
 				&nss_crypto_pll_main.clkr.hw },
 		.num_parents = 1,
 		.ops = &clk_alpha_pll_postdiv_ro_ops,
-		.flags = CLK_SET_RATE_PARENT,
 	},
 };
 

-- 
2.34.1

[PATCH RESEND 2/7] clk: qcom: ipq6018: drop the CLK_SET_RATE_PARENT flag from PLL clocks

[Kathiravan Thirumoorthy]

GPLL, UBI32 PLL, NSS crypto PLL clock rates are fixed and shouldn't be
scaled based on the request from dependent clocks. Doing so will result
in the unexpected behaviour. So drop the CLK_SET_RATE_PARENT flag from
the PLL clocks.

Fixes: d9db07f088af ("clk: qcom: Add ipq6018 Global Clock Controller support")
Signed-off-by: Kathiravan Thirumoorthy <quic_kathirav@quicinc.com>
---
 drivers/clk/qcom/gcc-ipq6018.c | 7 -------
 1 file changed, 7 deletions(-)

diff --git a/drivers/clk/qcom/gcc-ipq6018.c b/drivers/clk/qcom/gcc-ipq6018.c
index 6120fbbc5de0..d6be70538566 100644
--- a/drivers/clk/qcom/gcc-ipq6018.c
+++ b/drivers/clk/qcom/gcc-ipq6018.c
@@ -72,7 +72,6 @@ static struct clk_fixed_factor gpll0_out_main_div2 = {
 				&gpll0_main.clkr.hw },
 		.num_parents = 1,
 		.ops = &clk_fixed_factor_ops,
-		.flags = CLK_SET_RATE_PARENT,
 	},
 };
 
@@ -86,7 +85,6 @@ static struct clk_alpha_pll_postdiv gpll0 = {
 				&gpll0_main.clkr.hw },
 		.num_parents = 1,
 		.ops = &clk_alpha_pll_postdiv_ro_ops,
-		.flags = CLK_SET_RATE_PARENT,
 	},
 };
 
@@ -130,7 +128,6 @@ static struct clk_alpha_pll_postdiv ubi32_pll = {
 				&ubi32_pll_main.clkr.hw },
 		.num_parents = 1,
 		.ops = &clk_alpha_pll_postdiv_ro_ops,
-		.flags = CLK_SET_RATE_PARENT,
 	},
 };
 
@@ -161,7 +158,6 @@ static struct clk_alpha_pll_postdiv gpll6 = {
 				&gpll6_main.clkr.hw },
 		.num_parents = 1,
 		.ops = &clk_alpha_pll_postdiv_ro_ops,
-		.flags = CLK_SET_RATE_PARENT,
 	},
 };
 
@@ -192,7 +188,6 @@ static struct clk_alpha_pll_postdiv gpll4 = {
 				&gpll4_main.clkr.hw },
 		.num_parents = 1,
 		.ops = &clk_alpha_pll_postdiv_ro_ops,
-		.flags = CLK_SET_RATE_PARENT,
 	},
 };
 
@@ -243,7 +238,6 @@ static struct clk_alpha_pll_postdiv gpll2 = {
 				&gpll2_main.clkr.hw },
 		.num_parents = 1,
 		.ops = &clk_alpha_pll_postdiv_ro_ops,
-		.flags = CLK_SET_RATE_PARENT,
 	},
 };
 
@@ -274,7 +268,6 @@ static struct clk_alpha_pll_postdiv nss_crypto_pll = {
 				&nss_crypto_pll_main.clkr.hw },
 		.num_parents = 1,
 		.ops = &clk_alpha_pll_postdiv_ro_ops,
-		.flags = CLK_SET_RATE_PARENT,
 	},
 };
 

-- 
2.34.1

[PATCH RESEND 3/7] clk: qcom: ipq9574: drop the CLK_SET_RATE_PARENT flag from GPLL clocks

[Kathiravan Thirumoorthy]

GPLL clock rates are fixed and shouldn't be scaled based on the request
from dependent clocks. Doing so will result in the unexpected behaviour.
So drop the CLK_SET_RATE_PARENT flag from the GPLL clocks.

Fixes: d75b82cff488 ("clk: qcom: Add Global Clock Controller driver for IPQ9574")
Signed-off-by: Kathiravan Thirumoorthy <quic_kathirav@quicinc.com>
---
 drivers/clk/qcom/gcc-ipq9574.c | 4 ----
 1 file changed, 4 deletions(-)

diff --git a/drivers/clk/qcom/gcc-ipq9574.c b/drivers/clk/qcom/gcc-ipq9574.c
index 8f430367299e..e8190108e1ae 100644
--- a/drivers/clk/qcom/gcc-ipq9574.c
+++ b/drivers/clk/qcom/gcc-ipq9574.c
@@ -87,7 +87,6 @@ static struct clk_fixed_factor gpll0_out_main_div2 = {
 			&gpll0_main.clkr.hw
 		},
 		.num_parents = 1,
-		.flags = CLK_SET_RATE_PARENT,
 		.ops = &clk_fixed_factor_ops,
 	},
 };
@@ -102,7 +101,6 @@ static struct clk_alpha_pll_postdiv gpll0 = {
 			&gpll0_main.clkr.hw
 		},
 		.num_parents = 1,
-		.flags = CLK_SET_RATE_PARENT,
 		.ops = &clk_alpha_pll_postdiv_ro_ops,
 	},
 };
@@ -132,7 +130,6 @@ static struct clk_alpha_pll_postdiv gpll4 = {
 			&gpll4_main.clkr.hw
 		},
 		.num_parents = 1,
-		.flags = CLK_SET_RATE_PARENT,
 		.ops = &clk_alpha_pll_postdiv_ro_ops,
 	},
 };
@@ -162,7 +159,6 @@ static struct clk_alpha_pll_postdiv gpll2 = {
 			&gpll2_main.clkr.hw
 		},
 		.num_parents = 1,
-		.flags = CLK_SET_RATE_PARENT,
 		.ops = &clk_alpha_pll_postdiv_ro_ops,
 	},
 };

-- 
2.34.1

[PATCH RESEND 4/7] clk: qcom: ipq5332: drop the CLK_SET_RATE_PARENT flag from GPLL clocks

[Kathiravan Thirumoorthy]

GPLL clock rates are fixed and shouldn't be scaled based on the
request from dependent clocks. Doing so will result in the unexpected
behaviour. So drop the CLK_SET_RATE_PARENT flag from the GPLL clocks.

Fixes: 3d89d52970fd ("clk: qcom: add Global Clock controller (GCC) driver for IPQ5332 SoC")
Signed-off-by: Kathiravan Thirumoorthy <quic_kathirav@quicinc.com>
---
 drivers/clk/qcom/gcc-ipq5332.c | 2 --
 1 file changed, 2 deletions(-)

diff --git a/drivers/clk/qcom/gcc-ipq5332.c b/drivers/clk/qcom/gcc-ipq5332.c
index b02026f8549b..6c74a117ef0b 100644
--- a/drivers/clk/qcom/gcc-ipq5332.c
+++ b/drivers/clk/qcom/gcc-ipq5332.c
@@ -114,7 +114,6 @@ static struct clk_alpha_pll_postdiv gpll2 = {
 				&gpll2_main.clkr.hw },
 		.num_parents = 1,
 		.ops = &clk_alpha_pll_postdiv_ro_ops,
-		.flags = CLK_SET_RATE_PARENT,
 	},
 };
 
@@ -154,7 +153,6 @@ static struct clk_alpha_pll_postdiv gpll4 = {
 				&gpll4_main.clkr.hw },
 		.num_parents = 1,
 		.ops = &clk_alpha_pll_postdiv_ro_ops,
-		.flags = CLK_SET_RATE_PARENT,
 	},
 };
 

-- 
2.34.1

[PATCH RESEND 5/7] dt-bindings: mailbox: qcom: add one more clock provider for IPQ mailbox

[Kathiravan Thirumoorthy]

Mailbox controller present in the IPQ SoCs takes the GPLL0 clock also as
an input. Document the same.

Signed-off-by: Kathiravan Thirumoorthy <quic_kathirav@quicinc.com>
---
 Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml b/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml
index d2e25ff6db7f..a38413f8d132 100644
--- a/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml
+++ b/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml
@@ -125,10 +125,12 @@ allOf:
           items:
             - description: primary pll parent of the clock driver
             - description: XO clock
+            - description: GCC GPLL0 clock source
         clock-names:
           items:
             - const: pll
             - const: xo
+            - const: gpll0
 
   - if:
       properties:

-- 
2.34.1

[PATCH RESEND 6/7] clk: qcom: apss-ipq6018: add the GPLL0 clock also as clock provider

[Kathiravan Thirumoorthy]

While the kernel is booting up, APSS PLL will be running at 800MHz with
GPLL0 as source. Once the cpufreq driver is available, APSS PLL will be
configured and select the rate based on the opp table and the source will
be changed to APSS_PLL_EARLY.

Without this patch, CPU Freq driver reports that CPU is running at 24MHz
instead of the 800MHz.

Signed-off-by: Kathiravan Thirumoorthy <quic_kathirav@quicinc.com>
---
 drivers/clk/qcom/apss-ipq6018.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/clk/qcom/apss-ipq6018.c b/drivers/clk/qcom/apss-ipq6018.c
index f2f502e2d5a4..4e13a085a857 100644
--- a/drivers/clk/qcom/apss-ipq6018.c
+++ b/drivers/clk/qcom/apss-ipq6018.c
@@ -20,16 +20,19 @@
 
 enum {
 	P_XO,
+	P_GPLL0,
 	P_APSS_PLL_EARLY,
 };
 
 static const struct clk_parent_data parents_apcs_alias0_clk_src[] = {
 	{ .fw_name = "xo" },
+	{ .fw_name = "gpll0" },
 	{ .fw_name = "pll" },
 };
 
 static const struct parent_map parents_apcs_alias0_clk_src_map[] = {
 	{ P_XO, 0 },
+	{ P_GPLL0, 4 },
 	{ P_APSS_PLL_EARLY, 5 },
 };
 

-- 
2.34.1

[PATCH RESEND 7/7] arm64: dts: qcom: include the GPLL0 as clock provider for IPQ mailbox

[Kathiravan Thirumoorthy]

While the kernel is booting up, APSS PLL will be running at 800MHz with
GPLL0 as source. Once the cpufreq driver is available, APSS PLL will be
configured to the rate based on the opp table and the source also will be
changed to APSS_PLL_EARLY.

Also, dynamic scaling of CPUFreq is not supported on IPQ5332, so to switch
between the frequencies we need to park the APSS PLL in safe source,
here it is GPLL0 and then shutdown and bring up the APSS PLL in the
desired rate. So this patch is preparatory one to enable the CPUFreq on
IPQ5332.

Signed-off-by: Kathiravan Thirumoorthy <quic_kathirav@quicinc.com>
---
 arch/arm64/boot/dts/qcom/ipq5332.dtsi | 4 ++--
 arch/arm64/boot/dts/qcom/ipq6018.dtsi | 4 ++--
 arch/arm64/boot/dts/qcom/ipq8074.dtsi | 4 ++--
 arch/arm64/boot/dts/qcom/ipq9574.dtsi | 4 ++--
 4 files changed, 8 insertions(+), 8 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/ipq5332.dtsi b/arch/arm64/boot/dts/qcom/ipq5332.dtsi
index 8bfc2db44624..82761ae199a9 100644
--- a/arch/arm64/boot/dts/qcom/ipq5332.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq5332.dtsi
@@ -335,8 +335,8 @@ apcs_glb: mailbox@b111000 {
 				     "qcom,ipq6018-apcs-apps-global";
 			reg = <0x0b111000 0x1000>;
 			#clock-cells = <1>;
-			clocks = <&a53pll>, <&xo_board>;
-			clock-names = "pll", "xo";
+			clocks = <&a53pll>, <&xo_board>, <&gcc GPLL0>;
+			clock-names = "pll", "xo", "gpll0";
 			#mbox-cells = <1>;
 		};
 
diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
index 47b8b1d6730a..a30a5b893762 100644
--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
@@ -619,8 +619,8 @@ apcs_glb: mailbox@b111000 {
 			compatible = "qcom,ipq6018-apcs-apps-global";
 			reg = <0x0 0x0b111000 0x0 0x1000>;
 			#clock-cells = <1>;
-			clocks = <&a53pll>, <&xo>;
-			clock-names = "pll", "xo";
+			clocks = <&a53pll>, <&xo>, <&gcc GPLL0>;
+			clock-names = "pll", "xo", "gpll0";
 			#mbox-cells = <1>;
 		};
 
diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
index 00ed71936b47..0be19267bdcf 100644
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
@@ -719,8 +719,8 @@ apcs_glb: mailbox@b111000 {
 			compatible = "qcom,ipq8074-apcs-apps-global",
 				     "qcom,ipq6018-apcs-apps-global";
 			reg = <0x0b111000 0x1000>;
-			clocks = <&a53pll>, <&xo>;
-			clock-names = "pll", "xo";
+			clocks = <&a53pll>, <&xo>, <&gcc GPLL0>;
+			clock-names = "pll", "xo", "gpll0";
 
 			#clock-cells = <1>;
 			#mbox-cells = <1>;
diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
index 51aba071c1eb..89edb4b852df 100644
--- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
@@ -652,8 +652,8 @@ apcs_glb: mailbox@b111000 {
 				     "qcom,ipq6018-apcs-apps-global";
 			reg = <0x0b111000 0x1000>;
 			#clock-cells = <1>;
-			clocks = <&a73pll>, <&xo_board_clk>;
-			clock-names = "pll", "xo";
+			clocks = <&a73pll>, <&xo_board_clk>, <&gcc GPLL0>;
+			clock-names = "pll", "xo", "gpll0";
 			#mbox-cells = <1>;
 		};
 

-- 
2.34.1

Re: [PATCH RESEND 0/7] Add GPLL0 as clock provider for the Qualcomm's IPQ mailbox controller

[Kathiravan Thirumoorthy]

On 9/6/2023 10:26 AM, Kathiravan Thirumoorthy wrote:
> Currently mailbox controller takes the XO and APSS PLL as the input. It
> can take the GPLL0 also as an input. This patch series adds the same and
> fixes the issue caused by this.
>
> Once the cpufreq driver is up, it tries to bump up the cpu frequency
> above 800MHz, while doing so system is going to unusable state. Reason
> being, with the GPLL0 included as clock source, clock framework tries to
> achieve the required rate with the possible parent and since GPLL0 carries
> the CLK_SET_RATE_PARENT flag, clock rate of the GPLL0 is getting
> changed, causing the issue.
>
> First half of the series, removes the CLK_SET_RATE_PARENT flag from the
> PLL clocks since the PLL clock rates shouldn't be changed. Another
> half, add the necessary support to include the GPLL0 as clock provider
> for mailbox and accomodate the changes in APSS clock driver.
>
> This is also the preparatory series to enable the CPUFreq on IPQ5332
> SoC. Dynamic scaling of CPUFreq is not supported on IPQ5332, so to
> switch between the frequencies we need to park the APSS PLL in safe
> source, here it is GPLL0 and then shutdown and bring up the APSS PLL in
> the desired rate.
>
> For IPQ5332 SoC, this series depends on the below patch
> https://lore.kernel.org/linux-arm-msm/1693474133-10467-1-git-send-email-quic_varada@quicinc.com/


My bad.. This is not a 'resend', this is V1.. I'm trying to get used to 
b4 and messed up... Will rectify it in future.


>
> Signed-off-by: Kathiravan Thirumoorthy <quic_kathirav@quicinc.com>
> ---
> Kathiravan Thirumoorthy (7):
>        clk: qcom: ipq8074: drop the CLK_SET_RATE_PARENT flag from PLL clocks
>        clk: qcom: ipq6018: drop the CLK_SET_RATE_PARENT flag from PLL clocks
>        clk: qcom: ipq9574: drop the CLK_SET_RATE_PARENT flag from GPLL clocks
>        clk: qcom: ipq5332: drop the CLK_SET_RATE_PARENT flag from GPLL clocks
>        dt-bindings: mailbox: qcom: add one more clock provider for IPQ mailbox
>        clk: qcom: apss-ipq6018: add the GPLL0 clock also as clock provider
>        arm64: dts: qcom: include the GPLL0 as clock provider for IPQ mailbox
>
>   .../devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml         | 2 ++
>   arch/arm64/boot/dts/qcom/ipq5332.dtsi                              | 4 ++--
>   arch/arm64/boot/dts/qcom/ipq6018.dtsi                              | 4 ++--
>   arch/arm64/boot/dts/qcom/ipq8074.dtsi                              | 4 ++--
>   arch/arm64/boot/dts/qcom/ipq9574.dtsi                              | 4 ++--
>   drivers/clk/qcom/apss-ipq6018.c                                    | 3 +++
>   drivers/clk/qcom/gcc-ipq5332.c                                     | 2 --
>   drivers/clk/qcom/gcc-ipq6018.c                                     | 7 -------
>   drivers/clk/qcom/gcc-ipq8074.c                                     | 7 -------
>   drivers/clk/qcom/gcc-ipq9574.c                                     | 4 ----
>   10 files changed, 13 insertions(+), 28 deletions(-)
> ---
> base-commit: a47fc304d2b678db1a5d760a7d644dac9b067752
> change-id: 20230904-gpll_cleanup-8b3e8b058c8b
>
> Best regards,

Re: [PATCH RESEND 5/7] dt-bindings: mailbox: qcom: add one more clock provider for IPQ mailbox

[Krzysztof Kozlowski]

On 06/09/2023 06:56, Kathiravan Thirumoorthy wrote:
> Mailbox controller present in the IPQ SoCs takes the GPLL0 clock also as
> an input. Document the same.
> 

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

Best regards,
Krzysztof

Re: [PATCH RESEND 7/7] arm64: dts: qcom: include the GPLL0 as clock provider for IPQ mailbox

[Konrad Dybcio]

On 6.09.2023 06:56, Kathiravan Thirumoorthy wrote:
> While the kernel is booting up, APSS PLL will be running at 800MHz with
> GPLL0 as source. Once the cpufreq driver is available, APSS PLL will be
> configured to the rate based on the opp table and the source also will be
> changed to APSS_PLL_EARLY.
> 
> Also, dynamic scaling of CPUFreq is not supported on IPQ5332, so to switch
> between the frequencies we need to park the APSS PLL in safe source,
> here it is GPLL0 and then shutdown and bring up the APSS PLL in the
> desired rate. So this patch is preparatory one to enable the CPUFreq on
> IPQ5332.
> 
> Signed-off-by: Kathiravan Thirumoorthy <quic_kathirav@quicinc.com>
> ---
Please split this. Somebody reverting this in the future will have
a hard time resolving conflicts.

Konrad

Re: [PATCH RESEND 7/7] arm64: dts: qcom: include the GPLL0 as clock provider for IPQ mailbox

[Kathiravan Thirumoorthy]

On 9/6/2023 3:03 PM, Konrad Dybcio wrote:
> On 6.09.2023 06:56, Kathiravan Thirumoorthy wrote:
>> While the kernel is booting up, APSS PLL will be running at 800MHz with
>> GPLL0 as source. Once the cpufreq driver is available, APSS PLL will be
>> configured to the rate based on the opp table and the source also will be
>> changed to APSS_PLL_EARLY.
>>
>> Also, dynamic scaling of CPUFreq is not supported on IPQ5332, so to switch
>> between the frequencies we need to park the APSS PLL in safe source,
>> here it is GPLL0 and then shutdown and bring up the APSS PLL in the
>> desired rate. So this patch is preparatory one to enable the CPUFreq on
>> IPQ5332.
>>
>> Signed-off-by: Kathiravan Thirumoorthy <quic_kathirav@quicinc.com>
>> ---
> Please split this. Somebody reverting this in the future will have
> a hard time resolving conflicts.


Ack, will split it out in V2.


>
> Konrad

Re: [PATCH RESEND 6/7] clk: qcom: apss-ipq6018: add the GPLL0 clock also as clock provider

[Robert Marko]

On 06. 09. 2023. 06:56, Kathiravan Thirumoorthy wrote:
> While the kernel is booting up, APSS PLL will be running at 800MHz with
> GPLL0 as source. Once the cpufreq driver is available, APSS PLL will be
> configured and select the rate based on the opp table and the source will
> be changed to APSS_PLL_EARLY.
>
> Without this patch, CPU Freq driver reports that CPU is running at 24MHz
> instead of the 800MHz.
>
> Signed-off-by: Kathiravan Thirumoorthy <quic_kathirav@quicinc.com>
I can confirm that this works on IPQ8074 as well, it now properly sees the
default CPU clock of 800MHz instead of XO rate.

Tested-by: Robert Marko <robimarko@gmail.com>
> ---
>   drivers/clk/qcom/apss-ipq6018.c | 3 +++
>   1 file changed, 3 insertions(+)
>
> diff --git a/drivers/clk/qcom/apss-ipq6018.c b/drivers/clk/qcom/apss-ipq6018.c
> index f2f502e2d5a4..4e13a085a857 100644
> --- a/drivers/clk/qcom/apss-ipq6018.c
> +++ b/drivers/clk/qcom/apss-ipq6018.c
> @@ -20,16 +20,19 @@
>   
>   enum {
>   	P_XO,
> +	P_GPLL0,
>   	P_APSS_PLL_EARLY,
>   };
>   
>   static const struct clk_parent_data parents_apcs_alias0_clk_src[] = {
>   	{ .fw_name = "xo" },
> +	{ .fw_name = "gpll0" },
>   	{ .fw_name = "pll" },
>   };
>   
>   static const struct parent_map parents_apcs_alias0_clk_src_map[] = {
>   	{ P_XO, 0 },
> +	{ P_GPLL0, 4 },
>   	{ P_APSS_PLL_EARLY, 5 },
>   };
>   
>

Re: [PATCH RESEND 6/7] clk: qcom: apss-ipq6018: add the GPLL0 clock also as clock provider

[Konrad Dybcio]

On 6.09.2023 06:56, Kathiravan Thirumoorthy wrote:
> While the kernel is booting up, APSS PLL will be running at 800MHz with
> GPLL0 as source. Once the cpufreq driver is available, APSS PLL will be
> configured and select the rate based on the opp table and the source will
> be changed to APSS_PLL_EARLY.
> 
> Without this patch, CPU Freq driver reports that CPU is running at 24MHz
> instead of the 800MHz.
> 
> Signed-off-by: Kathiravan Thirumoorthy <quic_kathirav@quicinc.com>
> ---
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>

Konrad