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From: Dave Hansen <dave.hansen@linux.intel.com>
To: "Rafael J. Wysocki" <rafael@kernel.org>
Cc: Ingo Molnar <mingo@kernel.org>,
	kernel test robot <fengguang.wu@intel.com>, LKP <lkp@01.org>,
	kvm@vger.kernel.org,
	Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
	Thomas Gleixner <tglx@linutronix.de>,
	wfg@linux.intel.com, "Rafael J. Wysocki" <rjw@rjwysocki.net>,
	ACPI Devel Maling List <linux-acpi@vger.kernel.org>,
	"Brown, Len" <len.brown@intel.com>,
	Jesse Barnes <jbarnes@virtuousgeek.org>,
	Bjorn Helgaas <bhelgaas@google.com>
Subject: Re: 2f47e7e19f ("x86/mm/kaiser: Use PCID feature to make user and .."): WARNING: CPU: 0 PID: 1 at mm/early_ioremap.c:114 __early_ioremap
Date: Mon, 27 Nov 2017 17:22:02 -0800	[thread overview]
Message-ID: <9f73a515-ce07-c833-4e6b-2062fe03f354@linux.intel.com> (raw)
In-Reply-To: <CAJZ5v0hyAt1cPj3jpm9njOZAo02WmN-83ozeyvDF5qipBXqH=Q@mail.gmail.com>

I think I narrowed this down.

__native_flush_tlb_single() depends on cpu_tlbstate.loaded_mm_asid
matching what is in CR3.  But, while we are still "early" in boot, CR3
has hardware ASID=0, but cpu_tlbstate.loaded_mm_asid=0 which is actually
hardware ASID=1.

So, we have ASID=0 in CR3 and we try to *flush* ASID=1 with INVPCID,
which does nothing for us, effectively missing the TLB flush.

I think we need to steer __native_flush_tlb_single() into the
"!this_cpu_has(X86_FEATURE_INVPCID_SINGLE)" path if we get called before
initialize_tlbstate_and_flush() gives us a "real" ASID in CR3, but I
haven't found a nice way to do it, yet.

We probably also need a debugging warning in there to read CR3 and check
it against cpu_tlbstate.loaded_mm_asid.  I'll look at this in some more
detail tomorrow if nobody beats me to it.

WARNING: multiple messages have this Message-ID (diff)
From: Dave Hansen <dave.hansen@linux.intel.com>
To: lkp@lists.01.org
Subject: Re: 2f47e7e19f ("x86/mm/kaiser: Use PCID feature to make user and .."): WARNING: CPU: 0 PID: 1 at mm/early_ioremap.c:114 __early_ioremap
Date: Mon, 27 Nov 2017 17:22:02 -0800	[thread overview]
Message-ID: <9f73a515-ce07-c833-4e6b-2062fe03f354@linux.intel.com> (raw)
In-Reply-To: <CAJZ5v0hyAt1cPj3jpm9njOZAo02WmN-83ozeyvDF5qipBXqH=Q@mail.gmail.com>

[-- Attachment #1: Type: text/plain, Size: 842 bytes --]

I think I narrowed this down.

__native_flush_tlb_single() depends on cpu_tlbstate.loaded_mm_asid
matching what is in CR3.  But, while we are still "early" in boot, CR3
has hardware ASID=0, but cpu_tlbstate.loaded_mm_asid=0 which is actually
hardware ASID=1.

So, we have ASID=0 in CR3 and we try to *flush* ASID=1 with INVPCID,
which does nothing for us, effectively missing the TLB flush.

I think we need to steer __native_flush_tlb_single() into the
"!this_cpu_has(X86_FEATURE_INVPCID_SINGLE)" path if we get called before
initialize_tlbstate_and_flush() gives us a "real" ASID in CR3, but I
haven't found a nice way to do it, yet.

We probably also need a debugging warning in there to read CR3 and check
it against cpu_tlbstate.loaded_mm_asid.  I'll look at this in some more
detail tomorrow if nobody beats me to it.

  parent reply	other threads:[~2017-11-28  1:22 UTC|newest]

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-11-26 11:49 2f47e7e19f ("x86/mm/kaiser: Use PCID feature to make user and .."): WARNING: CPU: 0 PID: 1 at mm/early_ioremap.c:114 __early_ioremap kernel test robot
2017-11-26 11:49 ` kernel test robot
2017-11-27 10:18 ` Ingo Molnar
2017-11-27 10:18   ` Ingo Molnar
2017-11-27 14:51   ` Dave Hansen
2017-11-27 14:51     ` Dave Hansen
2017-11-27 18:03     ` Eduardo Valentin
2017-11-27 18:28       ` Dave Hansen
2017-11-27 18:28         ` Dave Hansen
2017-11-27 19:08         ` Eduardo Valentin
2017-11-27 16:14   ` Dave Hansen
2017-11-27 16:14     ` Dave Hansen
2017-11-27 22:13     ` Rafael J. Wysocki
2017-11-27 22:13       ` Rafael J. Wysocki
2017-11-27 22:33       ` Rafael J. Wysocki
2017-11-27 22:33         ` Rafael J. Wysocki
2017-11-28  1:22       ` Dave Hansen [this message]
2017-11-28  1:22         ` Dave Hansen

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