[PATCH 1/2] SVM: Replace numeric value for SME CPUID leaf with a #define

[PATCH 1/2] SVM: Replace numeric value for SME CPUID leaf with a #define

[Krish Sadhukhan]

Signed-off-by: Krish Sadhukhan <krish.sadhukhan@oracle.com>
---
 arch/x86/include/asm/svm.h | 1 +
 arch/x86/kvm/svm/svm.c     | 4 ++--
 2 files changed, 3 insertions(+), 2 deletions(-)

diff --git a/arch/x86/include/asm/svm.h b/arch/x86/include/asm/svm.h
index 8a1f5382a4ea..9eea127563fb 100644
--- a/arch/x86/include/asm/svm.h
+++ b/arch/x86/include/asm/svm.h
@@ -216,6 +216,7 @@ struct __attribute__ ((__packed__)) vmcb {
 };
 
 #define SVM_CPUID_FUNC 0x8000000a
+#define SVM_SME_CPUID_FUNC 0x8000001f
 
 #define SVM_VM_CR_SVM_DISABLE 4
 
diff --git a/arch/x86/kvm/svm/svm.c b/arch/x86/kvm/svm/svm.c
index 03dd7bac8034..97333b4ece5a 100644
--- a/arch/x86/kvm/svm/svm.c
+++ b/arch/x86/kvm/svm/svm.c
@@ -749,7 +749,7 @@ static __init void svm_adjust_mmio_mask(void)
 	u64 msr, mask;
 
 	/* If there is no memory encryption support, use existing mask */
-	if (cpuid_eax(0x80000000) < 0x8000001f)
+	if (cpuid_eax(0x80000000) < SVM_SME_CPUID_FUNC)
 		return;
 
 	/* If memory encryption is not enabled, use existing mask */
@@ -757,7 +757,7 @@ static __init void svm_adjust_mmio_mask(void)
 	if (!(msr & MSR_K8_SYSCFG_MEM_ENCRYPT))
 		return;
 
-	enc_bit = cpuid_ebx(0x8000001f) & 0x3f;
+	enc_bit = cpuid_ebx(SVM_SME_CPUID_FUNC) & 0x3f;
 	mask_bit = boot_cpu_data.x86_phys_bits;
 
 	/* Increment the mask bit if it is the same as the encryption bit */
-- 
2.18.4

[PATCH 2/2] KVM: SVM: Don't flush cache of SEV-encrypted pages if hardware enforces cache coherency across encryption domains

[Krish Sadhukhan]

Some hardware implementations may enforce cache coherency across encryption
domains. In such cases, it's not required to flush SEV-encrypted pages off
cache lines.

Signed-off-by: Krish Sadhukhan <krish.sadhukhan@oracle.com>
---
 arch/x86/kvm/svm/sev.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/arch/x86/kvm/svm/sev.c b/arch/x86/kvm/svm/sev.c
index 402dc4234e39..c8ed8a62d5ef 100644
--- a/arch/x86/kvm/svm/sev.c
+++ b/arch/x86/kvm/svm/sev.c
@@ -384,7 +384,8 @@ static void sev_clflush_pages(struct page *pages[], unsigned long npages)
 	uint8_t *page_virtual;
 	unsigned long i;
 
-	if (npages == 0 || pages == NULL)
+	if ((cpuid_eax(SVM_SME_CPUID_FUNC) & (1u << 10)) || npages == 0 ||
+	    pages == NULL)
 		return;
 
 	for (i = 0; i < npages; i++) {
-- 
2.18.4

Re: [PATCH 2/2] KVM: SVM: Don't flush cache of SEV-encrypted pages if hardware enforces cache coherency across encryption domains

[Tom Lendacky]

On 8/28/20 7:59 PM, Krish Sadhukhan wrote:
> Some hardware implementations may enforce cache coherency across encryption
> domains. In such cases, it's not required to flush SEV-encrypted pages off
> cache lines.
> 
> Signed-off-by: Krish Sadhukhan <krish.sadhukhan@oracle.com>
> ---
>   arch/x86/kvm/svm/sev.c | 3 ++-
>   1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/x86/kvm/svm/sev.c b/arch/x86/kvm/svm/sev.c
> index 402dc4234e39..c8ed8a62d5ef 100644
> --- a/arch/x86/kvm/svm/sev.c
> +++ b/arch/x86/kvm/svm/sev.c
> @@ -384,7 +384,8 @@ static void sev_clflush_pages(struct page *pages[], unsigned long npages)
>   	uint8_t *page_virtual;
>   	unsigned long i;
>   
> -	if (npages == 0 || pages == NULL)
> +	if ((cpuid_eax(SVM_SME_CPUID_FUNC) & (1u << 10)) || npages == 0 ||

Thanks for the patch. This should really be added as an X86_FEATURE bit, 
and then check that feature here, as opposed to calling CPUID every time. 
Also, there are other places in the kernel that this may be relevant, are 
you investigating those areas, also (e.g. set_memory_encrypted() / 
set_memory_decrypted())?

Thanks,
Tom

> +	    pages == NULL)
>   		return;
>   
>   	for (i = 0; i < npages; i++) {
> 

Re: [PATCH 2/2] KVM: SVM: Don't flush cache of SEV-encrypted pages if hardware enforces cache coherency across encryption domains

[Krish Sadhukhan]

On 8/31/20 9:14 AM, Tom Lendacky wrote:
> On 8/28/20 7:59 PM, Krish Sadhukhan wrote:
>> Some hardware implementations may enforce cache coherency across 
>> encryption
>> domains. In such cases, it's not required to flush SEV-encrypted 
>> pages off
>> cache lines.
>>
>> Signed-off-by: Krish Sadhukhan <krish.sadhukhan@oracle.com>
>> ---
>>   arch/x86/kvm/svm/sev.c | 3 ++-
>>   1 file changed, 2 insertions(+), 1 deletion(-)
>>
>> diff --git a/arch/x86/kvm/svm/sev.c b/arch/x86/kvm/svm/sev.c
>> index 402dc4234e39..c8ed8a62d5ef 100644
>> --- a/arch/x86/kvm/svm/sev.c
>> +++ b/arch/x86/kvm/svm/sev.c
>> @@ -384,7 +384,8 @@ static void sev_clflush_pages(struct page 
>> *pages[], unsigned long npages)
>>       uint8_t *page_virtual;
>>       unsigned long i;
>>   -    if (npages == 0 || pages == NULL)
>> +    if ((cpuid_eax(SVM_SME_CPUID_FUNC) & (1u << 10)) || npages == 0 ||
>
> Thanks for the patch. This should really be added as an X86_FEATURE 
> bit, and then check that feature here, as opposed to calling CPUID 
> every time. Also, there are other places in the kernel that this may 
> be relevant, are you investigating those areas, also (e.g. 
> set_memory_encrypted() / set_memory_decrypted())?


Thanks for the suggestions. I will add it as an X86_FEATURE bit.

As for other places, I see that __set_memory_enc_dec() is where we can 
add this condition. Not sure if I have missed anything, but other places 
where we call cpa_flush() and stuff like that, are for regular pages and 
not encrypted one.

I will send out v2 with these changes.


>
> Thanks,
> Tom
>
>> +        pages == NULL)
>>           return;
>>         for (i = 0; i < npages; i++) {
>>