[Qemu-devel] [PATCH v5 3/7] RTC: Add UIP(update in progress) check logic

[Qemu-devel] [PATCH v5 3/7] RTC: Add UIP(update in progress) check logic

[Zhang, Yang Z]

The UIP(update in progress) is set when RTC is updating. And the update cycle begins 244us later after UIP is set. And it is cleared when update end.

Signed-off-by: Yang Zhang <yang.z.zhang@Intel.com>
---
 hw/mc146818rtc.c |   18 ++++++++++++++++++
 1 files changed, 18 insertions(+), 0 deletions(-)

diff --git a/hw/mc146818rtc.c b/hw/mc146818rtc.c
index 2d10013..b70422a 100644
--- a/hw/mc146818rtc.c
+++ b/hw/mc146818rtc.c
@@ -380,6 +380,21 @@ static void rtc_calibrate_time(RTCState *s)
     s->current_tm = *ret;
 }

+static int update_in_progress(RTCState *s)
+{
+    int64_t guest_usec;
+
+    if (s->cmos_data[RTC_REG_B] & REG_B_SET) {
+        return 0;
+    }
+    guest_usec = get_guest_rtc_us(s);
+    /* UIP bit will be set at last 244us of every second. */
+    if ((guest_usec % USEC_PER_SEC) >= (USEC_PER_SEC - 244)) {
+        return 1;
+    }
+    return 0;
+}
+
 static uint32_t cmos_ioport_read(void *opaque, uint32_t addr)
 {
     RTCState *s = opaque;
@@ -405,6 +420,9 @@ static uint32_t cmos_ioport_read(void *opaque, uint32_t addr)
             break;
         case RTC_REG_A:
             ret = s->cmos_data[s->cmos_index];
+            if (update_in_progress(s)) {
+                ret |= REG_A_UIP;
+            }
             break;
         case RTC_REG_C:
             ret = s->cmos_data[s->cmos_index];
--
1.7.1