* [PATCH] x86: support newer Intel CPU models
@ 2015-03-23 15:44 Jan Beulich
2015-03-24 0:51 ` Tian, Kevin
0 siblings, 1 reply; 5+ messages in thread
From: Jan Beulich @ 2015-03-23 15:44 UTC (permalink / raw)
To: xen-devel
Cc: Andrew Cooper, Kevin Tian, Keir Fraser, Jun Nakajima, Donald D Dugger
[-- Attachment #1: Type: text/plain, Size: 4481 bytes --]
This just follows what the January 2015 edition of the SDM documents,
with additional clarification from Intel:
- Broadwell models 0x4f and 0x56 don't cross-reference other tables,
but should be treated like other Boradwell (0x3d),
- Xeon Phi model 0x57 lists LASTBRANCH_TOS but not where the actual
stack is. Being told it's Silvermont based, attach it there.
Signed-off-by: Jan Beulich <jbeulich@suse.com>
--- a/xen/arch/x86/acpi/cpu_idle.c
+++ b/xen/arch/x86/acpi/cpu_idle.c
@@ -62,6 +62,7 @@
#define GET_HW_RES_IN_NS(msr, val) \
do { rdmsrl(msr, val); val = tsc_ticks2ns(val); } while( 0 )
+#define GET_MC6_RES(val) GET_HW_RES_IN_NS(0x664, val) /* Atom E3000 only */
#define GET_PC2_RES(val) GET_HW_RES_IN_NS(0x60D, val) /* SNB onwards */
#define GET_PC3_RES(val) GET_HW_RES_IN_NS(0x3F8, val)
#define GET_PC6_RES(val) GET_HW_RES_IN_NS(0x3F9, val)
@@ -73,6 +74,7 @@
#define GET_CC3_RES(val) GET_HW_RES_IN_NS(0x3FC, val)
#define GET_CC6_RES(val) GET_HW_RES_IN_NS(0x3FD, val)
#define GET_CC7_RES(val) GET_HW_RES_IN_NS(0x3FE, val) /* SNB onwards */
+#define PHI_CC6_RES(val) GET_HW_RES_IN_NS(0x3FF, val) /* Xeon Phi only */
static void lapic_timer_nop(void) { }
void (*__read_mostly lapic_timer_off)(void);
@@ -122,6 +124,8 @@ struct acpi_processor_power *__read_most
struct hw_residencies
{
+ uint64_t mc0;
+ uint64_t mc6;
uint64_t pc2;
uint64_t pc3;
uint64_t pc4;
@@ -162,8 +166,11 @@ static void do_get_hw_residencies(void *
case 0x3C:
case 0x3F:
case 0x46:
- /* future */
+ /* Broadwell */
case 0x3D:
+ case 0x4F:
+ case 0x56:
+ /* future */
case 0x4E:
GET_PC2_RES(hw_res->pc2);
GET_CC7_RES(hw_res->cc7);
@@ -183,6 +190,16 @@ static void do_get_hw_residencies(void *
GET_CC3_RES(hw_res->cc3);
GET_CC6_RES(hw_res->cc6);
break;
+ /* next gen Xeon Phi */
+ case 0x57:
+ GET_CC3_RES(hw_res->mc0); /* abusing GET_CC3_RES */
+ GET_CC6_RES(hw_res->mc6); /* abusing GET_CC6_RES */
+ GET_PC2_RES(hw_res->pc2);
+ GET_PC3_RES(hw_res->pc3);
+ GET_PC6_RES(hw_res->pc6);
+ GET_PC7_RES(hw_res->pc7);
+ PHI_CC6_RES(hw_res->cc6);
+ break;
/* various Atoms */
case 0x27:
GET_PC3_RES(hw_res->pc2); /* abusing GET_PC3_RES */
@@ -191,10 +208,13 @@ static void do_get_hw_residencies(void *
break;
/* Silvermont */
case 0x37:
+ GET_MC6_RES(hw_res->mc6);
case 0x4A:
case 0x4D:
case 0x5A:
case 0x5D:
+ /* Airmont */
+ case 0x4C:
GET_PC7_RES(hw_res->pc6); /* abusing GET_PC7_RES */
GET_CC1_RES(hw_res->cc1);
GET_CC6_RES(hw_res->cc6);
@@ -218,6 +238,9 @@ static void print_hw_residencies(uint32_
get_hw_residencies(cpu, &hw_res);
+ if ( hw_res.mc0 | hw_res.mc6 )
+ printk("MC0[%"PRIu64"] MC6[%"PRIu64"]\n",
+ hw_res.mc0, hw_res.mc6);
printk("PC2[%"PRIu64"] PC%d[%"PRIu64"] PC6[%"PRIu64"] PC7[%"PRIu64"]\n",
hw_res.pc2,
hw_res.pc4 ? 4 : 3, hw_res.pc4 ?: hw_res.pc3,
--- a/xen/arch/x86/hvm/vmx/vmx.c
+++ b/xen/arch/x86/hvm/vmx/vmx.c
@@ -2055,14 +2055,20 @@ static const struct lbr_info *last_branc
case 58: case 62:
/* Haswell */
case 60: case 63: case 69: case 70:
+ /* Broadwell */
+ case 61: case 79: case 86:
/* future */
- case 61: case 78:
+ case 78:
return nh_lbr;
break;
/* Atom */
case 28: case 38: case 39: case 53: case 54:
/* Silvermont */
case 55: case 74: case 77: case 90: case 93:
+ /* next gen Xeon Phi */
+ case 87:
+ /* Airmont */
+ case 76:
return at_lbr;
break;
}
--- a/xen/arch/x86/hvm/vmx/vpmu_core2.c
+++ b/xen/arch/x86/hvm/vmx/vpmu_core2.c
@@ -859,9 +859,16 @@ int vmx_vpmu_initialise(struct vcpu *v,
case 0x45:
case 0x46:
- /* future: */
+ /* Broadwell */
case 0x3d:
+ case 0x4f:
+ case 0x56:
+
+ /* future: */
case 0x4e:
+
+ /* next gen Xeon Phi */
+ case 0x57:
ret = core2_vpmu_initialise(v, vpmu_flags);
if ( !ret )
vpmu->arch_vpmu_ops = &core2_vpmu_ops;
[-- Attachment #2: x86-Intel-CPU-models.patch --]
[-- Type: text/plain, Size: 4516 bytes --]
x86: support newer Intel CPU models
This just follows what the January 2015 edition of the SDM documents,
with additional clarification from Intel:
- Broadwell models 0x4f and 0x56 don't cross-reference other tables,
but should be treated like other Boradwell (0x3d),
- Xeon Phi model 0x57 lists LASTBRANCH_TOS but not where the actual
stack is. Being told it's Silvermont based, attach it there.
Signed-off-by: Jan Beulich <jbeulich@suse.com>
--- a/xen/arch/x86/acpi/cpu_idle.c
+++ b/xen/arch/x86/acpi/cpu_idle.c
@@ -62,6 +62,7 @@
#define GET_HW_RES_IN_NS(msr, val) \
do { rdmsrl(msr, val); val = tsc_ticks2ns(val); } while( 0 )
+#define GET_MC6_RES(val) GET_HW_RES_IN_NS(0x664, val) /* Atom E3000 only */
#define GET_PC2_RES(val) GET_HW_RES_IN_NS(0x60D, val) /* SNB onwards */
#define GET_PC3_RES(val) GET_HW_RES_IN_NS(0x3F8, val)
#define GET_PC6_RES(val) GET_HW_RES_IN_NS(0x3F9, val)
@@ -73,6 +74,7 @@
#define GET_CC3_RES(val) GET_HW_RES_IN_NS(0x3FC, val)
#define GET_CC6_RES(val) GET_HW_RES_IN_NS(0x3FD, val)
#define GET_CC7_RES(val) GET_HW_RES_IN_NS(0x3FE, val) /* SNB onwards */
+#define PHI_CC6_RES(val) GET_HW_RES_IN_NS(0x3FF, val) /* Xeon Phi only */
static void lapic_timer_nop(void) { }
void (*__read_mostly lapic_timer_off)(void);
@@ -122,6 +124,8 @@ struct acpi_processor_power *__read_most
struct hw_residencies
{
+ uint64_t mc0;
+ uint64_t mc6;
uint64_t pc2;
uint64_t pc3;
uint64_t pc4;
@@ -162,8 +166,11 @@ static void do_get_hw_residencies(void *
case 0x3C:
case 0x3F:
case 0x46:
- /* future */
+ /* Broadwell */
case 0x3D:
+ case 0x4F:
+ case 0x56:
+ /* future */
case 0x4E:
GET_PC2_RES(hw_res->pc2);
GET_CC7_RES(hw_res->cc7);
@@ -183,6 +190,16 @@ static void do_get_hw_residencies(void *
GET_CC3_RES(hw_res->cc3);
GET_CC6_RES(hw_res->cc6);
break;
+ /* next gen Xeon Phi */
+ case 0x57:
+ GET_CC3_RES(hw_res->mc0); /* abusing GET_CC3_RES */
+ GET_CC6_RES(hw_res->mc6); /* abusing GET_CC6_RES */
+ GET_PC2_RES(hw_res->pc2);
+ GET_PC3_RES(hw_res->pc3);
+ GET_PC6_RES(hw_res->pc6);
+ GET_PC7_RES(hw_res->pc7);
+ PHI_CC6_RES(hw_res->cc6);
+ break;
/* various Atoms */
case 0x27:
GET_PC3_RES(hw_res->pc2); /* abusing GET_PC3_RES */
@@ -191,10 +208,13 @@ static void do_get_hw_residencies(void *
break;
/* Silvermont */
case 0x37:
+ GET_MC6_RES(hw_res->mc6);
case 0x4A:
case 0x4D:
case 0x5A:
case 0x5D:
+ /* Airmont */
+ case 0x4C:
GET_PC7_RES(hw_res->pc6); /* abusing GET_PC7_RES */
GET_CC1_RES(hw_res->cc1);
GET_CC6_RES(hw_res->cc6);
@@ -218,6 +238,9 @@ static void print_hw_residencies(uint32_
get_hw_residencies(cpu, &hw_res);
+ if ( hw_res.mc0 | hw_res.mc6 )
+ printk("MC0[%"PRIu64"] MC6[%"PRIu64"]\n",
+ hw_res.mc0, hw_res.mc6);
printk("PC2[%"PRIu64"] PC%d[%"PRIu64"] PC6[%"PRIu64"] PC7[%"PRIu64"]\n",
hw_res.pc2,
hw_res.pc4 ? 4 : 3, hw_res.pc4 ?: hw_res.pc3,
--- a/xen/arch/x86/hvm/vmx/vmx.c
+++ b/xen/arch/x86/hvm/vmx/vmx.c
@@ -2055,14 +2055,20 @@ static const struct lbr_info *last_branc
case 58: case 62:
/* Haswell */
case 60: case 63: case 69: case 70:
+ /* Broadwell */
+ case 61: case 79: case 86:
/* future */
- case 61: case 78:
+ case 78:
return nh_lbr;
break;
/* Atom */
case 28: case 38: case 39: case 53: case 54:
/* Silvermont */
case 55: case 74: case 77: case 90: case 93:
+ /* next gen Xeon Phi */
+ case 87:
+ /* Airmont */
+ case 76:
return at_lbr;
break;
}
--- a/xen/arch/x86/hvm/vmx/vpmu_core2.c
+++ b/xen/arch/x86/hvm/vmx/vpmu_core2.c
@@ -859,9 +859,16 @@ int vmx_vpmu_initialise(struct vcpu *v,
case 0x45:
case 0x46:
- /* future: */
+ /* Broadwell */
case 0x3d:
+ case 0x4f:
+ case 0x56:
+
+ /* future: */
case 0x4e:
+
+ /* next gen Xeon Phi */
+ case 0x57:
ret = core2_vpmu_initialise(v, vpmu_flags);
if ( !ret )
vpmu->arch_vpmu_ops = &core2_vpmu_ops;
[-- Attachment #3: Type: text/plain, Size: 126 bytes --]
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http://lists.xen.org/xen-devel
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH] x86: support newer Intel CPU models
2015-03-23 15:44 [PATCH] x86: support newer Intel CPU models Jan Beulich
@ 2015-03-24 0:51 ` Tian, Kevin
0 siblings, 0 replies; 5+ messages in thread
From: Tian, Kevin @ 2015-03-24 0:51 UTC (permalink / raw)
To: Jan Beulich, xen-devel
Cc: Andrew Cooper, Keir Fraser, Nakajima, Jun, Dugger, Donald D
> From: Jan Beulich [mailto:JBeulich@suse.com]
> Sent: Monday, March 23, 2015 11:44 PM
>
> This just follows what the January 2015 edition of the SDM documents,
> with additional clarification from Intel:
> - Broadwell models 0x4f and 0x56 don't cross-reference other tables,
> but should be treated like other Boradwell (0x3d),
> - Xeon Phi model 0x57 lists LASTBRANCH_TOS but not where the actual
> stack is. Being told it's Silvermont based, attach it there.
>
> Signed-off-by: Jan Beulich <jbeulich@suse.com>
Acked-by: Kevin Tian <kevin.tian@intel.com>
>
> --- a/xen/arch/x86/acpi/cpu_idle.c
> +++ b/xen/arch/x86/acpi/cpu_idle.c
> @@ -62,6 +62,7 @@
>
> #define GET_HW_RES_IN_NS(msr, val) \
> do { rdmsrl(msr, val); val = tsc_ticks2ns(val); } while( 0 )
> +#define GET_MC6_RES(val) GET_HW_RES_IN_NS(0x664, val) /* Atom
> E3000 only */
> #define GET_PC2_RES(val) GET_HW_RES_IN_NS(0x60D, val) /* SNB
> onwards */
> #define GET_PC3_RES(val) GET_HW_RES_IN_NS(0x3F8, val)
> #define GET_PC6_RES(val) GET_HW_RES_IN_NS(0x3F9, val)
> @@ -73,6 +74,7 @@
> #define GET_CC3_RES(val) GET_HW_RES_IN_NS(0x3FC, val)
> #define GET_CC6_RES(val) GET_HW_RES_IN_NS(0x3FD, val)
> #define GET_CC7_RES(val) GET_HW_RES_IN_NS(0x3FE, val) /* SNB
> onwards */
> +#define PHI_CC6_RES(val) GET_HW_RES_IN_NS(0x3FF, val) /* Xeon Phi only
> */
>
> static void lapic_timer_nop(void) { }
> void (*__read_mostly lapic_timer_off)(void);
> @@ -122,6 +124,8 @@ struct acpi_processor_power *__read_most
>
> struct hw_residencies
> {
> + uint64_t mc0;
> + uint64_t mc6;
> uint64_t pc2;
> uint64_t pc3;
> uint64_t pc4;
> @@ -162,8 +166,11 @@ static void do_get_hw_residencies(void *
> case 0x3C:
> case 0x3F:
> case 0x46:
> - /* future */
> + /* Broadwell */
> case 0x3D:
> + case 0x4F:
> + case 0x56:
> + /* future */
> case 0x4E:
> GET_PC2_RES(hw_res->pc2);
> GET_CC7_RES(hw_res->cc7);
> @@ -183,6 +190,16 @@ static void do_get_hw_residencies(void *
> GET_CC3_RES(hw_res->cc3);
> GET_CC6_RES(hw_res->cc6);
> break;
> + /* next gen Xeon Phi */
> + case 0x57:
> + GET_CC3_RES(hw_res->mc0); /* abusing GET_CC3_RES */
> + GET_CC6_RES(hw_res->mc6); /* abusing GET_CC6_RES */
> + GET_PC2_RES(hw_res->pc2);
> + GET_PC3_RES(hw_res->pc3);
> + GET_PC6_RES(hw_res->pc6);
> + GET_PC7_RES(hw_res->pc7);
> + PHI_CC6_RES(hw_res->cc6);
> + break;
> /* various Atoms */
> case 0x27:
> GET_PC3_RES(hw_res->pc2); /* abusing GET_PC3_RES */
> @@ -191,10 +208,13 @@ static void do_get_hw_residencies(void *
> break;
> /* Silvermont */
> case 0x37:
> + GET_MC6_RES(hw_res->mc6);
> case 0x4A:
> case 0x4D:
> case 0x5A:
> case 0x5D:
> + /* Airmont */
> + case 0x4C:
> GET_PC7_RES(hw_res->pc6); /* abusing GET_PC7_RES */
> GET_CC1_RES(hw_res->cc1);
> GET_CC6_RES(hw_res->cc6);
> @@ -218,6 +238,9 @@ static void print_hw_residencies(uint32_
>
> get_hw_residencies(cpu, &hw_res);
>
> + if ( hw_res.mc0 | hw_res.mc6 )
> + printk("MC0[%"PRIu64"] MC6[%"PRIu64"]\n",
> + hw_res.mc0, hw_res.mc6);
> printk("PC2[%"PRIu64"] PC%d[%"PRIu64"] PC6[%"PRIu64"]
> PC7[%"PRIu64"]\n",
> hw_res.pc2,
> hw_res.pc4 ? 4 : 3, hw_res.pc4 ?: hw_res.pc3,
> --- a/xen/arch/x86/hvm/vmx/vmx.c
> +++ b/xen/arch/x86/hvm/vmx/vmx.c
> @@ -2055,14 +2055,20 @@ static const struct lbr_info *last_branc
> case 58: case 62:
> /* Haswell */
> case 60: case 63: case 69: case 70:
> + /* Broadwell */
> + case 61: case 79: case 86:
> /* future */
> - case 61: case 78:
> + case 78:
> return nh_lbr;
> break;
> /* Atom */
> case 28: case 38: case 39: case 53: case 54:
> /* Silvermont */
> case 55: case 74: case 77: case 90: case 93:
> + /* next gen Xeon Phi */
> + case 87:
> + /* Airmont */
> + case 76:
> return at_lbr;
> break;
> }
> --- a/xen/arch/x86/hvm/vmx/vpmu_core2.c
> +++ b/xen/arch/x86/hvm/vmx/vpmu_core2.c
> @@ -859,9 +859,16 @@ int vmx_vpmu_initialise(struct vcpu *v,
> case 0x45:
> case 0x46:
>
> - /* future: */
> + /* Broadwell */
> case 0x3d:
> + case 0x4f:
> + case 0x56:
> +
> + /* future: */
> case 0x4e:
> +
> + /* next gen Xeon Phi */
> + case 0x57:
> ret = core2_vpmu_initialise(v, vpmu_flags);
> if ( !ret )
> vpmu->arch_vpmu_ops = &core2_vpmu_ops;
>
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH] x86: support newer Intel CPU models
2016-08-03 8:38 Jan Beulich
2016-08-03 9:25 ` Andrew Cooper
@ 2016-08-04 8:13 ` Tian, Kevin
1 sibling, 0 replies; 5+ messages in thread
From: Tian, Kevin @ 2016-08-04 8:13 UTC (permalink / raw)
To: Jan Beulich, xen-devel; +Cc: Andrew Cooper, Lai, Paul C, Nakajima, Jun
> From: Jan Beulich [mailto:JBeulich@suse.com]
> Sent: Wednesday, August 03, 2016 4:38 PM
>
> ... as per the June 2016 edition of the SDM.
>
> Also remove a couple of dead break statements as well as unused
> *MSR_PM_LASTBRANCH* #define-s.
>
> Signed-off-by: Jan Beulich <jbeulich@suse.com>
Acked-by: Kevin Tian <kevin.tian@intel.com>
_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xen.org
https://lists.xen.org/xen-devel
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH] x86: support newer Intel CPU models
2016-08-03 8:38 Jan Beulich
@ 2016-08-03 9:25 ` Andrew Cooper
2016-08-04 8:13 ` Tian, Kevin
1 sibling, 0 replies; 5+ messages in thread
From: Andrew Cooper @ 2016-08-03 9:25 UTC (permalink / raw)
To: Jan Beulich, xen-devel; +Cc: Kevin Tian, Paul C Lai, Jun Nakajima
On 03/08/16 09:38, Jan Beulich wrote:
> ... as per the June 2016 edition of the SDM.
>
> Also remove a couple of dead break statements as well as unused
> *MSR_PM_LASTBRANCH* #define-s.
>
> Signed-off-by: Jan Beulich <jbeulich@suse.com>
Acked-by: Andrew Cooper <andrew.cooper3@citrix.com>
_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xen.org
https://lists.xen.org/xen-devel
^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH] x86: support newer Intel CPU models
@ 2016-08-03 8:38 Jan Beulich
2016-08-03 9:25 ` Andrew Cooper
2016-08-04 8:13 ` Tian, Kevin
0 siblings, 2 replies; 5+ messages in thread
From: Jan Beulich @ 2016-08-03 8:38 UTC (permalink / raw)
To: xen-devel; +Cc: Andrew Cooper, Kevin Tian, Paul C Lai, Jun Nakajima
[-- Attachment #1: Type: text/plain, Size: 6778 bytes --]
... as per the June 2016 edition of the SDM.
Also remove a couple of dead break statements as well as unused
*MSR_PM_LASTBRANCH* #define-s.
Signed-off-by: Jan Beulich <jbeulich@suse.com>
--- a/xen/arch/x86/acpi/cpu_idle.c
+++ b/xen/arch/x86/acpi/cpu_idle.c
@@ -61,14 +61,14 @@
#define GET_HW_RES_IN_NS(msr, val) \
do { rdmsrl(msr, val); val = tsc_ticks2ns(val); } while( 0 )
-#define GET_MC6_RES(val) GET_HW_RES_IN_NS(0x664, val) /* Atom E3000 only */
+#define GET_MC6_RES(val) GET_HW_RES_IN_NS(0x664, val)
#define GET_PC2_RES(val) GET_HW_RES_IN_NS(0x60D, val) /* SNB onwards */
#define GET_PC3_RES(val) GET_HW_RES_IN_NS(0x3F8, val)
#define GET_PC6_RES(val) GET_HW_RES_IN_NS(0x3F9, val)
#define GET_PC7_RES(val) GET_HW_RES_IN_NS(0x3FA, val)
-#define GET_PC8_RES(val) GET_HW_RES_IN_NS(0x630, val) /* some Haswells only */
-#define GET_PC9_RES(val) GET_HW_RES_IN_NS(0x631, val) /* some Haswells only */
-#define GET_PC10_RES(val) GET_HW_RES_IN_NS(0x632, val) /* some Haswells only */
+#define GET_PC8_RES(val) GET_HW_RES_IN_NS(0x630, val)
+#define GET_PC9_RES(val) GET_HW_RES_IN_NS(0x631, val)
+#define GET_PC10_RES(val) GET_HW_RES_IN_NS(0x632, val)
#define GET_CC1_RES(val) GET_HW_RES_IN_NS(0x660, val) /* Silvermont only */
#define GET_CC3_RES(val) GET_HW_RES_IN_NS(0x3FC, val)
#define GET_CC6_RES(val) GET_HW_RES_IN_NS(0x3FD, val)
@@ -142,6 +142,8 @@ static void do_get_hw_residencies(void *
{
/* 4th generation Intel Core (Haswell) */
case 0x45:
+ /* Xeon E5/E7 v4 (Broadwell) */
+ case 0x4F:
GET_PC8_RES(hw_res->pc8);
GET_PC9_RES(hw_res->pc9);
GET_PC10_RES(hw_res->pc10);
@@ -158,10 +160,11 @@ static void do_get_hw_residencies(void *
case 0x46:
/* Broadwell */
case 0x3D:
- case 0x4F:
+ case 0x47:
case 0x56:
- /* future */
+ /* Skylake */
case 0x4E:
+ case 0x5E:
GET_PC2_RES(hw_res->pc2);
GET_CC7_RES(hw_res->cc7);
/* fall through */
@@ -198,18 +201,28 @@ static void do_get_hw_residencies(void *
break;
/* Silvermont */
case 0x37:
- GET_MC6_RES(hw_res->mc6);
- /* fall through */
case 0x4A:
case 0x4D:
case 0x5A:
case 0x5D:
/* Airmont */
case 0x4C:
+ GET_MC6_RES(hw_res->mc6);
GET_PC7_RES(hw_res->pc6); /* abusing GET_PC7_RES */
GET_CC1_RES(hw_res->cc1);
GET_CC6_RES(hw_res->cc6);
break;
+ /* Goldmont */
+ case 0x5C:
+ case 0x5F:
+ GET_PC2_RES(hw_res->pc2);
+ GET_PC3_RES(hw_res->pc3);
+ GET_PC6_RES(hw_res->pc6);
+ GET_PC10_RES(hw_res->pc10);
+ GET_CC1_RES(hw_res->cc1);
+ GET_CC3_RES(hw_res->cc3);
+ GET_CC6_RES(hw_res->cc6);
+ break;
}
}
--- a/xen/arch/x86/hvm/vmx/vmx.c
+++ b/xen/arch/x86/hvm/vmx/vmx.c
@@ -2529,6 +2529,14 @@ static const struct lbr_info {
{ MSR_P4_LASTBRANCH_0_FROM_LIP, NUM_MSR_P4_LASTBRANCH_FROM_TO },
{ MSR_P4_LASTBRANCH_0_TO_LIP, NUM_MSR_P4_LASTBRANCH_FROM_TO },
{ 0, 0 }
+}, sk_lbr[] = {
+ { MSR_IA32_LASTINTFROMIP, 1 },
+ { MSR_IA32_LASTINTTOIP, 1 },
+ { MSR_SKL_LASTBRANCH_TOS, 1 },
+ { MSR_SKL_LASTBRANCH_0_FROM_IP, NUM_MSR_SKL_LASTBRANCH },
+ { MSR_SKL_LASTBRANCH_0_TO_IP, NUM_MSR_SKL_LASTBRANCH },
+ { MSR_SKL_LASTBRANCH_0_INFO, NUM_MSR_SKL_LASTBRANCH },
+ { 0, 0 }
}, at_lbr[] = {
{ MSR_IA32_LASTINTFROMIP, 1 },
{ MSR_IA32_LASTINTTOIP, 1 },
@@ -2536,6 +2544,13 @@ static const struct lbr_info {
{ MSR_C2_LASTBRANCH_0_FROM_IP, NUM_MSR_ATOM_LASTBRANCH_FROM_TO },
{ MSR_C2_LASTBRANCH_0_TO_IP, NUM_MSR_ATOM_LASTBRANCH_FROM_TO },
{ 0, 0 }
+}, gm_lbr[] = {
+ { MSR_IA32_LASTINTFROMIP, 1 },
+ { MSR_IA32_LASTINTTOIP, 1 },
+ { MSR_GM_LASTBRANCH_TOS, 1 },
+ { MSR_GM_LASTBRANCH_0_FROM_IP, NUM_MSR_GM_LASTBRANCH_FROM_TO },
+ { MSR_GM_LASTBRANCH_0_TO_IP, NUM_MSR_GM_LASTBRANCH_FROM_TO },
+ { 0, 0 }
};
static const struct lbr_info *last_branch_msr_get(void)
@@ -2550,7 +2565,6 @@ static const struct lbr_info *last_branc
/* Enhanced Core */
case 23:
return c2_lbr;
- break;
/* Nehalem */
case 26: case 30: case 31: case 46:
/* Westmere */
@@ -2562,11 +2576,13 @@ static const struct lbr_info *last_branc
/* Haswell */
case 60: case 63: case 69: case 70:
/* Broadwell */
- case 61: case 79: case 86:
- /* future */
- case 78:
+ case 61: case 71: case 79: case 86:
return nh_lbr;
- break;
+ /* Skylake */
+ case 78: case 94:
+ /* future */
+ case 142: case 158:
+ return sk_lbr;
/* Atom */
case 28: case 38: case 39: case 53: case 54:
/* Silvermont */
@@ -2576,7 +2592,9 @@ static const struct lbr_info *last_branc
/* Airmont */
case 76:
return at_lbr;
- break;
+ /* Goldmont */
+ case 92: case 95:
+ return gm_lbr;
}
break;
@@ -2586,7 +2604,6 @@ static const struct lbr_info *last_branc
/* Pentium4/Xeon with em64t */
case 3: case 4: case 6:
return p4_lbr;
- break;
}
break;
}
--- a/xen/include/asm-x86/msr-index.h
+++ b/xen/include/asm-x86/msr-index.h
@@ -460,11 +460,6 @@
#define MSR_P4_LASTBRANCH_0_TO_LIP 0x000006c0
#define NUM_MSR_P4_LASTBRANCH_FROM_TO 16
-/* Pentium M (and Core) last-branch recording */
-#define MSR_PM_LASTBRANCH_TOS 0x000001c9
-#define MSR_PM_LASTBRANCH_0 0x00000040
-#define NUM_MSR_PM_LASTBRANCH 8
-
/* Core 2 and Atom last-branch recording */
#define MSR_C2_LASTBRANCH_TOS 0x000001c9
#define MSR_C2_LASTBRANCH_0_FROM_IP 0x00000040
@@ -472,6 +467,19 @@
#define NUM_MSR_C2_LASTBRANCH_FROM_TO 4
#define NUM_MSR_ATOM_LASTBRANCH_FROM_TO 8
+/* Skylake (and newer) last-branch recording */
+#define MSR_SKL_LASTBRANCH_TOS 0x000001c9
+#define MSR_SKL_LASTBRANCH_0_FROM_IP 0x00000680
+#define MSR_SKL_LASTBRANCH_0_TO_IP 0x000006c0
+#define MSR_SKL_LASTBRANCH_0_INFO 0x00000dc0
+#define NUM_MSR_SKL_LASTBRANCH 32
+
+/* Goldmont last-branch recording */
+#define MSR_GM_LASTBRANCH_TOS 0x000001c9
+#define MSR_GM_LASTBRANCH_0_FROM_IP 0x00000680
+#define MSR_GM_LASTBRANCH_0_TO_IP 0x000006c0
+#define NUM_MSR_GM_LASTBRANCH_FROM_TO 32
+
/* Intel Core-based CPU performance counters */
#define MSR_CORE_PERF_FIXED_CTR0 0x00000309
#define MSR_CORE_PERF_FIXED_CTR1 0x0000030a
[-- Attachment #2: x86-Intel-CPUs.patch --]
[-- Type: text/plain, Size: 6813 bytes --]
x86: support newer Intel CPU models
... as per the June 2016 edition of the SDM.
Also remove a couple of dead break statements as well as unused
*MSR_PM_LASTBRANCH* #define-s.
Signed-off-by: Jan Beulich <jbeulich@suse.com>
--- a/xen/arch/x86/acpi/cpu_idle.c
+++ b/xen/arch/x86/acpi/cpu_idle.c
@@ -61,14 +61,14 @@
#define GET_HW_RES_IN_NS(msr, val) \
do { rdmsrl(msr, val); val = tsc_ticks2ns(val); } while( 0 )
-#define GET_MC6_RES(val) GET_HW_RES_IN_NS(0x664, val) /* Atom E3000 only */
+#define GET_MC6_RES(val) GET_HW_RES_IN_NS(0x664, val)
#define GET_PC2_RES(val) GET_HW_RES_IN_NS(0x60D, val) /* SNB onwards */
#define GET_PC3_RES(val) GET_HW_RES_IN_NS(0x3F8, val)
#define GET_PC6_RES(val) GET_HW_RES_IN_NS(0x3F9, val)
#define GET_PC7_RES(val) GET_HW_RES_IN_NS(0x3FA, val)
-#define GET_PC8_RES(val) GET_HW_RES_IN_NS(0x630, val) /* some Haswells only */
-#define GET_PC9_RES(val) GET_HW_RES_IN_NS(0x631, val) /* some Haswells only */
-#define GET_PC10_RES(val) GET_HW_RES_IN_NS(0x632, val) /* some Haswells only */
+#define GET_PC8_RES(val) GET_HW_RES_IN_NS(0x630, val)
+#define GET_PC9_RES(val) GET_HW_RES_IN_NS(0x631, val)
+#define GET_PC10_RES(val) GET_HW_RES_IN_NS(0x632, val)
#define GET_CC1_RES(val) GET_HW_RES_IN_NS(0x660, val) /* Silvermont only */
#define GET_CC3_RES(val) GET_HW_RES_IN_NS(0x3FC, val)
#define GET_CC6_RES(val) GET_HW_RES_IN_NS(0x3FD, val)
@@ -142,6 +142,8 @@ static void do_get_hw_residencies(void *
{
/* 4th generation Intel Core (Haswell) */
case 0x45:
+ /* Xeon E5/E7 v4 (Broadwell) */
+ case 0x4F:
GET_PC8_RES(hw_res->pc8);
GET_PC9_RES(hw_res->pc9);
GET_PC10_RES(hw_res->pc10);
@@ -158,10 +160,11 @@ static void do_get_hw_residencies(void *
case 0x46:
/* Broadwell */
case 0x3D:
- case 0x4F:
+ case 0x47:
case 0x56:
- /* future */
+ /* Skylake */
case 0x4E:
+ case 0x5E:
GET_PC2_RES(hw_res->pc2);
GET_CC7_RES(hw_res->cc7);
/* fall through */
@@ -198,18 +201,28 @@ static void do_get_hw_residencies(void *
break;
/* Silvermont */
case 0x37:
- GET_MC6_RES(hw_res->mc6);
- /* fall through */
case 0x4A:
case 0x4D:
case 0x5A:
case 0x5D:
/* Airmont */
case 0x4C:
+ GET_MC6_RES(hw_res->mc6);
GET_PC7_RES(hw_res->pc6); /* abusing GET_PC7_RES */
GET_CC1_RES(hw_res->cc1);
GET_CC6_RES(hw_res->cc6);
break;
+ /* Goldmont */
+ case 0x5C:
+ case 0x5F:
+ GET_PC2_RES(hw_res->pc2);
+ GET_PC3_RES(hw_res->pc3);
+ GET_PC6_RES(hw_res->pc6);
+ GET_PC10_RES(hw_res->pc10);
+ GET_CC1_RES(hw_res->cc1);
+ GET_CC3_RES(hw_res->cc3);
+ GET_CC6_RES(hw_res->cc6);
+ break;
}
}
--- a/xen/arch/x86/hvm/vmx/vmx.c
+++ b/xen/arch/x86/hvm/vmx/vmx.c
@@ -2529,6 +2529,14 @@ static const struct lbr_info {
{ MSR_P4_LASTBRANCH_0_FROM_LIP, NUM_MSR_P4_LASTBRANCH_FROM_TO },
{ MSR_P4_LASTBRANCH_0_TO_LIP, NUM_MSR_P4_LASTBRANCH_FROM_TO },
{ 0, 0 }
+}, sk_lbr[] = {
+ { MSR_IA32_LASTINTFROMIP, 1 },
+ { MSR_IA32_LASTINTTOIP, 1 },
+ { MSR_SKL_LASTBRANCH_TOS, 1 },
+ { MSR_SKL_LASTBRANCH_0_FROM_IP, NUM_MSR_SKL_LASTBRANCH },
+ { MSR_SKL_LASTBRANCH_0_TO_IP, NUM_MSR_SKL_LASTBRANCH },
+ { MSR_SKL_LASTBRANCH_0_INFO, NUM_MSR_SKL_LASTBRANCH },
+ { 0, 0 }
}, at_lbr[] = {
{ MSR_IA32_LASTINTFROMIP, 1 },
{ MSR_IA32_LASTINTTOIP, 1 },
@@ -2536,6 +2544,13 @@ static const struct lbr_info {
{ MSR_C2_LASTBRANCH_0_FROM_IP, NUM_MSR_ATOM_LASTBRANCH_FROM_TO },
{ MSR_C2_LASTBRANCH_0_TO_IP, NUM_MSR_ATOM_LASTBRANCH_FROM_TO },
{ 0, 0 }
+}, gm_lbr[] = {
+ { MSR_IA32_LASTINTFROMIP, 1 },
+ { MSR_IA32_LASTINTTOIP, 1 },
+ { MSR_GM_LASTBRANCH_TOS, 1 },
+ { MSR_GM_LASTBRANCH_0_FROM_IP, NUM_MSR_GM_LASTBRANCH_FROM_TO },
+ { MSR_GM_LASTBRANCH_0_TO_IP, NUM_MSR_GM_LASTBRANCH_FROM_TO },
+ { 0, 0 }
};
static const struct lbr_info *last_branch_msr_get(void)
@@ -2550,7 +2565,6 @@ static const struct lbr_info *last_branc
/* Enhanced Core */
case 23:
return c2_lbr;
- break;
/* Nehalem */
case 26: case 30: case 31: case 46:
/* Westmere */
@@ -2562,11 +2576,13 @@ static const struct lbr_info *last_branc
/* Haswell */
case 60: case 63: case 69: case 70:
/* Broadwell */
- case 61: case 79: case 86:
- /* future */
- case 78:
+ case 61: case 71: case 79: case 86:
return nh_lbr;
- break;
+ /* Skylake */
+ case 78: case 94:
+ /* future */
+ case 142: case 158:
+ return sk_lbr;
/* Atom */
case 28: case 38: case 39: case 53: case 54:
/* Silvermont */
@@ -2576,7 +2592,9 @@ static const struct lbr_info *last_branc
/* Airmont */
case 76:
return at_lbr;
- break;
+ /* Goldmont */
+ case 92: case 95:
+ return gm_lbr;
}
break;
@@ -2586,7 +2604,6 @@ static const struct lbr_info *last_branc
/* Pentium4/Xeon with em64t */
case 3: case 4: case 6:
return p4_lbr;
- break;
}
break;
}
--- a/xen/include/asm-x86/msr-index.h
+++ b/xen/include/asm-x86/msr-index.h
@@ -460,11 +460,6 @@
#define MSR_P4_LASTBRANCH_0_TO_LIP 0x000006c0
#define NUM_MSR_P4_LASTBRANCH_FROM_TO 16
-/* Pentium M (and Core) last-branch recording */
-#define MSR_PM_LASTBRANCH_TOS 0x000001c9
-#define MSR_PM_LASTBRANCH_0 0x00000040
-#define NUM_MSR_PM_LASTBRANCH 8
-
/* Core 2 and Atom last-branch recording */
#define MSR_C2_LASTBRANCH_TOS 0x000001c9
#define MSR_C2_LASTBRANCH_0_FROM_IP 0x00000040
@@ -472,6 +467,19 @@
#define NUM_MSR_C2_LASTBRANCH_FROM_TO 4
#define NUM_MSR_ATOM_LASTBRANCH_FROM_TO 8
+/* Skylake (and newer) last-branch recording */
+#define MSR_SKL_LASTBRANCH_TOS 0x000001c9
+#define MSR_SKL_LASTBRANCH_0_FROM_IP 0x00000680
+#define MSR_SKL_LASTBRANCH_0_TO_IP 0x000006c0
+#define MSR_SKL_LASTBRANCH_0_INFO 0x00000dc0
+#define NUM_MSR_SKL_LASTBRANCH 32
+
+/* Goldmont last-branch recording */
+#define MSR_GM_LASTBRANCH_TOS 0x000001c9
+#define MSR_GM_LASTBRANCH_0_FROM_IP 0x00000680
+#define MSR_GM_LASTBRANCH_0_TO_IP 0x000006c0
+#define NUM_MSR_GM_LASTBRANCH_FROM_TO 32
+
/* Intel Core-based CPU performance counters */
#define MSR_CORE_PERF_FIXED_CTR0 0x00000309
#define MSR_CORE_PERF_FIXED_CTR1 0x0000030a
[-- Attachment #3: Type: text/plain, Size: 127 bytes --]
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Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2015-03-23 15:44 [PATCH] x86: support newer Intel CPU models Jan Beulich
2015-03-24 0:51 ` Tian, Kevin
2016-08-03 8:38 Jan Beulich
2016-08-03 9:25 ` Andrew Cooper
2016-08-04 8:13 ` Tian, Kevin
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