* [PATCH] x86/Intel: Broadwell doesn't have PKG_C{8, 9, 10}_RESIDENCY MSRs
@ 2016-09-19 7:51 Jan Beulich
2016-09-19 9:29 ` Tian, Kevin
0 siblings, 1 reply; 2+ messages in thread
From: Jan Beulich @ 2016-09-19 7:51 UTC (permalink / raw)
To: xen-devel; +Cc: Andrew Cooper, Kevin Tian, Jun Nakajima
[-- Attachment #1: Type: text/plain, Size: 1649 bytes --]
According to
https://lists.xenproject.org/archives/html/xen-devel/2016-09/msg01797.html
this partially reverts commit 350bc1a9d4 ("x86: support newer Intel CPU
models") to account for the appearant earlier mis-documentation.
Signed-off-by: Jan Beulich <jbeulich@suse.com>
--- a/xen/arch/x86/acpi/cpu_idle.c
+++ b/xen/arch/x86/acpi/cpu_idle.c
@@ -66,9 +66,9 @@
#define GET_PC3_RES(val) GET_HW_RES_IN_NS(0x3F8, val)
#define GET_PC6_RES(val) GET_HW_RES_IN_NS(0x3F9, val)
#define GET_PC7_RES(val) GET_HW_RES_IN_NS(0x3FA, val)
-#define GET_PC8_RES(val) GET_HW_RES_IN_NS(0x630, val)
-#define GET_PC9_RES(val) GET_HW_RES_IN_NS(0x631, val)
-#define GET_PC10_RES(val) GET_HW_RES_IN_NS(0x632, val)
+#define GET_PC8_RES(val) GET_HW_RES_IN_NS(0x630, val) /* some Haswells only */
+#define GET_PC9_RES(val) GET_HW_RES_IN_NS(0x631, val) /* some Haswells only */
+#define GET_PC10_RES(val) GET_HW_RES_IN_NS(0x632, val) /* some Haswells only */
#define GET_CC1_RES(val) GET_HW_RES_IN_NS(0x660, val) /* Silvermont only */
#define GET_CC3_RES(val) GET_HW_RES_IN_NS(0x3FC, val)
#define GET_CC6_RES(val) GET_HW_RES_IN_NS(0x3FD, val)
@@ -142,8 +142,6 @@ static void do_get_hw_residencies(void *
{
/* 4th generation Intel Core (Haswell) */
case 0x45:
- /* Xeon E5/E7 v4 (Broadwell) */
- case 0x4F:
GET_PC8_RES(hw_res->pc8);
GET_PC9_RES(hw_res->pc9);
GET_PC10_RES(hw_res->pc10);
@@ -161,6 +159,7 @@ static void do_get_hw_residencies(void *
/* Broadwell */
case 0x3D:
case 0x47:
+ case 0x4F:
case 0x56:
/* Skylake */
case 0x4E:
[-- Attachment #2: x86-Broadwell-PC8-10.patch --]
[-- Type: text/plain, Size: 1708 bytes --]
x86/Intel: Broadwell doesn't have PKG_C{8,9,10}_RESIDENCY MSRs
According to
https://lists.xenproject.org/archives/html/xen-devel/2016-09/msg01797.html
this partially reverts commit 350bc1a9d4 ("x86: support newer Intel CPU
models") to account for the appearant earlier mis-documentation.
Signed-off-by: Jan Beulich <jbeulich@suse.com>
--- a/xen/arch/x86/acpi/cpu_idle.c
+++ b/xen/arch/x86/acpi/cpu_idle.c
@@ -66,9 +66,9 @@
#define GET_PC3_RES(val) GET_HW_RES_IN_NS(0x3F8, val)
#define GET_PC6_RES(val) GET_HW_RES_IN_NS(0x3F9, val)
#define GET_PC7_RES(val) GET_HW_RES_IN_NS(0x3FA, val)
-#define GET_PC8_RES(val) GET_HW_RES_IN_NS(0x630, val)
-#define GET_PC9_RES(val) GET_HW_RES_IN_NS(0x631, val)
-#define GET_PC10_RES(val) GET_HW_RES_IN_NS(0x632, val)
+#define GET_PC8_RES(val) GET_HW_RES_IN_NS(0x630, val) /* some Haswells only */
+#define GET_PC9_RES(val) GET_HW_RES_IN_NS(0x631, val) /* some Haswells only */
+#define GET_PC10_RES(val) GET_HW_RES_IN_NS(0x632, val) /* some Haswells only */
#define GET_CC1_RES(val) GET_HW_RES_IN_NS(0x660, val) /* Silvermont only */
#define GET_CC3_RES(val) GET_HW_RES_IN_NS(0x3FC, val)
#define GET_CC6_RES(val) GET_HW_RES_IN_NS(0x3FD, val)
@@ -142,8 +142,6 @@ static void do_get_hw_residencies(void *
{
/* 4th generation Intel Core (Haswell) */
case 0x45:
- /* Xeon E5/E7 v4 (Broadwell) */
- case 0x4F:
GET_PC8_RES(hw_res->pc8);
GET_PC9_RES(hw_res->pc9);
GET_PC10_RES(hw_res->pc10);
@@ -161,6 +159,7 @@ static void do_get_hw_residencies(void *
/* Broadwell */
case 0x3D:
case 0x47:
+ case 0x4F:
case 0x56:
/* Skylake */
case 0x4E:
[-- Attachment #3: Type: text/plain, Size: 127 bytes --]
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* Re: [PATCH] x86/Intel: Broadwell doesn't have PKG_C{8, 9, 10}_RESIDENCY MSRs
2016-09-19 7:51 [PATCH] x86/Intel: Broadwell doesn't have PKG_C{8, 9, 10}_RESIDENCY MSRs Jan Beulich
@ 2016-09-19 9:29 ` Tian, Kevin
0 siblings, 0 replies; 2+ messages in thread
From: Tian, Kevin @ 2016-09-19 9:29 UTC (permalink / raw)
To: Jan Beulich, xen-devel; +Cc: Andrew Cooper, Nakajima, Jun
> From: Jan Beulich [mailto:JBeulich@suse.com]
> Sent: Monday, September 19, 2016 3:52 PM
>
> According to
> https://lists.xenproject.org/archives/html/xen-devel/2016-09/msg01797.html
> this partially reverts commit 350bc1a9d4 ("x86: support newer Intel CPU
> models") to account for the appearant earlier mis-documentation.
>
> Signed-off-by: Jan Beulich <jbeulich@suse.com>
>
Acked-by: Kevin Tian <kevin.tian@intel.com>
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Xen-devel mailing list
Xen-devel@lists.xen.org
https://lists.xen.org/xen-devel
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2016-09-19 9:29 ` Tian, Kevin
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