* [ath9k-devel] Disabling CCA for ath9k
@ 2011-02-12 8:52 Sagar Bijwe
2011-02-15 19:49 ` [ath9k-devel] adjust the CCA (Clear Channel Assessment) value " Brandon Combs
0 siblings, 1 reply; 20+ messages in thread
From: Sagar Bijwe @ 2011-02-12 8:52 UTC (permalink / raw)
To: ath9k-devel
I wish to disable CCA for ath9k. Can anyone tell me how this can be
achieved? As far as I see it, modifying values of
AR9280_PHY_CCA_THRESH62
AR9280_PHY_CCA_THRESH62_S (present in phy.h)
should do.
-Sagar
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* [ath9k-devel] adjust the CCA (Clear Channel Assessment) value for ath9k
2011-02-12 8:52 [ath9k-devel] Disabling CCA for ath9k Sagar Bijwe
@ 2011-02-15 19:49 ` Brandon Combs
2011-02-16 13:17 ` Mohammed Shafi
2014-03-24 11:53 ` Javi Jap
0 siblings, 2 replies; 20+ messages in thread
From: Brandon Combs @ 2011-02-15 19:49 UTC (permalink / raw)
To: ath9k-devel
Sagar Bijwe <sag.bijwe <at> gmail.com> writes:
>
> I wish to disable CCA for ath9k. Can anyone tell me how this can be achieved?
As far as I see it, modifying values of?AR9280_PHY_CCA_THRESH62????
AR9280_PHY_CCA_THRESH62_S (present in phy.h)should do. -Sagar
> _______________________________________________
I also need to adjust the CCA (Clear Channel Assessment)value. Does anyone know
how to increase the CCA threshold so that one can get a node to send even when
it senses an unclear channel? Here is the code segments from
/source/drivers/net/wireless/ath/ath9k/ar9002_phy.h which I believe I need to
adjust to increase the CCA threshold but I am not quite sure how (thanks for any
help, Note: I am using AR9280 chip set):
127 #define AR_PHY_CCA 0x9864
128 #define AR_PHY_MINCCA_PWR 0x0FF80000
129 #define AR_PHY_MINCCA_PWR_S 19
130 #define AR_PHY_CCA_THRESH62 0x0007F000
131 #define AR_PHY_CCA_THRESH62_S 12
132 #define AR9280_PHY_MINCCA_PWR 0x1FF00000
133 #define AR9280_PHY_MINCCA_PWR_S 20
134 #define AR9280_PHY_CCA_THRESH62 0x000FF000
135 #define AR9280_PHY_CCA_THRESH62_S 12
561 #define AR_PHY_CH1_CCA 0xa864
562 #define AR_PHY_CH1_MINCCA_PWR 0x0FF80000
563 #define AR_PHY_CH1_MINCCA_PWR_S 19
564 #define AR9280_PHY_CH1_MINCCA_PWR 0x1FF00000
565 #define AR9280_PHY_CH1_MINCCA_PWR_S 20
566
567 #define AR_PHY_CH2_CCA 0xb864
568 #define AR_PHY_CH2_MINCCA_PWR 0x0FF80000
569 #define AR_PHY_CH2_MINCCA_PWR_S 19
570
571 #define AR_PHY_CH1_EXT_CCA 0xa9bc
572 #define AR_PHY_CH1_EXT_MINCCA_PWR 0xFF800000
573 #define AR_PHY_CH1_EXT_MINCCA_PWR_S 23
574 #define AR9280_PHY_CH1_EXT_MINCCA_PWR 0x01FF0000
575 #define AR9280_PHY_CH1_EXT_MINCCA_PWR_S 16
576
577 #define AR_PHY_CH2_EXT_CCA 0xb9bc
578 #define AR_PHY_CH2_EXT_MINCCA_PWR 0xFF800000
579 #define AR_PHY_CH2_EXT_MINCCA_PWR_S 23
580
581 #define AR_PHY_CCA_NOM_VAL_5416_2GHZ -90
582 #define AR_PHY_CCA_NOM_VAL_5416_5GHZ -100
583 #define AR_PHY_CCA_MIN_GOOD_VAL_5416_2GHZ -100
584 #define AR_PHY_CCA_MIN_GOOD_VAL_5416_5GHZ -110
585 #define AR_PHY_CCA_MAX_GOOD_VAL_5416_2GHZ -80
586 #define AR_PHY_CCA_MAX_GOOD_VAL_5416_5GHZ -90
587
588 #define AR_PHY_CCA_NOM_VAL_9280_2GHZ -112
589 #define AR_PHY_CCA_NOM_VAL_9280_5GHZ -112
590 #define AR_PHY_CCA_MIN_GOOD_VAL_9280_2GHZ -127
591 #define AR_PHY_CCA_MIN_GOOD_VAL_9280_5GHZ -122
592 #define AR_PHY_CCA_MAX_GOOD_VAL_9280_2GHZ -97
593 #define AR_PHY_CCA_MAX_GOOD_VAL_9280_5GHZ -102
594
595 #define AR_PHY_CCA_NOM_VAL_9285_2GHZ -118
596 #define AR_PHY_CCA_MIN_GOOD_VAL_9285_2GHZ -127
597 #define AR_PHY_CCA_MAX_GOOD_VAL_9285_2GHZ -108
598
599 #define AR_PHY_CCA_NOM_VAL_9271_2GHZ -118
600 #define AR_PHY_CCA_MIN_GOOD_VAL_9271_2GHZ -127
601 #define AR_PHY_CCA_MAX_GOOD_VAL_9271_2GHZ -116
602
603 #define AR_PHY_CCA_NOM_VAL_9287_2GHZ -120
604 #define AR_PHY_CCA_MIN_GOOD_VAL_9287_2GHZ -127
605 #define AR_PHY_CCA_MAX_GOOD_VAL_9287_2GHZ -110
Sagar Bijwe <sag.bijwe <at> gmail.com> writes:
>
> I wish to disable CCA for ath9k. Can anyone tell me how this can be achieved?
As far as I see it, modifying values of?AR9280_PHY_CCA_THRESH62????
AR9280_PHY_CCA_THRESH62_S (present in phy.h)should do. -Sagar
>
> _______________________________________________
> ath9k-devel mailing list
> ath9k-devel <at> lists.ath9k.org
> https://lists.ath9k.org/mailman/listinfo/ath9k-devel
>
^ permalink raw reply [flat|nested] 20+ messages in thread
* [ath9k-devel] adjust the CCA (Clear Channel Assessment) value for ath9k
2011-02-15 19:49 ` [ath9k-devel] adjust the CCA (Clear Channel Assessment) value " Brandon Combs
@ 2011-02-16 13:17 ` Mohammed Shafi
2011-02-16 14:04 ` Sagar Bijwe
2011-02-18 17:10 ` Brandon Combs
2014-03-24 11:53 ` Javi Jap
1 sibling, 2 replies; 20+ messages in thread
From: Mohammed Shafi @ 2011-02-16 13:17 UTC (permalink / raw)
To: ath9k-devel
On Wed, Feb 16, 2011 at 1:19 AM, Brandon Combs <brmcombs@iusb.edu> wrote:
> Sagar Bijwe <sag.bijwe <at> gmail.com> writes:
>>
>> I wish to disable CCA for ath9k. Can anyone tell me how this can be achieved?
> As far as I see it, modifying values of?AR9280_PHY_CCA_THRESH62
> AR9280_PHY_CCA_THRESH62_S (present in phy.h)should do. -Sagar
>> _______________________________________________
>
> I also need to adjust the CCA (Clear Channel Assessment)value. Does anyone know
> how to increase the CCA threshold so that one can get a node to send even when
> it senses an unclear channel? Here is the code segments from
> /source/drivers/net/wireless/ath/ath9k/ar9002_phy.h which I believe I need to
> adjust to increase the CCA threshold but I am not quite sure how (thanks for any
> help, Note: I am using AR9280 chip set):
>
> 127 #define AR_PHY_CCA ? ? ? ? ? ? ? ? ?0x9864
> 128 #define AR_PHY_MINCCA_PWR ? ? ? ? ? 0x0FF80000
> 129 #define AR_PHY_MINCCA_PWR_S ? ? ? ? 19
> 130 #define AR_PHY_CCA_THRESH62 ? ? ? ? 0x0007F000
> 131 #define AR_PHY_CCA_THRESH62_S ? ? ? 12
> 132 #define AR9280_PHY_MINCCA_PWR ? ? ? 0x1FF00000
> 133 #define AR9280_PHY_MINCCA_PWR_S ? ? 20
> 134 #define AR9280_PHY_CCA_THRESH62 ? ? 0x000FF000
> 135 #define AR9280_PHY_CCA_THRESH62_S ? 12
>
> 561 #define AR_PHY_CH1_CCA ? ? ? ? ?0xa864
> 562 #define AR_PHY_CH1_MINCCA_PWR ? 0x0FF80000
> 563 #define AR_PHY_CH1_MINCCA_PWR_S 19
> 564 #define AR9280_PHY_CH1_MINCCA_PWR ? 0x1FF00000
> 565 #define AR9280_PHY_CH1_MINCCA_PWR_S 20
> 566
> 567 #define AR_PHY_CH2_CCA ? ? ? ? ?0xb864
> 568 #define AR_PHY_CH2_MINCCA_PWR ? 0x0FF80000
> 569 #define AR_PHY_CH2_MINCCA_PWR_S 19
> 570
> 571 #define AR_PHY_CH1_EXT_CCA ? ? ? ? ?0xa9bc
> 572 #define AR_PHY_CH1_EXT_MINCCA_PWR ? 0xFF800000
> 573 #define AR_PHY_CH1_EXT_MINCCA_PWR_S 23
> 574 #define AR9280_PHY_CH1_EXT_MINCCA_PWR ? 0x01FF0000
> 575 #define AR9280_PHY_CH1_EXT_MINCCA_PWR_S 16
> 576
> 577 #define AR_PHY_CH2_EXT_CCA ? ? ? ? ?0xb9bc
> 578 #define AR_PHY_CH2_EXT_MINCCA_PWR ? 0xFF800000
> 579 #define AR_PHY_CH2_EXT_MINCCA_PWR_S 23
> 580
> 581 #define AR_PHY_CCA_NOM_VAL_5416_2GHZ ? ? ? ? ? ?-90
> 582 #define AR_PHY_CCA_NOM_VAL_5416_5GHZ ? ? ? ? ? ?-100
> 583 #define AR_PHY_CCA_MIN_GOOD_VAL_5416_2GHZ ? ? -100
> 584 #define AR_PHY_CCA_MIN_GOOD_VAL_5416_5GHZ ? ? -110
> 585 #define AR_PHY_CCA_MAX_GOOD_VAL_5416_2GHZ ? ? -80
> 586 #define AR_PHY_CCA_MAX_GOOD_VAL_5416_5GHZ ? ? -90
> 587
> 588 #define AR_PHY_CCA_NOM_VAL_9280_2GHZ ? ? ? ? -112
> 589 #define AR_PHY_CCA_NOM_VAL_9280_5GHZ ? ? ? ? -112
> 590 #define AR_PHY_CCA_MIN_GOOD_VAL_9280_2GHZ ?-127
> 591 #define AR_PHY_CCA_MIN_GOOD_VAL_9280_5GHZ ?-122
> 592 #define AR_PHY_CCA_MAX_GOOD_VAL_9280_2GHZ ?-97
> 593 #define AR_PHY_CCA_MAX_GOOD_VAL_9280_5GHZ ?-102
> 594
> 595 #define AR_PHY_CCA_NOM_VAL_9285_2GHZ ? ? ? ? ? -118
> 596 #define AR_PHY_CCA_MIN_GOOD_VAL_9285_2GHZ ? ?-127
> 597 #define AR_PHY_CCA_MAX_GOOD_VAL_9285_2GHZ ? ?-108
> 598
> 599 #define AR_PHY_CCA_NOM_VAL_9271_2GHZ ? ? ? ? ? ? -118
> 600 #define AR_PHY_CCA_MIN_GOOD_VAL_9271_2GHZ ? ? ?-127
> 601 #define AR_PHY_CCA_MAX_GOOD_VAL_9271_2GHZ ? ? ?-116
> 602
> 603 #define AR_PHY_CCA_NOM_VAL_9287_2GHZ ? ? ? ? ? -120
> 604 #define AR_PHY_CCA_MIN_GOOD_VAL_9287_2GHZ ? ?-127
> 605 #define AR_PHY_CCA_MAX_GOOD_VAL_9287_2GHZ ? ?-110
>
> Sagar Bijwe <sag.bijwe <at> gmail.com> writes:
>>
>> I wish to disable CCA for ath9k. Can anyone tell me how this can be achieved?
> As far as I see it, modifying values of?AR9280_PHY_CCA_THRESH62
> AR9280_PHY_CCA_THRESH62_S (present in phy.h)should do. -Sagar
>>
unfortunately its not a feature that we can simply disable it and I
guess it requires a deeper understanding of hardware code to do this.
>> _______________________________________________
>> ath9k-devel mailing list
>> ath9k-devel <at> lists.ath9k.org
>> https://lists.ath9k.org/mailman/listinfo/ath9k-devel
>>
>
>
>
>
> _______________________________________________
> ath9k-devel mailing list
> ath9k-devel at lists.ath9k.org
> https://lists.ath9k.org/mailman/listinfo/ath9k-devel
>
^ permalink raw reply [flat|nested] 20+ messages in thread
* [ath9k-devel] adjust the CCA (Clear Channel Assessment) value for ath9k
2011-02-16 13:17 ` Mohammed Shafi
@ 2011-02-16 14:04 ` Sagar Bijwe
2011-02-17 8:29 ` Mohammed Shafi
2011-02-18 17:10 ` Brandon Combs
1 sibling, 1 reply; 20+ messages in thread
From: Sagar Bijwe @ 2011-02-16 14:04 UTC (permalink / raw)
To: ath9k-devel
Will this do???
REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_RX_CLEAR);
Regards
-Sagar
On Wed, Feb 16, 2011 at 6:47 PM, Mohammed Shafi <shafi.ath9k@gmail.com>wrote:
> On Wed, Feb 16, 2011 at 1:19 AM, Brandon Combs <brmcombs@iusb.edu> wrote:
> > Sagar Bijwe <sag.bijwe <at> gmail.com> writes:
> >>
> >> I wish to disable CCA for ath9k. Can anyone tell me how this can be
> achieved?
> > As far as I see it, modifying values of AR9280_PHY_CCA_THRESH62
> > AR9280_PHY_CCA_THRESH62_S (present in phy.h)should do. -Sagar
> >> _______________________________________________
> >
> > I also need to adjust the CCA (Clear Channel Assessment)value. Does
> anyone know
> > how to increase the CCA threshold so that one can get a node to send even
> when
> > it senses an unclear channel? Here is the code segments from
> > /source/drivers/net/wireless/ath/ath9k/ar9002_phy.h which I believe I
> need to
> > adjust to increase the CCA threshold but I am not quite sure how (thanks
> for any
> > help, Note: I am using AR9280 chip set):
> >
> > 127 #define AR_PHY_CCA 0x9864
> > 128 #define AR_PHY_MINCCA_PWR 0x0FF80000
> > 129 #define AR_PHY_MINCCA_PWR_S 19
> > 130 #define AR_PHY_CCA_THRESH62 0x0007F000
> > 131 #define AR_PHY_CCA_THRESH62_S 12
> > 132 #define AR9280_PHY_MINCCA_PWR 0x1FF00000
> > 133 #define AR9280_PHY_MINCCA_PWR_S 20
> > 134 #define AR9280_PHY_CCA_THRESH62 0x000FF000
> > 135 #define AR9280_PHY_CCA_THRESH62_S 12
> >
> > 561 #define AR_PHY_CH1_CCA 0xa864
> > 562 #define AR_PHY_CH1_MINCCA_PWR 0x0FF80000
> > 563 #define AR_PHY_CH1_MINCCA_PWR_S 19
> > 564 #define AR9280_PHY_CH1_MINCCA_PWR 0x1FF00000
> > 565 #define AR9280_PHY_CH1_MINCCA_PWR_S 20
> > 566
> > 567 #define AR_PHY_CH2_CCA 0xb864
> > 568 #define AR_PHY_CH2_MINCCA_PWR 0x0FF80000
> > 569 #define AR_PHY_CH2_MINCCA_PWR_S 19
> > 570
> > 571 #define AR_PHY_CH1_EXT_CCA 0xa9bc
> > 572 #define AR_PHY_CH1_EXT_MINCCA_PWR 0xFF800000
> > 573 #define AR_PHY_CH1_EXT_MINCCA_PWR_S 23
> > 574 #define AR9280_PHY_CH1_EXT_MINCCA_PWR 0x01FF0000
> > 575 #define AR9280_PHY_CH1_EXT_MINCCA_PWR_S 16
> > 576
> > 577 #define AR_PHY_CH2_EXT_CCA 0xb9bc
> > 578 #define AR_PHY_CH2_EXT_MINCCA_PWR 0xFF800000
> > 579 #define AR_PHY_CH2_EXT_MINCCA_PWR_S 23
> > 580
> > 581 #define AR_PHY_CCA_NOM_VAL_5416_2GHZ -90
> > 582 #define AR_PHY_CCA_NOM_VAL_5416_5GHZ -100
> > 583 #define AR_PHY_CCA_MIN_GOOD_VAL_5416_2GHZ -100
> > 584 #define AR_PHY_CCA_MIN_GOOD_VAL_5416_5GHZ -110
> > 585 #define AR_PHY_CCA_MAX_GOOD_VAL_5416_2GHZ -80
> > 586 #define AR_PHY_CCA_MAX_GOOD_VAL_5416_5GHZ -90
> > 587
> > 588 #define AR_PHY_CCA_NOM_VAL_9280_2GHZ -112
> > 589 #define AR_PHY_CCA_NOM_VAL_9280_5GHZ -112
> > 590 #define AR_PHY_CCA_MIN_GOOD_VAL_9280_2GHZ -127
> > 591 #define AR_PHY_CCA_MIN_GOOD_VAL_9280_5GHZ -122
> > 592 #define AR_PHY_CCA_MAX_GOOD_VAL_9280_2GHZ -97
> > 593 #define AR_PHY_CCA_MAX_GOOD_VAL_9280_5GHZ -102
> > 594
> > 595 #define AR_PHY_CCA_NOM_VAL_9285_2GHZ -118
> > 596 #define AR_PHY_CCA_MIN_GOOD_VAL_9285_2GHZ -127
> > 597 #define AR_PHY_CCA_MAX_GOOD_VAL_9285_2GHZ -108
> > 598
> > 599 #define AR_PHY_CCA_NOM_VAL_9271_2GHZ -118
> > 600 #define AR_PHY_CCA_MIN_GOOD_VAL_9271_2GHZ -127
> > 601 #define AR_PHY_CCA_MAX_GOOD_VAL_9271_2GHZ -116
> > 602
> > 603 #define AR_PHY_CCA_NOM_VAL_9287_2GHZ -120
> > 604 #define AR_PHY_CCA_MIN_GOOD_VAL_9287_2GHZ -127
> > 605 #define AR_PHY_CCA_MAX_GOOD_VAL_9287_2GHZ -110
> >
> > Sagar Bijwe <sag.bijwe <at> gmail.com> writes:
> >>
> >> I wish to disable CCA for ath9k. Can anyone tell me how this can be
> achieved?
> > As far as I see it, modifying values of AR9280_PHY_CCA_THRESH62
> > AR9280_PHY_CCA_THRESH62_S (present in phy.h)should do. -Sagar
> >>
>
> unfortunately its not a feature that we can simply disable it and I
> guess it requires a deeper understanding of hardware code to do this.
>
> >> _______________________________________________
> >> ath9k-devel mailing list
> >> ath9k-devel <at> lists.ath9k.org
> >> https://lists.ath9k.org/mailman/listinfo/ath9k-devel
> >>
> >
> >
> >
> >
> > _______________________________________________
> > ath9k-devel mailing list
> > ath9k-devel at lists.ath9k.org
> > https://lists.ath9k.org/mailman/listinfo/ath9k-devel
> >
> _______________________________________________
> ath9k-devel mailing list
> ath9k-devel at lists.ath9k.org
> https://lists.ath9k.org/mailman/listinfo/ath9k-devel
>
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* [ath9k-devel] adjust the CCA (Clear Channel Assessment) value for ath9k
2011-02-16 14:04 ` Sagar Bijwe
@ 2011-02-17 8:29 ` Mohammed Shafi
0 siblings, 0 replies; 20+ messages in thread
From: Mohammed Shafi @ 2011-02-17 8:29 UTC (permalink / raw)
To: ath9k-devel
On Wed, Feb 16, 2011 at 7:34 PM, Sagar Bijwe <sag.bijwe@gmail.com> wrote:
> Will this do???
> REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_RX_CLEAR);
I don't know whether it will work.
>
> Regards
> -Sagar
>
>
> On Wed, Feb 16, 2011 at 6:47 PM, Mohammed Shafi <shafi.ath9k@gmail.com>
> wrote:
>>
>> On Wed, Feb 16, 2011 at 1:19 AM, Brandon Combs <brmcombs@iusb.edu> wrote:
>> > Sagar Bijwe <sag.bijwe <at> gmail.com> writes:
>> >>
>> >> I wish to disable CCA for ath9k. Can anyone tell me how this can be
>> >> achieved?
>> > As far as I see it, modifying values of?AR9280_PHY_CCA_THRESH62
>> > AR9280_PHY_CCA_THRESH62_S (present in phy.h)should do. -Sagar
>> >> _______________________________________________
>> >
>> > I also need to adjust the CCA (Clear Channel Assessment)value. Does
>> > anyone know
>> > how to increase the CCA threshold so that one can get a node to send
>> > even when
>> > it senses an unclear channel? Here is the code segments from
>> > /source/drivers/net/wireless/ath/ath9k/ar9002_phy.h which I believe I
>> > need to
>> > adjust to increase the CCA threshold but I am not quite sure how (thanks
>> > for any
>> > help, Note: I am using AR9280 chip set):
>> >
>> > 127 #define AR_PHY_CCA ? ? ? ? ? ? ? ? ?0x9864
>> > 128 #define AR_PHY_MINCCA_PWR ? ? ? ? ? 0x0FF80000
>> > 129 #define AR_PHY_MINCCA_PWR_S ? ? ? ? 19
>> > 130 #define AR_PHY_CCA_THRESH62 ? ? ? ? 0x0007F000
>> > 131 #define AR_PHY_CCA_THRESH62_S ? ? ? 12
>> > 132 #define AR9280_PHY_MINCCA_PWR ? ? ? 0x1FF00000
>> > 133 #define AR9280_PHY_MINCCA_PWR_S ? ? 20
>> > 134 #define AR9280_PHY_CCA_THRESH62 ? ? 0x000FF000
>> > 135 #define AR9280_PHY_CCA_THRESH62_S ? 12
>> >
>> > 561 #define AR_PHY_CH1_CCA ? ? ? ? ?0xa864
>> > 562 #define AR_PHY_CH1_MINCCA_PWR ? 0x0FF80000
>> > 563 #define AR_PHY_CH1_MINCCA_PWR_S 19
>> > 564 #define AR9280_PHY_CH1_MINCCA_PWR ? 0x1FF00000
>> > 565 #define AR9280_PHY_CH1_MINCCA_PWR_S 20
>> > 566
>> > 567 #define AR_PHY_CH2_CCA ? ? ? ? ?0xb864
>> > 568 #define AR_PHY_CH2_MINCCA_PWR ? 0x0FF80000
>> > 569 #define AR_PHY_CH2_MINCCA_PWR_S 19
>> > 570
>> > 571 #define AR_PHY_CH1_EXT_CCA ? ? ? ? ?0xa9bc
>> > 572 #define AR_PHY_CH1_EXT_MINCCA_PWR ? 0xFF800000
>> > 573 #define AR_PHY_CH1_EXT_MINCCA_PWR_S 23
>> > 574 #define AR9280_PHY_CH1_EXT_MINCCA_PWR ? 0x01FF0000
>> > 575 #define AR9280_PHY_CH1_EXT_MINCCA_PWR_S 16
>> > 576
>> > 577 #define AR_PHY_CH2_EXT_CCA ? ? ? ? ?0xb9bc
>> > 578 #define AR_PHY_CH2_EXT_MINCCA_PWR ? 0xFF800000
>> > 579 #define AR_PHY_CH2_EXT_MINCCA_PWR_S 23
>> > 580
>> > 581 #define AR_PHY_CCA_NOM_VAL_5416_2GHZ ? ? ? ? ? ?-90
>> > 582 #define AR_PHY_CCA_NOM_VAL_5416_5GHZ ? ? ? ? ? ?-100
>> > 583 #define AR_PHY_CCA_MIN_GOOD_VAL_5416_2GHZ ? ? -100
>> > 584 #define AR_PHY_CCA_MIN_GOOD_VAL_5416_5GHZ ? ? -110
>> > 585 #define AR_PHY_CCA_MAX_GOOD_VAL_5416_2GHZ ? ? -80
>> > 586 #define AR_PHY_CCA_MAX_GOOD_VAL_5416_5GHZ ? ? -90
>> > 587
>> > 588 #define AR_PHY_CCA_NOM_VAL_9280_2GHZ ? ? ? ? -112
>> > 589 #define AR_PHY_CCA_NOM_VAL_9280_5GHZ ? ? ? ? -112
>> > 590 #define AR_PHY_CCA_MIN_GOOD_VAL_9280_2GHZ ?-127
>> > 591 #define AR_PHY_CCA_MIN_GOOD_VAL_9280_5GHZ ?-122
>> > 592 #define AR_PHY_CCA_MAX_GOOD_VAL_9280_2GHZ ?-97
>> > 593 #define AR_PHY_CCA_MAX_GOOD_VAL_9280_5GHZ ?-102
>> > 594
>> > 595 #define AR_PHY_CCA_NOM_VAL_9285_2GHZ ? ? ? ? ? -118
>> > 596 #define AR_PHY_CCA_MIN_GOOD_VAL_9285_2GHZ ? ?-127
>> > 597 #define AR_PHY_CCA_MAX_GOOD_VAL_9285_2GHZ ? ?-108
>> > 598
>> > 599 #define AR_PHY_CCA_NOM_VAL_9271_2GHZ ? ? ? ? ? ? -118
>> > 600 #define AR_PHY_CCA_MIN_GOOD_VAL_9271_2GHZ ? ? ?-127
>> > 601 #define AR_PHY_CCA_MAX_GOOD_VAL_9271_2GHZ ? ? ?-116
>> > 602
>> > 603 #define AR_PHY_CCA_NOM_VAL_9287_2GHZ ? ? ? ? ? -120
>> > 604 #define AR_PHY_CCA_MIN_GOOD_VAL_9287_2GHZ ? ?-127
>> > 605 #define AR_PHY_CCA_MAX_GOOD_VAL_9287_2GHZ ? ?-110
>> >
>> > Sagar Bijwe <sag.bijwe <at> gmail.com> writes:
>> >>
>> >> I wish to disable CCA for ath9k. Can anyone tell me how this can be
>> >> achieved?
>> > As far as I see it, modifying values of?AR9280_PHY_CCA_THRESH62
>> > AR9280_PHY_CCA_THRESH62_S (present in phy.h)should do. -Sagar
>> >>
>>
>> unfortunately its not a feature that we can simply disable it and I
>> guess it requires a deeper understanding of hardware code to do this.
>>
>> >> _______________________________________________
>> >> ath9k-devel mailing list
>> >> ath9k-devel <at> lists.ath9k.org
>> >> https://lists.ath9k.org/mailman/listinfo/ath9k-devel
>> >>
>> >
>> >
>> >
>> >
>> > _______________________________________________
>> > ath9k-devel mailing list
>> > ath9k-devel at lists.ath9k.org
>> > https://lists.ath9k.org/mailman/listinfo/ath9k-devel
>> >
>> _______________________________________________
>> ath9k-devel mailing list
>> ath9k-devel at lists.ath9k.org
>> https://lists.ath9k.org/mailman/listinfo/ath9k-devel
>
>
^ permalink raw reply [flat|nested] 20+ messages in thread
* [ath9k-devel] adjust the CCA (Clear Channel Assessment) value for ath9k
2011-02-16 13:17 ` Mohammed Shafi
2011-02-16 14:04 ` Sagar Bijwe
@ 2011-02-18 17:10 ` Brandon Combs
2011-02-21 0:19 ` Wright, Brett
` (2 more replies)
1 sibling, 3 replies; 20+ messages in thread
From: Brandon Combs @ 2011-02-18 17:10 UTC (permalink / raw)
To: ath9k-devel
> > I also need to adjust the CCA (Clear Channel Assessment)value. Does anyone
know
> > how to increase the CCA threshold so that one can get a node to send even
when
> > it senses an unclear channel? Here is the code segments from
> > /source/drivers/net/wireless/ath/ath9k/ar9002_phy.h which I believe I need
to
> > adjust to increase the CCA threshold but I am not quite sure how (thanks for
any help, Note: I am using AR9280 chip set):
> >
> > 127 #define AR_PHY_CCA ? ? ? ? ? ? ? ? ?0x9864
> > 128 #define AR_PHY_MINCCA_PWR ? ? ? ? ? 0x0FF80000
> > 129 #define AR_PHY_MINCCA_PWR_S ? ? ? ? 19
> > 130 #define AR_PHY_CCA_THRESH62 ? ? ? ? 0x0007F000
> > 131 #define AR_PHY_CCA_THRESH62_S ? ? ? 12
> > 132 #define AR9280_PHY_MINCCA_PWR ? ? ? 0x1FF00000
> > 133 #define AR9280_PHY_MINCCA_PWR_S ? ? 20
> > 134 #define AR9280_PHY_CCA_THRESH62 ? ? 0x000FF000
> > 135 #define AR9280_PHY_CCA_THRESH62_S ? 12
> > 581 #define AR_PHY_CCA_NOM_VAL_5416_2GHZ ? ? ? ? ? ?-90
> > 582 #define AR_PHY_CCA_NOM_VAL_5416_5GHZ ? ? ? ? ? ?-100
> > 583 #define AR_PHY_CCA_MIN_GOOD_VAL_5416_2GHZ ? ? -100
> > 584 #define AR_PHY_CCA_MIN_GOOD_VAL_5416_5GHZ ? ? -110
> > 585 #define AR_PHY_CCA_MAX_GOOD_VAL_5416_2GHZ ? ? -80
> > 586 #define AR_PHY_CCA_MAX_GOOD_VAL_5416_5GHZ ? ? -90
> > 587
> > 588 #define AR_PHY_CCA_NOM_VAL_9280_2GHZ ? ? ? ? -112
> > 589 #define AR_PHY_CCA_NOM_VAL_9280_5GHZ ? ? ? ? -112
> > 590 #define AR_PHY_CCA_MIN_GOOD_VAL_9280_2GHZ ?-127
> > 591 #define AR_PHY_CCA_MIN_GOOD_VAL_9280_5GHZ ?-122
> > 592 #define AR_PHY_CCA_MAX_GOOD_VAL_9280_2GHZ ?-97
> > 593 #define AR_PHY_CCA_MAX_GOOD_VAL_9280_5GHZ ?-102
> > 594
> > 595 #define AR_PHY_CCA_NOM_VAL_9285_2GHZ ? ? ? ? ? -118
> > 596 #define AR_PHY_CCA_MIN_GOOD_VAL_9285_2GHZ ? ?-127
> > 597 #define AR_PHY_CCA_MAX_GOOD_VAL_9285_2GHZ ? ?-108
> > 598
> > 599 #define AR_PHY_CCA_NOM_VAL_9271_2GHZ ? ? ? ? ? ? -118
> > 600 #define AR_PHY_CCA_MIN_GOOD_VAL_9271_2GHZ ? ? ?-127
> > 601 #define AR_PHY_CCA_MAX_GOOD_VAL_9271_2GHZ ? ? ?-116
> > 602
> > 603 #define AR_PHY_CCA_NOM_VAL_9287_2GHZ ? ? ? ? ? -120
> > 604 #define AR_PHY_CCA_MIN_GOOD_VAL_9287_2GHZ ? ?-127
> > 605 #define AR_PHY_CCA_MAX_GOOD_VAL_9287_2GHZ ? ?-110
> >
> > Sagar Bijwe <sag.bijwe <at> gmail.com> writes:
> >>
> >> I wish to disable CCA for ath9k. Can anyone tell me how this can be
achieved?
> > As far as I see it, modifying values of?AR9280_PHY_CCA_THRESH62
> > AR9280_PHY_CCA_THRESH62_S (present in phy.h)should do. -Sagar
> >>
>
> unfortunately its not a feature that we can simply disable it and I
> guess it requires a deeper understanding of hardware code to do this.
/////////////////////////////////////////////////////////////////////
I realize that "it requires a deeper understanding of hardware code to" increase
the CCA threshold. Is this maybe not the correct mailing list to ask this "deep"
of a question?
Can someone please point me in the right direction on where to learn this
information? I have throughly looked through linuxwireless.org documentation and
I searched the web for hours and I cannot find any reference to adjusting CCA.
Is it not just simply a matter of changing one of the "#define AR_PHY_...." and
recompiling the driver in order to increase the CCA threshold?
I really, really appreciate ANY info on adjusting the AR9280 CCA threshold!
^ permalink raw reply [flat|nested] 20+ messages in thread
* [ath9k-devel] adjust the CCA (Clear Channel Assessment) value for ath9k
2011-02-18 17:10 ` Brandon Combs
@ 2011-02-21 0:19 ` Wright, Brett
2011-02-21 3:55 ` [ath9k-devel] adjust the CCA (Clear Channel Assessment) value?for ath9k Peter Stuge
2011-02-21 4:52 ` [ath9k-devel] adjust the CCA (Clear Channel Assessment) value for ath9k Mohammed Shafi
2 siblings, 0 replies; 20+ messages in thread
From: Wright, Brett @ 2011-02-21 0:19 UTC (permalink / raw)
To: ath9k-devel
> -----Original Message-----
> From: ath9k-devel-bounces at lists.ath9k.org [mailto:ath9k-devel-
> bounces at lists.ath9k.org] On Behalf Of Brandon Combs
> Sent: Saturday, 19 February 2011 3:10 AM
> To: ath9k-devel at lists.ath9k.org
> Subject: Re: [ath9k-devel]adjust the CCA (Clear Channel Assessment)
> value for ath9k
>
> I realize that "it requires a deeper understanding of hardware code to"
> increase
> the CCA threshold. Is this maybe not the correct mailing list to ask
> this "deep"
> of a question?
> Can someone please point me in the right direction on where to learn
> this
> information? I have throughly looked through linuxwireless.org
> documentation and
> I searched the web for hours and I cannot find any reference to
> adjusting CCA.
>
> Is it not just simply a matter of changing one of the "#define
> AR_PHY_...." and
> recompiling the driver in order to increase the CCA threshold?
>
> I really, really appreciate ANY info on adjusting the AR9280 CCA
> threshold!
>
I know it's not quit the same, but I have previously spent a LOT of time trying the make the same adjustments on ar5414. What I did eventually find is that it is not possible to adjust the CCA threshold directly - the CCA level is essentially the noise floor. That is, the radio will hold of due to ANY RF level higher than the noise floor.
Therefore it is possible to implicitly modify the CCA level by increasing the noise floor (you can manually do this if you disable the periodic calibration), but of course that also means you are "deaf" to any valid signal below the noise floor.
Hope this is slightly helpful.
Brett
^ permalink raw reply [flat|nested] 20+ messages in thread
* [ath9k-devel] adjust the CCA (Clear Channel Assessment) value?for ath9k
2011-02-18 17:10 ` Brandon Combs
2011-02-21 0:19 ` Wright, Brett
@ 2011-02-21 3:55 ` Peter Stuge
2011-02-21 17:09 ` Adrian Chadd
2011-02-21 4:52 ` [ath9k-devel] adjust the CCA (Clear Channel Assessment) value for ath9k Mohammed Shafi
2 siblings, 1 reply; 20+ messages in thread
From: Peter Stuge @ 2011-02-21 3:55 UTC (permalink / raw)
To: ath9k-devel
Brandon Combs wrote:
> > I guess it requires a deeper understanding of hardware code to do this.
>
> I realize that "it requires a deeper understanding of hardware code to"
> increase the CCA threshold. Is this maybe not the correct mailing list
> to ask this "deep" of a question?
Basically there exists no such mailing list (at least publically) for
ath9k. There has consistently been absolute lack of open discussion
about anything firmware level on this mailing list for the 15-or-so
months that I have been subscribed, and only limited open discussion
about anything driver level.
//Peter
^ permalink raw reply [flat|nested] 20+ messages in thread
* [ath9k-devel] adjust the CCA (Clear Channel Assessment) value for ath9k
2011-02-18 17:10 ` Brandon Combs
2011-02-21 0:19 ` Wright, Brett
2011-02-21 3:55 ` [ath9k-devel] adjust the CCA (Clear Channel Assessment) value?for ath9k Peter Stuge
@ 2011-02-21 4:52 ` Mohammed Shafi
2 siblings, 0 replies; 20+ messages in thread
From: Mohammed Shafi @ 2011-02-21 4:52 UTC (permalink / raw)
To: ath9k-devel
On Fri, Feb 18, 2011 at 10:40 PM, Brandon Combs <brmcombs@iusb.edu> wrote:
>> > I also need to adjust the CCA (Clear Channel Assessment)value. Does anyone
> know
>> > how to increase the CCA threshold so that one can get a node to send even
> when
>> > it senses an unclear channel? Here is the code segments from
>> > /source/drivers/net/wireless/ath/ath9k/ar9002_phy.h which I believe I need
> to
>> > adjust to increase the CCA threshold but I am not quite sure how (thanks for
> any help, Note: I am using AR9280 chip set):
>> >
>> > 127 #define AR_PHY_CCA ? ? ? ? ? ? ? ? ?0x9864
>> > 128 #define AR_PHY_MINCCA_PWR ? ? ? ? ? 0x0FF80000
>> > 129 #define AR_PHY_MINCCA_PWR_S ? ? ? ? 19
>> > 130 #define AR_PHY_CCA_THRESH62 ? ? ? ? 0x0007F000
>> > 131 #define AR_PHY_CCA_THRESH62_S ? ? ? 12
>> > 132 #define AR9280_PHY_MINCCA_PWR ? ? ? 0x1FF00000
>> > 133 #define AR9280_PHY_MINCCA_PWR_S ? ? 20
>> > 134 #define AR9280_PHY_CCA_THRESH62 ? ? 0x000FF000
>> > 135 #define AR9280_PHY_CCA_THRESH62_S ? 12
>
>> > 581 #define AR_PHY_CCA_NOM_VAL_5416_2GHZ ? ? ? ? ? ?-90
>> > 582 #define AR_PHY_CCA_NOM_VAL_5416_5GHZ ? ? ? ? ? ?-100
>> > 583 #define AR_PHY_CCA_MIN_GOOD_VAL_5416_2GHZ ? ? -100
>> > 584 #define AR_PHY_CCA_MIN_GOOD_VAL_5416_5GHZ ? ? -110
>> > 585 #define AR_PHY_CCA_MAX_GOOD_VAL_5416_2GHZ ? ? -80
>> > 586 #define AR_PHY_CCA_MAX_GOOD_VAL_5416_5GHZ ? ? -90
>> > 587
>> > 588 #define AR_PHY_CCA_NOM_VAL_9280_2GHZ ? ? ? ? -112
>> > 589 #define AR_PHY_CCA_NOM_VAL_9280_5GHZ ? ? ? ? -112
>> > 590 #define AR_PHY_CCA_MIN_GOOD_VAL_9280_2GHZ ?-127
>> > 591 #define AR_PHY_CCA_MIN_GOOD_VAL_9280_5GHZ ?-122
>> > 592 #define AR_PHY_CCA_MAX_GOOD_VAL_9280_2GHZ ?-97
>> > 593 #define AR_PHY_CCA_MAX_GOOD_VAL_9280_5GHZ ?-102
>> > 594
>> > 595 #define AR_PHY_CCA_NOM_VAL_9285_2GHZ ? ? ? ? ? -118
>> > 596 #define AR_PHY_CCA_MIN_GOOD_VAL_9285_2GHZ ? ?-127
>> > 597 #define AR_PHY_CCA_MAX_GOOD_VAL_9285_2GHZ ? ?-108
>> > 598
>> > 599 #define AR_PHY_CCA_NOM_VAL_9271_2GHZ ? ? ? ? ? ? -118
>> > 600 #define AR_PHY_CCA_MIN_GOOD_VAL_9271_2GHZ ? ? ?-127
>> > 601 #define AR_PHY_CCA_MAX_GOOD_VAL_9271_2GHZ ? ? ?-116
>> > 602
>> > 603 #define AR_PHY_CCA_NOM_VAL_9287_2GHZ ? ? ? ? ? -120
>> > 604 #define AR_PHY_CCA_MIN_GOOD_VAL_9287_2GHZ ? ?-127
>> > 605 #define AR_PHY_CCA_MAX_GOOD_VAL_9287_2GHZ ? ?-110
>> >
>> > Sagar Bijwe <sag.bijwe <at> gmail.com> writes:
>> >>
>> >> I wish to disable CCA for ath9k. Can anyone tell me how this can be
> achieved?
>> > As far as I see it, modifying values of?AR9280_PHY_CCA_THRESH62
>> > AR9280_PHY_CCA_THRESH62_S (present in phy.h)should do. -Sagar
>> >>
>>
>> unfortunately its not a feature that we can simply disable it and I
>> guess it requires a deeper understanding of hardware code to do this.
> /////////////////////////////////////////////////////////////////////
>
> I realize that "it requires a deeper understanding of hardware code to" increase
> the CCA threshold. Is this maybe not the correct mailing list to ask this "deep"
> of a question?
Yes it is, I will try my best.
> Can someone please point me in the right direction on where to learn this
> information? I have throughly looked through linuxwireless.org documentation and
> I searched the web for hours and I cannot find any reference to adjusting CCA.
>
> Is it not just simply a matter of changing one of the "#define AR_PHY_...." and
> recompiling the driver in order to increase the CCA threshold?
>
> I really, really appreciate ANY info on adjusting the AR9280 CCA threshold!
>
>
> _______________________________________________
> ath9k-devel mailing list
> ath9k-devel at lists.ath9k.org
> https://lists.ath9k.org/mailman/listinfo/ath9k-devel
>
^ permalink raw reply [flat|nested] 20+ messages in thread
* [ath9k-devel] adjust the CCA (Clear Channel Assessment) value?for ath9k
2011-02-21 3:55 ` [ath9k-devel] adjust the CCA (Clear Channel Assessment) value?for ath9k Peter Stuge
@ 2011-02-21 17:09 ` Adrian Chadd
2011-02-22 5:47 ` [ath9k-devel] Open discussion, e.g. about ath9k PCI Peter Stuge
0 siblings, 1 reply; 20+ messages in thread
From: Adrian Chadd @ 2011-02-21 17:09 UTC (permalink / raw)
To: ath9k-devel
I've had a lot of success with:
* tweaking things, and seeing what happens;
* asking the right questions at the right time.
I haven't had -all- of my questions answered, but I've so far managed to
glean enough from the email archives, patent filings and ath9k source to get
a good handle on how things work. Maybe I'm just thinking differently. :-)
Adrian
On 20 February 2011 22:55, Peter Stuge <peter@stuge.se> wrote:
> Brandon Combs wrote:
> > > I guess it requires a deeper understanding of hardware code to do this.
> >
> > I realize that "it requires a deeper understanding of hardware code to"
> > increase the CCA threshold. Is this maybe not the correct mailing list
> > to ask this "deep" of a question?
>
> Basically there exists no such mailing list (at least publically) for
> ath9k. There has consistently been absolute lack of open discussion
> about anything firmware level on this mailing list for the 15-or-so
> months that I have been subscribed, and only limited open discussion
> about anything driver level.
>
>
> //Peter
> _______________________________________________
> ath9k-devel mailing list
> ath9k-devel at lists.ath9k.org
> https://lists.ath9k.org/mailman/listinfo/ath9k-devel
>
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^ permalink raw reply [flat|nested] 20+ messages in thread
* [ath9k-devel] Open discussion, e.g. about ath9k PCI
2011-02-21 17:09 ` Adrian Chadd
@ 2011-02-22 5:47 ` Peter Stuge
2011-02-22 5:56 ` Peter Stuge
2011-02-22 15:31 ` Adrian Chadd
0 siblings, 2 replies; 20+ messages in thread
From: Peter Stuge @ 2011-02-22 5:47 UTC (permalink / raw)
To: ath9k-devel
Adrian Chadd wrote:
> > absolute lack of open discussion about anything firmware level
>
> I've had a lot of success with:
>
> * tweaking things, and seeing what happens;
This is reverse engineering by trial and error, not open discussion
with vendor experts. The reverse engineering effort is only made
slightly less inconvenient by availability of some source code.
> * asking the right questions at the right time.
Open discussion would be that there's never wrong questions, ie.
general interest in helping you solve your problems, and never a
wrong time.
> so far managed to glean enough from the email archives, patent
> filings and ath9k source to get a good handle on how things work.
Typical reverse engineering.
> Maybe I'm just thinking differently. :-)
When I subscribed and brought up my issues I stated rather explicitly
that I was not interested in becoming an ath9k core developer, but
that I was no stranger to kernel code, and that I desired a level of
discussion which reflected that.
I program enough hardware small and big on register level in other
contexts, heck I even make some hardware with registers, and I want
to get to the bottom of all the issues I have. There has been zero
qualified discussion, and there still seems to be lack of
understanding of efficient remote debugging. Convenient as it would
be to avoid, community work means that every issue isn't reproducible
by everyone everywhere, but I digress; I've been over this already.
At the very least you're thinking differently because you are also
developing a complete driver. That overall understanding is something
I'd actually prefer to avoid, I'm primarily interested in
understanding specific parts of the hardware firmware and driver as
neccessary to isolate the problems I encounter. I want to avoid the
full scope as much as possible because I have many other things to do
and would like to just use my wifi instead of e.g. having to debug
Atheros PCI core.
# while :;do lspci -n -A intel-conf1 -s 2:2; sleep .5s; done
02:02.0 0280: 168c:0029 (rev 01)
02:02.0 0280: 168c:0029 (rev 01)
02:02.0 0004: 0000:0004 (rev 08)
02:02.0 0280: 168c:0029 (rev 01)
02:02.0 0004: 0000:0004 (rev 08)
02:02.0 0280: 168c:0029 (rev 01)
02:02.0 0004: 0000:0004 (rev 08)
02:02.0 0004: 0000:0004 (rev 08)
02:02.0 0004: 0000:0004 (rev 08)
02:02.0 0280: 168c:0029 (rev 01)
02:02.0 0280: 168c:0029 (rev 01)
02:02.0 0280: 168c:0029 (rev 01)
02:02.0 0004: 0000:0004 (rev 08)
02:02.0 0004: 0000:0004 (rev 08)
02:02.0 0004: 0000:0004 (rev 08)
02:02.0 0004: 0000:0004 (rev 08)
02:02.0 0004: 0000:0004 (rev 08)
02:02.0 0280: 168c:0029 (rev 01)
02:02.0 0004: 0000:0004 (rev 08)
02:02.0 0004: 0000:0004 (rev 08)
pcilib: 0000:02:02.0: Invalid 64-bit address seen for BAR 5.
02:02.0 0004: 168c:0029 (rev 08)
02:02.0 0004: 0000:0004 (rev 08)
//Peter
^ permalink raw reply [flat|nested] 20+ messages in thread
* [ath9k-devel] Open discussion, e.g. about ath9k PCI
2011-02-22 5:47 ` [ath9k-devel] Open discussion, e.g. about ath9k PCI Peter Stuge
@ 2011-02-22 5:56 ` Peter Stuge
2011-02-22 15:29 ` Adrian Chadd
2011-02-24 2:12 ` Peter Stuge
2011-02-22 15:31 ` Adrian Chadd
1 sibling, 2 replies; 20+ messages in thread
From: Peter Stuge @ 2011-02-22 5:56 UTC (permalink / raw)
To: ath9k-devel
Peter Stuge wrote:
> debug Atheros PCI core.
>
> # while :;do lspci -n -A intel-conf1 -s 2:2; sleep .5s; done
> 02:02.0 0280: 168c:0029 (rev 01)
> 02:02.0 0280: 168c:0029 (rev 01)
> 02:02.0 0004: 0000:0004 (rev 08)
Here's some more detail. The first may be the healthy case, but is
quite rare. Invalid BAR 5 is also rare. The other two are common.
# while :;do lspci -n -A intel-conf1 -s 2:2 -xxx; sleep .5s; done
...
02:02.0 0280: 168c:0029 (rev 01)
00: 8c 16 29 00 00 00 b0 82 01 00 80 02 0c 00 00 00
10: 00 00 04 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 8c 16 96 20
30: 00 00 00 00 44 00 00 00 00 00 00 00 00 01 00 00
40: 80 00 00 00 01 00 82 48 00 00 00 00 00 00 00 00
50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
02:02.0 0004: 0000:0004 (rev 08)
00: 00 00 04 00 04 00 04 00 08 00 04 00 0c 00 04 00
10: 10 00 04 00 14 00 04 00 18 00 04 00 1c 00 04 00
20: 20 00 04 00 24 00 04 00 28 00 04 00 2c 00 04 00
30: 30 00 04 00 34 00 04 00 38 00 04 00 3c 00 04 00
40: 40 00 04 00 44 00 04 00 48 00 04 00 4c 00 04 00
50: 50 00 04 00 54 00 04 00 58 00 04 00 5c 00 04 00
60: 60 00 04 00 64 00 04 00 68 00 04 00 6c 00 04 00
70: 70 00 04 00 74 00 04 00 78 00 04 00 7c 00 04 00
80: 80 00 04 00 84 00 04 00 88 00 04 00 8c 00 04 00
90: 90 00 04 00 94 00 04 00 98 00 04 00 9c 00 04 00
a0: a0 00 04 00 a4 00 04 00 a8 00 04 00 ac 00 04 00
b0: b0 00 04 00 b4 00 04 00 b8 00 04 00 bc 00 04 00
c0: c0 00 04 00 c4 00 04 00 c8 00 04 00 cc 00 04 00
d0: d0 00 04 00 d4 00 04 00 d8 00 04 00 dc 00 04 00
e0: e0 00 04 00 e4 00 04 00 e8 00 04 00 ec 00 04 00
f0: f0 00 04 00 f4 00 04 00 f8 00 04 00 fc 00 04 00
02:02.0 0280: 168c:0029 (rev 01)
00: 8c 16 29 00 00 00 b0 82 01 00 80 02 0c 00 00 00
10: 00 00 04 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 8c 16 96 20
30: 00 00 00 00 44 00 00 00 00 00 00 00 00 01 00 00
40: 40 00 04 00 44 00 04 00 48 00 04 00 4c 00 04 00
50: 50 00 04 00 54 00 04 00 58 00 04 00 5c 00 04 00
60: 60 00 04 00 64 00 04 00 68 00 04 00 6c 00 04 00
70: 70 00 04 00 74 00 04 00 78 00 04 00 7c 00 04 00
80: 80 00 04 00 84 00 04 00 88 00 04 00 8c 00 04 00
90: 90 00 04 00 94 00 04 00 98 00 04 00 9c 00 04 00
a0: a0 00 04 00 a4 00 04 00 a8 00 04 00 ac 00 04 00
b0: b0 00 04 00 b4 00 04 00 b8 00 04 00 bc 00 04 00
c0: c0 00 04 00 c4 00 04 00 c8 00 04 00 cc 00 04 00
d0: d0 00 04 00 d4 00 04 00 d8 00 04 00 dc 00 04 00
e0: e0 00 04 00 e4 00 04 00 e8 00 04 00 ec 00 04 00
f0: f0 00 04 00 f4 00 04 00 f8 00 04 00 fc 00 04 00
..
pcilib: 0000:02:02.0: Invalid 64-bit address seen for BAR 5.
02:02.0 0280: 168c:0029 (rev 01)
00: 8c 16 29 00 04 00 b0 82 01 00 80 02 0c 00 00 00
10: 00 00 04 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 20 00 04 00 24 00 04 00 28 00 04 00 2c 00 04 00
30: 30 00 04 00 34 00 04 00 38 00 04 00 3c 00 04 00
40: 40 00 04 00 44 00 04 00 48 00 04 00 4c 00 04 00
50: 50 00 04 00 54 00 04 00 58 00 04 00 5c 00 04 00
60: 60 00 04 00 64 00 04 00 68 00 04 00 6c 00 04 00
70: 70 00 04 00 74 00 04 00 78 00 04 00 7c 00 04 00
80: 80 00 04 00 84 00 04 00 88 00 04 00 8c 00 04 00
90: 90 00 04 00 94 00 04 00 98 00 04 00 9c 00 04 00
a0: a0 00 04 00 a4 00 04 00 a8 00 04 00 ac 00 04 00
b0: b0 00 04 00 b4 00 04 00 b8 00 04 00 bc 00 04 00
c0: c0 00 04 00 c4 00 04 00 c8 00 04 00 cc 00 04 00
d0: d0 00 04 00 d4 00 04 00 d8 00 04 00 dc 00 04 00
e0: e0 00 04 00 e4 00 04 00 e8 00 04 00 ec 00 04 00
f0: f0 00 04 00 f4 00 04 00 f8 00 04 00 fc 00 04 00
//Peter
^ permalink raw reply [flat|nested] 20+ messages in thread
* [ath9k-devel] Open discussion, e.g. about ath9k PCI
2011-02-22 5:56 ` Peter Stuge
@ 2011-02-22 15:29 ` Adrian Chadd
2011-02-23 23:28 ` Peter Stuge
2011-02-24 2:33 ` Peter Stuge
2011-02-24 2:12 ` Peter Stuge
1 sibling, 2 replies; 20+ messages in thread
From: Adrian Chadd @ 2011-02-22 15:29 UTC (permalink / raw)
To: ath9k-devel
Is the hardware in some kind of deep sleep state? Is this on a laptop? It's
an AR9280 (merlin) from that PCI ID, so I'd gather it's in a laptop of some
sort.
If so, can you disable any/all power saving mode(s) and see if that fixes
the PCIe probe?
Adrian
On 22 February 2011 00:56, Peter Stuge <peter@stuge.se> wrote:
> Peter Stuge wrote:
> > debug Atheros PCI core.
> >
> > # while :;do lspci -n -A intel-conf1 -s 2:2; sleep .5s; done
> > 02:02.0 0280: 168c:0029 (rev 01)
> > 02:02.0 0280: 168c:0029 (rev 01)
> > 02:02.0 0004: 0000:0004 (rev 08)
>
> Here's some more detail. The first may be the healthy case, but is
> quite rare. Invalid BAR 5 is also rare. The other two are common.
>
> # while :;do lspci -n -A intel-conf1 -s 2:2 -xxx; sleep .5s; done
> ...
>
> 02:02.0 0280: 168c:0029 (rev 01)
> 00: 8c 16 29 00 00 00 b0 82 01 00 80 02 0c 00 00 00
> 10: 00 00 04 00 00 00 00 00 00 00 00 00 00 00 00 00
> 20: 00 00 00 00 00 00 00 00 00 00 00 00 8c 16 96 20
> 30: 00 00 00 00 44 00 00 00 00 00 00 00 00 01 00 00
> 40: 80 00 00 00 01 00 82 48 00 00 00 00 00 00 00 00
> 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
>
> 02:02.0 0004: 0000:0004 (rev 08)
> 00: 00 00 04 00 04 00 04 00 08 00 04 00 0c 00 04 00
> 10: 10 00 04 00 14 00 04 00 18 00 04 00 1c 00 04 00
> 20: 20 00 04 00 24 00 04 00 28 00 04 00 2c 00 04 00
> 30: 30 00 04 00 34 00 04 00 38 00 04 00 3c 00 04 00
> 40: 40 00 04 00 44 00 04 00 48 00 04 00 4c 00 04 00
> 50: 50 00 04 00 54 00 04 00 58 00 04 00 5c 00 04 00
> 60: 60 00 04 00 64 00 04 00 68 00 04 00 6c 00 04 00
> 70: 70 00 04 00 74 00 04 00 78 00 04 00 7c 00 04 00
> 80: 80 00 04 00 84 00 04 00 88 00 04 00 8c 00 04 00
> 90: 90 00 04 00 94 00 04 00 98 00 04 00 9c 00 04 00
> a0: a0 00 04 00 a4 00 04 00 a8 00 04 00 ac 00 04 00
> b0: b0 00 04 00 b4 00 04 00 b8 00 04 00 bc 00 04 00
> c0: c0 00 04 00 c4 00 04 00 c8 00 04 00 cc 00 04 00
> d0: d0 00 04 00 d4 00 04 00 d8 00 04 00 dc 00 04 00
> e0: e0 00 04 00 e4 00 04 00 e8 00 04 00 ec 00 04 00
> f0: f0 00 04 00 f4 00 04 00 f8 00 04 00 fc 00 04 00
>
> 02:02.0 0280: 168c:0029 (rev 01)
> 00: 8c 16 29 00 00 00 b0 82 01 00 80 02 0c 00 00 00
> 10: 00 00 04 00 00 00 00 00 00 00 00 00 00 00 00 00
> 20: 00 00 00 00 00 00 00 00 00 00 00 00 8c 16 96 20
> 30: 00 00 00 00 44 00 00 00 00 00 00 00 00 01 00 00
> 40: 40 00 04 00 44 00 04 00 48 00 04 00 4c 00 04 00
> 50: 50 00 04 00 54 00 04 00 58 00 04 00 5c 00 04 00
> 60: 60 00 04 00 64 00 04 00 68 00 04 00 6c 00 04 00
> 70: 70 00 04 00 74 00 04 00 78 00 04 00 7c 00 04 00
> 80: 80 00 04 00 84 00 04 00 88 00 04 00 8c 00 04 00
> 90: 90 00 04 00 94 00 04 00 98 00 04 00 9c 00 04 00
> a0: a0 00 04 00 a4 00 04 00 a8 00 04 00 ac 00 04 00
> b0: b0 00 04 00 b4 00 04 00 b8 00 04 00 bc 00 04 00
> c0: c0 00 04 00 c4 00 04 00 c8 00 04 00 cc 00 04 00
> d0: d0 00 04 00 d4 00 04 00 d8 00 04 00 dc 00 04 00
> e0: e0 00 04 00 e4 00 04 00 e8 00 04 00 ec 00 04 00
> f0: f0 00 04 00 f4 00 04 00 f8 00 04 00 fc 00 04 00
>
> ..
>
> pcilib: 0000:02:02.0: Invalid 64-bit address seen for BAR 5.
> 02:02.0 0280: 168c:0029 (rev 01)
> 00: 8c 16 29 00 04 00 b0 82 01 00 80 02 0c 00 00 00
> 10: 00 00 04 00 00 00 00 00 00 00 00 00 00 00 00 00
> 20: 20 00 04 00 24 00 04 00 28 00 04 00 2c 00 04 00
> 30: 30 00 04 00 34 00 04 00 38 00 04 00 3c 00 04 00
> 40: 40 00 04 00 44 00 04 00 48 00 04 00 4c 00 04 00
> 50: 50 00 04 00 54 00 04 00 58 00 04 00 5c 00 04 00
> 60: 60 00 04 00 64 00 04 00 68 00 04 00 6c 00 04 00
> 70: 70 00 04 00 74 00 04 00 78 00 04 00 7c 00 04 00
> 80: 80 00 04 00 84 00 04 00 88 00 04 00 8c 00 04 00
> 90: 90 00 04 00 94 00 04 00 98 00 04 00 9c 00 04 00
> a0: a0 00 04 00 a4 00 04 00 a8 00 04 00 ac 00 04 00
> b0: b0 00 04 00 b4 00 04 00 b8 00 04 00 bc 00 04 00
> c0: c0 00 04 00 c4 00 04 00 c8 00 04 00 cc 00 04 00
> d0: d0 00 04 00 d4 00 04 00 d8 00 04 00 dc 00 04 00
> e0: e0 00 04 00 e4 00 04 00 e8 00 04 00 ec 00 04 00
> f0: f0 00 04 00 f4 00 04 00 f8 00 04 00 fc 00 04 00
>
>
> //Peter
> _______________________________________________
> ath9k-devel mailing list
> ath9k-devel at lists.ath9k.org
> https://lists.ath9k.org/mailman/listinfo/ath9k-devel
>
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^ permalink raw reply [flat|nested] 20+ messages in thread
* [ath9k-devel] Open discussion, e.g. about ath9k PCI
2011-02-22 5:47 ` [ath9k-devel] Open discussion, e.g. about ath9k PCI Peter Stuge
2011-02-22 5:56 ` Peter Stuge
@ 2011-02-22 15:31 ` Adrian Chadd
1 sibling, 0 replies; 20+ messages in thread
From: Adrian Chadd @ 2011-02-22 15:31 UTC (permalink / raw)
To: ath9k-devel
On 22 February 2011 00:47, Peter Stuge <peter@stuge.se> wrote:
> Adrian Chadd wrote:
> > > absolute lack of open discussion about anything firmware level
> >
> > I've had a lot of success with:
> >
> > * tweaking things, and seeing what happens;
>
> This is reverse engineering by trial and error, not open discussion
> with vendor experts. The reverse engineering effort is only made
> slightly less inconvenient by availability of some source code.
Right until you catch the eye of some of the Atheros/ath9k developers who
have access to this stuff.
I admit, that hasn't been the easiest thing to do (and I've been very, very
persistent in the past to try and fix TX power calibration and NF/ADC
calibration in FreeBSD, so a big thankyou to Felix and the others who helped
me!) but it can and does happen.
Adrian
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^ permalink raw reply [flat|nested] 20+ messages in thread
* [ath9k-devel] Open discussion, e.g. about ath9k PCI
2011-02-22 15:29 ` Adrian Chadd
@ 2011-02-23 23:28 ` Peter Stuge
2011-02-24 1:04 ` Peter Stuge
2011-02-24 2:33 ` Peter Stuge
1 sibling, 1 reply; 20+ messages in thread
From: Peter Stuge @ 2011-02-23 23:28 UTC (permalink / raw)
To: ath9k-devel
Adrian Chadd wrote:
> > > # while :;do lspci -n -A intel-conf1 -s 2:2; sleep .5s; done
> > > 02:02.0 0280: 168c:0029 (rev 01)
> > > 02:02.0 0280: 168c:0029 (rev 01)
> > > 02:02.0 0004: 0000:0004 (rev 08)
>
> Is the hardware in some kind of deep sleep state?
Define hardware? I guess you mean chipset.
> Is this on a laptop? It's an AR9280 (merlin) from that PCI ID, so
> I'd gather it's in a laptop of some sort.
Yes, ThinkPad X40, Pentium-M and 855GM.
> If so, can you disable any/all power saving mode(s)
What I can easily change is the cpufreq governor, which is currently
ondemand. I don't think that changing it should affect the chipset
and the bus, but I'll give it a go. I'll grab latest linus git as
well, it's time for an update..
> and see if that fixes the PCIe probe?
Note that this card is not on PCIe, it is a mini-PCI card.
//Peter
^ permalink raw reply [flat|nested] 20+ messages in thread
* [ath9k-devel] Open discussion, e.g. about ath9k PCI
2011-02-23 23:28 ` Peter Stuge
@ 2011-02-24 1:04 ` Peter Stuge
0 siblings, 0 replies; 20+ messages in thread
From: Peter Stuge @ 2011-02-24 1:04 UTC (permalink / raw)
To: ath9k-devel
Peter Stuge wrote:
> > If so, can you disable any/all power saving mode(s)
>
> What I can easily change is the cpufreq governor, which is currently
> ondemand.
In the kernel I am running now I completely disabled cpufreq.
> I'll grab latest linus git as well, it's time for an update..
Sorry, never mind linux-2.6.git. I was running wireless-testing
from Jan 5 before and pulled again just now. I am running:
commit 2f478ddff0bbb3462f46e96e8d2763ea524c2a09
Merge: 09f3227 1472d3a
Author: John W. Linville <linville@tuxdriver.com>
Date: Wed Feb 23 16:59:14 2011 -0500
Merge ssh://master.kernel.org/pub/scm/linux/kernel/git/linville/wireless-next-2.6
> > and see if that fixes the PCIe probe?
I still have the same behavior if I run lspci in a shell loop. And
the problem is there on initial boot, which means that Linux does not
see the card. I've enabled PCI debugging too, but nothing really
useful so far.
[ 0.395120] pci 0000:02:02.0: [0000:0004] type 4 class 0x000004
[ 0.395125] pci 0000:02:02.0: calling quirk_mmio_always_on+0x0/0x1a
[ 0.395129] pci 0000:02:02.0: unknown header type 04, ignoring device
//Peter
^ permalink raw reply [flat|nested] 20+ messages in thread
* [ath9k-devel] Open discussion, e.g. about ath9k PCI
2011-02-22 5:56 ` Peter Stuge
2011-02-22 15:29 ` Adrian Chadd
@ 2011-02-24 2:12 ` Peter Stuge
1 sibling, 0 replies; 20+ messages in thread
From: Peter Stuge @ 2011-02-24 2:12 UTC (permalink / raw)
To: ath9k-devel
Peter Stuge wrote:
> Here's some more detail.
..
> # while :;do lspci -n -A intel-conf1 -s 2:2 -xxx; sleep .5s; done
> ...
>
> 02:02.0 0280: 168c:0029 (rev 01)
> 00: 8c 16 29 00 00 00 b0 82 01 00 80 02 0c 00 00 00
Looking briefly into these registers the Status register (06) bit 15
says that the card has detected a parity error.
If I clear it (setpci -A intel-conf1 -s 2:2 6.w=8000) the card sets
it again.
//Peter
^ permalink raw reply [flat|nested] 20+ messages in thread
* [ath9k-devel] Open discussion, e.g. about ath9k PCI
2011-02-22 15:29 ` Adrian Chadd
2011-02-23 23:28 ` Peter Stuge
@ 2011-02-24 2:33 ` Peter Stuge
2011-02-24 3:21 ` Adrian Chadd
1 sibling, 1 reply; 20+ messages in thread
From: Peter Stuge @ 2011-02-24 2:33 UTC (permalink / raw)
To: ath9k-devel
Adrian Chadd wrote:
> It's an AR9280 (merlin) from that PCI ID,
Well, it's not PCIe, so probably not. But I guess 9220 (which this is
according to my pci.ids) and 9280 may be quite similar.
//Peter
^ permalink raw reply [flat|nested] 20+ messages in thread
* [ath9k-devel] Open discussion, e.g. about ath9k PCI
2011-02-24 2:33 ` Peter Stuge
@ 2011-02-24 3:21 ` Adrian Chadd
0 siblings, 0 replies; 20+ messages in thread
From: Adrian Chadd @ 2011-02-24 3:21 UTC (permalink / raw)
To: ath9k-devel
Yup, if it's PCI (and not PCIe) then it's an AR9220.
Adrian
On 23 February 2011 21:33, Peter Stuge <peter@stuge.se> wrote:
> Adrian Chadd wrote:
> > It's an AR9280 (merlin) from that PCI ID,
>
> Well, it's not PCIe, so probably not. But I guess 9220 (which this is
> according to my pci.ids) and 9280 may be quite similar.
>
>
> //Peter
> _______________________________________________
> ath9k-devel mailing list
> ath9k-devel at lists.ath9k.org
> https://lists.ath9k.org/mailman/listinfo/ath9k-devel
>
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* [ath9k-devel] adjust the CCA (Clear Channel Assessment) value for ath9k
2011-02-15 19:49 ` [ath9k-devel] adjust the CCA (Clear Channel Assessment) value " Brandon Combs
2011-02-16 13:17 ` Mohammed Shafi
@ 2014-03-24 11:53 ` Javi Jap
1 sibling, 0 replies; 20+ messages in thread
From: Javi Jap @ 2014-03-24 11:53 UTC (permalink / raw)
To: ath9k-devel
Brandon Combs <brmcombs <at> iusb.edu> writes:
>
> Sagar Bijwe <sag.bijwe <at> gmail.com> writes:
> >
> > I wish to disable CCA for ath9k. Can anyone tell me how this can be
achieved?
> As far as I see it, modifying values of?AR9280_PHY_CCA_THRESH62????
> AR9280_PHY_CCA_THRESH62_S (present in phy.h)should do. -Sagar
> > _______________________________________________
>
> I also need to adjust the CCA (Clear Channel Assessment)value. Does anyone
know
> how to increase the CCA threshold so that one can get a node to send even
when
> it senses an unclear channel? Here is the code segments from
> /source/drivers/net/wireless/ath/ath9k/ar9002_phy.h which I believe I need
to
> adjust to increase the CCA threshold but I am not quite sure how (thanks
for any
Hi Brandon,
did you finally achieved to modify the noise floor? I am looking for a
similar fix because when scanning with madwifi and ath9k, madwifi shows much
more APs and stations because the noise floor in the ath9k wlan card is set
to -80.
Any help or clue will be apreciated!
^ permalink raw reply [flat|nested] 20+ messages in thread
end of thread, other threads:[~2014-03-24 11:53 UTC | newest]
Thread overview: 20+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2011-02-12 8:52 [ath9k-devel] Disabling CCA for ath9k Sagar Bijwe
2011-02-15 19:49 ` [ath9k-devel] adjust the CCA (Clear Channel Assessment) value " Brandon Combs
2011-02-16 13:17 ` Mohammed Shafi
2011-02-16 14:04 ` Sagar Bijwe
2011-02-17 8:29 ` Mohammed Shafi
2011-02-18 17:10 ` Brandon Combs
2011-02-21 0:19 ` Wright, Brett
2011-02-21 3:55 ` [ath9k-devel] adjust the CCA (Clear Channel Assessment) value?for ath9k Peter Stuge
2011-02-21 17:09 ` Adrian Chadd
2011-02-22 5:47 ` [ath9k-devel] Open discussion, e.g. about ath9k PCI Peter Stuge
2011-02-22 5:56 ` Peter Stuge
2011-02-22 15:29 ` Adrian Chadd
2011-02-23 23:28 ` Peter Stuge
2011-02-24 1:04 ` Peter Stuge
2011-02-24 2:33 ` Peter Stuge
2011-02-24 3:21 ` Adrian Chadd
2011-02-24 2:12 ` Peter Stuge
2011-02-22 15:31 ` Adrian Chadd
2011-02-21 4:52 ` [ath9k-devel] adjust the CCA (Clear Channel Assessment) value for ath9k Mohammed Shafi
2014-03-24 11:53 ` Javi Jap
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