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From: "Michał Mirosław" <mirqus@gmail.com>
To: linux-mmc@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
	kernel@pengutronix.de
Subject: Re: [PATCH 5/9] sdhci-5:add the 32BIT_CMD_TRANS_COMBINATION quirk to support FSl eSDHC
Date: Wed, 1 Sep 2010 19:52:41 +0200	[thread overview]
Message-ID: <AANLkTimHF4uS+ACLOKPmo86sd5Cvb77XdNB2jZNUDeU=@mail.gmail.com> (raw)
In-Reply-To: <1283334494-12678-1-git-send-email-r65037@freescale.com>

2010/9/1 Richard Zhu <r65037@freescale.com>:
> The FSL's eSDHC have one 32bit register that combine the two
> 16bit Transfer Mode and Command registers.
> Add this quirk to let SW driver to support FSL's eSDHC.

What happens if you do this for every SDHCI host? Is there one that
breaks if changing the two registers are combined into single 32-bit
write?

Best Regards,
Michał Mirosław

WARNING: multiple messages have this Message-ID (diff)
From: mirqus@gmail.com (Michał Mirosław)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 5/9] sdhci-5:add the 32BIT_CMD_TRANS_COMBINATION quirk to support FSl eSDHC
Date: Wed, 1 Sep 2010 19:52:41 +0200	[thread overview]
Message-ID: <AANLkTimHF4uS+ACLOKPmo86sd5Cvb77XdNB2jZNUDeU=@mail.gmail.com> (raw)
In-Reply-To: <1283334494-12678-1-git-send-email-r65037@freescale.com>

2010/9/1 Richard Zhu <r65037@freescale.com>:
> The FSL's eSDHC have one 32bit register that combine the two
> 16bit Transfer Mode and Command registers.
> Add this quirk to let SW driver to support FSL's eSDHC.

What happens if you do this for every SDHCI host? Is there one that
breaks if changing the two registers are combined into single 32-bit
write?

Best Regards,
Micha? Miros?aw

  reply	other threads:[~2010-09-01 17:52 UTC|newest]

Thread overview: 4+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2010-09-01  9:48 [PATCH 5/9] sdhci-5:add the 32BIT_CMD_TRANS_COMBINATION quirk to support FSl eSDHC Richard Zhu
2010-09-01  9:48 ` Richard Zhu
2010-09-01 17:52 ` Michał Mirosław [this message]
2010-09-01 17:52   ` Michał Mirosław

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