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* [U-Boot] [PATCH v4 2/7] gpio: Add Multi-Function-Pin configuration driver for Marvell SoCs
  2010-12-07 17:06 ` [U-Boot] [PATCH v4 2/7] gpio: Add Multi-Function-Pin configuration driver for Marvell SoCs Prafulla Wadaskar
@ 2010-12-07 15:23   ` Lei Wen
  2010-12-07 17:10     ` Prafulla Wadaskar
  2010-12-07 17:06   ` [U-Boot] [PATCH v4 3/7] add Multi Function Pin configuration support for ARMADA100 Prafulla Wadaskar
  1 sibling, 1 reply; 23+ messages in thread
From: Lei Wen @ 2010-12-07 15:23 UTC (permalink / raw)
  To: u-boot

Hi Prafulla,

On Wed, Dec 8, 2010 at 1:06 AM, Prafulla Wadaskar <prafulla@marvell.com> wrote:
> Most of the Marvell SoCs has Multi Function Pin (MFP) configuration registers
> For ex. ARMADA100.
>
> These registers are programmed to expose the specific functionality
> associated with respective SoC Pins
>
> This driver provides configuration APIs,
> using them, configuration need to be done in board specific code
>
> for ex- following code configures MFPs 107 and 108 for UART_TX/RX functionality
>
> int board_early_init_f(void)
> {
> ? ? ? ?u32 mfp_cfg[] = {
> ? ? ? ? ? ? ? ?/* Console on UART1 */
> ? ? ? ? ? ? ? ?MFP107_UART1_RXD,
> ? ? ? ? ? ? ? ?MFP108_UART1_TXD,
> ? ? ? ? ? ? ? ?MFP_EOC ? ? ? ? /*End of configureation*/
> ? ? ? ?};
> ? ? ? ?/* configure MFP's */
> ? ? ? ?mfp_config(mfp_cfg);
> ? ? ? ?return 0;
> }
>
> Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>
> ---
> Changelog v4:
> 1. Driver renamed as mvmfp
> 2. Re-architected mvmfp driver as per review feedback
>
> ?drivers/gpio/Makefile | ? ?1 +
> ?drivers/gpio/mvmfp.c ?| ? 90 ++++++++++++++++++++++++++++++++++++++++++++
> ?include/mvmfp.h ? ? ? | ?100 +++++++++++++++++++++++++++++++++++++++++++++++++
> ?3 files changed, 191 insertions(+), 0 deletions(-)
> ?create mode 100644 drivers/gpio/mvmfp.c
> ?create mode 100644 include/mvmfp.h
>
> diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
> index 398024c..a5fa2b5 100644
> --- a/drivers/gpio/Makefile
> +++ b/drivers/gpio/Makefile
> @@ -27,6 +27,7 @@ LIB ? := $(obj)libgpio.o
>
> ?COBJS-$(CONFIG_AT91_GPIO) ? ? ?+= at91_gpio.o
> ?COBJS-$(CONFIG_KIRKWOOD_GPIO) ?+= kw_gpio.o
> +COBJS-$(CONFIG_MARVELL_MFP) ? ?+= mvmfp.o
> ?COBJS-$(CONFIG_MXC_GPIO) ? ? ? += mxc_gpio.o
> ?COBJS-$(CONFIG_PCA953X) ? ? ? ? ? ? ? ?+= pca953x.o
> ?COBJS-$(CONFIG_S5P) ? ? ? ? ? ?+= s5p_gpio.o
> diff --git a/drivers/gpio/mvmfp.c b/drivers/gpio/mvmfp.c
> new file mode 100644
> index 0000000..3472278
> --- /dev/null
> +++ b/drivers/gpio/mvmfp.c
> @@ -0,0 +1,90 @@
> +/*
> + * (C) Copyright 2010
> + * Marvell Semiconductor <www.marvell.com>
> + * Written-by: Prafulla Wadaskar <prafulla@marvell.com>,
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
> + * MA 02110-1301 USA
> + */
> +
> +#include <common.h>
> +#include <asm/io.h>
> +#include <mvmfp.h>
> +#include <asm/arch/mfp.h>
> +#ifdef CONFIG_ARMADA100
> +#include <asm/arch/armada100.h>
> +#define MFPR_BASE ? ? ?ARMD1_MFPR_BASE
> +#else
> +#error Unsupported SoC...
> +#endif

Why not directly name a CONFIG_MFPR_BASE, and define its value in the
config file?
If we do like this ifdef, we may need do add each arch here, seems
some kind of redundant?


> +
> +/*
> + * mfp_config
> + *
> + * On most of Marvell SoCs (ex. ARMADA100) there is Multi-Funtion-Pin
> + * configuration registers to configure each GPIO/Function pin on the
> + * SoC.
> + *
> + * This function reads the array of values for
> + * MFPR_X registers and programms them into respective
> + * Multi-Function Pin registers.
> + * It supports - Alternate Function Selection programming.
> + *
> + * Whereas,
> + * The Configureation value is constructed using MFP()
> + * array consists of 32bit values as defined in MFP(xx,xx..) macro
> + */
> +void mfp_config(u32 *mfp_cfgs)
> +{
> + ? ? ? u32 *p_mfpr = NULL;
> + ? ? ? u32 cfg_val, val=0;
> +
> + ? ? ? do {
> + ? ? ? ? ? ? ? cfg_val = *mfp_cfgs++;
> + ? ? ? ? ? ? ? /* exit if End of configuration table detected */
> + ? ? ? ? ? ? ? if (cfg_val == MFP_EOC)
> + ? ? ? ? ? ? ? ? ? ? ? break;
> +
> + ? ? ? ? ? ? ? p_mfpr = (u32 *)(MFPR_BASE + MFP_REG_GET_OFFSET(cfg_val));



> +
> + ? ? ? ? ? ? ? /* Write a mfg register as per configuration */
> + ? ? ? ? ? ? ? if (cfg_val & MFP_AF_FLAG) {
> + ? ? ? ? ? ? ? ? ? ? ? /* Abstract and program Afternate-Func Selection */
> + ? ? ? ? ? ? ? ? ? ? ? val &= ~MFP_AF_MASK;
Do we need to do this & here? For val is only 0 here...
Should not it be more concise like:
writel(cfg_val, p_mfpr);


> + ? ? ? ? ? ? ? ? ? ? ? val |= cfg_val & MFP_AF_MASK;
> + ? ? ? ? ? ? ? } if (cfg_val & MFP_EDGE_FLAG) {
> + ? ? ? ? ? ? ? ? ? ? ? /* Abstract and program Edge configuration */
> + ? ? ? ? ? ? ? ? ? ? ? val &= ~MFP_LPM_EDGE_MASK;
> + ? ? ? ? ? ? ? ? ? ? ? val |= cfg_val & MFP_LPM_EDGE_MASK;
> + ? ? ? ? ? ? ? } if (cfg_val & MFP_DRIVE_FLAG) {
> + ? ? ? ? ? ? ? ? ? ? ? /* Abstract and program Drive configuration */
> + ? ? ? ? ? ? ? ? ? ? ? val &= ~MFP_DRIVE_MASK;
> + ? ? ? ? ? ? ? ? ? ? ? val |= cfg_val & MFP_DRIVE_MASK;
> + ? ? ? ? ? ? ? } if (cfg_val & MFP_PULL_FLAG) {
> + ? ? ? ? ? ? ? ? ? ? ? /* Abstract and program Pullup/down configuration */
> + ? ? ? ? ? ? ? ? ? ? ? val &= ~MFP_PULL_MASK;
> + ? ? ? ? ? ? ? ? ? ? ? val |= cfg_val & MFP_PULL_MASK;
> + ? ? ? ? ? ? ? }
> + ? ? ? ? ? ? ? writel(val, p_mfpr);
> + ? ? ? } while (1);
> + ? ? ? /*
> + ? ? ? ?* perform a read-back of any MFPR register to make sure the
> + ? ? ? ?* previous writings are finished
> + ? ? ? ?*/
> + ? ? ? readl(p_mfpr);
> +}
> diff --git a/include/mvmfp.h b/include/mvmfp.h
> new file mode 100644
> index 0000000..0b36393
> --- /dev/null
> +++ b/include/mvmfp.h
> @@ -0,0 +1,100 @@
> +/*
> + * (C) Copyright 2010
> + * Marvell Semiconductor <www.marvell.com>
> + * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
> + * MA 02110-1301 USA
> + */
> +
> +#ifndef __MVMFP_H
> +#define __MVMFP_H
> +
> +/*
> + * Header file for MultiFunctionPin (MFP) Configururation framework
> + *
> + * Processors Supported:
> + * 1. Marvell ARMADA100 Processors
> + *
> + * processor to be supported should be added here
> + */
> +
> +/*
> + * MFP configuration is represented by a 32-bit unsigned integer
> + */
> +#define MFP(_off, _pull, _pF, _drv, _dF, _edge, _eF, _afn, _aF) ( \
> + ? ? ? /* bits 31..16 - MFP Register Offset */ (((_off) & 0xffff) << 16) | \
> + ? ? ? /* bits 15..13 - Run Mode Pull State */ (((_pull) & 0x7) << 13) | \
> + ? ? ? /* bit ?12 ? ? - Unused */ \
> + ? ? ? /* bits 11..10 - Driver Strength */ ? ? (((_drv) & 0x3) << 10) | \
> + ? ? ? /* bit ?09 ? ? - Pull State flag */ ? ? (((_pF) & 0x1) << 9) | \
> + ? ? ? /* bit ?08 ? ? - Drv-strength flag */ ? (((_dF) & 0x1) << 8) | \
> + ? ? ? /* bit ?07 ? ? - Edge-det flag */ ? ? ? (((_eF) & 0x1) << 7) | \
> + ? ? ? /* bits 06..04 - Edge Detection */ ? ? ?(((_edge) & 0x7) << 4) | \
> + ? ? ? /* bits 03..00 - Alt-fun flag */ ? ? ? ?(((_aF) & 0x1) << 3) | \
> + ? ? ? /* bits Alternate-fun select */ ? ? ? ? ((_afn) & 0x7))
> +
> +/*
> + * to facilitate the definition, the following macros are provided
> + *
> + * ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? offset, pull,pF, drv,dF, edge,eF ,afn,aF
> + */
> +#define MFP_OFFSET_MASK ? ? ? ? ? ? ? ?MFP(0xffff, ? ?0,0, ? ?0,0, ? ? 0,0, ? 0,0)
> +#define MFP_REG(x) ? ? ? ? ? ? MFP(x, ? ? ? ? 0,0, ? ?0,0, ? ? 0,0, ? 0,0)
> +#define MFP_REG_GET_OFFSET(x) ?((x & MFP_OFFSET_MASK) >> 16)
> +
> +#define MFP_AF_FLAG ? ? ? ? ? ?MFP(0x0000, ? ?0,0, ? ?0,0, ? ? 0,0, ? 0,1)
> +#define MFP_DRIVE_FLAG ? ? ? ? MFP(0x0000, ? ?0,0, ? ?0,1, ? ? 0,0, ? 0,0)
> +#define MFP_EDGE_FLAG ? ? ? ? ?MFP(0x0000, ? ?0,0, ? ?0,0, ? ? 0,1, ? 0,0)
> +#define MFP_PULL_FLAG ? ? ? ? ?MFP(0x0000, ? ?0,1, ? ?0,0, ? ? 0,0, ? 0,0)
> +
> +#define MFP_AF0 ? ? ? ? ? ? ? ? ? ? ? ?MFP(0x0000, ? ?0,0, ? ?0,0, ? ? 0,0, ? 0,1)
> +#define MFP_AF1 ? ? ? ? ? ? ? ? ? ? ? ?MFP(0x0000, ? ?0,0, ? ?0,0, ? ? 0,0, ? 1,1)
> +#define MFP_AF2 ? ? ? ? ? ? ? ? ? ? ? ?MFP(0x0000, ? ?0,0, ? ?0,0, ? ? 0,0, ? 2,1)
> +#define MFP_AF3 ? ? ? ? ? ? ? ? ? ? ? ?MFP(0x0000, ? ?0,0, ? ?0,0, ? ? 0,0, ? 3,1)
> +#define MFP_AF4 ? ? ? ? ? ? ? ? ? ? ? ?MFP(0x0000, ? ?0,0, ? ?0,0, ? ? 0,0, ? 4,1)
> +#define MFP_AF5 ? ? ? ? ? ? ? ? ? ? ? ?MFP(0x0000, ? ?0,0, ? ?0,0, ? ? 0,0, ? 5,1)
> +#define MFP_AF6 ? ? ? ? ? ? ? ? ? ? ? ?MFP(0x0000, ? ?0,0, ? ?0,0, ? ? 0,0, ? 6,1)
> +#define MFP_AF7 ? ? ? ? ? ? ? ? ? ? ? ?MFP(0x0000, ? ?0,0, ? ?0,0, ? ? 0,0, ? 7,1)
> +#define MFP_AF_MASK ? ? ? ? ? ?MFP(0x0000, ? ?0,0, ? ?0,0, ? ? 0,0, ? 7,0)
> +
> +#define MFP_LPM_EDGE_NONE ? ? ?MFP(0x0000, ? ?0,0, ? ?0,0, ? ? 0,1, ? 0,0)
> +#define MFP_LPM_EDGE_RISE ? ? ?MFP(0x0000, ? ?0,0, ? ?0,0, ? ? 1,1, ? 0,0)
> +#define MFP_LPM_EDGE_FALL ? ? ?MFP(0x0000, ? ?0,0, ? ?0,0, ? ? 2,1, ? 0,0)
> +#define MFP_LPM_EDGE_BOTH ? ? ?MFP(0x0000, ? ?0,0, ? ?0,0, ? ? 3,1, ? 0,0)
> +#define MFP_LPM_EDGE_MASK ? ? ?MFP(0x0000, ? ?0,0, ? ?0,0, ? ? 3,0, ? 0,0)
> +
> +#define MFP_DRIVE_VERY_SLOW ? ?MFP(0x0000, ? ?0,0, ? ?0,1, ? ? 0,0, ? 0,0)
> +#define MFP_DRIVE_SLOW ? ? ? ? MFP(0x0000, ? ?0,0, ? ?1,1, ? ? 0,0, ? 0,0)
> +#define MFP_DRIVE_MEDIUM ? ? ? MFP(0x0000, ? ?0,0, ? ?2,1, ? ? 0,0, ? 0,0)
> +#define MFP_DRIVE_FAST ? ? ? ? MFP(0x0000, ? ?0,0, ? ?3,1, ? ? 0,0, ? 0,0)
> +#define MFP_DRIVE_MASK ? ? ? ? MFP(0x0000, ? ?0,0, ? ?3,0, ? ? 0,0, ? 0,0)
> +
> +#define MFP_PULL_NONE ? ? ? ? ?MFP(0x0000, ? ?0,1, ? ?0,0, ? ? 0,0, ? 0,0)
> +#define MFP_PULL_LOW ? ? ? ? ? MFP(0x0000, ? ?1,1, ? ?0,0, ? ? 0,0, ? 0,0)
> +#define MFP_PULL_HIGH ? ? ? ? ?MFP(0x0000, ? ?2,1, ? ?0,0, ? ? 0,0, ? 0,0)
> +#define MFP_PULL_BOTH ? ? ? ? ?MFP(0x0000, ? ?3,1, ? ?0,0, ? ? 0,0, ? 0,0)
> +#define MFP_PULL_FLOAT ? ? ? ? MFP(0x0000, ? ?4,1, ? ?0,0, ? ? 0,0, ? 0,0)
> +#define MFP_PULL_MASK ? ? ? ? ?MFP(0x0000, ? ?7,0, ? ?0,0, ? ? 0,0, ? 0,0)
> +
> +#define MFP_EOC ? ? ? ? ? ? ? ? ? ? ? ?0xffffffff ? ? ?/* indicates end-of-conf */
> +
> +/* Functions */
> +void mfp_config(u32 *mfp_cfgs);
> +
> +#endif /* __MVMFP_H */
> --
> 1.5.3.4
>
Best regards,
Lei

^ permalink raw reply	[flat|nested] 23+ messages in thread

* [U-Boot] [PATCH v4 6/7] mv-common.h: Add support for ARMADA100 Platforms
  2010-12-07 17:06         ` [U-Boot] [PATCH v4 6/7] mv-common.h: Add support for ARMADA100 Platforms Prafulla Wadaskar
@ 2010-12-07 15:32           ` Lei Wen
  2010-12-07 16:58             ` Prafulla Wadaskar
  2010-12-07 17:06           ` [U-Boot] [PATCH v4 7/7] Armada100: Add Board Support for Marvell Aspenite-DB Prafulla Wadaskar
  1 sibling, 1 reply; 23+ messages in thread
From: Lei Wen @ 2010-12-07 15:32 UTC (permalink / raw)
  To: u-boot

Hi Prafulla,

On Wed, Dec 8, 2010 at 1:06 AM, Prafulla Wadaskar <prafulla@marvell.com> wrote:
> This patch adds commonly used macros for ARMADA100 based
> baords, Also some code reshuffled and updated for typos and comments
>
> Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>
> ---
> Changelog v3:
> CONFIG_ARCH_CPU_INIT moved out of #ifdef
>
> Changelog v4:
> CONFIG_MFP change to CONFIG_MARVELL_MFP
> some whitespaces removed
>
> ?include/configs/mv-common.h | ? 65 ++++++++++++++++++++++++++++++++----------
> ?1 files changed, 49 insertions(+), 16 deletions(-)
>
> diff --git a/include/configs/mv-common.h b/include/configs/mv-common.h
> index 0a76163..067527a 100644
> --- a/include/configs/mv-common.h
> +++ b/include/configs/mv-common.h
> @@ -39,6 +39,7 @@
> ?#define CONFIG_MARVELL ? ? ? ? 1
> ?#define CONFIG_ARM926EJS ? ? ? 1 ? ? ? /* Basic Architecture */
>
> +/* ====> Kirkwood Platform Common Definations */
> ?#if defined(CONFIG_KIRKWOOD)
> ?#define CONFIG_MD5 ? ? /* get_random_hex on krikwood needs MD5 support */
> ?#define CONFIG_KIRKWOOD_EGIGA_INIT ? ? /* Enable GbePort0/1 for kernel */
> @@ -54,27 +55,45 @@
> ?#define ? ? ? ?CONFIG_SYS_KWD_CONFIG ? $(SRCTREE)/$(CONFIG_BOARDDIR)/kwbimage.cfg
> ?#endif /* CONFIG_SYS_KWD_CONFIG */
>
> -/*
> - * CONFIG_SYS_TEXT_BASE can be defined in board specific header file, if needed
> - */
> -#ifndef CONFIG_SYS_TEXT_BASE
> -#define ? ? ? ?CONFIG_SYS_TEXT_BASE ? ?0x00600000
> -#endif /* CONFIG_SYS_TEXT_BASE */
> +/* Kirkwood has 2k of Security SRAM, use it for SP */
> +#define CONFIG_SYS_INIT_SP_ADDR ? ? ? ? ? ? ? ?0xC8012000
> +#define CONFIG_NR_DRAM_BANKS_MAX ? ? ? 2
>
> ?#define CONFIG_I2C_MVTWSI_BASE KW_TWSI_BASE
> -#define MV_UART0_BASE ? ? ? ? ?KW_UART0_BASE
> +#define MV_UART_CONSOLE_BASE ? KW_UART0_BASE

Could we just define the uart base as hard coding one here? For it
must refer to the .h
file in the arch/arm/include directory, which make no sense for the
configure file.

> ?#define MV_SATA_BASE ? ? ? ? ? KW_SATA_BASE
> ?#define MV_SATA_PORT0_OFFSET ? KW_SATA_PORT0_OFFSET
> ?#define MV_SATA_PORT1_OFFSET ? KW_SATA_PORT1_OFFSET
>
> +/* ====> ARMADA100 Platform Common Definations */

I think you probably need to think to seperate armada100 sepecific and
kirkwood specific stuff from mv-common.h now.
For those two kind of definition makes mv-common not so common as it is.

> +#elif defined (CONFIG_ARMADA100)
> +
> +#define CONFIG_SYS_TCLK ? ? ? ? ? ? ? ?(14745600) ? ? ?/* NS16550 clk config */
> +#define CONFIG_SYS_HZ_CLOCK ? ?(3250000) ? ? ? /* Timer Freq. 3.25MHZ */
> +#define CONFIG_MARVELL_MFP ? ? ? ? ? ? ? ? ? ? /* Enable mvmfp driver */
> +#define MV_UART_CONSOLE_BASE ? ARMD1_UART1_BASE
> +#define CONFIG_SYS_NS16550_IER (1 << 6) ? ? ? ?/* Bit 6 in UART_IER register
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? represents UART Unit Enable */
> +/*
> + * There is no internal RAM in ARMADA100, using DRAM
> + * TBD: dcache to be used for this
> + */
> +#define CONFIG_SYS_INIT_SP_ADDR ? ? ? ? ? ? ? ?(CONFIG_SYS_TEXT_BASE - 0x00200000)
> +#define CONFIG_NR_DRAM_BANKS_MAX ? ? ? 2
> +
> ?#else
> -#error "Unsupported SoC"
> +#error "Unsupported SoC Platform..."
> ?#endif
>
> +/*
> + * Custom CONFIG_SYS_TEXT_BASE can be done in <board>.h
> + */
> +#ifndef CONFIG_SYS_TEXT_BASE
> +#define ? ? ? ?CONFIG_SYS_TEXT_BASE ? ?0x00600000
> +#endif /* CONFIG_SYS_TEXT_BASE */
> +
> ?/* additions for new ARM relocation support */
> -#define CONFIG_SYS_SDRAM_BASE ? ? ? ? ?0x00000000
> -/* Kirkwood has 2k of Security SRAM, use it for SP */
> -#define CONFIG_SYS_INIT_SP_ADDR ? ? ? ? ? ? ? ?0xC8012000
> +#define CONFIG_SYS_SDRAM_BASE ?0x00000000
>
> ?/*
> ?* CLKs configurations
> @@ -88,7 +107,7 @@
> ?#define CONFIG_SYS_NS16550_SERIAL
> ?#define CONFIG_SYS_NS16550_REG_SIZE ? ?(-4)
> ?#define CONFIG_SYS_NS16550_CLK ? ? ? ? CONFIG_SYS_TCLK
> -#define CONFIG_SYS_NS16550_COM1 ? ? ? ? ? ? ? ?MV_UART0_BASE
> +#define CONFIG_SYS_NS16550_COM1 ? ? ? ? ? ? ? ?MV_UART_CONSOLE_BASE
>
> ?/*
> ?* Serial Port configuration
> @@ -156,25 +175,37 @@
> ?#define CONFIG_CMDLINE_EDITING
> ?#define CONFIG_CONSOLE_INFO_QUIET ? ? ?/* some code reduction */
> ?#define CONFIG_ARCH_CPU_INIT ? /* call arch_cpu_init() */
> +#ifndef CONFIG_ARMADA100 ? ? ? /* will be removed latter */
> ?#define CONFIG_ARCH_MISC_INIT ?/* call arch_misc_init() */
> +#endif /* CONFIG_ARMADA100 */
> ?#define CONFIG_BOARD_EARLY_INIT_F /* call board_init_f for early inits */
> ?#define CONFIG_DISPLAY_CPUINFO /* Display cpu info */
> -#define CONFIG_NR_DRAM_BANKS ? 4
> ?#define CONFIG_STACKSIZE ? ? ? 0x00100000 ? ? ?/* regular stack- 1M */
> ?#define CONFIG_SYS_LOAD_ADDR ? 0x00800000 ? ? ?/* default load adr- 8M */
> -#define CONFIG_SYS_MEMTEST_START 0x00400000 ? ?/* 4M */
> -#define CONFIG_SYS_MEMTEST_END 0x007fffff ? ? ?/*(_8M -1) */
> +#define CONFIG_SYS_MEMTEST_START 0x00800000 ? ?/* 8M */
> +#define CONFIG_SYS_MEMTEST_END 0x00ffffff ? ? ?/*(_16M -1) */
> ?#define CONFIG_SYS_RESET_ADDRESS 0xffff0000 ? ?/* Rst Vector Adr */
> ?#define CONFIG_SYS_MAXARGS ? ? 16 ? ? ?/* max number of command args */
>
> ?/*
> + * DRAM Banks configuration, Custom config can be done in <board>.h
> + */
> +#ifndef CONFIG_NR_DRAM_BANKS
> +#define CONFIG_NR_DRAM_BANKS ? CONFIG_NR_DRAM_BANKS_MAX
> +#else
> +#if (CONFIG_NR_DRAM_BANKS > CONFIG_NR_DRAM_BANKS_MAX)
> +#error CONFIG_NR_DRAM_BANKS Configurated more than available
> +#endif
> +#endif /* CONFIG_NR_DRAM_BANKS */
> +
> +/*
> ?* Ethernet Driver configuration
> ?*/
> ?#ifdef CONFIG_CMD_NET
> ?#define CONFIG_CMD_MII
> ?#define CONFIG_NETCONSOLE ? ? ?/* include NetConsole support ? */
> ?#define CONFIG_NET_MULTI ? ? ? /* specify more that one ports available */
> -#define ? ? ? ?CONFIG_MII ? ? ? ? ? ? ?/* expose smi ove miiphy interface */
> +#define CONFIG_MII ? ? ? ? ? ? /* expose smi ove miiphy interface */
> ?#define CONFIG_MVGBE ? ? ? ? ? /* Enable Marvell Gbe Controller Driver */
> ?#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN ? ? ? ?/* detect link using phy */
> ?#define CONFIG_ENV_OVERWRITE ? /* ethaddr can be reprogrammed */
> @@ -232,6 +263,7 @@
> ?/*
> ?* File system
> ?*/
> +#ifndef CONFIG_ARMADA100 ? ? ? /* will be removed latter */
We may need think how to remove it later now...

> ?#define CONFIG_CMD_EXT2
> ?#define CONFIG_CMD_JFFS2
> ?#define CONFIG_CMD_FAT
> @@ -242,5 +274,6 @@
> ?#define CONFIG_MTD_PARTITIONS
> ?#define CONFIG_CMD_MTDPARTS
> ?#define CONFIG_LZO
> +#endif /* CONFIG_ARMADA100 */
>
> ?#endif /* _MV_COMMON_H */
> --
> 1.5.3.4

Best regards,
Lei

^ permalink raw reply	[flat|nested] 23+ messages in thread

* [U-Boot] [PATCH v4 6/7] mv-common.h: Add support for ARMADA100 Platforms
  2010-12-07 15:32           ` Lei Wen
@ 2010-12-07 16:58             ` Prafulla Wadaskar
  0 siblings, 0 replies; 23+ messages in thread
From: Prafulla Wadaskar @ 2010-12-07 16:58 UTC (permalink / raw)
  To: u-boot



> -----Original Message-----
> From: Lei Wen [mailto:adrian.wenl at gmail.com]
> Sent: Tuesday, December 07, 2010 9:02 PM
> To: Prafulla Wadaskar
> Cc: u-boot at lists.denx.de; Eric Miao; Manas Saksena; Lei Wen; Yu Tang;
> Ashish Karkare; Kiran Vedere; Prabhanjan Sarnaik
> Subject: Re: [U-Boot] [PATCH v4 6/7] mv-common.h: Add support for
> ARMADA100 Platforms
> 
> Hi Prafulla,
> 
> On Wed, Dec 8, 2010 at 1:06 AM, Prafulla Wadaskar <prafulla@marvell.com>
> wrote:
> > This patch adds commonly used macros for ARMADA100 based
> > baords, Also some code reshuffled and updated for typos and comments
> >
> > Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>
> > ---
> > Changelog v3:
> > CONFIG_ARCH_CPU_INIT moved out of #ifdef
> >
> > Changelog v4:
> > CONFIG_MFP change to CONFIG_MARVELL_MFP
> > some whitespaces removed
> >
> > ?include/configs/mv-common.h | ? 65 ++++++++++++++++++++++++++++++++----
> ------
> > ?1 files changed, 49 insertions(+), 16 deletions(-)
> >
> > diff --git a/include/configs/mv-common.h b/include/configs/mv-common.h
> > index 0a76163..067527a 100644
> > --- a/include/configs/mv-common.h
> > +++ b/include/configs/mv-common.h
> > @@ -39,6 +39,7 @@
> > ?#define CONFIG_MARVELL ? ? ? ? 1
> > ?#define CONFIG_ARM926EJS ? ? ? 1 ? ? ? /* Basic Architecture */
> >
> > +/* ====> Kirkwood Platform Common Definations */
> > ?#if defined(CONFIG_KIRKWOOD)
> > ?#define CONFIG_MD5 ? ? /* get_random_hex on krikwood needs MD5 support
> */
> > ?#define CONFIG_KIRKWOOD_EGIGA_INIT ? ? /* Enable GbePort0/1 for kernel
> */
> > @@ -54,27 +55,45 @@
> > ?#define ? ? ? ?CONFIG_SYS_KWD_CONFIG
> $(SRCTREE)/$(CONFIG_BOARDDIR)/kwbimage.cfg
> > ?#endif /* CONFIG_SYS_KWD_CONFIG */
> >
> > -/*
> > - * CONFIG_SYS_TEXT_BASE can be defined in board specific header file,
> if needed
> > - */
> > -#ifndef CONFIG_SYS_TEXT_BASE
> > -#define ? ? ? ?CONFIG_SYS_TEXT_BASE ? ?0x00600000
> > -#endif /* CONFIG_SYS_TEXT_BASE */
> > +/* Kirkwood has 2k of Security SRAM, use it for SP */
> > +#define CONFIG_SYS_INIT_SP_ADDR ? ? ? ? ? ? ? ?0xC8012000
> > +#define CONFIG_NR_DRAM_BANKS_MAX ? ? ? 2
> >
> > ?#define CONFIG_I2C_MVTWSI_BASE KW_TWSI_BASE
> > -#define MV_UART0_BASE ? ? ? ? ?KW_UART0_BASE
> > +#define MV_UART_CONSOLE_BASE ? KW_UART0_BASE
> 
> Could we just define the uart base as hard coding one here? For it
> must refer to the .h
> file in the arch/arm/include directory, which make no sense for the
> configure file.

NACK, Console can be on any one of available UART.

> 
> > ?#define MV_SATA_BASE ? ? ? ? ? KW_SATA_BASE
> > ?#define MV_SATA_PORT0_OFFSET ? KW_SATA_PORT0_OFFSET
> > ?#define MV_SATA_PORT1_OFFSET ? KW_SATA_PORT1_OFFSET
> >
> > +/* ====> ARMADA100 Platform Common Definations */
> 
> I think you probably need to think to seperate armada100 sepecific and
> kirkwood specific stuff from mv-common.h now.
> For those two kind of definition makes mv-common not so common as it is.

NACK, objective of mv-common.h to abstract marvell specific stuff.
There is no sense making SoC specific .h

...snip...
> > +#define CONFIG_MII ? ? ? ? ? ? /* expose smi ove miiphy interface */
> > ?#define CONFIG_MVGBE ? ? ? ? ? /* Enable Marvell Gbe Controller Driver
> */
> > ?#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN ? ? ? ?/* detect link using phy
> */
> > ?#define CONFIG_ENV_OVERWRITE ? /* ethaddr can be reprogrammed */
> > @@ -232,6 +263,7 @@
> > ?/*
> > ?* File system
> > ?*/
> > +#ifndef CONFIG_ARMADA100 ? ? ? /* will be removed latter */
> We may need think how to remove it later now...

Sure, when we will support respective peripheral, this will be removed.

Regards..
Prafulla . .

^ permalink raw reply	[flat|nested] 23+ messages in thread

* [U-Boot] [PATCH v4 1/7] arm: Add Support for Marvell ARMADA 100 Familiy SoCs
@ 2010-12-07 17:06 Prafulla Wadaskar
  2010-12-07 17:06 ` [U-Boot] [PATCH v4 2/7] gpio: Add Multi-Function-Pin configuration driver for Marvell SoCs Prafulla Wadaskar
                   ` (2 more replies)
  0 siblings, 3 replies; 23+ messages in thread
From: Prafulla Wadaskar @ 2010-12-07 17:06 UTC (permalink / raw)
  To: u-boot

ARMADA 100 Family processors are highly integrated SoCs
based on Sheeva_88SV331x-v5 PJ1 cpu core.
Ref: http://www.marvell.com/products/processors/applications/armada_100

SoC versions Supported:
1) ARMADA168/88AP168	(Aspen P)
2) ARMADA166/88AP166	(Aspen M)
3) ARMADA162/88AP162	(Aspen L)

Contributors:
Eric Miao <eric.y.miao@marvell.com>
Lei Wen <leiwen@marvell.com>
Mahavir Jain <mjain@marvell.com>

Signed-off-by: Mahavir Jain <mjain@marvell.com>
Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>
---
Change log V2:
1. C-struct used for dram.c
2. lib declaration changed from .a to .o
3. Implemented review feedback for v1

Changelog V3:
1. timer variables in gt_t used insted of locally defined global variables
2. register global pointer moved to respective functions
3. Macro READ_TIMER converted to function read_timer()
4. c-struc in armada100.h fixed for wrong padding

Changelog V4:
1. timer.c updated for build warning

 arch/arm/cpu/arm926ejs/armada100/Makefile       |   46 +++++
 arch/arm/cpu/arm926ejs/armada100/cpu.c          |   92 ++++++++++
 arch/arm/cpu/arm926ejs/armada100/dram.c         |  131 ++++++++++++++
 arch/arm/cpu/arm926ejs/armada100/timer.c        |  207 +++++++++++++++++++++++
 arch/arm/include/asm/arch-armada100/armada100.h |  121 +++++++++++++
 arch/arm/include/asm/arch-armada100/cpu.h       |   53 ++++++
 6 files changed, 650 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/cpu/arm926ejs/armada100/Makefile
 create mode 100644 arch/arm/cpu/arm926ejs/armada100/cpu.c
 create mode 100644 arch/arm/cpu/arm926ejs/armada100/dram.c
 create mode 100644 arch/arm/cpu/arm926ejs/armada100/timer.c
 create mode 100644 arch/arm/include/asm/arch-armada100/armada100.h
 create mode 100644 arch/arm/include/asm/arch-armada100/cpu.h

diff --git a/arch/arm/cpu/arm926ejs/armada100/Makefile b/arch/arm/cpu/arm926ejs/armada100/Makefile
new file mode 100644
index 0000000..76bd06d
--- /dev/null
+++ b/arch/arm/cpu/arm926ejs/armada100/Makefile
@@ -0,0 +1,46 @@
+#
+# (C) Copyright 2010
+# Marvell Semiconductor <www.marvell.com>
+# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+# MA 02110-1301 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(SOC).o
+
+COBJS-y	= cpu.o timer.o dram.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS-y))
+
+all:	$(obj).depend $(LIB)
+
+$(LIB):	$(OBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS)
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/arch/arm/cpu/arm926ejs/armada100/cpu.c b/arch/arm/cpu/arm926ejs/armada100/cpu.c
new file mode 100644
index 0000000..62aa175
--- /dev/null
+++ b/arch/arm/cpu/arm926ejs/armada100/cpu.c
@@ -0,0 +1,92 @@
+/*
+ * (C) Copyright 2010
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ * Contributor: Mahavir Jain <mjain@marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <common.h>
+#include <asm/arch/armada100.h>
+#include <asm/io.h>
+
+#define UARTCLK14745KHZ	(APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(1))
+#define SET_MRVL_ID	(1<<8)
+#define L2C_RAM_SEL	(1<<4)
+
+int arch_cpu_init(void)
+{
+	u32 val;
+	struct armd1cpu_registers *cpuregs =
+		(struct armd1cpu_registers *) ARMD1_CPU_BASE;
+
+	struct armd1apb1_registers *apb1clkres =
+		(struct armd1apb1_registers *) ARMD1_APBC1_BASE;
+
+	struct armd1mpmu_registers *mpmu =
+		(struct armd1mpmu_registers *) ARMD1_MPMU_BASE;
+
+	/* set SEL_MRVL_ID bit in ARMADA100_CPU_CONF register */
+	val = readl(&cpuregs->cpu_conf);
+	val = val | SET_MRVL_ID;
+	writel(val, &cpuregs->cpu_conf);
+
+	/* Enable Clocks for all hardware units */
+	writel(0xFFFFFFFF, &mpmu->acgr);
+
+	/* Turn on AIB and AIB-APB Functional clock */
+	writel(APBC_APBCLK | APBC_FNCLK, &apb1clkres->aib);
+
+	/* ensure L2 cache is not mapped as SRAM */
+	val = readl(&cpuregs->cpu_conf);
+	val = val & ~(L2C_RAM_SEL);
+	writel(val, &cpuregs->cpu_conf);
+
+	/* Enable GPIO clock */
+	writel(APBC_APBCLK, &apb1clkres->gpio);
+
+	/*
+	 * Enable Functional and APB clock at 14.7456MHz
+	 * for configured UART console
+	 */
+#if (CONFIG_SYS_NS16550_COM1 == ARMD1_UART3_BASE)
+	writel(UARTCLK14745KHZ, &apb1clkres->uart3);
+#elif (CONFIG_SYS_NS16550_COM1 == ARMD1_UART2_BASE)
+	writel(UARTCLK14745KHZ, &apb1clkres->uart2);
+#else
+	writel(UARTCLK14745KHZ, &apb1clkres->uart1);
+#endif
+	icache_enable();
+
+	return 0;
+}
+
+#if defined(CONFIG_DISPLAY_CPUINFO)
+int print_cpuinfo(void)
+{
+	u32 id;
+	struct armd1cpu_registers *cpuregs =
+		(struct armd1cpu_registers *) ARMD1_CPU_BASE;
+
+	id = readl(&cpuregs->chip_id);
+	printf("SoC:   Armada 88AP%X-%X\n", (id & 0xFFF), (id >> 0x10));
+	return 0;
+}
+#endif
diff --git a/arch/arm/cpu/arm926ejs/armada100/dram.c b/arch/arm/cpu/arm926ejs/armada100/dram.c
new file mode 100644
index 0000000..eacec23
--- /dev/null
+++ b/arch/arm/cpu/arm926ejs/armada100/dram.c
@@ -0,0 +1,131 @@
+/*
+ * (C) Copyright 2010
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>,
+ * Contributor: Mahavir Jain <mjain@marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <common.h>
+#include <asm/arch/armada100.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * ARMADA100 DRAM controller supports upto 8 banks
+ * for chip select 0 and 1
+ */
+
+/*
+ * DDR Memory Control Registers
+ * Refer Datasheet Appendix A.17
+ */
+struct armd1ddr_map_registers {
+	u32	cs;	/* Memory Address Map Register -CS */
+	u32	pad[3];
+};
+
+struct armd1ddr_registers {
+	u8	pad[0x100 - 0x000];
+	struct armd1ddr_map_registers mmap[2];
+};
+
+/*
+ * armd1_sdram_base - reads SDRAM Base Address Register
+ */
+u32 armd1_sdram_base(int chip_sel)
+{
+	struct armd1ddr_registers *ddr_regs =
+		(struct armd1ddr_registers *)ARMD1_DRAM_BASE;
+	u32 result = 0;
+	u32 CS_valid = 0x01 & readl(&ddr_regs->mmap[chip_sel].cs);
+
+	if (!CS_valid)
+		return 0;
+
+	result = readl(&ddr_regs->mmap[chip_sel].cs) & 0xFF800000;
+	return result;
+}
+
+/*
+ * armd1_sdram_size - reads SDRAM size
+ */
+u32 armd1_sdram_size(int chip_sel)
+{
+	struct armd1ddr_registers *ddr_regs =
+		(struct armd1ddr_registers *)ARMD1_DRAM_BASE;
+	u32 result = 0;
+	u32 CS_valid = 0x01 & readl(&ddr_regs->mmap[chip_sel].cs);
+
+	if (!CS_valid)
+		return 0;
+
+	result = readl(&ddr_regs->mmap[chip_sel].cs);
+	result = (result >> 16) & 0xF;
+	if (result < 0x7) {
+		printf("Unknown DRAM Size\n");
+		return -1;
+	} else {
+		return ((0x8 << (result - 0x7)) * 1024 * 1024);
+	}
+}
+
+#ifndef CONFIG_SYS_BOARD_DRAM_INIT
+int dram_init(void)
+{
+	int i;
+
+	gd->ram_size = 0;
+	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
+		gd->bd->bi_dram[i].start = armd1_sdram_base(i);
+		gd->bd->bi_dram[i].size = armd1_sdram_size(i);
+		/*
+		 * It is assumed that all memory banks are consecutive
+		 * and without gaps.
+		 * If the gap is found, ram_size will be reported for
+		 * consecutive memory only
+		 */
+		if (gd->bd->bi_dram[i].start != gd->ram_size)
+			break;
+
+		gd->ram_size += gd->bd->bi_dram[i].size;
+
+	}
+
+	for (; i < CONFIG_NR_DRAM_BANKS; i++) {
+		/* If above loop terminated prematurely, we need to set
+		 * remaining banks' start address & size as 0. Otherwise other
+		 * u-boot functions and Linux kernel gets wrong values which
+		 * could result in crash */
+		gd->bd->bi_dram[i].start = 0;
+		gd->bd->bi_dram[i].size = 0;
+	}
+	return 0;
+}
+
+/*
+ * If this function is not defined here,
+ * board.c alters dram bank zero configuration defined above.
+ */
+void dram_init_banksize(void)
+{
+	dram_init();
+}
+#endif /* CONFIG_SYS_BOARD_DRAM_INIT */
diff --git a/arch/arm/cpu/arm926ejs/armada100/timer.c b/arch/arm/cpu/arm926ejs/armada100/timer.c
new file mode 100644
index 0000000..5d911c5
--- /dev/null
+++ b/arch/arm/cpu/arm926ejs/armada100/timer.c
@@ -0,0 +1,207 @@
+/*
+ * (C) Copyright 2010
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ * Contributor: Mahavir Jain <mjain@marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <common.h>
+#include <asm/arch/armada100.h>
+
+/*
+ * Timer registers
+ * Refer Section A.6 in Datasheet
+ */
+struct armd1tmr_registers {
+	u32 clk_ctrl;	/* Timer clk control reg */
+	u32 match[9];	/* Timer match registers */
+	u32 count[3];	/* Timer count registers */
+	u32 status[3];
+	u32 ie[3];
+	u32 preload[3];	/* Timer preload value */
+	u32 preload_ctrl[3];
+	u32 wdt_match_en;
+	u32 wdt_match_r;
+	u32 wdt_val;
+	u32 wdt_sts;
+	u32 icr[3];
+	u32 wdt_icr;
+	u32 cer;	/* Timer count enable reg */
+	u32 cmr;
+	u32 ilr[3];
+	u32 wcr;
+	u32 wfar;
+	u32 wsar;
+	u32 cvwr;
+};
+
+#define TIMER			0	/* Use TIMER 0 */
+/* Each timer has 3 match registers */
+#define MATCH_CMP(x)		((3 * TIMER) + x)
+#define TIMER_LOAD_VAL 		0xffffffff
+#define	COUNT_RD_REQ		0x1
+
+DECLARE_GLOBAL_DATA_PTR;
+/* Using gd->tbu from timestamp and gd->tbl for lastdec */
+
+/* For preventing risk of instability in reading counter value,
+ * first set read request to register cvwr and then read same
+ * register after it captures counter value.
+ */
+ulong read_timer(void)
+{
+	struct armd1tmr_registers *armd1timers =
+		(struct armd1tmr_registers *) ARMD1_TIMER_BASE;
+	volatile int loop=100;
+
+	writel(COUNT_RD_REQ, &armd1timers->cvwr);
+	while (loop--);
+	return(readl(&armd1timers->cvwr));
+}
+
+void reset_timer_masked(void)
+{
+	/* reset time */
+	gd->tbl = read_timer();
+	gd->tbu = 0;
+}
+
+ulong get_timer_masked(void)
+{
+	ulong now = read_timer();
+
+	if (now >= gd->tbl) {
+		/* normal mode */
+		gd->tbu += now - gd->tbl;
+	} else {
+		/* we have an overflow ... */
+		gd->tbu += now + TIMER_LOAD_VAL - gd->tbl;
+	}
+	gd->tbl = now;
+
+	return gd->tbu;
+}
+
+void reset_timer(void)
+{
+	reset_timer_masked();
+}
+
+ulong get_timer(ulong base)
+{
+	return ((get_timer_masked() / (CONFIG_SYS_HZ_CLOCK / 1000)) -
+		base);
+}
+
+void set_timer(ulong t)
+{
+	gd->tbu = t;
+}
+
+void __udelay(unsigned long usec)
+{
+	ulong delayticks;
+	ulong endtime;
+
+	delayticks = (usec * (CONFIG_SYS_HZ_CLOCK / 1000000));
+	endtime = get_timer_masked() + delayticks;
+
+	while (get_timer_masked() < endtime);
+}
+
+/*
+ * init the Timer
+ */
+int timer_init(void)
+{
+	struct armd1apb1_registers *apb1clkres =
+		(struct armd1apb1_registers *) ARMD1_APBC1_BASE;
+	struct armd1tmr_registers *armd1timers =
+		(struct armd1tmr_registers *) ARMD1_TIMER_BASE;
+
+	/* Enable Timer clock@3.25 MHZ */
+	writel(APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(3), &apb1clkres->timers);
+
+	/* load value into timer */
+	writel(0x0, &armd1timers->clk_ctrl);
+	/* Use Timer 0 Match Resiger 0 */
+	writel(TIMER_LOAD_VAL, &armd1timers->match[MATCH_CMP(0)]);
+	/* Preload value is 0 */
+	writel(0x0, &armd1timers->preload[TIMER]);
+	/* Enable match comparator 0 for Timer 0 */
+	writel(0x1, &armd1timers->preload_ctrl[TIMER]);
+
+	/* Enable timer 0 */
+	writel(0x1, &armd1timers->cer);
+	/* init the gd->tbu and gd->tbl value */
+	reset_timer_masked();
+
+	return 0;
+}
+
+#define MPMU_APRR_WDTR	(1<<4)
+#define TMR_WFAR	0xbaba	/* WDT Register First key */
+#define TMP_WSAR	0xeb10	/* WDT Register Second key */
+
+/*
+ * This function uses internal Watchdog Timer
+ * based reset mechanism.
+ * Steps to write watchdog registers (protected access)
+ * 1. Write key value to TMR_WFAR reg.
+ * 2. Write key value to TMP_WSAR reg.
+ * 3. Perform write operation.
+ */
+void reset_cpu (unsigned long ignored)
+{
+	struct armd1mpmu_registers *mpmu =
+		(struct armd1mpmu_registers *) ARMD1_MPMU_BASE;
+	struct armd1tmr_registers *armd1timers =
+		(struct armd1tmr_registers *) ARMD1_TIMER_BASE;
+	u32 val;
+
+	/* negate hardware reset to the WDT after system reset */
+	val = readl(&mpmu->aprr);
+	val = val | MPMU_APRR_WDTR;
+	writel(val, &mpmu->aprr);
+
+	/* reset/enable WDT clock */
+	writel(APBC_APBCLK | APBC_FNCLK | APBC_RST, &mpmu->wdtpcr);
+	readl(&mpmu->wdtpcr);
+	writel(APBC_APBCLK | APBC_FNCLK, &mpmu->wdtpcr);
+	readl(&mpmu->wdtpcr);
+
+	/* clear previous WDT status */
+	writel(TMR_WFAR, &armd1timers->wfar);
+	writel(TMP_WSAR, &armd1timers->wsar);
+	writel(0, &armd1timers->wdt_sts);
+
+	/* set match counter */
+	writel(TMR_WFAR, &armd1timers->wfar);
+	writel(TMP_WSAR, &armd1timers->wsar);
+	writel(0xf, &armd1timers->wdt_match_r);
+
+	/* enable WDT reset */
+	writel(TMR_WFAR, &armd1timers->wfar);
+	writel(TMP_WSAR, &armd1timers->wsar);
+	writel(0x3, &armd1timers->wdt_match_en);
+
+	while(1);
+}
diff --git a/arch/arm/include/asm/arch-armada100/armada100.h b/arch/arm/include/asm/arch-armada100/armada100.h
new file mode 100644
index 0000000..d5d125a
--- /dev/null
+++ b/arch/arm/include/asm/arch-armada100/armada100.h
@@ -0,0 +1,121 @@
+/*
+ * (C) Copyright 2010
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ * Contributor: Mahavir Jain <mjain@marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef _ASM_ARCH_ARMADA100_H
+#define _ASM_ARCH_ARMADA100_H
+
+#ifndef __ASSEMBLY__
+#include <asm/types.h>
+#include <asm/io.h>
+#endif	/* __ASSEMBLY__ */
+
+#if defined (CONFIG_ARMADA100)
+#include <asm/arch/cpu.h>
+
+/* Common APB clock register bit definitions */
+#define APBC_APBCLK     (1<<0)  /* APB Bus Clock Enable */
+#define APBC_FNCLK      (1<<1)  /* Functional Clock Enable */
+#define APBC_RST        (1<<2)  /* Reset Generation */
+/* Functional Clock Selection Mask */
+#define APBC_FNCLKSEL(x)        (((x) & 0xf) << 4)
+
+/* Register Base Addresses */
+#define ARMD1_DRAM_BASE		0xB0000000
+#define ARMD1_TIMER_BASE	0xD4014000
+#define ARMD1_APBC1_BASE	0xD4015000
+#define ARMD1_APBC2_BASE	0xD4015800
+#define ARMD1_UART1_BASE	0xD4017000
+#define ARMD1_UART2_BASE	0xD4018000
+#define ARMD1_GPIO_BASE		0xD4019000
+#define ARMD1_SSP1_BASE		0xD401B000
+#define ARMD1_SSP2_BASE		0xD401C000
+#define ARMD1_MFPR_BASE		0xD401E000
+#define ARMD1_SSP3_BASE		0xD401F000
+#define ARMD1_SSP4_BASE		0xD4020000
+#define ARMD1_SSP5_BASE		0xD4021000
+#define ARMD1_UART3_BASE	0xD4026000
+#define ARMD1_MPMU_BASE		0xD4050000
+#define ARMD1_APMU_BASE		0xD4282800
+#define ARMD1_CPU_BASE		0xD4282C00
+
+/*
+ * Main Power Management (MPMU) Registers
+ * Refer Datasheet Appendix A.8
+ */
+struct armd1mpmu_registers {
+	u8 pad0[0x08 - 0x00];
+	u32 fccr;	/*0x0008*/
+	u32 pocr;	/*0x000c*/
+	u32 posr;	/*0x0010*/
+	u32 succr;	/*0x0014*/
+	u8 pad1[0x030 - 0x014 - 4];
+	u32 gpcr;	/*0x0030*/
+	u8 pad2[0x200 - 0x030 - 4];
+	u32 wdtpcr;	/*0x0200*/
+	u8 pad3[0x1000 - 0x200 - 4];
+	u32 apcr;	/*0x1000*/
+	u32 apsr;	/*0x1004*/
+	u8 pad4[0x1020 - 0x1004 - 4];
+	u32 aprr;	/*0x1020*/
+	u32 acgr;	/*0x1024*/
+	u32 arsr;	/*0x1028*/
+};
+
+/*
+ * APB1 Clock Reset/Control Registers
+ * Refer Datasheet Appendix A.10
+ */
+struct armd1apb1_registers {
+	u32 uart1;	/*0x000*/
+	u32 uart2;	/*0x004*/
+	u32 gpio;	/*0x008*/
+	u32 pwm1;	/*0x00c*/
+	u32 pwm2;	/*0x010*/
+	u32 pwm3;	/*0x014*/
+	u32 pwm4;	/*0x018*/
+	u8 pad0[0x028 - 0x018 - 4];
+	u32 rtc;	/*0x028*/
+	u32 twsi0;	/*0x02c*/
+	u32 kpc;	/*0x030*/
+	u32 timers;	/*0x034*/
+	u8 pad1[0x03c - 0x034 - 4];
+	u32 aib;	/*0x03c*/
+	u32 sw_jtag;	/*0x040*/
+	u32 timer1;	/*0x044*/
+	u32 onewire;	/*0x048*/
+	u8 pad2[0x050 - 0x048 - 4];
+	u32 asfar;	/*0x050 AIB Secure First Access Reg*/
+	u32 assar;	/*0x054 AIB Secure Second Access Reg*/
+	u8 pad3[0x06c - 0x054 - 4];
+	u32 twsi1;	/*0x06c*/
+	u32 uart3;	/*0x070*/
+	u8 pad4[0x07c - 0x070 - 4];
+	u32 timer2;	/*0x07C*/
+	u8 pad5[0x084 - 0x07c - 4];
+	u32 ac97;	/*0x084*/
+};
+
+#endif /* CONFIG_ARMADA100 */
+#endif /* _ASM_ARCH_ARMADA100_H */
diff --git a/arch/arm/include/asm/arch-armada100/cpu.h b/arch/arm/include/asm/arch-armada100/cpu.h
new file mode 100644
index 0000000..0518a6a
--- /dev/null
+++ b/arch/arm/include/asm/arch-armada100/cpu.h
@@ -0,0 +1,53 @@
+/*
+ * (C) Copyright 2010
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>, Contributor: Mahavir Jain <mjain@marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef _ARMADA100CPU_H
+#define _ARMADA100CPU_H
+
+#include <asm/io.h>
+#include <asm/system.h>
+
+/*
+ * CPU Interface Registers
+ * Refer Datasheet Appendix A.2
+ */
+struct armd1cpu_registers {
+	u32 chip_id;		/* Chip Id Reg */
+	u32 pad;
+	u32 cpu_conf;		/* CPU Conf Reg */
+	u32 pad1;
+	u32 cpu_sram_spd;	/* CPU SRAM Speed Reg */
+	u32 pad2;
+	u32 cpu_l2c_spd;	/* CPU L2cache Speed Conf */
+	u32 mcb_conf;		/* MCB Conf Reg */
+	u32 sys_boot_ctl;	/* Sytem Boot Control */
+};
+
+/*
+ * Functions
+ */
+u32 armd1_sdram_base(int);
+u32 armd1_sdram_size(int);
+
+#endif /* _ARMADA100CPU_H */
-- 
1.5.3.4

^ permalink raw reply related	[flat|nested] 23+ messages in thread

* [U-Boot] [PATCH v4 2/7] gpio: Add Multi-Function-Pin configuration driver for Marvell SoCs
  2010-12-07 17:06 [U-Boot] [PATCH v4 1/7] arm: Add Support for Marvell ARMADA 100 Familiy SoCs Prafulla Wadaskar
@ 2010-12-07 17:06 ` Prafulla Wadaskar
  2010-12-07 15:23   ` Lei Wen
  2010-12-07 17:06   ` [U-Boot] [PATCH v4 3/7] add Multi Function Pin configuration support for ARMADA100 Prafulla Wadaskar
  2010-12-08  2:32 ` [U-Boot] [PATCH v4 1/7] arm: Add Support for Marvell ARMADA 100 Familiy SoCs Eric Miao
  2010-12-11 14:12 ` Prafulla Wadaskar
  2 siblings, 2 replies; 23+ messages in thread
From: Prafulla Wadaskar @ 2010-12-07 17:06 UTC (permalink / raw)
  To: u-boot

Most of the Marvell SoCs has Multi Function Pin (MFP) configuration registers
For ex. ARMADA100.

These registers are programmed to expose the specific functionality
associated with respective SoC Pins

This driver provides configuration APIs,
using them, configuration need to be done in board specific code

for ex- following code configures MFPs 107 and 108 for UART_TX/RX functionality

int board_early_init_f(void)
{
        u32 mfp_cfg[] = {
                /* Console on UART1 */
                MFP107_UART1_RXD,
                MFP108_UART1_TXD,
                MFP_EOC         /*End of configureation*/
        };
        /* configure MFP's */
        mfp_config(mfp_cfg);
        return 0;
}

Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>
---
Changelog v4:
1. Driver renamed as mvmfp
2. Re-architected mvmfp driver as per review feedback

 drivers/gpio/Makefile |    1 +
 drivers/gpio/mvmfp.c  |   90 ++++++++++++++++++++++++++++++++++++++++++++
 include/mvmfp.h       |  100 +++++++++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 191 insertions(+), 0 deletions(-)
 create mode 100644 drivers/gpio/mvmfp.c
 create mode 100644 include/mvmfp.h

diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index 398024c..a5fa2b5 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -27,6 +27,7 @@ LIB 	:= $(obj)libgpio.o
 
 COBJS-$(CONFIG_AT91_GPIO)	+= at91_gpio.o
 COBJS-$(CONFIG_KIRKWOOD_GPIO)	+= kw_gpio.o
+COBJS-$(CONFIG_MARVELL_MFP)	+= mvmfp.o
 COBJS-$(CONFIG_MXC_GPIO)	+= mxc_gpio.o
 COBJS-$(CONFIG_PCA953X)		+= pca953x.o
 COBJS-$(CONFIG_S5P)		+= s5p_gpio.o
diff --git a/drivers/gpio/mvmfp.c b/drivers/gpio/mvmfp.c
new file mode 100644
index 0000000..3472278
--- /dev/null
+++ b/drivers/gpio/mvmfp.c
@@ -0,0 +1,90 @@
+/*
+ * (C) Copyright 2010
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>,
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <mvmfp.h>
+#include <asm/arch/mfp.h>
+#ifdef CONFIG_ARMADA100
+#include <asm/arch/armada100.h>
+#define MFPR_BASE	ARMD1_MFPR_BASE
+#else
+#error Unsupported SoC...
+#endif
+
+/*
+ * mfp_config
+ *
+ * On most of Marvell SoCs (ex. ARMADA100) there is Multi-Funtion-Pin
+ * configuration registers to configure each GPIO/Function pin on the
+ * SoC.
+ *
+ * This function reads the array of values for
+ * MFPR_X registers and programms them into respective
+ * Multi-Function Pin registers.
+ * It supports - Alternate Function Selection programming.
+ *
+ * Whereas,
+ * The Configureation value is constructed using MFP()
+ * array consists of 32bit values as defined in MFP(xx,xx..) macro
+ */
+void mfp_config(u32 *mfp_cfgs)
+{
+	u32 *p_mfpr = NULL;
+	u32 cfg_val, val=0;
+
+	do {
+		cfg_val = *mfp_cfgs++;
+		/* exit if End of configuration table detected */
+		if (cfg_val == MFP_EOC)
+			break;
+
+		p_mfpr = (u32 *)(MFPR_BASE + MFP_REG_GET_OFFSET(cfg_val));
+
+		/* Write a mfg register as per configuration */
+		if (cfg_val & MFP_AF_FLAG) {
+			/* Abstract and program Afternate-Func Selection */
+			val &= ~MFP_AF_MASK;
+			val |= cfg_val & MFP_AF_MASK;
+		} if (cfg_val & MFP_EDGE_FLAG) {
+			/* Abstract and program Edge configuration */
+			val &= ~MFP_LPM_EDGE_MASK;
+			val |= cfg_val & MFP_LPM_EDGE_MASK;
+		} if (cfg_val & MFP_DRIVE_FLAG) {
+			/* Abstract and program Drive configuration */
+			val &= ~MFP_DRIVE_MASK;
+			val |= cfg_val & MFP_DRIVE_MASK;
+		} if (cfg_val & MFP_PULL_FLAG) {
+			/* Abstract and program Pullup/down configuration */
+			val &= ~MFP_PULL_MASK;
+			val |= cfg_val & MFP_PULL_MASK;
+		}
+		writel(val, p_mfpr);
+	} while (1);
+	/*
+	 * perform a read-back of any MFPR register to make sure the
+	 * previous writings are finished
+	 */
+	readl(p_mfpr);
+}
diff --git a/include/mvmfp.h b/include/mvmfp.h
new file mode 100644
index 0000000..0b36393
--- /dev/null
+++ b/include/mvmfp.h
@@ -0,0 +1,100 @@
+/*
+ * (C) Copyright 2010
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef __MVMFP_H
+#define __MVMFP_H
+
+/*
+ * Header file for MultiFunctionPin (MFP) Configururation framework
+ *
+ * Processors Supported:
+ * 1. Marvell ARMADA100 Processors
+ *
+ * processor to be supported should be added here
+ */
+
+/*
+ * MFP configuration is represented by a 32-bit unsigned integer
+ */
+#define MFP(_off, _pull, _pF, _drv, _dF, _edge, _eF, _afn, _aF) ( \
+	/* bits 31..16 - MFP Register Offset */	(((_off) & 0xffff) << 16) | \
+	/* bits 15..13 - Run Mode Pull State */	(((_pull) & 0x7) << 13) | \
+	/* bit  12     - Unused */ \
+	/* bits 11..10 - Driver Strength */	(((_drv) & 0x3) << 10) | \
+	/* bit  09     - Pull State flag */	(((_pF) & 0x1) << 9) | \
+	/* bit  08     - Drv-strength flag */	(((_dF) & 0x1) << 8) | \
+	/* bit  07     - Edge-det flag */	(((_eF) & 0x1) << 7) | \
+	/* bits 06..04 - Edge Detection */	(((_edge) & 0x7) << 4) | \
+	/* bits 03..00 - Alt-fun flag */	(((_aF) & 0x1) << 3) | \
+	/* bits Alternate-fun select */		((_afn) & 0x7))
+
+/*
+ * to facilitate the definition, the following macros are provided
+ *
+ * 				    offset, pull,pF, drv,dF, edge,eF ,afn,aF
+ */
+#define MFP_OFFSET_MASK		MFP(0xffff,    0,0,    0,0,     0,0,   0,0)
+#define MFP_REG(x)		MFP(x,         0,0,    0,0,     0,0,   0,0)
+#define MFP_REG_GET_OFFSET(x)	((x & MFP_OFFSET_MASK) >> 16)
+
+#define MFP_AF_FLAG		MFP(0x0000,    0,0,    0,0,     0,0,   0,1)
+#define MFP_DRIVE_FLAG		MFP(0x0000,    0,0,    0,1,     0,0,   0,0)
+#define MFP_EDGE_FLAG		MFP(0x0000,    0,0,    0,0,     0,1,   0,0)
+#define MFP_PULL_FLAG		MFP(0x0000,    0,1,    0,0,     0,0,   0,0)
+
+#define MFP_AF0			MFP(0x0000,    0,0,    0,0,     0,0,   0,1)
+#define MFP_AF1			MFP(0x0000,    0,0,    0,0,     0,0,   1,1)
+#define MFP_AF2			MFP(0x0000,    0,0,    0,0,     0,0,   2,1)
+#define MFP_AF3			MFP(0x0000,    0,0,    0,0,     0,0,   3,1)
+#define MFP_AF4			MFP(0x0000,    0,0,    0,0,     0,0,   4,1)
+#define MFP_AF5			MFP(0x0000,    0,0,    0,0,     0,0,   5,1)
+#define MFP_AF6			MFP(0x0000,    0,0,    0,0,     0,0,   6,1)
+#define MFP_AF7			MFP(0x0000,    0,0,    0,0,     0,0,   7,1)
+#define MFP_AF_MASK		MFP(0x0000,    0,0,    0,0,     0,0,   7,0)
+
+#define MFP_LPM_EDGE_NONE	MFP(0x0000,    0,0,    0,0,     0,1,   0,0)
+#define MFP_LPM_EDGE_RISE	MFP(0x0000,    0,0,    0,0,     1,1,   0,0)
+#define MFP_LPM_EDGE_FALL	MFP(0x0000,    0,0,    0,0,     2,1,   0,0)
+#define MFP_LPM_EDGE_BOTH	MFP(0x0000,    0,0,    0,0,     3,1,   0,0)
+#define MFP_LPM_EDGE_MASK	MFP(0x0000,    0,0,    0,0,     3,0,   0,0)
+
+#define MFP_DRIVE_VERY_SLOW	MFP(0x0000,    0,0,    0,1,     0,0,   0,0)
+#define MFP_DRIVE_SLOW		MFP(0x0000,    0,0,    1,1,     0,0,   0,0)
+#define MFP_DRIVE_MEDIUM	MFP(0x0000,    0,0,    2,1,     0,0,   0,0)
+#define MFP_DRIVE_FAST		MFP(0x0000,    0,0,    3,1,     0,0,   0,0)
+#define MFP_DRIVE_MASK		MFP(0x0000,    0,0,    3,0,     0,0,   0,0)
+
+#define MFP_PULL_NONE		MFP(0x0000,    0,1,    0,0,     0,0,   0,0)
+#define MFP_PULL_LOW		MFP(0x0000,    1,1,    0,0,     0,0,   0,0)
+#define MFP_PULL_HIGH		MFP(0x0000,    2,1,    0,0,     0,0,   0,0)
+#define MFP_PULL_BOTH		MFP(0x0000,    3,1,    0,0,     0,0,   0,0)
+#define MFP_PULL_FLOAT		MFP(0x0000,    4,1,    0,0,     0,0,   0,0)
+#define MFP_PULL_MASK		MFP(0x0000,    7,0,    0,0,     0,0,   0,0)
+
+#define MFP_EOC			0xffffffff	/* indicates end-of-conf */
+
+/* Functions */
+void mfp_config(u32 *mfp_cfgs);
+
+#endif /* __MVMFP_H */
-- 
1.5.3.4

^ permalink raw reply related	[flat|nested] 23+ messages in thread

* [U-Boot] [PATCH v4 3/7] add Multi Function Pin configuration support for ARMADA100
  2010-12-07 17:06 ` [U-Boot] [PATCH v4 2/7] gpio: Add Multi-Function-Pin configuration driver for Marvell SoCs Prafulla Wadaskar
  2010-12-07 15:23   ` Lei Wen
@ 2010-12-07 17:06   ` Prafulla Wadaskar
  2010-12-07 17:06     ` [U-Boot] [PATCH v4 4/7] Serial: ns16550: Add support for CONFIG_SYS_NS16550_IER macro Prafulla Wadaskar
  2010-12-11 14:13     ` [U-Boot] [PATCH v4 3/7] add Multi Function Pin configuration support for ARMADA100 Prafulla Wadaskar
  1 sibling, 2 replies; 23+ messages in thread
From: Prafulla Wadaskar @ 2010-12-07 17:06 UTC (permalink / raw)
  To: u-boot

This patch adds the support MFP support for Marvell ARMADA100 SoCs

Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>
---
Changelog v4:
macros redefined as per new mvmfp driver architecture

 arch/arm/include/asm/arch-armada100/mfp.h |   67 +++++++++++++++++++++++++++++
 1 files changed, 67 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/include/asm/arch-armada100/mfp.h

diff --git a/arch/arm/include/asm/arch-armada100/mfp.h b/arch/arm/include/asm/arch-armada100/mfp.h
new file mode 100644
index 0000000..d21a79f
--- /dev/null
+++ b/arch/arm/include/asm/arch-armada100/mfp.h
@@ -0,0 +1,67 @@
+/*
+ * Based on linux/arch/arm/mach-mpp/include/mfp-pxa168.h
+ * (C) Copyright 2007
+ * Marvell Semiconductor <www.marvell.com>
+ * 2007-08-21: eric miao <eric.miao@marvell.com>
+ *
+ * (C) Copyright 2010
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ * Contributor: Mahavir Jain <mjain@marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef __ARMADA100_MFP_H
+#define __ARMADA100_MFP_H
+
+/*
+ * Frequently used MFP Configuration macros for all ARMADA100 family of SoCs
+ *
+ * 				    offset, pull,pF, drv,dF, edge,eF ,afn,aF
+ */
+/* UART1 */
+#define MFP107_UART1_TXD	MFP_REG(0x01ac) | MFP_AF1 | MFP_DRIVE_FAST
+#define MFP107_UART1_RXD	MFP_REG(0x01ac) | MFP_AF2 | MFP_DRIVE_FAST
+#define MFP108_UART1_RXD	MFP_REG(0x01b0) | MFP_AF1 | MFP_DRIVE_FAST
+#define MFP108_UART1_TXD	MFP_REG(0x01b0) | MFP_AF2 | MFP_DRIVE_FAST
+#define MFP109_UART1_CTS	MFP_REG(0x01b4) | MFP_AF1 | MFP_DRIVE_MEDIUM
+#define MFP109_UART1_RTS	MFP_REG(0x01b4) | MFP_AF2 | MFP_DRIVE_MEDIUM
+#define MFP110_UART1_RTS	MFP_REG(0x01b8) | MFP_AF1 | MFP_DRIVE_MEDIUM
+#define MFP110_UART1_CTS	MFP_REG(0x01b8) | MFP_AF2 | MFP_DRIVE_MEDIUM
+#define MFP111_UART1_RI		MFP_REG(0x01bc) | MFP_AF1 | MFP_DRIVE_MEDIUM
+#define MFP111_UART1_DSR	MFP_REG(0x01bc) | MFP_AF2 | MFP_DRIVE_MEDIUM
+#define MFP112_UART1_DTR	MFP_REG(0x01c0) | MFP_AF1 | MFP_DRIVE_MEDIUM
+#define MFP112_UART1_DCD	MFP_REG(0x01c0) | MFP_AF2 | MFP_DRIVE_MEDIUM
+
+/* UART2 */
+#define MFP47_UART2_RXD		MFP_REG(0x0028) | MFP_AF6 | MFP_DRIVE_MEDIUM
+#define MFP48_UART2_TXD		MFP_REG(0x002c) | MFP_AF6 | MFP_DRIVE_MEDIUM
+#define MFP88_UART2_RXD		MFP_REG(0x0160) | MFP_AF2 | MFP_DRIVE_MEDIUM
+#define MFP89_UART2_TXD		MFP_REG(0x0164) | MFP_AF2 | MFP_DRIVE_MEDIUM
+
+/* UART3 */
+#define MFPO8_UART3_RXD		MFP_REG(0x06c) | MFP_AF2 | MFP_DRIVE_MEDIUM
+#define MFPO9_UART3_TXD		MFP_REG(0x070) | MFP_AF2 | MFP_DRIVE_MEDIUM
+
+/* More macros can be defined here... */
+
+#define MFP_PIN_MAX	117
+
+#endif /* __ARMADA100_MFP_H */
-- 
1.5.3.4

^ permalink raw reply related	[flat|nested] 23+ messages in thread

* [U-Boot] [PATCH v4 4/7] Serial: ns16550: Add support for CONFIG_SYS_NS16550_IER macro
  2010-12-07 17:06   ` [U-Boot] [PATCH v4 3/7] add Multi Function Pin configuration support for ARMADA100 Prafulla Wadaskar
@ 2010-12-07 17:06     ` Prafulla Wadaskar
  2010-12-07 17:06       ` [U-Boot] [PATCH v4 5/7] Serial: Add UART support for Marvell ARMADA 100 SoCs Prafulla Wadaskar
  2010-12-11 14:13       ` [U-Boot] [PATCH v4 4/7] Serial: ns16550: Add support for CONFIG_SYS_NS16550_IER macro Prafulla Wadaskar
  2010-12-11 14:13     ` [U-Boot] [PATCH v4 3/7] add Multi Function Pin configuration support for ARMADA100 Prafulla Wadaskar
  1 sibling, 2 replies; 23+ messages in thread
From: Prafulla Wadaskar @ 2010-12-07 17:06 UTC (permalink / raw)
  To: u-boot

On some processors this ier register configuration is different
for ex. Marvell Armada100

This patch introduce CONFIG_SYS_NS16550_IER macro support to
unconditionally initialize this register.

Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>
---
Changelog v3:
macro defination CONFIG_SYS_NS16550_IER moved from ns16550.h to ns16550.c

 drivers/serial/ns16550.c |    8 ++++++--
 1 files changed, 6 insertions(+), 2 deletions(-)

diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c
index 32f24de..8eeb48f 100644
--- a/drivers/serial/ns16550.c
+++ b/drivers/serial/ns16550.c
@@ -24,9 +24,13 @@
 #define serial_in(y) 	readb(y)
 #endif
 
+#ifndef CONFIG_SYS_NS16550_IER
+#define CONFIG_SYS_NS16550_IER  0x00
+#endif /* CONFIG_SYS_NS16550_IER */
+
 void NS16550_init (NS16550_t com_port, int baud_divisor)
 {
-	serial_out(0x00, &com_port->ier);
+	serial_out(CONFIG_SYS_NS16550_IER, &com_port->ier);
 #if defined(CONFIG_OMAP) && !defined(CONFIG_OMAP3_ZOOM2)
 	serial_out(0x7, &com_port->mdr1);	/* mode select reset TL16C750*/
 #endif
@@ -52,7 +56,7 @@ void NS16550_init (NS16550_t com_port, int baud_divisor)
 #ifndef CONFIG_NS16550_MIN_FUNCTIONS
 void NS16550_reinit (NS16550_t com_port, int baud_divisor)
 {
-	serial_out(0x00, &com_port->ier);
+	serial_out(CONFIG_SYS_NS16550_IER, &com_port->ier);
 	serial_out(UART_LCR_BKSE | UART_LCRVAL, &com_port->lcr);
 	serial_out(0, &com_port->dll);
 	serial_out(0, &com_port->dlm);
-- 
1.5.3.4

^ permalink raw reply related	[flat|nested] 23+ messages in thread

* [U-Boot] [PATCH v4 5/7] Serial: Add UART support for Marvell ARMADA 100 SoCs.
  2010-12-07 17:06     ` [U-Boot] [PATCH v4 4/7] Serial: ns16550: Add support for CONFIG_SYS_NS16550_IER macro Prafulla Wadaskar
@ 2010-12-07 17:06       ` Prafulla Wadaskar
  2010-12-07 17:06         ` [U-Boot] [PATCH v4 6/7] mv-common.h: Add support for ARMADA100 Platforms Prafulla Wadaskar
  2010-12-11 14:13         ` [U-Boot] [PATCH v4 5/7] Serial: Add UART support for Marvell ARMADA 100 SoCs Prafulla Wadaskar
  2010-12-11 14:13       ` [U-Boot] [PATCH v4 4/7] Serial: ns16550: Add support for CONFIG_SYS_NS16550_IER macro Prafulla Wadaskar
  1 sibling, 2 replies; 23+ messages in thread
From: Prafulla Wadaskar @ 2010-12-07 17:06 UTC (permalink / raw)
  To: u-boot

ARMADA 100 SoCs has NS16550 compatible UART peripheral
This patch enables the same for ARMADA100 platforms

Signed-off-by: Mahavir Jain <mjain@marvell.com>
Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>
---
Change log for v2:
defined CONFIG_SYS_NS16550_IER macro in Soc heder file
Change log for v3:
Removed reordiring of header files, the diff is only
limited to include armada100.h

 drivers/serial/serial.c |    5 +++--
 1 files changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/serial/serial.c b/drivers/serial/serial.c
index 1073ac0..cd3439e 100644
--- a/drivers/serial/serial.c
+++ b/drivers/serial/serial.c
@@ -29,9 +29,10 @@
 #endif
 #ifdef CONFIG_KIRKWOOD
 #include <asm/arch/kirkwood.h>
-#endif
-#ifdef CONFIG_ORION5X
+#elif defined(CONFIG_ORION5X)
 #include <asm/arch/orion5x.h>
+#elif defined(CONFIG_ARMADA100)
+#include <asm/arch/armada100.h>
 #endif
 
 #if defined (CONFIG_SERIAL_MULTI)
-- 
1.5.3.4

^ permalink raw reply related	[flat|nested] 23+ messages in thread

* [U-Boot] [PATCH v4 6/7] mv-common.h: Add support for ARMADA100 Platforms
  2010-12-07 17:06       ` [U-Boot] [PATCH v4 5/7] Serial: Add UART support for Marvell ARMADA 100 SoCs Prafulla Wadaskar
@ 2010-12-07 17:06         ` Prafulla Wadaskar
  2010-12-07 15:32           ` Lei Wen
  2010-12-07 17:06           ` [U-Boot] [PATCH v4 7/7] Armada100: Add Board Support for Marvell Aspenite-DB Prafulla Wadaskar
  2010-12-11 14:13         ` [U-Boot] [PATCH v4 5/7] Serial: Add UART support for Marvell ARMADA 100 SoCs Prafulla Wadaskar
  1 sibling, 2 replies; 23+ messages in thread
From: Prafulla Wadaskar @ 2010-12-07 17:06 UTC (permalink / raw)
  To: u-boot

This patch adds commonly used macros for ARMADA100 based
baords, Also some code reshuffled and updated for typos and comments

Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>
---
Changelog v3:
CONFIG_ARCH_CPU_INIT moved out of #ifdef

Changelog v4:
CONFIG_MFP change to CONFIG_MARVELL_MFP
some whitespaces removed

 include/configs/mv-common.h |   65 ++++++++++++++++++++++++++++++++----------
 1 files changed, 49 insertions(+), 16 deletions(-)

diff --git a/include/configs/mv-common.h b/include/configs/mv-common.h
index 0a76163..067527a 100644
--- a/include/configs/mv-common.h
+++ b/include/configs/mv-common.h
@@ -39,6 +39,7 @@
 #define CONFIG_MARVELL		1
 #define CONFIG_ARM926EJS	1	/* Basic Architecture */
 
+/* ====> Kirkwood Platform Common Definations */
 #if defined(CONFIG_KIRKWOOD)
 #define CONFIG_MD5	/* get_random_hex on krikwood needs MD5 support */
 #define CONFIG_KIRKWOOD_EGIGA_INIT	/* Enable GbePort0/1 for kernel */
@@ -54,27 +55,45 @@
 #define	CONFIG_SYS_KWD_CONFIG	$(SRCTREE)/$(CONFIG_BOARDDIR)/kwbimage.cfg
 #endif /* CONFIG_SYS_KWD_CONFIG */
 
-/*
- * CONFIG_SYS_TEXT_BASE can be defined in board specific header file, if needed
- */
-#ifndef CONFIG_SYS_TEXT_BASE
-#define	CONFIG_SYS_TEXT_BASE	0x00600000
-#endif /* CONFIG_SYS_TEXT_BASE */
+/* Kirkwood has 2k of Security SRAM, use it for SP */
+#define CONFIG_SYS_INIT_SP_ADDR		0xC8012000
+#define CONFIG_NR_DRAM_BANKS_MAX	2
 
 #define CONFIG_I2C_MVTWSI_BASE	KW_TWSI_BASE
-#define MV_UART0_BASE		KW_UART0_BASE
+#define MV_UART_CONSOLE_BASE	KW_UART0_BASE
 #define MV_SATA_BASE		KW_SATA_BASE
 #define MV_SATA_PORT0_OFFSET	KW_SATA_PORT0_OFFSET
 #define MV_SATA_PORT1_OFFSET	KW_SATA_PORT1_OFFSET
 
+/* ====> ARMADA100 Platform Common Definations */
+#elif defined (CONFIG_ARMADA100)
+
+#define CONFIG_SYS_TCLK		(14745600)	/* NS16550 clk config */
+#define CONFIG_SYS_HZ_CLOCK	(3250000)	/* Timer Freq. 3.25MHZ */
+#define CONFIG_MARVELL_MFP			/* Enable mvmfp driver */
+#define MV_UART_CONSOLE_BASE	ARMD1_UART1_BASE
+#define CONFIG_SYS_NS16550_IER	(1 << 6)	/* Bit 6 in UART_IER register
+						represents UART Unit Enable */
+/*
+ * There is no internal RAM in ARMADA100, using DRAM
+ * TBD: dcache to be used for this
+ */
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_TEXT_BASE - 0x00200000)
+#define CONFIG_NR_DRAM_BANKS_MAX	2
+
 #else
-#error "Unsupported SoC"
+#error "Unsupported SoC Platform..."
 #endif
 
+/*
+ * Custom CONFIG_SYS_TEXT_BASE can be done in <board>.h
+ */
+#ifndef CONFIG_SYS_TEXT_BASE
+#define	CONFIG_SYS_TEXT_BASE	0x00600000
+#endif /* CONFIG_SYS_TEXT_BASE */
+
 /* additions for new ARM relocation support */
-#define CONFIG_SYS_SDRAM_BASE		0x00000000
-/* Kirkwood has 2k of Security SRAM, use it for SP */
-#define CONFIG_SYS_INIT_SP_ADDR		0xC8012000
+#define CONFIG_SYS_SDRAM_BASE	0x00000000
 
 /*
  * CLKs configurations
@@ -88,7 +107,7 @@
 #define CONFIG_SYS_NS16550_SERIAL
 #define CONFIG_SYS_NS16550_REG_SIZE	(-4)
 #define CONFIG_SYS_NS16550_CLK		CONFIG_SYS_TCLK
-#define CONFIG_SYS_NS16550_COM1		MV_UART0_BASE
+#define CONFIG_SYS_NS16550_COM1		MV_UART_CONSOLE_BASE
 
 /*
  * Serial Port configuration
@@ -156,25 +175,37 @@
 #define CONFIG_CMDLINE_EDITING
 #define CONFIG_CONSOLE_INFO_QUIET	/* some code reduction */
 #define CONFIG_ARCH_CPU_INIT	/* call arch_cpu_init() */
+#ifndef CONFIG_ARMADA100	/* will be removed latter */
 #define CONFIG_ARCH_MISC_INIT	/* call arch_misc_init() */
+#endif /* CONFIG_ARMADA100 */
 #define CONFIG_BOARD_EARLY_INIT_F /* call board_init_f for early inits */
 #define CONFIG_DISPLAY_CPUINFO	/* Display cpu info */
-#define CONFIG_NR_DRAM_BANKS	4
 #define CONFIG_STACKSIZE	0x00100000	/* regular stack- 1M */
 #define CONFIG_SYS_LOAD_ADDR	0x00800000	/* default load adr- 8M */
-#define CONFIG_SYS_MEMTEST_START 0x00400000	/* 4M */
-#define CONFIG_SYS_MEMTEST_END	0x007fffff	/*(_8M -1) */
+#define CONFIG_SYS_MEMTEST_START 0x00800000	/* 8M */
+#define CONFIG_SYS_MEMTEST_END	0x00ffffff	/*(_16M -1) */
 #define CONFIG_SYS_RESET_ADDRESS 0xffff0000	/* Rst Vector Adr */
 #define CONFIG_SYS_MAXARGS	16	/* max number of command args */
 
 /*
+ * DRAM Banks configuration, Custom config can be done in <board>.h
+ */
+#ifndef CONFIG_NR_DRAM_BANKS
+#define CONFIG_NR_DRAM_BANKS	CONFIG_NR_DRAM_BANKS_MAX
+#else
+#if (CONFIG_NR_DRAM_BANKS > CONFIG_NR_DRAM_BANKS_MAX)
+#error CONFIG_NR_DRAM_BANKS Configurated more than available
+#endif
+#endif /* CONFIG_NR_DRAM_BANKS */
+
+/*
  * Ethernet Driver configuration
  */
 #ifdef CONFIG_CMD_NET
 #define CONFIG_CMD_MII
 #define CONFIG_NETCONSOLE	/* include NetConsole support   */
 #define CONFIG_NET_MULTI	/* specify more that one ports available */
-#define	CONFIG_MII		/* expose smi ove miiphy interface */
+#define CONFIG_MII		/* expose smi ove miiphy interface */
 #define CONFIG_MVGBE		/* Enable Marvell Gbe Controller Driver */
 #define CONFIG_SYS_FAULT_ECHO_LINK_DOWN	/* detect link using phy */
 #define CONFIG_ENV_OVERWRITE	/* ethaddr can be reprogrammed */
@@ -232,6 +263,7 @@
 /*
  * File system
  */
+#ifndef CONFIG_ARMADA100	/* will be removed latter */
 #define CONFIG_CMD_EXT2
 #define CONFIG_CMD_JFFS2
 #define CONFIG_CMD_FAT
@@ -242,5 +274,6 @@
 #define CONFIG_MTD_PARTITIONS
 #define CONFIG_CMD_MTDPARTS
 #define CONFIG_LZO
+#endif /* CONFIG_ARMADA100 */
 
 #endif /* _MV_COMMON_H */
-- 
1.5.3.4

^ permalink raw reply related	[flat|nested] 23+ messages in thread

* [U-Boot] [PATCH v4 7/7] Armada100: Add Board Support for Marvell Aspenite-DB
  2010-12-07 17:06         ` [U-Boot] [PATCH v4 6/7] mv-common.h: Add support for ARMADA100 Platforms Prafulla Wadaskar
  2010-12-07 15:32           ` Lei Wen
@ 2010-12-07 17:06           ` Prafulla Wadaskar
  2010-12-07 17:06             ` [U-Boot] [PATCH v4 0/7] Add Marvell New Soc Support ARMADA100 Prafulla Wadaskar
  2010-12-11 14:14             ` [U-Boot] [PATCH v4 7/7] Armada100: Add Board Support for Marvell Aspenite-DB Prafulla Wadaskar
  1 sibling, 2 replies; 23+ messages in thread
From: Prafulla Wadaskar @ 2010-12-07 17:06 UTC (permalink / raw)
  To: u-boot

Aspenite is a Development Board for ASPEN/ARMADA168(88AP168) with
	* Processor upto 1.2GHz
        * Parallel 1Gb x8 DDR2-1066 MHz
        * 16 Mb x16 NOR, 4Gb x8 SLC NAND, footprint for SPI NOR
        * Footprints for eMMC/eSD NAND & MMC x8 card
        * 4-in-1 card reader (xD, MMC/SD/MS Pro), CF True IDE socket
        * SEAF memory board, subset of PISMO2
    With Peripherals:
        * 4.3? WVGA 24-bit LCD
        * Audio codecs (AC97 & I2S), TSI
        * VGA camera
        * Video in via 3 RCA jacks, and HDMI type C out
        * Marvell 88W8688 802.11bg/BT module
        * GPS RF IC
        * Dual analog mics & speakers, headset jack, LED, ambient light sensor
        * USB2.0 HS host  (A), OTG (micro AB)
        * FE PHY, PCIE Mini Card  slot
        * GPIO, GPIO expander with DIP switches for easier selection UART serial over USB, CIR

This patch adds basic board support with DRAM and UART functionality
The patch is tested for boot from DRAM using XDB

Signed-off-by: Mahavir Jain <mjain@marvell.com>
Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>
---
Change log for v2:
used mv-common.h
defined CONFIG_SYS_NS16550_IER macro in Soc heder file
removed config.mk

Change log for v3:
DEBUG removed from aspenite.h

Change log for v4:
name changes as per mvmfp

 MAINTAINERS                       |    1 +
 MAKEALL                           |    1 +
 board/Marvell/aspenite/Makefile   |   52 ++++++++++++++++++++++++++++++
 board/Marvell/aspenite/aspenite.c |   53 +++++++++++++++++++++++++++++++
 boards.cfg                        |    1 +
 include/configs/aspenite.h        |   63 +++++++++++++++++++++++++++++++++++++
 6 files changed, 171 insertions(+), 0 deletions(-)
 create mode 100644 board/Marvell/aspenite/Makefile
 create mode 100644 board/Marvell/aspenite/aspenite.c
 create mode 100644 include/configs/aspenite.h

diff --git a/MAINTAINERS b/MAINTAINERS
index f47fca5..d7e47a6 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -836,6 +836,7 @@ Matt Waddel <matt.waddel@linaro.org>
 
 Prafulla Wadaskar <prafulla@marvell.com>
 
+	aspenite	ARM926EJS (ARMADA100 88AP168 SoC)
 	mv88f6281gtw_ge	ARM926EJS (Kirkwood SoC)
 	rd6281a		ARM926EJS (Kirkwood SoC)
 	sheevaplug	ARM926EJS (Kirkwood SoC)
diff --git a/MAKEALL b/MAKEALL
index 767d561..e83c9d7 100755
--- a/MAKEALL
+++ b/MAKEALL
@@ -326,6 +326,7 @@ LIST_ARM9="			\
 	ap926ejs		\
 	ap946es			\
 	ap966			\
+	aspenite		\
 	cp920t			\
 	cp922_XA10		\
 	cp926ejs		\
diff --git a/board/Marvell/aspenite/Makefile b/board/Marvell/aspenite/Makefile
new file mode 100644
index 0000000..cb1b65f
--- /dev/null
+++ b/board/Marvell/aspenite/Makefile
@@ -0,0 +1,52 @@
+#
+# (C) Copyright 2010
+# Marvell Semiconductor <www.marvell.com>
+# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+# Contributor: Mahavir Jain <mjain@marvell.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+# MA 02110-1301 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB     = $(obj)lib$(BOARD).o
+
+COBJS	:= aspenite.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/Marvell/aspenite/aspenite.c b/board/Marvell/aspenite/aspenite.c
new file mode 100644
index 0000000..046ffd6
--- /dev/null
+++ b/board/Marvell/aspenite/aspenite.c
@@ -0,0 +1,53 @@
+/*
+ * (C) Copyright 2010
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ * Contributor: Mahavir Jain <mjain@marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <common.h>
+#include <mvmfp.h>
+#include <asm/arch/mfp.h>
+#include <asm/arch/armada100.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_early_init_f(void)
+{
+	u32 mfp_cfg[] = {
+		/* Enable Console on UART1 */
+		MFP107_UART1_RXD,
+		MFP108_UART1_TXD,
+		MFP_EOC		/*End of configureation*/
+	};
+	/* configure MFP's */
+	mfp_config(mfp_cfg);
+	return 0;
+}
+
+int board_init(void)
+{
+	/* arch number of Board */
+	gd->bd->bi_arch_number = MACH_TYPE_ASPENITE;
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = armd1_sdram_base(0) + 0x100;
+	return 0;
+}
diff --git a/boards.cfg b/boards.cfg
index 2209676..34cc6db 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -68,6 +68,7 @@ smdk2410                     arm         arm920t     -                   samsung
 netstar                      arm         arm925t
 voiceblue                    arm         arm925t
 omap1510inn                  arm         arm925t     -                   ti
+aspenite                     arm         arm926ejs   -                   Marvell        armada100
 afeb9260                     arm         arm926ejs   -                   -              at91
 at91cap9adk                  arm         arm926ejs   -                   atmel          at91
 meesc                        arm         arm926ejs   -                   esd            at91
diff --git a/include/configs/aspenite.h b/include/configs/aspenite.h
new file mode 100644
index 0000000..706365f
--- /dev/null
+++ b/include/configs/aspenite.h
@@ -0,0 +1,63 @@
+/*
+ * (C) Copyright 2010
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ * Contributor: Mahavir Jain <mjain@marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef __CONFIG_ASPENITE_H
+#define __CONFIG_ASPENITE_H
+
+/*
+ * Version number information
+ */
+#define CONFIG_IDENT_STRING	"\nMarvell-Aspenite DB"
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_SHEEVA_88SV331xV5	1	/* CPU Core subversion */
+#define CONFIG_ARMADA100		1	/* SOC Family Name */
+#define CONFIG_ARMADA168		1	/* SOC Used on this Board */
+#define CONFIG_MACH_ASPENITE			/* Machine type */
+#define CONFIG_SKIP_LOWLEVEL_INIT	/* disable board lowlevel_init */
+
+/*
+ * Commands configuration
+ */
+#define CONFIG_SYS_NO_FLASH		/* Declare no flash (NOR/SPI) */
+#include <config_cmd_default.h>
+#define CONFIG_CMD_AUTOSCRIPT
+#undef CONFIG_CMD_NET
+#undef CONFIG_CMD_NFS
+/*
+ * mv-common.h should be defined after CMD configs since it used them
+ * to enable certain macros
+ */
+#include "mv-common.h"
+
+/*
+ * Environment variables configurations
+ */
+#define CONFIG_ENV_IS_NOWHERE	1	/* if env in SDRAM */
+#define CONFIG_ENV_SIZE	0x20000	/* 64k */
+
+#endif	/* __CONFIG_ASPENITE_H */
-- 
1.5.3.4

^ permalink raw reply related	[flat|nested] 23+ messages in thread

* [U-Boot] [PATCH v4 0/7] Add Marvell New Soc Support ARMADA100
  2010-12-07 17:06           ` [U-Boot] [PATCH v4 7/7] Armada100: Add Board Support for Marvell Aspenite-DB Prafulla Wadaskar
@ 2010-12-07 17:06             ` Prafulla Wadaskar
  2010-12-11 14:14             ` [U-Boot] [PATCH v4 7/7] Armada100: Add Board Support for Marvell Aspenite-DB Prafulla Wadaskar
  1 sibling, 0 replies; 23+ messages in thread
From: Prafulla Wadaskar @ 2010-12-07 17:06 UTC (permalink / raw)
  To: u-boot

This patch series adds basic ARMADA100 support, with minimal drivers
(UART, MFP) support and Aspenite-DB board support for simple boot

Changelog v2:
1. This patch series is in sync latest u-boot
2. config.mk removed
3. CONFIG_SYS_NS16550_IER used for serial drivers
4. mv-common.h updated for aspenite support
5. c-struct used for dram.c
6. All review feedback for v1 implemented

Changelog v3:
1. timer.c: timer variables in gt_t used insted of locally defined global variables
2. timer.c: register global pointer moved to respective functions
3. timer.c: Macro READ_TIMER converted to function read_timer()
4. armada100.h: c-struc in armada100.h fixed for wrong padding
5. macro defination CONFIG_SYS_NS16550_IER moved from ns16550.h to ns16550.c
6. Removed reordiring of header files in serial.c, the diff is only limited
   to include armada100.h
7. mv-common.h: CONFIG_ARCH_CPU_INIT moved out of #ifdef
8. aspenite.h: #define DEBUG removed

Changelog v4:
1. mfp driver renamed as mvmfp
2. re-architected mvmfp driver as per review feedback

These patches are tested on board
Fo sucessfull build, these patches are dependent upon a patch.
 "ARM: make timer variables in gt_t available for all ARM platforms"
  ref: http://lists.denx.de/pipermail/u-boot/2010-December/082834.html

Regards..
Prafulla . .

Prafulla Wadaskar (7):
  arm: Add Support for Marvell ARMADA 100 Familiy SoCs
  gpio: Add Multi-Function-Pin configuration driver for Marvell SoCs
  add Multi Function Pin configuration support for ARMADA100
  Serial: ns16550: Add support for CONFIG_SYS_NS16550_IER macro
  Serial: Add UART support for Marvell ARMADA 100 SoCs.
  mv-common.h: Add support for ARMADA100 Platforms
  Armada100: Add Board Support for Marvell Aspenite-DB

 MAINTAINERS                                     |    1 +
 MAKEALL                                         |    1 +
 arch/arm/cpu/arm926ejs/armada100/Makefile       |   46 +++++
 arch/arm/cpu/arm926ejs/armada100/cpu.c          |   92 ++++++++++
 arch/arm/cpu/arm926ejs/armada100/dram.c         |  131 ++++++++++++++
 arch/arm/cpu/arm926ejs/armada100/timer.c        |  207 +++++++++++++++++++++++
 arch/arm/include/asm/arch-armada100/armada100.h |  121 +++++++++++++
 arch/arm/include/asm/arch-armada100/cpu.h       |   53 ++++++
 arch/arm/include/asm/arch-armada100/mfp.h       |   67 ++++++++
 board/Marvell/aspenite/Makefile                 |   52 ++++++
 board/Marvell/aspenite/aspenite.c               |   53 ++++++
 boards.cfg                                      |    1 +
 drivers/gpio/Makefile                           |    1 +
 drivers/gpio/mvmfp.c                            |   90 ++++++++++
 drivers/serial/ns16550.c                        |    8 +-
 drivers/serial/serial.c                         |    5 +-
 include/configs/aspenite.h                      |   63 +++++++
 include/configs/mv-common.h                     |   65 ++++++--
 include/mvmfp.h                                 |  100 +++++++++++
 19 files changed, 1137 insertions(+), 20 deletions(-)
 create mode 100644 arch/arm/cpu/arm926ejs/armada100/Makefile
 create mode 100644 arch/arm/cpu/arm926ejs/armada100/cpu.c
 create mode 100644 arch/arm/cpu/arm926ejs/armada100/dram.c
 create mode 100644 arch/arm/cpu/arm926ejs/armada100/timer.c
 create mode 100644 arch/arm/include/asm/arch-armada100/armada100.h
 create mode 100644 arch/arm/include/asm/arch-armada100/cpu.h
 create mode 100644 arch/arm/include/asm/arch-armada100/mfp.h
 create mode 100644 board/Marvell/aspenite/Makefile
 create mode 100644 board/Marvell/aspenite/aspenite.c
 create mode 100644 drivers/gpio/mvmfp.c
 create mode 100644 include/configs/aspenite.h
 create mode 100644 include/mvmfp.h

^ permalink raw reply	[flat|nested] 23+ messages in thread

* [U-Boot] [PATCH v4 2/7] gpio: Add Multi-Function-Pin configuration driver for Marvell SoCs
  2010-12-07 15:23   ` Lei Wen
@ 2010-12-07 17:10     ` Prafulla Wadaskar
  2010-12-07 17:39       ` Albert ARIBAUD
  0 siblings, 1 reply; 23+ messages in thread
From: Prafulla Wadaskar @ 2010-12-07 17:10 UTC (permalink / raw)
  To: u-boot



> -----Original Message-----
> From: Lei Wen [mailto:adrian.wenl at gmail.com]
> Sent: Tuesday, December 07, 2010 8:53 PM
> To: Prafulla Wadaskar
> Cc: u-boot at lists.denx.de; Eric Miao; Manas Saksena; Lei Wen; Yu Tang;
> Ashish Karkare; Kiran Vedere; Prabhanjan Sarnaik
> Subject: Re: [U-Boot] [PATCH v4 2/7] gpio: Add Multi-Function-Pin
> configuration driver for Marvell SoCs
> 
> Hi Prafulla,
> 
> On Wed, Dec 8, 2010 at 1:06 AM, Prafulla Wadaskar <prafulla@marvell.com>
> wrote:
> > Most of the Marvell SoCs has Multi Function Pin (MFP) configuration
> registers
> > For ex. ARMADA100.
> >
> > These registers are programmed to expose the specific functionality
> > associated with respective SoC Pins
> >
> > This driver provides configuration APIs,
> > using them, configuration need to be done in board specific code
> >
> > for ex- following code configures MFPs 107 and 108 for UART_TX/RX
> functionality
> >
> > int board_early_init_f(void)
> > {
> > ? ? ? ?u32 mfp_cfg[] = {
> > ? ? ? ? ? ? ? ?/* Console on UART1 */
> > ? ? ? ? ? ? ? ?MFP107_UART1_RXD,
> > ? ? ? ? ? ? ? ?MFP108_UART1_TXD,
> > ? ? ? ? ? ? ? ?MFP_EOC ? ? ? ? /*End of configureation*/
> > ? ? ? ?};
> > ? ? ? ?/* configure MFP's */
> > ? ? ? ?mfp_config(mfp_cfg);
> > ? ? ? ?return 0;
> > }
> >
> > Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>
> > ---
> > Changelog v4:
> > 1. Driver renamed as mvmfp
> > 2. Re-architected mvmfp driver as per review feedback
> >
> > ?drivers/gpio/Makefile | ? ?1 +
> > ?drivers/gpio/mvmfp.c ?| ? 90
> ++++++++++++++++++++++++++++++++++++++++++++
> > ?include/mvmfp.h ? ? ? | ?100
> +++++++++++++++++++++++++++++++++++++++++++++++++
> > ?3 files changed, 191 insertions(+), 0 deletions(-)
> > ?create mode 100644 drivers/gpio/mvmfp.c
> > ?create mode 100644 include/mvmfp.h
> >
> > diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
> > index 398024c..a5fa2b5 100644
> > --- a/drivers/gpio/Makefile
> > +++ b/drivers/gpio/Makefile
> > @@ -27,6 +27,7 @@ LIB ? := $(obj)libgpio.o
> >
> > ?COBJS-$(CONFIG_AT91_GPIO) ? ? ?+= at91_gpio.o
> > ?COBJS-$(CONFIG_KIRKWOOD_GPIO) ?+= kw_gpio.o
> > +COBJS-$(CONFIG_MARVELL_MFP) ? ?+= mvmfp.o
> > ?COBJS-$(CONFIG_MXC_GPIO) ? ? ? += mxc_gpio.o
> > ?COBJS-$(CONFIG_PCA953X) ? ? ? ? ? ? ? ?+= pca953x.o
> > ?COBJS-$(CONFIG_S5P) ? ? ? ? ? ?+= s5p_gpio.o
> > diff --git a/drivers/gpio/mvmfp.c b/drivers/gpio/mvmfp.c
> > new file mode 100644
> > index 0000000..3472278
> > --- /dev/null
> > +++ b/drivers/gpio/mvmfp.c
> > @@ -0,0 +1,90 @@
> > +/*
> > + * (C) Copyright 2010
> > + * Marvell Semiconductor <www.marvell.com>
> > + * Written-by: Prafulla Wadaskar <prafulla@marvell.com>,
> > + *
> > + * See file CREDITS for list of people who contributed to this
> > + * project.
> > + *
> > + * This program is free software; you can redistribute it and/or
> > + * modify it under the terms of the GNU General Public License as
> > + * published by the Free Software Foundation; either version 2 of
> > + * the License, or (at your option) any later version.
> > + *
> > + * This program is distributed in the hope that it will be useful,
> > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> > + * GNU General Public License for more details.
> > + *
> > + * You should have received a copy of the GNU General Public License
> > + * along with this program; if not, write to the Free Software
> > + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
> > + * MA 02110-1301 USA
> > + */
> > +
> > +#include <common.h>
> > +#include <asm/io.h>
> > +#include <mvmfp.h>
> > +#include <asm/arch/mfp.h>
> > +#ifdef CONFIG_ARMADA100
> > +#include <asm/arch/armada100.h>
> > +#define MFPR_BASE ? ? ?ARMD1_MFPR_BASE
> > +#else
> > +#error Unsupported SoC...
> > +#endif
> 
> Why not directly name a CONFIG_MFPR_BASE, and define its value in the
> config file?

Otherway, We can eliminate #define MFPR_BASE here and define the same in asm/arch/armada100.h instead of ARMD1_MFPR_BASE

> If we do like this ifdef, we may need do add each arch here, seems
> some kind of redundant?

This is required here, see drivers/serial/serial.c

...snip...
> > + ? ? ? ? ? ? ? /* Write a mfg register as per configuration */
> > + ? ? ? ? ? ? ? if (cfg_val & MFP_AF_FLAG) {
> > + ? ? ? ? ? ? ? ? ? ? ? /* Abstract and program Afternate-Func Selection
> */
> > + ? ? ? ? ? ? ? ? ? ? ? val &= ~MFP_AF_MASK;
> Do we need to do this & here? For val is only 0 here...

This can be removed.

> Should not it be more concise like:
> writel(cfg_val, p_mfpr);

NACK, cfg_val have some more stuff like offset, flags, those are not required to write on mfp register.

Regards..
Prafulla . .

^ permalink raw reply	[flat|nested] 23+ messages in thread

* [U-Boot] [PATCH v4 2/7] gpio: Add Multi-Function-Pin configuration driver for Marvell SoCs
  2010-12-07 17:10     ` Prafulla Wadaskar
@ 2010-12-07 17:39       ` Albert ARIBAUD
  2010-12-09  6:11         ` Chris Moore
  0 siblings, 1 reply; 23+ messages in thread
From: Albert ARIBAUD @ 2010-12-07 17:39 UTC (permalink / raw)
  To: u-boot

Le 07/12/2010 18:10, Prafulla Wadaskar a ?crit :

>>> +                       val&= ~MFP_AF_MASK;
>> Do we need to do this&  here? For val is only 0 here...
>
> This can be removed.

OTOH, with the &, this line makes no assumption about val, and thus will 
work regardless of it. If the & is removed, and if later val is set to 
non-zero before reaching this instruction, it will cause a bug.

IOW, the & makes the statement more resilient.

Amicalement,
-- 
Albert.

^ permalink raw reply	[flat|nested] 23+ messages in thread

* [U-Boot] [PATCH v4 1/7] arm: Add Support for Marvell ARMADA 100 Familiy SoCs
  2010-12-07 17:06 [U-Boot] [PATCH v4 1/7] arm: Add Support for Marvell ARMADA 100 Familiy SoCs Prafulla Wadaskar
  2010-12-07 17:06 ` [U-Boot] [PATCH v4 2/7] gpio: Add Multi-Function-Pin configuration driver for Marvell SoCs Prafulla Wadaskar
@ 2010-12-08  2:32 ` Eric Miao
  2010-12-08  5:19   ` Prafulla Wadaskar
  2010-12-11 14:12 ` Prafulla Wadaskar
  2 siblings, 1 reply; 23+ messages in thread
From: Eric Miao @ 2010-12-08  2:32 UTC (permalink / raw)
  To: u-boot

On Wed, Dec 8, 2010 at 1:06 AM, Prafulla Wadaskar <prafulla@marvell.com> wrote:
> ARMADA 100 Family processors are highly integrated SoCs
> based on Sheeva_88SV331x-v5 PJ1 cpu core.
> Ref: http://www.marvell.com/products/processors/applications/armada_100
>
> SoC versions Supported:
> 1) ARMADA168/88AP168 ? ?(Aspen P)
> 2) ARMADA166/88AP166 ? ?(Aspen M)
> 3) ARMADA162/88AP162 ? ?(Aspen L)
>
> Contributors:
> Eric Miao <eric.y.miao@marvell.com>

<eric.miao@marvell.com>

Or

<eric.y.miao@gmail.com>

Actually I have little contribution to this, // red face.

The patch below seems quite good. I'll be glad to see this be
upstreamed in the u-boot tree.

> Lei Wen <leiwen@marvell.com>
> Mahavir Jain <mjain@marvell.com>
>
> Signed-off-by: Mahavir Jain <mjain@marvell.com>
> Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>
> ---
> Change log V2:
> 1. C-struct used for dram.c
> 2. lib declaration changed from .a to .o
> 3. Implemented review feedback for v1
>
> Changelog V3:
> 1. timer variables in gt_t used insted of locally defined global variables
> 2. register global pointer moved to respective functions
> 3. Macro READ_TIMER converted to function read_timer()
> 4. c-struc in armada100.h fixed for wrong padding
>
> Changelog V4:
> 1. timer.c updated for build warning
>
> ?arch/arm/cpu/arm926ejs/armada100/Makefile ? ? ? | ? 46 +++++
> ?arch/arm/cpu/arm926ejs/armada100/cpu.c ? ? ? ? ?| ? 92 ++++++++++
> ?arch/arm/cpu/arm926ejs/armada100/dram.c ? ? ? ? | ?131 ++++++++++++++
> ?arch/arm/cpu/arm926ejs/armada100/timer.c ? ? ? ?| ?207 +++++++++++++++++++++++
> ?arch/arm/include/asm/arch-armada100/armada100.h | ?121 +++++++++++++
> ?arch/arm/include/asm/arch-armada100/cpu.h ? ? ? | ? 53 ++++++
> ?6 files changed, 650 insertions(+), 0 deletions(-)
> ?create mode 100644 arch/arm/cpu/arm926ejs/armada100/Makefile
> ?create mode 100644 arch/arm/cpu/arm926ejs/armada100/cpu.c
> ?create mode 100644 arch/arm/cpu/arm926ejs/armada100/dram.c
> ?create mode 100644 arch/arm/cpu/arm926ejs/armada100/timer.c
> ?create mode 100644 arch/arm/include/asm/arch-armada100/armada100.h
> ?create mode 100644 arch/arm/include/asm/arch-armada100/cpu.h
>
> diff --git a/arch/arm/cpu/arm926ejs/armada100/Makefile b/arch/arm/cpu/arm926ejs/armada100/Makefile
> new file mode 100644
> index 0000000..76bd06d
> --- /dev/null
> +++ b/arch/arm/cpu/arm926ejs/armada100/Makefile
> @@ -0,0 +1,46 @@
> +#
> +# (C) Copyright 2010
> +# Marvell Semiconductor <www.marvell.com>
> +# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
> +#
> +# See file CREDITS for list of people who contributed to this
> +# project.
> +#
> +# This program is free software; you can redistribute it and/or
> +# modify it under the terms of the GNU General Public License as
> +# published by the Free Software Foundation; either version 2 of
> +# the License, or (at your option) any later version.
> +#
> +# This program is distributed in the hope that it will be useful,
> +# but WITHOUT ANY WARRANTY; without even the implied warranty of
> +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> +# GNU General Public License for more details.
> +#
> +# You should have received a copy of the GNU General Public License
> +# along with this program; if not, write to the Free Software
> +# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
> +# MA 02110-1301 USA
> +#
> +
> +include $(TOPDIR)/config.mk
> +
> +LIB ? ?= $(obj)lib$(SOC).o
> +
> +COBJS-y ? ? ? ?= cpu.o timer.o dram.o
> +
> +SRCS ? := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
> +OBJS ? := $(addprefix $(obj),$(SOBJS) $(COBJS-y))
> +
> +all: ? $(obj).depend $(LIB)
> +
> +$(LIB): ? ? ? ?$(OBJS)
> + ? ? ? $(AR) $(ARFLAGS) $@ $(OBJS)
> +
> +#########################################################################
> +
> +# defines $(obj).depend target
> +include $(SRCTREE)/rules.mk
> +
> +sinclude $(obj).depend
> +
> +#########################################################################
> diff --git a/arch/arm/cpu/arm926ejs/armada100/cpu.c b/arch/arm/cpu/arm926ejs/armada100/cpu.c
> new file mode 100644
> index 0000000..62aa175
> --- /dev/null
> +++ b/arch/arm/cpu/arm926ejs/armada100/cpu.c
> @@ -0,0 +1,92 @@
> +/*
> + * (C) Copyright 2010
> + * Marvell Semiconductor <www.marvell.com>
> + * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
> + * Contributor: Mahavir Jain <mjain@marvell.com>
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
> + * MA 02110-1301 USA
> + */
> +
> +#include <common.h>
> +#include <asm/arch/armada100.h>
> +#include <asm/io.h>
> +
> +#define UARTCLK14745KHZ ? ? ? ?(APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(1))
> +#define SET_MRVL_ID ? ?(1<<8)
> +#define L2C_RAM_SEL ? ?(1<<4)
> +
> +int arch_cpu_init(void)
> +{
> + ? ? ? u32 val;
> + ? ? ? struct armd1cpu_registers *cpuregs =
> + ? ? ? ? ? ? ? (struct armd1cpu_registers *) ARMD1_CPU_BASE;
> +
> + ? ? ? struct armd1apb1_registers *apb1clkres =
> + ? ? ? ? ? ? ? (struct armd1apb1_registers *) ARMD1_APBC1_BASE;
> +
> + ? ? ? struct armd1mpmu_registers *mpmu =
> + ? ? ? ? ? ? ? (struct armd1mpmu_registers *) ARMD1_MPMU_BASE;
> +
> + ? ? ? /* set SEL_MRVL_ID bit in ARMADA100_CPU_CONF register */
> + ? ? ? val = readl(&cpuregs->cpu_conf);
> + ? ? ? val = val | SET_MRVL_ID;
> + ? ? ? writel(val, &cpuregs->cpu_conf);
> +
> + ? ? ? /* Enable Clocks for all hardware units */
> + ? ? ? writel(0xFFFFFFFF, &mpmu->acgr);
> +
> + ? ? ? /* Turn on AIB and AIB-APB Functional clock */
> + ? ? ? writel(APBC_APBCLK | APBC_FNCLK, &apb1clkres->aib);
> +
> + ? ? ? /* ensure L2 cache is not mapped as SRAM */
> + ? ? ? val = readl(&cpuregs->cpu_conf);
> + ? ? ? val = val & ~(L2C_RAM_SEL);
> + ? ? ? writel(val, &cpuregs->cpu_conf);
> +
> + ? ? ? /* Enable GPIO clock */
> + ? ? ? writel(APBC_APBCLK, &apb1clkres->gpio);
> +
> + ? ? ? /*
> + ? ? ? ?* Enable Functional and APB clock at 14.7456MHz
> + ? ? ? ?* for configured UART console
> + ? ? ? ?*/
> +#if (CONFIG_SYS_NS16550_COM1 == ARMD1_UART3_BASE)
> + ? ? ? writel(UARTCLK14745KHZ, &apb1clkres->uart3);
> +#elif (CONFIG_SYS_NS16550_COM1 == ARMD1_UART2_BASE)
> + ? ? ? writel(UARTCLK14745KHZ, &apb1clkres->uart2);
> +#else
> + ? ? ? writel(UARTCLK14745KHZ, &apb1clkres->uart1);
> +#endif
> + ? ? ? icache_enable();
> +
> + ? ? ? return 0;
> +}
> +
> +#if defined(CONFIG_DISPLAY_CPUINFO)
> +int print_cpuinfo(void)
> +{
> + ? ? ? u32 id;
> + ? ? ? struct armd1cpu_registers *cpuregs =
> + ? ? ? ? ? ? ? (struct armd1cpu_registers *) ARMD1_CPU_BASE;
> +
> + ? ? ? id = readl(&cpuregs->chip_id);
> + ? ? ? printf("SoC: ? Armada 88AP%X-%X\n", (id & 0xFFF), (id >> 0x10));
> + ? ? ? return 0;
> +}
> +#endif
> diff --git a/arch/arm/cpu/arm926ejs/armada100/dram.c b/arch/arm/cpu/arm926ejs/armada100/dram.c
> new file mode 100644
> index 0000000..eacec23
> --- /dev/null
> +++ b/arch/arm/cpu/arm926ejs/armada100/dram.c
> @@ -0,0 +1,131 @@
> +/*
> + * (C) Copyright 2010
> + * Marvell Semiconductor <www.marvell.com>
> + * Written-by: Prafulla Wadaskar <prafulla@marvell.com>,
> + * Contributor: Mahavir Jain <mjain@marvell.com>
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
> + * MA 02110-1301 USA
> + */
> +
> +#include <common.h>
> +#include <asm/arch/armada100.h>
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +/*
> + * ARMADA100 DRAM controller supports upto 8 banks
> + * for chip select 0 and 1
> + */
> +
> +/*
> + * DDR Memory Control Registers
> + * Refer Datasheet Appendix A.17
> + */
> +struct armd1ddr_map_registers {
> + ? ? ? u32 ? ? cs; ? ? /* Memory Address Map Register -CS */
> + ? ? ? u32 ? ? pad[3];
> +};
> +
> +struct armd1ddr_registers {
> + ? ? ? u8 ? ? ?pad[0x100 - 0x000];
> + ? ? ? struct armd1ddr_map_registers mmap[2];
> +};
> +
> +/*
> + * armd1_sdram_base - reads SDRAM Base Address Register
> + */
> +u32 armd1_sdram_base(int chip_sel)
> +{
> + ? ? ? struct armd1ddr_registers *ddr_regs =
> + ? ? ? ? ? ? ? (struct armd1ddr_registers *)ARMD1_DRAM_BASE;
> + ? ? ? u32 result = 0;
> + ? ? ? u32 CS_valid = 0x01 & readl(&ddr_regs->mmap[chip_sel].cs);
> +
> + ? ? ? if (!CS_valid)
> + ? ? ? ? ? ? ? return 0;
> +
> + ? ? ? result = readl(&ddr_regs->mmap[chip_sel].cs) & 0xFF800000;
> + ? ? ? return result;
> +}
> +
> +/*
> + * armd1_sdram_size - reads SDRAM size
> + */
> +u32 armd1_sdram_size(int chip_sel)
> +{
> + ? ? ? struct armd1ddr_registers *ddr_regs =
> + ? ? ? ? ? ? ? (struct armd1ddr_registers *)ARMD1_DRAM_BASE;
> + ? ? ? u32 result = 0;
> + ? ? ? u32 CS_valid = 0x01 & readl(&ddr_regs->mmap[chip_sel].cs);
> +
> + ? ? ? if (!CS_valid)
> + ? ? ? ? ? ? ? return 0;
> +
> + ? ? ? result = readl(&ddr_regs->mmap[chip_sel].cs);
> + ? ? ? result = (result >> 16) & 0xF;
> + ? ? ? if (result < 0x7) {
> + ? ? ? ? ? ? ? printf("Unknown DRAM Size\n");
> + ? ? ? ? ? ? ? return -1;
> + ? ? ? } else {
> + ? ? ? ? ? ? ? return ((0x8 << (result - 0x7)) * 1024 * 1024);
> + ? ? ? }
> +}
> +
> +#ifndef CONFIG_SYS_BOARD_DRAM_INIT
> +int dram_init(void)
> +{
> + ? ? ? int i;
> +
> + ? ? ? gd->ram_size = 0;
> + ? ? ? for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
> + ? ? ? ? ? ? ? gd->bd->bi_dram[i].start = armd1_sdram_base(i);
> + ? ? ? ? ? ? ? gd->bd->bi_dram[i].size = armd1_sdram_size(i);
> + ? ? ? ? ? ? ? /*
> + ? ? ? ? ? ? ? ?* It is assumed that all memory banks are consecutive
> + ? ? ? ? ? ? ? ?* and without gaps.
> + ? ? ? ? ? ? ? ?* If the gap is found, ram_size will be reported for
> + ? ? ? ? ? ? ? ?* consecutive memory only
> + ? ? ? ? ? ? ? ?*/
> + ? ? ? ? ? ? ? if (gd->bd->bi_dram[i].start != gd->ram_size)
> + ? ? ? ? ? ? ? ? ? ? ? break;
> +
> + ? ? ? ? ? ? ? gd->ram_size += gd->bd->bi_dram[i].size;
> +
> + ? ? ? }
> +
> + ? ? ? for (; i < CONFIG_NR_DRAM_BANKS; i++) {
> + ? ? ? ? ? ? ? /* If above loop terminated prematurely, we need to set
> + ? ? ? ? ? ? ? ?* remaining banks' start address & size as 0. Otherwise other
> + ? ? ? ? ? ? ? ?* u-boot functions and Linux kernel gets wrong values which
> + ? ? ? ? ? ? ? ?* could result in crash */
> + ? ? ? ? ? ? ? gd->bd->bi_dram[i].start = 0;
> + ? ? ? ? ? ? ? gd->bd->bi_dram[i].size = 0;
> + ? ? ? }
> + ? ? ? return 0;
> +}
> +
> +/*
> + * If this function is not defined here,
> + * board.c alters dram bank zero configuration defined above.
> + */
> +void dram_init_banksize(void)
> +{
> + ? ? ? dram_init();
> +}
> +#endif /* CONFIG_SYS_BOARD_DRAM_INIT */
> diff --git a/arch/arm/cpu/arm926ejs/armada100/timer.c b/arch/arm/cpu/arm926ejs/armada100/timer.c
> new file mode 100644
> index 0000000..5d911c5
> --- /dev/null
> +++ b/arch/arm/cpu/arm926ejs/armada100/timer.c
> @@ -0,0 +1,207 @@
> +/*
> + * (C) Copyright 2010
> + * Marvell Semiconductor <www.marvell.com>
> + * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
> + * Contributor: Mahavir Jain <mjain@marvell.com>
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
> + * MA 02110-1301 USA
> + */
> +
> +#include <common.h>
> +#include <asm/arch/armada100.h>
> +
> +/*
> + * Timer registers
> + * Refer Section A.6 in Datasheet
> + */
> +struct armd1tmr_registers {
> + ? ? ? u32 clk_ctrl; ? /* Timer clk control reg */
> + ? ? ? u32 match[9]; ? /* Timer match registers */
> + ? ? ? u32 count[3]; ? /* Timer count registers */
> + ? ? ? u32 status[3];
> + ? ? ? u32 ie[3];
> + ? ? ? u32 preload[3]; /* Timer preload value */
> + ? ? ? u32 preload_ctrl[3];
> + ? ? ? u32 wdt_match_en;
> + ? ? ? u32 wdt_match_r;
> + ? ? ? u32 wdt_val;
> + ? ? ? u32 wdt_sts;
> + ? ? ? u32 icr[3];
> + ? ? ? u32 wdt_icr;
> + ? ? ? u32 cer; ? ? ? ?/* Timer count enable reg */
> + ? ? ? u32 cmr;
> + ? ? ? u32 ilr[3];
> + ? ? ? u32 wcr;
> + ? ? ? u32 wfar;
> + ? ? ? u32 wsar;
> + ? ? ? u32 cvwr;
> +};
> +
> +#define TIMER ? ? ? ? ? ? ? ? ?0 ? ? ? /* Use TIMER 0 */
> +/* Each timer has 3 match registers */
> +#define MATCH_CMP(x) ? ? ? ? ? ((3 * TIMER) + x)
> +#define TIMER_LOAD_VAL ? ? ? ? ? ? ? ? 0xffffffff
> +#define ? ? ? ?COUNT_RD_REQ ? ? ? ? ? ?0x1
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +/* Using gd->tbu from timestamp and gd->tbl for lastdec */
> +
> +/* For preventing risk of instability in reading counter value,
> + * first set read request to register cvwr and then read same
> + * register after it captures counter value.
> + */
> +ulong read_timer(void)
> +{
> + ? ? ? struct armd1tmr_registers *armd1timers =
> + ? ? ? ? ? ? ? (struct armd1tmr_registers *) ARMD1_TIMER_BASE;
> + ? ? ? volatile int loop=100;
> +
> + ? ? ? writel(COUNT_RD_REQ, &armd1timers->cvwr);
> + ? ? ? while (loop--);
> + ? ? ? return(readl(&armd1timers->cvwr));
> +}
> +
> +void reset_timer_masked(void)
> +{
> + ? ? ? /* reset time */
> + ? ? ? gd->tbl = read_timer();
> + ? ? ? gd->tbu = 0;
> +}
> +
> +ulong get_timer_masked(void)
> +{
> + ? ? ? ulong now = read_timer();
> +
> + ? ? ? if (now >= gd->tbl) {
> + ? ? ? ? ? ? ? /* normal mode */
> + ? ? ? ? ? ? ? gd->tbu += now - gd->tbl;
> + ? ? ? } else {
> + ? ? ? ? ? ? ? /* we have an overflow ... */
> + ? ? ? ? ? ? ? gd->tbu += now + TIMER_LOAD_VAL - gd->tbl;
> + ? ? ? }
> + ? ? ? gd->tbl = now;
> +
> + ? ? ? return gd->tbu;
> +}
> +
> +void reset_timer(void)
> +{
> + ? ? ? reset_timer_masked();
> +}
> +
> +ulong get_timer(ulong base)
> +{
> + ? ? ? return ((get_timer_masked() / (CONFIG_SYS_HZ_CLOCK / 1000)) -
> + ? ? ? ? ? ? ? base);
> +}
> +
> +void set_timer(ulong t)
> +{
> + ? ? ? gd->tbu = t;
> +}
> +
> +void __udelay(unsigned long usec)
> +{
> + ? ? ? ulong delayticks;
> + ? ? ? ulong endtime;
> +
> + ? ? ? delayticks = (usec * (CONFIG_SYS_HZ_CLOCK / 1000000));
> + ? ? ? endtime = get_timer_masked() + delayticks;
> +
> + ? ? ? while (get_timer_masked() < endtime);
> +}
> +
> +/*
> + * init the Timer
> + */
> +int timer_init(void)
> +{
> + ? ? ? struct armd1apb1_registers *apb1clkres =
> + ? ? ? ? ? ? ? (struct armd1apb1_registers *) ARMD1_APBC1_BASE;
> + ? ? ? struct armd1tmr_registers *armd1timers =
> + ? ? ? ? ? ? ? (struct armd1tmr_registers *) ARMD1_TIMER_BASE;
> +
> + ? ? ? /* Enable Timer clock at 3.25 MHZ */
> + ? ? ? writel(APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(3), &apb1clkres->timers);
> +
> + ? ? ? /* load value into timer */
> + ? ? ? writel(0x0, &armd1timers->clk_ctrl);
> + ? ? ? /* Use Timer 0 Match Resiger 0 */
> + ? ? ? writel(TIMER_LOAD_VAL, &armd1timers->match[MATCH_CMP(0)]);
> + ? ? ? /* Preload value is 0 */
> + ? ? ? writel(0x0, &armd1timers->preload[TIMER]);
> + ? ? ? /* Enable match comparator 0 for Timer 0 */
> + ? ? ? writel(0x1, &armd1timers->preload_ctrl[TIMER]);
> +
> + ? ? ? /* Enable timer 0 */
> + ? ? ? writel(0x1, &armd1timers->cer);
> + ? ? ? /* init the gd->tbu and gd->tbl value */
> + ? ? ? reset_timer_masked();
> +
> + ? ? ? return 0;
> +}
> +
> +#define MPMU_APRR_WDTR (1<<4)
> +#define TMR_WFAR ? ? ? 0xbaba ?/* WDT Register First key */
> +#define TMP_WSAR ? ? ? 0xeb10 ?/* WDT Register Second key */
> +
> +/*
> + * This function uses internal Watchdog Timer
> + * based reset mechanism.
> + * Steps to write watchdog registers (protected access)
> + * 1. Write key value to TMR_WFAR reg.
> + * 2. Write key value to TMP_WSAR reg.
> + * 3. Perform write operation.
> + */
> +void reset_cpu (unsigned long ignored)
> +{
> + ? ? ? struct armd1mpmu_registers *mpmu =
> + ? ? ? ? ? ? ? (struct armd1mpmu_registers *) ARMD1_MPMU_BASE;
> + ? ? ? struct armd1tmr_registers *armd1timers =
> + ? ? ? ? ? ? ? (struct armd1tmr_registers *) ARMD1_TIMER_BASE;
> + ? ? ? u32 val;
> +
> + ? ? ? /* negate hardware reset to the WDT after system reset */
> + ? ? ? val = readl(&mpmu->aprr);
> + ? ? ? val = val | MPMU_APRR_WDTR;
> + ? ? ? writel(val, &mpmu->aprr);
> +
> + ? ? ? /* reset/enable WDT clock */
> + ? ? ? writel(APBC_APBCLK | APBC_FNCLK | APBC_RST, &mpmu->wdtpcr);
> + ? ? ? readl(&mpmu->wdtpcr);
> + ? ? ? writel(APBC_APBCLK | APBC_FNCLK, &mpmu->wdtpcr);
> + ? ? ? readl(&mpmu->wdtpcr);
> +
> + ? ? ? /* clear previous WDT status */
> + ? ? ? writel(TMR_WFAR, &armd1timers->wfar);
> + ? ? ? writel(TMP_WSAR, &armd1timers->wsar);
> + ? ? ? writel(0, &armd1timers->wdt_sts);
> +
> + ? ? ? /* set match counter */
> + ? ? ? writel(TMR_WFAR, &armd1timers->wfar);
> + ? ? ? writel(TMP_WSAR, &armd1timers->wsar);
> + ? ? ? writel(0xf, &armd1timers->wdt_match_r);
> +
> + ? ? ? /* enable WDT reset */
> + ? ? ? writel(TMR_WFAR, &armd1timers->wfar);
> + ? ? ? writel(TMP_WSAR, &armd1timers->wsar);
> + ? ? ? writel(0x3, &armd1timers->wdt_match_en);
> +
> + ? ? ? while(1);
> +}
> diff --git a/arch/arm/include/asm/arch-armada100/armada100.h b/arch/arm/include/asm/arch-armada100/armada100.h
> new file mode 100644
> index 0000000..d5d125a
> --- /dev/null
> +++ b/arch/arm/include/asm/arch-armada100/armada100.h
> @@ -0,0 +1,121 @@
> +/*
> + * (C) Copyright 2010
> + * Marvell Semiconductor <www.marvell.com>
> + * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
> + * Contributor: Mahavir Jain <mjain@marvell.com>
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
> + * MA 02110-1301 USA
> + */
> +
> +#ifndef _ASM_ARCH_ARMADA100_H
> +#define _ASM_ARCH_ARMADA100_H
> +
> +#ifndef __ASSEMBLY__
> +#include <asm/types.h>
> +#include <asm/io.h>
> +#endif /* __ASSEMBLY__ */
> +
> +#if defined (CONFIG_ARMADA100)
> +#include <asm/arch/cpu.h>
> +
> +/* Common APB clock register bit definitions */
> +#define APBC_APBCLK ? ? (1<<0) ?/* APB Bus Clock Enable */
> +#define APBC_FNCLK ? ? ?(1<<1) ?/* Functional Clock Enable */
> +#define APBC_RST ? ? ? ?(1<<2) ?/* Reset Generation */
> +/* Functional Clock Selection Mask */
> +#define APBC_FNCLKSEL(x) ? ? ? ?(((x) & 0xf) << 4)
> +
> +/* Register Base Addresses */
> +#define ARMD1_DRAM_BASE ? ? ? ? ? ? ? ?0xB0000000
> +#define ARMD1_TIMER_BASE ? ? ? 0xD4014000
> +#define ARMD1_APBC1_BASE ? ? ? 0xD4015000
> +#define ARMD1_APBC2_BASE ? ? ? 0xD4015800
> +#define ARMD1_UART1_BASE ? ? ? 0xD4017000
> +#define ARMD1_UART2_BASE ? ? ? 0xD4018000
> +#define ARMD1_GPIO_BASE ? ? ? ? ? ? ? ?0xD4019000
> +#define ARMD1_SSP1_BASE ? ? ? ? ? ? ? ?0xD401B000
> +#define ARMD1_SSP2_BASE ? ? ? ? ? ? ? ?0xD401C000
> +#define ARMD1_MFPR_BASE ? ? ? ? ? ? ? ?0xD401E000
> +#define ARMD1_SSP3_BASE ? ? ? ? ? ? ? ?0xD401F000
> +#define ARMD1_SSP4_BASE ? ? ? ? ? ? ? ?0xD4020000
> +#define ARMD1_SSP5_BASE ? ? ? ? ? ? ? ?0xD4021000
> +#define ARMD1_UART3_BASE ? ? ? 0xD4026000
> +#define ARMD1_MPMU_BASE ? ? ? ? ? ? ? ?0xD4050000
> +#define ARMD1_APMU_BASE ? ? ? ? ? ? ? ?0xD4282800
> +#define ARMD1_CPU_BASE ? ? ? ? 0xD4282C00
> +
> +/*
> + * Main Power Management (MPMU) Registers
> + * Refer Datasheet Appendix A.8
> + */
> +struct armd1mpmu_registers {
> + ? ? ? u8 pad0[0x08 - 0x00];
> + ? ? ? u32 fccr; ? ? ? /*0x0008*/
> + ? ? ? u32 pocr; ? ? ? /*0x000c*/
> + ? ? ? u32 posr; ? ? ? /*0x0010*/
> + ? ? ? u32 succr; ? ? ?/*0x0014*/
> + ? ? ? u8 pad1[0x030 - 0x014 - 4];
> + ? ? ? u32 gpcr; ? ? ? /*0x0030*/
> + ? ? ? u8 pad2[0x200 - 0x030 - 4];
> + ? ? ? u32 wdtpcr; ? ? /*0x0200*/
> + ? ? ? u8 pad3[0x1000 - 0x200 - 4];
> + ? ? ? u32 apcr; ? ? ? /*0x1000*/
> + ? ? ? u32 apsr; ? ? ? /*0x1004*/
> + ? ? ? u8 pad4[0x1020 - 0x1004 - 4];
> + ? ? ? u32 aprr; ? ? ? /*0x1020*/
> + ? ? ? u32 acgr; ? ? ? /*0x1024*/
> + ? ? ? u32 arsr; ? ? ? /*0x1028*/
> +};
> +
> +/*
> + * APB1 Clock Reset/Control Registers
> + * Refer Datasheet Appendix A.10
> + */
> +struct armd1apb1_registers {
> + ? ? ? u32 uart1; ? ? ?/*0x000*/
> + ? ? ? u32 uart2; ? ? ?/*0x004*/
> + ? ? ? u32 gpio; ? ? ? /*0x008*/
> + ? ? ? u32 pwm1; ? ? ? /*0x00c*/
> + ? ? ? u32 pwm2; ? ? ? /*0x010*/
> + ? ? ? u32 pwm3; ? ? ? /*0x014*/
> + ? ? ? u32 pwm4; ? ? ? /*0x018*/
> + ? ? ? u8 pad0[0x028 - 0x018 - 4];
> + ? ? ? u32 rtc; ? ? ? ?/*0x028*/
> + ? ? ? u32 twsi0; ? ? ?/*0x02c*/
> + ? ? ? u32 kpc; ? ? ? ?/*0x030*/
> + ? ? ? u32 timers; ? ? /*0x034*/
> + ? ? ? u8 pad1[0x03c - 0x034 - 4];
> + ? ? ? u32 aib; ? ? ? ?/*0x03c*/
> + ? ? ? u32 sw_jtag; ? ?/*0x040*/
> + ? ? ? u32 timer1; ? ? /*0x044*/
> + ? ? ? u32 onewire; ? ?/*0x048*/
> + ? ? ? u8 pad2[0x050 - 0x048 - 4];
> + ? ? ? u32 asfar; ? ? ?/*0x050 AIB Secure First Access Reg*/
> + ? ? ? u32 assar; ? ? ?/*0x054 AIB Secure Second Access Reg*/
> + ? ? ? u8 pad3[0x06c - 0x054 - 4];
> + ? ? ? u32 twsi1; ? ? ?/*0x06c*/
> + ? ? ? u32 uart3; ? ? ?/*0x070*/
> + ? ? ? u8 pad4[0x07c - 0x070 - 4];
> + ? ? ? u32 timer2; ? ? /*0x07C*/
> + ? ? ? u8 pad5[0x084 - 0x07c - 4];
> + ? ? ? u32 ac97; ? ? ? /*0x084*/
> +};
> +
> +#endif /* CONFIG_ARMADA100 */
> +#endif /* _ASM_ARCH_ARMADA100_H */
> diff --git a/arch/arm/include/asm/arch-armada100/cpu.h b/arch/arm/include/asm/arch-armada100/cpu.h
> new file mode 100644
> index 0000000..0518a6a
> --- /dev/null
> +++ b/arch/arm/include/asm/arch-armada100/cpu.h
> @@ -0,0 +1,53 @@
> +/*
> + * (C) Copyright 2010
> + * Marvell Semiconductor <www.marvell.com>
> + * Written-by: Prafulla Wadaskar <prafulla@marvell.com>, Contributor: Mahavir Jain <mjain@marvell.com>
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
> + * MA 02110-1301 USA
> + */
> +
> +#ifndef _ARMADA100CPU_H
> +#define _ARMADA100CPU_H
> +
> +#include <asm/io.h>
> +#include <asm/system.h>
> +
> +/*
> + * CPU Interface Registers
> + * Refer Datasheet Appendix A.2
> + */
> +struct armd1cpu_registers {
> + ? ? ? u32 chip_id; ? ? ? ? ? ?/* Chip Id Reg */
> + ? ? ? u32 pad;
> + ? ? ? u32 cpu_conf; ? ? ? ? ? /* CPU Conf Reg */
> + ? ? ? u32 pad1;
> + ? ? ? u32 cpu_sram_spd; ? ? ? /* CPU SRAM Speed Reg */
> + ? ? ? u32 pad2;
> + ? ? ? u32 cpu_l2c_spd; ? ? ? ?/* CPU L2cache Speed Conf */
> + ? ? ? u32 mcb_conf; ? ? ? ? ? /* MCB Conf Reg */
> + ? ? ? u32 sys_boot_ctl; ? ? ? /* Sytem Boot Control */
> +};
> +
> +/*
> + * Functions
> + */
> +u32 armd1_sdram_base(int);
> +u32 armd1_sdram_size(int);
> +
> +#endif /* _ARMADA100CPU_H */
> --
> 1.5.3.4
>
>

^ permalink raw reply	[flat|nested] 23+ messages in thread

* [U-Boot] [PATCH v4 1/7] arm: Add Support for Marvell ARMADA 100 Familiy SoCs
  2010-12-08  2:32 ` [U-Boot] [PATCH v4 1/7] arm: Add Support for Marvell ARMADA 100 Familiy SoCs Eric Miao
@ 2010-12-08  5:19   ` Prafulla Wadaskar
  0 siblings, 0 replies; 23+ messages in thread
From: Prafulla Wadaskar @ 2010-12-08  5:19 UTC (permalink / raw)
  To: u-boot



> -----Original Message-----
> From: Eric Miao [mailto:eric.y.miao at gmail.com]
> Sent: Wednesday, December 08, 2010 8:03 AM
> To: Prafulla Wadaskar
> Cc: u-boot at lists.denx.de; Lei Wen; Yu Tang; Kiran Vedere; Manas Saksena;
> Prabhanjan Sarnaik; Ashish Karkare; Mahavir Jain
> Subject: Re: [PATCH v4 1/7] arm: Add Support for Marvell ARMADA 100
> Familiy SoCs
> 
> On Wed, Dec 8, 2010 at 1:06 AM, Prafulla Wadaskar <prafulla@marvell.com>
> wrote:
> > ARMADA 100 Family processors are highly integrated SoCs
> > based on Sheeva_88SV331x-v5 PJ1 cpu core.
> > Ref: http://www.marvell.com/products/processors/applications/armada_100
> >
> > SoC versions Supported:
> > 1) ARMADA168/88AP168 ? ?(Aspen P)
> > 2) ARMADA166/88AP166 ? ?(Aspen M)
> > 3) ARMADA162/88AP162 ? ?(Aspen L)
> >
> > Contributors:
> > Eric Miao <eric.y.miao@marvell.com>
> 
> <eric.miao@marvell.com>
> 
> Or
> 
> <eric.y.miao@gmail.com>

Hi Eric
I will correct this.

> 
> Actually I have little contribution to this, // red face.

Something is always better than nothing :-)

> 
> The patch below seems quite good. I'll be glad to see this be
> upstreamed in the u-boot tree.

Thanks, hope it will happen soon.

Regards..
Prafulla .. 

^ permalink raw reply	[flat|nested] 23+ messages in thread

* [U-Boot] [PATCH v4 2/7] gpio: Add Multi-Function-Pin configuration driver for Marvell SoCs
  2010-12-07 17:39       ` Albert ARIBAUD
@ 2010-12-09  6:11         ` Chris Moore
  2010-12-09  6:59           ` Albert ARIBAUD
  0 siblings, 1 reply; 23+ messages in thread
From: Chris Moore @ 2010-12-09  6:11 UTC (permalink / raw)
  To: u-boot

Hi,

Le 07/12/2010 18:39, Albert ARIBAUD a ?crit :
> Le 07/12/2010 18:10, Prafulla Wadaskar a ?crit :
>
>>>> +                       val&= ~MFP_AF_MASK;
>>> Do we need to do this&   here? For val is only 0 here...
>> This can be removed.
> OTOH, with the&, this line makes no assumption about val, and thus will
> work regardless of it. If the&  is removed, and if later val is set to
> non-zero before reaching this instruction, it will cause a bug.
>
> IOW, the&  makes the statement more resilient.
>

If val really is zero then the result will always be zero :(
Simply removing the & would give a different result.
It would be better to remove the whole bloody line ;-)

I haven't followed this thread but I suspect the original code was wrong.

Cheers,
Chris

^ permalink raw reply	[flat|nested] 23+ messages in thread

* [U-Boot] [PATCH v4 2/7] gpio: Add Multi-Function-Pin configuration driver for Marvell SoCs
  2010-12-09  6:11         ` Chris Moore
@ 2010-12-09  6:59           ` Albert ARIBAUD
  2010-12-09  9:18             ` Prafulla Wadaskar
  0 siblings, 1 reply; 23+ messages in thread
From: Albert ARIBAUD @ 2010-12-09  6:59 UTC (permalink / raw)
  To: u-boot

Hi Chris,

Le 09/12/2010 07:11, Chris Moore a ?crit :
> Hi,
>
> Le 07/12/2010 18:39, Albert ARIBAUD a ?crit :
>> Le 07/12/2010 18:10, Prafulla Wadaskar a ?crit :
>>
>>>>> + val&= ~MFP_AF_MASK;
>>>> Do we need to do this& here? For val is only 0 here...
>>> This can be removed.
>> OTOH, with the&, this line makes no assumption about val, and thus will
>> work regardless of it. If the& is removed, and if later val is set to
>> non-zero before reaching this instruction, it will cause a bug.
>>
>> IOW, the& makes the statement more resilient.
>>
>
> If val really is zero then the result will always be zero :(
> Simply removing the & would give a different result.
> It would be better to remove the whole bloody line ;-)
>
> I haven't followed this thread but I suspect the original code was wrong.

Good point as to the removal if the removal must be done :)

I still think that the original is functionally more correct *if we are 
not sure that val will always be zero.

I'll have a second look tonight.

> Cheers,
> Chris

Amicalement,
-- 
Albert.

^ permalink raw reply	[flat|nested] 23+ messages in thread

* [U-Boot] [PATCH v4 2/7] gpio: Add Multi-Function-Pin configuration driver for Marvell SoCs
  2010-12-09  6:59           ` Albert ARIBAUD
@ 2010-12-09  9:18             ` Prafulla Wadaskar
  0 siblings, 0 replies; 23+ messages in thread
From: Prafulla Wadaskar @ 2010-12-09  9:18 UTC (permalink / raw)
  To: u-boot



> -----Original Message-----
> From: u-boot-bounces at lists.denx.de [mailto:u-boot-bounces at lists.denx.de]
> On Behalf Of Albert ARIBAUD
> Sent: Thursday, December 09, 2010 12:29 PM
> To: Chris Moore
> Cc: u-boot at lists.denx.de
> Subject: Re: [U-Boot] [PATCH v4 2/7] gpio: Add Multi-Function-Pin
> configuration driver for Marvell SoCs
> 
> Hi Chris,
> 
> Le 09/12/2010 07:11, Chris Moore a ?crit :
> > Hi,
> >
> > Le 07/12/2010 18:39, Albert ARIBAUD a ?crit :
> >> Le 07/12/2010 18:10, Prafulla Wadaskar a ?crit :
> >>
> >>>>> + val&= ~MFP_AF_MASK;
> >>>> Do we need to do this& here? For val is only 0 here...
> >>> This can be removed.
> >> OTOH, with the&, this line makes no assumption about val, and thus will
> >> work regardless of it. If the& is removed, and if later val is set to
> >> non-zero before reaching this instruction, it will cause a bug.
> >>
> >> IOW, the& makes the statement more resilient.
> >>
> >
> > If val really is zero then the result will always be zero :(
> > Simply removing the & would give a different result.
> > It would be better to remove the whole bloody line ;-)
> >
> > I haven't followed this thread but I suspect the original code was
> wrong.
> 
> Good point as to the removal if the removal must be done :)
> 
> I still think that the original is functionally more correct *if we are
> not sure that val will always be zero.

The earlier code was using read-modify-write strategy for mfpr programming.
It is changed to create-write.
So removing 'and' operation makes more sense, I will post v4.1 for this since I do not want to post entire patch series.

Regards..
Prafulla . .

^ permalink raw reply	[flat|nested] 23+ messages in thread

* [U-Boot] [PATCH v4 1/7] arm: Add Support for Marvell ARMADA 100 Familiy SoCs
  2010-12-07 17:06 [U-Boot] [PATCH v4 1/7] arm: Add Support for Marvell ARMADA 100 Familiy SoCs Prafulla Wadaskar
  2010-12-07 17:06 ` [U-Boot] [PATCH v4 2/7] gpio: Add Multi-Function-Pin configuration driver for Marvell SoCs Prafulla Wadaskar
  2010-12-08  2:32 ` [U-Boot] [PATCH v4 1/7] arm: Add Support for Marvell ARMADA 100 Familiy SoCs Eric Miao
@ 2010-12-11 14:12 ` Prafulla Wadaskar
  2 siblings, 0 replies; 23+ messages in thread
From: Prafulla Wadaskar @ 2010-12-11 14:12 UTC (permalink / raw)
  To: u-boot



> -----Original Message-----
> From: Prafulla Wadaskar [mailto:prafulla at marvell.com]
> Sent: Tuesday, December 07, 2010 10:36 PM
> To: u-boot at lists.denx.de
> Cc: Lei Wen; Eric Miao; Yu Tang; Kiran Vedere; Manas Saksena; Prabhanjan
> Sarnaik; Ashish Karkare; Prafulla Wadaskar; Mahavir Jain
> Subject: [PATCH v4 1/7] arm: Add Support for Marvell ARMADA 100 Familiy
> SoCs
> 
> ARMADA 100 Family processors are highly integrated SoCs
> based on Sheeva_88SV331x-v5 PJ1 cpu core.
> Ref: http://www.marvell.com/products/processors/applications/armada_100
> 
> SoC versions Supported:
> 1) ARMADA168/88AP168	(Aspen P)
> 2) ARMADA166/88AP166	(Aspen M)
> 3) ARMADA162/88AP162	(Aspen L)
> 
> Contributors:
> Eric Miao <eric.y.miao@marvell.com>
> Lei Wen <leiwen@marvell.com>
> Mahavir Jain <mjain@marvell.com>
> 
> Signed-off-by: Mahavir Jain <mjain@marvell.com>
> Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>
> ---
> Change log V2:
> 1. C-struct used for dram.c
> 2. lib declaration changed from .a to .o
> 3. Implemented review feedback for v1
> 
> Changelog V3:
> 1. timer variables in gt_t used insted of locally defined global variables
> 2. register global pointer moved to respective functions
> 3. Macro READ_TIMER converted to function read_timer()
> 4. c-struc in armada100.h fixed for wrong padding
> 
> Changelog V4:
> 1. timer.c updated for build warning
> 
>  arch/arm/cpu/arm926ejs/armada100/Makefile       |   46 +++++
>  arch/arm/cpu/arm926ejs/armada100/cpu.c          |   92 ++++++++++
>  arch/arm/cpu/arm926ejs/armada100/dram.c         |  131 ++++++++++++++
>  arch/arm/cpu/arm926ejs/armada100/timer.c        |  207
> +++++++++++++++++++++++
>  arch/arm/include/asm/arch-armada100/armada100.h |  121 +++++++++++++
>  arch/arm/include/asm/arch-armada100/cpu.h       |   53 ++++++
>  6 files changed, 650 insertions(+), 0 deletions(-)
>  create mode 100644 arch/arm/cpu/arm926ejs/armada100/Makefile
>  create mode 100644 arch/arm/cpu/arm926ejs/armada100/cpu.c
>  create mode 100644 arch/arm/cpu/arm926ejs/armada100/dram.c
>  create mode 100644 arch/arm/cpu/arm926ejs/armada100/timer.c
>  create mode 100644 arch/arm/include/asm/arch-armada100/armada100.h
>  create mode 100644 arch/arm/include/asm/arch-armada100/cpu.h
>

Applied to u-boot-marvell.git master branch

Regards..
Prafulla ..

^ permalink raw reply	[flat|nested] 23+ messages in thread

* [U-Boot] [PATCH v4 3/7] add Multi Function Pin configuration support for ARMADA100
  2010-12-07 17:06   ` [U-Boot] [PATCH v4 3/7] add Multi Function Pin configuration support for ARMADA100 Prafulla Wadaskar
  2010-12-07 17:06     ` [U-Boot] [PATCH v4 4/7] Serial: ns16550: Add support for CONFIG_SYS_NS16550_IER macro Prafulla Wadaskar
@ 2010-12-11 14:13     ` Prafulla Wadaskar
  1 sibling, 0 replies; 23+ messages in thread
From: Prafulla Wadaskar @ 2010-12-11 14:13 UTC (permalink / raw)
  To: u-boot



> -----Original Message-----
> From: Prafulla Wadaskar [mailto:prafulla at marvell.com]
> Sent: Tuesday, December 07, 2010 10:36 PM
> To: u-boot at lists.denx.de
> Cc: Lei Wen; Eric Miao; Yu Tang; Kiran Vedere; Manas Saksena; Prabhanjan
> Sarnaik; Ashish Karkare; Prafulla Wadaskar
> Subject: [PATCH v4 3/7] add Multi Function Pin configuration support for
> ARMADA100
> 
> This patch adds the support MFP support for Marvell ARMADA100 SoCs
> 
> Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>
> ---
> Changelog v4:
> macros redefined as per new mvmfp driver architecture
> 
>  arch/arm/include/asm/arch-armada100/mfp.h |   67
> +++++++++++++++++++++++++++++
>  1 files changed, 67 insertions(+), 0 deletions(-)
>  create mode 100644 arch/arm/include/asm/arch-armada100/mfp.h
> 

Applied to u-boot-marvell.git master branch

Regards..
Prafulla ..

^ permalink raw reply	[flat|nested] 23+ messages in thread

* [U-Boot] [PATCH v4 4/7] Serial: ns16550: Add support for CONFIG_SYS_NS16550_IER macro
  2010-12-07 17:06     ` [U-Boot] [PATCH v4 4/7] Serial: ns16550: Add support for CONFIG_SYS_NS16550_IER macro Prafulla Wadaskar
  2010-12-07 17:06       ` [U-Boot] [PATCH v4 5/7] Serial: Add UART support for Marvell ARMADA 100 SoCs Prafulla Wadaskar
@ 2010-12-11 14:13       ` Prafulla Wadaskar
  1 sibling, 0 replies; 23+ messages in thread
From: Prafulla Wadaskar @ 2010-12-11 14:13 UTC (permalink / raw)
  To: u-boot



> -----Original Message-----
> From: Prafulla Wadaskar [mailto:prafulla at marvell.com]
> Sent: Tuesday, December 07, 2010 10:36 PM
> To: u-boot at lists.denx.de
> Cc: Lei Wen; Eric Miao; Yu Tang; Kiran Vedere; Manas Saksena; Prabhanjan
> Sarnaik; Ashish Karkare; Prafulla Wadaskar
> Subject: [PATCH v4 4/7] Serial: ns16550: Add support for
> CONFIG_SYS_NS16550_IER macro
> 
> On some processors this ier register configuration is different
> for ex. Marvell Armada100
> 
> This patch introduce CONFIG_SYS_NS16550_IER macro support to
> unconditionally initialize this register.
> 
> Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>
> ---
> Changelog v3:
> macro defination CONFIG_SYS_NS16550_IER moved from ns16550.h to ns16550.c
> 
>  drivers/serial/ns16550.c |    8 ++++++--
>  1 files changed, 6 insertions(+), 2 deletions(-)
>

Applied to u-boot-marvell.git master branch

Regards..
Prafulla .. 

^ permalink raw reply	[flat|nested] 23+ messages in thread

* [U-Boot] [PATCH v4 5/7] Serial: Add UART support for Marvell ARMADA 100 SoCs.
  2010-12-07 17:06       ` [U-Boot] [PATCH v4 5/7] Serial: Add UART support for Marvell ARMADA 100 SoCs Prafulla Wadaskar
  2010-12-07 17:06         ` [U-Boot] [PATCH v4 6/7] mv-common.h: Add support for ARMADA100 Platforms Prafulla Wadaskar
@ 2010-12-11 14:13         ` Prafulla Wadaskar
  1 sibling, 0 replies; 23+ messages in thread
From: Prafulla Wadaskar @ 2010-12-11 14:13 UTC (permalink / raw)
  To: u-boot



> -----Original Message-----
> From: Prafulla Wadaskar [mailto:prafulla at marvell.com]
> Sent: Tuesday, December 07, 2010 10:36 PM
> To: u-boot at lists.denx.de
> Cc: Lei Wen; Eric Miao; Yu Tang; Kiran Vedere; Manas Saksena; Prabhanjan
> Sarnaik; Ashish Karkare; Prafulla Wadaskar; Mahavir Jain
> Subject: [PATCH v4 5/7] Serial: Add UART support for Marvell ARMADA 100
> SoCs.
> 
> ARMADA 100 SoCs has NS16550 compatible UART peripheral
> This patch enables the same for ARMADA100 platforms
> 
> Signed-off-by: Mahavir Jain <mjain@marvell.com>
> Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>
> ---
> Change log for v2:
> defined CONFIG_SYS_NS16550_IER macro in Soc heder file
> Change log for v3:
> Removed reordiring of header files, the diff is only
> limited to include armada100.h
> 
>  drivers/serial/serial.c |    5 +++--
>  1 files changed, 3 insertions(+), 2 deletions(-)
> 

Applied to u-boot-marvell.git master branch

Regards..
Prafulla ..

^ permalink raw reply	[flat|nested] 23+ messages in thread

* [U-Boot] [PATCH v4 7/7] Armada100: Add Board Support for Marvell Aspenite-DB
  2010-12-07 17:06           ` [U-Boot] [PATCH v4 7/7] Armada100: Add Board Support for Marvell Aspenite-DB Prafulla Wadaskar
  2010-12-07 17:06             ` [U-Boot] [PATCH v4 0/7] Add Marvell New Soc Support ARMADA100 Prafulla Wadaskar
@ 2010-12-11 14:14             ` Prafulla Wadaskar
  1 sibling, 0 replies; 23+ messages in thread
From: Prafulla Wadaskar @ 2010-12-11 14:14 UTC (permalink / raw)
  To: u-boot



> -----Original Message-----
> From: Prafulla Wadaskar [mailto:prafulla at marvell.com]
> Sent: Tuesday, December 07, 2010 10:36 PM
> To: u-boot at lists.denx.de
> Cc: Lei Wen; Eric Miao; Yu Tang; Kiran Vedere; Manas Saksena; Prabhanjan
> Sarnaik; Ashish Karkare; Prafulla Wadaskar; Mahavir Jain
> Subject: [PATCH v4 7/7] Armada100: Add Board Support for Marvell Aspenite-
> DB
> 
> Aspenite is a Development Board for ASPEN/ARMADA168(88AP168) with
> 	* Processor upto 1.2GHz
>         * Parallel 1Gb x8 DDR2-1066 MHz
>         * 16 Mb x16 NOR, 4Gb x8 SLC NAND, footprint for SPI NOR
>         * Footprints for eMMC/eSD NAND & MMC x8 card
>         * 4-in-1 card reader (xD, MMC/SD/MS Pro), CF True IDE socket
>         * SEAF memory board, subset of PISMO2
>     With Peripherals:
>         * 4.3" WVGA 24-bit LCD
>         * Audio codecs (AC97 & I2S), TSI
>         * VGA camera
>         * Video in via 3 RCA jacks, and HDMI type C out
>         * Marvell 88W8688 802.11bg/BT module
>         * GPS RF IC
>         * Dual analog mics & speakers, headset jack, LED, ambient light
> sensor
>         * USB2.0 HS host  (A), OTG (micro AB)
>         * FE PHY, PCIE Mini Card  slot
>         * GPIO, GPIO expander with DIP switches for easier selection UART
> serial over USB, CIR
> 
> This patch adds basic board support with DRAM and UART functionality
> The patch is tested for boot from DRAM using XDB
> 
> Signed-off-by: Mahavir Jain <mjain@marvell.com>
> Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>
> ---
> Change log for v2:
> used mv-common.h
> defined CONFIG_SYS_NS16550_IER macro in Soc heder file
> removed config.mk
> 
> Change log for v3:
> DEBUG removed from aspenite.h
> 
> Change log for v4:
> name changes as per mvmfp
> 
>  MAINTAINERS                       |    1 +
>  MAKEALL                           |    1 +
>  board/Marvell/aspenite/Makefile   |   52 ++++++++++++++++++++++++++++++
>  board/Marvell/aspenite/aspenite.c |   53 +++++++++++++++++++++++++++++++
>  boards.cfg                        |    1 +
>  include/configs/aspenite.h        |   63
> +++++++++++++++++++++++++++++++++++++
>  6 files changed, 171 insertions(+), 0 deletions(-)
>  create mode 100644 board/Marvell/aspenite/Makefile
>  create mode 100644 board/Marvell/aspenite/aspenite.c
>  create mode 100644 include/configs/aspenite.h
>

Applied to u-boot-marvell.git master branch

Regards..
Prafulla ..

^ permalink raw reply	[flat|nested] 23+ messages in thread

end of thread, other threads:[~2010-12-11 14:14 UTC | newest]

Thread overview: 23+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2010-12-07 17:06 [U-Boot] [PATCH v4 1/7] arm: Add Support for Marvell ARMADA 100 Familiy SoCs Prafulla Wadaskar
2010-12-07 17:06 ` [U-Boot] [PATCH v4 2/7] gpio: Add Multi-Function-Pin configuration driver for Marvell SoCs Prafulla Wadaskar
2010-12-07 15:23   ` Lei Wen
2010-12-07 17:10     ` Prafulla Wadaskar
2010-12-07 17:39       ` Albert ARIBAUD
2010-12-09  6:11         ` Chris Moore
2010-12-09  6:59           ` Albert ARIBAUD
2010-12-09  9:18             ` Prafulla Wadaskar
2010-12-07 17:06   ` [U-Boot] [PATCH v4 3/7] add Multi Function Pin configuration support for ARMADA100 Prafulla Wadaskar
2010-12-07 17:06     ` [U-Boot] [PATCH v4 4/7] Serial: ns16550: Add support for CONFIG_SYS_NS16550_IER macro Prafulla Wadaskar
2010-12-07 17:06       ` [U-Boot] [PATCH v4 5/7] Serial: Add UART support for Marvell ARMADA 100 SoCs Prafulla Wadaskar
2010-12-07 17:06         ` [U-Boot] [PATCH v4 6/7] mv-common.h: Add support for ARMADA100 Platforms Prafulla Wadaskar
2010-12-07 15:32           ` Lei Wen
2010-12-07 16:58             ` Prafulla Wadaskar
2010-12-07 17:06           ` [U-Boot] [PATCH v4 7/7] Armada100: Add Board Support for Marvell Aspenite-DB Prafulla Wadaskar
2010-12-07 17:06             ` [U-Boot] [PATCH v4 0/7] Add Marvell New Soc Support ARMADA100 Prafulla Wadaskar
2010-12-11 14:14             ` [U-Boot] [PATCH v4 7/7] Armada100: Add Board Support for Marvell Aspenite-DB Prafulla Wadaskar
2010-12-11 14:13         ` [U-Boot] [PATCH v4 5/7] Serial: Add UART support for Marvell ARMADA 100 SoCs Prafulla Wadaskar
2010-12-11 14:13       ` [U-Boot] [PATCH v4 4/7] Serial: ns16550: Add support for CONFIG_SYS_NS16550_IER macro Prafulla Wadaskar
2010-12-11 14:13     ` [U-Boot] [PATCH v4 3/7] add Multi Function Pin configuration support for ARMADA100 Prafulla Wadaskar
2010-12-08  2:32 ` [U-Boot] [PATCH v4 1/7] arm: Add Support for Marvell ARMADA 100 Familiy SoCs Eric Miao
2010-12-08  5:19   ` Prafulla Wadaskar
2010-12-11 14:12 ` Prafulla Wadaskar

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