[U-Boot] [PATCH V5 0/4] Add basic NVIDIA Tegra2 SoC support

[U-Boot] [PATCH V5 0/4] Add basic NVIDIA Tegra2 SoC support

[Tom Warren]

This series of patches adds preliminary/baseline support for NVIDIA's
Tegra2 SoC.  Basic CPU (AVP), RAM and UART init are covered so that the
system (Harmony or Seaboard) can boot to the U-Boot serial cmd prompt.

Further support (for Cortex-A9 CPU(s), USB, SD/MMC, etc.) to follow.

Changes for V2:
        - Coding style cleanup
        - Remove mach-types.h change; wait for ARM kernel sync-up
        - Move serial driver changes to separate patch
        - Use board/nvidia/ instead of /board/tegra
        - Remove TRUE/FALSE defines
        - Use standard NS16550 register/bit defines in UART init
        - Change nv-common.h config file to tegra2-common.h

Changes for V3:
        - Use I/O accessors for Tegra2 HW MMIO register access
        - Allow conditional compile of UARTA/UARTD code to save space

Changes for V4:
	- Use address of HW structs (&pmc, etc.) in readl/writel
	- Remove empty lines, fix mixed case hex #s & comments in header(s)
	- Move board/nvidia/common/board.c UART code & header to 
		arch/arm/cpu/armv7/tegra2/
	- Declare internal functions as static in UART code
	
Changes for V5:
	- Move arch/arm/cpu/armv7/uart.c & board.h to drivers/serial and
		rename to serial_tegra2.c
	- Remove use of uart_num & UART_A/D in serial_tegra2, simplify code

Tom Warren (4):
  arm: Tegra2: Add basic NVIDIA Tegra2 SoC support
  serial: Add Tegra2 serial port support
  arm: Tegra2: Add support for NVIDIA Harmony board
  arm: Tegra2: Add support for NVIDIA Seaboard board

 MAINTAINERS                                  |    5 +
 arch/arm/cpu/armv7/tegra2/Makefile           |   48 ++++++
 arch/arm/cpu/armv7/tegra2/board.c            |   91 ++++++++++++
 arch/arm/cpu/armv7/tegra2/config.mk          |   28 ++++
 arch/arm/cpu/armv7/tegra2/lowlevel_init.S    |   65 ++++++++
 arch/arm/cpu/armv7/tegra2/sys_info.c         |   35 +++++
 arch/arm/cpu/armv7/tegra2/timer.c            |  122 +++++++++++++++
 arch/arm/include/asm/arch-tegra2/clk_rst.h   |  154 +++++++++++++++++++
 arch/arm/include/asm/arch-tegra2/pinmux.h    |   51 +++++++
 arch/arm/include/asm/arch-tegra2/pmc.h       |  124 ++++++++++++++++
 arch/arm/include/asm/arch-tegra2/sys_proto.h |   33 ++++
 arch/arm/include/asm/arch-tegra2/tegra2.h    |   49 ++++++
 arch/arm/include/asm/arch-tegra2/uart.h      |   44 ++++++
 board/nvidia/common/board.c                  |   57 +++++++
 board/nvidia/harmony/Makefile                |   50 +++++++
 board/nvidia/seaboard/Makefile               |   50 +++++++
 boards.cfg                                   |    2 +
 common/serial.c                              |    3 +-
 drivers/serial/Makefile                      |    1 +
 drivers/serial/serial_tegra2.c               |  205 ++++++++++++++++++++++++++
 drivers/serial/serial_tegra2.h               |   49 ++++++
 include/configs/harmony.h                    |   48 ++++++
 include/configs/seaboard.h                   |   44 ++++++
 include/configs/tegra2-common.h              |  160 ++++++++++++++++++++
 include/serial.h                             |    3 +-
 25 files changed, 1519 insertions(+), 2 deletions(-)
 create mode 100644 arch/arm/cpu/armv7/tegra2/Makefile
 create mode 100644 arch/arm/cpu/armv7/tegra2/board.c
 create mode 100644 arch/arm/cpu/armv7/tegra2/config.mk
 create mode 100644 arch/arm/cpu/armv7/tegra2/lowlevel_init.S
 create mode 100644 arch/arm/cpu/armv7/tegra2/sys_info.c
 create mode 100644 arch/arm/cpu/armv7/tegra2/timer.c
 create mode 100644 arch/arm/include/asm/arch-tegra2/clk_rst.h
 create mode 100644 arch/arm/include/asm/arch-tegra2/pinmux.h
 create mode 100644 arch/arm/include/asm/arch-tegra2/pmc.h
 create mode 100644 arch/arm/include/asm/arch-tegra2/sys_proto.h
 create mode 100644 arch/arm/include/asm/arch-tegra2/tegra2.h
 create mode 100644 arch/arm/include/asm/arch-tegra2/uart.h
 create mode 100644 board/nvidia/common/board.c
 create mode 100644 board/nvidia/harmony/Makefile
 create mode 100644 board/nvidia/seaboard/Makefile
 create mode 100644 drivers/serial/serial_tegra2.c
 create mode 100644 drivers/serial/serial_tegra2.h
 create mode 100644 include/configs/harmony.h
 create mode 100644 include/configs/seaboard.h
 create mode 100644 include/configs/tegra2-common.h

-- 
1.7.3.5

[U-Boot] [PATCH V5 1/4] arm: Tegra2: Add basic NVIDIA Tegra2 SoC support

[Tom Warren]

Signed-off-by: Tom Warren <twarren@nvidia.com>
---
Changes for V2:
	- Coding style cleanup
	- Move serial driver changes to separate patch
	- Use board/nvidia instead of board/tegra
	- Remove TRUE/FALSE defines
	- Use standard NS16550 registers/bit defines in UART init

Changes for V3:
	- Use I/O accessors for Tegra2 HW MMIO register access
	- Allow conditional compile of UARTA/UARTD code to save space
		
Changes for V4:
	- Use address of HW structs (&pmc, etc.) in readl/writel
	- Remove empty lines, fix mixed case hex #s & comments in header(s)
	- Move board/nvidia/common/board.c UART code & header to 
		arch/arm/cpu/armv7/tegra2/
	- Declare internal functions as static in UART code

 arch/arm/cpu/armv7/tegra2/Makefile           |   48 ++++++
 arch/arm/cpu/armv7/tegra2/board.c            |   91 +++++++++++
 arch/arm/cpu/armv7/tegra2/board.h            |   58 +++++++
 arch/arm/cpu/armv7/tegra2/config.mk          |   28 ++++
 arch/arm/cpu/armv7/tegra2/lowlevel_init.S    |   65 ++++++++
 arch/arm/cpu/armv7/tegra2/sys_info.c         |   35 ++++
 arch/arm/cpu/armv7/tegra2/timer.c            |  122 +++++++++++++++
 arch/arm/cpu/armv7/tegra2/uart.c             |  216 ++++++++++++++++++++++++++
 arch/arm/include/asm/arch-tegra2/clk_rst.h   |  154 ++++++++++++++++++
 arch/arm/include/asm/arch-tegra2/pinmux.h    |   51 ++++++
 arch/arm/include/asm/arch-tegra2/pmc.h       |  124 +++++++++++++++
 arch/arm/include/asm/arch-tegra2/sys_proto.h |   33 ++++
 arch/arm/include/asm/arch-tegra2/tegra2.h    |   49 ++++++
 arch/arm/include/asm/arch-tegra2/uart.h      |   44 ++++++
 board/nvidia/common/board.c                  |   57 +++++++
 15 files changed, 1175 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/cpu/armv7/tegra2/Makefile
 create mode 100644 arch/arm/cpu/armv7/tegra2/board.c
 create mode 100644 arch/arm/cpu/armv7/tegra2/board.h
 create mode 100644 arch/arm/cpu/armv7/tegra2/config.mk
 create mode 100644 arch/arm/cpu/armv7/tegra2/lowlevel_init.S
 create mode 100644 arch/arm/cpu/armv7/tegra2/sys_info.c
 create mode 100644 arch/arm/cpu/armv7/tegra2/timer.c
 create mode 100644 arch/arm/cpu/armv7/tegra2/uart.c
 create mode 100644 arch/arm/include/asm/arch-tegra2/clk_rst.h
 create mode 100644 arch/arm/include/asm/arch-tegra2/pinmux.h
 create mode 100644 arch/arm/include/asm/arch-tegra2/pmc.h
 create mode 100644 arch/arm/include/asm/arch-tegra2/sys_proto.h
 create mode 100644 arch/arm/include/asm/arch-tegra2/tegra2.h
 create mode 100644 arch/arm/include/asm/arch-tegra2/uart.h
 create mode 100644 board/nvidia/common/board.c

diff --git a/arch/arm/cpu/armv7/tegra2/Makefile b/arch/arm/cpu/armv7/tegra2/Makefile
new file mode 100644
index 0000000..f5b657b
--- /dev/null
+++ b/arch/arm/cpu/armv7/tegra2/Makefile
@@ -0,0 +1,48 @@
+#
+# (C) Copyright 2010,2011 Nvidia Corporation.
+#
+# (C) Copyright 2000-2003
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	=  $(obj)lib$(SOC).o
+
+SOBJS	:= lowlevel_init.o
+COBJS	:= board.o sys_info.o timer.o uart.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS) $(SOBJS))
+
+all:	 $(obj).depend $(LIB)
+
+$(LIB):	$(OBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS)
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/arch/arm/cpu/armv7/tegra2/board.c b/arch/arm/cpu/armv7/tegra2/board.c
new file mode 100644
index 0000000..816a8cd
--- /dev/null
+++ b/arch/arm/cpu/armv7/tegra2/board.c
@@ -0,0 +1,91 @@
+/*
+ *  (C) Copyright 2010,2011
+ *  NVIDIA Corporation <www.nvidia.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/tegra2.h>
+#include "board.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Boot ROM initializes the odmdata in APBDEV_PMC_SCRATCH20_0,
+ * so we are using this value to identify memory size.
+ */
+
+unsigned int query_sdram_size(void)
+{
+	pmc_ctlr *const pmc = (pmc_ctlr *)NV_PA_PMC_BASE;
+	u32 reg;
+
+	reg = readl(&pmc->pmc_scratch20);
+	debug("pmc->pmc_scratch20 (ODMData) = 0x%08lX\n", reg);
+
+	/* bits 31:28 in OdmData are used for RAM size  */
+	switch ((reg) >> 28) {
+	case 1:
+		return 0x10000000;	/* 256 MB */
+	case 2:
+		return 0x20000000;	/* 512 MB */
+	case 3:
+	default:
+		return 0x40000000;	/* 1GB */
+	}
+}
+
+void s_init(void)
+{
+#ifndef CONFIG_ICACHE_OFF
+	icache_enable();
+#endif
+	invalidate_dcache();
+}
+
+int dram_init(void)
+{
+	unsigned long rs;
+
+	/* We do not initialise DRAM here. We just query the size */
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = gd->ram_size = query_sdram_size();
+
+	/* Now check it dynamically */
+	rs = get_ram_size(CONFIG_SYS_SDRAM_BASE, gd->ram_size);
+	if (rs) {
+		printf("dynamic ram_size = %lu\n", rs);
+		gd->bd->bi_dram[0].size = gd->ram_size = rs;
+	}
+	return 0;
+}
+
+#ifdef CONFIG_DISPLAY_BOARDINFO
+
+extern tegra2_sysinfo sysinfo;
+
+int checkboard(void)
+{
+	printf("Board: %s\n", sysinfo.board_string);
+	return 0;
+}
+#endif	/* CONFIG_DISPLAY_BOARDINFO */
diff --git a/arch/arm/cpu/armv7/tegra2/board.h b/arch/arm/cpu/armv7/tegra2/board.h
new file mode 100644
index 0000000..f8f09c0
--- /dev/null
+++ b/arch/arm/cpu/armv7/tegra2/board.h
@@ -0,0 +1,58 @@
+/*
+ *  (C) Copyright 2010,2011
+ *  NVIDIA Corporation <www.nvidia.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+#include <asm/arch/clk_rst.h>
+#include <asm/arch/pinmux.h>
+#include <asm/arch/pmc.h>
+#include <asm/arch/uart.h>
+
+#define NVRM_PLLP_FIXED_FREQ_KHZ	216000
+#define NV_DEFAULT_DEBUG_BAUD		115200
+
+#define PLL_BYPASS		(1 << 31)
+#define PLL_ENABLE		(1 << 30)
+#define PLL_BASE_OVRRIDE	(1 << 28)
+#define PLL_DIVP		(1 << 20)	/* post divider, b22:20 */
+#define PLL_DIVM		0x0C		/* input divider, b4:0 */
+
+#define SWR_UARTD_RST		(1 << 2)
+#define CLK_ENB_UARTD		(1 << 2)
+#define SWR_UARTA_RST		(1 << 6)
+#define CLK_ENB_UARTA		(1 << 6)
+
+#define Z_GMC			(1 << 29)
+#define Z_IRRX			(1 << 20)
+#define Z_IRTX			(1 << 19)
+
+enum {
+	UART_A = 1,
+	UART_B,
+	UART_C,
+	UART_D,
+	UART_E
+};
+
+#endif /* _BOARD_H_ */
diff --git a/arch/arm/cpu/armv7/tegra2/config.mk b/arch/arm/cpu/armv7/tegra2/config.mk
new file mode 100644
index 0000000..96c0795
--- /dev/null
+++ b/arch/arm/cpu/armv7/tegra2/config.mk
@@ -0,0 +1,28 @@
+#
+# (C) Copyright 2010,2011
+# NVIDIA Corporation <www.nvidia.com>
+#
+# (C) Copyright 2002
+# Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+# Use ARMv4 for Tegra2 - initial code runs on the AVP, which is an ARM7TDI.
+PLATFORM_CPPFLAGS += -march=armv4
diff --git a/arch/arm/cpu/armv7/tegra2/lowlevel_init.S b/arch/arm/cpu/armv7/tegra2/lowlevel_init.S
new file mode 100644
index 0000000..7f15746
--- /dev/null
+++ b/arch/arm/cpu/armv7/tegra2/lowlevel_init.S
@@ -0,0 +1,65 @@
+/*
+ * SoC-specific setup info
+ *
+ * (C) Copyright 2010,2011
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+
+_TEXT_BASE:
+	.word	CONFIG_SYS_TEXT_BASE	@ sdram load addr from config file
+
+.global invalidate_dcache
+invalidate_dcache:
+	mov pc, lr
+
+	.align	5
+.global reset_cpu
+reset_cpu:
+	ldr	r1, rstctl			@ get addr for global reset
+						@ reg
+	ldr	r3, [r1]
+	orr	r3, r3, #0x10
+	str	r3, [r1]			@ force reset
+	mov	r0, r0
+_loop_forever:
+	b	_loop_forever
+rstctl:
+	.word	PRM_RSTCTRL
+
+.globl lowlevel_init
+lowlevel_init:
+	ldr	sp, SRAM_STACK
+	str	ip, [sp]
+	mov	ip, lr
+	bl	s_init				@ go setup pll, mux & memory
+	ldr	ip, [sp]
+	mov	lr, ip
+
+	mov	pc, lr				@ back to arch calling code
+
+	@ the literal pools origin
+	.ltorg
+
+SRAM_STACK:
+	.word LOW_LEVEL_SRAM_STACK
diff --git a/arch/arm/cpu/armv7/tegra2/sys_info.c b/arch/arm/cpu/armv7/tegra2/sys_info.c
new file mode 100644
index 0000000..6d11dc1
--- /dev/null
+++ b/arch/arm/cpu/armv7/tegra2/sys_info.c
@@ -0,0 +1,35 @@
+/*
+ * (C) Copyright 2010,2011
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+#ifdef CONFIG_DISPLAY_CPUINFO
+/* Print CPU information */
+int print_cpuinfo(void)
+{
+	puts("TEGRA2\n");
+
+	/* TBD: Add printf of major/minor rev info, stepping, etc. */
+	return 0;
+}
+#endif	/* CONFIG_DISPLAY_CPUINFO */
diff --git a/arch/arm/cpu/armv7/tegra2/timer.c b/arch/arm/cpu/armv7/tegra2/timer.c
new file mode 100644
index 0000000..858af0f
--- /dev/null
+++ b/arch/arm/cpu/armv7/tegra2/timer.c
@@ -0,0 +1,122 @@
+/*
+ * (C) Copyright 2010,2011
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * (C) Copyright 2008
+ * Texas Instruments
+ *
+ * Richard Woodruff <r-woodruff2@ti.com>
+ * Syed Moahmmed Khasim <khasim@ti.com>
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ * Alex Zuepke <azu@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/tegra2.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static timerus_t *timer_base = (timerus_t *)NV_PA_TMRUS_BASE;
+
+/* counter runs at 1MHz */
+#define TIMER_CLK	(1000000)
+#define TIMER_LOAD_VAL	0xffffffff
+
+/* timer without interrupts */
+void reset_timer(void)
+{
+	reset_timer_masked();
+}
+
+ulong get_timer(ulong base)
+{
+	return get_timer_masked() - base;
+}
+
+void set_timer(ulong t)
+{
+	gd->tbl = t;
+}
+
+/* delay x useconds */
+void __udelay(unsigned long usec)
+{
+	long tmo = usec * (TIMER_CLK / 1000) / 1000;
+	unsigned long now, last = readl(&timer_base->cntr_1us);
+
+	while (tmo > 0) {
+		now = readl(&timer_base->cntr_1us);
+		if (last > now) /* count up timer overflow */
+			tmo -= TIMER_LOAD_VAL - last + now;
+		else
+			tmo -= now - last;
+		last = now;
+	}
+}
+
+void reset_timer_masked(void)
+{
+	/* reset time, capture current incrementer value time */
+	gd->lastinc = readl(&timer_base->cntr_1us) / (TIMER_CLK/CONFIG_SYS_HZ);
+	gd->tbl = 0;		/* start "advancing" time stamp from 0 */
+}
+
+ulong get_timer_masked(void)
+{
+	ulong now;
+
+	/* current tick value */
+	now = readl(&timer_base->cntr_1us) / (TIMER_CLK / CONFIG_SYS_HZ);
+
+	if (now >= gd->lastinc)	/* normal mode (non roll) */
+		/* move stamp forward with absolute diff ticks */
+		gd->tbl += (now - gd->lastinc);
+	else	/* we have rollover of incrementer */
+		gd->tbl += ((TIMER_LOAD_VAL / (TIMER_CLK / CONFIG_SYS_HZ))
+				- gd->lastinc) + now;
+	gd->lastinc = now;
+	return gd->tbl;
+}
+
+/*
+ * This function is derived from PowerPC code (read timebase as long long).
+ * On ARM it just returns the timer value.
+ */
+unsigned long long get_ticks(void)
+{
+	return get_timer(0);
+}
+
+/*
+ * This function is derived from PowerPC code (timebase clock frequency).
+ * On ARM it returns the number of timer ticks per second.
+ */
+ulong get_tbclk(void)
+{
+	return CONFIG_SYS_HZ;
+}
diff --git a/arch/arm/cpu/armv7/tegra2/uart.c b/arch/arm/cpu/armv7/tegra2/uart.c
new file mode 100644
index 0000000..5e60bd8
--- /dev/null
+++ b/arch/arm/cpu/armv7/tegra2/uart.c
@@ -0,0 +1,216 @@
+/*
+ *  (C) Copyright 2010,2011
+ *  NVIDIA Corporation <www.nvidia.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <ns16550.h>
+#include <asm/io.h>
+#include <asm/arch/tegra2.h>
+#include "board.h"
+
+/*
+ * Routine: uart_clock_init
+ * Description: init the PLL and clock for the UART in uart_num
+ */
+static void uart_clock_init(int uart_num)
+{
+	clk_rst_ctlr *const clkrst = (clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
+	static int pllp_init_done;
+	u32 reg;
+
+	if (!pllp_init_done) {
+		/* Override pllp setup for 216MHz operation. */
+		reg = (PLL_BYPASS | PLL_BASE_OVRRIDE | PLL_DIVP);
+		reg |= (((NVRM_PLLP_FIXED_FREQ_KHZ/500) << 8) | PLL_DIVM);
+		writel(reg, &clkrst->crc_pllp_base);
+
+		reg |= PLL_ENABLE;
+		writel(reg, &clkrst->crc_pllp_base);
+
+		reg &= ~PLL_BYPASS;
+		writel(reg, &clkrst->crc_pllp_base);
+
+		pllp_init_done++;
+	}
+
+	/* Now do the UART reset/clock enable based on uart_num */
+#if CONFIG_TEGRA2_ENABLE_UARTA
+	if (uart_num == UART_A) {
+		/* Assert Reset to UART */
+		reg = readl(&clkrst->crc_rst_dev_l);
+		reg |= SWR_UARTA_RST;		/* SWR_UARTA_RST = 1 */
+		writel(reg, &clkrst->crc_rst_dev_l);
+
+		/* Enable clk to UART */
+		reg = readl(&clkrst->crc_clk_out_enb_l);
+		reg |= CLK_ENB_UARTA;		/* CLK_ENB_UARTA = 1 */
+		writel(reg, &clkrst->crc_clk_out_enb_l);
+
+		/* Enable pllp_out0 to UART */
+		reg = readl(&clkrst->crc_clk_src_uarta);
+		reg &= 0x3FFFFFFF;	/* UARTA_CLK_SRC = 00, PLLP_OUT0 */
+		writel(reg, &clkrst->crc_clk_src_uarta);
+
+		/* wait for 2us */
+		udelay(2);
+
+		/* De-assert reset to UART */
+		reg = readl(&clkrst->crc_rst_dev_l);
+		reg &= ~SWR_UARTA_RST;		/* SWR_UARTA_RST = 0 */
+		writel(reg, &clkrst->crc_rst_dev_l);
+	}
+#endif	/* CONFIG_TEGRA2_ENABLE_UARTA */
+#if CONFIG_TEGRA2_ENABLE_UARTD
+	if (uart_num == UART_D) {
+		/* Assert Reset to UART */
+		reg = readl(&clkrst->crc_rst_dev_u);
+		reg |= SWR_UARTD_RST;		/* SWR_UARTD_RST = 1 */
+		writel(reg, &clkrst->crc_rst_dev_u);
+
+		/* Enable clk to UART */
+		reg = readl(&clkrst->crc_clk_out_enb_u);
+		reg |= CLK_ENB_UARTD;		/* CLK_ENB_UARTD = 1 */
+		writel(reg, &clkrst->crc_clk_out_enb_u);
+
+		/* Enable pllp_out0 to UART */
+		reg = readl(&clkrst->crc_clk_src_uartd);
+		reg &= 0x3FFFFFFF;	/* UARTD_CLK_SRC = 00, PLLP_OUT0 */
+		writel(reg, &clkrst->crc_clk_src_uartd);
+
+		/* wait for 2us */
+		udelay(2);
+
+		/* De-assert reset to UART */
+		reg = readl(&clkrst->crc_rst_dev_u);
+		reg &= ~SWR_UARTD_RST;		/* SWR_UARTD_RST = 0 */
+		writel(reg, &clkrst->crc_rst_dev_u);
+	}
+#endif	/* CONFIG_TEGRA2_ENABLE_UARTD */
+}
+
+/*
+ * Routine: pin_mux_uart
+ * Description: setup the pin muxes/tristate values for UART based on uart_num
+ */
+static void pin_mux_uart(int uart_num)
+{
+	pinmux_tri_ctlr *const pmt = (pinmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
+	u32 reg;
+
+#if CONFIG_TEGRA2_ENABLE_UARTA
+	if (uart_num  == UART_A) {
+		reg = readl(&pmt->pmt_ctl_c);
+		reg &= 0xFFF0FFFF;	/* IRRX_/IRTX_SEL [19:16] = 00 UARTA */
+		writel(reg, &pmt->pmt_ctl_c);
+
+		reg = readl(&pmt->pmt_tri_a);
+		reg &= ~Z_IRRX;		/* Z_IRRX = normal (0) */
+		reg &= ~Z_IRTX;		/* Z_IRTX = normal (0) */
+		writel(reg, &pmt->pmt_tri_a);
+	}
+#endif	/* CONFIG_TEGRA2_ENABLE_UARTA */
+#if CONFIG_TEGRA2_ENABLE_UARTD
+	if (uart_num == UART_D) {
+		reg = readl(&pmt->pmt_ctl_b);
+		reg &= 0xFFFFFFF3;	/* GMC_SEL [3:2] = 00, UARTD */
+		writel(reg, &pmt->pmt_ctl_b);
+
+		reg = readl(&pmt->pmt_tri_a);
+		reg &= ~Z_GMC;		/* Z_GMC = normal (0) */
+		writel(reg, &pmt->pmt_tri_a);
+	}
+#endif	/* CONFIG_TEGRA2_ENABLE_UARTD */
+}
+
+static void setup_uart(uart_ctlr *u)
+{
+	u32 reg;
+
+	/* Prepare the divisor value */
+	reg = NVRM_PLLP_FIXED_FREQ_KHZ * 1000 / NV_DEFAULT_DEBUG_BAUD / 16;
+
+	/* Set up UART parameters */
+	writel(UART_LCR_DLAB, &u->uart_lcr);
+	writel(reg, &u->uart_thr_dlab_0);
+	writel(0, &u->uart_ier_dlab_0);
+	writel(0, &u->uart_lcr);			/* clear DLAB */
+	writel((UART_FCR_TRIGGER_3 | UART_FCR_FIFO_EN | \
+		UART_FCR_CLEAR_XMIT | UART_FCR_CLEAR_RCVR), &u->uart_iir_fcr);
+	writel(0, &u->uart_ier_dlab_0);
+	writel(UART_LCR_WLS_8, &u->uart_lcr);	/* 8N1 */
+	writel(UART_MCR_RTS, &u->uart_mcr);
+	writel(0, &u->uart_msr);
+	writel(0, &u->uart_spr);
+	writel(0, &u->uart_irda_csr);
+	writel(0, &u->uart_asr);
+	writel((UART_FCR_TRIGGER_3 | UART_FCR_FIFO_EN), &u->uart_iir_fcr);
+
+	/* Flush any old characters out of the RX FIFO */
+	reg = readl(&u->uart_lsr);
+
+	while (reg & UART_LSR_DR) {
+		reg = readl(&u->uart_thr_dlab_0);
+		reg = readl(&u->uart_lsr);
+	}
+}
+
+/*
+ * Routine: init_uart
+ * Description: init the UART clocks, muxes, and baudrate/parity/etc.
+ */
+static void init_uart(int uart_num)
+{
+#if CONFIG_TEGRA2_ENABLE_UARTA
+	if (uart_num == UART_A) {
+		uart_ctlr *const uart = (uart_ctlr *)NV_PA_APB_UARTA_BASE;
+
+		uart_clock_init(UART_A);
+
+		/* Enable UARTA - uses config 0 */
+		pin_mux_uart(UART_A);
+
+		setup_uart(uart);
+	}
+#endif	/* CONFIG_TEGRA2_ENABLE_UARTD */
+#if CONFIG_TEGRA2_ENABLE_UARTD
+	if (uart_num == UART_D) {
+		uart_ctlr *const uart = (uart_ctlr *)NV_PA_APB_UARTD_BASE;
+
+		uart_clock_init(UART_D);
+
+		/* Enable UARTD - uses config 0 */
+		pin_mux_uart(UART_D);
+
+		setup_uart(uart);
+	}
+#endif	/* CONFIG_TEGRA2_ENABLE_UARTD */
+}
+
+void uart_init(void)
+{
+#if (CONFIG_TEGRA2_ENABLE_UARTA)
+	init_uart(UART_A);
+#endif
+#if (CONFIG_TEGRA2_ENABLE_UARTD)
+	init_uart(UART_D);
+#endif
+}
diff --git a/arch/arm/include/asm/arch-tegra2/clk_rst.h b/arch/arm/include/asm/arch-tegra2/clk_rst.h
new file mode 100644
index 0000000..c5eb5b8
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra2/clk_rst.h
@@ -0,0 +1,154 @@
+/*
+ *  (C) Copyright 2010,2011
+ *  NVIDIA Corporation <www.nvidia.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _CLK_RST_H_
+#define _CLK_RST_H_
+
+/* Clock/Reset Controller (CLK_RST_CONTROLLER_) regs */
+typedef volatile struct clk_rst_ctlr {
+	uint crc_rst_src;		/* _RST_SOURCE_0,	0x00 */
+	uint crc_rst_dev_l;		/* _RST_DEVICES_L_0,	0x04 */
+	uint crc_rst_dev_h;		/* _RST_DEVICES_H_0,	0x08 */
+	uint crc_rst_dev_u;		/* _RST_DEVICES_U_0,	0x0C */
+	uint crc_clk_out_enb_l;		/* _CLK_OUT_ENB_L_0,	0x10 */
+	uint crc_clk_out_enb_h;		/* _CLK_OUT_ENB_H_0,	0x14 */
+	uint crc_clk_out_enb_u;		/* _CLK_OUT_ENB_U_0,	0x18 */
+	uint crc_reserved0;		/* reserved_0,		0x1C */
+	uint crc_cclk_brst_pol;		/* _CCLK_BURST_POLICY_0,0x20 */
+	uint crc_super_cclk_div;	/* _SUPER_CCLK_DIVIDER_0,0x24 */
+	uint crc_sclk_brst_pol;		/* _SCLK_BURST_POLICY_0, 0x28 */
+	uint crc_super_sclk_div;	/* _SUPER_SCLK_DIVIDER_0,0x2C */
+	uint crc_clk_sys_rate;		/* _CLK_SYSTEM_RATE_0,	0x30 */
+	uint crc_prog_dly_clk;		/* _PROG_DLY_CLK_0,	0x34 */
+	uint crc_aud_sync_clk_rate;	/* _AUDIO_SYNC_CLK_RATE_0,0x38 */
+	uint crc_reserved1;		/* reserved_1,		0x3C */
+	uint crc_cop_clk_skip_plcy;	/* _COP_CLK_SKIP_POLICY_0,0x40 */
+	uint crc_clk_mask_arm;		/* _CLK_MASK_ARM_0,	0x44 */
+	uint crc_misc_clk_enb;		/* _MISC_CLK_ENB_0,	0x48 */
+	uint crc_clk_cpu_cmplx;		/* _CLK_CPU_CMPLX_0,	0x4C */
+	uint crc_osc_ctrl;		/* _OSC_CTRL_0,		0x50 */
+	uint crc_pll_lfsr;		/* _PLL_LFSR_0,		0x54 */
+	uint crc_osc_freq_det;		/* _OSC_FREQ_DET_0,	0x58 */
+	uint crc_osc_freq_det_stat;	/* _OSC_FREQ_DET_STATUS_0,0x5C */
+	uint crc_reserved2[8];		/* reserved_2[8],	0x60-7C */
+
+	uint crc_pllc_base;		/* _PLLC_BASE_0,	0x80 */
+	uint crc_pllc_out;		/* _PLLC_OUT_0,		0x84 */
+	uint crc_reserved3;		/* reserved_3,		0x88 */
+	uint crc_pllc_misc;		/* _PLLC_MISC_0,	0x8C */
+
+	uint crc_pllm_base;		/* _PLLM_BASE_0,	0x90 */
+	uint crc_pllm_out;		/* _PLLM_OUT_0,		0x94 */
+	uint crc_reserved4;		/* reserved_4,		0x98 */
+	uint crc_pllm_misc;		/* _PLLM_MISC_0,	0x9C */
+
+	uint crc_pllp_base;		/* _PLLP_BASE_0,	0xA0 */
+	uint crc_pllp_outa;		/* _PLLP_OUTA_0,	0xA4 */
+	uint crc_pllp_outb;		/* _PLLP_OUTB_0,	0xA8 */
+	uint crc_pllp_misc;		/* _PLLP_MISC_0,	0xAC */
+
+	uint crc_plla_base;		/* _PLLA_BASE_0,	0xB0 */
+	uint crc_plla_out;		/* _PLLA_OUT_0,		0xB4 */
+	uint crc_reserved5;		/* reserved_5,		0xB8 */
+	uint crc_plla_misc;		/* _PLLA_MISC_0,	0xBC */
+
+	uint crc_pllu_base;		/* _PLLU_BASE_0,	0xC0 */
+	uint crc_reserved6;		/* _reserved_6,		0xC4 */
+	uint crc_reserved7;		/* _reserved_7,		0xC8 */
+	uint crc_pllu_misc;		/* _PLLU_MISC_0,	0xCC */
+
+	uint crc_plld_base;		/* _PLLD_BASE_0,	0xD0 */
+	uint crc_reserved8;		/* _reserved_8,		0xD4 */
+	uint crc_reserved9;		/* _reserved_9,		0xD8 */
+	uint crc_plld_misc;		/* _PLLD_MISC_0,	0xDC */
+
+	uint crc_pllx_base;		/* _PLLX_BASE_0,	0xE0 */
+	uint crc_pllx_misc;		/* _PLLX_MISC_0,	0xE4 */
+
+	uint crc_plle_base;		/* _PLLE_BASE_0,	0xE8 */
+	uint crc_plle_misc;		/* _PLLE_MISC_0,	0xEC */
+
+	uint crc_plls_base;		/* _PLLS_BASE_0,	0xF0 */
+	uint crc_plls_misc;		/* _PLLS_MISC_0,	0xF4 */
+	uint crc_reserved10;		/* _reserved_10,	0xF8 */
+	uint crc_reserved11;		/* _reserved_11,	0xFC */
+
+	uint crc_clk_src_i2s1;		/*_I2S1_0,		0x100 */
+	uint crc_clk_src_i2s2;		/*_I2S2_0,		0x104 */
+	uint crc_clk_src_spdif_out;	/*_SPDIF_OUT_0,		0x108 */
+	uint crc_clk_src_spdif_in;	/*_SPDIF_IN_0,		0x10C */
+	uint crc_clk_src_pwm;		/*_PWM_0,		0x110 */
+	uint crc_clk_src_spi1;		/*_SPI1_0,		0x114 */
+	uint crc_clk_src_sbc2;		/*_SBC2_0,		0x118 */
+	uint crc_clk_src_sbc3;		/*_SBC3_0,		0x11C */
+	uint crc_clk_src_xio;		/*_XIO_0,		0x120 */
+	uint crc_clk_src_i2c1;		/*_I2C1_0,		0x124 */
+	uint crc_clk_src_dvc_i2c;	/*_DVC_I2C_0,		0x128 */
+	uint crc_clk_src_twc;		/*_TWC_0,		0x12C */
+	uint crc_reserved12;		/*			0x130 */
+	uint crc_clk_src_sbc1;		/*_SBC1_0,		0x134 */
+	uint crc_clk_src_disp1;		/*_DISP1_0,		0x138 */
+	uint crc_clk_src_disp2;		/*_DISP2_0,		0x13C */
+	uint crc_clk_src_cve;		/*_CVE_0,		0x140 */
+	uint crc_clk_src_ide;		/*_IDE_0,		0x144 */
+	uint crc_clk_src_vi;		/*_VI_0,		0x148 */
+	uint crc_reserved13;		/*			0x14C */
+	uint crc_clk_src_sdmmc1;	/*_SDMMC1_0,		0x150 */
+	uint crc_clk_src_sdmmc2;	/*_SDMMC2_0,		0x154 */
+	uint crc_clk_src_g3d;		/*_G3D_0,		0x158 */
+	uint crc_clk_src_g2d;		/*_G2D_0,		0x15C */
+	uint crc_clk_src_ndflash;	/*_NDFLASH_0,		0x160 */
+	uint crc_clk_src_sdmmc4;	/*_SDMMC4_0,		0x164 */
+	uint crc_clk_src_vfir;		/*_VFIR_0,		0x168 */
+	uint crc_clk_src_epp;		/*_EPP_0,		0x16C */
+	uint crc_clk_src_mp3;		/*_MPE_0,		0x170 */
+	uint crc_clk_src_mipi;		/*_MIPI_0,		0x174 */
+	uint crc_clk_src_uarta;		/*_UARTA_0,		0x178 */
+	uint crc_clk_src_uartb;		/*_UARTB_0,		0x17C */
+	uint crc_clk_src_host1x;	/*_HOST1X_0,		0x180 */
+	uint crc_reserved14;		/*			0x184 */
+	uint crc_clk_src_tvo;		/*_TVO_0,		0x188 */
+	uint crc_clk_src_hdmi;		/*_HDMI_0,		0x18C */
+	uint crc_reserved15;		/*			0x190 */
+	uint crc_clk_src_tvdac;		/*_TVDAC_0,		0x194 */
+	uint crc_clk_src_i2c2;		/*_I2C2_0,		0x198 */
+	uint crc_clk_src_emc;		/*_EMC_0,		0x19C */
+	uint crc_clk_src_uartc;		/*_UARTC_0,		0x1A0 */
+	uint crc_reserved16;		/*			0x1A4 */
+	uint crc_clk_src_vi_sensor;	/*_VI_SENSOR_0,		0x1A8 */
+	uint crc_reserved17;		/*			0x1AC */
+	uint crc_reserved18;		/*			0x1B0 */
+	uint crc_clk_src_sbc4;		/*_SBC4_0,		0x1B4 */
+	uint crc_clk_src_i2c3;		/*_I2C3_0,		0x1B8 */
+	uint crc_clk_src_sdmmc3;	/*_SDMMC3_0,		0x1BC */
+	uint crc_clk_src_uartd;		/*_UARTD_0,		0x1C0 */
+	uint crc_clk_src_uarte;		/*_UARTE_0,		0x1C4 */
+	uint crc_clk_src_vde;		/*_VDE_0,		0x1C8 */
+	uint crc_clk_src_owr;		/*_OWR_0,		0x1CC */
+	uint crc_clk_src_nor;		/*_NOR_0,		0x1D0 */
+	uint crc_clk_src_csite;		/*_CSITE_0,		0x1D4 */
+	uint crc_reserved19[9];		/*			0x1D8-1F8 */
+	uint crc_clk_src_osc;		/*_OSC_0,		0x1FC */
+} clk_rst_ctlr;
+
+#endif	/* CLK_RST_H */
diff --git a/arch/arm/include/asm/arch-tegra2/pinmux.h b/arch/arm/include/asm/arch-tegra2/pinmux.h
new file mode 100644
index 0000000..2730be3
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra2/pinmux.h
@@ -0,0 +1,51 @@
+/*
+ *  (C) Copyright 2010,2011
+ *  NVIDIA Corporation <www.nvidia.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _PINMUX_H_
+#define _PINMUX_H_
+
+/* APB MISC Pin Mux and Tristate (APB_MISC_PP_) registers */
+typedef volatile struct pinmux_tri_ctlr {
+	uint pmt_reserved0;		/* ABP_MISC_PP_ reserved offset 00 */
+	uint pmt_reserved1;		/* ABP_MISC_PP_ reserved offset 04 */
+	uint pmt_strap_opt_a;		/* _STRAPPING_OPT_A_0, offset 08 */
+	uint pmt_reserved2;		/* ABP_MISC_PP_ reserved offset 0C */
+	uint pmt_reserved3;		/* ABP_MISC_PP_ reserved offset 10 */
+	uint pmt_tri_a;			/* _TRI_STATE_REG_A_0, offset 14 */
+	uint pmt_tri_b;			/* _TRI_STATE_REG_B_0, offset 18 */
+	uint pmt_tri_c;			/* _TRI_STATE_REG_C_0, offset 1C */
+	uint pmt_tri_d;			/* _TRI_STATE_REG_D_0, offset 20 */
+	uint pmt_cfg_ctl;		/* _CONFIG_CTL_0, offset 24 */
+
+	uint pmt_reserved[22];		/* ABP_MISC_PP_ reserved offs 28-7C */
+
+	uint pmt_ctl_a;			/* _PIN_MUX_CTL_A_0, offset 80 */
+	uint pmt_ctl_b;			/* _PIN_MUX_CTL_B_0, offset 84 */
+	uint pmt_ctl_c;			/* _PIN_MUX_CTL_C_0, offset 88 */
+	uint pmt_ctl_d;			/* _PIN_MUX_CTL_D_0, offset 8C */
+	uint pmt_ctl_e;			/* _PIN_MUX_CTL_E_0, offset 90 */
+	uint pmt_ctl_f;			/* _PIN_MUX_CTL_F_0, offset 94 */
+	uint pmt_ctl_g;			/* _PIN_MUX_CTL_G_0, offset 98 */
+} pinmux_tri_ctlr;
+
+#endif	/* PINMUX_H */
diff --git a/arch/arm/include/asm/arch-tegra2/pmc.h b/arch/arm/include/asm/arch-tegra2/pmc.h
new file mode 100644
index 0000000..4fbdb3d
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra2/pmc.h
@@ -0,0 +1,124 @@
+/*
+ *  (C) Copyright 2010,2011
+ *  NVIDIA Corporation <www.nvidia.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _PMC_H_
+#define _PMC_H_
+
+/* Power Management Controller (APBDEV_PMC_) registers */
+typedef volatile struct pmc_ctlr {
+	uint pmc_cntrl;			/* _CNTRL_0, offset 00 */
+	uint pmc_sec_disable;		/* _SEC_DISABLE_0, offset 04 */
+	uint pmc_pmc_swrst;		/* _PMC_SWRST_0, offset 08 */
+	uint pmc_wake_mask;		/* _WAKE_MASK_0, offset 0C */
+	uint pmc_wake_lvl;		/* _WAKE_LVL_0, offset 10 */
+	uint pmc_wake_status;		/* _WAKE_STATUS_0, offset 14 */
+	uint pmc_sw_wake_status;	/* _SW_WAKE_STATUS_0, offset 18 */
+	uint pmc_dpd_pads_oride;	/* _DPD_PADS_ORIDE_0, offset 1C */
+	uint pmc_dpd_sample;		/* _DPD_PADS_SAMPLE_0, offset 20 */
+	uint pmc_dpd_enable;		/* _DPD_PADS_ENABLE_0, offset 24 */
+	uint pmc_pwrgate_timer_off;	/* _PWRGATE_TIMER_OFF_0, offset 28 */
+	uint pmc_pwrgate_timer_on;	/* _PWRGATE_TIMER_ON_0, offset 2C */
+	uint pmc_pwrgate_toggle;	/* _PWRGATE_TOGGLE_0, offset 30 */
+	uint pmc_remove_clamping;	/* _REMOVE_CLAMPING_CMD_0, offset 34 */
+	uint pmc_pwrgate_status;	/* _PWRGATE_STATUS_0, offset 38 */
+	uint pmc_pwrgood_timer;		/* _PWRGOOD_TIMER_0, offset 3C */
+	uint pmc_blink_timer;		/* _BLINK_TIMER_0, offset 40 */
+	uint pmc_no_iopower;		/* _NO_IOPOWER_0, offset 44 */
+	uint pmc_pwr_det;		/* _PWR_DET_0, offset 48 */
+	uint pmc_pwr_det_latch;		/* _PWR_DET_LATCH_0, offset 4C */
+
+	uint pmc_scratch0;		/* _SCRATCH0_0, offset 50 */
+	uint pmc_scratch1;		/* _SCRATCH1_0, offset 54 */
+	uint pmc_scratch2;		/* _SCRATCH2_0, offset 58 */
+	uint pmc_scratch3;		/* _SCRATCH3_0, offset 5C */
+	uint pmc_scratch4;		/* _SCRATCH4_0, offset 60 */
+	uint pmc_scratch5;		/* _SCRATCH5_0, offset 64 */
+	uint pmc_scratch6;		/* _SCRATCH6_0, offset 68 */
+	uint pmc_scratch7;		/* _SCRATCH7_0, offset 6C */
+	uint pmc_scratch8;		/* _SCRATCH8_0, offset 70 */
+	uint pmc_scratch9;		/* _SCRATCH9_0, offset 74 */
+	uint pmc_scratch10;		/* _SCRATCH10_0, offset 78 */
+	uint pmc_scratch11;		/* _SCRATCH11_0, offset 7C */
+	uint pmc_scratch12;		/* _SCRATCH12_0, offset 80 */
+	uint pmc_scratch13;		/* _SCRATCH13_0, offset 84 */
+	uint pmc_scratch14;		/* _SCRATCH14_0, offset 88 */
+	uint pmc_scratch15;		/* _SCRATCH15_0, offset 8C */
+	uint pmc_scratch16;		/* _SCRATCH16_0, offset 90 */
+	uint pmc_scratch17;		/* _SCRATCH17_0, offset 94 */
+	uint pmc_scratch18;		/* _SCRATCH18_0, offset 98 */
+	uint pmc_scratch19;		/* _SCRATCH19_0, offset 9C */
+	uint pmc_scratch20;		/* _SCRATCH20_0, offset A0 */
+	uint pmc_scratch21;		/* _SCRATCH21_0, offset A4 */
+	uint pmc_scratch22;		/* _SCRATCH22_0, offset A8 */
+	uint pmc_scratch23;		/* _SCRATCH23_0, offset AC */
+
+	uint pmc_secure_scratch0;	/* _SECURE_SCRATCH0_0, offset B0 */
+	uint pmc_secure_scratch1;	/* _SECURE_SCRATCH1_0, offset B4 */
+	uint pmc_secure_scratch2;	/* _SECURE_SCRATCH2_0, offset B8 */
+	uint pmc_secure_scratch3;	/* _SECURE_SCRATCH3_0, offset BC */
+	uint pmc_secure_scratch4;	/* _SECURE_SCRATCH4_0, offset C0 */
+	uint pmc_secure_scratch5;	/* _SECURE_SCRATCH5_0, offset C4 */
+
+	uint pmc_cpupwrgood_timer;	/* _CPUPWRGOOD_TIMER_0, offset C8 */
+	uint pmc_cpupwroff_timer;	/* _CPUPWROFF_TIMER_0, offset CC */
+	uint pmc_pg_mask;		/* _PG_MASK_0, offset D0 */
+	uint pmc_pg_mask_1;		/* _PG_MASK_1_0, offset D4 */
+	uint pmc_auto_wake_lvl;		/* _AUTO_WAKE_LVL_0, offset D8 */
+	uint pmc_auto_wake_lvl_mask;	/* _AUTO_WAKE_LVL_MASK_0, offset DC */
+	uint pmc_wake_delay;		/* _WAKE_DELAY_0, offset E0 */
+	uint pmc_pwr_det_val;		/* _PWR_DET_VAL_0, offset E4 */
+	uint pmc_ddr_pwr;		/* _DDR_PWR_0, offset E8 */
+	uint pmc_usb_debounce_del;	/* _USB_DEBOUNCE_DEL_0, offset EC */
+	uint pmc_usb_ao;		/* _USB_AO_0, offset F0 */
+	uint pmc_crypto_op;		/* _CRYPTO_OP__0, offset F4 */
+	uint pmc_pllp_wb0_override;	/* _PLLP_WB0_OVERRIDE_0, offset F8 */
+
+	uint pmc_scratch24;		/* _SCRATCH24_0, offset FC */
+	uint pmc_scratch25;		/* _SCRATCH24_0, offset 100 */
+	uint pmc_scratch26;		/* _SCRATCH24_0, offset 104 */
+	uint pmc_scratch27;		/* _SCRATCH24_0, offset 108 */
+	uint pmc_scratch28;		/* _SCRATCH24_0, offset 10C */
+	uint pmc_scratch29;		/* _SCRATCH24_0, offset 110 */
+	uint pmc_scratch30;		/* _SCRATCH24_0, offset 114 */
+	uint pmc_scratch31;		/* _SCRATCH24_0, offset 118 */
+	uint pmc_scratch32;		/* _SCRATCH24_0, offset 11C */
+	uint pmc_scratch33;		/* _SCRATCH24_0, offset 120 */
+	uint pmc_scratch34;		/* _SCRATCH24_0, offset 124 */
+	uint pmc_scratch35;		/* _SCRATCH24_0, offset 128 */
+	uint pmc_scratch36;		/* _SCRATCH24_0, offset 12C */
+	uint pmc_scratch37;		/* _SCRATCH24_0, offset 130 */
+	uint pmc_scratch38;		/* _SCRATCH24_0, offset 134 */
+	uint pmc_scratch39;		/* _SCRATCH24_0, offset 138 */
+	uint pmc_scratch40;		/* _SCRATCH24_0, offset 13C */
+	uint pmc_scratch41;		/* _SCRATCH24_0, offset 140 */
+	uint pmc_scratch42;		/* _SCRATCH24_0, offset 144 */
+
+	uint pmc_bo_mirror0;		/* _BOUNDOUT_MIRROR0_0, offset 148 */
+	uint pmc_bo_mirror1;		/* _BOUNDOUT_MIRROR1_0, offset 14C */
+	uint pmc_bo_mirror2;		/* _BOUNDOUT_MIRROR2_0, offset 150 */
+	uint pmc_sys_33v_en;		/* _SYS_33V_EN_0, offset 154 */
+	uint pmc_bo_mirror_access;	/* _BOUNDOUT_MIRROR_ACCESS_0, off158 */
+	uint pmc_gate;			/* _GATE_0, offset 15C */
+} pmc_ctlr;
+
+#endif	/* PMC_H */
diff --git a/arch/arm/include/asm/arch-tegra2/sys_proto.h b/arch/arm/include/asm/arch-tegra2/sys_proto.h
new file mode 100644
index 0000000..70e63a8
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra2/sys_proto.h
@@ -0,0 +1,33 @@
+/*
+ * (C) Copyright 2010,2011
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _SYS_PROTO_H_
+#define _SYS_PROTO_H_
+
+typedef struct {
+	char *board_string;
+} tegra2_sysinfo;
+
+void invalidate_dcache(void);
+
+#endif
diff --git a/arch/arm/include/asm/arch-tegra2/tegra2.h b/arch/arm/include/asm/arch-tegra2/tegra2.h
new file mode 100644
index 0000000..3bd0212
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra2/tegra2.h
@@ -0,0 +1,49 @@
+/*
+ * (C) Copyright 2010,2011
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _TEGRA2_H_
+#define _TEGRA2_H_
+
+#define NV_PA_SDRAM_BASE	0x00000000
+#define NV_PA_TMRUS_BASE	0x60005010
+#define NV_PA_CLK_RST_BASE	0x60006000
+#define NV_PA_APB_MISC_BASE	0x70000000
+#define NV_PA_APB_UARTA_BASE	(NV_PA_APB_MISC_BASE + 0x6000)
+#define NV_PA_APB_UARTB_BASE	(NV_PA_APB_MISC_BASE + 0x6040)
+#define NV_PA_APB_UARTC_BASE	(NV_PA_APB_MISC_BASE + 0x6200)
+#define NV_PA_APB_UARTD_BASE	(NV_PA_APB_MISC_BASE + 0x6300)
+#define NV_PA_APB_UARTE_BASE	(NV_PA_APB_MISC_BASE + 0x6400)
+#define NV_PA_PMC_BASE		0x7000E400
+
+#define TEGRA2_SDRC_CS0		NV_PA_SDRAM_BASE
+#define LOW_LEVEL_SRAM_STACK	0x4000FFFC
+
+#ifndef __ASSEMBLY__
+typedef volatile struct timerus {
+	unsigned int cntr_1us;
+} timerus_t;
+#else  /* __ASSEMBLY__ */
+#define PRM_RSTCTRL		NV_PA_PMC_BASE
+#endif
+
+#endif	/* TEGRA2_H */
diff --git a/arch/arm/include/asm/arch-tegra2/uart.h b/arch/arm/include/asm/arch-tegra2/uart.h
new file mode 100644
index 0000000..702f9b4
--- /dev/null
+++ b/arch/arm/include/asm/arch-tegra2/uart.h
@@ -0,0 +1,44 @@
+/*
+ *  (C) Copyright 2010,2011
+ *  NVIDIA Corporation <www.nvidia.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _UART_H_
+#define _UART_H_
+
+/* UART registers */
+typedef volatile struct uart_ctlr {
+	uint uart_thr_dlab_0;		/* UART_THR_DLAB_0_0, offset 00 */
+	uint uart_ier_dlab_0;		/* UART_IER_DLAB_0_0, offset 04 */
+	uint uart_iir_fcr;		/* UART_IIR_FCR_0, offset 08 */
+	uint uart_lcr;			/* UART_LCR_0, offset 0C */
+	uint uart_mcr;			/* UART_MCR_0, offset 10 */
+	uint uart_lsr;			/* UART_LSR_0, offset 14 */
+	uint uart_msr;			/* UART_MSR_0, offset 18 */
+	uint uart_spr;			/* UART_SPR_0, offset 1C */
+	uint uart_irda_csr;		/* UART_IRDA_CSR_0, offset 20 */
+	uint uart_reserved[6];		/* Reserved, unused, offset 24-38*/
+	uint uart_asr;			/* UART_ASR_0, offset 3C */
+} uart_ctlr;
+
+#define UART_FCR_TRIGGER_3	0x30	/* Mask for trigger set at 3 */
+
+#endif	/* UART_H */
diff --git a/board/nvidia/common/board.c b/board/nvidia/common/board.c
new file mode 100644
index 0000000..defc359
--- /dev/null
+++ b/board/nvidia/common/board.c
@@ -0,0 +1,57 @@
+/*
+ *  (C) Copyright 2010,2011
+ *  NVIDIA Corporation <www.nvidia.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <ns16550.h>
+#include <asm/arch/tegra2.h>
+#include <asm/arch/sys_proto.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+const tegra2_sysinfo sysinfo = {
+	CONFIG_TEGRA2_BOARD_STRING
+};
+
+/*
+ * Routine: board_init
+ * Description: Early hardware init.
+ */
+int board_init(void)
+{
+	/* boot param addr */
+	gd->bd->bi_boot_params = (NV_PA_SDRAM_BASE + 0x100);
+	/* board id for Linux */
+	gd->bd->bi_arch_number = CONFIG_MACH_TYPE;
+
+	return 0;
+}
+
+/*
+ * Routine: timer_init
+ * Description: init the timestamp and lastinc value
+ */
+int timer_init(void)
+{
+	reset_timer();
+	return 0;
+}
-- 
1.7.3.5

[U-Boot] [PATCH V5 1/4] arm: Tegra2: Add basic NVIDIA Tegra2 SoC support

[Wolfgang Denk]

Dear Tom Warren,

In message <1295651217-32421-2-git-send-email-twarren@nvidia.com> you wrote:
> Signed-off-by: Tom Warren <twarren@nvidia.com>
>...
...
> +/* Clock/Reset Controller (CLK_RST_CONTROLLER_) regs */
> +typedef volatile struct clk_rst_ctlr {
...
> +/* APB MISC Pin Mux and Tristate (APB_MISC_PP_) registers */
> +typedef volatile struct pinmux_tri_ctlr {
...
> +/* Power Management Controller (APBDEV_PMC_) registers */
> +typedef volatile struct pmc_ctlr {
...
> +#ifndef __ASSEMBLY__
> +typedef volatile struct timerus {
> +	unsigned int cntr_1us;
> +} timerus_t;
...
> +/* UART registers */
> +typedef volatile struct uart_ctlr {

Please drop the "typedef" and the "volatile" from all these (and all
other, similar) declarations.

See linux/Documentation/CodingStyle:

	It's a _mistake_ to use typedef for structures and pointers.

See Documentation/volatile-considered-harmful.txt

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
I am a computer. I am dumber than any human and smarter than any  ad-
ministrator.

[U-Boot] [PATCH V5 2/4] serial: Add Tegra2 serial port support

[Tom Warren]

Signed-off-by: Tom Warren <twarren@nvidia.com>
---
Changes for V2:
	- Move serial driver to separate patch

Changes for V5:
	- Move arch/arm/cpu/armv7/uart.c & board.h to drivers/serial and
		rename to serial_tegra2.c
	- Remove use of uart_num & UART_A/D in serial_tegra2, simplify code

 arch/arm/cpu/armv7/tegra2/Makefile |    2 +-
 arch/arm/cpu/armv7/tegra2/board.c  |    2 +-
 arch/arm/cpu/armv7/tegra2/board.h  |   58 ----------
 arch/arm/cpu/armv7/tegra2/uart.c   |  216 ------------------------------------
 common/serial.c                    |    3 +-
 drivers/serial/Makefile            |    1 +
 drivers/serial/serial_tegra2.c     |  205 ++++++++++++++++++++++++++++++++++
 drivers/serial/serial_tegra2.h     |   49 ++++++++
 include/serial.h                   |    3 +-
 9 files changed, 261 insertions(+), 278 deletions(-)
 delete mode 100644 arch/arm/cpu/armv7/tegra2/board.h
 delete mode 100644 arch/arm/cpu/armv7/tegra2/uart.c
 create mode 100644 drivers/serial/serial_tegra2.c
 create mode 100644 drivers/serial/serial_tegra2.h

diff --git a/arch/arm/cpu/armv7/tegra2/Makefile b/arch/arm/cpu/armv7/tegra2/Makefile
index f5b657b..687c887 100644
--- a/arch/arm/cpu/armv7/tegra2/Makefile
+++ b/arch/arm/cpu/armv7/tegra2/Makefile
@@ -28,7 +28,7 @@ include $(TOPDIR)/config.mk
 LIB	=  $(obj)lib$(SOC).o
 
 SOBJS	:= lowlevel_init.o
-COBJS	:= board.o sys_info.o timer.o uart.o
+COBJS	:= board.o sys_info.o timer.o
 
 SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS) $(SOBJS))
diff --git a/arch/arm/cpu/armv7/tegra2/board.c b/arch/arm/cpu/armv7/tegra2/board.c
index 816a8cd..1e92d98 100644
--- a/arch/arm/cpu/armv7/tegra2/board.c
+++ b/arch/arm/cpu/armv7/tegra2/board.c
@@ -25,7 +25,7 @@
 #include <asm/io.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/arch/tegra2.h>
-#include "board.h"
+#include <asm/arch/pmc.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
diff --git a/arch/arm/cpu/armv7/tegra2/board.h b/arch/arm/cpu/armv7/tegra2/board.h
deleted file mode 100644
index f8f09c0..0000000
--- a/arch/arm/cpu/armv7/tegra2/board.h
+++ /dev/null
@@ -1,58 +0,0 @@
-/*
- *  (C) Copyright 2010,2011
- *  NVIDIA Corporation <www.nvidia.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef _BOARD_H_
-#define _BOARD_H_
-
-#include <asm/arch/clk_rst.h>
-#include <asm/arch/pinmux.h>
-#include <asm/arch/pmc.h>
-#include <asm/arch/uart.h>
-
-#define NVRM_PLLP_FIXED_FREQ_KHZ	216000
-#define NV_DEFAULT_DEBUG_BAUD		115200
-
-#define PLL_BYPASS		(1 << 31)
-#define PLL_ENABLE		(1 << 30)
-#define PLL_BASE_OVRRIDE	(1 << 28)
-#define PLL_DIVP		(1 << 20)	/* post divider, b22:20 */
-#define PLL_DIVM		0x0C		/* input divider, b4:0 */
-
-#define SWR_UARTD_RST		(1 << 2)
-#define CLK_ENB_UARTD		(1 << 2)
-#define SWR_UARTA_RST		(1 << 6)
-#define CLK_ENB_UARTA		(1 << 6)
-
-#define Z_GMC			(1 << 29)
-#define Z_IRRX			(1 << 20)
-#define Z_IRTX			(1 << 19)
-
-enum {
-	UART_A = 1,
-	UART_B,
-	UART_C,
-	UART_D,
-	UART_E
-};
-
-#endif /* _BOARD_H_ */
diff --git a/arch/arm/cpu/armv7/tegra2/uart.c b/arch/arm/cpu/armv7/tegra2/uart.c
deleted file mode 100644
index 5e60bd8..0000000
--- a/arch/arm/cpu/armv7/tegra2/uart.c
+++ /dev/null
@@ -1,216 +0,0 @@
-/*
- *  (C) Copyright 2010,2011
- *  NVIDIA Corporation <www.nvidia.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <ns16550.h>
-#include <asm/io.h>
-#include <asm/arch/tegra2.h>
-#include "board.h"
-
-/*
- * Routine: uart_clock_init
- * Description: init the PLL and clock for the UART in uart_num
- */
-static void uart_clock_init(int uart_num)
-{
-	clk_rst_ctlr *const clkrst = (clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
-	static int pllp_init_done;
-	u32 reg;
-
-	if (!pllp_init_done) {
-		/* Override pllp setup for 216MHz operation. */
-		reg = (PLL_BYPASS | PLL_BASE_OVRRIDE | PLL_DIVP);
-		reg |= (((NVRM_PLLP_FIXED_FREQ_KHZ/500) << 8) | PLL_DIVM);
-		writel(reg, &clkrst->crc_pllp_base);
-
-		reg |= PLL_ENABLE;
-		writel(reg, &clkrst->crc_pllp_base);
-
-		reg &= ~PLL_BYPASS;
-		writel(reg, &clkrst->crc_pllp_base);
-
-		pllp_init_done++;
-	}
-
-	/* Now do the UART reset/clock enable based on uart_num */
-#if CONFIG_TEGRA2_ENABLE_UARTA
-	if (uart_num == UART_A) {
-		/* Assert Reset to UART */
-		reg = readl(&clkrst->crc_rst_dev_l);
-		reg |= SWR_UARTA_RST;		/* SWR_UARTA_RST = 1 */
-		writel(reg, &clkrst->crc_rst_dev_l);
-
-		/* Enable clk to UART */
-		reg = readl(&clkrst->crc_clk_out_enb_l);
-		reg |= CLK_ENB_UARTA;		/* CLK_ENB_UARTA = 1 */
-		writel(reg, &clkrst->crc_clk_out_enb_l);
-
-		/* Enable pllp_out0 to UART */
-		reg = readl(&clkrst->crc_clk_src_uarta);
-		reg &= 0x3FFFFFFF;	/* UARTA_CLK_SRC = 00, PLLP_OUT0 */
-		writel(reg, &clkrst->crc_clk_src_uarta);
-
-		/* wait for 2us */
-		udelay(2);
-
-		/* De-assert reset to UART */
-		reg = readl(&clkrst->crc_rst_dev_l);
-		reg &= ~SWR_UARTA_RST;		/* SWR_UARTA_RST = 0 */
-		writel(reg, &clkrst->crc_rst_dev_l);
-	}
-#endif	/* CONFIG_TEGRA2_ENABLE_UARTA */
-#if CONFIG_TEGRA2_ENABLE_UARTD
-	if (uart_num == UART_D) {
-		/* Assert Reset to UART */
-		reg = readl(&clkrst->crc_rst_dev_u);
-		reg |= SWR_UARTD_RST;		/* SWR_UARTD_RST = 1 */
-		writel(reg, &clkrst->crc_rst_dev_u);
-
-		/* Enable clk to UART */
-		reg = readl(&clkrst->crc_clk_out_enb_u);
-		reg |= CLK_ENB_UARTD;		/* CLK_ENB_UARTD = 1 */
-		writel(reg, &clkrst->crc_clk_out_enb_u);
-
-		/* Enable pllp_out0 to UART */
-		reg = readl(&clkrst->crc_clk_src_uartd);
-		reg &= 0x3FFFFFFF;	/* UARTD_CLK_SRC = 00, PLLP_OUT0 */
-		writel(reg, &clkrst->crc_clk_src_uartd);
-
-		/* wait for 2us */
-		udelay(2);
-
-		/* De-assert reset to UART */
-		reg = readl(&clkrst->crc_rst_dev_u);
-		reg &= ~SWR_UARTD_RST;		/* SWR_UARTD_RST = 0 */
-		writel(reg, &clkrst->crc_rst_dev_u);
-	}
-#endif	/* CONFIG_TEGRA2_ENABLE_UARTD */
-}
-
-/*
- * Routine: pin_mux_uart
- * Description: setup the pin muxes/tristate values for UART based on uart_num
- */
-static void pin_mux_uart(int uart_num)
-{
-	pinmux_tri_ctlr *const pmt = (pinmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
-	u32 reg;
-
-#if CONFIG_TEGRA2_ENABLE_UARTA
-	if (uart_num  == UART_A) {
-		reg = readl(&pmt->pmt_ctl_c);
-		reg &= 0xFFF0FFFF;	/* IRRX_/IRTX_SEL [19:16] = 00 UARTA */
-		writel(reg, &pmt->pmt_ctl_c);
-
-		reg = readl(&pmt->pmt_tri_a);
-		reg &= ~Z_IRRX;		/* Z_IRRX = normal (0) */
-		reg &= ~Z_IRTX;		/* Z_IRTX = normal (0) */
-		writel(reg, &pmt->pmt_tri_a);
-	}
-#endif	/* CONFIG_TEGRA2_ENABLE_UARTA */
-#if CONFIG_TEGRA2_ENABLE_UARTD
-	if (uart_num == UART_D) {
-		reg = readl(&pmt->pmt_ctl_b);
-		reg &= 0xFFFFFFF3;	/* GMC_SEL [3:2] = 00, UARTD */
-		writel(reg, &pmt->pmt_ctl_b);
-
-		reg = readl(&pmt->pmt_tri_a);
-		reg &= ~Z_GMC;		/* Z_GMC = normal (0) */
-		writel(reg, &pmt->pmt_tri_a);
-	}
-#endif	/* CONFIG_TEGRA2_ENABLE_UARTD */
-}
-
-static void setup_uart(uart_ctlr *u)
-{
-	u32 reg;
-
-	/* Prepare the divisor value */
-	reg = NVRM_PLLP_FIXED_FREQ_KHZ * 1000 / NV_DEFAULT_DEBUG_BAUD / 16;
-
-	/* Set up UART parameters */
-	writel(UART_LCR_DLAB, &u->uart_lcr);
-	writel(reg, &u->uart_thr_dlab_0);
-	writel(0, &u->uart_ier_dlab_0);
-	writel(0, &u->uart_lcr);			/* clear DLAB */
-	writel((UART_FCR_TRIGGER_3 | UART_FCR_FIFO_EN | \
-		UART_FCR_CLEAR_XMIT | UART_FCR_CLEAR_RCVR), &u->uart_iir_fcr);
-	writel(0, &u->uart_ier_dlab_0);
-	writel(UART_LCR_WLS_8, &u->uart_lcr);	/* 8N1 */
-	writel(UART_MCR_RTS, &u->uart_mcr);
-	writel(0, &u->uart_msr);
-	writel(0, &u->uart_spr);
-	writel(0, &u->uart_irda_csr);
-	writel(0, &u->uart_asr);
-	writel((UART_FCR_TRIGGER_3 | UART_FCR_FIFO_EN), &u->uart_iir_fcr);
-
-	/* Flush any old characters out of the RX FIFO */
-	reg = readl(&u->uart_lsr);
-
-	while (reg & UART_LSR_DR) {
-		reg = readl(&u->uart_thr_dlab_0);
-		reg = readl(&u->uart_lsr);
-	}
-}
-
-/*
- * Routine: init_uart
- * Description: init the UART clocks, muxes, and baudrate/parity/etc.
- */
-static void init_uart(int uart_num)
-{
-#if CONFIG_TEGRA2_ENABLE_UARTA
-	if (uart_num == UART_A) {
-		uart_ctlr *const uart = (uart_ctlr *)NV_PA_APB_UARTA_BASE;
-
-		uart_clock_init(UART_A);
-
-		/* Enable UARTA - uses config 0 */
-		pin_mux_uart(UART_A);
-
-		setup_uart(uart);
-	}
-#endif	/* CONFIG_TEGRA2_ENABLE_UARTD */
-#if CONFIG_TEGRA2_ENABLE_UARTD
-	if (uart_num == UART_D) {
-		uart_ctlr *const uart = (uart_ctlr *)NV_PA_APB_UARTD_BASE;
-
-		uart_clock_init(UART_D);
-
-		/* Enable UARTD - uses config 0 */
-		pin_mux_uart(UART_D);
-
-		setup_uart(uart);
-	}
-#endif	/* CONFIG_TEGRA2_ENABLE_UARTD */
-}
-
-void uart_init(void)
-{
-#if (CONFIG_TEGRA2_ENABLE_UARTA)
-	init_uart(UART_A);
-#endif
-#if (CONFIG_TEGRA2_ENABLE_UARTD)
-	init_uart(UART_D);
-#endif
-}
diff --git a/common/serial.c b/common/serial.c
index 051ae4e..8ebf9a5 100644
--- a/common/serial.c
+++ b/common/serial.c
@@ -41,7 +41,8 @@ struct serial_device *__default_serial_console (void)
 #elif defined(CONFIG_4xx) \
    || defined(CONFIG_MB86R0x) || defined(CONFIG_MPC5xxx) \
    || defined(CONFIG_MPC83xx) || defined(CONFIG_MPC85xx) \
-   || defined(CONFIG_MPC86xx) || defined(CONFIG_SYS_SC520)
+   || defined(CONFIG_MPC86xx) || defined(CONFIG_SYS_SC520) \
+   || defined(CONFIG_TEGRA2)
 #if defined(CONFIG_CONS_INDEX) && defined(CONFIG_SYS_NS16550_SERIAL)
 #if (CONFIG_CONS_INDEX==1)
 	return &eserial1_device;
diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile
index 7d221fc..5a6011e 100644
--- a/drivers/serial/Makefile
+++ b/drivers/serial/Makefile
@@ -55,6 +55,7 @@ COBJS-$(CONFIG_S3C24X0_SERIAL) += serial_s3c24x0.o
 COBJS-$(CONFIG_S3C44B0_SERIAL) += serial_s3c44b0.o
 COBJS-$(CONFIG_XILINX_UARTLITE) += serial_xuartlite.o
 COBJS-$(CONFIG_SCIF_CONSOLE) += serial_sh.o
+COBJS-$(CONFIG_TEGRA2) += serial_tegra2.o
 COBJS-$(CONFIG_USB_TTY) += usbtty.o
 
 COBJS	:= $(sort $(COBJS-y))
diff --git a/drivers/serial/serial_tegra2.c b/drivers/serial/serial_tegra2.c
new file mode 100644
index 0000000..64dc6b4
--- /dev/null
+++ b/drivers/serial/serial_tegra2.c
@@ -0,0 +1,205 @@
+/*
+ *  (C) Copyright 2010,2011
+ *  NVIDIA Corporation <www.nvidia.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <ns16550.h>
+#include <asm/io.h>
+#include <asm/arch/tegra2.h>
+#include "serial_tegra2.h"
+
+/*
+ * Routine: uart_clock_init
+ * Description: init the PLL and clock for the UART
+ */
+static void uart_clock_init(void)
+{
+	clk_rst_ctlr *const clkrst = (clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
+	static int pllp_init_done;
+	u32 reg;
+
+	if (!pllp_init_done) {
+		/* Override pllp setup for 216MHz operation. */
+		reg = (PLL_BYPASS | PLL_BASE_OVRRIDE | PLL_DIVP);
+		reg |= (((NVRM_PLLP_FIXED_FREQ_KHZ/500) << 8) | PLL_DIVM);
+		writel(reg, &clkrst->crc_pllp_base);
+
+		reg |= PLL_ENABLE;
+		writel(reg, &clkrst->crc_pllp_base);
+
+		reg &= ~PLL_BYPASS;
+		writel(reg, &clkrst->crc_pllp_base);
+
+		pllp_init_done++;
+	}
+
+	/* Now do the UART reset/clock enable */
+#if CONFIG_TEGRA2_ENABLE_UARTA
+		/* Assert Reset to UART */
+		reg = readl(&clkrst->crc_rst_dev_l);
+		reg |= SWR_UARTA_RST;		/* SWR_UARTA_RST = 1 */
+		writel(reg, &clkrst->crc_rst_dev_l);
+
+		/* Enable clk to UART */
+		reg = readl(&clkrst->crc_clk_out_enb_l);
+		reg |= CLK_ENB_UARTA;		/* CLK_ENB_UARTA = 1 */
+		writel(reg, &clkrst->crc_clk_out_enb_l);
+
+		/* Enable pllp_out0 to UART */
+		reg = readl(&clkrst->crc_clk_src_uarta);
+		reg &= 0x3FFFFFFF;	/* UARTA_CLK_SRC = 00, PLLP_OUT0 */
+		writel(reg, &clkrst->crc_clk_src_uarta);
+
+		/* wait for 2us */
+		udelay(2);
+
+		/* De-assert reset to UART */
+		reg = readl(&clkrst->crc_rst_dev_l);
+		reg &= ~SWR_UARTA_RST;		/* SWR_UARTA_RST = 0 */
+		writel(reg, &clkrst->crc_rst_dev_l);
+#endif	/* CONFIG_TEGRA2_ENABLE_UARTA */
+#if CONFIG_TEGRA2_ENABLE_UARTD
+		/* Assert Reset to UART */
+		reg = readl(&clkrst->crc_rst_dev_u);
+		reg |= SWR_UARTD_RST;		/* SWR_UARTD_RST = 1 */
+		writel(reg, &clkrst->crc_rst_dev_u);
+
+		/* Enable clk to UART */
+		reg = readl(&clkrst->crc_clk_out_enb_u);
+		reg |= CLK_ENB_UARTD;		/* CLK_ENB_UARTD = 1 */
+		writel(reg, &clkrst->crc_clk_out_enb_u);
+
+		/* Enable pllp_out0 to UART */
+		reg = readl(&clkrst->crc_clk_src_uartd);
+		reg &= 0x3FFFFFFF;	/* UARTD_CLK_SRC = 00, PLLP_OUT0 */
+		writel(reg, &clkrst->crc_clk_src_uartd);
+
+		/* wait for 2us */
+		udelay(2);
+
+		/* De-assert reset to UART */
+		reg = readl(&clkrst->crc_rst_dev_u);
+		reg &= ~SWR_UARTD_RST;		/* SWR_UARTD_RST = 0 */
+		writel(reg, &clkrst->crc_rst_dev_u);
+#endif	/* CONFIG_TEGRA2_ENABLE_UARTD */
+}
+
+/*
+ * Routine: pin_mux_uart
+ * Description: setup the pin muxes/tristate values for a UART
+ */
+static void pin_mux_uart(void)
+{
+	pinmux_tri_ctlr *const pmt = (pinmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
+	u32 reg;
+
+#if CONFIG_TEGRA2_ENABLE_UARTA
+		reg = readl(&pmt->pmt_ctl_c);
+		reg &= 0xFFF0FFFF;	/* IRRX_/IRTX_SEL [19:16] = 00 UARTA */
+		writel(reg, &pmt->pmt_ctl_c);
+
+		reg = readl(&pmt->pmt_tri_a);
+		reg &= ~Z_IRRX;		/* Z_IRRX = normal (0) */
+		reg &= ~Z_IRTX;		/* Z_IRTX = normal (0) */
+		writel(reg, &pmt->pmt_tri_a);
+#endif	/* CONFIG_TEGRA2_ENABLE_UARTA */
+#if CONFIG_TEGRA2_ENABLE_UARTD
+		reg = readl(&pmt->pmt_ctl_b);
+		reg &= 0xFFFFFFF3;	/* GMC_SEL [3:2] = 00, UARTD */
+		writel(reg, &pmt->pmt_ctl_b);
+
+		reg = readl(&pmt->pmt_tri_a);
+		reg &= ~Z_GMC;		/* Z_GMC = normal (0) */
+		writel(reg, &pmt->pmt_tri_a);
+#endif	/* CONFIG_TEGRA2_ENABLE_UARTD */
+}
+
+static void setup_uart(uart_ctlr *u)
+{
+	u32 reg;
+
+	/* Prepare the divisor value */
+	reg = NVRM_PLLP_FIXED_FREQ_KHZ * 1000 / NV_DEFAULT_DEBUG_BAUD / 16;
+
+	/* Set up UART parameters */
+	writel(UART_LCR_DLAB, &u->uart_lcr);
+	writel(reg, &u->uart_thr_dlab_0);
+	writel(0, &u->uart_ier_dlab_0);
+	writel(0, &u->uart_lcr);			/* clear DLAB */
+	writel((UART_FCR_TRIGGER_3 | UART_FCR_FIFO_EN | \
+		UART_FCR_CLEAR_XMIT | UART_FCR_CLEAR_RCVR), &u->uart_iir_fcr);
+	writel(0, &u->uart_ier_dlab_0);
+	writel(UART_LCR_WLS_8, &u->uart_lcr);	/* 8N1 */
+	writel(UART_MCR_RTS, &u->uart_mcr);
+	writel(0, &u->uart_msr);
+	writel(0, &u->uart_spr);
+	writel(0, &u->uart_irda_csr);
+	writel(0, &u->uart_asr);
+	writel((UART_FCR_TRIGGER_3 | UART_FCR_FIFO_EN), &u->uart_iir_fcr);
+
+	/* Flush any old characters out of the RX FIFO */
+	reg = readl(&u->uart_lsr);
+
+	while (reg & UART_LSR_DR) {
+		reg = readl(&u->uart_thr_dlab_0);
+		reg = readl(&u->uart_lsr);
+	}
+}
+
+/*
+ * Routine: init_uart
+ * Description: init the UART clocks, muxes, and baudrate/parity/etc.
+ */
+static void init_uart(void)
+{
+#if CONFIG_TEGRA2_ENABLE_UARTA
+		uart_ctlr *const uart = (uart_ctlr *)NV_PA_APB_UARTA_BASE;
+
+		uart_clock_init();
+
+		/* Enable UARTA - uses config 0 */
+		pin_mux_uart();
+
+		setup_uart(uart);
+#endif	/* CONFIG_TEGRA2_ENABLE_UARTD */
+#if CONFIG_TEGRA2_ENABLE_UARTD
+		uart_ctlr *const uart = (uart_ctlr *)NV_PA_APB_UARTD_BASE;
+
+		uart_clock_init();
+
+		/* Enable UARTD - uses config 0 */
+		pin_mux_uart();
+
+		setup_uart(uart);
+#endif	/* CONFIG_TEGRA2_ENABLE_UARTD */
+}
+
+void uart_init(void)
+{
+	/* Init each UART - there may be more than 1 on a board/build */
+#if (CONFIG_TEGRA2_ENABLE_UARTA)
+	init_uart();
+#endif
+#if (CONFIG_TEGRA2_ENABLE_UARTD)
+	init_uart();
+#endif
+}
diff --git a/drivers/serial/serial_tegra2.h b/drivers/serial/serial_tegra2.h
new file mode 100644
index 0000000..a8ead9f
--- /dev/null
+++ b/drivers/serial/serial_tegra2.h
@@ -0,0 +1,49 @@
+/*
+ *  (C) Copyright 2010,2011
+ *  NVIDIA Corporation <www.nvidia.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _SERIAL_TEGRA_H_
+#define _SERIAL_TEGRA_H_
+
+#include <asm/arch/clk_rst.h>
+#include <asm/arch/pinmux.h>
+#include <asm/arch/uart.h>
+
+#define NVRM_PLLP_FIXED_FREQ_KHZ	216000
+#define NV_DEFAULT_DEBUG_BAUD		115200
+
+#define PLL_BYPASS		(1 << 31)
+#define PLL_ENABLE		(1 << 30)
+#define PLL_BASE_OVRRIDE	(1 << 28)
+#define PLL_DIVP		(1 << 20)	/* post divider, b22:20 */
+#define PLL_DIVM		0x0C		/* input divider, b4:0 */
+
+#define SWR_UARTD_RST		(1 << 2)
+#define CLK_ENB_UARTD		(1 << 2)
+#define SWR_UARTA_RST		(1 << 6)
+#define CLK_ENB_UARTA		(1 << 6)
+
+#define Z_GMC			(1 << 29)
+#define Z_IRRX			(1 << 20)
+#define Z_IRTX			(1 << 19)
+
+#endif /* _SERIAL_TEGRA_H_ */
diff --git a/include/serial.h b/include/serial.h
index 15ab73c..f21d961 100644
--- a/include/serial.h
+++ b/include/serial.h
@@ -27,7 +27,8 @@ extern struct serial_device * default_serial_console (void);
     defined(CONFIG_405EP) || defined(CONFIG_405EZ) || defined(CONFIG_405EX) || \
     defined(CONFIG_MB86R0x) || defined(CONFIG_MPC5xxx) || \
     defined(CONFIG_MPC83xx) || defined(CONFIG_MPC85xx) || \
-    defined(CONFIG_MPC86xx) || defined(CONFIG_SYS_SC520)
+    defined(CONFIG_MPC86xx) || defined(CONFIG_SYS_SC520) || \
+    defined(CONFIG_TEGRA2)
 extern struct serial_device serial0_device;
 extern struct serial_device serial1_device;
 #if defined(CONFIG_SYS_NS16550_SERIAL)
-- 
1.7.3.5

[U-Boot] [PATCH V5 2/4] serial: Add Tegra2 serial port support

[Peter Tyser]

Hi Tom,

On Fri, 2011-01-21 at 16:06 -0700, Tom Warren wrote:
> Signed-off-by: Tom Warren <twarren@nvidia.com>
> ---
> Changes for V2:
> 	- Move serial driver to separate patch
> 
> Changes for V5:
> 	- Move arch/arm/cpu/armv7/uart.c & board.h to drivers/serial and
> 		rename to serial_tegra2.c
> 	- Remove use of uart_num & UART_A/D in serial_tegra2, simplify code
> 
>  arch/arm/cpu/armv7/tegra2/Makefile |    2 +-
>  arch/arm/cpu/armv7/tegra2/board.c  |    2 +-
>  arch/arm/cpu/armv7/tegra2/board.h  |   58 ----------
>  arch/arm/cpu/armv7/tegra2/uart.c   |  216 ------------------------------------
>  common/serial.c                    |    3 +-
>  drivers/serial/Makefile            |    1 +
>  drivers/serial/serial_tegra2.c     |  205 ++++++++++++++++++++++++++++++++++
>  drivers/serial/serial_tegra2.h     |   49 ++++++++
>  include/serial.h                   |    3 +-
>  9 files changed, 261 insertions(+), 278 deletions(-)
>  delete mode 100644 arch/arm/cpu/armv7/tegra2/board.h
>  delete mode 100644 arch/arm/cpu/armv7/tegra2/uart.c
>  create mode 100644 drivers/serial/serial_tegra2.c
>  create mode 100644 drivers/serial/serial_tegra2.h

It looks like arch/arm/cpu/armv7/tegra2/board.h and
arch/arm/cpu/armv7/tegra2/uart.c are added in the first patch, then
moved in this patch.  It'd be ideal to just add them once in the proper
location.

On a side note, if you pass "git format-patch" the -M and -C options it
will make pretty diffs that only show what lines changed during a move.
In the case that you do move files in the future its nice to use those
options to ease review.

<snip>

+void uart_init(void)
> +{
> +	/* Init each UART - there may be more than 1 on a board/build */
> +#if (CONFIG_TEGRA2_ENABLE_UARTA)
> +	init_uart();
> +#endif
> +#if (CONFIG_TEGRA2_ENABLE_UARTD)
> +	init_uart();
> +#endif
> +}

How about:
#if defined(CONFIG_TEGRA2_ENABLE_UARTA) || defined(CONFIG_TEGRA2_ENABLE_UARTD)
	init_uart();
#endif

Best,
Peter

[U-Boot] [PATCH V5 2/4] serial: Add Tegra2 serial port support

[Tom Warren]

Peter,

On Fri, Jan 21, 2011 at 4:46 PM, Peter Tyser <ptyser@xes-inc.com> wrote:
> Hi Tom,
>
> On Fri, 2011-01-21 at 16:06 -0700, Tom Warren wrote:
>> Signed-off-by: Tom Warren <twarren@nvidia.com>
>> ---
>> Changes for V2:
>> ? ? ? - Move serial driver to separate patch
>>
>> Changes for V5:
>> ? ? ? - Move arch/arm/cpu/armv7/uart.c & board.h to drivers/serial and
>> ? ? ? ? ? ? ? rename to serial_tegra2.c
>> ? ? ? - Remove use of uart_num & UART_A/D in serial_tegra2, simplify code
>>
>> ?arch/arm/cpu/armv7/tegra2/Makefile | ? ?2 +-
>> ?arch/arm/cpu/armv7/tegra2/board.c ?| ? ?2 +-
>> ?arch/arm/cpu/armv7/tegra2/board.h ?| ? 58 ----------
>> ?arch/arm/cpu/armv7/tegra2/uart.c ? | ?216 ------------------------------------
>> ?common/serial.c ? ? ? ? ? ? ? ? ? ?| ? ?3 +-
>> ?drivers/serial/Makefile ? ? ? ? ? ?| ? ?1 +
>> ?drivers/serial/serial_tegra2.c ? ? | ?205 ++++++++++++++++++++++++++++++++++
>> ?drivers/serial/serial_tegra2.h ? ? | ? 49 ++++++++
>> ?include/serial.h ? ? ? ? ? ? ? ? ? | ? ?3 +-
>> ?9 files changed, 261 insertions(+), 278 deletions(-)
>> ?delete mode 100644 arch/arm/cpu/armv7/tegra2/board.h
>> ?delete mode 100644 arch/arm/cpu/armv7/tegra2/uart.c
>> ?create mode 100644 drivers/serial/serial_tegra2.c
>> ?create mode 100644 drivers/serial/serial_tegra2.h
>
> It looks like arch/arm/cpu/armv7/tegra2/board.h and
> arch/arm/cpu/armv7/tegra2/uart.c are added in the first patch, then
> moved in this patch. ?It'd be ideal to just add them once in the proper
> location.
>
> On a side note, if you pass "git format-patch" the -M and -C options it
> will make pretty diffs that only show what lines changed during a move.
> In the case that you do move files in the future its nice to use those
> options to ease review.
>
I'll use those options in the future (thanks!) to keep things cleaner.
Hopefully we can just go with this set of patches so I can get to the
other, more interesting code (drivers, A9 CPU init, etc.).

> <snip>
>
> +void uart_init(void)
>> +{
>> + ? ? /* Init each UART - there may be more than 1 on a board/build */
>> +#if (CONFIG_TEGRA2_ENABLE_UARTA)
>> + ? ? init_uart();
>> +#endif
>> +#if (CONFIG_TEGRA2_ENABLE_UARTD)
>> + ? ? init_uart();
>> +#endif
>> +}
>
> How about:
> #if defined(CONFIG_TEGRA2_ENABLE_UARTA) || defined(CONFIG_TEGRA2_ENABLE_UARTD)
> ? ? ? ?init_uart();
> #endif
That won't work for a board like Harmony where the developer wants
both UARTs active, since uart_init is only called once.

>
> Best,
> Peter
Thanks,
Tom
>
>

[U-Boot] [PATCH V5 2/4] serial: Add Tegra2 serial port support

[Peter Tyser]

<snip>

> > It looks like arch/arm/cpu/armv7/tegra2/board.h and
> > arch/arm/cpu/armv7/tegra2/uart.c are added in the first patch, then
> > moved in this patch.  It'd be ideal to just add them once in the proper
> > location.
> >
> > On a side note, if you pass "git format-patch" the -M and -C options it
> > will make pretty diffs that only show what lines changed during a move.
> > In the case that you do move files in the future its nice to use those
> > options to ease review.
> >
> I'll use those options in the future (thanks!) to keep things cleaner.
> Hopefully we can just go with this set of patches so I can get to the
> other, more interesting code (drivers, A9 CPU init, etc.).

Its up to the ARM maintainer and Wolfgang to decide if adding code in
one patch just to move it around in the 2nd is acceptable.  I'm guess it
won't be acceptable since its considered "bad form", and its unclear
what patch in this series contains what functionality.  Eg this isn't
really meant to "Add Tegra2 serial port support", it moves existing
serial port code around?  And more?  Its not really just adding serial
port support as the patch title states in any case.

> > <snip>
> >
> > +void uart_init(void)
> >> +{
> >> +     /* Init each UART - there may be more than 1 on a board/build */
> >> +#if (CONFIG_TEGRA2_ENABLE_UARTA)
> >> +     init_uart();
> >> +#endif
> >> +#if (CONFIG_TEGRA2_ENABLE_UARTD)
> >> +     init_uart();
> >> +#endif
> >> +}
> >
> > How about:
> > #if defined(CONFIG_TEGRA2_ENABLE_UARTA) || defined(CONFIG_TEGRA2_ENABLE_UARTD)
> >        init_uart();
> > #endif
> That won't work for a board like Harmony where the developer wants
> both UARTs active, since uart_init is only called once.

Why should init_uart() be called two times?  It looks to initialize both
ports, meaning it should only be called once, right?

Also, just noticed:
+static void init_uart(void)
+{
+#if CONFIG_TEGRA2_ENABLE_UARTA
+               uart_ctlr *const uart = (uart_ctlr *)NV_PA_APB_UARTA_BASE;
+
+               uart_clock_init();
+
+               /* Enable UARTA - uses config 0 */
+               pin_mux_uart();
+
+               setup_uart(uart);
+#endif /* CONFIG_TEGRA2_ENABLE_UARTD */
+#if CONFIG_TEGRA2_ENABLE_UARTD
+               uart_ctlr *const uart = (uart_ctlr *)NV_PA_APB_UARTD_BASE;
+

Have you compiled with both UARTA and UARTD enabled?  Redeclaring 'uart'
in the middle of the function should throw an error or warning.

+               uart_clock_init();
+
+               /* Enable UARTD - uses config 0 */
+               pin_mux_uart();
+
+               setup_uart(uart);
+#endif /* CONFIG_TEGRA2_ENABLE_UARTD */
+}

Best,
Peter

[U-Boot] [PATCH V5 2/4] serial: Add Tegra2 serial port support

[Tom Warren]

Peter,

On Mon, Jan 24, 2011 at 10:51 AM, Peter Tyser <ptyser@xes-inc.com> wrote:
> <snip>
>
>> > It looks like arch/arm/cpu/armv7/tegra2/board.h and
>> > arch/arm/cpu/armv7/tegra2/uart.c are added in the first patch, then
>> > moved in this patch. ?It'd be ideal to just add them once in the proper
>> > location.
>> >
>> > On a side note, if you pass "git format-patch" the -M and -C options it
>> > will make pretty diffs that only show what lines changed during a move.
>> > In the case that you do move files in the future its nice to use those
>> > options to ease review.
>> >
>> I'll use those options in the future (thanks!) to keep things cleaner.
>> Hopefully we can just go with this set of patches so I can get to the
>> other, more interesting code (drivers, A9 CPU init, etc.).
>
> Its up to the ARM maintainer and Wolfgang to decide if adding code in
> one patch just to move it around in the 2nd is acceptable. ?I'm guess it
> won't be acceptable since its considered "bad form", and its unclear
> what patch in this series contains what functionality. ?Eg this isn't
> really meant to "Add Tegra2 serial port support", it moves existing
> serial port code around? ?And more? ?Its not really just adding serial
> port support as the patch title states in any case.
I see what you're talking about now - I've got uart.c in 2 patch files - created
in 0001 and then moved in 0002. My bad - that wasn't the intent, just what
happened when I applied my V4 patches to a new branch to get the V5 patchset
built.  I'll fix it and resubmit.

As to 0002 not adding serial port support for Tegra2, that's all it does - adds
TEGRA2 defines to serial.h/serial.c for the eserial* tables, and then adds
code to turn on Tegra2-specific UART HW.  If I remove any mention of uart.c
in patch 0001 (add basic Tegra2 support), then does patch 0002 make
sense to you?

>
>> > <snip>
>> >
>> > +void uart_init(void)
>> >> +{
>> >> + ? ? /* Init each UART - there may be more than 1 on a board/build */
>> >> +#if (CONFIG_TEGRA2_ENABLE_UARTA)
>> >> + ? ? init_uart();
>> >> +#endif
>> >> +#if (CONFIG_TEGRA2_ENABLE_UARTD)
>> >> + ? ? init_uart();
>> >> +#endif
>> >> +}
>> >
>> > How about:
>> > #if defined(CONFIG_TEGRA2_ENABLE_UARTA) || defined(CONFIG_TEGRA2_ENABLE_UARTD)
>> > ? ? ? ?init_uart();
>> > #endif
>> That won't work for a board like Harmony where the developer wants
>> both UARTs active, since uart_init is only called once.
>
> Why should init_uart() be called two times? ?It looks to initialize both
> ports, meaning it should only be called once, right?
Correct, again (need more coffee!)  Your if defined construct wouldn't work
as written, though, because CONFIG_TEGRA2_ENABLE_UARTx is always
defined (as 0 or 1). I'd have to rework it.

>
> Also, just noticed:
> +static void init_uart(void)
> +{
> +#if CONFIG_TEGRA2_ENABLE_UARTA
> + ? ? ? ? ? ? ? uart_ctlr *const uart = (uart_ctlr *)NV_PA_APB_UARTA_BASE;
> +
> + ? ? ? ? ? ? ? uart_clock_init();
> +
> + ? ? ? ? ? ? ? /* Enable UARTA - uses config 0 */
> + ? ? ? ? ? ? ? pin_mux_uart();
> +
> + ? ? ? ? ? ? ? setup_uart(uart);
> +#endif /* CONFIG_TEGRA2_ENABLE_UARTD */
> +#if CONFIG_TEGRA2_ENABLE_UARTD
> + ? ? ? ? ? ? ? uart_ctlr *const uart = (uart_ctlr *)NV_PA_APB_UARTD_BASE;
> +
>
> Have you compiled with both UARTA and UARTD enabled? ?Redeclaring 'uart'
> in the middle of the function should throw an error or warning.
I'd tested with both enabled earlier, but maybe not since the rewrite.
I'll check & resubmit.

>
> + ? ? ? ? ? ? ? uart_clock_init();
> +
> + ? ? ? ? ? ? ? /* Enable UARTD - uses config 0 */
> + ? ? ? ? ? ? ? pin_mux_uart();
> +
> + ? ? ? ? ? ? ? setup_uart(uart);
> +#endif /* CONFIG_TEGRA2_ENABLE_UARTD */
> +}
>
> Best,
> Peter
Thanks, again, for your thoroughness!
Tom
>
>

[U-Boot] [PATCH V5 2/4] serial: Add Tegra2 serial port support

[Wolfgang Denk]

Dear Tom Warren,

In message <AANLkTi=uPxZUEeO52EJgQALWL0hznkdGvtdRzMMwibNp@mail.gmail.com> you wrote:
> 
> Correct, again (need more coffee!)  Your if defined construct wouldn't work
> as written, though, because CONFIG_TEGRA2_ENABLE_UARTx is always
> defined (as 0 or 1). I'd have to rework it.

Please try and avoid relying on specific values.
Rather use "#if defined".

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
"We have the right to survive!"
"Not be killing others."
	-- Deela and Kirk, "Wink of An Eye", stardate 5710.5

[U-Boot] [PATCH V5 2/4] serial: Add Tegra2 serial port support

[Peter Tyser]

<snip>

> I see what you're talking about now - I've got uart.c in 2 patch files - created
> in 0001 and then moved in 0002. My bad - that wasn't the intent, just what
> happened when I applied my V4 patches to a new branch to get the V5 patchset
> built.  I'll fix it and resubmit.
> 
> As to 0002 not adding serial port support for Tegra2, that's all it does - adds
> TEGRA2 defines to serial.h/serial.c for the eserial* tables, and then adds
> code to turn on Tegra2-specific UART HW.  If I remove any mention of uart.c
> in patch 0001 (add basic Tegra2 support), then does patch 0002 make
> sense to you?

Yeah, that'd make more sense.  Patch 2 would just contain:
 common/serial.c                    |    3 +-
 drivers/serial/Makefile            |    1 +
 drivers/serial/serial_tegra2.c     |  205 ++++++++++++++++++++++++++++++++++
 drivers/serial/serial_tegra2.h     |   49 ++++++++
 include/serial.h                   |    3 +-

> >> > <snip>
> >> >
> >> > +void uart_init(void)
> >> >> +{
> >> >> +     /* Init each UART - there may be more than 1 on a board/build */
> >> >> +#if (CONFIG_TEGRA2_ENABLE_UARTA)
> >> >> +     init_uart();
> >> >> +#endif
> >> >> +#if (CONFIG_TEGRA2_ENABLE_UARTD)
> >> >> +     init_uart();
> >> >> +#endif
> >> >> +}
> >> >
> >> > How about:
> >> > #if defined(CONFIG_TEGRA2_ENABLE_UARTA) || defined(CONFIG_TEGRA2_ENABLE_UARTD)
> >> >        init_uart();
> >> > #endif
> >> That won't work for a board like Harmony where the developer wants
> >> both UARTs active, since uart_init is only called once.
> >
> > Why should init_uart() be called two times?  It looks to initialize both
> > ports, meaning it should only be called once, right?
> Correct, again (need more coffee!)  Your if defined construct wouldn't work
> as written, though, because CONFIG_TEGRA2_ENABLE_UARTx is always
> defined (as 0 or 1). I'd have to rework it.

You could also just get rid of uart_init() altogether and rename
init_uart() to uart_init().  That would get rid of some idefs and
simplify the flow.

Best,
Peter

[U-Boot] [PATCH V5 2/4] serial: Add Tegra2 serial port support

[Tom Warren]

Peter,

On Mon, Jan 24, 2011 at 12:14 PM, Peter Tyser <ptyser@xes-inc.com> wrote:
> <snip>
>
>> I see what you're talking about now - I've got uart.c in 2 patch files - created
>> in 0001 and then moved in 0002. My bad - that wasn't the intent, just what
>> happened when I applied my V4 patches to a new branch to get the V5 patchset
>> built. ?I'll fix it and resubmit.
>>
>> As to 0002 not adding serial port support for Tegra2, that's all it does - adds
>> TEGRA2 defines to serial.h/serial.c for the eserial* tables, and then adds
>> code to turn on Tegra2-specific UART HW. ?If I remove any mention of uart.c
>> in patch 0001 (add basic Tegra2 support), then does patch 0002 make
>> sense to you?
>
> Yeah, that'd make more sense. ?Patch 2 would just contain:
> ?common/serial.c ? ? ? ? ? ? ? ? ? ?| ? ?3 +-
> ?drivers/serial/Makefile ? ? ? ? ? ?| ? ?1 +
> ?drivers/serial/serial_tegra2.c ? ? | ?205 ++++++++++++++++++++++++++++++++++
> ?drivers/serial/serial_tegra2.h ? ? | ? 49 ++++++++
> ?include/serial.h ? ? ? ? ? ? ? ? ? | ? ?3 +-
>
Exactly what I was thinking. I'll try to get it right in patch V6.

>> >> > <snip>
>> >> >
>> >> > +void uart_init(void)
>> >> >> +{
>> >> >> + ? ? /* Init each UART - there may be more than 1 on a board/build */
>> >> >> +#if (CONFIG_TEGRA2_ENABLE_UARTA)
>> >> >> + ? ? init_uart();
>> >> >> +#endif
>> >> >> +#if (CONFIG_TEGRA2_ENABLE_UARTD)
>> >> >> + ? ? init_uart();
>> >> >> +#endif
>> >> >> +}
>> >> >
>> >> > How about:
>> >> > #if defined(CONFIG_TEGRA2_ENABLE_UARTA) || defined(CONFIG_TEGRA2_ENABLE_UARTD)
>> >> > ? ? ? ?init_uart();
>> >> > #endif
>> >> That won't work for a board like Harmony where the developer wants
>> >> both UARTs active, since uart_init is only called once.
>> >
>> > Why should init_uart() be called two times? ?It looks to initialize both
>> > ports, meaning it should only be called once, right?
>> Correct, again (need more coffee!) ?Your if defined construct wouldn't work
>> as written, though, because CONFIG_TEGRA2_ENABLE_UARTx is always
>> defined (as 0 or 1). I'd have to rework it.
>
> You could also just get rid of uart_init() altogether and rename
> init_uart() to uart_init(). ?That would get rid of some idefs and
> simplify the flow.
Yeah, I saw that as I was cleaning up the indentation & reworking the
code to compile
with both UARTs defined. I'll get rid of  uart_init (renamed to
init_uart). Thanks.

>
> Best,
> Peter
Thanks,

Tom
>
>

[U-Boot] [PATCH V5 2/4] serial: Add Tegra2 serial port support

[Wolfgang Denk]

Dear Peter Tyser,

In message <1295891506.2045.146.camel@petert> you wrote:
> 
> > I'll use those options in the future (thanks!) to keep things cleaner.
> > Hopefully we can just go with this set of patches so I can get to the
> > other, more interesting code (drivers, A9 CPU init, etc.).
> 
> Its up to the ARM maintainer and Wolfgang to decide if adding code in
> one patch just to move it around in the 2nd is acceptable.  I'm guess it

No, it is not acceptable. This should be fixed.  Thanks for pointing
out.

> Also, just noticed:
> +static void init_uart(void)
> +{
> +#if CONFIG_TEGRA2_ENABLE_UARTA
> +               uart_ctlr *const uart = (uart_ctlr *)NV_PA_APB_UARTA_BASE;
> +
> +               uart_clock_init();
> +
> +               /* Enable UARTA - uses config 0 */
> +               pin_mux_uart();
> +
> +               setup_uart(uart);
> +#endif /* CONFIG_TEGRA2_ENABLE_UARTD */
> +#if CONFIG_TEGRA2_ENABLE_UARTD
> +               uart_ctlr *const uart = (uart_ctlr *)NV_PA_APB_UARTD_BASE;
> +
> 
> Have you compiled with both UARTA and UARTD enabled?  Redeclaring 'uart'
> in the middle of the function should throw an error or warning.


Even if the compiler should accept it (which I hpe not), then I will
not accept this ;-)  Thanks for pointing out.


Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
There is an old custom among my people. When a woman  saves  a  man's
life, he is grateful.
	-- Nona, the Kanuto which woman, "A Private Little War",
	   stardate 4211.8.

[U-Boot] [PATCH V5 2/4] serial: Add Tegra2 serial port support

[Mike Rapoport]

On 01/22/11 01:06, Tom Warren wrote:
> Signed-off-by: Tom Warren <twarren@nvidia.com>
> ---

[ snip ]

> +/*
> + * Routine: pin_mux_uart
> + * Description: setup the pin muxes/tristate values for a UART
> + */
> +static void pin_mux_uart(void)
> +{
> +	pinmux_tri_ctlr *const pmt = (pinmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
> +	u32 reg;
> +
> +#if CONFIG_TEGRA2_ENABLE_UARTA
> +		reg = readl(&pmt->pmt_ctl_c);
> +		reg &= 0xFFF0FFFF;	/* IRRX_/IRTX_SEL [19:16] = 00 UARTA */
> +		writel(reg, &pmt->pmt_ctl_c);
> +
> +		reg = readl(&pmt->pmt_tri_a);
> +		reg &= ~Z_IRRX;		/* Z_IRRX = normal (0) */
> +		reg &= ~Z_IRTX;		/* Z_IRTX = normal (0) */
> +		writel(reg, &pmt->pmt_tri_a);
> +#endif	/* CONFIG_TEGRA2_ENABLE_UARTA */
> +#if CONFIG_TEGRA2_ENABLE_UARTD
> +		reg = readl(&pmt->pmt_ctl_b);
> +		reg &= 0xFFFFFFF3;	/* GMC_SEL [3:2] = 00, UARTD */
> +		writel(reg, &pmt->pmt_ctl_b);
> +
> +		reg = readl(&pmt->pmt_tri_a);
> +		reg &= ~Z_GMC;		/* Z_GMC = normal (0) */
> +		writel(reg, &pmt->pmt_tri_a);
> +#endif	/* CONFIG_TEGRA2_ENABLE_UARTD */

As I've already pointed out (1) this covers only one possibility of UART pin
muxing options. I agree that it makes sense when this is a part of the
board-specific code. However, forcing specific pins configuration in the generic
driver seems problematic to me, even if most Tegra2 boards use the same
configuration.
As a side note, I'd prefer to have all the pin multiplexing defined in one place
in board file rather than scattered among different drivers.

(1) http://thread.gmane.org/gmane.comp.boot-loaders.u-boot/92887/focus=93233


-- 
Sincerely yours,
Mike.

[U-Boot] [PATCH V5 2/4] serial: Add Tegra2 serial port support

[Tom Warren]

Mike,

On Tue, Jan 25, 2011 at 1:11 AM, Mike Rapoport <mike@compulab.co.il> wrote:
> On 01/22/11 01:06, Tom Warren wrote:
>> Signed-off-by: Tom Warren <twarren@nvidia.com>
>> ---
>
> [ snip ]
>
>> +/*
>> + * Routine: pin_mux_uart
>> + * Description: setup the pin muxes/tristate values for a UART
>> + */
>> +static void pin_mux_uart(void)
>> +{
>> + ? ? pinmux_tri_ctlr *const pmt = (pinmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
>> + ? ? u32 reg;
>> +
>> +#if CONFIG_TEGRA2_ENABLE_UARTA
>> + ? ? ? ? ? ? reg = readl(&pmt->pmt_ctl_c);
>> + ? ? ? ? ? ? reg &= 0xFFF0FFFF; ? ? ?/* IRRX_/IRTX_SEL [19:16] = 00 UARTA */
>> + ? ? ? ? ? ? writel(reg, &pmt->pmt_ctl_c);
>> +
>> + ? ? ? ? ? ? reg = readl(&pmt->pmt_tri_a);
>> + ? ? ? ? ? ? reg &= ~Z_IRRX; ? ? ? ? /* Z_IRRX = normal (0) */
>> + ? ? ? ? ? ? reg &= ~Z_IRTX; ? ? ? ? /* Z_IRTX = normal (0) */
>> + ? ? ? ? ? ? writel(reg, &pmt->pmt_tri_a);
>> +#endif ? ? ? /* CONFIG_TEGRA2_ENABLE_UARTA */
>> +#if CONFIG_TEGRA2_ENABLE_UARTD
>> + ? ? ? ? ? ? reg = readl(&pmt->pmt_ctl_b);
>> + ? ? ? ? ? ? reg &= 0xFFFFFFF3; ? ? ?/* GMC_SEL [3:2] = 00, UARTD */
>> + ? ? ? ? ? ? writel(reg, &pmt->pmt_ctl_b);
>> +
>> + ? ? ? ? ? ? reg = readl(&pmt->pmt_tri_a);
>> + ? ? ? ? ? ? reg &= ~Z_GMC; ? ? ? ? ?/* Z_GMC = normal (0) */
>> + ? ? ? ? ? ? writel(reg, &pmt->pmt_tri_a);
>> +#endif ? ? ? /* CONFIG_TEGRA2_ENABLE_UARTD */
>
> As I've already pointed out (1) this covers only one possibility of UART pin
> muxing options. I agree that it makes sense when this is a part of the
> board-specific code. However, forcing specific pins configuration in the generic
> driver seems problematic to me, even if most Tegra2 boards use the same
> configuration.
> As a side note, I'd prefer to have all the pin multiplexing defined in one place
> in board file rather than scattered among different drivers.
>
Alright. I'd like to get this wrapped up and accepted before the merge window
closes so I can get on with the important bits (drivers, etc.). What
would you like
here? A generic function like 'pinmux_set_config(reg, val, bit)' that
lives in the board
files and gets called from the driver code with specifics of that
board's/drivers pinmux
config? Or do you see the pinmux code living entirely in the board
files, and being done
as part of board init? That's where it was before, BTW.

If there are examples that you approve of in any extant U-Boot code (omap,
ti91, davinci, etc.), please point them out.  I'd really like to
finalize this patch series.

> (1) http://thread.gmane.org/gmane.comp.boot-loaders.u-boot/92887/focus=93233
>
>
> --
> Sincerely yours,
> Mike.
Thanks,

Tom
>

[U-Boot] [PATCH V5 2/4] serial: Add Tegra2 serial port support

[Mike Rapoport]

On 01/25/11 18:50, Tom Warren wrote:
> Mike,
> 
> On Tue, Jan 25, 2011 at 1:11 AM, Mike Rapoport <mike@compulab.co.il> wrote:
>> On 01/22/11 01:06, Tom Warren wrote:
>>> Signed-off-by: Tom Warren <twarren@nvidia.com>
>>> ---
>>
>> [ snip ]
>>
>>> +/*
>>> + * Routine: pin_mux_uart
>>> + * Description: setup the pin muxes/tristate values for a UART
>>> + */
>>> +static void pin_mux_uart(void)
>>> +{
>>> +     pinmux_tri_ctlr *const pmt = (pinmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
>>> +     u32 reg;
>>> +
>>> +#if CONFIG_TEGRA2_ENABLE_UARTA
>>> +             reg = readl(&pmt->pmt_ctl_c);
>>> +             reg &= 0xFFF0FFFF;      /* IRRX_/IRTX_SEL [19:16] = 00 UARTA */
>>> +             writel(reg, &pmt->pmt_ctl_c);
>>> +
>>> +             reg = readl(&pmt->pmt_tri_a);
>>> +             reg &= ~Z_IRRX;         /* Z_IRRX = normal (0) */
>>> +             reg &= ~Z_IRTX;         /* Z_IRTX = normal (0) */
>>> +             writel(reg, &pmt->pmt_tri_a);
>>> +#endif       /* CONFIG_TEGRA2_ENABLE_UARTA */
>>> +#if CONFIG_TEGRA2_ENABLE_UARTD
>>> +             reg = readl(&pmt->pmt_ctl_b);
>>> +             reg &= 0xFFFFFFF3;      /* GMC_SEL [3:2] = 00, UARTD */
>>> +             writel(reg, &pmt->pmt_ctl_b);
>>> +
>>> +             reg = readl(&pmt->pmt_tri_a);
>>> +             reg &= ~Z_GMC;          /* Z_GMC = normal (0) */
>>> +             writel(reg, &pmt->pmt_tri_a);
>>> +#endif       /* CONFIG_TEGRA2_ENABLE_UARTD */
>>
>> As I've already pointed out (1) this covers only one possibility of UART pin
>> muxing options. I agree that it makes sense when this is a part of the
>> board-specific code. However, forcing specific pins configuration in the generic
>> driver seems problematic to me, even if most Tegra2 boards use the same
>> configuration.
>> As a side note, I'd prefer to have all the pin multiplexing defined in one place
>> in board file rather than scattered among different drivers.
>>
> Alright. I'd like to get this wrapped up and accepted before the merge window
> closes so I can get on with the important bits (drivers, etc.). What
> would you like
> here? A generic function like 'pinmux_set_config(reg, val, bit)' that
> lives in the board
> files and gets called from the driver code with specifics of that
> board's/drivers pinmux
> config? Or do you see the pinmux code living entirely in the board
> files, and being done
> as part of board init? That's where it was before, BTW.

I think that the pinmux code should live entirely in the board file and
performed as part of board init. The drivers than can assume that the pins are
configured properly.

> If there are examples that you approve of in any extant U-Boot code (omap,
> ti91, davinci, etc.), please point them out.  I'd really like to
> finalize this patch series.

I think OMAP is a good example. There's set_muxconf_regs function in each board
file that is responsible for configuration of all the pins.

>> (1) http://thread.gmane.org/gmane.comp.boot-loaders.u-boot/92887/focus=93233
>>
>>
>> --
>> Sincerely yours,
>> Mike.
> Thanks,
> 
> Tom
>>


-- 
Sincerely yours,
Mike.

[U-Boot] [PATCH V5 2/4] serial: Add Tegra2 serial port support

[Tom Warren]

Mike,

On Tue, Jan 25, 2011 at 2:12 PM, Mike Rapoport <mike@compulab.co.il> wrote:
> On 01/25/11 18:50, Tom Warren wrote:
>> Mike,
>>
>> On Tue, Jan 25, 2011 at 1:11 AM, Mike Rapoport <mike@compulab.co.il> wrote:
>>> On 01/22/11 01:06, Tom Warren wrote:
>>>> Signed-off-by: Tom Warren <twarren@nvidia.com>
>>>> ---
>>>
>>> [ snip ]
>>>
>>>> +/*
>>>> + * Routine: pin_mux_uart
>>>> + * Description: setup the pin muxes/tristate values for a UART
>>>> + */
>>>> +static void pin_mux_uart(void)
>>>> +{
>>>> + ? ? pinmux_tri_ctlr *const pmt = (pinmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
>>>> + ? ? u32 reg;
>>>> +
>>>> +#if CONFIG_TEGRA2_ENABLE_UARTA
>>>> + ? ? ? ? ? ? reg = readl(&pmt->pmt_ctl_c);
>>>> + ? ? ? ? ? ? reg &= 0xFFF0FFFF; ? ? ?/* IRRX_/IRTX_SEL [19:16] = 00 UARTA */
>>>> + ? ? ? ? ? ? writel(reg, &pmt->pmt_ctl_c);
>>>> +
>>>> + ? ? ? ? ? ? reg = readl(&pmt->pmt_tri_a);
>>>> + ? ? ? ? ? ? reg &= ~Z_IRRX; ? ? ? ? /* Z_IRRX = normal (0) */
>>>> + ? ? ? ? ? ? reg &= ~Z_IRTX; ? ? ? ? /* Z_IRTX = normal (0) */
>>>> + ? ? ? ? ? ? writel(reg, &pmt->pmt_tri_a);
>>>> +#endif ? ? ? /* CONFIG_TEGRA2_ENABLE_UARTA */
>>>> +#if CONFIG_TEGRA2_ENABLE_UARTD
>>>> + ? ? ? ? ? ? reg = readl(&pmt->pmt_ctl_b);
>>>> + ? ? ? ? ? ? reg &= 0xFFFFFFF3; ? ? ?/* GMC_SEL [3:2] = 00, UARTD */
>>>> + ? ? ? ? ? ? writel(reg, &pmt->pmt_ctl_b);
>>>> +
>>>> + ? ? ? ? ? ? reg = readl(&pmt->pmt_tri_a);
>>>> + ? ? ? ? ? ? reg &= ~Z_GMC; ? ? ? ? ?/* Z_GMC = normal (0) */
>>>> + ? ? ? ? ? ? writel(reg, &pmt->pmt_tri_a);
>>>> +#endif ? ? ? /* CONFIG_TEGRA2_ENABLE_UARTD */
>>>
>>> As I've already pointed out (1) this covers only one possibility of UART pin
>>> muxing options. I agree that it makes sense when this is a part of the
>>> board-specific code. However, forcing specific pins configuration in the generic
>>> driver seems problematic to me, even if most Tegra2 boards use the same
>>> configuration.
>>> As a side note, I'd prefer to have all the pin multiplexing defined in one place
>>> in board file rather than scattered among different drivers.
>>>
>> Alright. I'd like to get this wrapped up and accepted before the merge window
>> closes so I can get on with the important bits (drivers, etc.). What
>> would you like
>> here? A generic function like 'pinmux_set_config(reg, val, bit)' that
>> lives in the board
>> files and gets called from the driver code with specifics of that
>> board's/drivers pinmux
>> config? Or do you see the pinmux code living entirely in the board
>> files, and being done
>> as part of board init? That's where it was before, BTW.
>
> I think that the pinmux code should live entirely in the board file and
> performed as part of board init. The drivers than can assume that the pins are
> configured properly.
OK. I'll move the clock/pinmux init code into armv7/tegra/board.c
(since it's SoC-centric),
and call it during board_init().

>
>> If there are examples that you approve of in any extant U-Boot code (omap,
>> ti91, davinci, etc.), please point them out. ?I'd really like to
>> finalize this patch series.
>
> I think OMAP is a good example. There's set_muxconf_regs function in each board
> file that is responsible for configuration of all the pins.
I'll take a look. Thanks.
>
>>> (1) http://thread.gmane.org/gmane.comp.boot-loaders.u-boot/92887/focus=93233
>>>
>>>
>>> --
>>> Sincerely yours,
>>> Mike.
>> Thanks,
>>
>> Tom
>>>
>
>
> --
> Sincerely yours,
> Mike.
>

[U-Boot] [PATCH V5 2/4] serial: Add Tegra2 serial port support

[Tom Warren]

Mike et al,

On Tue, Jan 25, 2011 at 2:37 PM, Tom Warren <twarren.nvidia@gmail.com> wrote:
> Mike,
>
> On Tue, Jan 25, 2011 at 2:12 PM, Mike Rapoport <mike@compulab.co.il> wrote:
>> On 01/25/11 18:50, Tom Warren wrote:
>>> Mike,
>>>
>>> On Tue, Jan 25, 2011 at 1:11 AM, Mike Rapoport <mike@compulab.co.il> wrote:
>>>> On 01/22/11 01:06, Tom Warren wrote:
>>>>> Signed-off-by: Tom Warren <twarren@nvidia.com>
>>>>> ---
>>>>
>>>> [ snip ]
>>>>
>>>>> +/*
>>>>> + * Routine: pin_mux_uart
>>>>> + * Description: setup the pin muxes/tristate values for a UART
>>>>> + */
>>>>> +static void pin_mux_uart(void)
>>>>> +{
>>>>> + ? ? pinmux_tri_ctlr *const pmt = (pinmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
>>>>> + ? ? u32 reg;
>>>>> +
>>>>> +#if CONFIG_TEGRA2_ENABLE_UARTA
>>>>> + ? ? ? ? ? ? reg = readl(&pmt->pmt_ctl_c);
>>>>> + ? ? ? ? ? ? reg &= 0xFFF0FFFF; ? ? ?/* IRRX_/IRTX_SEL [19:16] = 00 UARTA */
>>>>> + ? ? ? ? ? ? writel(reg, &pmt->pmt_ctl_c);
>>>>> +
>>>>> + ? ? ? ? ? ? reg = readl(&pmt->pmt_tri_a);
>>>>> + ? ? ? ? ? ? reg &= ~Z_IRRX; ? ? ? ? /* Z_IRRX = normal (0) */
>>>>> + ? ? ? ? ? ? reg &= ~Z_IRTX; ? ? ? ? /* Z_IRTX = normal (0) */
>>>>> + ? ? ? ? ? ? writel(reg, &pmt->pmt_tri_a);
>>>>> +#endif ? ? ? /* CONFIG_TEGRA2_ENABLE_UARTA */
>>>>> +#if CONFIG_TEGRA2_ENABLE_UARTD
>>>>> + ? ? ? ? ? ? reg = readl(&pmt->pmt_ctl_b);
>>>>> + ? ? ? ? ? ? reg &= 0xFFFFFFF3; ? ? ?/* GMC_SEL [3:2] = 00, UARTD */
>>>>> + ? ? ? ? ? ? writel(reg, &pmt->pmt_ctl_b);
>>>>> +
>>>>> + ? ? ? ? ? ? reg = readl(&pmt->pmt_tri_a);
>>>>> + ? ? ? ? ? ? reg &= ~Z_GMC; ? ? ? ? ?/* Z_GMC = normal (0) */
>>>>> + ? ? ? ? ? ? writel(reg, &pmt->pmt_tri_a);
>>>>> +#endif ? ? ? /* CONFIG_TEGRA2_ENABLE_UARTD */
>>>>
>>>> As I've already pointed out (1) this covers only one possibility of UART pin
>>>> muxing options. I agree that it makes sense when this is a part of the
>>>> board-specific code. However, forcing specific pins configuration in the generic
>>>> driver seems problematic to me, even if most Tegra2 boards use the same
>>>> configuration.
>>>> As a side note, I'd prefer to have all the pin multiplexing defined in one place
>>>> in board file rather than scattered among different drivers.
>>>>
>>> Alright. I'd like to get this wrapped up and accepted before the merge window
>>> closes so I can get on with the important bits (drivers, etc.). What
>>> would you like
>>> here? A generic function like 'pinmux_set_config(reg, val, bit)' that
>>> lives in the board
>>> files and gets called from the driver code with specifics of that
>>> board's/drivers pinmux
>>> config? Or do you see the pinmux code living entirely in the board
>>> files, and being done
>>> as part of board init? That's where it was before, BTW.
>>
>> I think that the pinmux code should live entirely in the board file and
>> performed as part of board init. The drivers than can assume that the pins are
>> configured properly.
> OK. I'll move the clock/pinmux init code into armv7/tegra/board.c
> (since it's SoC-centric),
> and call it during board_init().
Actually, I think it makes more sense to move pinmux_init_uart and
clock_init_uart to board/nvidia/common/board.c.
These routines are more board-specific than SoC-specific - they depend
on how the UART is routed on a board.
Let me do that & gen up a new patchset.

>
>>
>>> If there are examples that you approve of in any extant U-Boot code (omap,
>>> ti91, davinci, etc.), please point them out. ?I'd really like to
>>> finalize this patch series.
>>
>> I think OMAP is a good example. There's set_muxconf_regs function in each board
>> file that is responsible for configuration of all the pins.
> I'll take a look. Thanks.
>>
>>>> (1) http://thread.gmane.org/gmane.comp.boot-loaders.u-boot/92887/focus=93233
>>>>
>>>>
>>>> --
>>>> Sincerely yours,
>>>> Mike.
>>> Thanks,
>>>
>>> Tom
>>>>
>>
>>
>> --
>> Sincerely yours,
>> Mike.
>>
>

[U-Boot] [PATCH V5 2/4] serial: Add Tegra2 serial port support

[Peter Tyser]

> >>>> [ snip ]
> >>>>
> >>>>> +/*
> >>>>> + * Routine: pin_mux_uart
> >>>>> + * Description: setup the pin muxes/tristate values for a UART
> >>>>> + */
> >>>>> +static void pin_mux_uart(void)
> >>>>> +{
> >>>>> +     pinmux_tri_ctlr *const pmt = (pinmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
> >>>>> +     u32 reg;
> >>>>> +
> >>>>> +#if CONFIG_TEGRA2_ENABLE_UARTA
> >>>>> +             reg = readl(&pmt->pmt_ctl_c);
> >>>>> +             reg &= 0xFFF0FFFF;      /* IRRX_/IRTX_SEL [19:16] = 00 UARTA */
> >>>>> +             writel(reg, &pmt->pmt_ctl_c);
> >>>>> +
> >>>>> +             reg = readl(&pmt->pmt_tri_a);
> >>>>> +             reg &= ~Z_IRRX;         /* Z_IRRX = normal (0) */
> >>>>> +             reg &= ~Z_IRTX;         /* Z_IRTX = normal (0) */
> >>>>> +             writel(reg, &pmt->pmt_tri_a);
> >>>>> +#endif       /* CONFIG_TEGRA2_ENABLE_UARTA */
> >>>>> +#if CONFIG_TEGRA2_ENABLE_UARTD
> >>>>> +             reg = readl(&pmt->pmt_ctl_b);
> >>>>> +             reg &= 0xFFFFFFF3;      /* GMC_SEL [3:2] = 00, UARTD */
> >>>>> +             writel(reg, &pmt->pmt_ctl_b);
> >>>>> +
> >>>>> +             reg = readl(&pmt->pmt_tri_a);
> >>>>> +             reg &= ~Z_GMC;          /* Z_GMC = normal (0) */
> >>>>> +             writel(reg, &pmt->pmt_tri_a);
> >>>>> +#endif       /* CONFIG_TEGRA2_ENABLE_UARTD */
> >>>>
> >>>> As I've already pointed out (1) this covers only one possibility of UART pin
> >>>> muxing options. I agree that it makes sense when this is a part of the
> >>>> board-specific code. However, forcing specific pins configuration in the generic
> >>>> driver seems problematic to me, even if most Tegra2 boards use the same
> >>>> configuration.
> >>>> As a side note, I'd prefer to have all the pin multiplexing defined in one place
> >>>> in board file rather than scattered among different drivers.
> >>>>
> >>> Alright. I'd like to get this wrapped up and accepted before the merge window
> >>> closes so I can get on with the important bits (drivers, etc.). What
> >>> would you like
> >>> here? A generic function like 'pinmux_set_config(reg, val, bit)' that
> >>> lives in the board
> >>> files and gets called from the driver code with specifics of that
> >>> board's/drivers pinmux
> >>> config? Or do you see the pinmux code living entirely in the board
> >>> files, and being done
> >>> as part of board init? That's where it was before, BTW.
> >>
> >> I think that the pinmux code should live entirely in the board file and
> >> performed as part of board init. The drivers than can assume that the pins are
> >> configured properly.
> > OK. I'll move the clock/pinmux init code into armv7/tegra/board.c
> > (since it's SoC-centric),
> > and call it during board_init().
> Actually, I think it makes more sense to move pinmux_init_uart and
> clock_init_uart to board/nvidia/common/board.c.
> These routines are more board-specific than SoC-specific - they depend
> on how the UART is routed on a board.
> Let me do that & gen up a new patchset.

You previously mentioned that "To date, all of our Tegra boards use
these pinmux options for both UARTs.  If a board vendor chooses to use
different pinmuxes, then they can override these funcs in their board
files, or use their own code triggered by their own defines. But
according to our HW guys, the vast majority will use these pins"

If the vast majority of boards really will use the same pinmuxing, it
would be nice to provide that common muxing as a default which can be
overridden.  Perhaps moving pinmux_init_uart() and uart_clock_init()
into armv7/tegra/*, and making them weak functions would make everyone
happy.

Or could you make default defines that board's could override as needed?
eg in pin_mux_uart():
#ifndef CONFIG_TEGRA2_PMT_CTLC_MASK
#define CONFIG_TEGRA2_PMC_CTLC_MASK 0xfff0ffff
#endif
#ifndef CONFIG_TEGRA2_PMT_TRI_A_MASK
#define CONFIG_TEGRA2_PMC_TRI_A_MASK ~(Z_IRRX | Z_IRTX)
#endif
pin_mux_uart() {
	reg = readl(&pmt->pmt_ctl_c);
	reg &= CONFIG_TEGRA2_PMT_CTLC_MASK;
	writel(reg, &pmt->pmt_ctl_c);

	reg = readl(&pmt->pmt_tri_a);
	reg &= CONFIG_TEGRA2_PMC_TRI_A_MASK;
	writel(reg, &pmt->pmt_tri_a);
}

Or make the functions table driven so each board would define a
pinmux/clock configuration table?

I think its worthwhile to try and reduce duplicated code whenever
possible.

Best,
Peter

[U-Boot] [PATCH V5 2/4] serial: Add Tegra2 serial port support

[Mike Rapoport]

On 01/26/11 00:24, Peter Tyser wrote:
>>>>>> As I've already pointed out (1) this covers only one possibility of UART pin
>>>>>> muxing options. I agree that it makes sense when this is a part of the
>>>>>> board-specific code. However, forcing specific pins configuration in the generic
>>>>>> driver seems problematic to me, even if most Tegra2 boards use the same
>>>>>> configuration.
>>>>>> As a side note, I'd prefer to have all the pin multiplexing defined in one place
>>>>>> in board file rather than scattered among different drivers.
>>>>>>
>>>>> Alright. I'd like to get this wrapped up and accepted before the merge window
>>>>> closes so I can get on with the important bits (drivers, etc.). What
>>>>> would you like
>>>>> here? A generic function like 'pinmux_set_config(reg, val, bit)' that
>>>>> lives in the board
>>>>> files and gets called from the driver code with specifics of that
>>>>> board's/drivers pinmux
>>>>> config? Or do you see the pinmux code living entirely in the board
>>>>> files, and being done
>>>>> as part of board init? That's where it was before, BTW.
>>>>
>>>> I think that the pinmux code should live entirely in the board file and
>>>> performed as part of board init. The drivers than can assume that the pins are
>>>> configured properly.
>>> OK. I'll move the clock/pinmux init code into armv7/tegra/board.c
>>> (since it's SoC-centric),
>>> and call it during board_init().
>> Actually, I think it makes more sense to move pinmux_init_uart and
>> clock_init_uart to board/nvidia/common/board.c.
>> These routines are more board-specific than SoC-specific - they depend
>> on how the UART is routed on a board.
>> Let me do that & gen up a new patchset.
> 
> You previously mentioned that "To date, all of our Tegra boards use
> these pinmux options for both UARTs.  If a board vendor chooses to use
> different pinmuxes, then they can override these funcs in their board
> files, or use their own code triggered by their own defines. But
> according to our HW guys, the vast majority will use these pins"
> 
> If the vast majority of boards really will use the same pinmuxing, it
> would be nice to provide that common muxing as a default which can be
> overridden.  Perhaps moving pinmux_init_uart() and uart_clock_init()
> into armv7/tegra/*, and making them weak functions would make everyone
> happy.

My point was that pin muxing belongs to the board code rather than to the
driver. Driver should just assume that pins are configured elsewhere and it does
not need to deal with pin muxing at all.
Moreover, I'd prefer to see pinmux_board_init or something similar that
configures all the pins at once rather than collection of pinmux_init_uart,
pinmux_init_sdmmc, pinmux_init_gmi etc that will grow as more drivers are added.

> Or could you make default defines that board's could override as needed?
> eg in pin_mux_uart():
> #ifndef CONFIG_TEGRA2_PMT_CTLC_MASK
> #define CONFIG_TEGRA2_PMC_CTLC_MASK 0xfff0ffff
> #endif
> #ifndef CONFIG_TEGRA2_PMT_TRI_A_MASK
> #define CONFIG_TEGRA2_PMC_TRI_A_MASK ~(Z_IRRX | Z_IRTX)
> #endif
> pin_mux_uart() {
> 	reg = readl(&pmt->pmt_ctl_c);
> 	reg &= CONFIG_TEGRA2_PMT_CTLC_MASK;
> 	writel(reg, &pmt->pmt_ctl_c);
> 
> 	reg = readl(&pmt->pmt_tri_a);
> 	reg &= CONFIG_TEGRA2_PMC_TRI_A_MASK;
> 	writel(reg, &pmt->pmt_tri_a);
> }
> 
> Or make the functions table driven so each board would define a
> pinmux/clock configuration table?
> 
> I think its worthwhile to try and reduce duplicated code whenever
> possible.
> 
> Best,
> Peter
> 

-- 
Sincerely yours,
Mike.

[U-Boot] [PATCH V5 2/4] serial: Add Tegra2 serial port support

[Peter Tyser]

On Wed, 2011-01-26 at 10:13 +0200, Mike Rapoport wrote:
> On 01/26/11 00:24, Peter Tyser wrote:
> >>>>>> As I've already pointed out (1) this covers only one possibility of UART pin
> >>>>>> muxing options. I agree that it makes sense when this is a part of the
> >>>>>> board-specific code. However, forcing specific pins configuration in the generic
> >>>>>> driver seems problematic to me, even if most Tegra2 boards use the same
> >>>>>> configuration.
> >>>>>> As a side note, I'd prefer to have all the pin multiplexing defined in one place
> >>>>>> in board file rather than scattered among different drivers.
> >>>>>>
> >>>>> Alright. I'd like to get this wrapped up and accepted before the merge window
> >>>>> closes so I can get on with the important bits (drivers, etc.). What
> >>>>> would you like
> >>>>> here? A generic function like 'pinmux_set_config(reg, val, bit)' that
> >>>>> lives in the board
> >>>>> files and gets called from the driver code with specifics of that
> >>>>> board's/drivers pinmux
> >>>>> config? Or do you see the pinmux code living entirely in the board
> >>>>> files, and being done
> >>>>> as part of board init? That's where it was before, BTW.
> >>>>
> >>>> I think that the pinmux code should live entirely in the board file and
> >>>> performed as part of board init. The drivers than can assume that the pins are
> >>>> configured properly.
> >>> OK. I'll move the clock/pinmux init code into armv7/tegra/board.c
> >>> (since it's SoC-centric),
> >>> and call it during board_init().
> >> Actually, I think it makes more sense to move pinmux_init_uart and
> >> clock_init_uart to board/nvidia/common/board.c.
> >> These routines are more board-specific than SoC-specific - they depend
> >> on how the UART is routed on a board.
> >> Let me do that & gen up a new patchset.
> > 
> > You previously mentioned that "To date, all of our Tegra boards use
> > these pinmux options for both UARTs.  If a board vendor chooses to use
> > different pinmuxes, then they can override these funcs in their board
> > files, or use their own code triggered by their own defines. But
> > according to our HW guys, the vast majority will use these pins"
> > 
> > If the vast majority of boards really will use the same pinmuxing, it
> > would be nice to provide that common muxing as a default which can be
> > overridden.  Perhaps moving pinmux_init_uart() and uart_clock_init()
> > into armv7/tegra/*, and making them weak functions would make everyone
> > happy.
> 
> My point was that pin muxing belongs to the board code rather than to the
> driver. Driver should just assume that pins are configured elsewhere and it does
> not need to deal with pin muxing at all.

I understand your point, but think if 9/10 boards use the same pin
muxing its good to provide a default so we don't have 9 chunks of
duplicate code floating around in board/*.  What's the harm in providing
a default?  It can be overridden if needed.

> Moreover, I'd prefer to see pinmux_board_init or something similar that
> configures all the pins at once rather than collection of pinmux_init_uart,
> pinmux_init_sdmmc, pinmux_init_gmi etc that will grow as more drivers are added.

I can see that point but its a different discussion.  I don't know
enough about the Tegra2 to comment on this, but it seems like a good
idea based on previous experiences with boards with similar pinmuxing
(eg mpc8260).  In my last email I mentioned a table-driven approach
(similar to the mpc8260 implementation?) which sounds somewhat like
you're proposing.

Best,
Peter

[U-Boot] [PATCH V5 2/4] serial: Add Tegra2 serial port support

[Mike Rapoport]

On 01/26/11 17:58, Peter Tyser wrote:
> On Wed, 2011-01-26 at 10:13 +0200, Mike Rapoport wrote:
>> On 01/26/11 00:24, Peter Tyser wrote:
> 
>> Moreover, I'd prefer to see pinmux_board_init or something similar that
>> configures all the pins at once rather than collection of pinmux_init_uart,
>> pinmux_init_sdmmc, pinmux_init_gmi etc that will grow as more drivers are added.
> 
> I can see that point but its a different discussion.  I don't know
> enough about the Tegra2 to comment on this, but it seems like a good
> idea based on previous experiences with boards with similar pinmuxing
> (eg mpc8260).  In my last email I mentioned a table-driven approach
> (similar to the mpc8260 implementation?) which sounds somewhat like
> you're proposing.

Yes, I was thinking about table-driven approach, though slightly more
complicated than in mpc8260 :)
I think we can mostly reuse the Linux implementation of Tegra2 pinmux (1 and 2):
However, the pinmuxing API can be added after the basic Tegra2 support is
merged, IMO.

(1)
http://git.kernel.org/?p=linux/kernel/git/torvalds/linux-2.6.git;a=blob;f=arch/arm/mach-tegra/pinmux.c;h=f80d507671bc1b22921ab2821c8a2cde427f1b5f;hb=HEAD
(2)
http://git.kernel.org/?p=linux/kernel/git/torvalds/linux-2.6.git;a=blob;f=arch/arm/mach-tegra/pinmux-t2-tables.c;h=a6ea34e782dc339091b49e54871f953048651ad3;hb=HEAD


> Best,
> Peter
> 


-- 
Sincerely yours,
Mike.

[U-Boot] [PATCH V5 2/4] serial: Add Tegra2 serial port support

[Tom Warren]

Mike,

On Wed, Jan 26, 2011 at 1:13 AM, Mike Rapoport <mike@compulab.co.il> wrote:
> On 01/26/11 00:24, Peter Tyser wrote:
>>>>>>> As I've already pointed out (1) this covers only one possibility of UART pin
>>>>>>> muxing options. I agree that it makes sense when this is a part of the
>>>>>>> board-specific code. However, forcing specific pins configuration in the generic
>>>>>>> driver seems problematic to me, even if most Tegra2 boards use the same
>>>>>>> configuration.
>>>>>>> As a side note, I'd prefer to have all the pin multiplexing defined in one place
>>>>>>> in board file rather than scattered among different drivers.
>>>>>>>
>>>>>> Alright. I'd like to get this wrapped up and accepted before the merge window
>>>>>> closes so I can get on with the important bits (drivers, etc.). What
>>>>>> would you like
>>>>>> here? A generic function like 'pinmux_set_config(reg, val, bit)' that
>>>>>> lives in the board
>>>>>> files and gets called from the driver code with specifics of that
>>>>>> board's/drivers pinmux
>>>>>> config? Or do you see the pinmux code living entirely in the board
>>>>>> files, and being done
>>>>>> as part of board init? That's where it was before, BTW.
>>>>>
>>>>> I think that the pinmux code should live entirely in the board file and
>>>>> performed as part of board init. The drivers than can assume that the pins are
>>>>> configured properly.
>>>> OK. I'll move the clock/pinmux init code into armv7/tegra/board.c
>>>> (since it's SoC-centric),
>>>> and call it during board_init().
>>> Actually, I think it makes more sense to move pinmux_init_uart and
>>> clock_init_uart to board/nvidia/common/board.c.
>>> These routines are more board-specific than SoC-specific - they depend
>>> on how the UART is routed on a board.
>>> Let me do that & gen up a new patchset.
>>
>> You previously mentioned that "To date, all of our Tegra boards use
>> these pinmux options for both UARTs. ?If a board vendor chooses to use
>> different pinmuxes, then they can override these funcs in their board
>> files, or use their own code triggered by their own defines. But
>> according to our HW guys, the vast majority will use these pins"
>>
>> If the vast majority of boards really will use the same pinmuxing, it
>> would be nice to provide that common muxing as a default which can be
>> overridden. ?Perhaps moving pinmux_init_uart() and uart_clock_init()
>> into armv7/tegra/*, and making them weak functions would make everyone
>> happy.
>
> My point was that pin muxing belongs to the board code rather than to the
> driver. Driver should just assume that pins are configured elsewhere and it does
> not need to deal with pin muxing at all.
I understand that point - sorry if I wasn't clear. No objection to
having pinmux code in board files.

> Moreover, I'd prefer to see pinmux_board_init or something similar that
> configures all the pins at once rather than collection of pinmux_init_uart,
> pinmux_init_sdmmc, pinmux_init_gmi etc that will grow as more drivers are added.
>
I see a couple of reasons not to do it that way. First, I don't know
at this time what all the pinmux settings will be, since I haven't
ported all the periph driver code yet. It's vastly different from
what's acceptable in U-Boot, and will all need significant rewrite.
It'd take me a week to gather all that info, and I'm not at full BW on
this project (one of 4 on my plate right now).
Second, I've been chastised before for including code/features in this
initial patchset that aren't needed or used.  I'm trying to keep the
code as simple as possible to make it easier on reviewers and get
through the review in as short a time as possible. This has already
dragged on far longer than I thought it would.
I'm willing to change the pinmux code to make it as generic as
possible, but only if there's a consensus on the list that it has to
be that way to get accepted & pushed.
>> Or could you make default defines that board's could override as needed?
>> eg in pin_mux_uart():
>> #ifndef CONFIG_TEGRA2_PMT_CTLC_MASK
>> #define CONFIG_TEGRA2_PMC_CTLC_MASK 0xfff0ffff
>> #endif
>> #ifndef CONFIG_TEGRA2_PMT_TRI_A_MASK
>> #define CONFIG_TEGRA2_PMC_TRI_A_MASK ~(Z_IRRX | Z_IRTX)
>> #endif
>> pin_mux_uart() {
>> ? ? ? reg = readl(&pmt->pmt_ctl_c);
>> ? ? ? reg &= CONFIG_TEGRA2_PMT_CTLC_MASK;
>> ? ? ? writel(reg, &pmt->pmt_ctl_c);
>>
>> ? ? ? reg = readl(&pmt->pmt_tri_a);
>> ? ? ? reg &= CONFIG_TEGRA2_PMC_TRI_A_MASK;
>> ? ? ? writel(reg, &pmt->pmt_tri_a);
>> }
>>
>> Or make the functions table driven so each board would define a
>> pinmux/clock configuration table?
>>
>> I think its worthwhile to try and reduce duplicated code whenever
>> possible.
>>
>> Best,
>> Peter
>>
>
> --
> Sincerely yours,
> Mike.
>
Thanks,
Tom

[U-Boot] [PATCH V5 2/4] serial: Add Tegra2 serial port support

[Mike Rapoport]

Tom,

On 01/26/11 19:05, Tom Warren wrote:
> Mike,
> 
> On Wed, Jan 26, 2011 at 1:13 AM, Mike Rapoport <mike@compulab.co.il> wrote:
>> My point was that pin muxing belongs to the board code rather than to the
>> driver. Driver should just assume that pins are configured elsewhere and it does
>> not need to deal with pin muxing at all.
> I understand that point - sorry if I wasn't clear. No objection to
> having pinmux code in board files.
> 
>> Moreover, I'd prefer to see pinmux_board_init or something similar that
>> configures all the pins at once rather than collection of pinmux_init_uart,
>> pinmux_init_sdmmc, pinmux_init_gmi etc that will grow as more drivers are added.
>>
> I see a couple of reasons not to do it that way. First, I don't know
> at this time what all the pinmux settings will be, since I haven't
> ported all the periph driver code yet. It's vastly different from
> what's acceptable in U-Boot, and will all need significant rewrite.
> It'd take me a week to gather all that info, and I'm not at full BW on
> this project (one of 4 on my plate right now).
> Second, I've been chastised before for including code/features in this
> initial patchset that aren't needed or used.  I'm trying to keep the
> code as simple as possible to make it easier on reviewers and get
> through the review in as short a time as possible. This has already
> dragged on far longer than I thought it would.
> I'm willing to change the pinmux code to make it as generic as
> possible, but only if there's a consensus on the list that it has to
> be that way to get accepted & pushed.

I'm Ok with pinmux_init_uart in the board code for now. I think that the generic
pinmux functionality can be added afterwards.

>>
> Thanks,
> Tom


-- 
Sincerely yours,
Mike.

[U-Boot] [PATCH V5 2/4] serial: Add Tegra2 serial port support

[Tom Warren]

Mike,

On Thu, Jan 27, 2011 at 12:41 AM, Mike Rapoport <mike@compulab.co.il> wrote:
> Tom,
>
> On 01/26/11 19:05, Tom Warren wrote:
>> Mike,
>>
>> On Wed, Jan 26, 2011 at 1:13 AM, Mike Rapoport <mike@compulab.co.il> wrote:
>>> My point was that pin muxing belongs to the board code rather than to the
>>> driver. Driver should just assume that pins are configured elsewhere and it does
>>> not need to deal with pin muxing at all.
>> I understand that point - sorry if I wasn't clear. No objection to
>> having pinmux code in board files.
>>
>>> Moreover, I'd prefer to see pinmux_board_init or something similar that
>>> configures all the pins at once rather than collection of pinmux_init_uart,
>>> pinmux_init_sdmmc, pinmux_init_gmi etc that will grow as more drivers are added.
>>>
>> I see a couple of reasons not to do it that way. First, I don't know
>> at this time what all the pinmux settings will be, since I haven't
>> ported all the periph driver code yet. It's vastly different from
>> what's acceptable in U-Boot, and will all need significant rewrite.
>> It'd take me a week to gather all that info, and I'm not at full BW on
>> this project (one of 4 on my plate right now).
>> Second, I've been chastised before for including code/features in this
>> initial patchset that aren't needed or used. ?I'm trying to keep the
>> code as simple as possible to make it easier on reviewers and get
>> through the review in as short a time as possible. This has already
>> dragged on far longer than I thought it would.
>> I'm willing to change the pinmux code to make it as generic as
>> possible, but only if there's a consensus on the list that it has to
>> be that way to get accepted & pushed.
>
> I'm Ok with pinmux_init_uart in the board code for now. I think that the generic
> pinmux functionality can be added afterwards.
>
Great. My main goal is to get the baseline Tegra2 support in upstream
U-Boot. I'm happy to refine the pinmux approach in the next patchset.
Either a generic pinmux as you propose, or a set of weak pinmux
configs that can be overridden by another board design, etc. as Peter
proposes.

>>>
>> Thanks,
>> Tom
>
>
> --
> Sincerely yours,
> Mike.
>
Thanks,
Tom

[U-Boot] [PATCH V5 3/4] arm: Tegra2: Add support for NVIDIA Harmony board

[Tom Warren]

Signed-off-by: Tom Warren <twarren@nvidia.com>
---
Changes for V2:
	- Use board/nvidia/ instead of /board/tegra
	- Change nv-common.h config file to tegra2-common.h

 MAINTAINERS                     |    4 +
 board/nvidia/harmony/Makefile   |   50 ++++++++++++
 boards.cfg                      |    1 +
 include/configs/harmony.h       |   48 ++++++++++++
 include/configs/tegra2-common.h |  160 +++++++++++++++++++++++++++++++++++++++
 5 files changed, 263 insertions(+), 0 deletions(-)
 create mode 100644 board/nvidia/harmony/Makefile
 create mode 100644 include/configs/harmony.h
 create mode 100644 include/configs/tegra2-common.h

diff --git a/MAINTAINERS b/MAINTAINERS
index ba83f71..b5cff19 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -841,6 +841,10 @@ Prafulla Wadaskar <prafulla@marvell.com>
 	rd6281a		ARM926EJS (Kirkwood SoC)
 	sheevaplug	ARM926EJS (Kirkwood SoC)
 
+Tom Warren <twarren@nvidia.com>
+
+	harmony		Tegra2 (ARM7 & A9 Dual Core)
+
 Matthias Weisser <weisserm@arcor.de>
 
 	jadecpu		ARM926EJS (MB86R01 SoC)
diff --git a/board/nvidia/harmony/Makefile b/board/nvidia/harmony/Makefile
new file mode 100644
index 0000000..3a146cb
--- /dev/null
+++ b/board/nvidia/harmony/Makefile
@@ -0,0 +1,50 @@
+#
+#  (C) Copyright 2010,2011
+#  NVIDIA Corporation <www.nvidia.com>
+#
+#
+#  See file CREDITS for list of people who contributed to this
+#  project.
+#
+#  This program is free software; you can redistribute it and/or
+#  modify it under the terms of the GNU General Public License as
+#  published by the Free Software Foundation; either version 2 of
+#  the License, or (at your option) any later version.
+#
+#  This program is distributed in the hope that it will be useful,
+#  but WITHOUT ANY WARRANTY; without even the implied warranty of
+#  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+#  GNU General Public License for more details.
+#
+#  You should have received a copy of the GNU General Public License
+#  along with this program; if not, write to the Free Software
+#  Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+#  MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	+= ../common/board.o
+
+SRCS	:= $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS)
+
+clean:
+	rm -f $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/boards.cfg b/boards.cfg
index 94b8745..ee7c4b7 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -122,6 +122,7 @@ omap4_panda                  arm         armv7       panda               ti
 omap4_sdp4430                arm         armv7       sdp4430             ti             omap4
 s5p_goni                     arm         armv7       goni                samsung        s5pc1xx
 smdkc100                     arm         armv7       smdkc100            samsung        s5pc1xx
+harmony                      arm         armv7       harmony             nvidia         tegra2
 actux1                       arm         ixp
 actux2                       arm         ixp
 actux3                       arm         ixp
diff --git a/include/configs/harmony.h b/include/configs/harmony.h
new file mode 100644
index 0000000..7d8f27a
--- /dev/null
+++ b/include/configs/harmony.h
@@ -0,0 +1,48 @@
+/*
+ *  (C) Copyright 2010,2011
+ *  NVIDIA Corporation <www.nvidia.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <asm/sizes.h>
+#include "tegra2-common.h"
+
+/* High-level configuration options */
+#define TEGRA2_SYSMEM		"mem=384M at 0M nvmem=128M at 384M mem=512M at 512M"
+#define V_PROMPT		"Tegra2 (Harmony) # "
+#define CONFIG_TEGRA2_BOARD_STRING	"NVIDIA Harmony"
+
+/* Board-specific serial config */
+#define CONFIG_SERIAL_MULTI
+#define CONFIG_TEGRA2_ENABLE_UARTD	1
+#define CONFIG_TEGRA2_ENABLE_UARTA	0
+
+/* UARTD: keyboard satellite board uart, default */
+#define CONFIG_SYS_NS16550_COM1		NV_PA_APB_UARTD_BASE
+/* UARTA: debug board uart */
+#define CONFIG_SYS_NS16550_COM2		NV_PA_APB_UARTA_BASE
+
+#define CONFIG_MACH_TYPE		MACH_TYPE_HARMONY
+#define CONFIG_SYS_BOARD_ODMDATA	0x300d8011 /* lp1, 1GB */
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/tegra2-common.h b/include/configs/tegra2-common.h
new file mode 100644
index 0000000..4f4374a
--- /dev/null
+++ b/include/configs/tegra2-common.h
@@ -0,0 +1,160 @@
+/*
+ *  (C) Copyright 2010,2011
+ *  NVIDIA Corporation <www.nvidia.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __TEGRA2_COMMON_H
+#define __TEGRA2_COMMON_H
+#include <asm/sizes.h>
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_ARMCORTEXA9		/* This is an ARM V7 CPU core */
+#define CONFIG_TEGRA2			/* in a NVidia Tegra2 core */
+#define CONFIG_MACH_TEGRA_GENERIC	/* which is a Tegra generic machine */
+#define CONFIG_L2_OFF			/* No L2 cache */
+
+#include <asm/arch/tegra2.h>		/* get chip and board defs */
+
+/*
+ * Display CPU and Board information
+ */
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+
+#define CONFIG_SKIP_RELOCATE_UBOOT
+#define CONFIG_SKIP_LOWLEVEL_INIT
+
+#define CONFIG_CMDLINE_TAG		/* enable passing of ATAGs */
+
+/* Environment */
+#define CONFIG_ENV_IS_NOWHERE
+#define CONFIG_ENV_SIZE			0x20000	/* Total Size Environment */
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN		(4 << 20)	/* 4MB  */
+
+/*
+ * PllX Configuration
+ */
+#define CONFIG_SYS_CPU_OSC_FREQUENCY	1000000	/* Set CPU clock to 1GHz */
+
+/*
+ * NS16550 Configuration
+ */
+#define V_NS16550_CLK			216000000	/* 216MHz (pllp_out0) */
+
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
+#define CONFIG_SYS_NS16550_CLK		V_NS16550_CLK
+
+/*
+ * select serial console configuration
+ */
+#define CONFIG_CONS_INDEX	1
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_BAUDRATE			115200
+#define CONFIG_SYS_BAUDRATE_TABLE	{4800, 9600, 19200, 38400, 57600,\
+					115200}
+
+/* include default commands */
+#include <config_cmd_default.h>
+
+/* remove unused commands */
+#undef CONFIG_CMD_FLASH		/* flinfo, erase, protect */
+#undef CONFIG_CMD_FPGA		/* FPGA configuration support */
+#undef CONFIG_CMD_IMI
+#undef CONFIG_CMD_IMLS
+#undef CONFIG_CMD_NFS		/* NFS support */
+#undef CONFIG_CMD_NET		/* network support */
+
+/* turn on command-line edit/hist/auto */
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_COMMAND_HISTORY
+#define CONFIG_AUTOCOMPLETE
+
+#define CONFIG_SYS_NO_FLASH
+
+/* Environment information */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"console=ttyS0,115200n8\0" \
+	"mem=" TEGRA2_SYSMEM "\0" \
+	"smpflag=smp\0" \
+
+#define CONFIG_LOADADDR		0x408000	/* def. location for kernel */
+#define CONFIG_BOOTDELAY	2		/* -1 to disable auto boot */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP		/* undef to save memory */
+#define CONFIG_SYS_HUSH_PARSER		/* use "hush" command parser */
+#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
+#define CONFIG_SYS_PROMPT		V_PROMPT
+/*
+ * Increasing the size of the IO buffer as default nfsargs size is more
+ *  than 256 and so it is not possible to edit it
+ */
+#define CONFIG_SYS_CBSIZE		(256 * 2) /* Console I/O Buffer Size */
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
+					sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS		16	/* max number of command args */
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE		(CONFIG_SYS_CBSIZE)
+
+#define CONFIG_SYS_MEMTEST_START	(TEGRA2_SDRC_CS0 + 0x600000)
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + 0x100000)
+
+#define CONFIG_SYS_LOAD_ADDR		(0xA00800)	/* default */
+#define CONFIG_SYS_HZ			1000
+
+/*-----------------------------------------------------------------------
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKBASE	0x2800000	/* 40MB */
+#define CONFIG_STACKSIZE	0x20000		/* 128K regular stack*/
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS	1
+#define PHYS_SDRAM_1		TEGRA2_SDRC_CS0
+#define PHYS_SDRAM_1_SIZE	0x20000000	/* 512M */
+
+#define CONFIG_SYS_TEXT_BASE	0x00E08000
+#define CONFIG_SYS_SDRAM_BASE	PHYS_SDRAM_1
+
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_STACKBASE
+#define CONFIG_SYS_INIT_RAM_SIZE	CONFIG_SYS_MALLOC_LEN
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INIT_RAM_ADDR + \
+						CONFIG_SYS_INIT_RAM_SIZE - \
+						GENERATED_GBL_DATA_SIZE)
+
+#endif /* __TEGRA2_COMMON_H */
-- 
1.7.3.5

[U-Boot] [PATCH V5 4/4] arm: Tegra2: Add support for NVIDIA Seaboard board

[Tom Warren]

Signed-off-by: Tom Warren <twarren@nvidia.com>
---
Changes for V2:
	- Remove mach-types.h change; wait for ARM kernel sync-up
	- Use board/nvidia instead of board/tegra

 MAINTAINERS                    |    1 +
 board/nvidia/seaboard/Makefile |   50 ++++++++++++++++++++++++++++++++++++++++
 boards.cfg                     |    1 +
 include/configs/seaboard.h     |   44 +++++++++++++++++++++++++++++++++++
 4 files changed, 96 insertions(+), 0 deletions(-)
 create mode 100644 board/nvidia/seaboard/Makefile
 create mode 100644 include/configs/seaboard.h

diff --git a/MAINTAINERS b/MAINTAINERS
index b5cff19..f4795d3 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -844,6 +844,7 @@ Prafulla Wadaskar <prafulla@marvell.com>
 Tom Warren <twarren@nvidia.com>
 
 	harmony		Tegra2 (ARM7 & A9 Dual Core)
+	seaboard	Tegra2 (ARM7 & A9 Dual Core)
 
 Matthias Weisser <weisserm@arcor.de>
 
diff --git a/board/nvidia/seaboard/Makefile b/board/nvidia/seaboard/Makefile
new file mode 100644
index 0000000..3a146cb
--- /dev/null
+++ b/board/nvidia/seaboard/Makefile
@@ -0,0 +1,50 @@
+#
+#  (C) Copyright 2010,2011
+#  NVIDIA Corporation <www.nvidia.com>
+#
+#
+#  See file CREDITS for list of people who contributed to this
+#  project.
+#
+#  This program is free software; you can redistribute it and/or
+#  modify it under the terms of the GNU General Public License as
+#  published by the Free Software Foundation; either version 2 of
+#  the License, or (at your option) any later version.
+#
+#  This program is distributed in the hope that it will be useful,
+#  but WITHOUT ANY WARRANTY; without even the implied warranty of
+#  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+#  GNU General Public License for more details.
+#
+#  You should have received a copy of the GNU General Public License
+#  along with this program; if not, write to the Free Software
+#  Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+#  MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	+= ../common/board.o
+
+SRCS	:= $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS)
+
+clean:
+	rm -f $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/boards.cfg b/boards.cfg
index ee7c4b7..3c4c249 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -123,6 +123,7 @@ omap4_sdp4430                arm         armv7       sdp4430             ti
 s5p_goni                     arm         armv7       goni                samsung        s5pc1xx
 smdkc100                     arm         armv7       smdkc100            samsung        s5pc1xx
 harmony                      arm         armv7       harmony             nvidia         tegra2
+seaboard                     arm         armv7       seaboard            nvidia         tegra2
 actux1                       arm         ixp
 actux2                       arm         ixp
 actux3                       arm         ixp
diff --git a/include/configs/seaboard.h b/include/configs/seaboard.h
new file mode 100644
index 0000000..98d82d6
--- /dev/null
+++ b/include/configs/seaboard.h
@@ -0,0 +1,44 @@
+/*
+ *  (C) Copyright 2010,2011
+ *  NVIDIA Corporation <www.nvidia.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <asm/sizes.h>
+#include "tegra2-common.h"
+
+/* High-level configuration options */
+#define TEGRA2_SYSMEM		"mem=384M at 0M nvmem=128M at 384M mem=512M at 512M"
+#define V_PROMPT		"Tegra2 (SeaBoard) # "
+#define CONFIG_TEGRA2_BOARD_STRING	"NVIDIA Seaboard"
+
+/* Board-specific serial config */
+#define CONFIG_SERIAL_MULTI
+#define CONFIG_TEGRA2_ENABLE_UARTA	0
+#define CONFIG_TEGRA2_ENABLE_UARTD	1
+#define CONFIG_SYS_NS16550_COM1		NV_PA_APB_UARTD_BASE
+
+#define CONFIG_MACH_TYPE		MACH_TYPE_TEGRA_SEABOARD
+#define CONFIG_SYS_BOARD_ODMDATA	0x300d8011 /* lp1, 1GB */
+
+#endif /* __CONFIG_H */
-- 
1.7.3.5