[PATCH V2 0/8] ARM: imx: add imx7ulp support

[PATCH V2 0/8] ARM: imx: add imx7ulp support

[A.s. Dong]

The i.MX 7ULP family of processors represents NXP?s latest achievement
in ultra-low-power processing for use cases demanding long battery life.
Targeted towards the growing market of portable devices, the i.MX 7ULP
family of processors features NXP's advanced implementation of the Arm?
Cortex?-A7 core, the Arm Cortex-M4 core, as well as a 3D and 2D Graphics
Processing Units (GPUs). The i.MX 7ULP family provides up to 32-bit
LPDDR2/LPDDR3 memory interface and a number of other interfaces for
connecting peripherals, such as WLAN, Bluetooth, GPS, displays, and
camera sensors.

This patch series adds the basic support for imx7ulp. It includes machine
level support code and device tree.
Note: it depends on clk driver which is still under review.

v1->v2:
 * switch to SPDX license
 * rebase to latest tree
 * pad name update
 * add gpio clk support
 * minor fix

Dong Aisheng (8):
  dt-bindings: fsl: add compatible for imx7ulp evk
  dt-bindings: fsl: add imx7ulp pm related components bindings
  dt-bindings: gpio: vf610: add optional clocks property
  gpio: vf610: add optional clock support
  ARM: imx: add initial support for imx7ulp
  dts: imx: add common imx7ulp dtsi support
  dts: fsl: add imx7ulp evk support
  ARM: imx_v6_v7_defconfig: add imx7ulp support

 .../bindings/arm/freescale/fsl,imx7ulp-pm.txt      |  23 ++
 Documentation/devicetree/bindings/arm/fsl.txt      |   8 +
 .../devicetree/bindings/gpio/gpio-vf610.txt        |   6 +
 arch/arm/boot/dts/Makefile                         |   2 +
 arch/arm/boot/dts/imx7ulp-evk.dts                  |  94 ++++++
 arch/arm/boot/dts/imx7ulp.dtsi                     | 323 +++++++++++++++++++++
 arch/arm/configs/imx_v6_v7_defconfig               |   1 +
 arch/arm/mach-imx/Kconfig                          |   9 +
 arch/arm/mach-imx/Makefile                         |   1 +
 arch/arm/mach-imx/common.h                         |   1 +
 arch/arm/mach-imx/cpu.c                            |   3 +
 arch/arm/mach-imx/mach-imx7ulp.c                   |  32 ++
 arch/arm/mach-imx/mxc.h                            |   1 +
 arch/arm/mach-imx/pm-imx7ulp.c                     |  28 ++
 drivers/gpio/gpio-vf610.c                          |  20 ++
 15 files changed, 552 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/arm/freescale/fsl,imx7ulp-pm.txt
 create mode 100644 arch/arm/boot/dts/imx7ulp-evk.dts
 create mode 100644 arch/arm/boot/dts/imx7ulp.dtsi
 create mode 100644 arch/arm/mach-imx/mach-imx7ulp.c
 create mode 100644 arch/arm/mach-imx/pm-imx7ulp.c

-- 
2.7.4

[PATCH V2 1/8] dt-bindings: fsl: add compatible for imx7ulp evk

[A.s. Dong]

Cc: devicetree@vger.kernel.org
Cc: Shawn Guo <shawnguo@kernel.org>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
---
 Documentation/devicetree/bindings/arm/fsl.txt | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/fsl.txt b/Documentation/devicetree/bindings/arm/fsl.txt
index 7b964d8..9c7c788 100644
--- a/Documentation/devicetree/bindings/arm/fsl.txt
+++ b/Documentation/devicetree/bindings/arm/fsl.txt
@@ -101,6 +101,10 @@ i.MX7 SabreSD Board
 Required root node properties:
     - compatible = "fsl,imx7d-sdb", "fsl,imx7d";
 
+i.MX7ULP Evaluation Kit
+Required root node properties:
+    - compatible = "fsl,imx7ulp-evk", "fsl,imx7ulp";
+
 Generic i.MX boards
 -------------------
 
@@ -123,6 +127,10 @@ i.MX6q generic board
 Required root node properties:
     - compatible = "fsl,imx6q";
 
+i.MX7ULP generic board
+Required root node properties:
+    - compatible = "fsl,imx7ulp";
+
 Freescale Vybrid Platform Device Tree Bindings
 ----------------------------------------------
 
-- 
2.7.4

[PATCH V2 1/8] dt-bindings: fsl: add compatible for imx7ulp evk

[A.s. Dong]

Cc: devicetree at vger.kernel.org
Cc: Shawn Guo <shawnguo@kernel.org>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
---
 Documentation/devicetree/bindings/arm/fsl.txt | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/fsl.txt b/Documentation/devicetree/bindings/arm/fsl.txt
index 7b964d8..9c7c788 100644
--- a/Documentation/devicetree/bindings/arm/fsl.txt
+++ b/Documentation/devicetree/bindings/arm/fsl.txt
@@ -101,6 +101,10 @@ i.MX7 SabreSD Board
 Required root node properties:
     - compatible = "fsl,imx7d-sdb", "fsl,imx7d";
 
+i.MX7ULP Evaluation Kit
+Required root node properties:
+    - compatible = "fsl,imx7ulp-evk", "fsl,imx7ulp";
+
 Generic i.MX boards
 -------------------
 
@@ -123,6 +127,10 @@ i.MX6q generic board
 Required root node properties:
     - compatible = "fsl,imx6q";
 
+i.MX7ULP generic board
+Required root node properties:
+    - compatible = "fsl,imx7ulp";
+
 Freescale Vybrid Platform Device Tree Bindings
 ----------------------------------------------
 
-- 
2.7.4

[PATCH V2 2/8] dt-bindings: fsl: add imx7ulp pm related components bindings

Add imx7ulp pm related components bindings

Cc: Rob Herring <robh+dt@kernel.org>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: devicetree@vger.kernel.org
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
---
ChangeLog:
v1->v2:
 * new patch
---
 .../bindings/arm/freescale/fsl,imx7ulp-pm.txt      | 23 ++++++++++++++++++++++
 1 file changed, 23 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/arm/freescale/fsl,imx7ulp-pm.txt

diff --git a/Documentation/devicetree/bindings/arm/freescale/fsl,imx7ulp-pm.txt b/Documentation/devicetree/bindings/arm/freescale/fsl,imx7ulp-pm.txt
new file mode 100644
index 0000000..75195be
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/freescale/fsl,imx7ulp-pm.txt
@@ -0,0 +1,23 @@
+Freescale i.MX7ULP Power Management Components
+----------------------------------------------
+
+The Multi-System Mode Controller (MSMC) is responsible for sequencing
+the MCU into and out of all stop and run power modes. Specifically, it
+monitors events to trigger transitions between power modes while
+controlling the power, clocks, and memories of the MCU to achieve the
+power consumption and functionality of that mode.
+
+The WFI or WFE instruction is used to invoke a Sleep, Deep Sleep or
+Standby modes for either Cortex family. Run, Wait, and Stop are the
+common terms used for the primary operating modes of Kinetis
+microcontrollers.
+
+Required properties:
+- compatible:	Should be "fsl,imx7ulp-smc1".
+- reg:		Specifies base physical address and size of the register sets.
+
+Example:
+smc1: smc1@40410000 {
+	compatible = "fsl,imx7ulp-smc1";
+	reg = <0x40410000 0x1000>;
+};
-- 
2.7.4

[PATCH V2 2/8] dt-bindings: fsl: add imx7ulp pm related components bindings

[A.s. Dong]

Add imx7ulp pm related components bindings

Cc: Rob Herring <robh+dt@kernel.org>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: devicetree at vger.kernel.org
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
---
ChangeLog:
v1->v2:
 * new patch
---
 .../bindings/arm/freescale/fsl,imx7ulp-pm.txt      | 23 ++++++++++++++++++++++
 1 file changed, 23 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/arm/freescale/fsl,imx7ulp-pm.txt

diff --git a/Documentation/devicetree/bindings/arm/freescale/fsl,imx7ulp-pm.txt b/Documentation/devicetree/bindings/arm/freescale/fsl,imx7ulp-pm.txt
new file mode 100644
index 0000000..75195be
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/freescale/fsl,imx7ulp-pm.txt
@@ -0,0 +1,23 @@
+Freescale i.MX7ULP Power Management Components
+----------------------------------------------
+
+The Multi-System Mode Controller (MSMC) is responsible for sequencing
+the MCU into and out of all stop and run power modes. Specifically, it
+monitors events to trigger transitions between power modes while
+controlling the power, clocks, and memories of the MCU to achieve the
+power consumption and functionality of that mode.
+
+The WFI or WFE instruction is used to invoke a Sleep, Deep Sleep or
+Standby modes for either Cortex family. Run, Wait, and Stop are the
+common terms used for the primary operating modes of Kinetis
+microcontrollers.
+
+Required properties:
+- compatible:	Should be "fsl,imx7ulp-smc1".
+- reg:		Specifies base physical address and size of the register sets.
+
+Example:
+smc1: smc1 at 40410000 {
+	compatible = "fsl,imx7ulp-smc1";
+	reg = <0x40410000 0x1000>;
+};
-- 
2.7.4

Re: [PATCH V2 2/8] dt-bindings: fsl: add imx7ulp pm related components bindings

[Rob Herring]

On Tue, 23 Oct 2018 11:49:08 +0000, "A.s. Dong" wrote:
> Add imx7ulp pm related components bindings
> 
> Cc: Rob Herring <robh+dt@kernel.org>
> Cc: Shawn Guo <shawnguo@kernel.org>
> Cc: devicetree@vger.kernel.org
> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
> ---
> ChangeLog:
> v1->v2:
>  * new patch
> ---
>  .../bindings/arm/freescale/fsl,imx7ulp-pm.txt      | 23 ++++++++++++++++++++++
>  1 file changed, 23 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/arm/freescale/fsl,imx7ulp-pm.txt
> 

Reviewed-by: Rob Herring <robh@kernel.org>

[PATCH V2 2/8] dt-bindings: fsl: add imx7ulp pm related components bindings

[Rob Herring]

On Tue, 23 Oct 2018 11:49:08 +0000, "A.s. Dong" wrote:
> Add imx7ulp pm related components bindings
> 
> Cc: Rob Herring <robh+dt@kernel.org>
> Cc: Shawn Guo <shawnguo@kernel.org>
> Cc: devicetree at vger.kernel.org
> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
> ---
> ChangeLog:
> v1->v2:
>  * new patch
> ---
>  .../bindings/arm/freescale/fsl,imx7ulp-pm.txt      | 23 ++++++++++++++++++++++
>  1 file changed, 23 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/arm/freescale/fsl,imx7ulp-pm.txt
> 

Reviewed-by: Rob Herring <robh@kernel.org>

[PATCH V2 3/8] dt-bindings: gpio: vf610: add optional clocks property

[A.s. Dong]

On some SoCs(e.g. MX7ULP), GPIO clock is gatable and maybe
disabled by default. Users have to make sure it's enabled before
being able to access controller registers, otherwise an external
abort error may occur. Let's add the optional clocks property to
handle this case.

For ULP GPIO clock, it includes two separate clocks: one is for
GPIO controller Input/Output function clock while another is
GPIO port control clock for interrupt function.

Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Stefan Agner <stefan@agner.ch>
Cc: linux-gpio@vger.kernel.org
Cc: devicetree@vger.kernel.org
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
---
v1->v2:
 * new patch
---
 Documentation/devicetree/bindings/gpio/gpio-vf610.txt | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/Documentation/devicetree/bindings/gpio/gpio-vf610.txt b/Documentation/devicetree/bindings/gpio/gpio-vf610.txt
index 0ccbae4..ae254aa 100644
--- a/Documentation/devicetree/bindings/gpio/gpio-vf610.txt
+++ b/Documentation/devicetree/bindings/gpio/gpio-vf610.txt
@@ -24,6 +24,12 @@ Required properties for GPIO node:
       4 = active high level-sensitive.
       8 = active low level-sensitive.
 
+Optional properties:
+-clocks:	Must contain an entry for each entry in clock-names.
+		See common clock-bindings.txt for details.
+-clock-names:	A list of clock names. For imx7ulp, it must contain
+		"gpio", "port".
+
 Note: Each GPIO port should have an alias correctly numbered in "aliases"
 node.
 
-- 
2.7.4

[PATCH V2 3/8] dt-bindings: gpio: vf610: add optional clocks property

[A.s. Dong]

On some SoCs(e.g. MX7ULP), GPIO clock is gatable and maybe
disabled by default. Users have to make sure it's enabled before
being able to access controller registers, otherwise an external
abort error may occur. Let's add the optional clocks property to
handle this case.

For ULP GPIO clock, it includes two separate clocks: one is for
GPIO controller Input/Output function clock while another is
GPIO port control clock for interrupt function.

Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Stefan Agner <stefan@agner.ch>
Cc: linux-gpio at vger.kernel.org
Cc: devicetree at vger.kernel.org
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
---
v1->v2:
 * new patch
---
 Documentation/devicetree/bindings/gpio/gpio-vf610.txt | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/Documentation/devicetree/bindings/gpio/gpio-vf610.txt b/Documentation/devicetree/bindings/gpio/gpio-vf610.txt
index 0ccbae4..ae254aa 100644
--- a/Documentation/devicetree/bindings/gpio/gpio-vf610.txt
+++ b/Documentation/devicetree/bindings/gpio/gpio-vf610.txt
@@ -24,6 +24,12 @@ Required properties for GPIO node:
       4 = active high level-sensitive.
       8 = active low level-sensitive.
 
+Optional properties:
+-clocks:	Must contain an entry for each entry in clock-names.
+		See common clock-bindings.txt for details.
+-clock-names:	A list of clock names. For imx7ulp, it must contain
+		"gpio", "port".
+
 Note: Each GPIO port should have an alias correctly numbered in "aliases"
 node.
 
-- 
2.7.4

Re: [PATCH V2 3/8] dt-bindings: gpio: vf610: add optional clocks property

[Rob Herring]

On Tue, 23 Oct 2018 11:49:13 +0000, "A.s. Dong" wrote:
> On some SoCs(e.g. MX7ULP), GPIO clock is gatable and maybe
> disabled by default. Users have to make sure it's enabled before
> being able to access controller registers, otherwise an external
> abort error may occur. Let's add the optional clocks property to
> handle this case.
> 
> For ULP GPIO clock, it includes two separate clocks: one is for
> GPIO controller Input/Output function clock while another is
> GPIO port control clock for interrupt function.
> 
> Cc: Linus Walleij <linus.walleij@linaro.org>
> Cc: Rob Herring <robh+dt@kernel.org>
> Cc: Mark Rutland <mark.rutland@arm.com>
> Cc: Stefan Agner <stefan@agner.ch>
> Cc: linux-gpio@vger.kernel.org
> Cc: devicetree@vger.kernel.org
> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
> ---
> v1->v2:
>  * new patch
> ---
>  Documentation/devicetree/bindings/gpio/gpio-vf610.txt | 6 ++++++
>  1 file changed, 6 insertions(+)
> 

Reviewed-by: Rob Herring <robh@kernel.org>

[PATCH V2 3/8] dt-bindings: gpio: vf610: add optional clocks property

[Rob Herring]

On Tue, 23 Oct 2018 11:49:13 +0000, "A.s. Dong" wrote:
> On some SoCs(e.g. MX7ULP), GPIO clock is gatable and maybe
> disabled by default. Users have to make sure it's enabled before
> being able to access controller registers, otherwise an external
> abort error may occur. Let's add the optional clocks property to
> handle this case.
> 
> For ULP GPIO clock, it includes two separate clocks: one is for
> GPIO controller Input/Output function clock while another is
> GPIO port control clock for interrupt function.
> 
> Cc: Linus Walleij <linus.walleij@linaro.org>
> Cc: Rob Herring <robh+dt@kernel.org>
> Cc: Mark Rutland <mark.rutland@arm.com>
> Cc: Stefan Agner <stefan@agner.ch>
> Cc: linux-gpio at vger.kernel.org
> Cc: devicetree at vger.kernel.org
> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
> ---
> v1->v2:
>  * new patch
> ---
>  Documentation/devicetree/bindings/gpio/gpio-vf610.txt | 6 ++++++
>  1 file changed, 6 insertions(+)
> 

Reviewed-by: Rob Herring <robh@kernel.org>

[PATCH V2 4/8] gpio: vf610: add optional clock support

[A.s. Dong]

Some SoCs need the gpio clock to be enabled before accessing
HW registers. This patch add the optional clock handling.

Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: Stefan Agner <stefan@agner.ch>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: linux-gpio@vger.kernel.org
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
---
v1->v2:
 * new patch
---
 drivers/gpio/gpio-vf610.c | 20 ++++++++++++++++++++
 1 file changed, 20 insertions(+)

diff --git a/drivers/gpio/gpio-vf610.c b/drivers/gpio/gpio-vf610.c
index d4ad6d0..cbc4f44 100644
--- a/drivers/gpio/gpio-vf610.c
+++ b/drivers/gpio/gpio-vf610.c
@@ -16,6 +16,7 @@
  */
 
 #include <linux/bitops.h>
+#include <linux/clk.h>
 #include <linux/err.h>
 #include <linux/gpio.h>
 #include <linux/init.h>
@@ -256,6 +257,7 @@ static int vf610_gpio_probe(struct platform_device *pdev)
 {
 	struct device *dev = &pdev->dev;
 	struct device_node *np = dev->of_node;
+	struct clk *clk_gpio, *clk_port;
 	struct vf610_gpio_port *port;
 	struct resource *iores;
 	struct gpio_chip *gc;
@@ -280,6 +282,24 @@ static int vf610_gpio_probe(struct platform_device *pdev)
 	if (port->irq < 0)
 		return port->irq;
 
+	clk_gpio = devm_clk_get(&pdev->dev, "gpio");
+	clk_port = devm_clk_get(&pdev->dev, "port");
+	if ((PTR_ERR(clk_gpio) == -EPROBE_DEFER) ||
+	    (PTR_ERR(clk_port) == -EPROBE_DEFER)) {
+		return -EPROBE_DEFER;
+	} else if (!IS_ERR_OR_NULL(clk_gpio) &&
+		   !IS_ERR_OR_NULL(clk_port)) {
+		ret = clk_prepare_enable(clk_gpio);
+		if (ret)
+			return ret;
+
+		ret = clk_prepare_enable(clk_port);
+		if (ret) {
+			clk_disable_unprepare(clk_gpio);
+			return ret;
+		}
+	}
+
 	gc = &port->gc;
 	gc->of_node = np;
 	gc->parent = dev;
-- 
2.7.4

[PATCH V2 4/8] gpio: vf610: add optional clock support

[A.s. Dong]

Some SoCs need the gpio clock to be enabled before accessing
HW registers. This patch add the optional clock handling.

Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: Stefan Agner <stefan@agner.ch>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: linux-gpio at vger.kernel.org
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
---
v1->v2:
 * new patch
---
 drivers/gpio/gpio-vf610.c | 20 ++++++++++++++++++++
 1 file changed, 20 insertions(+)

diff --git a/drivers/gpio/gpio-vf610.c b/drivers/gpio/gpio-vf610.c
index d4ad6d0..cbc4f44 100644
--- a/drivers/gpio/gpio-vf610.c
+++ b/drivers/gpio/gpio-vf610.c
@@ -16,6 +16,7 @@
  */
 
 #include <linux/bitops.h>
+#include <linux/clk.h>
 #include <linux/err.h>
 #include <linux/gpio.h>
 #include <linux/init.h>
@@ -256,6 +257,7 @@ static int vf610_gpio_probe(struct platform_device *pdev)
 {
 	struct device *dev = &pdev->dev;
 	struct device_node *np = dev->of_node;
+	struct clk *clk_gpio, *clk_port;
 	struct vf610_gpio_port *port;
 	struct resource *iores;
 	struct gpio_chip *gc;
@@ -280,6 +282,24 @@ static int vf610_gpio_probe(struct platform_device *pdev)
 	if (port->irq < 0)
 		return port->irq;
 
+	clk_gpio = devm_clk_get(&pdev->dev, "gpio");
+	clk_port = devm_clk_get(&pdev->dev, "port");
+	if ((PTR_ERR(clk_gpio) == -EPROBE_DEFER) ||
+	    (PTR_ERR(clk_port) == -EPROBE_DEFER)) {
+		return -EPROBE_DEFER;
+	} else if (!IS_ERR_OR_NULL(clk_gpio) &&
+		   !IS_ERR_OR_NULL(clk_port)) {
+		ret = clk_prepare_enable(clk_gpio);
+		if (ret)
+			return ret;
+
+		ret = clk_prepare_enable(clk_port);
+		if (ret) {
+			clk_disable_unprepare(clk_gpio);
+			return ret;
+		}
+	}
+
 	gc = &port->gc;
 	gc->of_node = np;
 	gc->parent = dev;
-- 
2.7.4

Re: [PATCH V2 4/8] gpio: vf610: add optional clock support

[Russell King - ARM Linux]

On Tue, Oct 23, 2018 at 11:49:17AM +0000, A.s. Dong wrote:
> +	clk_gpio = devm_clk_get(&pdev->dev, "gpio");
> +	clk_port = devm_clk_get(&pdev->dev, "port");
> +	if ((PTR_ERR(clk_gpio) == -EPROBE_DEFER) ||
> +	    (PTR_ERR(clk_port) == -EPROBE_DEFER)) {

	if (clk_gpio == ERR_PTR(-EPROBE_DEFER) ||
	    clk_port == ERR_PTR(-EPROBE_DEFER)) {

-- 
RMK's Patch system: http://www.armlinux.org.uk/developer/patches/
FTTC broadband for 0.8mile line in suburbia: sync at 12.1Mbps down 622kbps up
According to speedtest.net: 11.9Mbps down 500kbps up

[PATCH V2 4/8] gpio: vf610: add optional clock support

[Russell King - ARM Linux]

On Tue, Oct 23, 2018 at 11:49:17AM +0000, A.s. Dong wrote:
> +	clk_gpio = devm_clk_get(&pdev->dev, "gpio");
> +	clk_port = devm_clk_get(&pdev->dev, "port");
> +	if ((PTR_ERR(clk_gpio) == -EPROBE_DEFER) ||
> +	    (PTR_ERR(clk_port) == -EPROBE_DEFER)) {

	if (clk_gpio == ERR_PTR(-EPROBE_DEFER) ||
	    clk_port == ERR_PTR(-EPROBE_DEFER)) {

-- 
RMK's Patch system: http://www.armlinux.org.uk/developer/patches/
FTTC broadband for 0.8mile line in suburbia: sync at 12.1Mbps down 622kbps up
According to speedtest.net: 11.9Mbps down 500kbps up

RE: [PATCH V2 4/8] gpio: vf610: add optional clock support

[A.s. Dong]

Hi Russell,

> -----Original Message-----
> From: Russell King - ARM Linux [mailto:linux@armlinux.org.uk]
> Sent: Tuesday, October 23, 2018 8:04 PM
[...]
> On Tue, Oct 23, 2018 at 11:49:17AM +0000, A.s. Dong wrote:
> > +	clk_gpio = devm_clk_get(&pdev->dev, "gpio");
> > +	clk_port = devm_clk_get(&pdev->dev, "port");
> > +	if ((PTR_ERR(clk_gpio) == -EPROBE_DEFER) ||
> > +	    (PTR_ERR(clk_port) == -EPROBE_DEFER)) {
> 
> 	if (clk_gpio == ERR_PTR(-EPROBE_DEFER) ||
> 	    clk_port == ERR_PTR(-EPROBE_DEFER)) {
> 

Thanks for the suggestion. I will update it in next series.
Before that, let's wait a moment to see if any more review comments.

BTW, as I see kernel currently is widely using PTR_ERR(ptr) to compare
-EPROBE_DEFER, I'm not quite get the point why the new approach
you suggested is better, is it less error-prone? Or something else?
would you please help clarify a bit more?

Regards
Dong Aisheng

> --
> RMK's Patch system:
> https://emea01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fwww.
> armlinux.org.uk%2Fdeveloper%2Fpatches%2F&data=02%7C01%7Caishen
> g.dong%40nxp.com%7C34fcfce2f5d042efd0b808d638dfaaed%7C686ea1d3bc
> 2b4c6fa92cd99c5c301635%7C0%7C0%7C636758930627945785&sdata=
> PME05RkmX0mxRmhO%2Bj%2FofV3VN2VMx3FWU9bbqFr3XAg%3D&res
> erved=0
> FTTC broadband for 0.8mile line in suburbia: sync at 12.1Mbps down 622kbps
> up According to speedtest.net: 11.9Mbps down 500kbps up

[PATCH V2 4/8] gpio: vf610: add optional clock support

[A.s. Dong]

Hi Russell,

> -----Original Message-----
> From: Russell King - ARM Linux [mailto:linux at armlinux.org.uk]
> Sent: Tuesday, October 23, 2018 8:04 PM
[...]
> On Tue, Oct 23, 2018 at 11:49:17AM +0000, A.s. Dong wrote:
> > +	clk_gpio = devm_clk_get(&pdev->dev, "gpio");
> > +	clk_port = devm_clk_get(&pdev->dev, "port");
> > +	if ((PTR_ERR(clk_gpio) == -EPROBE_DEFER) ||
> > +	    (PTR_ERR(clk_port) == -EPROBE_DEFER)) {
> 
> 	if (clk_gpio == ERR_PTR(-EPROBE_DEFER) ||
> 	    clk_port == ERR_PTR(-EPROBE_DEFER)) {
> 

Thanks for the suggestion. I will update it in next series.
Before that, let's wait a moment to see if any more review comments.

BTW, as I see kernel currently is widely using PTR_ERR(ptr) to compare
-EPROBE_DEFER, I'm not quite get the point why the new approach
you suggested is better, is it less error-prone? Or something else?
would you please help clarify a bit more?

Regards
Dong Aisheng

> --
> RMK's Patch system:
> https://emea01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fwww.
> armlinux.org.uk%2Fdeveloper%2Fpatches%2F&data=02%7C01%7Caishen
> g.dong%40nxp.com%7C34fcfce2f5d042efd0b808d638dfaaed%7C686ea1d3bc
> 2b4c6fa92cd99c5c301635%7C0%7C0%7C636758930627945785&sdata=
> PME05RkmX0mxRmhO%2Bj%2FofV3VN2VMx3FWU9bbqFr3XAg%3D&res
> erved=0
> FTTC broadband for 0.8mile line in suburbia: sync at 12.1Mbps down 622kbps
> up According to speedtest.net: 11.9Mbps down 500kbps up

Re: [PATCH V2 4/8] gpio: vf610: add optional clock support

[Uwe Kleine-König]

On Tue, Oct 23, 2018 at 12:23:12PM +0000, A.s. Dong wrote:
> Hi Russell,
> 
> > -----Original Message-----
> > From: Russell King - ARM Linux [mailto:linux@armlinux.org.uk]
> > Sent: Tuesday, October 23, 2018 8:04 PM
> [...]
> > On Tue, Oct 23, 2018 at 11:49:17AM +0000, A.s. Dong wrote:
> > > +	clk_gpio = devm_clk_get(&pdev->dev, "gpio");
> > > +	clk_port = devm_clk_get(&pdev->dev, "port");
> > > +	if ((PTR_ERR(clk_gpio) == -EPROBE_DEFER) ||
> > > +	    (PTR_ERR(clk_port) == -EPROBE_DEFER)) {
> > 
> > 	if (clk_gpio == ERR_PTR(-EPROBE_DEFER) ||
> > 	    clk_port == ERR_PTR(-EPROBE_DEFER)) {
> > 
> 
> Thanks for the suggestion. I will update it in next series.
> Before that, let's wait a moment to see if any more review comments.
> 
> BTW, as I see kernel currently is widely using PTR_ERR(ptr) to compare
> -EPROBE_DEFER, I'm not quite get the point why the new approach
> you suggested is better, is it less error-prone? Or something else?
> would you please help clarify a bit more?

See the discussion in https://lore.kernel.org/patchwork/patch/999602/.

Best regards
Uwe

-- 
Pengutronix e.K.                           | Uwe Kleine-König            |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |

[PATCH V2 4/8] gpio: vf610: add optional clock support

[Uwe Kleine-König]

On Tue, Oct 23, 2018 at 12:23:12PM +0000, A.s. Dong wrote:
> Hi Russell,
> 
> > -----Original Message-----
> > From: Russell King - ARM Linux [mailto:linux at armlinux.org.uk]
> > Sent: Tuesday, October 23, 2018 8:04 PM
> [...]
> > On Tue, Oct 23, 2018 at 11:49:17AM +0000, A.s. Dong wrote:
> > > +	clk_gpio = devm_clk_get(&pdev->dev, "gpio");
> > > +	clk_port = devm_clk_get(&pdev->dev, "port");
> > > +	if ((PTR_ERR(clk_gpio) == -EPROBE_DEFER) ||
> > > +	    (PTR_ERR(clk_port) == -EPROBE_DEFER)) {
> > 
> > 	if (clk_gpio == ERR_PTR(-EPROBE_DEFER) ||
> > 	    clk_port == ERR_PTR(-EPROBE_DEFER)) {
> > 
> 
> Thanks for the suggestion. I will update it in next series.
> Before that, let's wait a moment to see if any more review comments.
> 
> BTW, as I see kernel currently is widely using PTR_ERR(ptr) to compare
> -EPROBE_DEFER, I'm not quite get the point why the new approach
> you suggested is better, is it less error-prone? Or something else?
> would you please help clarify a bit more?

See the discussion in https://lore.kernel.org/patchwork/patch/999602/.

Best regards
Uwe

-- 
Pengutronix e.K.                           | Uwe Kleine-K?nig            |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |

RE: [PATCH V2 4/8] gpio: vf610: add optional clock support

[A.s. Dong]

> -----Original Message-----
> From: Uwe Kleine-König [mailto:u.kleine-koenig@pengutronix.de]
> Sent: Tuesday, October 23, 2018 8:42 PM
> To: A.s. Dong <aisheng.dong@nxp.com>
> Cc: Russell King - ARM Linux <linux@armlinux.org.uk>; dongas86@gmail.com;
> Linus Walleij <linus.walleij@linaro.org>; Stefan Agner <stefan@agner.ch>;
> linux-gpio@vger.kernel.org; robh+dt@kernel.org; dl-linux-imx
> <linux-imx@nxp.com>; kernel@pengutronix.de; Fabio Estevam
> <fabio.estevam@nxp.com>; shawnguo@kernel.org;
> linux-arm-kernel@lists.infradead.org
> Subject: Re: [PATCH V2 4/8] gpio: vf610: add optional clock support
> 
> On Tue, Oct 23, 2018 at 12:23:12PM +0000, A.s. Dong wrote:
> > Hi Russell,
> >
> > > -----Original Message-----
> > > From: Russell King - ARM Linux [mailto:linux@armlinux.org.uk]
> > > Sent: Tuesday, October 23, 2018 8:04 PM
> > [...]
> > > On Tue, Oct 23, 2018 at 11:49:17AM +0000, A.s. Dong wrote:
> > > > +	clk_gpio = devm_clk_get(&pdev->dev, "gpio");
> > > > +	clk_port = devm_clk_get(&pdev->dev, "port");
> > > > +	if ((PTR_ERR(clk_gpio) == -EPROBE_DEFER) ||
> > > > +	    (PTR_ERR(clk_port) == -EPROBE_DEFER)) {
> > >
> > > 	if (clk_gpio == ERR_PTR(-EPROBE_DEFER) ||
> > > 	    clk_port == ERR_PTR(-EPROBE_DEFER)) {
> > >
> >
> > Thanks for the suggestion. I will update it in next series.
> > Before that, let's wait a moment to see if any more review comments.
> >
> > BTW, as I see kernel currently is widely using PTR_ERR(ptr) to compare
> > -EPROBE_DEFER, I'm not quite get the point why the new approach you
> > suggested is better, is it less error-prone? Or something else?
> > would you please help clarify a bit more?
> 
> See the discussion in
> https://lore.kernel.org/patchwork/patch/999602/ 
>

Thanks for sharing the info.
It does help.

Regards
Dong Aisheng
 
> Best regards
> Uwe
> 
> --
> Pengutronix e.K.                           | Uwe Kleine-König
> |
> Industrial Linux Solutions                 |
> https://emea01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fwww.
> pengutronix.de%2F&amp;data=02%7C01%7Caisheng.dong%40nxp.com%7C06
> 5f26466899474bf61a08d638e4e308%7C686ea1d3bc2b4c6fa92cd99c5c3016
> 35%7C0%7C0%7C636758953039817883&amp;sdata=hSgiadfyiFoK4AVTF2BR
> guOU5H8C77%2BY2bdjViC4Sfw%3D&amp;reserved=0  |

[PATCH V2 4/8] gpio: vf610: add optional clock support

[A.s. Dong]

> -----Original Message-----
> From: Uwe Kleine-K?nig [mailto:u.kleine-koenig at pengutronix.de]
> Sent: Tuesday, October 23, 2018 8:42 PM
> To: A.s. Dong <aisheng.dong@nxp.com>
> Cc: Russell King - ARM Linux <linux@armlinux.org.uk>; dongas86 at gmail.com;
> Linus Walleij <linus.walleij@linaro.org>; Stefan Agner <stefan@agner.ch>;
> linux-gpio at vger.kernel.org; robh+dt at kernel.org; dl-linux-imx
> <linux-imx@nxp.com>; kernel at pengutronix.de; Fabio Estevam
> <fabio.estevam@nxp.com>; shawnguo at kernel.org;
> linux-arm-kernel at lists.infradead.org
> Subject: Re: [PATCH V2 4/8] gpio: vf610: add optional clock support
> 
> On Tue, Oct 23, 2018 at 12:23:12PM +0000, A.s. Dong wrote:
> > Hi Russell,
> >
> > > -----Original Message-----
> > > From: Russell King - ARM Linux [mailto:linux at armlinux.org.uk]
> > > Sent: Tuesday, October 23, 2018 8:04 PM
> > [...]
> > > On Tue, Oct 23, 2018 at 11:49:17AM +0000, A.s. Dong wrote:
> > > > +	clk_gpio = devm_clk_get(&pdev->dev, "gpio");
> > > > +	clk_port = devm_clk_get(&pdev->dev, "port");
> > > > +	if ((PTR_ERR(clk_gpio) == -EPROBE_DEFER) ||
> > > > +	    (PTR_ERR(clk_port) == -EPROBE_DEFER)) {
> > >
> > > 	if (clk_gpio == ERR_PTR(-EPROBE_DEFER) ||
> > > 	    clk_port == ERR_PTR(-EPROBE_DEFER)) {
> > >
> >
> > Thanks for the suggestion. I will update it in next series.
> > Before that, let's wait a moment to see if any more review comments.
> >
> > BTW, as I see kernel currently is widely using PTR_ERR(ptr) to compare
> > -EPROBE_DEFER, I'm not quite get the point why the new approach you
> > suggested is better, is it less error-prone? Or something else?
> > would you please help clarify a bit more?
> 
> See the discussion in
> https://lore.kernel.org/patchwork/patch/999602/ 
>

Thanks for sharing the info.
It does help.

Regards
Dong Aisheng
 
> Best regards
> Uwe
> 
> --
> Pengutronix e.K.                           | Uwe Kleine-K?nig
> |
> Industrial Linux Solutions                 |
> https://emea01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fwww.
> pengutronix.de%2F&amp;data=02%7C01%7Caisheng.dong%40nxp.com%7C06
> 5f26466899474bf61a08d638e4e308%7C686ea1d3bc2b4c6fa92cd99c5c3016
> 35%7C0%7C0%7C636758953039817883&amp;sdata=hSgiadfyiFoK4AVTF2BR
> guOU5H8C77%2BY2bdjViC4Sfw%3D&amp;reserved=0  |

Re: [PATCH V2 4/8] gpio: vf610: add optional clock support

[Stefan Agner]

On 23.10.2018 13:49, A.s. Dong wrote:
> Some SoCs need the gpio clock to be enabled before accessing
> HW registers. This patch add the optional clock handling.
> 
> Cc: Linus Walleij <linus.walleij@linaro.org>
> Cc: Stefan Agner <stefan@agner.ch>
> Cc: Shawn Guo <shawnguo@kernel.org>
> Cc: linux-gpio@vger.kernel.org
> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
> ---
> v1->v2:
>  * new patch
> ---
>  drivers/gpio/gpio-vf610.c | 20 ++++++++++++++++++++
>  1 file changed, 20 insertions(+)
> 
> diff --git a/drivers/gpio/gpio-vf610.c b/drivers/gpio/gpio-vf610.c
> index d4ad6d0..cbc4f44 100644
> --- a/drivers/gpio/gpio-vf610.c
> +++ b/drivers/gpio/gpio-vf610.c
> @@ -16,6 +16,7 @@
>   */
>  
>  #include <linux/bitops.h>
> +#include <linux/clk.h>
>  #include <linux/err.h>
>  #include <linux/gpio.h>
>  #include <linux/init.h>
> @@ -256,6 +257,7 @@ static int vf610_gpio_probe(struct platform_device *pdev)
>  {
>  	struct device *dev = &pdev->dev;
>  	struct device_node *np = dev->of_node;
> +	struct clk *clk_gpio, *clk_port;
>  	struct vf610_gpio_port *port;
>  	struct resource *iores;
>  	struct gpio_chip *gc;
> @@ -280,6 +282,24 @@ static int vf610_gpio_probe(struct platform_device *pdev)
>  	if (port->irq < 0)
>  		return port->irq;
>  
> +	clk_gpio = devm_clk_get(&pdev->dev, "gpio");
> +	clk_port = devm_clk_get(&pdev->dev, "port");

Are you sure that those are two independent clocks? On i.MX 7 usually
there was a single clock gate controlling multiple clocks at once (which
should be modeled as a single clock gate in the clock tree).

--
Stefan 

> +	if ((PTR_ERR(clk_gpio) == -EPROBE_DEFER) ||
> +	    (PTR_ERR(clk_port) == -EPROBE_DEFER)) {
> +		return -EPROBE_DEFER;
> +	} else if (!IS_ERR_OR_NULL(clk_gpio) &&
> +		   !IS_ERR_OR_NULL(clk_port)) {
> +		ret = clk_prepare_enable(clk_gpio);
> +		if (ret)
> +			return ret;
> +
> +		ret = clk_prepare_enable(clk_port);
> +		if (ret) {
> +			clk_disable_unprepare(clk_gpio);
> +			return ret;
> +		}
> +	}
> +
>  	gc = &port->gc;
>  	gc->of_node = np;
>  	gc->parent = dev;

[PATCH V2 4/8] gpio: vf610: add optional clock support

[Stefan Agner]

On 23.10.2018 13:49, A.s. Dong wrote:
> Some SoCs need the gpio clock to be enabled before accessing
> HW registers. This patch add the optional clock handling.
> 
> Cc: Linus Walleij <linus.walleij@linaro.org>
> Cc: Stefan Agner <stefan@agner.ch>
> Cc: Shawn Guo <shawnguo@kernel.org>
> Cc: linux-gpio at vger.kernel.org
> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
> ---
> v1->v2:
>  * new patch
> ---
>  drivers/gpio/gpio-vf610.c | 20 ++++++++++++++++++++
>  1 file changed, 20 insertions(+)
> 
> diff --git a/drivers/gpio/gpio-vf610.c b/drivers/gpio/gpio-vf610.c
> index d4ad6d0..cbc4f44 100644
> --- a/drivers/gpio/gpio-vf610.c
> +++ b/drivers/gpio/gpio-vf610.c
> @@ -16,6 +16,7 @@
>   */
>  
>  #include <linux/bitops.h>
> +#include <linux/clk.h>
>  #include <linux/err.h>
>  #include <linux/gpio.h>
>  #include <linux/init.h>
> @@ -256,6 +257,7 @@ static int vf610_gpio_probe(struct platform_device *pdev)
>  {
>  	struct device *dev = &pdev->dev;
>  	struct device_node *np = dev->of_node;
> +	struct clk *clk_gpio, *clk_port;
>  	struct vf610_gpio_port *port;
>  	struct resource *iores;
>  	struct gpio_chip *gc;
> @@ -280,6 +282,24 @@ static int vf610_gpio_probe(struct platform_device *pdev)
>  	if (port->irq < 0)
>  		return port->irq;
>  
> +	clk_gpio = devm_clk_get(&pdev->dev, "gpio");
> +	clk_port = devm_clk_get(&pdev->dev, "port");

Are you sure that those are two independent clocks? On i.MX 7 usually
there was a single clock gate controlling multiple clocks at once (which
should be modeled as a single clock gate in the clock tree).

--
Stefan 

> +	if ((PTR_ERR(clk_gpio) == -EPROBE_DEFER) ||
> +	    (PTR_ERR(clk_port) == -EPROBE_DEFER)) {
> +		return -EPROBE_DEFER;
> +	} else if (!IS_ERR_OR_NULL(clk_gpio) &&
> +		   !IS_ERR_OR_NULL(clk_port)) {
> +		ret = clk_prepare_enable(clk_gpio);
> +		if (ret)
> +			return ret;
> +
> +		ret = clk_prepare_enable(clk_port);
> +		if (ret) {
> +			clk_disable_unprepare(clk_gpio);
> +			return ret;
> +		}
> +	}
> +
>  	gc = &port->gc;
>  	gc->of_node = np;
>  	gc->parent = dev;

RE: [PATCH V2 4/8] gpio: vf610: add optional clock support

[A.s. Dong]

> -----Original Message-----
> From: Stefan Agner [mailto:stefan@agner.ch]
> Sent: Friday, October 26, 2018 1:59 AM
[...]
> 
> On 23.10.2018 13:49, A.s. Dong wrote:
> > Some SoCs need the gpio clock to be enabled before accessing HW
> > registers. This patch add the optional clock handling.
> >
> > Cc: Linus Walleij <linus.walleij@linaro.org>
> > Cc: Stefan Agner <stefan@agner.ch>
> > Cc: Shawn Guo <shawnguo@kernel.org>
> > Cc: linux-gpio@vger.kernel.org
> > Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
> > ---
> > v1->v2:
> >  * new patch
> > ---
> >  drivers/gpio/gpio-vf610.c | 20 ++++++++++++++++++++
> >  1 file changed, 20 insertions(+)
> >
> > diff --git a/drivers/gpio/gpio-vf610.c b/drivers/gpio/gpio-vf610.c
> > index d4ad6d0..cbc4f44 100644
> > --- a/drivers/gpio/gpio-vf610.c
> > +++ b/drivers/gpio/gpio-vf610.c
> > @@ -16,6 +16,7 @@
> >   */
> >
> >  #include <linux/bitops.h>
> > +#include <linux/clk.h>
> >  #include <linux/err.h>
> >  #include <linux/gpio.h>
> >  #include <linux/init.h>
> > @@ -256,6 +257,7 @@ static int vf610_gpio_probe(struct platform_device
> > *pdev)  {
> >  	struct device *dev = &pdev->dev;
> >  	struct device_node *np = dev->of_node;
> > +	struct clk *clk_gpio, *clk_port;
> >  	struct vf610_gpio_port *port;
> >  	struct resource *iores;
> >  	struct gpio_chip *gc;
> > @@ -280,6 +282,24 @@ static int vf610_gpio_probe(struct platform_device
> *pdev)
> >  	if (port->irq < 0)
> >  		return port->irq;
> >
> > +	clk_gpio = devm_clk_get(&pdev->dev, "gpio");
> > +	clk_port = devm_clk_get(&pdev->dev, "port");
> 
> Are you sure that those are two independent clocks? On i.MX 7 usually there
> was a single clock gate controlling multiple clocks at once (which should be
> modeled as a single clock gate in the clock tree).
> 

Yes, they're two separate clocks in HW for gpio and port controller respectively.
One is for GPIO general purpose input/output function which another for port Interrupt.
Just like we have separate register ranges for gpio and port.

Regards
Dong Aisheng

> --
> Stefan
> 
> > +	if ((PTR_ERR(clk_gpio) == -EPROBE_DEFER) ||
> > +	    (PTR_ERR(clk_port) == -EPROBE_DEFER)) {
> > +		return -EPROBE_DEFER;
> > +	} else if (!IS_ERR_OR_NULL(clk_gpio) &&
> > +		   !IS_ERR_OR_NULL(clk_port)) {
> > +		ret = clk_prepare_enable(clk_gpio);
> > +		if (ret)
> > +			return ret;
> > +
> > +		ret = clk_prepare_enable(clk_port);
> > +		if (ret) {
> > +			clk_disable_unprepare(clk_gpio);
> > +			return ret;
> > +		}
> > +	}
> > +
> >  	gc = &port->gc;
> >  	gc->of_node = np;
> >  	gc->parent = dev;

[PATCH V2 4/8] gpio: vf610: add optional clock support

[A.s. Dong]

> -----Original Message-----
> From: Stefan Agner [mailto:stefan at agner.ch]
> Sent: Friday, October 26, 2018 1:59 AM
[...]
> 
> On 23.10.2018 13:49, A.s. Dong wrote:
> > Some SoCs need the gpio clock to be enabled before accessing HW
> > registers. This patch add the optional clock handling.
> >
> > Cc: Linus Walleij <linus.walleij@linaro.org>
> > Cc: Stefan Agner <stefan@agner.ch>
> > Cc: Shawn Guo <shawnguo@kernel.org>
> > Cc: linux-gpio at vger.kernel.org
> > Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
> > ---
> > v1->v2:
> >  * new patch
> > ---
> >  drivers/gpio/gpio-vf610.c | 20 ++++++++++++++++++++
> >  1 file changed, 20 insertions(+)
> >
> > diff --git a/drivers/gpio/gpio-vf610.c b/drivers/gpio/gpio-vf610.c
> > index d4ad6d0..cbc4f44 100644
> > --- a/drivers/gpio/gpio-vf610.c
> > +++ b/drivers/gpio/gpio-vf610.c
> > @@ -16,6 +16,7 @@
> >   */
> >
> >  #include <linux/bitops.h>
> > +#include <linux/clk.h>
> >  #include <linux/err.h>
> >  #include <linux/gpio.h>
> >  #include <linux/init.h>
> > @@ -256,6 +257,7 @@ static int vf610_gpio_probe(struct platform_device
> > *pdev)  {
> >  	struct device *dev = &pdev->dev;
> >  	struct device_node *np = dev->of_node;
> > +	struct clk *clk_gpio, *clk_port;
> >  	struct vf610_gpio_port *port;
> >  	struct resource *iores;
> >  	struct gpio_chip *gc;
> > @@ -280,6 +282,24 @@ static int vf610_gpio_probe(struct platform_device
> *pdev)
> >  	if (port->irq < 0)
> >  		return port->irq;
> >
> > +	clk_gpio = devm_clk_get(&pdev->dev, "gpio");
> > +	clk_port = devm_clk_get(&pdev->dev, "port");
> 
> Are you sure that those are two independent clocks? On i.MX 7 usually there
> was a single clock gate controlling multiple clocks at once (which should be
> modeled as a single clock gate in the clock tree).
> 

Yes, they're two separate clocks in HW for gpio and port controller respectively.
One is for GPIO general purpose input/output function which another for port Interrupt.
Just like we have separate register ranges for gpio and port.

Regards
Dong Aisheng

> --
> Stefan
> 
> > +	if ((PTR_ERR(clk_gpio) == -EPROBE_DEFER) ||
> > +	    (PTR_ERR(clk_port) == -EPROBE_DEFER)) {
> > +		return -EPROBE_DEFER;
> > +	} else if (!IS_ERR_OR_NULL(clk_gpio) &&
> > +		   !IS_ERR_OR_NULL(clk_port)) {
> > +		ret = clk_prepare_enable(clk_gpio);
> > +		if (ret)
> > +			return ret;
> > +
> > +		ret = clk_prepare_enable(clk_port);
> > +		if (ret) {
> > +			clk_disable_unprepare(clk_gpio);
> > +			return ret;
> > +		}
> > +	}
> > +
> >  	gc = &port->gc;
> >  	gc->of_node = np;
> >  	gc->parent = dev;

Re: [PATCH V2 4/8] gpio: vf610: add optional clock support

[Stefan Agner]

On 26.10.2018 05:49, A.s. Dong wrote:
>> -----Original Message-----
>> From: Stefan Agner [mailto:stefan@agner.ch]
>> Sent: Friday, October 26, 2018 1:59 AM
> [...]
>>
>> On 23.10.2018 13:49, A.s. Dong wrote:
>> > Some SoCs need the gpio clock to be enabled before accessing HW
>> > registers. This patch add the optional clock handling.
>> >
>> > Cc: Linus Walleij <linus.walleij@linaro.org>
>> > Cc: Stefan Agner <stefan@agner.ch>
>> > Cc: Shawn Guo <shawnguo@kernel.org>
>> > Cc: linux-gpio@vger.kernel.org
>> > Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
>> > ---
>> > v1->v2:
>> >  * new patch
>> > ---
>> >  drivers/gpio/gpio-vf610.c | 20 ++++++++++++++++++++
>> >  1 file changed, 20 insertions(+)
>> >
>> > diff --git a/drivers/gpio/gpio-vf610.c b/drivers/gpio/gpio-vf610.c
>> > index d4ad6d0..cbc4f44 100644
>> > --- a/drivers/gpio/gpio-vf610.c
>> > +++ b/drivers/gpio/gpio-vf610.c
>> > @@ -16,6 +16,7 @@
>> >   */
>> >
>> >  #include <linux/bitops.h>
>> > +#include <linux/clk.h>
>> >  #include <linux/err.h>
>> >  #include <linux/gpio.h>
>> >  #include <linux/init.h>
>> > @@ -256,6 +257,7 @@ static int vf610_gpio_probe(struct platform_device
>> > *pdev)  {
>> >  	struct device *dev = &pdev->dev;
>> >  	struct device_node *np = dev->of_node;
>> > +	struct clk *clk_gpio, *clk_port;
>> >  	struct vf610_gpio_port *port;
>> >  	struct resource *iores;
>> >  	struct gpio_chip *gc;
>> > @@ -280,6 +282,24 @@ static int vf610_gpio_probe(struct platform_device
>> *pdev)
>> >  	if (port->irq < 0)
>> >  		return port->irq;
>> >
>> > +	clk_gpio = devm_clk_get(&pdev->dev, "gpio");
>> > +	clk_port = devm_clk_get(&pdev->dev, "port");
>>
>> Are you sure that those are two independent clocks? On i.MX 7 usually there
>> was a single clock gate controlling multiple clocks at once (which should be
>> modeled as a single clock gate in the clock tree).
>>
> 
> Yes, they're two separate clocks in HW for gpio and port controller
> respectively.
> One is for GPIO general purpose input/output function which another
> for port Interrupt.
> Just like we have separate register ranges for gpio and port.

Oh I see, that is the same with Vybrid actually. However, in Vybrid, for
some reason, there is only a clock for port (Port X multiplexing
control).

Can we make port clock independently optional?

E.g.

	clk_port = devm_clk_get(&pdev->dev, "port");
	if (clk_gpio == ERR_PTR(-EPROBE_DEFER))
		return -EPROBE_DEFER;

	clk_gpio = devm_clk_get(&pdev->dev, "gpio");
	if (clk_gpio == ERR_PTR(-EPROBE_DEFER))
		return -EPROBE_DEFER;

	if (!IS_ERR_OR_NULL(clk_port)) {
		ret = clk_prepare_enable(clk_port);
		if (ret)
			return ret;
	}

	if (!IS_ERR_OR_NULL(clk_gpio))
		ret = clk_prepare_enable(clk_gpio);
		if (ret) {
			clk_disable_unprepare(clk_port);
			return ret;
		}
	}

Also there is some error handling a bit further down which needs proper
disabling the clocks.

--
Stefan


> 
> Regards
> Dong Aisheng
> 
>> --
>> Stefan
>>
>> > +	if ((PTR_ERR(clk_gpio) == -EPROBE_DEFER) ||
>> > +	    (PTR_ERR(clk_port) == -EPROBE_DEFER)) {
>> > +		return -EPROBE_DEFER;
>> > +	} else if (!IS_ERR_OR_NULL(clk_gpio) &&
>> > +		   !IS_ERR_OR_NULL(clk_port)) {
>> > +		ret = clk_prepare_enable(clk_gpio);
>> > +		if (ret)
>> > +			return ret;
>> > +
>> > +		ret = clk_prepare_enable(clk_port);
>> > +		if (ret) {
>> > +			clk_disable_unprepare(clk_gpio);
>> > +			return ret;
>> > +		}
>> > +	}
>> > +
>> >  	gc = &port->gc;
>> >  	gc->of_node = np;
>> >  	gc->parent = dev;

[PATCH V2 4/8] gpio: vf610: add optional clock support

[Stefan Agner]

On 26.10.2018 05:49, A.s. Dong wrote:
>> -----Original Message-----
>> From: Stefan Agner [mailto:stefan at agner.ch]
>> Sent: Friday, October 26, 2018 1:59 AM
> [...]
>>
>> On 23.10.2018 13:49, A.s. Dong wrote:
>> > Some SoCs need the gpio clock to be enabled before accessing HW
>> > registers. This patch add the optional clock handling.
>> >
>> > Cc: Linus Walleij <linus.walleij@linaro.org>
>> > Cc: Stefan Agner <stefan@agner.ch>
>> > Cc: Shawn Guo <shawnguo@kernel.org>
>> > Cc: linux-gpio at vger.kernel.org
>> > Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
>> > ---
>> > v1->v2:
>> >  * new patch
>> > ---
>> >  drivers/gpio/gpio-vf610.c | 20 ++++++++++++++++++++
>> >  1 file changed, 20 insertions(+)
>> >
>> > diff --git a/drivers/gpio/gpio-vf610.c b/drivers/gpio/gpio-vf610.c
>> > index d4ad6d0..cbc4f44 100644
>> > --- a/drivers/gpio/gpio-vf610.c
>> > +++ b/drivers/gpio/gpio-vf610.c
>> > @@ -16,6 +16,7 @@
>> >   */
>> >
>> >  #include <linux/bitops.h>
>> > +#include <linux/clk.h>
>> >  #include <linux/err.h>
>> >  #include <linux/gpio.h>
>> >  #include <linux/init.h>
>> > @@ -256,6 +257,7 @@ static int vf610_gpio_probe(struct platform_device
>> > *pdev)  {
>> >  	struct device *dev = &pdev->dev;
>> >  	struct device_node *np = dev->of_node;
>> > +	struct clk *clk_gpio, *clk_port;
>> >  	struct vf610_gpio_port *port;
>> >  	struct resource *iores;
>> >  	struct gpio_chip *gc;
>> > @@ -280,6 +282,24 @@ static int vf610_gpio_probe(struct platform_device
>> *pdev)
>> >  	if (port->irq < 0)
>> >  		return port->irq;
>> >
>> > +	clk_gpio = devm_clk_get(&pdev->dev, "gpio");
>> > +	clk_port = devm_clk_get(&pdev->dev, "port");
>>
>> Are you sure that those are two independent clocks? On i.MX 7 usually there
>> was a single clock gate controlling multiple clocks at once (which should be
>> modeled as a single clock gate in the clock tree).
>>
> 
> Yes, they're two separate clocks in HW for gpio and port controller
> respectively.
> One is for GPIO general purpose input/output function which another
> for port Interrupt.
> Just like we have separate register ranges for gpio and port.

Oh I see, that is the same with Vybrid actually. However, in Vybrid, for
some reason, there is only a clock for port (Port X multiplexing
control).

Can we make port clock independently optional?

E.g.

	clk_port = devm_clk_get(&pdev->dev, "port");
	if (clk_gpio == ERR_PTR(-EPROBE_DEFER))
		return -EPROBE_DEFER;

	clk_gpio = devm_clk_get(&pdev->dev, "gpio");
	if (clk_gpio == ERR_PTR(-EPROBE_DEFER))
		return -EPROBE_DEFER;

	if (!IS_ERR_OR_NULL(clk_port)) {
		ret = clk_prepare_enable(clk_port);
		if (ret)
			return ret;
	}

	if (!IS_ERR_OR_NULL(clk_gpio))
		ret = clk_prepare_enable(clk_gpio);
		if (ret) {
			clk_disable_unprepare(clk_port);
			return ret;
		}
	}

Also there is some error handling a bit further down which needs proper
disabling the clocks.

--
Stefan


> 
> Regards
> Dong Aisheng
> 
>> --
>> Stefan
>>
>> > +	if ((PTR_ERR(clk_gpio) == -EPROBE_DEFER) ||
>> > +	    (PTR_ERR(clk_port) == -EPROBE_DEFER)) {
>> > +		return -EPROBE_DEFER;
>> > +	} else if (!IS_ERR_OR_NULL(clk_gpio) &&
>> > +		   !IS_ERR_OR_NULL(clk_port)) {
>> > +		ret = clk_prepare_enable(clk_gpio);
>> > +		if (ret)
>> > +			return ret;
>> > +
>> > +		ret = clk_prepare_enable(clk_port);
>> > +		if (ret) {
>> > +			clk_disable_unprepare(clk_gpio);
>> > +			return ret;
>> > +		}
>> > +	}
>> > +
>> >  	gc = &port->gc;
>> >  	gc->of_node = np;
>> >  	gc->parent = dev;

RE: [PATCH V2 4/8] gpio: vf610: add optional clock support

[A.s. Dong]

Hi Stefan,

[...]
> 
> On 26.10.2018 05:49, A.s. Dong wrote:
> >> -----Original Message-----
> >> From: Stefan Agner [mailto:stefan@agner.ch]
> >> Sent: Friday, October 26, 2018 1:59 AM
> > [...]
> >>
> >> On 23.10.2018 13:49, A.s. Dong wrote:
> >> > Some SoCs need the gpio clock to be enabled before accessing HW
> >> > registers. This patch add the optional clock handling.
> >> >
> >> > Cc: Linus Walleij <linus.walleij@linaro.org>
> >> > Cc: Stefan Agner <stefan@agner.ch>
> >> > Cc: Shawn Guo <shawnguo@kernel.org>
> >> > Cc: linux-gpio@vger.kernel.org
> >> > Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
> >> > ---
> >> > v1->v2:
> >> >  * new patch
> >> > ---
> >> >  drivers/gpio/gpio-vf610.c | 20 ++++++++++++++++++++
> >> >  1 file changed, 20 insertions(+)
> >> >
> >> > diff --git a/drivers/gpio/gpio-vf610.c b/drivers/gpio/gpio-vf610.c
> >> > index d4ad6d0..cbc4f44 100644
> >> > --- a/drivers/gpio/gpio-vf610.c
> >> > +++ b/drivers/gpio/gpio-vf610.c
> >> > @@ -16,6 +16,7 @@
> >> >   */
> >> >
> >> >  #include <linux/bitops.h>
> >> > +#include <linux/clk.h>
> >> >  #include <linux/err.h>
> >> >  #include <linux/gpio.h>
> >> >  #include <linux/init.h>
> >> > @@ -256,6 +257,7 @@ static int vf610_gpio_probe(struct
> >> > platform_device
> >> > *pdev)  {
> >> >  	struct device *dev = &pdev->dev;
> >> >  	struct device_node *np = dev->of_node;
> >> > +	struct clk *clk_gpio, *clk_port;
> >> >  	struct vf610_gpio_port *port;
> >> >  	struct resource *iores;
> >> >  	struct gpio_chip *gc;
> >> > @@ -280,6 +282,24 @@ static int vf610_gpio_probe(struct
> >> > platform_device
> >> *pdev)
> >> >  	if (port->irq < 0)
> >> >  		return port->irq;
> >> >
> >> > +	clk_gpio = devm_clk_get(&pdev->dev, "gpio");
> >> > +	clk_port = devm_clk_get(&pdev->dev, "port");
> >>
> >> Are you sure that those are two independent clocks? On i.MX 7 usually
> >> there was a single clock gate controlling multiple clocks at once
> >> (which should be modeled as a single clock gate in the clock tree).
> >>
> >
> > Yes, they're two separate clocks in HW for gpio and port controller
> > respectively.
> > One is for GPIO general purpose input/output function which another
> > for port Interrupt.
> > Just like we have separate register ranges for gpio and port.
> 
> Oh I see, that is the same with Vybrid actually. However, in Vybrid, for some
> reason, there is only a clock for port (Port X multiplexing control).
> 
> Can we make port clock independently optional?
> 
> E.g.
> 
> 	clk_port = devm_clk_get(&pdev->dev, "port");
> 	if (clk_gpio == ERR_PTR(-EPROBE_DEFER))
> 		return -EPROBE_DEFER;
> 
> 	clk_gpio = devm_clk_get(&pdev->dev, "gpio");
> 	if (clk_gpio == ERR_PTR(-EPROBE_DEFER))
> 		return -EPROBE_DEFER;
> 
> 	if (!IS_ERR_OR_NULL(clk_port)) {
> 		ret = clk_prepare_enable(clk_port);
> 		if (ret)
> 			return ret;
> 	}
> 
> 	if (!IS_ERR_OR_NULL(clk_gpio))
> 		ret = clk_prepare_enable(clk_gpio);
> 		if (ret) {
> 			clk_disable_unprepare(clk_port);
> 			return ret;
> 		}
> 	}
> 
> Also there is some error handling a bit further down which needs proper
> disabling the clocks.
> 

Got it, thanks for the suggestion.
Will change in next version.

Regards
Dong Aisheng

> --
> Stefan
> 
> 
> >
> > Regards
> > Dong Aisheng
> >
> >> --
> >> Stefan
> >>
> >> > +	if ((PTR_ERR(clk_gpio) == -EPROBE_DEFER) ||
> >> > +	    (PTR_ERR(clk_port) == -EPROBE_DEFER)) {
> >> > +		return -EPROBE_DEFER;
> >> > +	} else if (!IS_ERR_OR_NULL(clk_gpio) &&
> >> > +		   !IS_ERR_OR_NULL(clk_port)) {
> >> > +		ret = clk_prepare_enable(clk_gpio);
> >> > +		if (ret)
> >> > +			return ret;
> >> > +
> >> > +		ret = clk_prepare_enable(clk_port);
> >> > +		if (ret) {
> >> > +			clk_disable_unprepare(clk_gpio);
> >> > +			return ret;
> >> > +		}
> >> > +	}
> >> > +
> >> >  	gc = &port->gc;
> >> >  	gc->of_node = np;
> >> >  	gc->parent = dev;

[PATCH V2 4/8] gpio: vf610: add optional clock support

[A.s. Dong]

Hi Stefan,

[...]
> 
> On 26.10.2018 05:49, A.s. Dong wrote:
> >> -----Original Message-----
> >> From: Stefan Agner [mailto:stefan at agner.ch]
> >> Sent: Friday, October 26, 2018 1:59 AM
> > [...]
> >>
> >> On 23.10.2018 13:49, A.s. Dong wrote:
> >> > Some SoCs need the gpio clock to be enabled before accessing HW
> >> > registers. This patch add the optional clock handling.
> >> >
> >> > Cc: Linus Walleij <linus.walleij@linaro.org>
> >> > Cc: Stefan Agner <stefan@agner.ch>
> >> > Cc: Shawn Guo <shawnguo@kernel.org>
> >> > Cc: linux-gpio at vger.kernel.org
> >> > Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
> >> > ---
> >> > v1->v2:
> >> >  * new patch
> >> > ---
> >> >  drivers/gpio/gpio-vf610.c | 20 ++++++++++++++++++++
> >> >  1 file changed, 20 insertions(+)
> >> >
> >> > diff --git a/drivers/gpio/gpio-vf610.c b/drivers/gpio/gpio-vf610.c
> >> > index d4ad6d0..cbc4f44 100644
> >> > --- a/drivers/gpio/gpio-vf610.c
> >> > +++ b/drivers/gpio/gpio-vf610.c
> >> > @@ -16,6 +16,7 @@
> >> >   */
> >> >
> >> >  #include <linux/bitops.h>
> >> > +#include <linux/clk.h>
> >> >  #include <linux/err.h>
> >> >  #include <linux/gpio.h>
> >> >  #include <linux/init.h>
> >> > @@ -256,6 +257,7 @@ static int vf610_gpio_probe(struct
> >> > platform_device
> >> > *pdev)  {
> >> >  	struct device *dev = &pdev->dev;
> >> >  	struct device_node *np = dev->of_node;
> >> > +	struct clk *clk_gpio, *clk_port;
> >> >  	struct vf610_gpio_port *port;
> >> >  	struct resource *iores;
> >> >  	struct gpio_chip *gc;
> >> > @@ -280,6 +282,24 @@ static int vf610_gpio_probe(struct
> >> > platform_device
> >> *pdev)
> >> >  	if (port->irq < 0)
> >> >  		return port->irq;
> >> >
> >> > +	clk_gpio = devm_clk_get(&pdev->dev, "gpio");
> >> > +	clk_port = devm_clk_get(&pdev->dev, "port");
> >>
> >> Are you sure that those are two independent clocks? On i.MX 7 usually
> >> there was a single clock gate controlling multiple clocks at once
> >> (which should be modeled as a single clock gate in the clock tree).
> >>
> >
> > Yes, they're two separate clocks in HW for gpio and port controller
> > respectively.
> > One is for GPIO general purpose input/output function which another
> > for port Interrupt.
> > Just like we have separate register ranges for gpio and port.
> 
> Oh I see, that is the same with Vybrid actually. However, in Vybrid, for some
> reason, there is only a clock for port (Port X multiplexing control).
> 
> Can we make port clock independently optional?
> 
> E.g.
> 
> 	clk_port = devm_clk_get(&pdev->dev, "port");
> 	if (clk_gpio == ERR_PTR(-EPROBE_DEFER))
> 		return -EPROBE_DEFER;
> 
> 	clk_gpio = devm_clk_get(&pdev->dev, "gpio");
> 	if (clk_gpio == ERR_PTR(-EPROBE_DEFER))
> 		return -EPROBE_DEFER;
> 
> 	if (!IS_ERR_OR_NULL(clk_port)) {
> 		ret = clk_prepare_enable(clk_port);
> 		if (ret)
> 			return ret;
> 	}
> 
> 	if (!IS_ERR_OR_NULL(clk_gpio))
> 		ret = clk_prepare_enable(clk_gpio);
> 		if (ret) {
> 			clk_disable_unprepare(clk_port);
> 			return ret;
> 		}
> 	}
> 
> Also there is some error handling a bit further down which needs proper
> disabling the clocks.
> 

Got it, thanks for the suggestion.
Will change in next version.

Regards
Dong Aisheng

> --
> Stefan
> 
> 
> >
> > Regards
> > Dong Aisheng
> >
> >> --
> >> Stefan
> >>
> >> > +	if ((PTR_ERR(clk_gpio) == -EPROBE_DEFER) ||
> >> > +	    (PTR_ERR(clk_port) == -EPROBE_DEFER)) {
> >> > +		return -EPROBE_DEFER;
> >> > +	} else if (!IS_ERR_OR_NULL(clk_gpio) &&
> >> > +		   !IS_ERR_OR_NULL(clk_port)) {
> >> > +		ret = clk_prepare_enable(clk_gpio);
> >> > +		if (ret)
> >> > +			return ret;
> >> > +
> >> > +		ret = clk_prepare_enable(clk_port);
> >> > +		if (ret) {
> >> > +			clk_disable_unprepare(clk_gpio);
> >> > +			return ret;
> >> > +		}
> >> > +	}
> >> > +
> >> >  	gc = &port->gc;
> >> >  	gc->of_node = np;
> >> >  	gc->parent = dev;

[PATCH V2 5/8] ARM: imx: add initial support for imx7ulp

[A.s. Dong]

The i.MX 7ULP family of processors represents NXP?s latest achievement
in ultra-low-power processing for use cases demanding long battery life.
Targeted towards the growing market of portable devices, the i.MX 7ULP
family of processors features NXP's advanced implementation of the Arm?
Cortex?-A7 core, the Arm Cortex-M4 core, as well as a 3D and 2D Graphics
Processing Units (GPUs). The i.MX 7ULP family provides up to 32-bit
LPDDR2/LPDDR3 memory interface and a number of other interfaces for
connecting peripherals, such as WLAN, Bluetooth, GPS, displays, and
camera sensors.

This patch aims to add an initial support for imx7ulp. Note that we need
configure power mode to Partial Stop mode 3 with system/bus clock enabled
first as the default enabled STOP mode will gate off system/bus clock when
execute WFI in MX7ULP SoC.

And there's still no MXC_CPU_IMX7ULP IDs read from register as ULP has no
anatop as before. So we encode one with 0xff in reverse order in case new
ones will be in the future.

Cc: Shawn Guo <shawnguo@kernel.org>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
---
ChangeLog:
v1->v2:
 * switch to SPDX license
 * more description of new SOC in commit message
---
 arch/arm/mach-imx/Kconfig        |  9 +++++++++
 arch/arm/mach-imx/Makefile       |  1 +
 arch/arm/mach-imx/common.h       |  1 +
 arch/arm/mach-imx/cpu.c          |  3 +++
 arch/arm/mach-imx/mach-imx7ulp.c | 32 ++++++++++++++++++++++++++++++++
 arch/arm/mach-imx/mxc.h          |  1 +
 arch/arm/mach-imx/pm-imx7ulp.c   | 28 ++++++++++++++++++++++++++++
 7 files changed, 75 insertions(+)
 create mode 100644 arch/arm/mach-imx/mach-imx7ulp.c
 create mode 100644 arch/arm/mach-imx/pm-imx7ulp.c

diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index abc3371..c12a05c 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -558,6 +558,15 @@ config SOC_IMX7D
 	help
 		This enables support for Freescale i.MX7 Dual processor.
 
+config SOC_IMX7ULP
+	bool "i.MX7ULP support"
+	select ARM_GIC
+	select CLKSRC_IMX_TPM
+	select HAVE_ARM_ARCH_TIMER
+	select PINCTRL_IMX7ULP
+	help
+	  This enables support for Freescale i.MX7 Ultra Low Power processor.
+
 config SOC_VF610
 	bool "Vybrid Family VF610 support"
 	select ARM_GIC if ARCH_MULTI_V7
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index bae179a..8af2f7e 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -83,6 +83,7 @@ obj-$(CONFIG_SOC_IMX6SX) += mach-imx6sx.o
 obj-$(CONFIG_SOC_IMX6UL) += mach-imx6ul.o
 obj-$(CONFIG_SOC_IMX7D_CA7) += mach-imx7d.o
 obj-$(CONFIG_SOC_IMX7D_CM4) += mach-imx7d-cm4.o
+obj-$(CONFIG_SOC_IMX7ULP) += mach-imx7ulp.o pm-imx7ulp.o
 
 ifeq ($(CONFIG_SUSPEND),y)
 AFLAGS_suspend-imx6.o :=-Wa,-march=armv7-a
diff --git a/arch/arm/mach-imx/common.h b/arch/arm/mach-imx/common.h
index 423dd76..bc915e5 100644
--- a/arch/arm/mach-imx/common.h
+++ b/arch/arm/mach-imx/common.h
@@ -120,6 +120,7 @@ void imx6dl_pm_init(void);
 void imx6sl_pm_init(void);
 void imx6sx_pm_init(void);
 void imx6ul_pm_init(void);
+void imx7ulp_pm_init(void);
 
 #ifdef CONFIG_PM
 void imx51_pm_init(void);
diff --git a/arch/arm/mach-imx/cpu.c b/arch/arm/mach-imx/cpu.c
index c73593e..0b137ee 100644
--- a/arch/arm/mach-imx/cpu.c
+++ b/arch/arm/mach-imx/cpu.c
@@ -145,6 +145,9 @@ struct device * __init imx_soc_device_init(void)
 	case MXC_CPU_IMX7D:
 		soc_id = "i.MX7D";
 		break;
+	case MXC_CPU_IMX7ULP:
+		soc_id = "i.MX7ULP";
+		break;
 	default:
 		soc_id = "Unknown";
 	}
diff --git a/arch/arm/mach-imx/mach-imx7ulp.c b/arch/arm/mach-imx/mach-imx7ulp.c
new file mode 100644
index 0000000..ad8be07
--- /dev/null
+++ b/arch/arm/mach-imx/mach-imx7ulp.c
@@ -0,0 +1,32 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017-2018 NXP
+ *   Author: Dong Aisheng <aisheng.dong@nxp.com>
+ */
+
+#include <linux/irqchip.h>
+#include <linux/of_platform.h>
+#include <asm/mach/arch.h>
+
+#include "common.h"
+#include "hardware.h"
+
+static void __init imx7ulp_init_machine(void)
+{
+	imx7ulp_pm_init();
+
+	mxc_set_cpu_type(MXC_CPU_IMX7ULP);
+	imx_print_silicon_rev("i.MX7ULP", IMX_CHIP_REVISION_1_0);
+	of_platform_default_populate(NULL, NULL, imx_soc_device_init());
+}
+
+static const char *const imx7ulp_dt_compat[] __initconst = {
+	"fsl,imx7ulp",
+	NULL,
+};
+
+DT_MACHINE_START(IMX7ulp, "Freescale i.MX7ULP (Device Tree)")
+	.init_machine	= imx7ulp_init_machine,
+	.dt_compat	= imx7ulp_dt_compat,
+MACHINE_END
diff --git a/arch/arm/mach-imx/mxc.h b/arch/arm/mach-imx/mxc.h
index b130a53..8e72d4e 100644
--- a/arch/arm/mach-imx/mxc.h
+++ b/arch/arm/mach-imx/mxc.h
@@ -44,6 +44,7 @@
 #define MXC_CPU_IMX6ULZ		0x6b
 #define MXC_CPU_IMX6SLL		0x67
 #define MXC_CPU_IMX7D		0x72
+#define MXC_CPU_IMX7ULP		0xff
 
 #define IMX_DDR_TYPE_LPDDR2		1
 
diff --git a/arch/arm/mach-imx/pm-imx7ulp.c b/arch/arm/mach-imx/pm-imx7ulp.c
new file mode 100644
index 0000000..9fb7da0
--- /dev/null
+++ b/arch/arm/mach-imx/pm-imx7ulp.c
@@ -0,0 +1,28 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017-2018 NXP
+ *   Author: Dong Aisheng <aisheng.dong@nxp.com>
+ */
+
+#include <linux/io.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+
+#define SMC_PMCTRL		0x10
+#define BP_PMCTRL_PSTOPO        16
+#define PSTOPO_PSTOP3		0x3
+
+void __init imx7ulp_pm_init(void)
+{
+	struct device_node *np;
+	void __iomem *smc1_base;
+
+	np = of_find_compatible_node(NULL, NULL, "fsl,imx7ulp-smc1");
+	smc1_base = of_iomap(np, 0);
+	WARN_ON(!smc1_base);
+
+	/* Partial Stop mode 3 with system/bus clock enabled */
+	writel_relaxed(PSTOPO_PSTOP3 << BP_PMCTRL_PSTOPO,
+		       smc1_base + SMC_PMCTRL);
+}
-- 
2.7.4

[PATCH V2 6/8] dts: imx: add common imx7ulp dtsi support

[A.s. Dong]

The i.MX 7ULP family of processors represents NXP’s latest achievement
in ultra-low-power processing for use cases demanding long battery life.
Targeted towards the growing market of portable devices, the i.MX 7ULP
family of processors features NXP's advanced implementation of the Arm®
Cortex®-A7 core, the Arm Cortex-M4 core, as well as a 3D and 2D Graphics
Processing Units (GPUs).

This patch aims to add the initial support including:
1) CLK
2) GPIO PTC, PTD, PTE, PTF
3) uSDHC 1/2
4) LPUART 4/5/6/7
5) LPI2C 6/7

Cc: Rob Herring <robh+dt@kernel.org>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: devicetree@vger.kernel.org
Cc: Sascha Hauer <kernel@pengutronix.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
---
ChangeLog:
v1->v2:
 * update clk part due to binding change
 * separate soc.dtsi from board.dts
---
 arch/arm/boot/dts/imx7ulp.dtsi | 323 +++++++++++++++++++++++++++++++++++++++++
 1 file changed, 323 insertions(+)
 create mode 100644 arch/arm/boot/dts/imx7ulp.dtsi

diff --git a/arch/arm/boot/dts/imx7ulp.dtsi b/arch/arm/boot/dts/imx7ulp.dtsi
new file mode 100644
index 0000000..795edc2
--- /dev/null
+++ b/arch/arm/boot/dts/imx7ulp.dtsi
@@ -0,0 +1,323 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017-2018 NXP
+ *   Dong Aisheng <aisheng.dong@nxp.com>
+ */
+
+#include <dt-bindings/clock/imx7ulp-clock.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+#include "imx7ulp-pinfunc.h"
+
+/ {
+	interrupt-parent = <&intc>;
+
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	aliases {
+		gpio0 = &gpio_ptc;
+		gpio1 = &gpio_ptd;
+		gpio2 = &gpio_pte;
+		gpio3 = &gpio_ptf;
+		i2c0 = &lpi2c6;
+		i2c1 = &lpi2c7;
+		mmc0 = &usdhc0;
+		mmc1 = &usdhc1;
+		serial0 = &lpuart4;
+		serial1 = &lpuart5;
+		serial2 = &lpuart6;
+		serial3 = &lpuart7;
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu0: cpu@0 {
+			compatible = "arm,cortex-a7";
+			device_type = "cpu";
+			reg = <0>;
+		};
+	};
+
+	intc: interrupt-controller@40021000 {
+		compatible = "arm,cortex-a7-gic";
+		#interrupt-cells = <3>;
+		interrupt-controller;
+		reg = <0x40021000 0x1000>,
+		      <0x40022000 0x1000>;
+	};
+
+	rosc: clock-rosc {
+		compatible = "fixed-clock";
+		clock-frequency = <32768>;
+		clock-output-names = "rosc";
+		#clock-cells = <0>;
+	};
+
+	sosc: clock-sosc {
+		compatible = "fixed-clock";
+		clock-frequency = <24000000>;
+		clock-output-names = "sosc";
+		#clock-cells = <0>;
+	};
+
+	sirc: clock-sirc {
+		compatible = "fixed-clock";
+		clock-frequency = <16000000>;
+		clock-output-names = "sirc";
+		#clock-cells = <0>;
+	};
+
+	firc: clock-firc {
+		compatible = "fixed-clock";
+		clock-frequency = <48000000>;
+		clock-output-names = "firc";
+		#clock-cells = <0>;
+	};
+
+	upll: clock-upll {
+		compatible = "fixed-clock";
+		clock-frequency = <480000000>;
+		clock-output-names = "upll";
+		#clock-cells = <0>;
+	};
+
+	mpll: clock-mpll {
+		compatible = "fixed-clock";
+		clock-frequency = <480000000>;
+		clock-output-names = "mpll";
+		#clock-cells = <0>;
+	};
+
+	timer {
+		compatible = "arm,armv7-timer";
+		arm,cpu-registers-not-fw-configured;
+		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+		clock-frequency = <1000000>;
+		status = "disabled";
+	};
+
+	ahbbridge0: bus@40000000 {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		reg = <0x40000000 0x800000>;
+		ranges;
+
+		lpuart4: serial@402d0000 {
+			compatible = "fsl,imx7ulp-lpuart";
+			reg = <0x402d0000 0x1000>;
+			interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&pcc2 IMX7ULP_CLK_LPUART4>;
+			clock-names = "ipg";
+			assigned-clocks = <&pcc2 IMX7ULP_CLK_LPUART4>;
+			assigned-clock-parents = <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>;
+			assigned-clock-rates = <24000000>;
+			status = "disabled";
+		};
+
+		lpuart5: serial@402e0000 {
+			compatible = "fsl,imx7ulp-lpuart";
+			reg = <0x402e0000 0x1000>;
+			interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&pcc2 IMX7ULP_CLK_LPUART5>;
+			clock-names = "ipg";
+			assigned-clocks = <&pcc2 IMX7ULP_CLK_LPUART5>;
+			assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;
+			assigned-clock-rates = <48000000>;
+			status = "disabled";
+		};
+
+		tpm5: tpm@40260000 {
+			compatible = "fsl,imx7ulp-tpm";
+			reg = <0x40260000 0x1000>;
+			interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,
+				 <&pcc2 IMX7ULP_CLK_LPTPM5>;
+			clock-names = "ipg", "per";
+		};
+
+		usdhc0: usdhc@40370000 {
+			compatible = "fsl,imx7ulp-usdhc", "fsl,imx6sx-usdhc";
+			reg = <0x40370000 0x10000>;
+			interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,
+				 <&scg1 IMX7ULP_CLK_NIC1_DIV>,
+				 <&pcc2 IMX7ULP_CLK_USDHC0>;
+			clock-names ="ipg", "ahb", "per";
+			assigned-clocks = <&pcc2 IMX7ULP_CLK_USDHC0>;
+			assigned-clock-parents = <&scg1 IMX7ULP_CLK_NIC1_DIV>;
+			bus-width = <4>;
+			fsl,tuning-start-tap = <20>;
+			fsl,tuning-step= <2>;
+			status = "disabled";
+		};
+
+		usdhc1: usdhc@40380000 {
+			compatible = "fsl,imx7ulp-usdhc", "fsl,imx6sx-usdhc";
+			reg = <0x40380000 0x10000>;
+			interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,
+				 <&scg1 IMX7ULP_CLK_NIC1_DIV>,
+				 <&pcc2 IMX7ULP_CLK_USDHC1>;
+			clock-names ="ipg", "ahb", "per";
+			assigned-clocks = <&pcc2 IMX7ULP_CLK_USDHC1>;
+			assigned-clock-parents = <&scg1 IMX7ULP_CLK_NIC1_DIV>;
+			bus-width = <4>;
+			fsl,tuning-start-tap = <20>;
+			fsl,tuning-step= <2>;
+			status = "disabled";
+		};
+
+		scg1: scg1@403e0000 {
+			compatible = "fsl,imx7ulp-scg1";
+			reg = <0x403e0000 0x10000>;
+			clocks = <&rosc>, <&sosc>, <&sirc>,
+				 <&firc>, <&upll>, <&mpll>;
+			clock-names = "rosc", "sosc", "sirc",
+				      "firc", "upll", "mpll";
+			#clock-cells = <1>;
+		};
+
+		pcc2: pcc2@403f0000 {
+			compatible = "fsl,imx7ulp-pcc2";
+			reg = <0x403f0000 0x10000>;
+			#clock-cells = <1>;
+			assigned-clocks = <&pcc2 IMX7ULP_CLK_LPTPM5>;
+			assigned-clock-parents = <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>;
+		};
+
+		smc1: smc1@40410000 {
+			compatible = "fsl,imx7ulp-smc1";
+			reg = <0x40410000 0x1000>;
+		};
+
+		pcc3: pcc3@40b30000 {
+			compatible = "fsl,imx7ulp-pcc3";
+			reg = <0x40b30000 0x10000>;
+			#clock-cells = <1>;
+		};
+	};
+
+	ahbbridge1: bus@40800000 {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		reg = <0x40800000 0x800000>;
+		ranges;
+
+		lpi2c6: lpi2c@40a40000 {
+			compatible = "fsl,imx7ulp-lpi2c";
+			reg = <0x40a40000 0x10000>;
+			interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&pcc3 IMX7ULP_CLK_LPI2C6>;
+			clock-names = "ipg";
+			assigned-clocks = <&pcc3 IMX7ULP_CLK_LPI2C6>;
+			assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;
+			assigned-clock-rates = <48000000>;
+			status = "disabled";
+		};
+
+		lpi2c7: lpi2c@40a50000 {
+			compatible = "fsl,imx7ulp-lpi2c";
+			reg = <0x40a50000 0x10000>;
+			interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&pcc3 IMX7ULP_CLK_LPI2C7>;
+			clock-names = "ipg";
+			assigned-clocks = <&pcc3 IMX7ULP_CLK_LPI2C7>;
+			assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;
+			assigned-clock-rates = <48000000>;
+			status = "disabled";
+		};
+
+		lpuart6: serial@40a60000 {
+			compatible = "fsl,imx7ulp-lpuart";
+			reg = <0x40a60000 0x1000>;
+			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&pcc3 IMX7ULP_CLK_LPUART6>;
+			clock-names = "ipg";
+			assigned-clocks = <&pcc3 IMX7ULP_CLK_LPUART6>;
+			assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;
+			assigned-clock-rates = <48000000>;
+			status = "disabled";
+		};
+
+		lpuart7: serial@40a70000 {
+			compatible = "fsl,imx7ulp-lpuart";
+			reg = <0x40a70000 0x1000>;
+			interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&pcc3  IMX7ULP_CLK_LPUART7>;
+			clock-names = "ipg";
+			assigned-clocks = <&pcc3 IMX7ULP_CLK_LPUART7>;
+			assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;
+			assigned-clock-rates = <48000000>;
+			status = "disabled";
+		};
+
+		iomuxc1: iomuxc@40ac0000 {
+			compatible = "fsl,imx7ulp-iomuxc1";
+			reg = <0x40ac0000 0x1000>;
+		};
+
+		gpio_ptc: gpio@40ae0000 {
+			compatible = "fsl,vf610-gpio";
+			reg = <0x40ae0000 0x1000 0x400f0000 0x40>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			clocks = <&pcc2 IMX7ULP_CLK_RGPIO2P1>,
+				 <&pcc3 IMX7ULP_CLK_PCTLC>;
+			clock-names = "gpio", "port";
+			gpio-ranges = <&iomuxc1 0 0 32>;
+		};
+
+		gpio_ptd: gpio@40af0000 {
+			compatible = "fsl,vf610-gpio";
+			reg = <0x40af0000 0x1000 0x400f0040 0x40>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			clocks = <&pcc2 IMX7ULP_CLK_RGPIO2P1>,
+				 <&pcc3 IMX7ULP_CLK_PCTLD>;
+			clock-names = "gpio", "port";
+			gpio-ranges = <&iomuxc1 0 32 32>;
+		};
+
+		gpio_pte: gpio@40b00000 {
+			compatible = "fsl,vf610-gpio";
+			reg = <0x40b00000 0x1000 0x400f0080 0x40>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			clocks = <&pcc2 IMX7ULP_CLK_RGPIO2P1>,
+				 <&pcc3 IMX7ULP_CLK_PCTLE>;
+			clock-names = "gpio", "port";
+			gpio-ranges = <&iomuxc1 0 64 32>;
+		};
+
+		gpio_ptf: gpio@40b10000 {
+			compatible = "fsl,vf610-gpio";
+			reg = <0x40b10000 0x1000 0x400f00c0 0x40>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			clocks = <&pcc2 IMX7ULP_CLK_RGPIO2P1>,
+				 <&pcc3 IMX7ULP_CLK_PCTLF>;
+			clock-names = "gpio", "port";
+			gpio-ranges = <&iomuxc1 0 96 32>;
+		};
+	};
+};
-- 
2.7.4

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

[PATCH V2 6/8] dts: imx: add common imx7ulp dtsi support

[A.s. Dong]

The i.MX 7ULP family of processors represents NXP?s latest achievement
in ultra-low-power processing for use cases demanding long battery life.
Targeted towards the growing market of portable devices, the i.MX 7ULP
family of processors features NXP's advanced implementation of the Arm?
Cortex?-A7 core, the Arm Cortex-M4 core, as well as a 3D and 2D Graphics
Processing Units (GPUs).

This patch aims to add the initial support including:
1) CLK
2) GPIO PTC, PTD, PTE, PTF
3) uSDHC 1/2
4) LPUART 4/5/6/7
5) LPI2C 6/7

Cc: Rob Herring <robh+dt@kernel.org>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: devicetree at vger.kernel.org
Cc: Sascha Hauer <kernel@pengutronix.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
---
ChangeLog:
v1->v2:
 * update clk part due to binding change
 * separate soc.dtsi from board.dts
---
 arch/arm/boot/dts/imx7ulp.dtsi | 323 +++++++++++++++++++++++++++++++++++++++++
 1 file changed, 323 insertions(+)
 create mode 100644 arch/arm/boot/dts/imx7ulp.dtsi

diff --git a/arch/arm/boot/dts/imx7ulp.dtsi b/arch/arm/boot/dts/imx7ulp.dtsi
new file mode 100644
index 0000000..795edc2
--- /dev/null
+++ b/arch/arm/boot/dts/imx7ulp.dtsi
@@ -0,0 +1,323 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017-2018 NXP
+ *   Dong Aisheng <aisheng.dong@nxp.com>
+ */
+
+#include <dt-bindings/clock/imx7ulp-clock.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+#include "imx7ulp-pinfunc.h"
+
+/ {
+	interrupt-parent = <&intc>;
+
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	aliases {
+		gpio0 = &gpio_ptc;
+		gpio1 = &gpio_ptd;
+		gpio2 = &gpio_pte;
+		gpio3 = &gpio_ptf;
+		i2c0 = &lpi2c6;
+		i2c1 = &lpi2c7;
+		mmc0 = &usdhc0;
+		mmc1 = &usdhc1;
+		serial0 = &lpuart4;
+		serial1 = &lpuart5;
+		serial2 = &lpuart6;
+		serial3 = &lpuart7;
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu0: cpu at 0 {
+			compatible = "arm,cortex-a7";
+			device_type = "cpu";
+			reg = <0>;
+		};
+	};
+
+	intc: interrupt-controller at 40021000 {
+		compatible = "arm,cortex-a7-gic";
+		#interrupt-cells = <3>;
+		interrupt-controller;
+		reg = <0x40021000 0x1000>,
+		      <0x40022000 0x1000>;
+	};
+
+	rosc: clock-rosc {
+		compatible = "fixed-clock";
+		clock-frequency = <32768>;
+		clock-output-names = "rosc";
+		#clock-cells = <0>;
+	};
+
+	sosc: clock-sosc {
+		compatible = "fixed-clock";
+		clock-frequency = <24000000>;
+		clock-output-names = "sosc";
+		#clock-cells = <0>;
+	};
+
+	sirc: clock-sirc {
+		compatible = "fixed-clock";
+		clock-frequency = <16000000>;
+		clock-output-names = "sirc";
+		#clock-cells = <0>;
+	};
+
+	firc: clock-firc {
+		compatible = "fixed-clock";
+		clock-frequency = <48000000>;
+		clock-output-names = "firc";
+		#clock-cells = <0>;
+	};
+
+	upll: clock-upll {
+		compatible = "fixed-clock";
+		clock-frequency = <480000000>;
+		clock-output-names = "upll";
+		#clock-cells = <0>;
+	};
+
+	mpll: clock-mpll {
+		compatible = "fixed-clock";
+		clock-frequency = <480000000>;
+		clock-output-names = "mpll";
+		#clock-cells = <0>;
+	};
+
+	timer {
+		compatible = "arm,armv7-timer";
+		arm,cpu-registers-not-fw-configured;
+		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+		clock-frequency = <1000000>;
+		status = "disabled";
+	};
+
+	ahbbridge0: bus at 40000000 {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		reg = <0x40000000 0x800000>;
+		ranges;
+
+		lpuart4: serial at 402d0000 {
+			compatible = "fsl,imx7ulp-lpuart";
+			reg = <0x402d0000 0x1000>;
+			interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&pcc2 IMX7ULP_CLK_LPUART4>;
+			clock-names = "ipg";
+			assigned-clocks = <&pcc2 IMX7ULP_CLK_LPUART4>;
+			assigned-clock-parents = <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>;
+			assigned-clock-rates = <24000000>;
+			status = "disabled";
+		};
+
+		lpuart5: serial at 402e0000 {
+			compatible = "fsl,imx7ulp-lpuart";
+			reg = <0x402e0000 0x1000>;
+			interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&pcc2 IMX7ULP_CLK_LPUART5>;
+			clock-names = "ipg";
+			assigned-clocks = <&pcc2 IMX7ULP_CLK_LPUART5>;
+			assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;
+			assigned-clock-rates = <48000000>;
+			status = "disabled";
+		};
+
+		tpm5: tpm at 40260000 {
+			compatible = "fsl,imx7ulp-tpm";
+			reg = <0x40260000 0x1000>;
+			interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,
+				 <&pcc2 IMX7ULP_CLK_LPTPM5>;
+			clock-names = "ipg", "per";
+		};
+
+		usdhc0: usdhc at 40370000 {
+			compatible = "fsl,imx7ulp-usdhc", "fsl,imx6sx-usdhc";
+			reg = <0x40370000 0x10000>;
+			interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,
+				 <&scg1 IMX7ULP_CLK_NIC1_DIV>,
+				 <&pcc2 IMX7ULP_CLK_USDHC0>;
+			clock-names ="ipg", "ahb", "per";
+			assigned-clocks = <&pcc2 IMX7ULP_CLK_USDHC0>;
+			assigned-clock-parents = <&scg1 IMX7ULP_CLK_NIC1_DIV>;
+			bus-width = <4>;
+			fsl,tuning-start-tap = <20>;
+			fsl,tuning-step= <2>;
+			status = "disabled";
+		};
+
+		usdhc1: usdhc at 40380000 {
+			compatible = "fsl,imx7ulp-usdhc", "fsl,imx6sx-usdhc";
+			reg = <0x40380000 0x10000>;
+			interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,
+				 <&scg1 IMX7ULP_CLK_NIC1_DIV>,
+				 <&pcc2 IMX7ULP_CLK_USDHC1>;
+			clock-names ="ipg", "ahb", "per";
+			assigned-clocks = <&pcc2 IMX7ULP_CLK_USDHC1>;
+			assigned-clock-parents = <&scg1 IMX7ULP_CLK_NIC1_DIV>;
+			bus-width = <4>;
+			fsl,tuning-start-tap = <20>;
+			fsl,tuning-step= <2>;
+			status = "disabled";
+		};
+
+		scg1: scg1 at 403e0000 {
+			compatible = "fsl,imx7ulp-scg1";
+			reg = <0x403e0000 0x10000>;
+			clocks = <&rosc>, <&sosc>, <&sirc>,
+				 <&firc>, <&upll>, <&mpll>;
+			clock-names = "rosc", "sosc", "sirc",
+				      "firc", "upll", "mpll";
+			#clock-cells = <1>;
+		};
+
+		pcc2: pcc2 at 403f0000 {
+			compatible = "fsl,imx7ulp-pcc2";
+			reg = <0x403f0000 0x10000>;
+			#clock-cells = <1>;
+			assigned-clocks = <&pcc2 IMX7ULP_CLK_LPTPM5>;
+			assigned-clock-parents = <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>;
+		};
+
+		smc1: smc1 at 40410000 {
+			compatible = "fsl,imx7ulp-smc1";
+			reg = <0x40410000 0x1000>;
+		};
+
+		pcc3: pcc3 at 40b30000 {
+			compatible = "fsl,imx7ulp-pcc3";
+			reg = <0x40b30000 0x10000>;
+			#clock-cells = <1>;
+		};
+	};
+
+	ahbbridge1: bus at 40800000 {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		reg = <0x40800000 0x800000>;
+		ranges;
+
+		lpi2c6: lpi2c at 40a40000 {
+			compatible = "fsl,imx7ulp-lpi2c";
+			reg = <0x40a40000 0x10000>;
+			interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&pcc3 IMX7ULP_CLK_LPI2C6>;
+			clock-names = "ipg";
+			assigned-clocks = <&pcc3 IMX7ULP_CLK_LPI2C6>;
+			assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;
+			assigned-clock-rates = <48000000>;
+			status = "disabled";
+		};
+
+		lpi2c7: lpi2c at 40a50000 {
+			compatible = "fsl,imx7ulp-lpi2c";
+			reg = <0x40a50000 0x10000>;
+			interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&pcc3 IMX7ULP_CLK_LPI2C7>;
+			clock-names = "ipg";
+			assigned-clocks = <&pcc3 IMX7ULP_CLK_LPI2C7>;
+			assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;
+			assigned-clock-rates = <48000000>;
+			status = "disabled";
+		};
+
+		lpuart6: serial at 40a60000 {
+			compatible = "fsl,imx7ulp-lpuart";
+			reg = <0x40a60000 0x1000>;
+			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&pcc3 IMX7ULP_CLK_LPUART6>;
+			clock-names = "ipg";
+			assigned-clocks = <&pcc3 IMX7ULP_CLK_LPUART6>;
+			assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;
+			assigned-clock-rates = <48000000>;
+			status = "disabled";
+		};
+
+		lpuart7: serial at 40a70000 {
+			compatible = "fsl,imx7ulp-lpuart";
+			reg = <0x40a70000 0x1000>;
+			interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&pcc3  IMX7ULP_CLK_LPUART7>;
+			clock-names = "ipg";
+			assigned-clocks = <&pcc3 IMX7ULP_CLK_LPUART7>;
+			assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;
+			assigned-clock-rates = <48000000>;
+			status = "disabled";
+		};
+
+		iomuxc1: iomuxc at 40ac0000 {
+			compatible = "fsl,imx7ulp-iomuxc1";
+			reg = <0x40ac0000 0x1000>;
+		};
+
+		gpio_ptc: gpio at 40ae0000 {
+			compatible = "fsl,vf610-gpio";
+			reg = <0x40ae0000 0x1000 0x400f0000 0x40>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			clocks = <&pcc2 IMX7ULP_CLK_RGPIO2P1>,
+				 <&pcc3 IMX7ULP_CLK_PCTLC>;
+			clock-names = "gpio", "port";
+			gpio-ranges = <&iomuxc1 0 0 32>;
+		};
+
+		gpio_ptd: gpio at 40af0000 {
+			compatible = "fsl,vf610-gpio";
+			reg = <0x40af0000 0x1000 0x400f0040 0x40>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			clocks = <&pcc2 IMX7ULP_CLK_RGPIO2P1>,
+				 <&pcc3 IMX7ULP_CLK_PCTLD>;
+			clock-names = "gpio", "port";
+			gpio-ranges = <&iomuxc1 0 32 32>;
+		};
+
+		gpio_pte: gpio at 40b00000 {
+			compatible = "fsl,vf610-gpio";
+			reg = <0x40b00000 0x1000 0x400f0080 0x40>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			clocks = <&pcc2 IMX7ULP_CLK_RGPIO2P1>,
+				 <&pcc3 IMX7ULP_CLK_PCTLE>;
+			clock-names = "gpio", "port";
+			gpio-ranges = <&iomuxc1 0 64 32>;
+		};
+
+		gpio_ptf: gpio at 40b10000 {
+			compatible = "fsl,vf610-gpio";
+			reg = <0x40b10000 0x1000 0x400f00c0 0x40>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			clocks = <&pcc2 IMX7ULP_CLK_RGPIO2P1>,
+				 <&pcc3 IMX7ULP_CLK_PCTLF>;
+			clock-names = "gpio", "port";
+			gpio-ranges = <&iomuxc1 0 96 32>;
+		};
+	};
+};
-- 
2.7.4

Re: [PATCH V2 6/8] dts: imx: add common imx7ulp dtsi support

[Rob Herring]

On Tue, Oct 23, 2018 at 11:49:25AM +0000, A.s. Dong wrote:
> The i.MX 7ULP family of processors represents NXP’s latest achievement
> in ultra-low-power processing for use cases demanding long battery life.
> Targeted towards the growing market of portable devices, the i.MX 7ULP
> family of processors features NXP's advanced implementation of the Arm®
> Cortex®-A7 core, the Arm Cortex-M4 core, as well as a 3D and 2D Graphics
> Processing Units (GPUs).
> 
> This patch aims to add the initial support including:
> 1) CLK
> 2) GPIO PTC, PTD, PTE, PTF
> 3) uSDHC 1/2
> 4) LPUART 4/5/6/7
> 5) LPI2C 6/7
> 
> Cc: Rob Herring <robh+dt@kernel.org>
> Cc: Shawn Guo <shawnguo@kernel.org>
> Cc: devicetree@vger.kernel.org
> Cc: Sascha Hauer <kernel@pengutronix.de>
> Cc: Fabio Estevam <fabio.estevam@nxp.com>
> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
> ---
> ChangeLog:
> v1->v2:
>  * update clk part due to binding change
>  * separate soc.dtsi from board.dts
> ---
>  arch/arm/boot/dts/imx7ulp.dtsi | 323 +++++++++++++++++++++++++++++++++++++++++
>  1 file changed, 323 insertions(+)
>  create mode 100644 arch/arm/boot/dts/imx7ulp.dtsi
> 
> diff --git a/arch/arm/boot/dts/imx7ulp.dtsi b/arch/arm/boot/dts/imx7ulp.dtsi
> new file mode 100644
> index 0000000..795edc2
> --- /dev/null
> +++ b/arch/arm/boot/dts/imx7ulp.dtsi
> @@ -0,0 +1,323 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright (C) 2016 Freescale Semiconductor, Inc.
> + * Copyright 2017-2018 NXP
> + *   Dong Aisheng <aisheng.dong@nxp.com>
> + */
> +
> +#include <dt-bindings/clock/imx7ulp-clock.h>
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> +#include "imx7ulp-pinfunc.h"
> +
> +/ {
> +	interrupt-parent = <&intc>;
> +
> +	#address-cells = <1>;
> +	#size-cells = <1>;
> +
> +	aliases {
> +		gpio0 = &gpio_ptc;
> +		gpio1 = &gpio_ptd;
> +		gpio2 = &gpio_pte;
> +		gpio3 = &gpio_ptf;
> +		i2c0 = &lpi2c6;
> +		i2c1 = &lpi2c7;
> +		mmc0 = &usdhc0;
> +		mmc1 = &usdhc1;
> +		serial0 = &lpuart4;
> +		serial1 = &lpuart5;
> +		serial2 = &lpuart6;
> +		serial3 = &lpuart7;
> +	};
> +
> +	cpus {
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +
> +		cpu0: cpu@0 {
> +			compatible = "arm,cortex-a7";
> +			device_type = "cpu";
> +			reg = <0>;
> +		};
> +	};
> +
> +	intc: interrupt-controller@40021000 {
> +		compatible = "arm,cortex-a7-gic";
> +		#interrupt-cells = <3>;
> +		interrupt-controller;
> +		reg = <0x40021000 0x1000>,
> +		      <0x40022000 0x1000>;
> +	};
> +
> +	rosc: clock-rosc {
> +		compatible = "fixed-clock";
> +		clock-frequency = <32768>;
> +		clock-output-names = "rosc";
> +		#clock-cells = <0>;
> +	};
> +
> +	sosc: clock-sosc {
> +		compatible = "fixed-clock";
> +		clock-frequency = <24000000>;
> +		clock-output-names = "sosc";
> +		#clock-cells = <0>;
> +	};
> +
> +	sirc: clock-sirc {
> +		compatible = "fixed-clock";
> +		clock-frequency = <16000000>;
> +		clock-output-names = "sirc";
> +		#clock-cells = <0>;
> +	};
> +
> +	firc: clock-firc {
> +		compatible = "fixed-clock";
> +		clock-frequency = <48000000>;
> +		clock-output-names = "firc";
> +		#clock-cells = <0>;
> +	};
> +
> +	upll: clock-upll {
> +		compatible = "fixed-clock";
> +		clock-frequency = <480000000>;
> +		clock-output-names = "upll";
> +		#clock-cells = <0>;
> +	};
> +
> +	mpll: clock-mpll {
> +		compatible = "fixed-clock";
> +		clock-frequency = <480000000>;
> +		clock-output-names = "mpll";
> +		#clock-cells = <0>;
> +	};
> +
> +	timer {
> +		compatible = "arm,armv7-timer";
> +		arm,cpu-registers-not-fw-configured;

AIUI, this was a work-around for some existing platform. New platforms 
should not have this property.

> +		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
> +			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
> +		clock-frequency = <1000000>;

This too should be initialized by firmware and not in DT IIRC.

> +		status = "disabled";

I think enabled should be the norm.

> +	};
> +
> +	ahbbridge0: bus@40000000 {
> +		compatible = "simple-bus";
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +		reg = <0x40000000 0x800000>;
> +		ranges;
> +
> +		lpuart4: serial@402d0000 {
> +			compatible = "fsl,imx7ulp-lpuart";
> +			reg = <0x402d0000 0x1000>;
> +			interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&pcc2 IMX7ULP_CLK_LPUART4>;
> +			clock-names = "ipg";
> +			assigned-clocks = <&pcc2 IMX7ULP_CLK_LPUART4>;
> +			assigned-clock-parents = <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>;
> +			assigned-clock-rates = <24000000>;
> +			status = "disabled";
> +		};
> +
> +		lpuart5: serial@402e0000 {
> +			compatible = "fsl,imx7ulp-lpuart";
> +			reg = <0x402e0000 0x1000>;
> +			interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&pcc2 IMX7ULP_CLK_LPUART5>;
> +			clock-names = "ipg";
> +			assigned-clocks = <&pcc2 IMX7ULP_CLK_LPUART5>;
> +			assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;
> +			assigned-clock-rates = <48000000>;
> +			status = "disabled";
> +		};
> +
> +		tpm5: tpm@40260000 {
> +			compatible = "fsl,imx7ulp-tpm";
> +			reg = <0x40260000 0x1000>;
> +			interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,
> +				 <&pcc2 IMX7ULP_CLK_LPTPM5>;
> +			clock-names = "ipg", "per";
> +		};
> +
> +		usdhc0: usdhc@40370000 {

mmc@... is the standard name.

> +			compatible = "fsl,imx7ulp-usdhc", "fsl,imx6sx-usdhc";
> +			reg = <0x40370000 0x10000>;
> +			interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,
> +				 <&scg1 IMX7ULP_CLK_NIC1_DIV>,
> +				 <&pcc2 IMX7ULP_CLK_USDHC0>;
> +			clock-names ="ipg", "ahb", "per";
> +			assigned-clocks = <&pcc2 IMX7ULP_CLK_USDHC0>;
> +			assigned-clock-parents = <&scg1 IMX7ULP_CLK_NIC1_DIV>;
> +			bus-width = <4>;
> +			fsl,tuning-start-tap = <20>;
> +			fsl,tuning-step= <2>;
> +			status = "disabled";
> +		};
> +
> +		usdhc1: usdhc@40380000 {

ditto.

> +			compatible = "fsl,imx7ulp-usdhc", "fsl,imx6sx-usdhc";
> +			reg = <0x40380000 0x10000>;
> +			interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,
> +				 <&scg1 IMX7ULP_CLK_NIC1_DIV>,
> +				 <&pcc2 IMX7ULP_CLK_USDHC1>;
> +			clock-names ="ipg", "ahb", "per";
> +			assigned-clocks = <&pcc2 IMX7ULP_CLK_USDHC1>;
> +			assigned-clock-parents = <&scg1 IMX7ULP_CLK_NIC1_DIV>;
> +			bus-width = <4>;
> +			fsl,tuning-start-tap = <20>;
> +			fsl,tuning-step= <2>;
> +			status = "disabled";
> +		};
> +
> +		scg1: scg1@403e0000 {

clock-controller@...

> +			compatible = "fsl,imx7ulp-scg1";
> +			reg = <0x403e0000 0x10000>;
> +			clocks = <&rosc>, <&sosc>, <&sirc>,
> +				 <&firc>, <&upll>, <&mpll>;
> +			clock-names = "rosc", "sosc", "sirc",
> +				      "firc", "upll", "mpll";
> +			#clock-cells = <1>;
> +		};
> +
> +		pcc2: pcc2@403f0000 {

clock-controller@...

> +			compatible = "fsl,imx7ulp-pcc2";
> +			reg = <0x403f0000 0x10000>;
> +			#clock-cells = <1>;
> +			assigned-clocks = <&pcc2 IMX7ULP_CLK_LPTPM5>;
> +			assigned-clock-parents = <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>;
> +		};
> +
> +		smc1: smc1@40410000 {
> +			compatible = "fsl,imx7ulp-smc1";
> +			reg = <0x40410000 0x1000>;
> +		};
> +
> +		pcc3: pcc3@40b30000 {

clock-controller@...

> +			compatible = "fsl,imx7ulp-pcc3";
> +			reg = <0x40b30000 0x10000>;
> +			#clock-cells = <1>;
> +		};
> +	};
> +
> +	ahbbridge1: bus@40800000 {
> +		compatible = "simple-bus";
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +		reg = <0x40800000 0x800000>;
> +		ranges;
> +
> +		lpi2c6: lpi2c@40a40000 {

i2c@...

> +			compatible = "fsl,imx7ulp-lpi2c";
> +			reg = <0x40a40000 0x10000>;
> +			interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&pcc3 IMX7ULP_CLK_LPI2C6>;
> +			clock-names = "ipg";
> +			assigned-clocks = <&pcc3 IMX7ULP_CLK_LPI2C6>;
> +			assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;
> +			assigned-clock-rates = <48000000>;
> +			status = "disabled";
> +		};
> +
> +		lpi2c7: lpi2c@40a50000 {

i2c@...

> +			compatible = "fsl,imx7ulp-lpi2c";
> +			reg = <0x40a50000 0x10000>;
> +			interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&pcc3 IMX7ULP_CLK_LPI2C7>;
> +			clock-names = "ipg";
> +			assigned-clocks = <&pcc3 IMX7ULP_CLK_LPI2C7>;
> +			assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;
> +			assigned-clock-rates = <48000000>;
> +			status = "disabled";
> +		};
> +
> +		lpuart6: serial@40a60000 {
> +			compatible = "fsl,imx7ulp-lpuart";
> +			reg = <0x40a60000 0x1000>;
> +			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&pcc3 IMX7ULP_CLK_LPUART6>;
> +			clock-names = "ipg";
> +			assigned-clocks = <&pcc3 IMX7ULP_CLK_LPUART6>;
> +			assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;
> +			assigned-clock-rates = <48000000>;
> +			status = "disabled";
> +		};
> +
> +		lpuart7: serial@40a70000 {
> +			compatible = "fsl,imx7ulp-lpuart";
> +			reg = <0x40a70000 0x1000>;
> +			interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&pcc3  IMX7ULP_CLK_LPUART7>;
> +			clock-names = "ipg";
> +			assigned-clocks = <&pcc3 IMX7ULP_CLK_LPUART7>;
> +			assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;
> +			assigned-clock-rates = <48000000>;
> +			status = "disabled";
> +		};
> +
> +		iomuxc1: iomuxc@40ac0000 {

pinctrl@...

> +			compatible = "fsl,imx7ulp-iomuxc1";
> +			reg = <0x40ac0000 0x1000>;
> +		};
> +
> +		gpio_ptc: gpio@40ae0000 {
> +			compatible = "fsl,vf610-gpio";
> +			reg = <0x40ae0000 0x1000 0x400f0000 0x40>;
> +			gpio-controller;
> +			#gpio-cells = <2>;
> +			interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
> +			interrupt-controller;
> +			#interrupt-cells = <2>;
> +			clocks = <&pcc2 IMX7ULP_CLK_RGPIO2P1>,
> +				 <&pcc3 IMX7ULP_CLK_PCTLC>;
> +			clock-names = "gpio", "port";
> +			gpio-ranges = <&iomuxc1 0 0 32>;
> +		};
> +
> +		gpio_ptd: gpio@40af0000 {
> +			compatible = "fsl,vf610-gpio";
> +			reg = <0x40af0000 0x1000 0x400f0040 0x40>;
> +			gpio-controller;
> +			#gpio-cells = <2>;
> +			interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
> +			interrupt-controller;
> +			#interrupt-cells = <2>;
> +			clocks = <&pcc2 IMX7ULP_CLK_RGPIO2P1>,
> +				 <&pcc3 IMX7ULP_CLK_PCTLD>;
> +			clock-names = "gpio", "port";
> +			gpio-ranges = <&iomuxc1 0 32 32>;
> +		};
> +
> +		gpio_pte: gpio@40b00000 {
> +			compatible = "fsl,vf610-gpio";
> +			reg = <0x40b00000 0x1000 0x400f0080 0x40>;
> +			gpio-controller;
> +			#gpio-cells = <2>;
> +			interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
> +			interrupt-controller;
> +			#interrupt-cells = <2>;
> +			clocks = <&pcc2 IMX7ULP_CLK_RGPIO2P1>,
> +				 <&pcc3 IMX7ULP_CLK_PCTLE>;
> +			clock-names = "gpio", "port";
> +			gpio-ranges = <&iomuxc1 0 64 32>;
> +		};
> +
> +		gpio_ptf: gpio@40b10000 {
> +			compatible = "fsl,vf610-gpio";
> +			reg = <0x40b10000 0x1000 0x400f00c0 0x40>;
> +			gpio-controller;
> +			#gpio-cells = <2>;
> +			interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
> +			interrupt-controller;
> +			#interrupt-cells = <2>;
> +			clocks = <&pcc2 IMX7ULP_CLK_RGPIO2P1>,
> +				 <&pcc3 IMX7ULP_CLK_PCTLF>;
> +			clock-names = "gpio", "port";
> +			gpio-ranges = <&iomuxc1 0 96 32>;
> +		};
> +	};
> +};
> -- 
> 2.7.4
> 

_______________________________________________
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[PATCH V2 6/8] dts: imx: add common imx7ulp dtsi support

[Rob Herring]

On Tue, Oct 23, 2018 at 11:49:25AM +0000, A.s. Dong wrote:
> The i.MX 7ULP family of processors represents NXP?s latest achievement
> in ultra-low-power processing for use cases demanding long battery life.
> Targeted towards the growing market of portable devices, the i.MX 7ULP
> family of processors features NXP's advanced implementation of the Arm?
> Cortex?-A7 core, the Arm Cortex-M4 core, as well as a 3D and 2D Graphics
> Processing Units (GPUs).
> 
> This patch aims to add the initial support including:
> 1) CLK
> 2) GPIO PTC, PTD, PTE, PTF
> 3) uSDHC 1/2
> 4) LPUART 4/5/6/7
> 5) LPI2C 6/7
> 
> Cc: Rob Herring <robh+dt@kernel.org>
> Cc: Shawn Guo <shawnguo@kernel.org>
> Cc: devicetree at vger.kernel.org
> Cc: Sascha Hauer <kernel@pengutronix.de>
> Cc: Fabio Estevam <fabio.estevam@nxp.com>
> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
> ---
> ChangeLog:
> v1->v2:
>  * update clk part due to binding change
>  * separate soc.dtsi from board.dts
> ---
>  arch/arm/boot/dts/imx7ulp.dtsi | 323 +++++++++++++++++++++++++++++++++++++++++
>  1 file changed, 323 insertions(+)
>  create mode 100644 arch/arm/boot/dts/imx7ulp.dtsi
> 
> diff --git a/arch/arm/boot/dts/imx7ulp.dtsi b/arch/arm/boot/dts/imx7ulp.dtsi
> new file mode 100644
> index 0000000..795edc2
> --- /dev/null
> +++ b/arch/arm/boot/dts/imx7ulp.dtsi
> @@ -0,0 +1,323 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright (C) 2016 Freescale Semiconductor, Inc.
> + * Copyright 2017-2018 NXP
> + *   Dong Aisheng <aisheng.dong@nxp.com>
> + */
> +
> +#include <dt-bindings/clock/imx7ulp-clock.h>
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> +#include "imx7ulp-pinfunc.h"
> +
> +/ {
> +	interrupt-parent = <&intc>;
> +
> +	#address-cells = <1>;
> +	#size-cells = <1>;
> +
> +	aliases {
> +		gpio0 = &gpio_ptc;
> +		gpio1 = &gpio_ptd;
> +		gpio2 = &gpio_pte;
> +		gpio3 = &gpio_ptf;
> +		i2c0 = &lpi2c6;
> +		i2c1 = &lpi2c7;
> +		mmc0 = &usdhc0;
> +		mmc1 = &usdhc1;
> +		serial0 = &lpuart4;
> +		serial1 = &lpuart5;
> +		serial2 = &lpuart6;
> +		serial3 = &lpuart7;
> +	};
> +
> +	cpus {
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +
> +		cpu0: cpu at 0 {
> +			compatible = "arm,cortex-a7";
> +			device_type = "cpu";
> +			reg = <0>;
> +		};
> +	};
> +
> +	intc: interrupt-controller at 40021000 {
> +		compatible = "arm,cortex-a7-gic";
> +		#interrupt-cells = <3>;
> +		interrupt-controller;
> +		reg = <0x40021000 0x1000>,
> +		      <0x40022000 0x1000>;
> +	};
> +
> +	rosc: clock-rosc {
> +		compatible = "fixed-clock";
> +		clock-frequency = <32768>;
> +		clock-output-names = "rosc";
> +		#clock-cells = <0>;
> +	};
> +
> +	sosc: clock-sosc {
> +		compatible = "fixed-clock";
> +		clock-frequency = <24000000>;
> +		clock-output-names = "sosc";
> +		#clock-cells = <0>;
> +	};
> +
> +	sirc: clock-sirc {
> +		compatible = "fixed-clock";
> +		clock-frequency = <16000000>;
> +		clock-output-names = "sirc";
> +		#clock-cells = <0>;
> +	};
> +
> +	firc: clock-firc {
> +		compatible = "fixed-clock";
> +		clock-frequency = <48000000>;
> +		clock-output-names = "firc";
> +		#clock-cells = <0>;
> +	};
> +
> +	upll: clock-upll {
> +		compatible = "fixed-clock";
> +		clock-frequency = <480000000>;
> +		clock-output-names = "upll";
> +		#clock-cells = <0>;
> +	};
> +
> +	mpll: clock-mpll {
> +		compatible = "fixed-clock";
> +		clock-frequency = <480000000>;
> +		clock-output-names = "mpll";
> +		#clock-cells = <0>;
> +	};
> +
> +	timer {
> +		compatible = "arm,armv7-timer";
> +		arm,cpu-registers-not-fw-configured;

AIUI, this was a work-around for some existing platform. New platforms 
should not have this property.

> +		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
> +			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
> +		clock-frequency = <1000000>;

This too should be initialized by firmware and not in DT IIRC.

> +		status = "disabled";

I think enabled should be the norm.

> +	};
> +
> +	ahbbridge0: bus at 40000000 {
> +		compatible = "simple-bus";
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +		reg = <0x40000000 0x800000>;
> +		ranges;
> +
> +		lpuart4: serial at 402d0000 {
> +			compatible = "fsl,imx7ulp-lpuart";
> +			reg = <0x402d0000 0x1000>;
> +			interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&pcc2 IMX7ULP_CLK_LPUART4>;
> +			clock-names = "ipg";
> +			assigned-clocks = <&pcc2 IMX7ULP_CLK_LPUART4>;
> +			assigned-clock-parents = <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>;
> +			assigned-clock-rates = <24000000>;
> +			status = "disabled";
> +		};
> +
> +		lpuart5: serial at 402e0000 {
> +			compatible = "fsl,imx7ulp-lpuart";
> +			reg = <0x402e0000 0x1000>;
> +			interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&pcc2 IMX7ULP_CLK_LPUART5>;
> +			clock-names = "ipg";
> +			assigned-clocks = <&pcc2 IMX7ULP_CLK_LPUART5>;
> +			assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;
> +			assigned-clock-rates = <48000000>;
> +			status = "disabled";
> +		};
> +
> +		tpm5: tpm at 40260000 {
> +			compatible = "fsl,imx7ulp-tpm";
> +			reg = <0x40260000 0x1000>;
> +			interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,
> +				 <&pcc2 IMX7ULP_CLK_LPTPM5>;
> +			clock-names = "ipg", "per";
> +		};
> +
> +		usdhc0: usdhc at 40370000 {

mmc at ... is the standard name.

> +			compatible = "fsl,imx7ulp-usdhc", "fsl,imx6sx-usdhc";
> +			reg = <0x40370000 0x10000>;
> +			interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,
> +				 <&scg1 IMX7ULP_CLK_NIC1_DIV>,
> +				 <&pcc2 IMX7ULP_CLK_USDHC0>;
> +			clock-names ="ipg", "ahb", "per";
> +			assigned-clocks = <&pcc2 IMX7ULP_CLK_USDHC0>;
> +			assigned-clock-parents = <&scg1 IMX7ULP_CLK_NIC1_DIV>;
> +			bus-width = <4>;
> +			fsl,tuning-start-tap = <20>;
> +			fsl,tuning-step= <2>;
> +			status = "disabled";
> +		};
> +
> +		usdhc1: usdhc at 40380000 {

ditto.

> +			compatible = "fsl,imx7ulp-usdhc", "fsl,imx6sx-usdhc";
> +			reg = <0x40380000 0x10000>;
> +			interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,
> +				 <&scg1 IMX7ULP_CLK_NIC1_DIV>,
> +				 <&pcc2 IMX7ULP_CLK_USDHC1>;
> +			clock-names ="ipg", "ahb", "per";
> +			assigned-clocks = <&pcc2 IMX7ULP_CLK_USDHC1>;
> +			assigned-clock-parents = <&scg1 IMX7ULP_CLK_NIC1_DIV>;
> +			bus-width = <4>;
> +			fsl,tuning-start-tap = <20>;
> +			fsl,tuning-step= <2>;
> +			status = "disabled";
> +		};
> +
> +		scg1: scg1 at 403e0000 {

clock-controller at ...

> +			compatible = "fsl,imx7ulp-scg1";
> +			reg = <0x403e0000 0x10000>;
> +			clocks = <&rosc>, <&sosc>, <&sirc>,
> +				 <&firc>, <&upll>, <&mpll>;
> +			clock-names = "rosc", "sosc", "sirc",
> +				      "firc", "upll", "mpll";
> +			#clock-cells = <1>;
> +		};
> +
> +		pcc2: pcc2 at 403f0000 {

clock-controller at ...

> +			compatible = "fsl,imx7ulp-pcc2";
> +			reg = <0x403f0000 0x10000>;
> +			#clock-cells = <1>;
> +			assigned-clocks = <&pcc2 IMX7ULP_CLK_LPTPM5>;
> +			assigned-clock-parents = <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>;
> +		};
> +
> +		smc1: smc1 at 40410000 {
> +			compatible = "fsl,imx7ulp-smc1";
> +			reg = <0x40410000 0x1000>;
> +		};
> +
> +		pcc3: pcc3 at 40b30000 {

clock-controller at ...

> +			compatible = "fsl,imx7ulp-pcc3";
> +			reg = <0x40b30000 0x10000>;
> +			#clock-cells = <1>;
> +		};
> +	};
> +
> +	ahbbridge1: bus at 40800000 {
> +		compatible = "simple-bus";
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +		reg = <0x40800000 0x800000>;
> +		ranges;
> +
> +		lpi2c6: lpi2c at 40a40000 {

i2c at ...

> +			compatible = "fsl,imx7ulp-lpi2c";
> +			reg = <0x40a40000 0x10000>;
> +			interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&pcc3 IMX7ULP_CLK_LPI2C6>;
> +			clock-names = "ipg";
> +			assigned-clocks = <&pcc3 IMX7ULP_CLK_LPI2C6>;
> +			assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;
> +			assigned-clock-rates = <48000000>;
> +			status = "disabled";
> +		};
> +
> +		lpi2c7: lpi2c at 40a50000 {

i2c at ...

> +			compatible = "fsl,imx7ulp-lpi2c";
> +			reg = <0x40a50000 0x10000>;
> +			interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&pcc3 IMX7ULP_CLK_LPI2C7>;
> +			clock-names = "ipg";
> +			assigned-clocks = <&pcc3 IMX7ULP_CLK_LPI2C7>;
> +			assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;
> +			assigned-clock-rates = <48000000>;
> +			status = "disabled";
> +		};
> +
> +		lpuart6: serial at 40a60000 {
> +			compatible = "fsl,imx7ulp-lpuart";
> +			reg = <0x40a60000 0x1000>;
> +			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&pcc3 IMX7ULP_CLK_LPUART6>;
> +			clock-names = "ipg";
> +			assigned-clocks = <&pcc3 IMX7ULP_CLK_LPUART6>;
> +			assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;
> +			assigned-clock-rates = <48000000>;
> +			status = "disabled";
> +		};
> +
> +		lpuart7: serial at 40a70000 {
> +			compatible = "fsl,imx7ulp-lpuart";
> +			reg = <0x40a70000 0x1000>;
> +			interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&pcc3  IMX7ULP_CLK_LPUART7>;
> +			clock-names = "ipg";
> +			assigned-clocks = <&pcc3 IMX7ULP_CLK_LPUART7>;
> +			assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;
> +			assigned-clock-rates = <48000000>;
> +			status = "disabled";
> +		};
> +
> +		iomuxc1: iomuxc at 40ac0000 {

pinctrl at ...

> +			compatible = "fsl,imx7ulp-iomuxc1";
> +			reg = <0x40ac0000 0x1000>;
> +		};
> +
> +		gpio_ptc: gpio at 40ae0000 {
> +			compatible = "fsl,vf610-gpio";
> +			reg = <0x40ae0000 0x1000 0x400f0000 0x40>;
> +			gpio-controller;
> +			#gpio-cells = <2>;
> +			interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
> +			interrupt-controller;
> +			#interrupt-cells = <2>;
> +			clocks = <&pcc2 IMX7ULP_CLK_RGPIO2P1>,
> +				 <&pcc3 IMX7ULP_CLK_PCTLC>;
> +			clock-names = "gpio", "port";
> +			gpio-ranges = <&iomuxc1 0 0 32>;
> +		};
> +
> +		gpio_ptd: gpio at 40af0000 {
> +			compatible = "fsl,vf610-gpio";
> +			reg = <0x40af0000 0x1000 0x400f0040 0x40>;
> +			gpio-controller;
> +			#gpio-cells = <2>;
> +			interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
> +			interrupt-controller;
> +			#interrupt-cells = <2>;
> +			clocks = <&pcc2 IMX7ULP_CLK_RGPIO2P1>,
> +				 <&pcc3 IMX7ULP_CLK_PCTLD>;
> +			clock-names = "gpio", "port";
> +			gpio-ranges = <&iomuxc1 0 32 32>;
> +		};
> +
> +		gpio_pte: gpio at 40b00000 {
> +			compatible = "fsl,vf610-gpio";
> +			reg = <0x40b00000 0x1000 0x400f0080 0x40>;
> +			gpio-controller;
> +			#gpio-cells = <2>;
> +			interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
> +			interrupt-controller;
> +			#interrupt-cells = <2>;
> +			clocks = <&pcc2 IMX7ULP_CLK_RGPIO2P1>,
> +				 <&pcc3 IMX7ULP_CLK_PCTLE>;
> +			clock-names = "gpio", "port";
> +			gpio-ranges = <&iomuxc1 0 64 32>;
> +		};
> +
> +		gpio_ptf: gpio at 40b10000 {
> +			compatible = "fsl,vf610-gpio";
> +			reg = <0x40b10000 0x1000 0x400f00c0 0x40>;
> +			gpio-controller;
> +			#gpio-cells = <2>;
> +			interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
> +			interrupt-controller;
> +			#interrupt-cells = <2>;
> +			clocks = <&pcc2 IMX7ULP_CLK_RGPIO2P1>,
> +				 <&pcc3 IMX7ULP_CLK_PCTLF>;
> +			clock-names = "gpio", "port";
> +			gpio-ranges = <&iomuxc1 0 96 32>;
> +		};
> +	};
> +};
> -- 
> 2.7.4
> 

RE: [PATCH V2 6/8] dts: imx: add common imx7ulp dtsi support

[A.s. Dong]

> -----Original Message-----
> From: Rob Herring [mailto:robh@kernel.org]
> Sent: Thursday, October 25, 2018 6:02 AM
[...]
> On Tue, Oct 23, 2018 at 11:49:25AM +0000, A.s. Dong wrote:
> > The i.MX 7ULP family of processors represents NXP’s latest achievement
> > in ultra-low-power processing for use cases demanding long battery life.
> > Targeted towards the growing market of portable devices, the i.MX 7ULP
> > family of processors features NXP's advanced implementation of the
> > Arm®
> > Cortex®-A7 core, the Arm Cortex-M4 core, as well as a 3D and 2D
> > Graphics Processing Units (GPUs).
> >
> > This patch aims to add the initial support including:
> > 1) CLK
> > 2) GPIO PTC, PTD, PTE, PTF
> > 3) uSDHC 1/2
> > 4) LPUART 4/5/6/7
> > 5) LPI2C 6/7
> >
> > Cc: Rob Herring <robh+dt@kernel.org>
> > Cc: Shawn Guo <shawnguo@kernel.org>
> > Cc: devicetree@vger.kernel.org
> > Cc: Sascha Hauer <kernel@pengutronix.de>
> > Cc: Fabio Estevam <fabio.estevam@nxp.com>
> > Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
> > ---
> > ChangeLog:
> > v1->v2:
> >  * update clk part due to binding change
> >  * separate soc.dtsi from board.dts
> > ---
> >  arch/arm/boot/dts/imx7ulp.dtsi | 323
> > +++++++++++++++++++++++++++++++++++++++++
> >  1 file changed, 323 insertions(+)
> >  create mode 100644 arch/arm/boot/dts/imx7ulp.dtsi
> >
> > diff --git a/arch/arm/boot/dts/imx7ulp.dtsi
> > b/arch/arm/boot/dts/imx7ulp.dtsi new file mode 100644 index
> > 0000000..795edc2
> > --- /dev/null
> > +++ b/arch/arm/boot/dts/imx7ulp.dtsi
> > @@ -0,0 +1,323 @@
> > +// SPDX-License-Identifier: GPL-2.0+
> > +/*
> > + * Copyright (C) 2016 Freescale Semiconductor, Inc.
> > + * Copyright 2017-2018 NXP
> > + *   Dong Aisheng <aisheng.dong@nxp.com>
> > + */
> > +
> > +#include <dt-bindings/clock/imx7ulp-clock.h>
> > +#include <dt-bindings/gpio/gpio.h>
> > +#include <dt-bindings/interrupt-controller/arm-gic.h>
> > +
> > +#include "imx7ulp-pinfunc.h"
> > +
> > +/ {
> > +	interrupt-parent = <&intc>;
> > +
> > +	#address-cells = <1>;
> > +	#size-cells = <1>;
> > +
> > +	aliases {
> > +		gpio0 = &gpio_ptc;
> > +		gpio1 = &gpio_ptd;
> > +		gpio2 = &gpio_pte;
> > +		gpio3 = &gpio_ptf;
> > +		i2c0 = &lpi2c6;
> > +		i2c1 = &lpi2c7;
> > +		mmc0 = &usdhc0;
> > +		mmc1 = &usdhc1;
> > +		serial0 = &lpuart4;
> > +		serial1 = &lpuart5;
> > +		serial2 = &lpuart6;
> > +		serial3 = &lpuart7;
> > +	};
> > +
> > +	cpus {
> > +		#address-cells = <1>;
> > +		#size-cells = <0>;
> > +
> > +		cpu0: cpu@0 {
> > +			compatible = "arm,cortex-a7";
> > +			device_type = "cpu";
> > +			reg = <0>;
> > +		};
> > +	};
> > +
> > +	intc: interrupt-controller@40021000 {
> > +		compatible = "arm,cortex-a7-gic";
> > +		#interrupt-cells = <3>;
> > +		interrupt-controller;
> > +		reg = <0x40021000 0x1000>,
> > +		      <0x40022000 0x1000>;
> > +	};
> > +
> > +	rosc: clock-rosc {
> > +		compatible = "fixed-clock";
> > +		clock-frequency = <32768>;
> > +		clock-output-names = "rosc";
> > +		#clock-cells = <0>;
> > +	};
> > +
> > +	sosc: clock-sosc {
> > +		compatible = "fixed-clock";
> > +		clock-frequency = <24000000>;
> > +		clock-output-names = "sosc";
> > +		#clock-cells = <0>;
> > +	};
> > +
> > +	sirc: clock-sirc {
> > +		compatible = "fixed-clock";
> > +		clock-frequency = <16000000>;
> > +		clock-output-names = "sirc";
> > +		#clock-cells = <0>;
> > +	};
> > +
> > +	firc: clock-firc {
> > +		compatible = "fixed-clock";
> > +		clock-frequency = <48000000>;
> > +		clock-output-names = "firc";
> > +		#clock-cells = <0>;
> > +	};
> > +
> > +	upll: clock-upll {
> > +		compatible = "fixed-clock";
> > +		clock-frequency = <480000000>;
> > +		clock-output-names = "upll";
> > +		#clock-cells = <0>;
> > +	};
> > +
> > +	mpll: clock-mpll {
> > +		compatible = "fixed-clock";
> > +		clock-frequency = <480000000>;
> > +		clock-output-names = "mpll";
> > +		#clock-cells = <0>;
> > +	};
> > +
> > +	timer {
> > +		compatible = "arm,armv7-timer";
> > +		arm,cpu-registers-not-fw-configured;
> 
> AIUI, this was a work-around for some existing platform. New platforms should
> not have this property.
> 
> > +		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) |
> IRQ_TYPE_LEVEL_LOW)>,
> > +			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) |
> IRQ_TYPE_LEVEL_LOW)>;
> > +		clock-frequency = <1000000>;
> 
> This too should be initialized by firmware and not in DT IIRC.
> 

Sorry for the careless. I should double checking these codes before sending
as the origin code base is quite old since first version.


> > +		status = "disabled";
> 
> I think enabled should be the norm.
> 

This is mostly because the arm timer may stop during low power idle
and we already have a TPM timer function the same in SoC.
Do you think we should still enable it?

> > +	};
> > +
> > +	ahbbridge0: bus@40000000 {
> > +		compatible = "simple-bus";
> > +		#address-cells = <1>;
> > +		#size-cells = <1>;
> > +		reg = <0x40000000 0x800000>;
> > +		ranges;
> > +
> > +		lpuart4: serial@402d0000 {
> > +			compatible = "fsl,imx7ulp-lpuart";
> > +			reg = <0x402d0000 0x1000>;
> > +			interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
> > +			clocks = <&pcc2 IMX7ULP_CLK_LPUART4>;
> > +			clock-names = "ipg";
> > +			assigned-clocks = <&pcc2 IMX7ULP_CLK_LPUART4>;
> > +			assigned-clock-parents = <&scg1
> IMX7ULP_CLK_SOSC_BUS_CLK>;
> > +			assigned-clock-rates = <24000000>;
> > +			status = "disabled";
> > +		};
> > +
> > +		lpuart5: serial@402e0000 {
> > +			compatible = "fsl,imx7ulp-lpuart";
> > +			reg = <0x402e0000 0x1000>;
> > +			interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
> > +			clocks = <&pcc2 IMX7ULP_CLK_LPUART5>;
> > +			clock-names = "ipg";
> > +			assigned-clocks = <&pcc2 IMX7ULP_CLK_LPUART5>;
> > +			assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;
> > +			assigned-clock-rates = <48000000>;
> > +			status = "disabled";
> > +		};
> > +
> > +		tpm5: tpm@40260000 {
> > +			compatible = "fsl,imx7ulp-tpm";
> > +			reg = <0x40260000 0x1000>;
> > +			interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
> > +			clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,
> > +				 <&pcc2 IMX7ULP_CLK_LPTPM5>;
> > +			clock-names = "ipg", "per";
> > +		};
> > +
> > +		usdhc0: usdhc@40370000 {
> 
> mmc@... is the standard name.
> 

I should be more careful about these. Other places are the same.
Thanks for the reminder.

Regards
Dong Aisheng
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

[PATCH V2 6/8] dts: imx: add common imx7ulp dtsi support

[A.s. Dong]

> -----Original Message-----
> From: Rob Herring [mailto:robh at kernel.org]
> Sent: Thursday, October 25, 2018 6:02 AM
[...]
> On Tue, Oct 23, 2018 at 11:49:25AM +0000, A.s. Dong wrote:
> > The i.MX 7ULP family of processors represents NXP?s latest achievement
> > in ultra-low-power processing for use cases demanding long battery life.
> > Targeted towards the growing market of portable devices, the i.MX 7ULP
> > family of processors features NXP's advanced implementation of the
> > Arm?
> > Cortex?-A7 core, the Arm Cortex-M4 core, as well as a 3D and 2D
> > Graphics Processing Units (GPUs).
> >
> > This patch aims to add the initial support including:
> > 1) CLK
> > 2) GPIO PTC, PTD, PTE, PTF
> > 3) uSDHC 1/2
> > 4) LPUART 4/5/6/7
> > 5) LPI2C 6/7
> >
> > Cc: Rob Herring <robh+dt@kernel.org>
> > Cc: Shawn Guo <shawnguo@kernel.org>
> > Cc: devicetree at vger.kernel.org
> > Cc: Sascha Hauer <kernel@pengutronix.de>
> > Cc: Fabio Estevam <fabio.estevam@nxp.com>
> > Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
> > ---
> > ChangeLog:
> > v1->v2:
> >  * update clk part due to binding change
> >  * separate soc.dtsi from board.dts
> > ---
> >  arch/arm/boot/dts/imx7ulp.dtsi | 323
> > +++++++++++++++++++++++++++++++++++++++++
> >  1 file changed, 323 insertions(+)
> >  create mode 100644 arch/arm/boot/dts/imx7ulp.dtsi
> >
> > diff --git a/arch/arm/boot/dts/imx7ulp.dtsi
> > b/arch/arm/boot/dts/imx7ulp.dtsi new file mode 100644 index
> > 0000000..795edc2
> > --- /dev/null
> > +++ b/arch/arm/boot/dts/imx7ulp.dtsi
> > @@ -0,0 +1,323 @@
> > +// SPDX-License-Identifier: GPL-2.0+
> > +/*
> > + * Copyright (C) 2016 Freescale Semiconductor, Inc.
> > + * Copyright 2017-2018 NXP
> > + *   Dong Aisheng <aisheng.dong@nxp.com>
> > + */
> > +
> > +#include <dt-bindings/clock/imx7ulp-clock.h>
> > +#include <dt-bindings/gpio/gpio.h>
> > +#include <dt-bindings/interrupt-controller/arm-gic.h>
> > +
> > +#include "imx7ulp-pinfunc.h"
> > +
> > +/ {
> > +	interrupt-parent = <&intc>;
> > +
> > +	#address-cells = <1>;
> > +	#size-cells = <1>;
> > +
> > +	aliases {
> > +		gpio0 = &gpio_ptc;
> > +		gpio1 = &gpio_ptd;
> > +		gpio2 = &gpio_pte;
> > +		gpio3 = &gpio_ptf;
> > +		i2c0 = &lpi2c6;
> > +		i2c1 = &lpi2c7;
> > +		mmc0 = &usdhc0;
> > +		mmc1 = &usdhc1;
> > +		serial0 = &lpuart4;
> > +		serial1 = &lpuart5;
> > +		serial2 = &lpuart6;
> > +		serial3 = &lpuart7;
> > +	};
> > +
> > +	cpus {
> > +		#address-cells = <1>;
> > +		#size-cells = <0>;
> > +
> > +		cpu0: cpu at 0 {
> > +			compatible = "arm,cortex-a7";
> > +			device_type = "cpu";
> > +			reg = <0>;
> > +		};
> > +	};
> > +
> > +	intc: interrupt-controller at 40021000 {
> > +		compatible = "arm,cortex-a7-gic";
> > +		#interrupt-cells = <3>;
> > +		interrupt-controller;
> > +		reg = <0x40021000 0x1000>,
> > +		      <0x40022000 0x1000>;
> > +	};
> > +
> > +	rosc: clock-rosc {
> > +		compatible = "fixed-clock";
> > +		clock-frequency = <32768>;
> > +		clock-output-names = "rosc";
> > +		#clock-cells = <0>;
> > +	};
> > +
> > +	sosc: clock-sosc {
> > +		compatible = "fixed-clock";
> > +		clock-frequency = <24000000>;
> > +		clock-output-names = "sosc";
> > +		#clock-cells = <0>;
> > +	};
> > +
> > +	sirc: clock-sirc {
> > +		compatible = "fixed-clock";
> > +		clock-frequency = <16000000>;
> > +		clock-output-names = "sirc";
> > +		#clock-cells = <0>;
> > +	};
> > +
> > +	firc: clock-firc {
> > +		compatible = "fixed-clock";
> > +		clock-frequency = <48000000>;
> > +		clock-output-names = "firc";
> > +		#clock-cells = <0>;
> > +	};
> > +
> > +	upll: clock-upll {
> > +		compatible = "fixed-clock";
> > +		clock-frequency = <480000000>;
> > +		clock-output-names = "upll";
> > +		#clock-cells = <0>;
> > +	};
> > +
> > +	mpll: clock-mpll {
> > +		compatible = "fixed-clock";
> > +		clock-frequency = <480000000>;
> > +		clock-output-names = "mpll";
> > +		#clock-cells = <0>;
> > +	};
> > +
> > +	timer {
> > +		compatible = "arm,armv7-timer";
> > +		arm,cpu-registers-not-fw-configured;
> 
> AIUI, this was a work-around for some existing platform. New platforms should
> not have this property.
> 
> > +		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) |
> IRQ_TYPE_LEVEL_LOW)>,
> > +			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) |
> IRQ_TYPE_LEVEL_LOW)>;
> > +		clock-frequency = <1000000>;
> 
> This too should be initialized by firmware and not in DT IIRC.
> 

Sorry for the careless. I should double checking these codes before sending
as the origin code base is quite old since first version.


> > +		status = "disabled";
> 
> I think enabled should be the norm.
> 

This is mostly because the arm timer may stop during low power idle
and we already have a TPM timer function the same in SoC.
Do you think we should still enable it?

> > +	};
> > +
> > +	ahbbridge0: bus at 40000000 {
> > +		compatible = "simple-bus";
> > +		#address-cells = <1>;
> > +		#size-cells = <1>;
> > +		reg = <0x40000000 0x800000>;
> > +		ranges;
> > +
> > +		lpuart4: serial at 402d0000 {
> > +			compatible = "fsl,imx7ulp-lpuart";
> > +			reg = <0x402d0000 0x1000>;
> > +			interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
> > +			clocks = <&pcc2 IMX7ULP_CLK_LPUART4>;
> > +			clock-names = "ipg";
> > +			assigned-clocks = <&pcc2 IMX7ULP_CLK_LPUART4>;
> > +			assigned-clock-parents = <&scg1
> IMX7ULP_CLK_SOSC_BUS_CLK>;
> > +			assigned-clock-rates = <24000000>;
> > +			status = "disabled";
> > +		};
> > +
> > +		lpuart5: serial at 402e0000 {
> > +			compatible = "fsl,imx7ulp-lpuart";
> > +			reg = <0x402e0000 0x1000>;
> > +			interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
> > +			clocks = <&pcc2 IMX7ULP_CLK_LPUART5>;
> > +			clock-names = "ipg";
> > +			assigned-clocks = <&pcc2 IMX7ULP_CLK_LPUART5>;
> > +			assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;
> > +			assigned-clock-rates = <48000000>;
> > +			status = "disabled";
> > +		};
> > +
> > +		tpm5: tpm at 40260000 {
> > +			compatible = "fsl,imx7ulp-tpm";
> > +			reg = <0x40260000 0x1000>;
> > +			interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
> > +			clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,
> > +				 <&pcc2 IMX7ULP_CLK_LPTPM5>;
> > +			clock-names = "ipg", "per";
> > +		};
> > +
> > +		usdhc0: usdhc at 40370000 {
> 
> mmc at ... is the standard name.
> 

I should be more careful about these. Other places are the same.
Thanks for the reminder.

Regards
Dong Aisheng

Re: [PATCH V2 6/8] dts: imx: add common imx7ulp dtsi support

[Fabio Estevam]

On Tue, Oct 23, 2018 at 8:55 AM A.s. Dong <aisheng.dong@nxp.com> wrote:

> +               gpio_ptc: gpio@40ae0000 {
> +                       compatible = "fsl,vf610-gpio";

This should be:

compatible = "fsl,imx7ulp-gpio", "fsl,vf610-gpio";

[PATCH V2 6/8] dts: imx: add common imx7ulp dtsi support

[Fabio Estevam]

On Tue, Oct 23, 2018 at 8:55 AM A.s. Dong <aisheng.dong@nxp.com> wrote:

> +               gpio_ptc: gpio at 40ae0000 {
> +                       compatible = "fsl,vf610-gpio";

This should be:

compatible = "fsl,imx7ulp-gpio", "fsl,vf610-gpio";

RE: [PATCH V2 6/8] dts: imx: add common imx7ulp dtsi support

[A.s. Dong]

> -----Original Message-----
> From: Fabio Estevam [mailto:festevam@gmail.com]
> Sent: Friday, October 26, 2018 12:44 AM
[...]
> On Tue, Oct 23, 2018 at 8:55 AM A.s. Dong <aisheng.dong@nxp.com> wrote:
> 
> > +               gpio_ptc: gpio@40ae0000 {
> > +                       compatible = "fsl,vf610-gpio";
> 
> This should be:
> 
> compatible = "fsl,imx7ulp-gpio", "fsl,vf610-gpio";

That's true.
Thanks for reminder.

Regards
Dong Aisheng

[PATCH V2 6/8] dts: imx: add common imx7ulp dtsi support

[A.s. Dong]

> -----Original Message-----
> From: Fabio Estevam [mailto:festevam at gmail.com]
> Sent: Friday, October 26, 2018 12:44 AM
[...]
> On Tue, Oct 23, 2018 at 8:55 AM A.s. Dong <aisheng.dong@nxp.com> wrote:
> 
> > +               gpio_ptc: gpio at 40ae0000 {
> > +                       compatible = "fsl,vf610-gpio";
> 
> This should be:
> 
> compatible = "fsl,imx7ulp-gpio", "fsl,vf610-gpio";

That's true.
Thanks for reminder.

Regards
Dong Aisheng

[PATCH V2 7/8] dts: fsl: add imx7ulp evk support

[A.s. Dong]

The NXP i.MX 7ULP Evaluation Kit (EVK) provides a platform for rapid
evaluation of the i.MX 7ULP, which features NXP's advanced implementation
of the Arm® Cortex®-A7 core, the Arm Cortex-M4 core, as well as a 3D and
2D Graphics Processing Units (GPUs).

The EVK enables HDMI output for simple out-of-the-box to bring up but
allows reconfiguration for MIPI displays. The EVK is designed as a
System-On-Module(SOM) board that connects to an associated baseboard.
The SOM provides 1 GB LPDDR3, 8 MB Quad SPI flash, Micro SD 3.0 card
socket, WiFi/ Bluetooth capability, USB 2.0 OTG with Type C connector
and an NXP PF1550 power management IC (PMIC). The baseboard provides
additional capabilities including a full SD/MMC 3.0 card socket, audio
codec, multiple sensors, an HDMI connector, and an alternate MIPI display
connector. Additionally, the EVK facilitates software development with the
ultimate goal of faster time to market through the support of both
Linux® OS and AndroidTM rich operating systems, as well as FreeRTOS.

This patch aims to support the preliminary booting up features
as follows:
GPIO
LPUART
FEC
SD/MMC

See more board details:
https://www.nxp.com/products/processors-and-microcontrollers/
arm-based-processors-and-mcus/i.mx-applications-processors/
i.mx-7-processors/evaluation-kit-for-the-i.mx-7ulp-applications
-processor:MCIMX7ULP-EVK

Cc: Rob Herring <robh+dt@kernel.org>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: devicetree@vger.kernel.org
Cc: Sascha Hauer <kernel@pengutronix.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
---
ChangeLog:
v1->v2:
 * switch to SPDX license
 * pad name update
 * fix Character '_' not recommended in node name
 * separate from soc.dtsi file
---
 arch/arm/boot/dts/Makefile        |  2 +
 arch/arm/boot/dts/imx7ulp-evk.dts | 94 +++++++++++++++++++++++++++++++++++++++
 2 files changed, 96 insertions(+)
 create mode 100644 arch/arm/boot/dts/imx7ulp-evk.dts

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index d7268ae..39eac9c 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -573,6 +573,8 @@ dtb-$(CONFIG_SOC_IMX7D) += \
 	imx7d-sdb-sht11.dtb \
 	imx7s-colibri-eval-v3.dtb \
 	imx7s-warp.dtb
+dtb-$(CONFIG_SOC_IMX7ULP) += \
+	imx7ulp-evk.dtb
 dtb-$(CONFIG_SOC_LS1021A) += \
 	ls1021a-moxa-uc-8410a.dtb \
 	ls1021a-qds.dtb \
diff --git a/arch/arm/boot/dts/imx7ulp-evk.dts b/arch/arm/boot/dts/imx7ulp-evk.dts
new file mode 100644
index 0000000..d876cb3
--- /dev/null
+++ b/arch/arm/boot/dts/imx7ulp-evk.dts
@@ -0,0 +1,94 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017-2018 NXP
+ *   Dong Aisheng <aisheng.dong@nxp.com>
+ */
+
+/dts-v1/;
+
+#include "imx7ulp.dtsi"
+
+/ {
+	model = "NXP i.MX7ULP EVK";
+	compatible = "fsl,imx7ulp-evk", "fsl,imx7ulp", "Generic DT based system";
+
+	chosen {
+		stdout-path = &lpuart4;
+	};
+
+	memory@60000000 {
+		reg = <0x60000000 0x40000000>;
+	};
+
+	reg_vsd_3v3: regulator-vsd-3v3 {
+		compatible = "regulator-fixed";
+		regulator-name = "VSD_3V3";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_usdhc0_rst>;
+		gpio = <&gpio_ptd 0 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+	};
+};
+
+&lpuart4 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_lpuart4>;
+	status = "okay";
+};
+
+&usdhc0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usdhc0_cmd_data>, <&pinctrl_usdhc0_clk>,
+		    <&pinctrl_usdhc0_cd>;
+	cd-gpios = <&gpio_ptc 10 GPIO_ACTIVE_LOW>;
+	vmmc-supply = <&reg_vsd_3v3>;
+	status = "okay";
+};
+
+&iomuxc1 {
+	pinctrl_lpuart4: lpuart4grp {
+		pinmux = <
+			IMX7ULP_PAD_PTC3__LPUART4_RX
+			IMX7ULP_PAD_PTC2__LPUART4_TX
+		>;
+		bias-pull-up;
+	};
+
+	pinctrl_usdhc0_cmd_data: usdhc0-cmd-data-grp {
+		pinmux = <
+			IMX7ULP_PAD_PTD1__SDHC0_CMD
+			IMX7ULP_PAD_PTD2__SDHC0_CLK
+			IMX7ULP_PAD_PTD7__SDHC0_D3
+			IMX7ULP_PAD_PTD8__SDHC0_D2
+			IMX7ULP_PAD_PTD9__SDHC0_D1
+			IMX7ULP_PAD_PTD10__SDHC0_D0
+		>;
+		drive-strength = <1>;
+		bias-pull-up;
+	};
+
+	pinctrl_usdhc0_clk: usdhc0-clk-grp {
+		pinmux = <
+			IMX7ULP_PAD_PTD2__SDHC0_CLK
+		>;
+		drive-strength = <1>;
+		bias-pull-down;
+	};
+
+	pinctrl_usdhc0_cd: usdhc0-gpio-cd-grp {
+		pinmux = <
+			IMX7ULP_PAD_PTC10__PTC10	/* USDHC0 CD */
+		>;
+		bias-pull-up;
+	};
+
+	pinctrl_usdhc0_rst: usdhc0-gpio-rst-grp {
+		pinmux = <
+			IMX7ULP_PAD_PTD0__PTD0		/* USDHC0 RST */
+		>;
+		bias-pull-up;
+	};
+};
-- 
2.7.4

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[PATCH V2 7/8] dts: fsl: add imx7ulp evk support

[A.s. Dong]

The NXP i.MX 7ULP Evaluation Kit (EVK) provides a platform for rapid
evaluation of the i.MX 7ULP, which features NXP's advanced implementation
of the Arm? Cortex?-A7 core, the Arm Cortex-M4 core, as well as a 3D and
2D Graphics Processing Units (GPUs).

The EVK enables HDMI output for simple out-of-the-box to bring up but
allows reconfiguration for MIPI displays. The EVK is designed as a
System-On-Module(SOM) board that connects to an associated baseboard.
The SOM provides 1 GB LPDDR3, 8 MB Quad SPI flash, Micro SD 3.0 card
socket, WiFi/ Bluetooth capability, USB 2.0 OTG with Type C connector
and an NXP PF1550 power management IC (PMIC). The baseboard provides
additional capabilities including a full SD/MMC 3.0 card socket, audio
codec, multiple sensors, an HDMI connector, and an alternate MIPI display
connector. Additionally, the EVK facilitates software development with the
ultimate goal of faster time to market through the support of both
Linux? OS and AndroidTM rich operating systems, as well as FreeRTOS.

This patch aims to support the preliminary booting up features
as follows:
GPIO
LPUART
FEC
SD/MMC

See more board details:
https://www.nxp.com/products/processors-and-microcontrollers/
arm-based-processors-and-mcus/i.mx-applications-processors/
i.mx-7-processors/evaluation-kit-for-the-i.mx-7ulp-applications
-processor:MCIMX7ULP-EVK

Cc: Rob Herring <robh+dt@kernel.org>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: devicetree at vger.kernel.org
Cc: Sascha Hauer <kernel@pengutronix.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
---
ChangeLog:
v1->v2:
 * switch to SPDX license
 * pad name update
 * fix Character '_' not recommended in node name
 * separate from soc.dtsi file
---
 arch/arm/boot/dts/Makefile        |  2 +
 arch/arm/boot/dts/imx7ulp-evk.dts | 94 +++++++++++++++++++++++++++++++++++++++
 2 files changed, 96 insertions(+)
 create mode 100644 arch/arm/boot/dts/imx7ulp-evk.dts

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index d7268ae..39eac9c 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -573,6 +573,8 @@ dtb-$(CONFIG_SOC_IMX7D) += \
 	imx7d-sdb-sht11.dtb \
 	imx7s-colibri-eval-v3.dtb \
 	imx7s-warp.dtb
+dtb-$(CONFIG_SOC_IMX7ULP) += \
+	imx7ulp-evk.dtb
 dtb-$(CONFIG_SOC_LS1021A) += \
 	ls1021a-moxa-uc-8410a.dtb \
 	ls1021a-qds.dtb \
diff --git a/arch/arm/boot/dts/imx7ulp-evk.dts b/arch/arm/boot/dts/imx7ulp-evk.dts
new file mode 100644
index 0000000..d876cb3
--- /dev/null
+++ b/arch/arm/boot/dts/imx7ulp-evk.dts
@@ -0,0 +1,94 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017-2018 NXP
+ *   Dong Aisheng <aisheng.dong@nxp.com>
+ */
+
+/dts-v1/;
+
+#include "imx7ulp.dtsi"
+
+/ {
+	model = "NXP i.MX7ULP EVK";
+	compatible = "fsl,imx7ulp-evk", "fsl,imx7ulp", "Generic DT based system";
+
+	chosen {
+		stdout-path = &lpuart4;
+	};
+
+	memory at 60000000 {
+		reg = <0x60000000 0x40000000>;
+	};
+
+	reg_vsd_3v3: regulator-vsd-3v3 {
+		compatible = "regulator-fixed";
+		regulator-name = "VSD_3V3";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_usdhc0_rst>;
+		gpio = <&gpio_ptd 0 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+	};
+};
+
+&lpuart4 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_lpuart4>;
+	status = "okay";
+};
+
+&usdhc0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usdhc0_cmd_data>, <&pinctrl_usdhc0_clk>,
+		    <&pinctrl_usdhc0_cd>;
+	cd-gpios = <&gpio_ptc 10 GPIO_ACTIVE_LOW>;
+	vmmc-supply = <&reg_vsd_3v3>;
+	status = "okay";
+};
+
+&iomuxc1 {
+	pinctrl_lpuart4: lpuart4grp {
+		pinmux = <
+			IMX7ULP_PAD_PTC3__LPUART4_RX
+			IMX7ULP_PAD_PTC2__LPUART4_TX
+		>;
+		bias-pull-up;
+	};
+
+	pinctrl_usdhc0_cmd_data: usdhc0-cmd-data-grp {
+		pinmux = <
+			IMX7ULP_PAD_PTD1__SDHC0_CMD
+			IMX7ULP_PAD_PTD2__SDHC0_CLK
+			IMX7ULP_PAD_PTD7__SDHC0_D3
+			IMX7ULP_PAD_PTD8__SDHC0_D2
+			IMX7ULP_PAD_PTD9__SDHC0_D1
+			IMX7ULP_PAD_PTD10__SDHC0_D0
+		>;
+		drive-strength = <1>;
+		bias-pull-up;
+	};
+
+	pinctrl_usdhc0_clk: usdhc0-clk-grp {
+		pinmux = <
+			IMX7ULP_PAD_PTD2__SDHC0_CLK
+		>;
+		drive-strength = <1>;
+		bias-pull-down;
+	};
+
+	pinctrl_usdhc0_cd: usdhc0-gpio-cd-grp {
+		pinmux = <
+			IMX7ULP_PAD_PTC10__PTC10	/* USDHC0 CD */
+		>;
+		bias-pull-up;
+	};
+
+	pinctrl_usdhc0_rst: usdhc0-gpio-rst-grp {
+		pinmux = <
+			IMX7ULP_PAD_PTD0__PTD0		/* USDHC0 RST */
+		>;
+		bias-pull-up;
+	};
+};
-- 
2.7.4

Re: [PATCH V2 7/8] dts: fsl: add imx7ulp evk support

[Fabio Estevam]

On Tue, Oct 23, 2018 at 8:56 AM A.s. Dong <aisheng.dong@nxp.com> wrote:

> +/ {
> +       model = "NXP i.MX7ULP EVK";
> +       compatible = "fsl,imx7ulp-evk", "fsl,imx7ulp", "Generic DT based system";

This "Generic DT based system" should be removed.

> +       chosen {
> +               stdout-path = &lpuart4;
> +       };
> +
> +       memory@60000000 {

       device_type = "memory";
> +               reg = <0x60000000 0x40000000>;
> +       };

> +&iomuxc1 {
> +       pinctrl_lpuart4: lpuart4grp {
> +               pinmux = <
> +                       IMX7ULP_PAD_PTC3__LPUART4_RX
> +                       IMX7ULP_PAD_PTC2__LPUART4_TX
> +               >;
> +               bias-pull-up;

Please change the mx7ulp pinctrl driver to accept the "old" notation
and change the dts to use:

IMX7ULP_PAD_PTC3__LPUART4_RX 0x3

This way we use the same method for all i.MX devices.

[PATCH V2 7/8] dts: fsl: add imx7ulp evk support

[Fabio Estevam]

On Tue, Oct 23, 2018 at 8:56 AM A.s. Dong <aisheng.dong@nxp.com> wrote:

> +/ {
> +       model = "NXP i.MX7ULP EVK";
> +       compatible = "fsl,imx7ulp-evk", "fsl,imx7ulp", "Generic DT based system";

This "Generic DT based system" should be removed.

> +       chosen {
> +               stdout-path = &lpuart4;
> +       };
> +
> +       memory at 60000000 {

       device_type = "memory";
> +               reg = <0x60000000 0x40000000>;
> +       };

> +&iomuxc1 {
> +       pinctrl_lpuart4: lpuart4grp {
> +               pinmux = <
> +                       IMX7ULP_PAD_PTC3__LPUART4_RX
> +                       IMX7ULP_PAD_PTC2__LPUART4_TX
> +               >;
> +               bias-pull-up;

Please change the mx7ulp pinctrl driver to accept the "old" notation
and change the dts to use:

IMX7ULP_PAD_PTC3__LPUART4_RX 0x3

This way we use the same method for all i.MX devices.

RE: [PATCH V2 7/8] dts: fsl: add imx7ulp evk support

[A.s. Dong]

> -----Original Message-----
> From: Fabio Estevam [mailto:festevam@gmail.com]
> Sent: Tuesday, October 23, 2018 8:29 PM
[...] 
> On Tue, Oct 23, 2018 at 8:56 AM A.s. Dong <aisheng.dong@nxp.com> wrote:
> 
> > +/ {
> > +       model = "NXP i.MX7ULP EVK";
> > +       compatible = "fsl,imx7ulp-evk", "fsl,imx7ulp", "Generic DT
> > +based system";
> 
> This "Generic DT based system" should be removed.
> 

Got it

> > +       chosen {
> > +               stdout-path = &lpuart4;
> > +       };
> > +
> > +       memory@60000000 {
> 
>        device_type = "memory";

Got it

> > +               reg = <0x60000000 0x40000000>;
> > +       };
> 
> > +&iomuxc1 {
> > +       pinctrl_lpuart4: lpuart4grp {
> > +               pinmux = <
> > +                       IMX7ULP_PAD_PTC3__LPUART4_RX
> > +                       IMX7ULP_PAD_PTC2__LPUART4_TX
> > +               >;
> > +               bias-pull-up;
> 
> Please change the mx7ulp pinctrl driver to accept the "old" notation and
> change the dts to use:
> 
> IMX7ULP_PAD_PTC3__LPUART4_RX 0x3
> 
> This way we use the same method for all i.MX devices.

I'm a bit hesitate to do that as the driver already supports it. There's no extra effort
to use it. And we probably could take ULP as a special case to test generic binding
rather then simply drop it and drop driver features. Once we get objection from users
later, we still can simply fallback as there's still only official boards using it.

Last, it's not correct that there's not only one method for all i.MX devices.
MX23/28 are different ones and ULP is more like MX23/28.
And I saw no objections from users for MX23/28.

Regards
Dong Aisheng

[PATCH V2 7/8] dts: fsl: add imx7ulp evk support

[A.s. Dong]

> -----Original Message-----
> From: Fabio Estevam [mailto:festevam at gmail.com]
> Sent: Tuesday, October 23, 2018 8:29 PM
[...] 
> On Tue, Oct 23, 2018 at 8:56 AM A.s. Dong <aisheng.dong@nxp.com> wrote:
> 
> > +/ {
> > +       model = "NXP i.MX7ULP EVK";
> > +       compatible = "fsl,imx7ulp-evk", "fsl,imx7ulp", "Generic DT
> > +based system";
> 
> This "Generic DT based system" should be removed.
> 

Got it

> > +       chosen {
> > +               stdout-path = &lpuart4;
> > +       };
> > +
> > +       memory at 60000000 {
> 
>        device_type = "memory";

Got it

> > +               reg = <0x60000000 0x40000000>;
> > +       };
> 
> > +&iomuxc1 {
> > +       pinctrl_lpuart4: lpuart4grp {
> > +               pinmux = <
> > +                       IMX7ULP_PAD_PTC3__LPUART4_RX
> > +                       IMX7ULP_PAD_PTC2__LPUART4_TX
> > +               >;
> > +               bias-pull-up;
> 
> Please change the mx7ulp pinctrl driver to accept the "old" notation and
> change the dts to use:
> 
> IMX7ULP_PAD_PTC3__LPUART4_RX 0x3
> 
> This way we use the same method for all i.MX devices.

I'm a bit hesitate to do that as the driver already supports it. There's no extra effort
to use it. And we probably could take ULP as a special case to test generic binding
rather then simply drop it and drop driver features. Once we get objection from users
later, we still can simply fallback as there's still only official boards using it.

Last, it's not correct that there's not only one method for all i.MX devices.
MX23/28 are different ones and ULP is more like MX23/28.
And I saw no objections from users for MX23/28.

Regards
Dong Aisheng

Re: [PATCH V2 7/8] dts: fsl: add imx7ulp evk support

[Fabio Estevam]

On Tue, Oct 23, 2018 at 11:42 AM A.s. Dong <aisheng.dong@nxp.com> wrote:

> I'm a bit hesitate to do that as the driver already supports it. There's no extra effort
> to use it. And we probably could take ULP as a special case to test generic binding
> rather then simply drop it and drop driver features. Once we get objection from users
> later, we still can simply fallback as there's still only official boards using it.

We had this same discussion some months ago when we were reviewing
i.MX8 support.

I don't see the value in doing pinctrl differently on i.MX7ULP.

> Last, it's not correct that there's not only one method for all i.MX devices.
> MX23/28 are different ones and ULP is more like MX23/28.
> And I saw no objections from users for MX23/28.

Yes, but these are legacy platforms.

For new ones, we should try to keep consistency, just like we
discussed during i.MX8 review.

[PATCH V2 7/8] dts: fsl: add imx7ulp evk support

[Fabio Estevam]

On Tue, Oct 23, 2018 at 11:42 AM A.s. Dong <aisheng.dong@nxp.com> wrote:

> I'm a bit hesitate to do that as the driver already supports it. There's no extra effort
> to use it. And we probably could take ULP as a special case to test generic binding
> rather then simply drop it and drop driver features. Once we get objection from users
> later, we still can simply fallback as there's still only official boards using it.

We had this same discussion some months ago when we were reviewing
i.MX8 support.

I don't see the value in doing pinctrl differently on i.MX7ULP.

> Last, it's not correct that there's not only one method for all i.MX devices.
> MX23/28 are different ones and ULP is more like MX23/28.
> And I saw no objections from users for MX23/28.

Yes, but these are legacy platforms.

For new ones, we should try to keep consistency, just like we
discussed during i.MX8 review.

RE: [PATCH V2 7/8] dts: fsl: add imx7ulp evk support

[A.s. Dong]

> -----Original Message-----
> From: Fabio Estevam [mailto:festevam@gmail.com]
> Sent: Wednesday, October 24, 2018 12:26 AM
[...]
> On Tue, Oct 23, 2018 at 11:42 AM A.s. Dong <aisheng.dong@nxp.com> wrote:
> 
> > I'm a bit hesitate to do that as the driver already supports it.
> > There's no extra effort to use it. And we probably could take ULP as a
> > special case to test generic binding rather then simply drop it and
> > drop driver features. Once we get objection from users later, we still can
> simply fallback as there's still only official boards using it.
> 
> We had this same discussion some months ago when we were reviewing
> i.MX8 support.
>
> I don't see the value in doing pinctrl differently on i.MX7ULP.
>

I thought the situation is different as ULP actually already supports generic binding
before that discussion.

> > Last, it's not correct that there's not only one method for all i.MX devices.
> > MX23/28 are different ones and ULP is more like MX23/28.
> > And I saw no objections from users for MX23/28.
> 
> Yes, but these are legacy platforms.
> 
> For new ones, we should try to keep consistency, just like we discussed during
> i.MX8 review.

So the question is whether it's necessary to switch generic binding back to the
legacy one for ULP. Personally I'm not strongly against this, but I need some
confirmation from Shawn and Sascha.

Shawn & Sascha, would you make a judgement call?
If you also strongly request that, I will try to make it patch to test Linus W.
Hopefully our agreement could satisfy Linus W.

Regards
Dong Aisheng

[PATCH V2 7/8] dts: fsl: add imx7ulp evk support

[A.s. Dong]

> -----Original Message-----
> From: Fabio Estevam [mailto:festevam at gmail.com]
> Sent: Wednesday, October 24, 2018 12:26 AM
[...]
> On Tue, Oct 23, 2018 at 11:42 AM A.s. Dong <aisheng.dong@nxp.com> wrote:
> 
> > I'm a bit hesitate to do that as the driver already supports it.
> > There's no extra effort to use it. And we probably could take ULP as a
> > special case to test generic binding rather then simply drop it and
> > drop driver features. Once we get objection from users later, we still can
> simply fallback as there's still only official boards using it.
> 
> We had this same discussion some months ago when we were reviewing
> i.MX8 support.
>
> I don't see the value in doing pinctrl differently on i.MX7ULP.
>

I thought the situation is different as ULP actually already supports generic binding
before that discussion.

> > Last, it's not correct that there's not only one method for all i.MX devices.
> > MX23/28 are different ones and ULP is more like MX23/28.
> > And I saw no objections from users for MX23/28.
> 
> Yes, but these are legacy platforms.
> 
> For new ones, we should try to keep consistency, just like we discussed during
> i.MX8 review.

So the question is whether it's necessary to switch generic binding back to the
legacy one for ULP. Personally I'm not strongly against this, but I need some
confirmation from Shawn and Sascha.

Shawn & Sascha, would you make a judgement call?
If you also strongly request that, I will try to make it patch to test Linus W.
Hopefully our agreement could satisfy Linus W.

Regards
Dong Aisheng

RE: [PATCH V2 7/8] dts: fsl: add imx7ulp evk support

[A.s. Dong]

Hi Shawn & Sascha,

> -----Original Message-----
> From: A.s. Dong
> Sent: Wednesday, October 24, 2018 4:14 PM
[...]
> > -----Original Message-----
> > From: Fabio Estevam [mailto:festevam@gmail.com]
> > Sent: Wednesday, October 24, 2018 12:26 AM
> [...]
> > On Tue, Oct 23, 2018 at 11:42 AM A.s. Dong <aisheng.dong@nxp.com>
> wrote:
> >
> > > I'm a bit hesitate to do that as the driver already supports it.
> > > There's no extra effort to use it. And we probably could take ULP as
> > > a special case to test generic binding rather then simply drop it
> > > and drop driver features. Once we get objection from users later, we
> > > still can
> > simply fallback as there's still only official boards using it.
> >
> > We had this same discussion some months ago when we were reviewing
> > i.MX8 support.
> >
> > I don't see the value in doing pinctrl differently on i.MX7ULP.
> >
> 
> I thought the situation is different as ULP actually already supports generic
> binding before that discussion.
> 
> > > Last, it's not correct that there's not only one method for all i.MX devices.
> > > MX23/28 are different ones and ULP is more like MX23/28.
> > > And I saw no objections from users for MX23/28.
> >
> > Yes, but these are legacy platforms.
> >
> > For new ones, we should try to keep consistency, just like we
> > discussed during
> > i.MX8 review.
> 
> So the question is whether it's necessary to switch generic binding back to the
> legacy one for ULP. Personally I'm not strongly against this, but I need some
> confirmation from Shawn and Sascha.
> 
> Shawn & Sascha, would you make a judgement call?
> If you also strongly request that, I will try to make it patch to test Linus W.
> Hopefully our agreement could satisfy Linus W.
> 

Would you please let me know if you're all okay with this?

Regards
Dong Aisheng

> Regards
> Dong Aisheng

[PATCH V2 7/8] dts: fsl: add imx7ulp evk support

[A.s. Dong]

Hi Shawn & Sascha,

> -----Original Message-----
> From: A.s. Dong
> Sent: Wednesday, October 24, 2018 4:14 PM
[...]
> > -----Original Message-----
> > From: Fabio Estevam [mailto:festevam at gmail.com]
> > Sent: Wednesday, October 24, 2018 12:26 AM
> [...]
> > On Tue, Oct 23, 2018 at 11:42 AM A.s. Dong <aisheng.dong@nxp.com>
> wrote:
> >
> > > I'm a bit hesitate to do that as the driver already supports it.
> > > There's no extra effort to use it. And we probably could take ULP as
> > > a special case to test generic binding rather then simply drop it
> > > and drop driver features. Once we get objection from users later, we
> > > still can
> > simply fallback as there's still only official boards using it.
> >
> > We had this same discussion some months ago when we were reviewing
> > i.MX8 support.
> >
> > I don't see the value in doing pinctrl differently on i.MX7ULP.
> >
> 
> I thought the situation is different as ULP actually already supports generic
> binding before that discussion.
> 
> > > Last, it's not correct that there's not only one method for all i.MX devices.
> > > MX23/28 are different ones and ULP is more like MX23/28.
> > > And I saw no objections from users for MX23/28.
> >
> > Yes, but these are legacy platforms.
> >
> > For new ones, we should try to keep consistency, just like we
> > discussed during
> > i.MX8 review.
> 
> So the question is whether it's necessary to switch generic binding back to the
> legacy one for ULP. Personally I'm not strongly against this, but I need some
> confirmation from Shawn and Sascha.
> 
> Shawn & Sascha, would you make a judgement call?
> If you also strongly request that, I will try to make it patch to test Linus W.
> Hopefully our agreement could satisfy Linus W.
> 

Would you please let me know if you're all okay with this?

Regards
Dong Aisheng

> Regards
> Dong Aisheng

Re: [PATCH V2 7/8] dts: fsl: add imx7ulp evk support

[Sascha Hauer]

On Wed, Oct 24, 2018 at 08:14:01AM +0000, A.s. Dong wrote:
> > -----Original Message-----
> > From: Fabio Estevam [mailto:festevam@gmail.com]
> > Sent: Wednesday, October 24, 2018 12:26 AM
> [...]
> > On Tue, Oct 23, 2018 at 11:42 AM A.s. Dong <aisheng.dong@nxp.com> wrote:
> > 
> > > I'm a bit hesitate to do that as the driver already supports it.
> > > There's no extra effort to use it. And we probably could take ULP as a
> > > special case to test generic binding rather then simply drop it and
> > > drop driver features. Once we get objection from users later, we still can
> > simply fallback as there's still only official boards using it.
> > 
> > We had this same discussion some months ago when we were reviewing
> > i.MX8 support.
> >
> > I don't see the value in doing pinctrl differently on i.MX7ULP.
> >
> 
> I thought the situation is different as ULP actually already supports generic binding
> before that discussion.
> 
> > > Last, it's not correct that there's not only one method for all i.MX devices.
> > > MX23/28 are different ones and ULP is more like MX23/28.
> > > And I saw no objections from users for MX23/28.
> > 
> > Yes, but these are legacy platforms.
> > 
> > For new ones, we should try to keep consistency, just like we discussed during
> > i.MX8 review.
> 
> So the question is whether it's necessary to switch generic binding back to the
> legacy one for ULP. Personally I'm not strongly against this, but I need some
> confirmation from Shawn and Sascha.
> 
> Shawn & Sascha, would you make a judgement call?
> If you also strongly request that, I will try to make it patch to test Linus W.
> Hopefully our agreement could satisfy Linus W.

For consistency reasons I vote for using the legacy binding for i.MX7ulp
aswell.

Sascha

-- 
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[PATCH V2 7/8] dts: fsl: add imx7ulp evk support

[Sascha Hauer]

On Wed, Oct 24, 2018 at 08:14:01AM +0000, A.s. Dong wrote:
> > -----Original Message-----
> > From: Fabio Estevam [mailto:festevam at gmail.com]
> > Sent: Wednesday, October 24, 2018 12:26 AM
> [...]
> > On Tue, Oct 23, 2018 at 11:42 AM A.s. Dong <aisheng.dong@nxp.com> wrote:
> > 
> > > I'm a bit hesitate to do that as the driver already supports it.
> > > There's no extra effort to use it. And we probably could take ULP as a
> > > special case to test generic binding rather then simply drop it and
> > > drop driver features. Once we get objection from users later, we still can
> > simply fallback as there's still only official boards using it.
> > 
> > We had this same discussion some months ago when we were reviewing
> > i.MX8 support.
> >
> > I don't see the value in doing pinctrl differently on i.MX7ULP.
> >
> 
> I thought the situation is different as ULP actually already supports generic binding
> before that discussion.
> 
> > > Last, it's not correct that there's not only one method for all i.MX devices.
> > > MX23/28 are different ones and ULP is more like MX23/28.
> > > And I saw no objections from users for MX23/28.
> > 
> > Yes, but these are legacy platforms.
> > 
> > For new ones, we should try to keep consistency, just like we discussed during
> > i.MX8 review.
> 
> So the question is whether it's necessary to switch generic binding back to the
> legacy one for ULP. Personally I'm not strongly against this, but I need some
> confirmation from Shawn and Sascha.
> 
> Shawn & Sascha, would you make a judgement call?
> If you also strongly request that, I will try to make it patch to test Linus W.
> Hopefully our agreement could satisfy Linus W.

For consistency reasons I vote for using the legacy binding for i.MX7ulp
aswell.

Sascha

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
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RE: [PATCH V2 7/8] dts: fsl: add imx7ulp evk support

[A.s. Dong]

> -----Original Message-----
> From: Sascha Hauer [mailto:s.hauer@pengutronix.de]
> Sent: Friday, October 26, 2018 6:57 PM
[...]
> 
> On Wed, Oct 24, 2018 at 08:14:01AM +0000, A.s. Dong wrote:
> > > -----Original Message-----
> > > From: Fabio Estevam [mailto:festevam@gmail.com]
> > > Sent: Wednesday, October 24, 2018 12:26 AM
> > [...]
> > > On Tue, Oct 23, 2018 at 11:42 AM A.s. Dong <aisheng.dong@nxp.com>
> wrote:
> > >
> > > > I'm a bit hesitate to do that as the driver already supports it.
> > > > There's no extra effort to use it. And we probably could take ULP
> > > > as a special case to test generic binding rather then simply drop
> > > > it and drop driver features. Once we get objection from users
> > > > later, we still can
> > > simply fallback as there's still only official boards using it.
> > >
> > > We had this same discussion some months ago when we were reviewing
> > > i.MX8 support.
> > >
> > > I don't see the value in doing pinctrl differently on i.MX7ULP.
> > >
> >
> > I thought the situation is different as ULP actually already supports
> > generic binding before that discussion.
> >
> > > > Last, it's not correct that there's not only one method for all i.MX devices.
> > > > MX23/28 are different ones and ULP is more like MX23/28.
> > > > And I saw no objections from users for MX23/28.
> > >
> > > Yes, but these are legacy platforms.
> > >
> > > For new ones, we should try to keep consistency, just like we
> > > discussed during
> > > i.MX8 review.
> >
> > So the question is whether it's necessary to switch generic binding
> > back to the legacy one for ULP. Personally I'm not strongly against
> > this, but I need some confirmation from Shawn and Sascha.
> >
> > Shawn & Sascha, would you make a judgement call?
> > If you also strongly request that, I will try to make it patch to test Linus W.
> > Hopefully our agreement could satisfy Linus W.
> 
> For consistency reasons I vote for using the legacy binding for i.MX7ulp aswell.
> 

Thanks for the feedback.
Will try to cook a patch to send to Linus W.

Regards
Dong Aisheng

> Sascha
> 
> --
> Pengutronix e.K.                           |
> |
> Industrial Linux Solutions                 |
> https://emea01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fwww.
> pengutronix.de%2F&amp;data=02%7C01%7Caisheng.dong%40nxp.com%7C74
> a0d2aca1cf432528a608d63b31c614%7C686ea1d3bc2b4c6fa92cd99c5c3016
> 35%7C0%7C0%7C636761482309424341&amp;sdata=Mi5aWJmBcYI3xZLsEdj
> O%2BQ7JUKZS1EzXuW%2Bd2WBJtek%3D&amp;reserved=0  |
> Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0
> |
> Amtsgericht Hildesheim, HRA 2686           | Fax:
> +49-5121-206917-5555 |

[PATCH V2 7/8] dts: fsl: add imx7ulp evk support

[A.s. Dong]

> -----Original Message-----
> From: Sascha Hauer [mailto:s.hauer at pengutronix.de]
> Sent: Friday, October 26, 2018 6:57 PM
[...]
> 
> On Wed, Oct 24, 2018 at 08:14:01AM +0000, A.s. Dong wrote:
> > > -----Original Message-----
> > > From: Fabio Estevam [mailto:festevam at gmail.com]
> > > Sent: Wednesday, October 24, 2018 12:26 AM
> > [...]
> > > On Tue, Oct 23, 2018 at 11:42 AM A.s. Dong <aisheng.dong@nxp.com>
> wrote:
> > >
> > > > I'm a bit hesitate to do that as the driver already supports it.
> > > > There's no extra effort to use it. And we probably could take ULP
> > > > as a special case to test generic binding rather then simply drop
> > > > it and drop driver features. Once we get objection from users
> > > > later, we still can
> > > simply fallback as there's still only official boards using it.
> > >
> > > We had this same discussion some months ago when we were reviewing
> > > i.MX8 support.
> > >
> > > I don't see the value in doing pinctrl differently on i.MX7ULP.
> > >
> >
> > I thought the situation is different as ULP actually already supports
> > generic binding before that discussion.
> >
> > > > Last, it's not correct that there's not only one method for all i.MX devices.
> > > > MX23/28 are different ones and ULP is more like MX23/28.
> > > > And I saw no objections from users for MX23/28.
> > >
> > > Yes, but these are legacy platforms.
> > >
> > > For new ones, we should try to keep consistency, just like we
> > > discussed during
> > > i.MX8 review.
> >
> > So the question is whether it's necessary to switch generic binding
> > back to the legacy one for ULP. Personally I'm not strongly against
> > this, but I need some confirmation from Shawn and Sascha.
> >
> > Shawn & Sascha, would you make a judgement call?
> > If you also strongly request that, I will try to make it patch to test Linus W.
> > Hopefully our agreement could satisfy Linus W.
> 
> For consistency reasons I vote for using the legacy binding for i.MX7ulp aswell.
> 

Thanks for the feedback.
Will try to cook a patch to send to Linus W.

Regards
Dong Aisheng

> Sascha
> 
> --
> Pengutronix e.K.                           |
> |
> Industrial Linux Solutions                 |
> https://emea01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fwww.
> pengutronix.de%2F&amp;data=02%7C01%7Caisheng.dong%40nxp.com%7C74
> a0d2aca1cf432528a608d63b31c614%7C686ea1d3bc2b4c6fa92cd99c5c3016
> 35%7C0%7C0%7C636761482309424341&amp;sdata=Mi5aWJmBcYI3xZLsEdj
> O%2BQ7JUKZS1EzXuW%2Bd2WBJtek%3D&amp;reserved=0  |
> Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0
> |
> Amtsgericht Hildesheim, HRA 2686           | Fax:
> +49-5121-206917-5555 |

[PATCH V2 8/8] ARM: imx_v6_v7_defconfig: add imx7ulp support

[A.s. Dong]

Select CONFIG_SOC_IMX7ULP by default.
Patch generated via make ARCH=arm savedefconfig

Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Sascha Hauer <kernel@pengutronix.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
---
v1->v2:
 * rebase to new version
---
 arch/arm/configs/imx_v6_v7_defconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/configs/imx_v6_v7_defconfig b/arch/arm/configs/imx_v6_v7_defconfig
index 1ad5736..27ee422 100644
--- a/arch/arm/configs/imx_v6_v7_defconfig
+++ b/arch/arm/configs/imx_v6_v7_defconfig
@@ -38,6 +38,7 @@ CONFIG_SOC_IMX6SLL=y
 CONFIG_SOC_IMX6SX=y
 CONFIG_SOC_IMX6UL=y
 CONFIG_SOC_IMX7D=y
+CONFIG_SOC_IMX7ULP=y
 CONFIG_SOC_VF610=y
 CONFIG_PCI=y
 CONFIG_PCI_MSI=y
-- 
2.7.4