[U-Boot] [i.MX8MM+CCF 00/41] i.MX8MM + CCF

[U-Boot] [i.MX8MM+CCF 00/41] i.MX8MM + CCF

[Peng Fan]

This patch set is based Lukasz V3 CCF patchset,
[PATCH v3 00/11] clk: Port Linux common clock framework [CCF] to U-boot (tag: 5.0-rc3)
https://github.com/lmajewski/u-boot-dfu/commits/CCF-v3

Added a few fixes to Lukasz's v3 patchset.
Introduced clk-gate/composite
Added set rate support
Per my understanding, U-Boot CCF will not support mux reparent, and
support rate prograte setting to parent automatically. So new clk
feature added follow this rule.

There are many warnings when importing linux ccf code, I did not
modify them all.

The rest patches are for i.MX8MM, part of legacy clk code are still
kept, because we are hard to enable CCF at very early stage, we set
malloc space to DRAM when dram initialized in spl stage, so we have
limited SRAM for uclass dm and dm clk, so keep the DRAM PLL related
setting with legacy clk code which use small ram.

The u-boot-spl.bin now is about 100KB without ddr firmware,usb stack and hab,
so really large......
I am thinking what we could do to shrink the size, welcome any suggestions.

Not expect this patchset could be merged, because of the CCF/clock code
change, but since the clock part blocks i.MX8MM upstream, just would like
to speed up the development with community and move on.

Peng Fan (40):
  clk: correct get clk_x pointer
  clk: fixed-factor: fix get clk_fixed_factor
  clk: introduce clk_dev_binded
  clk: use clk_dev_binded
  clk-provider: sync more clk flags from Linux Kernel
  cmd: clk: print err value when clk_get_rate failed
  clk: mux: add set parent support
  clk: export mux/divider ops
  clk: add clk-gate support
  divider set rate supporrt
  clk: fixed_rate: export clk_fixed_rate
  clk: fixed_rate: add pre reloc flag
  clk: imx: import clk heplers
  clk: imx: gate2 add set rate
  linux: compat: guard PAGE_SIZE
  drivers: core: use strcmp when find device by name
  ddr: imx8m: fix ddr firmware location when enable SPL OF
  imx: add IMX8MQ kconfig entry
  imx: add IMX8MM kconfig entry
  imx: imx8mm: add clock bindings header
  imx: add i.MX8MM cpu type
  imx: spl: add spl_board_boot_device for i.MX8MM
  imx8m: update imx-regs for i.MX8MM
  imx: add get_cpu_rev support for i.MX8MM
  imx8m: rename clock to clock_imx8mq
  imx8m: restructure clock.h
  imx8m: add clk support for i.MX8MM
  imx8m: soc: probe clk before relocation
  imx8m: add pin header for i.MX8MM
  imx: add i.MX8MM PE property
  imx8m: Fix MMU table issue for OPTEE memory
  imx8m: set BYPASS ID SWAP to avoid AXI bus errors
  imx8m: soc: enable SCTR clock before timer init
  serial: Kconfig: make MXC_UART usable for MX7 and IMX8M
  clk: imx: add Kconfig entry for i.MX8MM
  clk: imx: add pll14xx driver
  clk: add composite clk support
  clk: imx: add i.MX8MM composite clk support
  clk: imx: add i.MX8MM clk driver
  imx: add i.MX8MM EVK board support

Ye Li (1):
  imx8m: Configure trustzone region 0 for non-secure access

 arch/arm/dts/Makefile                              |    3 +-
 arch/arm/dts/imx8mm-evk-u-boot.dtsi                |   92 +
 arch/arm/dts/imx8mm-evk.dts                        |  235 +++
 arch/arm/dts/imx8mm-pinfunc.h                      |  629 +++++++
 arch/arm/dts/imx8mm.dtsi                           |  733 ++++++++
 arch/arm/include/asm/arch-imx/cpu.h                |    6 +
 arch/arm/include/asm/arch-imx8m/clock.h            |  493 +----
 arch/arm/include/asm/arch-imx8m/clock_imx8mm.h     |  387 ++++
 arch/arm/include/asm/arch-imx8m/clock_imx8mq.h     |  424 +++++
 arch/arm/include/asm/arch-imx8m/imx-regs.h         |   75 +-
 arch/arm/include/asm/arch-imx8m/imx8mm_pins.h      |  691 +++++++
 arch/arm/include/asm/mach-imx/iomux-v3.h           |    4 +
 arch/arm/include/asm/mach-imx/sys_proto.h          |    8 +
 arch/arm/mach-imx/cpu.c                            |   12 +
 arch/arm/mach-imx/imx8m/Kconfig                    |   17 +-
 arch/arm/mach-imx/imx8m/Makefile                   |    4 +-
 arch/arm/mach-imx/imx8m/clock_imx8mm.c             |  292 +++
 .../arm/mach-imx/imx8m/{clock.c => clock_imx8mq.c} |    5 +-
 arch/arm/mach-imx/imx8m/clock_slice.c              |  461 +++++
 arch/arm/mach-imx/imx8m/soc.c                      |  112 +-
 arch/arm/mach-imx/spl.c                            |    8 +
 board/freescale/imx8mm_evk/Kconfig                 |   12 +
 board/freescale/imx8mm_evk/MAINTAINERS             |    6 +
 board/freescale/imx8mm_evk/Makefile                |   12 +
 board/freescale/imx8mm_evk/imx8mm_evk.c            |   90 +
 board/freescale/imx8mm_evk/lpddr4_timing.c         | 1980 ++++++++++++++++++++
 board/freescale/imx8mm_evk/spl.c                   |  216 +++
 cmd/clk.c                                          |    2 +
 configs/imx8mm_evk_defconfig                       |   52 +
 drivers/clk/Kconfig                                |   14 +
 drivers/clk/Makefile                               |    3 +-
 drivers/clk/clk-composite.c                        |  165 ++
 drivers/clk/clk-divider.c                          |   92 +-
 drivers/clk/clk-fixed-factor.c                     |    2 +-
 drivers/clk/clk-gate.c                             |  151 ++
 drivers/clk/clk-mux.c                              |   76 +-
 drivers/clk/clk.c                                  |    8 +
 drivers/clk/clk_fixed_rate.c                       |    9 +-
 drivers/clk/imx/Kconfig                            |    9 +
 drivers/clk/imx/Makefile                           |    1 +
 drivers/clk/imx/clk-composite-8m.c                 |  170 ++
 drivers/clk/imx/clk-gate2.c                        |   15 +-
 drivers/clk/imx/clk-imx8mm.c                       |  415 ++++
 drivers/clk/imx/clk-pfd.c                          |    2 +-
 drivers/clk/imx/clk-pll14xx.c                      |  377 ++++
 drivers/clk/imx/clk-pllv3.c                        |    2 +-
 drivers/clk/imx/clk.h                              |  106 ++
 drivers/core/uclass.c                              |    2 +-
 drivers/ddr/imx/imx8m/helper.c                     |   12 +-
 drivers/serial/Kconfig                             |    2 +-
 include/clk.h                                      |    9 +
 include/configs/imx8mm_evk.h                       |  199 ++
 include/dt-bindings/clock/imx8mm-clock.h           |  244 +++
 include/linux/clk-provider.h                       |   74 +
 include/linux/compat.h                             |    2 +
 55 files changed, 8728 insertions(+), 494 deletions(-)
 create mode 100644 arch/arm/dts/imx8mm-evk-u-boot.dtsi
 create mode 100644 arch/arm/dts/imx8mm-evk.dts
 create mode 100644 arch/arm/dts/imx8mm-pinfunc.h
 create mode 100644 arch/arm/dts/imx8mm.dtsi
 create mode 100644 arch/arm/include/asm/arch-imx8m/clock_imx8mm.h
 create mode 100644 arch/arm/include/asm/arch-imx8m/clock_imx8mq.h
 create mode 100644 arch/arm/include/asm/arch-imx8m/imx8mm_pins.h
 create mode 100644 arch/arm/mach-imx/imx8m/clock_imx8mm.c
 rename arch/arm/mach-imx/imx8m/{clock.c => clock_imx8mq.c} (99%)
 create mode 100644 board/freescale/imx8mm_evk/Kconfig
 create mode 100644 board/freescale/imx8mm_evk/MAINTAINERS
 create mode 100644 board/freescale/imx8mm_evk/Makefile
 create mode 100644 board/freescale/imx8mm_evk/imx8mm_evk.c
 create mode 100644 board/freescale/imx8mm_evk/lpddr4_timing.c
 create mode 100644 board/freescale/imx8mm_evk/spl.c
 create mode 100644 configs/imx8mm_evk_defconfig
 create mode 100644 drivers/clk/clk-composite.c
 create mode 100644 drivers/clk/clk-gate.c
 create mode 100644 drivers/clk/imx/clk-composite-8m.c
 create mode 100644 drivers/clk/imx/clk-imx8mm.c
 create mode 100644 drivers/clk/imx/clk-pll14xx.c
 create mode 100644 include/configs/imx8mm_evk.h
 create mode 100644 include/dt-bindings/clock/imx8mm-clock.h

-- 
2.16.4

[U-Boot] [i.MX8MM+CCF 01/41] clk: correct get clk_x pointer

[Peng Fan]

Directly use driver data is wrong, need to the helper to get
the correct clk_divider and etc

Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 drivers/clk/clk-divider.c   | 2 +-
 drivers/clk/imx/clk-gate2.c | 4 ++--
 drivers/clk/imx/clk-pfd.c   | 2 +-
 drivers/clk/imx/clk-pllv3.c | 2 +-
 4 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c
index 3841d8bfbb..1d2c1b1ec4 100644
--- a/drivers/clk/clk-divider.c
+++ b/drivers/clk/clk-divider.c
@@ -70,7 +70,7 @@ unsigned long divider_recalc_rate(struct clk *hw, unsigned long parent_rate,
 static ulong clk_divider_recalc_rate(struct clk *clk)
 {
 	struct clk_divider *divider =
-		(struct clk_divider *)dev_get_driver_data(clk->dev);
+		to_clk_divider((struct clk *)dev_get_driver_data(clk->dev));
 	unsigned long parent_rate = clk_get_parent_rate(clk);
 	unsigned int val;
 
diff --git a/drivers/clk/imx/clk-gate2.c b/drivers/clk/imx/clk-gate2.c
index 1e53e4f9db..83589b9206 100644
--- a/drivers/clk/imx/clk-gate2.c
+++ b/drivers/clk/imx/clk-gate2.c
@@ -38,7 +38,7 @@ struct clk_gate2 {
 static int clk_gate2_enable(struct clk *clk)
 {
 	struct clk_gate2 *gate =
-		(struct clk_gate2 *)dev_get_driver_data(clk->dev);
+		to_clk_gate2((struct clk *)dev_get_driver_data(clk->dev));
 	u32 reg;
 
 	reg = readl(gate->reg);
@@ -52,7 +52,7 @@ static int clk_gate2_enable(struct clk *clk)
 static int clk_gate2_disable(struct clk *clk)
 {
 	struct clk_gate2 *gate =
-		(struct clk_gate2 *)dev_get_driver_data(clk->dev);
+		to_clk_gate2((struct clk *)dev_get_driver_data(clk->dev));
 	u32 reg;
 
 	reg = readl(gate->reg);
diff --git a/drivers/clk/imx/clk-pfd.c b/drivers/clk/imx/clk-pfd.c
index 2293d481d4..51521ccee6 100644
--- a/drivers/clk/imx/clk-pfd.c
+++ b/drivers/clk/imx/clk-pfd.c
@@ -41,7 +41,7 @@ struct clk_pfd {
 static unsigned long clk_pfd_recalc_rate(struct clk *clk)
 {
 	struct clk_pfd *pfd =
-		(struct clk_pfd *)dev_get_driver_data(clk->dev);
+		to_clk_pfd((struct clk *)dev_get_driver_data(clk->dev));
 	unsigned long parent_rate = clk_get_parent_rate(clk);
 	u64 tmp = parent_rate;
 	u8 frac = (readl(pfd->reg) >> (pfd->idx * 8)) & 0x3f;
diff --git a/drivers/clk/imx/clk-pllv3.c b/drivers/clk/imx/clk-pllv3.c
index 3fe9b7c03d..28c0439878 100644
--- a/drivers/clk/imx/clk-pllv3.c
+++ b/drivers/clk/imx/clk-pllv3.c
@@ -27,7 +27,7 @@ struct clk_pllv3 {
 static ulong clk_pllv3_get_rate(struct clk *clk)
 {
 	struct clk_pllv3 *pll =
-		(struct clk_pllv3 *)dev_get_driver_data(clk->dev);
+		to_clk_pllv3((struct clk *)dev_get_driver_data(clk->dev));
 	unsigned long parent_rate = clk_get_parent_rate(clk);
 
 	u32 div = (readl(pll->base) >> pll->div_shift) & pll->div_mask;
-- 
2.16.4

[U-Boot] [i.MX8MM+CCF 02/41] clk: fixed-factor: fix get clk_fixed_factor

[Peng Fan]

driver data is not clk, not clk_fixed_factor, fix it.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 drivers/clk/clk-fixed-factor.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/clk-fixed-factor.c b/drivers/clk/clk-fixed-factor.c
index acbc0909b4..c535aadc48 100644
--- a/drivers/clk/clk-fixed-factor.c
+++ b/drivers/clk/clk-fixed-factor.c
@@ -19,7 +19,7 @@
 static ulong clk_factor_recalc_rate(struct clk *clk)
 {
 	struct clk_fixed_factor *fix =
-		(struct clk_fixed_factor *)dev_get_driver_data(clk->dev);
+		to_clk_fixed_factor((struct clk *)dev_get_driver_data(clk->dev));
 	unsigned long parent_rate = clk_get_parent_rate(clk);
 	unsigned long long int rate;
 
-- 
2.16.4

[U-Boot] [i.MX8MM+CCF 03/41] clk: introduce clk_dev_binded

[Peng Fan]

When support Clock Common Framework, U-Boot use dev for
clk tree information, there is no clk->parent. When
support composite clk, it contains mux/gate/divider,
but the mux/gate/divider is not binded with device.
So we could not use dev_get_driver_data to get the correct
clk_mux/gate/divider. So add clk_dev_binded to let
choose the correct method.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 drivers/clk/clk.c | 8 ++++++++
 include/clk.h     | 9 +++++++++
 2 files changed, 17 insertions(+)

diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
index 0a0fffb50b..025bb99ecc 100644
--- a/drivers/clk/clk.c
+++ b/drivers/clk/clk.c
@@ -54,3 +54,11 @@ const char *clk_hw_get_name(const struct clk *hw)
 {
 	return hw->dev->name;
 }
+
+bool clk_dev_binded(struct clk *clk)
+{
+	if (clk->dev && (clk->dev->flags & DM_FLAG_BOUND))
+		return true;
+
+	return false;
+}
diff --git a/include/clk.h b/include/clk.h
index a4ecca9fbc..8199119d01 100644
--- a/include/clk.h
+++ b/include/clk.h
@@ -337,4 +337,13 @@ static inline bool clk_valid(struct clk *clk)
  * @return zero on success, or -ENOENT on error
  */
 int clk_get_by_id(ulong id, struct clk **clkp);
+
+/**
+ * clk_dev_binded() - Check whether the clk has a device binded
+ *
+ * @clk		A pointer to the clk
+ *
+ * @return true on binded, or false on no
+ */
+bool clk_dev_binded(struct clk *clk);
 #endif
-- 
2.16.4

[U-Boot] [i.MX8MM+CCF 04/41] clk: use clk_dev_binded

[Peng Fan]

Preparing to support composite clk.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 drivers/clk/clk-divider.c | 4 ++--
 drivers/clk/clk-mux.c     | 6 ++++--
 2 files changed, 6 insertions(+), 4 deletions(-)

diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c
index 1d2c1b1ec4..2f09e0bb58 100644
--- a/drivers/clk/clk-divider.c
+++ b/drivers/clk/clk-divider.c
@@ -69,8 +69,8 @@ unsigned long divider_recalc_rate(struct clk *hw, unsigned long parent_rate,
 
 static ulong clk_divider_recalc_rate(struct clk *clk)
 {
-	struct clk_divider *divider =
-		to_clk_divider((struct clk *)dev_get_driver_data(clk->dev));
+	struct clk_divider *divider = to_clk_divider(clk_dev_binded(clk) ?
+			(struct clk *)dev_get_driver_data(clk->dev) : clk);
 	unsigned long parent_rate = clk_get_parent_rate(clk);
 	unsigned int val;
 
diff --git a/drivers/clk/clk-mux.c b/drivers/clk/clk-mux.c
index 2c85f2052c..55fc97367a 100644
--- a/drivers/clk/clk-mux.c
+++ b/drivers/clk/clk-mux.c
@@ -35,7 +35,8 @@
 int clk_mux_val_to_index(struct clk *clk, u32 *table, unsigned int flags,
 			 unsigned int val)
 {
-	struct clk_mux *mux = to_clk_mux(clk);
+	struct clk_mux *mux = to_clk_mux(clk_dev_binded(clk) ?
+			(struct clk *)dev_get_driver_data(clk->dev) : clk);
 	int num_parents = mux->num_parents;
 
 	if (table) {
@@ -61,7 +62,8 @@ int clk_mux_val_to_index(struct clk *clk, u32 *table, unsigned int flags,
 
 static u8 clk_mux_get_parent(struct clk *clk)
 {
-	struct clk_mux *mux = to_clk_mux(clk);
+	struct clk_mux *mux = to_clk_mux(clk_dev_binded(clk) ?
+			(struct clk *)dev_get_driver_data(clk->dev) : clk);
 	u32 val;
 
 	val = readl(mux->reg) >> mux->shift;
-- 
2.16.4

[U-Boot] [i.MX8MM+CCF 05/41] clk-provider: sync more clk flags from Linux Kernel

[Peng Fan]

Sync more clk flags that might be used in U-Boot CCF.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 include/linux/clk-provider.h | 21 +++++++++++++++++++++
 1 file changed, 21 insertions(+)

diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index eac045c5f8..3458746a60 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -9,8 +9,29 @@
 #ifndef __LINUX_CLK_PROVIDER_H
 #define __LINUX_CLK_PROVIDER_H
 
+/*
+ * flags used across common struct clk.  these flags should only affect the
+ * top-level framework.  custom flags for dealing with hardware specifics
+ * belong in struct clk_foo
+ *
+ * Please update clk_flags[] in drivers/clk/clk.c when making changes here!
+ */
+#define CLK_SET_RATE_GATE	BIT(0) /* must be gated across rate change */
+#define CLK_SET_PARENT_GATE	BIT(1) /* must be gated across re-parent */
 #define CLK_SET_RATE_PARENT	BIT(2) /* propagate rate change up one level */
+#define CLK_IGNORE_UNUSED	BIT(3) /* do not gate even if unused */
+				/* unused */
+#define CLK_IS_BASIC		BIT(5) /* Basic clk, can't do a to_clk_foo() */
+#define CLK_GET_RATE_NOCACHE	BIT(6) /* do not use the cached clk rate */
 #define CLK_SET_RATE_NO_REPARENT BIT(7) /* don't re-parent on rate change */
+#define CLK_GET_ACCURACY_NOCACHE BIT(8) /* do not use the cached clk accuracy */
+#define CLK_RECALC_NEW_RATES	BIT(9) /* recalc rates after notifications */
+#define CLK_SET_RATE_UNGATE	BIT(10) /* clock needs to run to set rate */
+#define CLK_IS_CRITICAL		BIT(11) /* do not gate, ever */
+/* parents need enable during gate/ungate, set rate and re-parent */
+#define CLK_OPS_PARENT_ENABLE	BIT(12)
+/* duty cycle call may be forwarded to the parent clock */
+#define CLK_DUTY_CYCLE_PARENT	BIT(13)
 
 #define CLK_MUX_INDEX_ONE		BIT(0)
 #define CLK_MUX_INDEX_BIT		BIT(1)
-- 
2.16.4

[U-Boot] [i.MX8MM+CCF 06/41] cmd: clk: print err value when clk_get_rate failed

[Peng Fan]

Print err value when clk_get_rate failed

Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 cmd/clk.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/cmd/clk.c b/cmd/clk.c
index 2ea82176aa..73d963184d 100644
--- a/cmd/clk.c
+++ b/cmd/clk.c
@@ -41,6 +41,8 @@ int __weak soc_clk_dump(void)
 		rate = clk_get_rate(&clk);
 		if (!IS_ERR_VALUE(rate))
 			printf("%-30.30s : %lu Hz\n", dev->name, rate);
+		else
+			printf("%-30.30s : err=%ld\n", dev->name, rate);
 
 		clk_free(&clk);
 	}
-- 
2.16.4

[U-Boot] [i.MX8MM+CCF 07/41] clk: mux: add set parent support

[Peng Fan]

Add set parent support for clk mux

Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 drivers/clk/clk-mux.c        | 70 ++++++++++++++++++++++++++++++++++++++++++--
 include/linux/clk-provider.h |  2 ++
 2 files changed, 70 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/clk-mux.c b/drivers/clk/clk-mux.c
index 55fc97367a..1a937bf923 100644
--- a/drivers/clk/clk-mux.c
+++ b/drivers/clk/clk-mux.c
@@ -60,7 +60,24 @@ int clk_mux_val_to_index(struct clk *clk, u32 *table, unsigned int flags,
 	return val;
 }
 
-static u8 clk_mux_get_parent(struct clk *clk)
+unsigned int clk_mux_index_to_val(u32 *table, unsigned int flags, u8 index)
+{
+	unsigned int val = index;
+
+	if (table) {
+		val = table[index];
+	} else {
+		if (flags & CLK_MUX_INDEX_BIT)
+			val = 1 << index;
+
+		if (flags & CLK_MUX_INDEX_ONE)
+			val++;
+	}
+
+	return val;
+}
+
+u8 clk_mux_get_parent(struct clk *clk)
 {
 	struct clk_mux *mux = to_clk_mux(clk_dev_binded(clk) ?
 			(struct clk *)dev_get_driver_data(clk->dev) : clk);
@@ -72,8 +89,57 @@ static u8 clk_mux_get_parent(struct clk *clk)
 	return clk_mux_val_to_index(clk, mux->table, mux->flags, val);
 }
 
+static int clk_fetch_parent_index(struct clk *clk,
+				  struct clk *parent)
+{
+	struct clk_mux *mux = to_clk_mux(clk_dev_binded(clk) ?
+			(struct clk *)dev_get_driver_data(clk->dev) : clk);
+
+	int i;
+
+	if (!parent)
+		return -EINVAL;
+
+	for (i = 0; i < mux->num_parents; i++) {
+		if (!strcmp(parent->dev->name, mux->parent_names[i]))
+			return i;
+	}
+
+	return -EINVAL;
+}
+
+static int clk_mux_set_parent(struct clk *clk, struct clk *parent)
+{
+	struct clk_mux *mux = to_clk_mux(clk_dev_binded(clk) ?
+			(struct clk *)dev_get_driver_data(clk->dev) : clk);
+	int index;
+	u32 val;
+	u32 reg;
+
+	index = clk_fetch_parent_index(clk, parent);
+	if (index < 0) {
+		printf("Could not fetch index\n");
+		return index;
+	}
+
+	val = clk_mux_index_to_val(mux->table, mux->flags, index);
+
+	if (mux->flags & CLK_MUX_HIWORD_MASK) {
+		reg = mux->mask << (mux->shift + 16);
+	} else {
+		reg = readl(mux->reg);
+		reg &= ~(mux->mask << mux->shift);
+	}
+	val = val << mux->shift;
+	reg |= val;
+	writel(reg, mux->reg);
+
+	return 0;
+}
+
 const struct clk_ops clk_mux_ops = {
-		.get_rate = clk_generic_get_rate,
+	.get_rate = clk_generic_get_rate,
+	.set_parent = clk_mux_set_parent,
 };
 
 struct clk *clk_hw_register_mux_table(struct device *dev, const char *name,
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index 3458746a60..216095d28c 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -56,6 +56,8 @@ struct clk_mux {
 };
 
 #define to_clk_mux(_clk) container_of(_clk, struct clk_mux, clk)
+extern const struct clk_ops clk_mux_ops;
+u8 clk_mux_get_parent(struct clk *clk);
 
 struct clk_div_table {
 	unsigned int	val;
-- 
2.16.4

[U-Boot] [i.MX8MM+CCF 08/41] clk: export mux/divider ops

[Peng Fan]

Export mux/divider ops for composite usage

Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 include/linux/clk-provider.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index 216095d28c..a60cf6e833 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -83,6 +83,7 @@ struct clk_divider {
 #define CLK_DIVIDER_ROUND_CLOSEST	BIT(4)
 #define CLK_DIVIDER_READ_ONLY		BIT(5)
 #define CLK_DIVIDER_MAX_AT_ZERO		BIT(6)
+extern const struct clk_ops clk_divider_ops;
 
 struct clk_fixed_factor {
 	struct clk	clk;
-- 
2.16.4

[U-Boot] [i.MX8MM+CCF 09/41] clk: add clk-gate support

[Peng Fan]

Import clk-gate support from Linux Kernel 5.1-rc5

Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 drivers/clk/Makefile         |   2 +-
 drivers/clk/clk-gate.c       | 151 +++++++++++++++++++++++++++++++++++++++++++
 include/linux/clk-provider.h |  18 ++++++
 3 files changed, 170 insertions(+), 1 deletion(-)
 create mode 100644 drivers/clk/clk-gate.c

diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 9fcc75e0ea..0bc8f7e5ce 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -7,7 +7,7 @@
 obj-$(CONFIG_$(SPL_TPL_)CLK) += clk-uclass.o
 obj-$(CONFIG_$(SPL_TPL_)CLK) += clk_fixed_rate.o
 obj-$(CONFIG_$(SPL_TPL_)CLK) += clk_fixed_factor.o
-obj-$(CONFIG_$(SPL_TPL_)CLK_CCF) += clk.o clk-divider.o clk-mux.o
+obj-$(CONFIG_$(SPL_TPL_)CLK_CCF) += clk.o clk-divider.o clk-mux.o clk-gate.o
 obj-$(CONFIG_$(SPL_TPL_)CLK_CCF) += clk-fixed-factor.o
 
 obj-y += imx/
diff --git a/drivers/clk/clk-gate.c b/drivers/clk/clk-gate.c
new file mode 100644
index 0000000000..bb59d0e04e
--- /dev/null
+++ b/drivers/clk/clk-gate.c
@@ -0,0 +1,151 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2010-2011 Canonical Ltd <jeremy.kerr@canonical.com>
+ * Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette@linaro.org>
+ * Copyright 2019 NXP
+ *
+ * Gated clock implementation
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <malloc.h>
+#include <clk-uclass.h>
+#include <dm/device.h>
+#include <linux/clk-provider.h>
+#include <clk.h>
+#include "clk.h"
+
+#define UBOOT_DM_CLK_GATE "clk_gate"
+
+/**
+ * DOC: basic gatable clock which can gate and ungate it's output
+ *
+ * Traits of this clock:
+ * prepare - clk_(un)prepare only ensures parent is (un)prepared
+ * enable - clk_enable and clk_disable are functional & control gating
+ * rate - inherits rate from parent.  No clk_set_rate support
+ * parent - fixed parent.  No clk_set_parent support
+ */
+
+/*
+ * It works on following logic:
+ *
+ * For enabling clock, enable = 1
+ *	set2dis = 1	-> clear bit	-> set = 0
+ *	set2dis = 0	-> set bit	-> set = 1
+ *
+ * For disabling clock, enable = 0
+ *	set2dis = 1	-> set bit	-> set = 1
+ *	set2dis = 0	-> clear bit	-> set = 0
+ *
+ * So, result is always: enable xor set2dis.
+ */
+static void clk_gate_endisable(struct clk *clk, int enable)
+{
+	struct clk_gate *gate = to_clk_gate(clk_dev_binded(clk) ?
+		(struct clk *)dev_get_driver_data(clk->dev) :
+		clk);
+	int set = gate->flags & CLK_GATE_SET_TO_DISABLE ? 1 : 0;
+	u32 reg;
+
+	set ^= enable;
+
+	if (gate->flags & CLK_GATE_HIWORD_MASK) {
+		reg = BIT(gate->bit_idx + 16);
+		if (set)
+			reg |= BIT(gate->bit_idx);
+	} else {
+		reg = readl(gate->reg);
+
+		if (set)
+			reg |= BIT(gate->bit_idx);
+		else
+			reg &= ~BIT(gate->bit_idx);
+	}
+
+	writel(reg, gate->reg);
+}
+
+static int clk_gate_enable(struct clk *clk)
+{
+	clk_gate_endisable(clk, 1);
+
+	return 0;
+}
+
+static int clk_gate_disable(struct clk *clk)
+{
+	clk_gate_endisable(clk, 0);
+
+	return 0;
+}
+
+int clk_gate_is_enabled(struct clk *clk)
+{
+	struct clk_gate *gate = to_clk_gate(clk_dev_binded(clk) ?
+		(struct clk *)dev_get_driver_data(clk->dev) :
+		clk);
+	u32 reg;
+
+	reg = readl(gate->reg);
+
+	/* if a set bit disables this clk, flip it before masking */
+	if (gate->flags & CLK_GATE_SET_TO_DISABLE)
+		reg ^= BIT(gate->bit_idx);
+
+	reg &= BIT(gate->bit_idx);
+
+	return reg ? 1 : 0;
+}
+
+const struct clk_ops clk_gate_ops = {
+	.enable = clk_gate_enable,
+	.disable = clk_gate_disable,
+	.get_rate = clk_generic_get_rate,
+};
+
+struct clk *clk_register_gate(struct device *dev, const char *name,
+			      const char *parent_name, unsigned long flags,
+			      void __iomem *reg, u8 bit_idx,
+			      u8 clk_gate_flags, spinlock_t *lock)
+{
+	struct clk_gate *gate;
+	struct clk *clk;
+	int ret;
+
+	if (clk_gate_flags & CLK_GATE_HIWORD_MASK) {
+		if (bit_idx > 15) {
+			pr_err("gate bit exceeds LOWORD field\n");
+			return ERR_PTR(-EINVAL);
+		}
+	}
+
+	/* allocate the gate */
+	gate = kzalloc(sizeof(*gate), GFP_KERNEL);
+	if (!gate)
+		return ERR_PTR(-ENOMEM);
+
+	/* struct clk_gate assignments */
+	gate->reg = reg;
+	gate->bit_idx = bit_idx;
+	gate->flags = clk_gate_flags;
+
+	clk = &gate->clk;
+
+	ret = clk_register(clk, UBOOT_DM_CLK_GATE, (ulong)clk,
+			   name, parent_name);
+	if (ret) {
+		kfree(gate);
+		return ERR_PTR(ret);
+	}
+
+	return clk;
+}
+
+U_BOOT_DRIVER(clk_gate) = {
+	.name	= UBOOT_DM_CLK_GATE,
+	.id	= UCLASS_CLK,
+	.ops	= &clk_gate_ops,
+	.flags = DM_FLAG_PRE_RELOC,
+};
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index a60cf6e833..3ed0db86d2 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -59,6 +59,24 @@ struct clk_mux {
 extern const struct clk_ops clk_mux_ops;
 u8 clk_mux_get_parent(struct clk *clk);
 
+struct clk_gate {
+	struct clk	clk;
+	void __iomem	*reg;
+	u8		bit_idx;
+	u8		flags;
+};
+
+#define to_clk_gate(_clk) container_of(_clk, struct clk_gate, clk)
+
+#define CLK_GATE_SET_TO_DISABLE		BIT(0)
+#define CLK_GATE_HIWORD_MASK		BIT(1)
+
+extern const struct clk_ops clk_gate_ops;
+struct clk *clk_register_gate(struct device *dev, const char *name,
+			      const char *parent_name, unsigned long flags,
+			      void __iomem *reg, u8 bit_idx,
+			      u8 clk_gate_flags, spinlock_t *lock);
+
 struct clk_div_table {
 	unsigned int	val;
 	unsigned int	div;
-- 
2.16.4

[U-Boot] [i.MX8MM+CCF 10/41] divider set rate supporrt

[Peng Fan]

Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 drivers/clk/clk-divider.c | 88 +++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 88 insertions(+)

diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c
index 2f09e0bb58..8615f9815d 100644
--- a/drivers/clk/clk-divider.c
+++ b/drivers/clk/clk-divider.c
@@ -18,6 +18,7 @@
 #include <dm/lists.h>
 #include <dm/device-internal.h>
 #include <linux/clk-provider.h>
+#include <linux/log2.h>
 #include <div64.h>
 #include <clk.h>
 #include "clk.h"
@@ -81,8 +82,95 @@ static ulong clk_divider_recalc_rate(struct clk *clk)
 				   divider->flags, divider->width);
 }
 
+static bool _is_valid_table_div(const struct clk_div_table *table,
+				unsigned int div)
+{
+	const struct clk_div_table *clkt;
+
+	for (clkt = table; clkt->div; clkt++)
+		if (clkt->div == div)
+			return true;
+	return false;
+}
+
+static bool _is_valid_div(const struct clk_div_table *table, unsigned int div,
+			  unsigned long flags)
+{
+	if (flags & CLK_DIVIDER_POWER_OF_TWO)
+		return is_power_of_2(div);
+	if (table)
+		return _is_valid_table_div(table, div);
+	return true;
+}
+
+static unsigned int _get_table_val(const struct clk_div_table *table,
+				   unsigned int div)
+{
+	const struct clk_div_table *clkt;
+
+	for (clkt = table; clkt->div; clkt++)
+		if (clkt->div == div)
+			return clkt->val;
+	return 0;
+}
+
+static unsigned int _get_val(const struct clk_div_table *table,
+			     unsigned int div, unsigned long flags, u8 width)
+{
+	if (flags & CLK_DIVIDER_ONE_BASED)
+		return div;
+	if (flags & CLK_DIVIDER_POWER_OF_TWO)
+		return __ffs(div);
+	if (flags & CLK_DIVIDER_MAX_AT_ZERO)
+		return (div == clk_div_mask(width) + 1) ? 0 : div;
+	if (table)
+		return  _get_table_val(table, div);
+	return div - 1;
+}
+int divider_get_val(unsigned long rate, unsigned long parent_rate,
+		    const struct clk_div_table *table, u8 width,
+		    unsigned long flags)
+{
+	unsigned int div, value;
+
+	div = DIV_ROUND_UP_ULL((u64)parent_rate, rate);
+
+	if (!_is_valid_div(table, div, flags))
+		return -EINVAL;
+
+	value = _get_val(table, div, flags, width);
+
+	return min_t(unsigned int, value, clk_div_mask(width));
+}
+
+static ulong clk_divider_set_rate(struct clk *clk, unsigned long rate)
+{
+	struct clk_divider *divider = to_clk_divider(clk_dev_binded(clk) ?
+			(struct clk *)dev_get_driver_data(clk->dev) : clk);
+	unsigned long parent_rate = clk_get_parent_rate(clk);
+	int value;
+	u32 val;
+
+	value = divider_get_val(rate, parent_rate, divider->table,
+				divider->width, divider->flags);
+	if (value < 0)
+		return value;
+
+	if (divider->flags & CLK_DIVIDER_HIWORD_MASK) {
+		val = clk_div_mask(divider->width) << (divider->shift + 16);
+	} else {
+		val = readl(divider->reg);
+		val &= ~(clk_div_mask(divider->width) << divider->shift);
+	}
+	val |= (u32)value << divider->shift;
+	writel(val, divider->reg);
+
+	return clk_get_rate(clk);
+}
+
 const struct clk_ops clk_divider_ops = {
 	.get_rate = clk_divider_recalc_rate,
+	.set_rate = clk_divider_set_rate,
 };
 
 static struct clk *_register_divider(struct device *dev, const char *name,
-- 
2.16.4

[U-Boot] [i.MX8MM+CCF 11/41] clk: fixed_rate: export clk_fixed_rate

[Peng Fan]

Export the structure for others to use.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 drivers/clk/clk_fixed_rate.c | 8 +-------
 include/linux/clk-provider.h | 7 +++++++
 2 files changed, 8 insertions(+), 7 deletions(-)

diff --git a/drivers/clk/clk_fixed_rate.c b/drivers/clk/clk_fixed_rate.c
index 089f060a23..069e643fbc 100644
--- a/drivers/clk/clk_fixed_rate.c
+++ b/drivers/clk/clk_fixed_rate.c
@@ -6,13 +6,7 @@
 #include <common.h>
 #include <clk-uclass.h>
 #include <dm.h>
-
-struct clk_fixed_rate {
-	struct clk clk;
-	unsigned long fixed_rate;
-};
-
-#define to_clk_fixed_rate(dev)	((struct clk_fixed_rate *)dev_get_platdata(dev))
+#include <linux/clk-provider.h>
 
 static ulong clk_fixed_rate_get_rate(struct clk *clk)
 {
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index 3ed0db86d2..b2bed768b6 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -112,6 +112,13 @@ struct clk_fixed_factor {
 #define to_clk_fixed_factor(_clk) container_of(_clk, struct clk_fixed_factor,\
 					       clk)
 
+struct clk_fixed_rate {
+	struct clk clk;
+	unsigned long fixed_rate;
+};
+
+#define to_clk_fixed_rate(dev)	((struct clk_fixed_rate *)dev_get_platdata(dev))
+
 int clk_register(struct clk *clk, const char *drv_name,
 		 ulong drv_data, const char *name,
 		 const char *parent_name);
-- 
2.16.4

[U-Boot] [i.MX8MM+CCF 12/41] clk: fixed_rate: add pre reloc flag

[Peng Fan]

Add pre reloc flag to use this driver before relocation

Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 drivers/clk/clk_fixed_rate.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/clk/clk_fixed_rate.c b/drivers/clk/clk_fixed_rate.c
index 069e643fbc..debada1463 100644
--- a/drivers/clk/clk_fixed_rate.c
+++ b/drivers/clk/clk_fixed_rate.c
@@ -45,4 +45,5 @@ U_BOOT_DRIVER(clk_fixed_rate) = {
 	.ofdata_to_platdata = clk_fixed_rate_ofdata_to_platdata,
 	.platdata_auto_alloc_size = sizeof(struct clk_fixed_rate),
 	.ops = &clk_fixed_rate_ops,
+	.flags = DM_FLAG_PRE_RELOC,
 };
-- 
2.16.4

[U-Boot] [i.MX8MM+CCF 13/41] clk: imx: import clk heplers

[Peng Fan]

Import some clk helpers from Linux Kernel for i.MX8MM usage

Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 drivers/clk/imx/clk.h | 81 +++++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 81 insertions(+)

diff --git a/drivers/clk/imx/clk.h b/drivers/clk/imx/clk.h
index 864a215a22..aa6e81ff13 100644
--- a/drivers/clk/imx/clk.h
+++ b/drivers/clk/imx/clk.h
@@ -42,6 +42,23 @@ static inline struct clk *imx_clk_gate2(const char *name, const char *parent,
 			shift, 0x3, 0);
 }
 
+static inline struct clk *imx_clk_gate4(const char *name, const char *parent,
+		void __iomem *reg, u8 shift)
+{
+	return clk_register_gate2(NULL, name, parent,
+			CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
+			reg, shift, 0x3, 0);
+}
+
+static inline struct clk *imx_clk_gate4_flags(const char *name,
+		const char *parent, void __iomem *reg, u8 shift,
+		unsigned long flags)
+{
+	return clk_register_gate2(NULL, name, parent,
+			flags | CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
+			reg, shift, 0x3, 0);
+}
+
 static inline struct clk *imx_clk_fixed_factor(const char *name,
 		const char *parent, unsigned int mult, unsigned int div)
 {
@@ -56,6 +73,14 @@ static inline struct clk *imx_clk_divider(const char *name, const char *parent,
 			reg, shift, width, 0);
 }
 
+static inline struct clk *imx_clk_divider2(const char *name, const char *parent,
+		void __iomem *reg, u8 shift, u8 width)
+{
+	return clk_register_divider(NULL, name, parent,
+			CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
+			reg, shift, width, 0);
+}
+
 struct clk *imx_clk_pfd(const char *name, const char *parent_name,
 			void __iomem *reg, u8 idx);
 
@@ -63,6 +88,16 @@ struct clk *imx_clk_fixup_mux(const char *name, void __iomem *reg,
 			      u8 shift, u8 width, const char * const *parents,
 			      int num_parents, void (*fixup)(u32 *val));
 
+static inline struct clk *imx_clk_mux_flags(const char *name,
+			void __iomem *reg, u8 shift, u8 width,
+			const char * const *parents, int num_parents,
+			unsigned long flags)
+{
+	return clk_register_mux(NULL, name, parents, num_parents,
+				flags | CLK_SET_RATE_NO_REPARENT, reg, shift,
+				width, 0);
+}
+
 static inline struct clk *imx_clk_mux(const char *name, void __iomem *reg,
 			u8 shift, u8 width, const char * const *parents,
 			int num_parents)
@@ -72,4 +107,50 @@ static inline struct clk *imx_clk_mux(const char *name, void __iomem *reg,
 			width, 0);
 }
 
+static inline struct clk *imx_clk_mux2(const char *name, void __iomem *reg,
+			u8 shift, u8 width, const char * const *parents,
+			int num_parents)
+{
+	return clk_register_mux(NULL, name, parents, num_parents,
+			CLK_SET_RATE_NO_REPARENT | CLK_OPS_PARENT_ENABLE,
+			reg, shift, width, 0);
+}
+
+static inline struct clk *imx_clk_gate(const char *name, const char *parent,
+		void __iomem *reg, u8 shift)
+{
+	return clk_register_gate(NULL, name, parent, CLK_SET_RATE_PARENT, reg,
+			shift, 0, NULL);
+}
+
+static inline struct clk *imx_clk_gate_flags(const char *name, const char *parent,
+		void __iomem *reg, u8 shift, unsigned long flags)
+{
+	return clk_register_gate(NULL, name, parent, flags | CLK_SET_RATE_PARENT, reg,
+			shift, 0, NULL);
+}
+
+static inline struct clk *imx_clk_gate3(const char *name, const char *parent,
+		void __iomem *reg, u8 shift)
+{
+	return clk_register_gate(NULL, name, parent,
+			CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
+			reg, shift, 0, NULL);
+}
+
+struct clk *imx8m_clk_composite_flags(const char *name,
+		const char * const *parent_names,
+		int num_parents, void __iomem *reg, unsigned long flags);
+
+#define __imx8m_clk_composite(name, parent_names, reg, flags) \
+	imx8m_clk_composite_flags(name, parent_names, \
+		ARRAY_SIZE(parent_names), reg, \
+		flags | CLK_SET_RATE_NO_REPARENT | CLK_OPS_PARENT_ENABLE)
+
+#define imx8m_clk_composite(name, parent_names, reg) \
+	__imx8m_clk_composite(name, parent_names, reg, 0)
+
+#define imx8m_clk_composite_critical(name, parent_names, reg) \
+	__imx8m_clk_composite(name, parent_names, reg, CLK_IS_CRITICAL)
+
 #endif /* __MACH_IMX_CLK_H */
-- 
2.16.4

[U-Boot] [i.MX8MM+CCF 14/41] clk: imx: gate2 add set rate

[Peng Fan]

Add set rate for imx clk-gate2

Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 drivers/clk/imx/clk-gate2.c | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/drivers/clk/imx/clk-gate2.c b/drivers/clk/imx/clk-gate2.c
index 83589b9206..75b6b85e07 100644
--- a/drivers/clk/imx/clk-gate2.c
+++ b/drivers/clk/imx/clk-gate2.c
@@ -62,7 +62,18 @@ static int clk_gate2_disable(struct clk *clk)
 	return 0;
 }
 
+static ulong clk_gate2_set_rate(struct clk *clk, ulong rate)
+{
+	struct clk *parent = clk_get_parent(clk);
+
+	if (parent)
+		return clk_set_rate(parent, rate);
+
+	return -ENODEV;
+}
+
 static const struct clk_ops clk_gate2_ops = {
+	.set_rate = clk_gate2_set_rate,
 	.enable = clk_gate2_enable,
 	.disable = clk_gate2_disable,
 	.get_rate = clk_generic_get_rate,
-- 
2.16.4

[U-Boot] [i.MX8MM+CCF 15/41] linux: compat: guard PAGE_SIZE

[Peng Fan]

Some archs defined PAGE_SIZE, such as ARMv8, to avoid build warning,
guard PAGE_SIZE.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 include/linux/compat.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/include/linux/compat.h b/include/linux/compat.h
index d0f51baab4..c1f8bdf8f2 100644
--- a/include/linux/compat.h
+++ b/include/linux/compat.h
@@ -123,7 +123,9 @@ static inline void kmem_cache_destroy(struct kmem_cache *cachep)
 
 #define KERNEL_VERSION(a,b,c)	(((a) << 16) + ((b) << 8) + (c))
 
+#ifndef PAGE_SIZE
 #define PAGE_SIZE	4096
+#endif
 
 /* drivers/char/random.c */
 #define get_random_bytes(...)
-- 
2.16.4

[U-Boot] [i.MX8MM+CCF 16/41] drivers: core: use strcmp when find device by name

[Peng Fan]

`if (!strncmp(dev->name, name, strlen(name)))` might find out
the wrong device, it might find out `dram_pll_ref_sel`, when name is
`dram_pll`. So use strcmp to avoid such issue.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 drivers/core/uclass.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/core/uclass.c b/drivers/core/uclass.c
index fc3157de39..e2f35393a9 100644
--- a/drivers/core/uclass.c
+++ b/drivers/core/uclass.c
@@ -260,7 +260,7 @@ int uclass_find_device_by_name(enum uclass_id id, const char *name,
 		return ret;
 
 	uclass_foreach_dev(dev, uc) {
-		if (!strncmp(dev->name, name, strlen(name))) {
+		if (!strcmp(dev->name, name)) {
 			*devp = dev;
 			return 0;
 		}
-- 
2.16.4

[U-Boot] [i.MX8MM+CCF 17/41] ddr: imx8m: fix ddr firmware location when enable SPL OF

[Peng Fan]

With SPL_OF_SPERATE, the device tree will be padded to
end of the u-boot-spl-nodtb.bin, however we also put
the ddr firmware file to this location, so need to adapt
the code with SPL OF and align to 16bytes to ease copy firmware.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 drivers/ddr/imx/imx8m/helper.c | 12 +++++++++++-
 1 file changed, 11 insertions(+), 1 deletion(-)

diff --git a/drivers/ddr/imx/imx8m/helper.c b/drivers/ddr/imx/imx8m/helper.c
index 61cd4f6db1..1bf580d306 100644
--- a/drivers/ddr/imx/imx8m/helper.c
+++ b/drivers/ddr/imx/imx8m/helper.c
@@ -31,7 +31,17 @@ void ddr_load_train_firmware(enum fw_type type)
 	unsigned long pr_to32, pr_from32;
 	unsigned long fw_offset = type ? IMEM_2D_OFFSET : 0;
 	unsigned long imem_start = (unsigned long)&_end + fw_offset;
-	unsigned long dmem_start = imem_start + IMEM_LEN;
+	unsigned long dmem_start;
+
+#ifdef CONFIG_SPL_OF_CONTROL
+	if (gd->fdt_blob && !fdt_check_header(gd->fdt_blob)) {
+		imem_start = roundup((unsigned long)&_end +
+				     fdt_totalsize(gd->fdt_blob), 16) +
+			fw_offset;
+	}
+#endif
+
+	dmem_start = imem_start + IMEM_LEN;
 
 	pr_from32 = imem_start;
 	pr_to32 = DDR_TRAIN_CODE_BASE_ADDR + 4 * IMEM_OFFSET_ADDR;
-- 
2.16.4

[U-Boot] [i.MX8MM+CCF 18/41] imx: add IMX8MQ kconfig entry

[Peng Fan]

Add IMX8MQ kconfig entry, preparing support IMX8MM

Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 arch/arm/mach-imx/imx8m/Kconfig | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach-imx/imx8m/Kconfig
index 317dee9bc1..9c487870a6 100644
--- a/arch/arm/mach-imx/imx8m/Kconfig
+++ b/arch/arm/mach-imx/imx8m/Kconfig
@@ -4,6 +4,10 @@ config IMX8M
 	bool
 	select ROM_UNIFIED_SECTIONS
 
+config IMX8MQ
+	bool
+	select IMX8M
+
 config SYS_SOC
 	default "imx8m"
 
@@ -13,7 +17,7 @@ choice
 
 config TARGET_IMX8MQ_EVK
 	bool "imx8mq_evk"
-	select IMX8M
+	select IMX8MQ
 	select IMX8M_LPDDR4
 
 endchoice
-- 
2.16.4

[U-Boot] [i.MX8MM+CCF 19/41] imx: add IMX8MM kconfig entry

[Peng Fan]

Add IMX8MM kconfig entry

Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 arch/arm/mach-imx/imx8m/Kconfig | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach-imx/imx8m/Kconfig
index 9c487870a6..35c978e863 100644
--- a/arch/arm/mach-imx/imx8m/Kconfig
+++ b/arch/arm/mach-imx/imx8m/Kconfig
@@ -8,6 +8,10 @@ config IMX8MQ
 	bool
 	select IMX8M
 
+config IMX8MM
+	bool
+	select IMX8M
+
 config SYS_SOC
 	default "imx8m"
 
-- 
2.16.4

[U-Boot] [i.MX8MM+CCF 20/41] imx: imx8mm: add clock bindings header

[Peng Fan]

Add i.MX8MM clock binding header for i.MX8MM

Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 include/dt-bindings/clock/imx8mm-clock.h | 244 +++++++++++++++++++++++++++++++
 1 file changed, 244 insertions(+)
 create mode 100644 include/dt-bindings/clock/imx8mm-clock.h

diff --git a/include/dt-bindings/clock/imx8mm-clock.h b/include/dt-bindings/clock/imx8mm-clock.h
new file mode 100644
index 0000000000..1b4353e7b4
--- /dev/null
+++ b/include/dt-bindings/clock/imx8mm-clock.h
@@ -0,0 +1,244 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright 2017-2018 NXP
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_IMX8MM_H
+#define __DT_BINDINGS_CLOCK_IMX8MM_H
+
+#define IMX8MM_CLK_DUMMY			0
+#define IMX8MM_CLK_32K				1
+#define IMX8MM_CLK_24M				2
+#define IMX8MM_OSC_HDMI_CLK			3
+#define IMX8MM_CLK_EXT1				4
+#define IMX8MM_CLK_EXT2				5
+#define IMX8MM_CLK_EXT3				6
+#define IMX8MM_CLK_EXT4				7
+#define IMX8MM_AUDIO_PLL1_REF_SEL		8
+#define IMX8MM_AUDIO_PLL2_REF_SEL		9
+#define IMX8MM_VIDEO_PLL1_REF_SEL		10
+#define IMX8MM_DRAM_PLL_REF_SEL			11
+#define IMX8MM_GPU_PLL_REF_SEL			12
+#define IMX8MM_VPU_PLL_REF_SEL			13
+#define IMX8MM_ARM_PLL_REF_SEL			14
+#define IMX8MM_SYS_PLL1_REF_SEL			15
+#define IMX8MM_SYS_PLL2_REF_SEL			16
+#define IMX8MM_SYS_PLL3_REF_SEL			17
+#define IMX8MM_AUDIO_PLL1			18
+#define IMX8MM_AUDIO_PLL2			19
+#define IMX8MM_VIDEO_PLL1			20
+#define IMX8MM_DRAM_PLL				21
+#define IMX8MM_GPU_PLL				22
+#define IMX8MM_VPU_PLL				23
+#define IMX8MM_ARM_PLL				24
+#define IMX8MM_SYS_PLL1				25
+#define IMX8MM_SYS_PLL2				26
+#define IMX8MM_SYS_PLL3				27
+#define IMX8MM_AUDIO_PLL1_BYPASS		28
+#define IMX8MM_AUDIO_PLL2_BYPASS		29
+#define IMX8MM_VIDEO_PLL1_BYPASS		30
+#define IMX8MM_DRAM_PLL_BYPASS			31
+#define IMX8MM_GPU_PLL_BYPASS			32
+#define IMX8MM_VPU_PLL_BYPASS			33
+#define IMX8MM_ARM_PLL_BYPASS			34
+#define IMX8MM_SYS_PLL1_BYPASS			35
+#define IMX8MM_SYS_PLL2_BYPASS			36
+#define IMX8MM_SYS_PLL3_BYPASS			37
+#define IMX8MM_AUDIO_PLL1_OUT			38
+#define IMX8MM_AUDIO_PLL2_OUT			39
+#define IMX8MM_VIDEO_PLL1_OUT			40
+#define IMX8MM_DRAM_PLL_OUT			41
+#define IMX8MM_GPU_PLL_OUT			42
+#define IMX8MM_VPU_PLL_OUT			43
+#define IMX8MM_ARM_PLL_OUT			44
+#define IMX8MM_SYS_PLL1_OUT			45
+#define IMX8MM_SYS_PLL2_OUT			46
+#define IMX8MM_SYS_PLL3_OUT			47
+#define IMX8MM_SYS_PLL1_40M			48
+#define IMX8MM_SYS_PLL1_80M			49
+#define IMX8MM_SYS_PLL1_100M			50
+#define IMX8MM_SYS_PLL1_133M			51
+#define IMX8MM_SYS_PLL1_160M			52
+#define IMX8MM_SYS_PLL1_200M			53
+#define IMX8MM_SYS_PLL1_266M			54
+#define IMX8MM_SYS_PLL1_400M			55
+#define IMX8MM_SYS_PLL1_800M			56
+#define IMX8MM_SYS_PLL2_50M			57
+#define IMX8MM_SYS_PLL2_100M			58
+#define IMX8MM_SYS_PLL2_125M			59
+#define IMX8MM_SYS_PLL2_166M			60
+#define IMX8MM_SYS_PLL2_200M			61
+#define IMX8MM_SYS_PLL2_250M			62
+#define IMX8MM_SYS_PLL2_333M			63
+#define IMX8MM_SYS_PLL2_500M			64
+#define IMX8MM_SYS_PLL2_1000M			65
+
+/* core */
+#define IMX8MM_CLK_A53_SRC			66
+#define IMX8MM_CLK_M4_SRC			67
+#define IMX8MM_CLK_VPU_SRC			68
+#define IMX8MM_CLK_GPU3D_SRC			69
+#define IMX8MM_CLK_GPU2D_SRC			70
+#define IMX8MM_CLK_A53_CG			71
+#define IMX8MM_CLK_M4_CG			72
+#define IMX8MM_CLK_VPU_CG			73
+#define IMX8MM_CLK_GPU3D_CG			74
+#define IMX8MM_CLK_GPU2D_CG			75
+#define IMX8MM_CLK_A53_DIV			76
+#define IMX8MM_CLK_M4_DIV			77
+#define IMX8MM_CLK_VPU_DIV			78
+#define IMX8MM_CLK_GPU3D_DIV			79
+#define IMX8MM_CLK_GPU2D_DIV			80
+
+/* bus */
+#define IMX8MM_CLK_MAIN_AXI			81
+#define IMX8MM_CLK_ENET_AXI			82
+#define IMX8MM_CLK_NAND_USDHC_BUS		83
+#define IMX8MM_CLK_VPU_BUS			84
+#define IMX8MM_CLK_DISP_AXI			85
+#define IMX8MM_CLK_DISP_APB			86
+#define IMX8MM_CLK_DISP_RTRM			87
+#define IMX8MM_CLK_USB_BUS			88
+#define IMX8MM_CLK_GPU_AXI			89
+#define IMX8MM_CLK_GPU_AHB			90
+#define IMX8MM_CLK_NOC				91
+#define IMX8MM_CLK_NOC_APB			92
+
+#define IMX8MM_CLK_AHB				93
+#define IMX8MM_CLK_AUDIO_AHB			94
+#define IMX8MM_CLK_IPG_ROOT			95
+#define IMX8MM_CLK_IPG_AUDIO_ROOT		96
+
+#define IMX8MM_CLK_DRAM_ALT			97
+#define IMX8MM_CLK_DRAM_APB			98
+#define IMX8MM_CLK_VPU_G1			99
+#define IMX8MM_CLK_VPU_G2			100
+#define IMX8MM_CLK_DISP_DTRC			101
+#define IMX8MM_CLK_DISP_DC8000			102
+#define IMX8MM_CLK_PCIE1_CTRL			103
+#define IMX8MM_CLK_PCIE1_PHY			104
+#define IMX8MM_CLK_PCIE1_AUX			105
+#define IMX8MM_CLK_DC_PIXEL			106
+#define IMX8MM_CLK_LCDIF_PIXEL			107
+#define IMX8MM_CLK_SAI1				108
+#define IMX8MM_CLK_SAI2				109
+#define IMX8MM_CLK_SAI3				110
+#define IMX8MM_CLK_SAI4				111
+#define IMX8MM_CLK_SAI5				112
+#define IMX8MM_CLK_SAI6				113
+#define IMX8MM_CLK_SPDIF1			114
+#define IMX8MM_CLK_SPDIF2			115
+#define IMX8MM_CLK_ENET_REF			116
+#define IMX8MM_CLK_ENET_TIMER			117
+#define IMX8MM_CLK_ENET_PHY_REF			118
+#define IMX8MM_CLK_NAND				119
+#define IMX8MM_CLK_QSPI				120
+#define IMX8MM_CLK_USDHC1			121
+#define IMX8MM_CLK_USDHC2			122
+#define IMX8MM_CLK_I2C1				123
+#define IMX8MM_CLK_I2C2				124
+#define IMX8MM_CLK_I2C3				125
+#define IMX8MM_CLK_I2C4				126
+#define IMX8MM_CLK_UART1			127
+#define IMX8MM_CLK_UART2			128
+#define IMX8MM_CLK_UART3			129
+#define IMX8MM_CLK_UART4			130
+#define IMX8MM_CLK_USB_CORE_REF			131
+#define IMX8MM_CLK_USB_PHY_REF			132
+#define IMX8MM_CLK_ECSPI1			133
+#define IMX8MM_CLK_ECSPI2			134
+#define IMX8MM_CLK_PWM1				135
+#define IMX8MM_CLK_PWM2				136
+#define IMX8MM_CLK_PWM3				137
+#define IMX8MM_CLK_PWM4				138
+#define IMX8MM_CLK_GPT1				139
+#define IMX8MM_CLK_WDOG				140
+#define IMX8MM_CLK_WRCLK			141
+#define IMX8MM_CLK_DSI_CORE			142
+#define IMX8MM_CLK_DSI_PHY_REF			143
+#define IMX8MM_CLK_DSI_DBI			144
+#define IMX8MM_CLK_USDHC3			145
+#define IMX8MM_CLK_CSI1_CORE			146
+#define IMX8MM_CLK_CSI1_PHY_REF			147
+#define IMX8MM_CLK_CSI1_ESC			148
+#define IMX8MM_CLK_CSI2_CORE			149
+#define IMX8MM_CLK_CSI2_PHY_REF			150
+#define IMX8MM_CLK_CSI2_ESC			151
+#define IMX8MM_CLK_PCIE2_CTRL			152
+#define IMX8MM_CLK_PCIE2_PHY			153
+#define IMX8MM_CLK_PCIE2_AUX			154
+#define IMX8MM_CLK_ECSPI3			155
+#define IMX8MM_CLK_PDM				156
+#define IMX8MM_CLK_VPU_H1			157
+#define IMX8MM_CLK_CLKO1			158
+
+#define IMX8MM_CLK_ECSPI1_ROOT			159
+#define IMX8MM_CLK_ECSPI2_ROOT			160
+#define IMX8MM_CLK_ECSPI3_ROOT			161
+#define IMX8MM_CLK_ENET1_ROOT			162
+#define IMX8MM_CLK_GPT1_ROOT			163
+#define IMX8MM_CLK_I2C1_ROOT			164
+#define IMX8MM_CLK_I2C2_ROOT			165
+#define IMX8MM_CLK_I2C3_ROOT			166
+#define IMX8MM_CLK_I2C4_ROOT			167
+#define IMX8MM_CLK_OCOTP_ROOT			168
+#define IMX8MM_CLK_PCIE1_ROOT			169
+#define IMX8MM_CLK_PWM1_ROOT			170
+#define IMX8MM_CLK_PWM2_ROOT			171
+#define IMX8MM_CLK_PWM3_ROOT			172
+#define IMX8MM_CLK_PWM4_ROOT			173
+#define IMX8MM_CLK_QSPI_ROOT			174
+#define IMX8MM_CLK_NAND_ROOT			175
+#define IMX8MM_CLK_SAI1_ROOT			176
+#define IMX8MM_CLK_SAI1_IPG			177
+#define IMX8MM_CLK_SAI2_ROOT			178
+#define IMX8MM_CLK_SAI2_IPG			179
+#define IMX8MM_CLK_SAI3_ROOT			180
+#define IMX8MM_CLK_SAI3_IPG			181
+#define IMX8MM_CLK_SAI4_ROOT			182
+#define IMX8MM_CLK_SAI4_IPG			183
+#define IMX8MM_CLK_SAI5_ROOT			184
+#define IMX8MM_CLK_SAI5_IPG			185
+#define IMX8MM_CLK_SAI6_ROOT			186
+#define IMX8MM_CLK_SAI6_IPG			187
+#define IMX8MM_CLK_UART1_ROOT			188
+#define IMX8MM_CLK_UART2_ROOT			189
+#define IMX8MM_CLK_UART3_ROOT			190
+#define IMX8MM_CLK_UART4_ROOT			191
+#define IMX8MM_CLK_USB1_CTRL_ROOT		192
+#define IMX8MM_CLK_GPU3D_ROOT			193
+#define IMX8MM_CLK_USDHC1_ROOT			194
+#define IMX8MM_CLK_USDHC2_ROOT			195
+#define IMX8MM_CLK_WDOG1_ROOT			196
+#define IMX8MM_CLK_WDOG2_ROOT			197
+#define IMX8MM_CLK_WDOG3_ROOT			198
+#define IMX8MM_CLK_VPU_G1_ROOT			199
+#define IMX8MM_CLK_GPU_BUS_ROOT			200
+#define IMX8MM_CLK_VPU_H1_ROOT			201
+#define IMX8MM_CLK_VPU_G2_ROOT			202
+#define IMX8MM_CLK_PDM_ROOT			203
+#define IMX8MM_CLK_DISP_ROOT			204
+#define IMX8MM_CLK_DISP_AXI_ROOT		205
+#define IMX8MM_CLK_DISP_APB_ROOT		206
+#define IMX8MM_CLK_DISP_RTRM_ROOT		207
+#define IMX8MM_CLK_USDHC3_ROOT			208
+#define IMX8MM_CLK_TMU_ROOT			209
+#define IMX8MM_CLK_VPU_DEC_ROOT			210
+#define IMX8MM_CLK_SDMA1_ROOT			211
+#define IMX8MM_CLK_SDMA2_ROOT			212
+#define IMX8MM_CLK_SDMA3_ROOT			213
+#define IMX8MM_CLK_GPT_3M			214
+#define IMX8MM_CLK_ARM				215
+#define IMX8MM_CLK_PDM_IPG			216
+#define IMX8MM_CLK_GPU2D_ROOT			217
+#define IMX8MM_CLK_MU_ROOT			218
+#define IMX8MM_CLK_CSI1_ROOT			219
+
+#define IMX8MM_CLK_DRAM_CORE			220
+#define IMX8MM_CLK_DRAM_ALT_ROOT		221
+
+#define IMX8MM_CLK_NAND_USDHC_BUS_RAWNAND_CLK	222
+
+#define IMX8MM_CLK_END				223
+
+#endif
-- 
2.16.4

[U-Boot] [i.MX8MM+CCF 21/41] imx: add i.MX8MM cpu type

[Peng Fan]

Add i.MX8MM cpu type and related helper functions

Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 arch/arm/include/asm/arch-imx/cpu.h       |  6 ++++++
 arch/arm/include/asm/mach-imx/sys_proto.h |  8 ++++++++
 arch/arm/mach-imx/cpu.c                   | 12 ++++++++++++
 3 files changed, 26 insertions(+)

diff --git a/arch/arm/include/asm/arch-imx/cpu.h b/arch/arm/include/asm/arch-imx/cpu.h
index 667badbc06..fab530e324 100644
--- a/arch/arm/include/asm/arch-imx/cpu.h
+++ b/arch/arm/include/asm/arch-imx/cpu.h
@@ -25,6 +25,12 @@
 #define MXC_CPU_MX7S		0x71 /* dummy ID */
 #define MXC_CPU_MX7D		0x72
 #define MXC_CPU_IMX8MQ		0x82
+#define MXC_CPU_IMX8MM		0x85 /* dummy ID */
+#define MXC_CPU_IMX8MML		0x86 /* dummy ID */
+#define MXC_CPU_IMX8MMD		0x87 /* dummy ID */
+#define MXC_CPU_IMX8MMDL	0x88 /* dummy ID */
+#define MXC_CPU_IMX8MMS		0x89 /* dummy ID */
+#define MXC_CPU_IMX8MMSL	0x8a /* dummy ID */
 #define MXC_CPU_IMX8QXP_A0	0x90 /* dummy ID */
 #define MXC_CPU_IMX8QXP		0x92 /* dummy ID */
 #define MXC_CPU_MX7ULP		0xE1 /* Temporally hard code */
diff --git a/arch/arm/include/asm/mach-imx/sys_proto.h b/arch/arm/include/asm/mach-imx/sys_proto.h
index d0f866b630..88927aeb6b 100644
--- a/arch/arm/include/asm/mach-imx/sys_proto.h
+++ b/arch/arm/include/asm/mach-imx/sys_proto.h
@@ -43,6 +43,14 @@
 #define is_mx7ulp() (is_cpu_type(MXC_CPU_MX7ULP))
 
 #define is_imx8mq() (is_cpu_type(MXC_CPU_IMX8MQ))
+#define is_imx8mm() (is_cpu_type(MXC_CPU_IMX8MM) || is_cpu_type(MXC_CPU_IMX8MML) ||\
+	is_cpu_type(MXC_CPU_IMX8MMD) || is_cpu_type(MXC_CPU_IMX8MMDL) || \
+	is_cpu_type(MXC_CPU_IMX8MMS) || is_cpu_type(MXC_CPU_IMX8MMSL))
+#define is_imx8mml() (is_cpu_type(MXC_CPU_IMX8MML))
+#define is_imx8mmd() (is_cpu_type(MXC_CPU_IMX8MMD))
+#define is_imx8mmdl() (is_cpu_type(MXC_CPU_IMX8MMDL))
+#define is_imx8mms() (is_cpu_type(MXC_CPU_IMX8MMS))
+#define is_imx8mmsl() (is_cpu_type(MXC_CPU_IMX8MMSL))
 #define is_imx8qxp() (is_cpu_type(MXC_CPU_IMX8QXP))
 
 #ifdef CONFIG_MX6
diff --git a/arch/arm/mach-imx/cpu.c b/arch/arm/mach-imx/cpu.c
index 6b83f92662..14370929de 100644
--- a/arch/arm/mach-imx/cpu.c
+++ b/arch/arm/mach-imx/cpu.c
@@ -145,6 +145,18 @@ unsigned imx_ddr_size(void)
 const char *get_imx_type(u32 imxtype)
 {
 	switch (imxtype) {
+	case MXC_CPU_IMX8MM:
+		return "8MMQ";	/* Quad-core version of the imx8mm */
+	case MXC_CPU_IMX8MML:
+		return "8MMQL";	/* Quad-core Lite version of the imx8mm */
+	case MXC_CPU_IMX8MMD:
+		return "8MMD";	/* Dual-core version of the imx8mm */
+	case MXC_CPU_IMX8MMDL:
+		return "8MMDL";	/* Dual-core Lite version of the imx8mm */
+	case MXC_CPU_IMX8MMS:
+		return "8MMS";	/* Single-core version of the imx8mm */
+	case MXC_CPU_IMX8MMSL:
+		return "8MMSL";	/* Single-core Lite version of the imx8mm */
 	case MXC_CPU_IMX8MQ:
 		return "8MQ";	/* Quad-core version of the imx8m */
 	case MXC_CPU_MX7S:
-- 
2.16.4

[U-Boot] [i.MX8MM+CCF 22/41] imx: spl: add spl_board_boot_device for i.MX8MM

[Peng Fan]

Differnet board has different controller used, it is
hard to use one layout for them all.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 arch/arm/mach-imx/spl.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/arch/arm/mach-imx/spl.c b/arch/arm/mach-imx/spl.c
index 9f1e0f6a72..a6d7b69ad8 100644
--- a/arch/arm/mach-imx/spl.c
+++ b/arch/arm/mach-imx/spl.c
@@ -18,6 +18,11 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+__weak int spl_board_boot_device(enum boot_device boot_dev_spl)
+{
+	return 0;
+}
+
 #if defined(CONFIG_MX6)
 /* determine boot device from SRC_SBMR1 (BOOT_CFG[4:1]) or SRC_GPR9 register */
 u32 spl_boot_device(void)
@@ -125,6 +130,9 @@ u32 spl_boot_device(void)
 
 	enum boot_device boot_device_spl = get_boot_device();
 
+	if (IS_ENABLED(CONFIG_IMX8MM))
+		return spl_board_boot_device(boot_device_spl);
+
 	switch (boot_device_spl) {
 #if defined(CONFIG_MX7)
 	case SD1_BOOT:
-- 
2.16.4

[U-Boot] [i.MX8MM+CCF 23/41] imx8m: update imx-regs for i.MX8MM

[Peng Fan]

i.MX8MM has similar architecture with i.MX8MQ, but it has totally
different PLL design and some register layout change.

Note: Some registers in this file are not updated because not used now.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 arch/arm/include/asm/arch-imx8m/imx-regs.h | 75 ++++++++++++++++++++++++++++--
 1 file changed, 71 insertions(+), 4 deletions(-)

diff --git a/arch/arm/include/asm/arch-imx8m/imx-regs.h b/arch/arm/include/asm/arch-imx8m/imx-regs.h
index 3facd5450c..44b2f728ee 100644
--- a/arch/arm/include/asm/arch-imx8m/imx-regs.h
+++ b/arch/arm/include/asm/arch-imx8m/imx-regs.h
@@ -8,8 +8,8 @@
 
 #include <asm/mach-imx/regs-lcdif.h>
 
-#define ROM_VERSION_A0		0x800
-#define ROM_VERSION_B0		0x83C
+#define ROM_VERSION_A0		IS_ENABLED(CONFIG_IMX8MQ) ? 0x800 : 0x800
+#define ROM_VERSION_B0		IS_ENABLED(CONFIG_IMX8MQ) ? 0x83C : 0x800
 
 #define M4_BOOTROM_BASE_ADDR	0x007E0000
 
@@ -91,7 +91,11 @@
 #define SEMAPHOR_HS_BASE_ADDR	0x30AC0000
 #define USDHC1_BASE_ADDR	0x30B40000
 #define USDHC2_BASE_ADDR	0x30B50000
+#ifdef CONFIG_IMX8MM
+#define USDHC3_BASE_ADDR	0x30B60000
+#else
 #define MIPI_CS2_BASE_ADDR	0x30B60000
+#endif
 #define MIPI_CSI_PHY2_BASE_ADDR	0x30B70000
 #define CSI2_BASE_ADDR		0x30B80000
 #define QSPI0_BASE_ADDR		0x30BB0000
@@ -118,7 +122,8 @@
 #define USB1_PHY_BASE_ADDR	0x381F0000
 #define USB2_PHY_BASE_ADDR	0x382F0000
 
-#define MXS_LCDIF_BASE		LCDIF_BASE_ADDR
+#define MXS_LCDIF_BASE		is_enable(CONFIG_IMX8MQ) ? \
+					0x30320000 : 0x32e00000
 
 #define SRC_IPS_BASE_ADDR	0x30390000
 #define SRC_DDRC_RCR_ADDR	0x30391000
@@ -147,6 +152,9 @@
 #define SRC_DDR1_RCR_CORE_RESET_N_MASK	BIT(1)
 #define SRC_DDR1_RCR_PRESET_N_MASK	BIT(0)
 
+#define IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK 0x2000u
+#define IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_SHIFT 13
+
 struct iomuxc_gpr_base_regs {
 	u32 gpr[47];
 };
@@ -203,6 +211,7 @@ struct fuse_bank1_regs {
 	u32 rsvd3[3];
 };
 
+#ifdef CONFIG_IMX8MQ
 struct anamix_pll {
 	u32 audio_pll1_cfg0;
 	u32 audio_pll1_cfg1;
@@ -237,6 +246,60 @@ struct anamix_pll {
 	u32 frac_pllout_div_cfg;
 	u32 sscg_pllout_div_cfg;
 };
+#else
+struct anamix_pll {
+	u32 audio_pll1_gnrl_ctl;
+	u32 audio_pll1_fdiv_ctl0;
+	u32 audio_pll1_fdiv_ctl1;
+	u32 audio_pll1_sscg_ctl;
+	u32 audio_pll1_mnit_ctl;
+	u32 audio_pll2_gnrl_ctl;
+	u32 audio_pll2_fdiv_ctl0;
+	u32 audio_pll2_fdiv_ctl1;
+	u32 audio_pll2_sscg_ctl;
+	u32 audio_pll2_mnit_ctl;
+	u32 video_pll1_gnrl_ctl;
+	u32 video_pll1_fdiv_ctl0;
+	u32 video_pll1_fdiv_ctl1;
+	u32 video_pll1_sscg_ctl;
+	u32 video_pll1_mnit_ctl;
+	u32 reserved[5];
+	u32 dram_pll_gnrl_ctl;
+	u32 dram_pll_fdiv_ctl0;
+	u32 dram_pll_fdiv_ctl1;
+	u32 dram_pll_sscg_ctl;
+	u32 dram_pll_mnit_ctl;
+	u32 gpu_pll_gnrl_ctl;
+	u32 gpu_pll_div_ctl;
+	u32 gpu_pll_locked_ctl1;
+	u32 gpu_pll_mnit_ctl;
+	u32 vpu_pll_gnrl_ctl;
+	u32 vpu_pll_div_ctl;
+	u32 vpu_pll_locked_ctl1;
+	u32 vpu_pll_mnit_ctl;
+	u32 arm_pll_gnrl_ctl;
+	u32 arm_pll_div_ctl;
+	u32 arm_pll_locked_ctl1;
+	u32 arm_pll_mnit_ctl;
+	u32 sys_pll1_gnrl_ctl;
+	u32 sys_pll1_div_ctl;
+	u32 sys_pll1_locked_ctl1;
+	u32 reserved2[24];
+	u32 sys_pll1_mnit_ctl;
+	u32 sys_pll2_gnrl_ctl;
+	u32 sys_pll2_div_ctl;
+	u32 sys_pll2_locked_ctl1;
+	u32 sys_pll2_mnit_ctl;
+	u32 sys_pll3_gnrl_ctl;
+	u32 sys_pll3_div_ctl;
+	u32 sys_pll3_locked_ctl1;
+	u32 sys_pll3_mnit_ctl;
+	u32 anamix_misc_ctl;
+	u32 anamix_clk_mnit_ctl;
+	u32 reserved3[437];
+	u32 digprog;
+};
+#endif
 
 struct fuse_bank9_regs {
 	u32 mac_addr0;
@@ -256,11 +319,13 @@ struct src {
 	u32 usbophy2_rcr;
 	u32 mipiphy_rcr;
 	u32 pciephy_rcr;
+	/* Exits on i.MX8MQ */
 	u32 hdmi_rcr;
 	u32 disp_rcr;
 	u32 reserved2[2];
 	u32 gpu_rcr;
 	u32 vpu_rcr;
+	/* The following four exits on i.MX8MQ */
 	u32 pcie2_rcr;
 	u32 mipiphy1_rcr;
 	u32 mipiphy2_rcr;
@@ -283,6 +348,7 @@ struct src {
 	u32 gpr10;
 	u32 reserved5[985];
 	u32 ddr1_rcr;
+	/* Exist on i.MX8MQ */
 	u32 ddr2_rcr;
 };
 
@@ -457,7 +523,8 @@ struct bootrom_sw_info {
 	u32 reserved_3[3];
 };
 
-#define ROM_SW_INFO_ADDR_B0	0x00000968
+#define ROM_SW_INFO_ADDR_B0	(IS_ENABLED(CONFIG_IMX8MQ) ? 0x00000968 :\
+				 0x000009e8)
 #define ROM_SW_INFO_ADDR_A0	0x000009e8
 
 #define ROM_SW_INFO_ADDR is_soc_rev(CHIP_REV_1_0) ? \
-- 
2.16.4

[U-Boot] [i.MX8MM+CCF 24/41] imx: add get_cpu_rev support for i.MX8MM

[Peng Fan]

There are several variants based on i.MX8MM, add the support in
get_cpu_rev

Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 arch/arm/mach-imx/imx8m/soc.c | 57 +++++++++++++++++++++++++++++++++++--------
 1 file changed, 47 insertions(+), 10 deletions(-)

diff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/mach-imx/imx8m/soc.c
index 11251c5f9a..42b99945b4 100644
--- a/arch/arm/mach-imx/imx8m/soc.c
+++ b/arch/arm/mach-imx/imx8m/soc.c
@@ -130,25 +130,62 @@ static struct mm_region imx8m_mem_map[] = {
 
 struct mm_region *mem_map = imx8m_mem_map;
 
+static u32 get_cpu_variant_type(u32 type)
+{
+	struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
+	struct fuse_bank *bank = &ocotp->bank[1];
+	struct fuse_bank1_regs *fuse =
+		(struct fuse_bank1_regs *)bank->fuse_regs;
+
+	u32 value = readl(&fuse->tester4);
+
+	if (type == MXC_CPU_IMX8MM) {
+		switch (value & 0x3) {
+		case 2:
+			if (value & 0x1c0000)
+				return MXC_CPU_IMX8MMDL;
+			else
+				return MXC_CPU_IMX8MMD;
+		case 3:
+			if (value & 0x1c0000)
+				return MXC_CPU_IMX8MMSL;
+			else
+				return MXC_CPU_IMX8MMS;
+		default:
+			if (value & 0x1c0000)
+				return MXC_CPU_IMX8MML;
+			break;
+		}
+	}
+
+	return type;
+}
+
 u32 get_cpu_rev(void)
 {
 	struct anamix_pll *ana_pll = (struct anamix_pll *)ANATOP_BASE_ADDR;
 	u32 reg = readl(&ana_pll->digprog);
 	u32 type = (reg >> 16) & 0xff;
+	u32 major_low = (reg >> 8) & 0xff;
 	u32 rom_version;
 
 	reg &= 0xff;
 
-	if (reg == CHIP_REV_1_0) {
-		/*
-		 * For B0 chip, the DIGPROG is not updated, still TO1.0.
-		 * we have to check ROM version further
-		 */
-		rom_version = readl((void __iomem *)ROM_VERSION_A0);
-		if (rom_version != CHIP_REV_1_0) {
-			rom_version = readl((void __iomem *)ROM_VERSION_B0);
-			if (rom_version >= CHIP_REV_2_0)
-				reg = CHIP_REV_2_0;
+	/* i.MX8MM */
+	if (major_low == 0x41) {
+		type = get_cpu_variant_type(MXC_CPU_IMX8MM);
+	} else {
+		if (reg == CHIP_REV_1_0) {
+			/*
+			 * For B0 chip, the DIGPROG is not updated, still TO1.0.
+			 * we have to check ROM version further
+			 */
+			rom_version = readl((void __iomem *)ROM_VERSION_A0);
+			if (rom_version != CHIP_REV_1_0) {
+				rom_version = readl((void __iomem *)ROM_VERSION_B0);
+				if (rom_version >= CHIP_REV_2_0)
+					reg = CHIP_REV_2_0;
+			}
 		}
 	}
 
-- 
2.16.4

[U-Boot] [i.MX8MM+CCF 25/41] imx8m: rename clock to clock_imx8mq

[Peng Fan]

i.MX8MQ and i.MX8MM has totally different pll design, so
rename clock to clock_imx8mq.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 arch/arm/mach-imx/imx8m/Makefile                    | 3 ++-
 arch/arm/mach-imx/imx8m/{clock.c => clock_imx8mq.c} | 0
 2 files changed, 2 insertions(+), 1 deletion(-)
 rename arch/arm/mach-imx/imx8m/{clock.c => clock_imx8mq.c} (100%)

diff --git a/arch/arm/mach-imx/imx8m/Makefile b/arch/arm/mach-imx/imx8m/Makefile
index feff4941c1..42a1544c6b 100644
--- a/arch/arm/mach-imx/imx8m/Makefile
+++ b/arch/arm/mach-imx/imx8m/Makefile
@@ -3,4 +3,5 @@
 # Copyright 2017 NXP
 
 obj-y += lowlevel_init.o
-obj-y += clock.o clock_slice.o soc.o
+obj-y += clock_slice.o soc.o
+obj-$(CONFIG_IMX8MQ) += clock_imx8mq.o
diff --git a/arch/arm/mach-imx/imx8m/clock.c b/arch/arm/mach-imx/imx8m/clock_imx8mq.c
similarity index 100%
rename from arch/arm/mach-imx/imx8m/clock.c
rename to arch/arm/mach-imx/imx8m/clock_imx8mq.c
-- 
2.16.4

[U-Boot] [i.MX8MM+CCF 26/41] imx8m: restructure clock.h

[Peng Fan]

i.MX8MQ and i.MX8MM use different analog pll design, but they
share same ccm design.
Add clock_imx8mq.h for i.MX8MQ
keep common part in clock.h

Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 arch/arm/include/asm/arch-imx8m/clock.h        | 491 +++----------------------
 arch/arm/include/asm/arch-imx8m/clock_imx8mq.h | 424 +++++++++++++++++++++
 arch/arm/mach-imx/imx8m/clock_imx8mq.c         |   5 +-
 3 files changed, 467 insertions(+), 453 deletions(-)
 create mode 100644 arch/arm/include/asm/arch-imx8m/clock_imx8mq.h

diff --git a/arch/arm/include/asm/arch-imx8m/clock.h b/arch/arm/include/asm/arch-imx8m/clock.h
index e7c1670f6b..7225c760fe 100644
--- a/arch/arm/include/asm/arch-imx8m/clock.h
+++ b/arch/arm/include/asm/arch-imx8m/clock.h
@@ -1,28 +1,29 @@
 /* SPDX-License-Identifier: GPL-2.0+ */
 /*
- * Copyright 2017 NXP
- *
- * Peng Fan <peng.fan@nxp.com>
+ * Copyright 2017-2019 NXP
  */
 
-#ifndef _ASM_ARCH_IMX8M_CLOCK_H
-#define _ASM_ARCH_IMX8M_CLOCK_H
-
 #include <linux/bitops.h>
 
+#ifdef CONFIG_IMX8MQ
+#include <asm/arch/clock_imx8mq.h>
+#else
+#error "Error no clock.h"
+#endif
+
 #define MHZ(X)	((X) * 1000000UL)
 
-enum pll_clocks {
-	ANATOP_ARM_PLL,
-	ANATOP_GPU_PLL,
-	ANATOP_SYSTEM_PLL1,
-	ANATOP_SYSTEM_PLL2,
-	ANATOP_SYSTEM_PLL3,
-	ANATOP_AUDIO_PLL1,
-	ANATOP_AUDIO_PLL2,
-	ANATOP_VIDEO_PLL1,
-	ANATOP_VIDEO_PLL2,
-	ANATOP_DRAM_PLL,
+/* Mainly for compatible to imx common code. */
+enum mxc_clock {
+	MXC_ARM_CLK = 0,
+	MXC_IPG_CLK,
+	MXC_CSPI_CLK,
+	MXC_ESDHC_CLK,
+	MXC_ESDHC2_CLK,
+	MXC_ESDHC3_CLK,
+	MXC_I2C_CLK,
+	MXC_UART_CLK,
+	MXC_QSPI_CLK,
 };
 
 enum clk_slice_type {
@@ -35,297 +36,6 @@ enum clk_slice_type {
 	DRAM_SEL_CLOCK_SLICE,
 };
 
-enum clk_root_index {
-	MXC_ARM_CLK			= 0,
-	ARM_A53_CLK_ROOT		= 0,
-	ARM_M4_CLK_ROOT			= 1,
-	VPU_A53_CLK_ROOT		= 2,
-	GPU_CORE_CLK_ROOT		= 3,
-	GPU_SHADER_CLK_ROOT		= 4,
-	MAIN_AXI_CLK_ROOT		= 16,
-	ENET_AXI_CLK_ROOT		= 17,
-	NAND_USDHC_BUS_CLK_ROOT		= 18,
-	VPU_BUS_CLK_ROOT		= 19,
-	DISPLAY_AXI_CLK_ROOT		= 20,
-	DISPLAY_APB_CLK_ROOT		= 21,
-	DISPLAY_RTRM_CLK_ROOT		= 22,
-	USB_BUS_CLK_ROOT		= 23,
-	GPU_AXI_CLK_ROOT		= 24,
-	GPU_AHB_CLK_ROOT		= 25,
-	NOC_CLK_ROOT			= 26,
-	NOC_APB_CLK_ROOT		= 27,
-	AHB_CLK_ROOT			= 32,
-	IPG_CLK_ROOT			= 33,
-	MXC_IPG_CLK			= 33,
-	AUDIO_AHB_CLK_ROOT		= 34,
-	MIPI_DSI_ESC_RX_CLK_ROOT	= 36,
-	DRAM_SEL_CFG			= 48,
-	CORE_SEL_CFG			= 49,
-	DRAM_ALT_CLK_ROOT		= 64,
-	DRAM_APB_CLK_ROOT		= 65,
-	VPU_G1_CLK_ROOT			= 66,
-	VPU_G2_CLK_ROOT			= 67,
-	DISPLAY_DTRC_CLK_ROOT		= 68,
-	DISPLAY_DC8000_CLK_ROOT		= 69,
-	PCIE1_CTRL_CLK_ROOT		= 70,
-	PCIE1_PHY_CLK_ROOT		= 71,
-	PCIE1_AUX_CLK_ROOT		= 72,
-	DC_PIXEL_CLK_ROOT		= 73,
-	LCDIF_PIXEL_CLK_ROOT		= 74,
-	SAI1_CLK_ROOT			= 75,
-	SAI2_CLK_ROOT			= 76,
-	SAI3_CLK_ROOT			= 77,
-	SAI4_CLK_ROOT			= 78,
-	SAI5_CLK_ROOT			= 79,
-	SAI6_CLK_ROOT			= 80,
-	SPDIF1_CLK_ROOT			= 81,
-	SPDIF2_CLK_ROOT			= 82,
-	ENET_REF_CLK_ROOT		= 83,
-	ENET_TIMER_CLK_ROOT		= 84,
-	ENET_PHY_REF_CLK_ROOT		= 85,
-	NAND_CLK_ROOT			= 86,
-	QSPI_CLK_ROOT			= 87,
-	MXC_ESDHC_CLK			= 88,
-	USDHC1_CLK_ROOT			= 88,
-	MXC_ESDHC2_CLK			= 89,
-	USDHC2_CLK_ROOT			= 89,
-	I2C1_CLK_ROOT			= 90,
-	MXC_I2C_CLK			= 90,
-	I2C2_CLK_ROOT			= 91,
-	I2C3_CLK_ROOT			= 92,
-	I2C4_CLK_ROOT			= 93,
-	UART1_CLK_ROOT			= 94,
-	UART2_CLK_ROOT			= 95,
-	UART3_CLK_ROOT			= 96,
-	UART4_CLK_ROOT			= 97,
-	USB_CORE_REF_CLK_ROOT		= 98,
-	USB_PHY_REF_CLK_ROOT		= 99,
-	GIC_CLK_ROOT			= 100,
-	ECSPI1_CLK_ROOT			= 101,
-	ECSPI2_CLK_ROOT			= 102,
-	PWM1_CLK_ROOT			= 103,
-	PWM2_CLK_ROOT			= 104,
-	PWM3_CLK_ROOT			= 105,
-	PWM4_CLK_ROOT			= 106,
-	GPT1_CLK_ROOT			= 107,
-	GPT2_CLK_ROOT			= 108,
-	GPT3_CLK_ROOT			= 109,
-	GPT4_CLK_ROOT			= 110,
-	GPT5_CLK_ROOT			= 111,
-	GPT6_CLK_ROOT			= 112,
-	TRACE_CLK_ROOT			= 113,
-	WDOG_CLK_ROOT			= 114,
-	WRCLK_CLK_ROOT			= 115,
-	IPP_DO_CLKO1			= 116,
-	IPP_DO_CLKO2			= 117,
-	MIPI_DSI_CORE_CLK_ROOT		= 118,
-	MIPI_DSI_PHY_REF_CLK_ROOT	= 119,
-	MIPI_DSI_DBI_CLK_ROOT		= 120,
-	OLD_MIPI_DSI_ESC_CLK_ROOT	= 121,
-	MIPI_CSI1_CORE_CLK_ROOT		= 122,
-	MIPI_CSI1_PHY_REF_CLK_ROOT	= 123,
-	MIPI_CSI1_ESC_CLK_ROOT		= 124,
-	MIPI_CSI2_CORE_CLK_ROOT		= 125,
-	MIPI_CSI2_PHY_REF_CLK_ROOT	= 126,
-	MIPI_CSI2_ESC_CLK_ROOT		= 127,
-	PCIE2_CTRL_CLK_ROOT		= 128,
-	PCIE2_PHY_CLK_ROOT		= 129,
-	PCIE2_AUX_CLK_ROOT		= 130,
-	ECSPI3_CLK_ROOT			= 131,
-	OLD_MIPI_DSI_ESC_RX_ROOT	= 132,
-	DISPLAY_HDMI_CLK_ROOT		= 133,
-	CLK_ROOT_MAX,
-};
-
-enum clk_root_src {
-	OSC_25M_CLK,
-	ARM_PLL_CLK,
-	DRAM_PLL1_CLK,
-	VIDEO_PLL2_CLK,
-	VPU_PLL_CLK,
-	GPU_PLL_CLK,
-	SYSTEM_PLL1_800M_CLK,
-	SYSTEM_PLL1_400M_CLK,
-	SYSTEM_PLL1_266M_CLK,
-	SYSTEM_PLL1_200M_CLK,
-	SYSTEM_PLL1_160M_CLK,
-	SYSTEM_PLL1_133M_CLK,
-	SYSTEM_PLL1_100M_CLK,
-	SYSTEM_PLL1_80M_CLK,
-	SYSTEM_PLL1_40M_CLK,
-	SYSTEM_PLL2_1000M_CLK,
-	SYSTEM_PLL2_500M_CLK,
-	SYSTEM_PLL2_333M_CLK,
-	SYSTEM_PLL2_250M_CLK,
-	SYSTEM_PLL2_200M_CLK,
-	SYSTEM_PLL2_166M_CLK,
-	SYSTEM_PLL2_125M_CLK,
-	SYSTEM_PLL2_100M_CLK,
-	SYSTEM_PLL2_50M_CLK,
-	SYSTEM_PLL3_CLK,
-	AUDIO_PLL1_CLK,
-	AUDIO_PLL2_CLK,
-	VIDEO_PLL_CLK,
-	OSC_32K_CLK,
-	EXT_CLK_1,
-	EXT_CLK_2,
-	EXT_CLK_3,
-	EXT_CLK_4,
-	OSC_27M_CLK,
-};
-
-/* CCGR index */
-enum clk_ccgr_index {
-	CCGR_DVFS = 0,
-	CCGR_ANAMIX = 1,
-	CCGR_CPU = 2,
-	CCGR_CSU = 4,
-	CCGR_DRAM1 = 5,
-	CCGR_DRAM2_OBSOLETE = 6,
-	CCGR_ECSPI1 = 7,
-	CCGR_ECSPI2 = 8,
-	CCGR_ECSPI3 = 9,
-	CCGR_ENET1 = 10,
-	CCGR_GPIO1 = 11,
-	CCGR_GPIO2 = 12,
-	CCGR_GPIO3 = 13,
-	CCGR_GPIO4 = 14,
-	CCGR_GPIO5 = 15,
-	CCGR_GPT1 = 16,
-	CCGR_GPT2 = 17,
-	CCGR_GPT3 = 18,
-	CCGR_GPT4 = 19,
-	CCGR_GPT5 = 20,
-	CCGR_GPT6 = 21,
-	CCGR_HS = 22,
-	CCGR_I2C1 = 23,
-	CCGR_I2C2 = 24,
-	CCGR_I2C3 = 25,
-	CCGR_I2C4 = 26,
-	CCGR_IOMUX = 27,
-	CCGR_IOMUX1 = 28,
-	CCGR_IOMUX2 = 29,
-	CCGR_IOMUX3 = 30,
-	CCGR_IOMUX4 = 31,
-	CCGR_M4 = 32,
-	CCGR_MU = 33,
-	CCGR_OCOTP = 34,
-	CCGR_OCRAM = 35,
-	CCGR_OCRAM_S = 36,
-	CCGR_PCIE = 37,
-	CCGR_PERFMON1 = 38,
-	CCGR_PERFMON2 = 39,
-	CCGR_PWM1 = 40,
-	CCGR_PWM2 = 41,
-	CCGR_PWM3 = 42,
-	CCGR_PWM4 = 43,
-	CCGR_QOS = 44,
-	CCGR_DISMIX = 45,
-	CCGR_MEGAMIX = 46,
-	CCGR_QSPI = 47,
-	CCGR_RAWNAND = 48,
-	CCGR_RDC = 49,
-	CCGR_ROM = 50,
-	CCGR_SAI1 = 51,
-	CCGR_SAI2 = 52,
-	CCGR_SAI3 = 53,
-	CCGR_SAI4 = 54,
-	CCGR_SAI5 = 55,
-	CCGR_SAI6 = 56,
-	CCGR_SCTR = 57,
-	CCGR_SDMA1 = 58,
-	CCGR_SDMA2 = 59,
-	CCGR_SEC_DEBUG = 60,
-	CCGR_SEMA1 = 61,
-	CCGR_SEMA2 = 62,
-	CCGR_SIM_DISPLAY = 63,
-	CCGR_SIM_ENET = 64,
-	CCGR_SIM_M = 65,
-	CCGR_SIM_MAIN = 66,
-	CCGR_SIM_S = 67,
-	CCGR_SIM_WAKEUP = 68,
-	CCGR_SIM_USB = 69,
-	CCGR_SIM_VPU = 70,
-	CCGR_SNVS = 71,
-	CCGR_TRACE = 72,
-	CCGR_UART1 = 73,
-	CCGR_UART2 = 74,
-	CCGR_UART3 = 75,
-	CCGR_UART4 = 76,
-	CCGR_USB_CTRL1 = 77,
-	CCGR_USB_CTRL2 = 78,
-	CCGR_USB_PHY1 = 79,
-	CCGR_USB_PHY2 = 80,
-	CCGR_USDHC1 = 81,
-	CCGR_USDHC2 = 82,
-	CCGR_WDOG1 = 83,
-	CCGR_WDOG2 = 84,
-	CCGR_WDOG3 = 85,
-	CCGR_VA53 = 86,
-	CCGR_GPU = 87,
-	CCGR_HEVC = 88,
-	CCGR_AVC = 89,
-	CCGR_VP9 = 90,
-	CCGR_HEVC_INTER = 91,
-	CCGR_GIC = 92,
-	CCGR_DISPLAY = 93,
-	CCGR_HDMI = 94,
-	CCGR_HDMI_PHY = 95,
-	CCGR_XTAL = 96,
-	CCGR_PLL = 97,
-	CCGR_TSENSOR = 98,
-	CCGR_VPU_DEC = 99,
-	CCGR_PCIE2 = 100,
-	CCGR_MIPI_CSI1 = 101,
-	CCGR_MIPI_CSI2 = 102,
-	CCGR_MAX,
-};
-
-/* src index */
-enum clk_src_index {
-	CLK_SRC_CKIL_SYNC_REQ = 0,
-	CLK_SRC_ARM_PLL_EN = 1,
-	CLK_SRC_GPU_PLL_EN = 2,
-	CLK_SRC_VPU_PLL_EN = 3,
-	CLK_SRC_DRAM_PLL_EN = 4,
-	CLK_SRC_SYSTEM_PLL1_EN = 5,
-	CLK_SRC_SYSTEM_PLL2_EN = 6,
-	CLK_SRC_SYSTEM_PLL3_EN = 7,
-	CLK_SRC_AUDIO_PLL1_EN = 8,
-	CLK_SRC_AUDIO_PLL2_EN = 9,
-	CLK_SRC_VIDEO_PLL1_EN = 10,
-	CLK_SRC_VIDEO_PLL2_EN = 11,
-	CLK_SRC_ARM_PLL = 12,
-	CLK_SRC_GPU_PLL = 13,
-	CLK_SRC_VPU_PLL = 14,
-	CLK_SRC_DRAM_PLL = 15,
-	CLK_SRC_SYSTEM_PLL1_800M = 16,
-	CLK_SRC_SYSTEM_PLL1_400M = 17,
-	CLK_SRC_SYSTEM_PLL1_266M = 18,
-	CLK_SRC_SYSTEM_PLL1_200M = 19,
-	CLK_SRC_SYSTEM_PLL1_160M = 20,
-	CLK_SRC_SYSTEM_PLL1_133M = 21,
-	CLK_SRC_SYSTEM_PLL1_100M = 22,
-	CLK_SRC_SYSTEM_PLL1_80M = 23,
-	CLK_SRC_SYSTEM_PLL1_40M = 24,
-	CLK_SRC_SYSTEM_PLL2_1000M = 25,
-	CLK_SRC_SYSTEM_PLL2_500M = 26,
-	CLK_SRC_SYSTEM_PLL2_333M = 27,
-	CLK_SRC_SYSTEM_PLL2_250M = 28,
-	CLK_SRC_SYSTEM_PLL2_200M = 29,
-	CLK_SRC_SYSTEM_PLL2_166M = 30,
-	CLK_SRC_SYSTEM_PLL2_125M = 31,
-	CLK_SRC_SYSTEM_PLL2_100M = 32,
-	CLK_SRC_SYSTEM_PLL2_50M = 33,
-	CLK_SRC_SYSTEM_PLL3 = 34,
-	CLK_SRC_AUDIO_PLL1 = 35,
-	CLK_SRC_AUDIO_PLL2 = 36,
-	CLK_SRC_VIDEO_PLL1 = 37,
-	CLK_SRC_VIDEO_PLL2 = 38,
-	CLK_SRC_OSC_25M = 39,
-	CLK_SRC_OSC_27M = 40,
-};
-
 enum root_pre_div {
 	CLK_ROOT_PRE_DIV1 = 0,
 	CLK_ROOT_PRE_DIV2,
@@ -466,6 +176,29 @@ struct ccm_reg {
 	struct ccm_root ip_root[78];
 };
 
+enum enet_freq {
+	ENET_25MHZ = 0,
+	ENET_50MHZ,
+	ENET_125MHZ,
+};
+
+#define DRAM_BYPASS_ROOT_CONFIG(_rate, _m, _p, _s, _k)			\
+	{								\
+		.clk		=	(_rate),			\
+		.alt_root_sel	=	(_m),				\
+		.alt_pre_div	=	(_p),				\
+		.apb_root_sel	=	(_s),				\
+		.apb_pre_div	=	(_k),				\
+	}
+
+struct dram_bypass_clk_setting {
+	ulong clk;
+	int alt_root_sel;
+	enum root_pre_div alt_pre_div;
+	int apb_root_sel;
+	enum root_pre_div apb_pre_div;
+};
+
 #define CCGR_CLK_ON_MASK	0x03
 #define CLK_SRC_ON_MASK		0x03
 
@@ -503,117 +236,6 @@ struct ccm_reg {
 #define CLK_ROOT_IPG_POST_DIV_MASK	0x3
 #define CLK_ROOT_POST_DIV_SHIFT		0
 #define CLK_ROOT_POST_DIV(n)		((n) & 0x3f)
-
-/* AUDIO PLL1/2 VIDEO PLL1 GPU PLL VPU PLL ARM PLL*/
-#define FRAC_PLL_LOCK_MASK		BIT(31)
-#define FRAC_PLL_CLKE_MASK		BIT(21)
-#define FRAC_PLL_PD_MASK		BIT(19)
-#define FRAC_PLL_REFCLK_SEL_MASK	BIT(16)
-#define FRAC_PLL_LOCK_SEL_MASK		BIT(15)
-#define FRAC_PLL_BYPASS_MASK		BIT(14)
-#define FRAC_PLL_COUNTCLK_SEL_MASK	BIT(13)
-#define FRAC_PLL_NEWDIV_VAL_MASK	BIT(12)
-#define FRAC_PLL_NEWDIV_ACK_MASK	BIT(11)
-#define FRAC_PLL_REFCLK_DIV_VAL(n)	(((n) << 5) & (0x3f << 5))
-#define FRAC_PLL_REFCLK_DIV_VAL_MASK	(0x3f << 5)
-#define FRAC_PLL_REFCLK_DIV_VAL_SHIFT	5
-#define FRAC_PLL_OUTPUT_DIV_VAL_MASK	0x1f
-#define FRAC_PLL_OUTPUT_DIV_VAL(n)	((n) & 0x1f)
-
-#define FRAC_PLL_REFCLK_SEL_OSC_25M	(0 << 16)
-#define FRAC_PLL_REFCLK_SEL_OSC_27M	BIT(16)
-#define FRAC_PLL_REFCLK_SEL_HDMI_PHY_27M (2 << 16)
-#define FRAC_PLL_REFCLK_SEL_CLK_PN	(3 << 16)
-
-#define FRAC_PLL_FRAC_DIV_CTL_MASK	(0x1ffffff << 7)
-#define FRAC_PLL_FRAC_DIV_CTL_SHIFT	7
-#define FRAC_PLL_INT_DIV_CTL_MASK	0x7f
-#define FRAC_PLL_INT_DIV_CTL_VAL(n)	((n) & 0x7f)
-
-/* SYS PLL1/2/3 VIDEO PLL2 DRAM PLL */
-#define SSCG_PLL_LOCK_MASK		BIT(31)
-#define SSCG_PLL_CLKE_MASK		BIT(25)
-#define SSCG_PLL_DIV2_CLKE_MASK		BIT(23)
-#define SSCG_PLL_DIV3_CLKE_MASK		BIT(21)
-#define SSCG_PLL_DIV4_CLKE_MASK		BIT(19)
-#define SSCG_PLL_DIV5_CLKE_MASK		BIT(17)
-#define SSCG_PLL_DIV6_CLKE_MASK		BIT(15)
-#define SSCG_PLL_DIV8_CLKE_MASK		BIT(13)
-#define SSCG_PLL_DIV10_CLKE_MASK	BIT(11)
-#define SSCG_PLL_DIV20_CLKE_MASK	BIT(9)
-#define SSCG_PLL_VIDEO_PLL2_CLKE_MASK	BIT(9)
-#define SSCG_PLL_DRAM_PLL_CLKE_MASK	BIT(9)
-#define SSCG_PLL_PLL3_CLKE_MASK		BIT(9)
-#define SSCG_PLL_PD_MASK		BIT(7)
-#define SSCG_PLL_BYPASS1_MASK		BIT(5)
-#define SSCG_PLL_BYPASS2_MASK		BIT(4)
-#define SSCG_PLL_LOCK_SEL_MASK		BIT(3)
-#define SSCG_PLL_COUNTCLK_SEL_MASK	BIT(2)
-#define SSCG_PLL_REFCLK_SEL_MASK	0x3
-#define SSCG_PLL_REFCLK_SEL_OSC_25M	(0 << 16)
-#define SSCG_PLL_REFCLK_SEL_OSC_27M	BIT(16)
-#define SSCG_PLL_REFCLK_SEL_HDMI_PHY_27M (2 << 16)
-#define SSCG_PLL_REFCLK_SEL_CLK_PN	(3 << 16)
-
-#define SSCG_PLL_SSDS_MASK		BIT(8)
-#define SSCG_PLL_SSMD_MASK		(0x7 << 5)
-#define SSCG_PLL_SSMF_MASK		(0xf << 1)
-#define SSCG_PLL_SSE_MASK		0x1
-
-#define SSCG_PLL_REF_DIVR1_MASK		(0x7 << 25)
-#define SSCG_PLL_REF_DIVR1_SHIFT	25
-#define SSCG_PLL_REF_DIVR1_VAL(n)	(((n) << 25) & SSCG_PLL_REF_DIVR1_MASK)
-#define SSCG_PLL_REF_DIVR2_MASK		(0x3f << 19)
-#define SSCG_PLL_REF_DIVR2_SHIFT	19
-#define SSCG_PLL_REF_DIVR2_VAL(n)	(((n) << 19) & SSCG_PLL_REF_DIVR2_MASK)
-#define SSCG_PLL_FEEDBACK_DIV_F1_MASK	(0x3f << 13)
-#define SSCG_PLL_FEEDBACK_DIV_F1_SHIFT	13
-#define SSCG_PLL_FEEDBACK_DIV_F1_VAL(n)	(((n) << 13) & \
-					 SSCG_PLL_FEEDBACK_DIV_F1_MASK)
-#define SSCG_PLL_FEEDBACK_DIV_F2_MASK	(0x3f << 7)
-#define SSCG_PLL_FEEDBACK_DIV_F2_SHIFT	7
-#define SSCG_PLL_FEEDBACK_DIV_F2_VAL(n)	(((n) << 7) & \
-					 SSCG_PLL_FEEDBACK_DIV_F2_MASK)
-#define SSCG_PLL_OUTPUT_DIV_VAL_MASK	(0x3f << 1)
-#define SSCG_PLL_OUTPUT_DIV_VAL_SHIFT	1
-#define SSCG_PLL_OUTPUT_DIV_VAL(n)	(((n) << 1) & \
-					 SSCG_PLL_OUTPUT_DIV_VAL_MASK)
-#define SSCG_PLL_FILTER_RANGE_MASK	0x1
-
-#define HW_DIGPROG_MAJOR_UPPER_MASK	(0xff << 16)
-#define HW_DIGPROG_MAJOR_LOWER_MASK	(0xff << 8)
-#define HW_DIGPROG_MINOR_MASK		0xff
-
-#define HW_OSC_27M_CLKE_MASK		BIT(4)
-#define HW_OSC_25M_CLKE_MASK		BIT(2)
-#define HW_OSC_32K_SEL_MASK		0x1
-#define HW_OSC_32K_SEL_RTC		0x1
-#define HW_OSC_32K_SEL_25M_DIV800	0x0
-
-#define HW_FRAC_ARM_PLL_DIV_MASK	(0x7 << 20)
-#define HW_FRAC_ARM_PLL_DIV_SHIFT	20
-#define HW_FRAC_VPU_PLL_DIV_MASK	(0x7 << 16)
-#define HW_FRAC_VPU_PLL_DIV_SHIFT	16
-#define HW_FRAC_GPU_PLL_DIV_MASK	(0x7 << 12)
-#define HW_FRAC_GPU_PLL_DIV_SHIFT	12
-#define HW_FRAC_VIDEO_PLL1_DIV_MASK	(0x7 << 10)
-#define HW_FRAC_VIDEO_PLL1_DIV_SHIFT	10
-#define HW_FRAC_AUDIO_PLL2_DIV_MASK	(0x7 << 4)
-#define HW_FRAC_AUDIO_PLL2_DIV_SHIFT	4
-#define HW_FRAC_AUDIO_PLL1_DIV_MASK	0x7
-#define HW_FRAC_AUDIO_PLL1_DIV_SHIFT	0
-
-#define HW_SSCG_VIDEO_PLL2_DIV_MASK	(0x7 << 16)
-#define HW_SSCG_VIDEO_PLL2_DIV_SHIFT	16
-#define HW_SSCG_DRAM_PLL_DIV_MASK	(0x7 << 14)
-#define HW_SSCG_DRAM_PLL_DIV_SHIFT	14
-#define HW_SSCG_SYSTEM_PLL3_DIV_MASK	(0x7 << 8)
-#define HW_SSCG_SYSTEM_PLL3_DIV_SHIFT	8
-#define HW_SSCG_SYSTEM_PLL2_DIV_MASK	(0x7 << 4)
-#define HW_SSCG_SYSTEM_PLL2_DIV_SHIFT	4
-#define HW_SSCG_SYSTEM_PLL1_DIV_MASK	0x7
-#define HW_SSCG_SYSTEM_PLL1_DIV_SHIFT	0
-
 #define ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK		0x01000000
 #define ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_50M_CLK		0x02000000
 #define ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK		0x03000000
@@ -622,34 +244,6 @@ struct ccm_reg {
 #define ENET1_TIME_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK		0x01000000
 #define ENET_PHY_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK	0x01000000
 
-enum enet_freq {
-	ENET_25MHZ = 0,
-	ENET_50MHZ,
-	ENET_125MHZ,
-};
-
-enum frac_pll_out_val {
-	FRAC_PLL_OUT_1000M,
-	FRAC_PLL_OUT_1600M,
-};
-
-#define DRAM_BYPASS_ROOT_CONFIG(_rate, _m, _p, _s, _k)			\
-	{								\
-		.clk		=	(_rate),			\
-		.alt_root_sel	=	(_m),				\
-		.alt_pre_div	=	(_p),				\
-		.apb_root_sel	=	(_s),				\
-		.apb_pre_div	=	(_k),				\
-	}
-
-struct dram_bypass_clk_setting {
-	ulong clk;
-	int alt_root_sel;
-	enum root_pre_div alt_pre_div;
-	int apb_root_sel;
-	enum root_pre_div apb_pre_div;
-};
-
 void dram_pll_init(ulong pll_val);
 void dram_enable_bypass(ulong clk_val);
 void dram_disable_bypass(void);
@@ -659,7 +253,7 @@ int clock_init(void);
 void init_clk_usdhc(u32 index);
 void init_uart_clk(u32 index);
 void init_wdog_clk(void);
-unsigned int mxc_get_clock(enum clk_root_index clk);
+unsigned int mxc_get_clock(enum mxc_clock clk);
 int clock_enable(enum clk_ccgr_index index, bool enable);
 int clock_root_enabled(enum clk_root_index clock_id);
 int clock_root_cfg(enum clk_root_index clock_id, enum root_pre_div pre_div,
@@ -675,4 +269,3 @@ int set_clk_qspi(void);
 void enable_ocotp_clk(unsigned char enable);
 int enable_i2c_clk(unsigned char enable, unsigned int i2c_num);
 int set_clk_enet(enum enet_freq type);
-#endif
diff --git a/arch/arm/include/asm/arch-imx8m/clock_imx8mq.h b/arch/arm/include/asm/arch-imx8m/clock_imx8mq.h
new file mode 100644
index 0000000000..9fa9eb2687
--- /dev/null
+++ b/arch/arm/include/asm/arch-imx8m/clock_imx8mq.h
@@ -0,0 +1,424 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2017 NXP
+ *
+ * Peng Fan <peng.fan@nxp.com>
+ */
+
+#ifndef _ASM_ARCH_IMX8M_CLOCK_H
+#define _ASM_ARCH_IMX8M_CLOCK_H
+
+enum pll_clocks {
+	ANATOP_ARM_PLL,
+	ANATOP_GPU_PLL,
+	ANATOP_SYSTEM_PLL1,
+	ANATOP_SYSTEM_PLL2,
+	ANATOP_SYSTEM_PLL3,
+	ANATOP_AUDIO_PLL1,
+	ANATOP_AUDIO_PLL2,
+	ANATOP_VIDEO_PLL1,
+	ANATOP_VIDEO_PLL2,
+	ANATOP_DRAM_PLL,
+};
+
+enum clk_root_index {
+	ARM_A53_CLK_ROOT		= 0,
+	ARM_M4_CLK_ROOT			= 1,
+	VPU_A53_CLK_ROOT		= 2,
+	GPU_CORE_CLK_ROOT		= 3,
+	GPU_SHADER_CLK_ROOT		= 4,
+	MAIN_AXI_CLK_ROOT		= 16,
+	ENET_AXI_CLK_ROOT		= 17,
+	NAND_USDHC_BUS_CLK_ROOT		= 18,
+	VPU_BUS_CLK_ROOT		= 19,
+	DISPLAY_AXI_CLK_ROOT		= 20,
+	DISPLAY_APB_CLK_ROOT		= 21,
+	DISPLAY_RTRM_CLK_ROOT		= 22,
+	USB_BUS_CLK_ROOT		= 23,
+	GPU_AXI_CLK_ROOT		= 24,
+	GPU_AHB_CLK_ROOT		= 25,
+	NOC_CLK_ROOT			= 26,
+	NOC_APB_CLK_ROOT		= 27,
+	AHB_CLK_ROOT			= 32,
+	IPG_CLK_ROOT			= 33,
+	AUDIO_AHB_CLK_ROOT		= 34,
+	MIPI_DSI_ESC_RX_CLK_ROOT	= 36,
+	DRAM_SEL_CFG			= 48,
+	CORE_SEL_CFG			= 49,
+	DRAM_ALT_CLK_ROOT		= 64,
+	DRAM_APB_CLK_ROOT		= 65,
+	VPU_G1_CLK_ROOT			= 66,
+	VPU_G2_CLK_ROOT			= 67,
+	DISPLAY_DTRC_CLK_ROOT		= 68,
+	DISPLAY_DC8000_CLK_ROOT		= 69,
+	PCIE1_CTRL_CLK_ROOT		= 70,
+	PCIE1_PHY_CLK_ROOT		= 71,
+	PCIE1_AUX_CLK_ROOT		= 72,
+	DC_PIXEL_CLK_ROOT		= 73,
+	LCDIF_PIXEL_CLK_ROOT		= 74,
+	SAI1_CLK_ROOT			= 75,
+	SAI2_CLK_ROOT			= 76,
+	SAI3_CLK_ROOT			= 77,
+	SAI4_CLK_ROOT			= 78,
+	SAI5_CLK_ROOT			= 79,
+	SAI6_CLK_ROOT			= 80,
+	SPDIF1_CLK_ROOT			= 81,
+	SPDIF2_CLK_ROOT			= 82,
+	ENET_REF_CLK_ROOT		= 83,
+	ENET_TIMER_CLK_ROOT		= 84,
+	ENET_PHY_REF_CLK_ROOT		= 85,
+	NAND_CLK_ROOT			= 86,
+	QSPI_CLK_ROOT			= 87,
+	USDHC1_CLK_ROOT			= 88,
+	USDHC2_CLK_ROOT			= 89,
+	I2C1_CLK_ROOT			= 90,
+	I2C2_CLK_ROOT			= 91,
+	I2C3_CLK_ROOT			= 92,
+	I2C4_CLK_ROOT			= 93,
+	UART1_CLK_ROOT			= 94,
+	UART2_CLK_ROOT			= 95,
+	UART3_CLK_ROOT			= 96,
+	UART4_CLK_ROOT			= 97,
+	USB_CORE_REF_CLK_ROOT		= 98,
+	USB_PHY_REF_CLK_ROOT		= 99,
+	GIC_CLK_ROOT			= 100,
+	ECSPI1_CLK_ROOT			= 101,
+	ECSPI2_CLK_ROOT			= 102,
+	PWM1_CLK_ROOT			= 103,
+	PWM2_CLK_ROOT			= 104,
+	PWM3_CLK_ROOT			= 105,
+	PWM4_CLK_ROOT			= 106,
+	GPT1_CLK_ROOT			= 107,
+	GPT2_CLK_ROOT			= 108,
+	GPT3_CLK_ROOT			= 109,
+	GPT4_CLK_ROOT			= 110,
+	GPT5_CLK_ROOT			= 111,
+	GPT6_CLK_ROOT			= 112,
+	TRACE_CLK_ROOT			= 113,
+	WDOG_CLK_ROOT			= 114,
+	WRCLK_CLK_ROOT			= 115,
+	IPP_DO_CLKO1			= 116,
+	IPP_DO_CLKO2			= 117,
+	MIPI_DSI_CORE_CLK_ROOT		= 118,
+	MIPI_DSI_PHY_REF_CLK_ROOT	= 119,
+	MIPI_DSI_DBI_CLK_ROOT		= 120,
+	OLD_MIPI_DSI_ESC_CLK_ROOT	= 121,
+	MIPI_CSI1_CORE_CLK_ROOT		= 122,
+	MIPI_CSI1_PHY_REF_CLK_ROOT	= 123,
+	MIPI_CSI1_ESC_CLK_ROOT		= 124,
+	MIPI_CSI2_CORE_CLK_ROOT		= 125,
+	MIPI_CSI2_PHY_REF_CLK_ROOT	= 126,
+	MIPI_CSI2_ESC_CLK_ROOT		= 127,
+	PCIE2_CTRL_CLK_ROOT		= 128,
+	PCIE2_PHY_CLK_ROOT		= 129,
+	PCIE2_AUX_CLK_ROOT		= 130,
+	ECSPI3_CLK_ROOT			= 131,
+	OLD_MIPI_DSI_ESC_RX_ROOT	= 132,
+	DISPLAY_HDMI_CLK_ROOT		= 133,
+	CLK_ROOT_MAX,
+};
+
+enum clk_root_src {
+	OSC_25M_CLK,
+	ARM_PLL_CLK,
+	DRAM_PLL1_CLK,
+	VIDEO_PLL2_CLK,
+	VPU_PLL_CLK,
+	GPU_PLL_CLK,
+	SYSTEM_PLL1_800M_CLK,
+	SYSTEM_PLL1_400M_CLK,
+	SYSTEM_PLL1_266M_CLK,
+	SYSTEM_PLL1_200M_CLK,
+	SYSTEM_PLL1_160M_CLK,
+	SYSTEM_PLL1_133M_CLK,
+	SYSTEM_PLL1_100M_CLK,
+	SYSTEM_PLL1_80M_CLK,
+	SYSTEM_PLL1_40M_CLK,
+	SYSTEM_PLL2_1000M_CLK,
+	SYSTEM_PLL2_500M_CLK,
+	SYSTEM_PLL2_333M_CLK,
+	SYSTEM_PLL2_250M_CLK,
+	SYSTEM_PLL2_200M_CLK,
+	SYSTEM_PLL2_166M_CLK,
+	SYSTEM_PLL2_125M_CLK,
+	SYSTEM_PLL2_100M_CLK,
+	SYSTEM_PLL2_50M_CLK,
+	SYSTEM_PLL3_CLK,
+	AUDIO_PLL1_CLK,
+	AUDIO_PLL2_CLK,
+	VIDEO_PLL_CLK,
+	OSC_32K_CLK,
+	EXT_CLK_1,
+	EXT_CLK_2,
+	EXT_CLK_3,
+	EXT_CLK_4,
+	OSC_27M_CLK,
+};
+
+/* CCGR index */
+enum clk_ccgr_index {
+	CCGR_DVFS = 0,
+	CCGR_ANAMIX = 1,
+	CCGR_CPU = 2,
+	CCGR_CSU = 4,
+	CCGR_DRAM1 = 5,
+	CCGR_DRAM2_OBSOLETE = 6,
+	CCGR_ECSPI1 = 7,
+	CCGR_ECSPI2 = 8,
+	CCGR_ECSPI3 = 9,
+	CCGR_ENET1 = 10,
+	CCGR_GPIO1 = 11,
+	CCGR_GPIO2 = 12,
+	CCGR_GPIO3 = 13,
+	CCGR_GPIO4 = 14,
+	CCGR_GPIO5 = 15,
+	CCGR_GPT1 = 16,
+	CCGR_GPT2 = 17,
+	CCGR_GPT3 = 18,
+	CCGR_GPT4 = 19,
+	CCGR_GPT5 = 20,
+	CCGR_GPT6 = 21,
+	CCGR_HS = 22,
+	CCGR_I2C1 = 23,
+	CCGR_I2C2 = 24,
+	CCGR_I2C3 = 25,
+	CCGR_I2C4 = 26,
+	CCGR_IOMUX = 27,
+	CCGR_IOMUX1 = 28,
+	CCGR_IOMUX2 = 29,
+	CCGR_IOMUX3 = 30,
+	CCGR_IOMUX4 = 31,
+	CCGR_M4 = 32,
+	CCGR_MU = 33,
+	CCGR_OCOTP = 34,
+	CCGR_OCRAM = 35,
+	CCGR_OCRAM_S = 36,
+	CCGR_PCIE = 37,
+	CCGR_PERFMON1 = 38,
+	CCGR_PERFMON2 = 39,
+	CCGR_PWM1 = 40,
+	CCGR_PWM2 = 41,
+	CCGR_PWM3 = 42,
+	CCGR_PWM4 = 43,
+	CCGR_QOS = 44,
+	CCGR_DISMIX = 45,
+	CCGR_MEGAMIX = 46,
+	CCGR_QSPI = 47,
+	CCGR_RAWNAND = 48,
+	CCGR_RDC = 49,
+	CCGR_ROM = 50,
+	CCGR_SAI1 = 51,
+	CCGR_SAI2 = 52,
+	CCGR_SAI3 = 53,
+	CCGR_SAI4 = 54,
+	CCGR_SAI5 = 55,
+	CCGR_SAI6 = 56,
+	CCGR_SCTR = 57,
+	CCGR_SDMA1 = 58,
+	CCGR_SDMA2 = 59,
+	CCGR_SEC_DEBUG = 60,
+	CCGR_SEMA1 = 61,
+	CCGR_SEMA2 = 62,
+	CCGR_SIM_DISPLAY = 63,
+	CCGR_SIM_ENET = 64,
+	CCGR_SIM_M = 65,
+	CCGR_SIM_MAIN = 66,
+	CCGR_SIM_S = 67,
+	CCGR_SIM_WAKEUP = 68,
+	CCGR_SIM_USB = 69,
+	CCGR_SIM_VPU = 70,
+	CCGR_SNVS = 71,
+	CCGR_TRACE = 72,
+	CCGR_UART1 = 73,
+	CCGR_UART2 = 74,
+	CCGR_UART3 = 75,
+	CCGR_UART4 = 76,
+	CCGR_USB_CTRL1 = 77,
+	CCGR_USB_CTRL2 = 78,
+	CCGR_USB_PHY1 = 79,
+	CCGR_USB_PHY2 = 80,
+	CCGR_USDHC1 = 81,
+	CCGR_USDHC2 = 82,
+	CCGR_WDOG1 = 83,
+	CCGR_WDOG2 = 84,
+	CCGR_WDOG3 = 85,
+	CCGR_VA53 = 86,
+	CCGR_GPU = 87,
+	CCGR_HEVC = 88,
+	CCGR_AVC = 89,
+	CCGR_VP9 = 90,
+	CCGR_HEVC_INTER = 91,
+	CCGR_GIC = 92,
+	CCGR_DISPLAY = 93,
+	CCGR_HDMI = 94,
+	CCGR_HDMI_PHY = 95,
+	CCGR_XTAL = 96,
+	CCGR_PLL = 97,
+	CCGR_TSENSOR = 98,
+	CCGR_VPU_DEC = 99,
+	CCGR_PCIE2 = 100,
+	CCGR_MIPI_CSI1 = 101,
+	CCGR_MIPI_CSI2 = 102,
+	CCGR_MAX,
+};
+
+/* src index */
+enum clk_src_index {
+	CLK_SRC_CKIL_SYNC_REQ = 0,
+	CLK_SRC_ARM_PLL_EN = 1,
+	CLK_SRC_GPU_PLL_EN = 2,
+	CLK_SRC_VPU_PLL_EN = 3,
+	CLK_SRC_DRAM_PLL_EN = 4,
+	CLK_SRC_SYSTEM_PLL1_EN = 5,
+	CLK_SRC_SYSTEM_PLL2_EN = 6,
+	CLK_SRC_SYSTEM_PLL3_EN = 7,
+	CLK_SRC_AUDIO_PLL1_EN = 8,
+	CLK_SRC_AUDIO_PLL2_EN = 9,
+	CLK_SRC_VIDEO_PLL1_EN = 10,
+	CLK_SRC_VIDEO_PLL2_EN = 11,
+	CLK_SRC_ARM_PLL = 12,
+	CLK_SRC_GPU_PLL = 13,
+	CLK_SRC_VPU_PLL = 14,
+	CLK_SRC_DRAM_PLL = 15,
+	CLK_SRC_SYSTEM_PLL1_800M = 16,
+	CLK_SRC_SYSTEM_PLL1_400M = 17,
+	CLK_SRC_SYSTEM_PLL1_266M = 18,
+	CLK_SRC_SYSTEM_PLL1_200M = 19,
+	CLK_SRC_SYSTEM_PLL1_160M = 20,
+	CLK_SRC_SYSTEM_PLL1_133M = 21,
+	CLK_SRC_SYSTEM_PLL1_100M = 22,
+	CLK_SRC_SYSTEM_PLL1_80M = 23,
+	CLK_SRC_SYSTEM_PLL1_40M = 24,
+	CLK_SRC_SYSTEM_PLL2_1000M = 25,
+	CLK_SRC_SYSTEM_PLL2_500M = 26,
+	CLK_SRC_SYSTEM_PLL2_333M = 27,
+	CLK_SRC_SYSTEM_PLL2_250M = 28,
+	CLK_SRC_SYSTEM_PLL2_200M = 29,
+	CLK_SRC_SYSTEM_PLL2_166M = 30,
+	CLK_SRC_SYSTEM_PLL2_125M = 31,
+	CLK_SRC_SYSTEM_PLL2_100M = 32,
+	CLK_SRC_SYSTEM_PLL2_50M = 33,
+	CLK_SRC_SYSTEM_PLL3 = 34,
+	CLK_SRC_AUDIO_PLL1 = 35,
+	CLK_SRC_AUDIO_PLL2 = 36,
+	CLK_SRC_VIDEO_PLL1 = 37,
+	CLK_SRC_VIDEO_PLL2 = 38,
+	CLK_SRC_OSC_25M = 39,
+	CLK_SRC_OSC_27M = 40,
+};
+
+/* AUDIO PLL1/2 VIDEO PLL1 GPU PLL VPU PLL ARM PLL*/
+#define FRAC_PLL_LOCK_MASK		BIT(31)
+#define FRAC_PLL_CLKE_MASK		BIT(21)
+#define FRAC_PLL_PD_MASK		BIT(19)
+#define FRAC_PLL_REFCLK_SEL_MASK	BIT(16)
+#define FRAC_PLL_LOCK_SEL_MASK		BIT(15)
+#define FRAC_PLL_BYPASS_MASK		BIT(14)
+#define FRAC_PLL_COUNTCLK_SEL_MASK	BIT(13)
+#define FRAC_PLL_NEWDIV_VAL_MASK	BIT(12)
+#define FRAC_PLL_NEWDIV_ACK_MASK	BIT(11)
+#define FRAC_PLL_REFCLK_DIV_VAL(n)	(((n) << 5) & (0x3f << 5))
+#define FRAC_PLL_REFCLK_DIV_VAL_MASK	(0x3f << 5)
+#define FRAC_PLL_REFCLK_DIV_VAL_SHIFT	5
+#define FRAC_PLL_OUTPUT_DIV_VAL_MASK	0x1f
+#define FRAC_PLL_OUTPUT_DIV_VAL(n)	((n) & 0x1f)
+
+#define FRAC_PLL_REFCLK_SEL_OSC_25M	(0 << 16)
+#define FRAC_PLL_REFCLK_SEL_OSC_27M	BIT(16)
+#define FRAC_PLL_REFCLK_SEL_HDMI_PHY_27M (2 << 16)
+#define FRAC_PLL_REFCLK_SEL_CLK_PN	(3 << 16)
+
+#define FRAC_PLL_FRAC_DIV_CTL_MASK	(0x1ffffff << 7)
+#define FRAC_PLL_FRAC_DIV_CTL_SHIFT	7
+#define FRAC_PLL_INT_DIV_CTL_MASK	0x7f
+#define FRAC_PLL_INT_DIV_CTL_VAL(n)	((n) & 0x7f)
+
+/* SYS PLL1/2/3 VIDEO PLL2 DRAM PLL */
+#define SSCG_PLL_LOCK_MASK		BIT(31)
+#define SSCG_PLL_CLKE_MASK		BIT(25)
+#define SSCG_PLL_DIV2_CLKE_MASK		BIT(23)
+#define SSCG_PLL_DIV3_CLKE_MASK		BIT(21)
+#define SSCG_PLL_DIV4_CLKE_MASK		BIT(19)
+#define SSCG_PLL_DIV5_CLKE_MASK		BIT(17)
+#define SSCG_PLL_DIV6_CLKE_MASK		BIT(15)
+#define SSCG_PLL_DIV8_CLKE_MASK		BIT(13)
+#define SSCG_PLL_DIV10_CLKE_MASK	BIT(11)
+#define SSCG_PLL_DIV20_CLKE_MASK	BIT(9)
+#define SSCG_PLL_VIDEO_PLL2_CLKE_MASK	BIT(9)
+#define SSCG_PLL_DRAM_PLL_CLKE_MASK	BIT(9)
+#define SSCG_PLL_PLL3_CLKE_MASK		BIT(9)
+#define SSCG_PLL_PD_MASK		BIT(7)
+#define SSCG_PLL_BYPASS1_MASK		BIT(5)
+#define SSCG_PLL_BYPASS2_MASK		BIT(4)
+#define SSCG_PLL_LOCK_SEL_MASK		BIT(3)
+#define SSCG_PLL_COUNTCLK_SEL_MASK	BIT(2)
+#define SSCG_PLL_REFCLK_SEL_MASK	0x3
+#define SSCG_PLL_REFCLK_SEL_OSC_25M	(0 << 16)
+#define SSCG_PLL_REFCLK_SEL_OSC_27M	BIT(16)
+#define SSCG_PLL_REFCLK_SEL_HDMI_PHY_27M (2 << 16)
+#define SSCG_PLL_REFCLK_SEL_CLK_PN	(3 << 16)
+
+#define SSCG_PLL_SSDS_MASK		BIT(8)
+#define SSCG_PLL_SSMD_MASK		(0x7 << 5)
+#define SSCG_PLL_SSMF_MASK		(0xf << 1)
+#define SSCG_PLL_SSE_MASK		0x1
+
+#define SSCG_PLL_REF_DIVR1_MASK		(0x7 << 25)
+#define SSCG_PLL_REF_DIVR1_SHIFT	25
+#define SSCG_PLL_REF_DIVR1_VAL(n)	(((n) << 25) & SSCG_PLL_REF_DIVR1_MASK)
+#define SSCG_PLL_REF_DIVR2_MASK		(0x3f << 19)
+#define SSCG_PLL_REF_DIVR2_SHIFT	19
+#define SSCG_PLL_REF_DIVR2_VAL(n)	(((n) << 19) & SSCG_PLL_REF_DIVR2_MASK)
+#define SSCG_PLL_FEEDBACK_DIV_F1_MASK	(0x3f << 13)
+#define SSCG_PLL_FEEDBACK_DIV_F1_SHIFT	13
+#define SSCG_PLL_FEEDBACK_DIV_F1_VAL(n)	(((n) << 13) & \
+					 SSCG_PLL_FEEDBACK_DIV_F1_MASK)
+#define SSCG_PLL_FEEDBACK_DIV_F2_MASK	(0x3f << 7)
+#define SSCG_PLL_FEEDBACK_DIV_F2_SHIFT	7
+#define SSCG_PLL_FEEDBACK_DIV_F2_VAL(n)	(((n) << 7) & \
+					 SSCG_PLL_FEEDBACK_DIV_F2_MASK)
+#define SSCG_PLL_OUTPUT_DIV_VAL_MASK	(0x3f << 1)
+#define SSCG_PLL_OUTPUT_DIV_VAL_SHIFT	1
+#define SSCG_PLL_OUTPUT_DIV_VAL(n)	(((n) << 1) & \
+					 SSCG_PLL_OUTPUT_DIV_VAL_MASK)
+#define SSCG_PLL_FILTER_RANGE_MASK	0x1
+
+#define HW_DIGPROG_MAJOR_UPPER_MASK	(0xff << 16)
+#define HW_DIGPROG_MAJOR_LOWER_MASK	(0xff << 8)
+#define HW_DIGPROG_MINOR_MASK		0xff
+
+#define HW_OSC_27M_CLKE_MASK		BIT(4)
+#define HW_OSC_25M_CLKE_MASK		BIT(2)
+#define HW_OSC_32K_SEL_MASK		0x1
+#define HW_OSC_32K_SEL_RTC		0x1
+#define HW_OSC_32K_SEL_25M_DIV800	0x0
+
+#define HW_FRAC_ARM_PLL_DIV_MASK	(0x7 << 20)
+#define HW_FRAC_ARM_PLL_DIV_SHIFT	20
+#define HW_FRAC_VPU_PLL_DIV_MASK	(0x7 << 16)
+#define HW_FRAC_VPU_PLL_DIV_SHIFT	16
+#define HW_FRAC_GPU_PLL_DIV_MASK	(0x7 << 12)
+#define HW_FRAC_GPU_PLL_DIV_SHIFT	12
+#define HW_FRAC_VIDEO_PLL1_DIV_MASK	(0x7 << 10)
+#define HW_FRAC_VIDEO_PLL1_DIV_SHIFT	10
+#define HW_FRAC_AUDIO_PLL2_DIV_MASK	(0x7 << 4)
+#define HW_FRAC_AUDIO_PLL2_DIV_SHIFT	4
+#define HW_FRAC_AUDIO_PLL1_DIV_MASK	0x7
+#define HW_FRAC_AUDIO_PLL1_DIV_SHIFT	0
+
+#define HW_SSCG_VIDEO_PLL2_DIV_MASK	(0x7 << 16)
+#define HW_SSCG_VIDEO_PLL2_DIV_SHIFT	16
+#define HW_SSCG_DRAM_PLL_DIV_MASK	(0x7 << 14)
+#define HW_SSCG_DRAM_PLL_DIV_SHIFT	14
+#define HW_SSCG_SYSTEM_PLL3_DIV_MASK	(0x7 << 8)
+#define HW_SSCG_SYSTEM_PLL3_DIV_SHIFT	8
+#define HW_SSCG_SYSTEM_PLL2_DIV_MASK	(0x7 << 4)
+#define HW_SSCG_SYSTEM_PLL2_DIV_SHIFT	4
+#define HW_SSCG_SYSTEM_PLL1_DIV_MASK	0x7
+#define HW_SSCG_SYSTEM_PLL1_DIV_SHIFT	0
+
+enum frac_pll_out_val {
+	FRAC_PLL_OUT_1000M,
+	FRAC_PLL_OUT_1600M,
+};
+#endif
diff --git a/arch/arm/mach-imx/imx8m/clock_imx8mq.c b/arch/arm/mach-imx/imx8m/clock_imx8mq.c
index 289b9417aa..feecdb50f6 100644
--- a/arch/arm/mach-imx/imx8m/clock_imx8mq.c
+++ b/arch/arm/mach-imx/imx8m/clock_imx8mq.c
@@ -322,13 +322,10 @@ int enable_i2c_clk(unsigned char enable, unsigned int i2c_num)
 	return 0;
 }
 
-unsigned int mxc_get_clock(enum clk_root_index clk)
+unsigned int mxc_get_clock(enum mxc_clock clk)
 {
 	u32 val;
 
-	if (clk >= CLK_ROOT_MAX)
-		return 0;
-
 	if (clk == MXC_ARM_CLK)
 		return get_root_clk(ARM_A53_CLK_ROOT);
 
-- 
2.16.4

[U-Boot] [i.MX8MM+CCF 27/41] imx8m: add clk support for i.MX8MM

[Peng Fan]

Introduce clk implementation for i.MX8MM, including pll configuration,
ccm configuration. Mostly will be done clk dm driver,
but such as DRAM part, we still use non clk dm driver, because we
have limited sram.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 arch/arm/include/asm/arch-imx8m/clock.h        |   2 +
 arch/arm/include/asm/arch-imx8m/clock_imx8mm.h | 387 +++++++++++++++++++++
 arch/arm/mach-imx/imx8m/Makefile               |   1 +
 arch/arm/mach-imx/imx8m/clock_imx8mm.c         | 292 ++++++++++++++++
 arch/arm/mach-imx/imx8m/clock_slice.c          | 461 +++++++++++++++++++++++++
 5 files changed, 1143 insertions(+)
 create mode 100644 arch/arm/include/asm/arch-imx8m/clock_imx8mm.h
 create mode 100644 arch/arm/mach-imx/imx8m/clock_imx8mm.c

diff --git a/arch/arm/include/asm/arch-imx8m/clock.h b/arch/arm/include/asm/arch-imx8m/clock.h
index 7225c760fe..ead4b8d3dc 100644
--- a/arch/arm/include/asm/arch-imx8m/clock.h
+++ b/arch/arm/include/asm/arch-imx8m/clock.h
@@ -7,6 +7,8 @@
 
 #ifdef CONFIG_IMX8MQ
 #include <asm/arch/clock_imx8mq.h>
+#elif defined(CONFIG_IMX8MM)
+#include <asm/arch/clock_imx8mm.h>
 #else
 #error "Error no clock.h"
 #endif
diff --git a/arch/arm/include/asm/arch-imx8m/clock_imx8mm.h b/arch/arm/include/asm/arch-imx8m/clock_imx8mm.h
new file mode 100644
index 0000000000..305514a4ec
--- /dev/null
+++ b/arch/arm/include/asm/arch-imx8m/clock_imx8mm.h
@@ -0,0 +1,387 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2018-2019 NXP
+ *
+ * Peng Fan <peng.fan@nxp.com>
+ */
+
+#ifndef _ASM_ARCH_IMX8MM_CLOCK_H
+#define _ASM_ARCH_IMX8MM_CLOCK_H
+
+#define PLL_1443X_RATE(_rate, _m, _p, _s, _k)			\
+	{							\
+		.rate	=	(_rate),			\
+		.mdiv	=	(_m),				\
+		.pdiv	=	(_p),				\
+		.sdiv	=	(_s),				\
+		.kdiv	=	(_k),				\
+	}
+
+#define LOCK_STATUS	BIT(31)
+#define LOCK_SEL_MASK	BIT(29)
+#define CLKE_MASK	BIT(11)
+#define RST_MASK	BIT(9)
+#define BYPASS_MASK	BIT(4)
+#define	MDIV_SHIFT	12
+#define	MDIV_MASK	GENMASK(21, 12)
+#define PDIV_SHIFT	4
+#define PDIV_MASK	GENMASK(9, 4)
+#define SDIV_SHIFT	0
+#define SDIV_MASK	GENMASK(2, 0)
+#define KDIV_SHIFT	0
+#define KDIV_MASK	GENMASK(15, 0)
+
+struct imx_int_pll_rate_table {
+	u32 rate;
+	int mdiv;
+	int pdiv;
+	int sdiv;
+	int kdiv;
+};
+
+enum pll_clocks {
+	ANATOP_ARM_PLL,
+	ANATOP_VPU_PLL,
+	ANATOP_GPU_PLL,
+	ANATOP_SYSTEM_PLL1,
+	ANATOP_SYSTEM_PLL2,
+	ANATOP_SYSTEM_PLL3,
+	ANATOP_AUDIO_PLL1,
+	ANATOP_AUDIO_PLL2,
+	ANATOP_VIDEO_PLL,
+	ANATOP_DRAM_PLL,
+};
+
+enum clk_root_index {
+	ARM_A53_CLK_ROOT		= 0,
+	ARM_M4_CLK_ROOT			= 1,
+	VPU_A53_CLK_ROOT		= 2,
+	GPU3D_CLK_ROOT			= 3,
+	GPU2D_CLK_ROOT			= 4,
+	MAIN_AXI_CLK_ROOT		= 16,
+	ENET_AXI_CLK_ROOT		= 17,
+	NAND_USDHC_BUS_CLK_ROOT		= 18,
+	VPU_BUS_CLK_ROOT		= 19,
+	DISPLAY_AXI_CLK_ROOT		= 20,
+	DISPLAY_APB_CLK_ROOT		= 21,
+	DISPLAY_RTRM_CLK_ROOT		= 22,
+	USB_BUS_CLK_ROOT		= 23,
+	GPU_AXI_CLK_ROOT		= 24,
+	GPU_AHB_CLK_ROOT		= 25,
+	NOC_CLK_ROOT			= 26,
+	NOC_APB_CLK_ROOT		= 27,
+	AHB_CLK_ROOT			= 32,
+	IPG_CLK_ROOT			= 33,
+	AUDIO_AHB_CLK_ROOT		= 34,
+	MIPI_DSI_ESC_RX_CLK_ROOT	= 36,
+	DRAM_SEL_CFG			= 48,
+	CORE_SEL_CFG			= 49,
+	DRAM_ALT_CLK_ROOT		= 64,
+	DRAM_APB_CLK_ROOT		= 65,
+	VPU_G1_CLK_ROOT			= 66,
+	VPU_G2_CLK_ROOT			= 67,
+	DISPLAY_DTRC_CLK_ROOT		= 68,
+	DISPLAY_DC8000_CLK_ROOT		= 69,
+	PCIE_CTRL_CLK_ROOT		= 70,
+	PCIE_PHY_CLK_ROOT		= 71,
+	PCIE_AUX_CLK_ROOT		= 72,
+	DC_PIXEL_CLK_ROOT		= 73,
+	LCDIF_PIXEL_CLK_ROOT		= 74,
+	SAI1_CLK_ROOT			= 75,
+	SAI2_CLK_ROOT			= 76,
+	SAI3_CLK_ROOT			= 77,
+	SAI4_CLK_ROOT			= 78,
+	SAI5_CLK_ROOT			= 79,
+	SAI6_CLK_ROOT			= 80,
+	SPDIF1_CLK_ROOT			= 81,
+	SPDIF2_CLK_ROOT			= 82,
+	ENET_REF_CLK_ROOT		= 83,
+	ENET_TIMER_CLK_ROOT		= 84,
+	ENET_PHY_REF_CLK_ROOT		= 85,
+	NAND_CLK_ROOT			= 86,
+	QSPI_CLK_ROOT			= 87,
+	USDHC1_CLK_ROOT			= 88,
+	USDHC2_CLK_ROOT			= 89,
+	I2C1_CLK_ROOT			= 90,
+	I2C2_CLK_ROOT			= 91,
+	I2C3_CLK_ROOT			= 92,
+	I2C4_CLK_ROOT			= 93,
+	UART1_CLK_ROOT			= 94,
+	UART2_CLK_ROOT			= 95,
+	UART3_CLK_ROOT			= 96,
+	UART4_CLK_ROOT			= 97,
+	USB_CORE_REF_CLK_ROOT		= 98,
+	USB_PHY_REF_CLK_ROOT		= 99,
+	GIC_CLK_ROOT			= 100,
+	ECSPI1_CLK_ROOT			= 101,
+	ECSPI2_CLK_ROOT			= 102,
+	PWM1_CLK_ROOT			= 103,
+	PWM2_CLK_ROOT			= 104,
+	PWM3_CLK_ROOT			= 105,
+	PWM4_CLK_ROOT			= 106,
+	GPT1_CLK_ROOT			= 107,
+	GPT2_CLK_ROOT			= 108,
+	GPT3_CLK_ROOT			= 109,
+	GPT4_CLK_ROOT			= 110,
+	GPT5_CLK_ROOT			= 111,
+	GPT6_CLK_ROOT			= 112,
+	TRACE_CLK_ROOT			= 113,
+	WDOG_CLK_ROOT			= 114,
+	WRCLK_CLK_ROOT			= 115,
+	IPP_DO_CLKO1			= 116,
+	IPP_DO_CLKO2			= 117,
+	MIPI_DSI_CORE_CLK_ROOT		= 118,
+	MIPI_DSI_PHY_REF_CLK_ROOT	= 119,
+	MIPI_DSI_DBI_CLK_ROOT		= 120,
+	USDHC3_CLK_ROOT			= 121,
+	MIPI_CSI1_CORE_CLK_ROOT		= 122,
+	MIPI_CSI1_PHY_REF_CLK_ROOT	= 123,
+	MIPI_CSI1_ESC_CLK_ROOT		= 124,
+	MIPI_CSI2_CORE_CLK_ROOT		= 125,
+	MIPI_CSI2_PHY_REF_CLK_ROOT	= 126,
+	MIPI_CSI2_ESC_CLK_ROOT		= 127,
+	PCIE2_CTRL_CLK_ROOT		= 128,
+	PCIE2_PHY_CLK_ROOT		= 129,
+	PCIE2_AUX_CLK_ROOT		= 130,
+	ECSPI3_CLK_ROOT			= 131,
+	PDM_CLK_ROOT			= 132,
+	VPU_H1_CLK_ROOT			= 133,
+	CLK_ROOT_MAX,
+};
+
+enum clk_root_src {
+	OSC_24M_CLK,
+	ARM_PLL_CLK,
+	DRAM_PLL1_CLK,
+	VIDEO_PLL2_CLK,
+	VPU_PLL_CLK,
+	GPU_PLL_CLK,
+	SYSTEM_PLL1_800M_CLK,
+	SYSTEM_PLL1_400M_CLK,
+	SYSTEM_PLL1_266M_CLK,
+	SYSTEM_PLL1_200M_CLK,
+	SYSTEM_PLL1_160M_CLK,
+	SYSTEM_PLL1_133M_CLK,
+	SYSTEM_PLL1_100M_CLK,
+	SYSTEM_PLL1_80M_CLK,
+	SYSTEM_PLL1_40M_CLK,
+	SYSTEM_PLL2_1000M_CLK,
+	SYSTEM_PLL2_500M_CLK,
+	SYSTEM_PLL2_333M_CLK,
+	SYSTEM_PLL2_250M_CLK,
+	SYSTEM_PLL2_200M_CLK,
+	SYSTEM_PLL2_166M_CLK,
+	SYSTEM_PLL2_125M_CLK,
+	SYSTEM_PLL2_100M_CLK,
+	SYSTEM_PLL2_50M_CLK,
+	SYSTEM_PLL3_CLK,
+	AUDIO_PLL1_CLK,
+	AUDIO_PLL2_CLK,
+	VIDEO_PLL_CLK,
+	OSC_32K_CLK,
+	EXT_CLK_1,
+	EXT_CLK_2,
+	EXT_CLK_3,
+	EXT_CLK_4,
+	OSC_HDMI_CLK
+};
+
+enum clk_ccgr_index {
+	CCGR_DVFS = 0,
+	CCGR_ANAMIX = 1,
+	CCGR_CPU = 2,
+	CCGR_CSU = 3,
+	CCGR_DEBUG = 4,
+	CCGR_DDR1 = 5,
+	CCGR_ECSPI1 = 7,
+	CCGR_ECSPI2 = 8,
+	CCGR_ECSPI3 = 9,
+	CCGR_ENET1 = 10,
+	CCGR_GPIO1 = 11,
+	CCGR_GPIO2 = 12,
+	CCGR_GPIO3 = 13,
+	CCGR_GPIO4 = 14,
+	CCGR_GPIO5 = 15,
+	CCGR_GPT1 = 16,
+	CCGR_GPT2 = 17,
+	CCGR_GPT3 = 18,
+	CCGR_GPT4 = 19,
+	CCGR_GPT5 = 20,
+	CCGR_GPT6 = 21,
+	CCGR_HS = 22,
+	CCGR_I2C1 = 23,
+	CCGR_I2C2 = 24,
+	CCGR_I2C3 = 25,
+	CCGR_I2C4 = 26,
+	CCGR_IOMUX = 27,
+	CCGR_IOMUX1 = 28,
+	CCGR_IOMUX2 = 29,
+	CCGR_IOMUX3 = 30,
+	CCGR_IOMUX4 = 31,
+	CCGR_SNVSMIX_IPG_CLK = 32,
+	CCGR_MU = 33,
+	CCGR_OCOTP = 34,
+	CCGR_OCRAM = 35,
+	CCGR_OCRAM_S = 36,
+	CCGR_PCIE = 37,
+	CCGR_PERFMON1 = 38,
+	CCGR_PERFMON2 = 39,
+	CCGR_PWM1 = 40,
+	CCGR_PWM2 = 41,
+	CCGR_PWM3 = 42,
+	CCGR_PWM4 = 43,
+	CCGR_QOS = 44,
+	CCGR_QOS_DISPMIX = 45,
+	CCGR_QOS_ETHENET = 46,
+	CCGR_QSPI = 47,
+	CCGR_RAWNAND = 48,
+	CCGR_RDC = 49,
+	CCGR_ROM = 50,
+	CCGR_SAI1 = 51,
+	CCGR_SAI2 = 52,
+	CCGR_SAI3 = 53,
+	CCGR_SAI4 = 54,
+	CCGR_SAI5 = 55,
+	CCGR_SAI6 = 56,
+	CCGR_SCTR = 57,
+	CCGR_SDMA1 = 58,
+	CCGR_SDMA2 = 59,
+	CCGR_SEC_DEBUG = 60,
+	CCGR_SEMA1 = 61,
+	CCGR_SEMA2 = 62,
+	CCGR_SIM_DISPLAY = 63,
+	CCGR_SIM_ENET = 64,
+	CCGR_SIM_M = 65,
+	CCGR_SIM_MAIN = 66,
+	CCGR_SIM_S = 67,
+	CCGR_SIM_WAKEUP = 68,
+	CCGR_SIM_HSIO = 69,
+	CCGR_SIM_VPU = 70,
+	CCGR_SNVS = 71,
+	CCGR_TRACE = 72,
+	CCGR_UART1 = 73,
+	CCGR_UART2 = 74,
+	CCGR_UART3 = 75,
+	CCGR_UART4 = 76,
+	CCGR_USB_MSCALE_PL301 = 77,
+	CCGR_GPU3D = 79,
+	CCGR_USDHC1 = 81,
+	CCGR_USDHC2 = 82,
+	CCGR_WDOG1 = 83,
+	CCGR_WDOG2 = 84,
+	CCGR_WDOG3 = 85,
+	CCGR_VPUG1 = 86,
+	CCGR_GPU_BUS = 87,
+	CCGR_VPUH1 = 89,
+	CCGR_VPUG2 = 90,
+	CCGR_PDM = 91,
+	CCGR_GIC = 92,
+	CCGR_DISPMIX = 93,
+	CCGR_USDHC3 = 94,
+	CCGR_SDMA3 = 95,
+	CCGR_XTAL = 96,
+	CCGR_PLL = 97,
+	CCGR_TEMP_SENSOR = 98,
+	CCGR_VPUMIX_BUS = 99,
+	CCGR_GPU2D = 102,
+	CCGR_MAX
+};
+
+enum clk_src_index {
+	CLK_SRC_CKIL_SYNC_REQ = 0,
+	CLK_SRC_ARM_PLL_EN = 1,
+	CLK_SRC_GPU_PLL_EN = 2,
+	CLK_SRC_VPU_PLL_EN = 3,
+	CLK_SRC_DRAM_PLL_EN = 4,
+	CLK_SRC_SYSTEM_PLL1_EN = 5,
+	CLK_SRC_SYSTEM_PLL2_EN = 6,
+	CLK_SRC_SYSTEM_PLL3_EN = 7,
+	CLK_SRC_AUDIO_PLL1_EN = 8,
+	CLK_SRC_AUDIO_PLL2_EN = 9,
+	CLK_SRC_VIDEO_PLL1_EN = 10,
+	CLK_SRC_RESERVED = 11,
+	CLK_SRC_ARM_PLL = 12,
+	CLK_SRC_GPU_PLL = 13,
+	CLK_SRC_VPU_PLL = 14,
+	CLK_SRC_DRAM_PLL = 15,
+	CLK_SRC_SYSTEM_PLL1_800M = 16,
+	CLK_SRC_SYSTEM_PLL1_400M = 17,
+	CLK_SRC_SYSTEM_PLL1_266M = 18,
+	CLK_SRC_SYSTEM_PLL1_200M = 19,
+	CLK_SRC_SYSTEM_PLL1_160M = 20,
+	CLK_SRC_SYSTEM_PLL1_133M = 21,
+	CLK_SRC_SYSTEM_PLL1_100M = 22,
+	CLK_SRC_SYSTEM_PLL1_80M = 23,
+	CLK_SRC_SYSTEM_PLL1_40M = 24,
+	CLK_SRC_SYSTEM_PLL2_1000M = 25,
+	CLK_SRC_SYSTEM_PLL2_500M = 26,
+	CLK_SRC_SYSTEM_PLL2_333M = 27,
+	CLK_SRC_SYSTEM_PLL2_250M = 28,
+	CLK_SRC_SYSTEM_PLL2_200M = 29,
+	CLK_SRC_SYSTEM_PLL2_166M = 30,
+	CLK_SRC_SYSTEM_PLL2_125M = 31,
+	CLK_SRC_SYSTEM_PLL2_100M = 32,
+	CLK_SRC_SYSTEM_PLL2_50M = 33,
+	CLK_SRC_SYSTEM_PLL3 = 34,
+	CLK_SRC_AUDIO_PLL1 = 35,
+	CLK_SRC_AUDIO_PLL2 = 36,
+	CLK_SRC_VIDEO_PLL1 = 37,
+};
+
+#define INTPLL_LOCK_MASK			BIT(31)
+#define INTPLL_LOCK_SEL_MASK			BIT(29)
+#define INTPLL_EXT_BYPASS_MASK			BIT(28)
+#define INTPLL_DIV20_CLKE_MASK			BIT(27)
+#define INTPLL_DIV20_CLKE_OVERRIDE_MASK		BIT(26)
+#define INTPLL_DIV10_CLKE_MASK			BIT(25)
+#define INTPLL_DIV10_CLKE_OVERRIDE_MASK		BIT(24)
+#define INTPLL_DIV8_CLKE_MASK			BIT(23)
+#define INTPLL_DIV8_CLKE_OVERRIDE_MASK		BIT(22)
+#define INTPLL_DIV6_CLKE_MASK			BIT(21)
+#define INTPLL_DIV6_CLKE_OVERRIDE_MASK		BIT(20)
+#define INTPLL_DIV5_CLKE_MASK			BIT(19)
+#define INTPLL_DIV5_CLKE_OVERRIDE_MASK		BIT(18)
+#define INTPLL_DIV4_CLKE_MASK			BIT(17)
+#define INTPLL_DIV4_CLKE_OVERRIDE_MASK		BIT(16)
+#define INTPLL_DIV3_CLKE_MASK			BIT(15)
+#define INTPLL_DIV3_CLKE_OVERRIDE_MASK		BIT(14)
+#define INTPLL_DIV2_CLKE_MASK			BIT(13)
+#define INTPLL_DIV2_CLKE_OVERRIDE_MASK		BIT(12)
+#define INTPLL_CLKE_MASK			BIT(11)
+#define INTPLL_CLKE_OVERRIDE_MASK		BIT(10)
+#define INTPLL_RST_MASK				BIT(9)
+#define INTPLL_RST_OVERRIDE_MASK		BIT(8)
+#define INTPLL_BYPASS_MASK			BIT(4)
+#define INTPLL_PAD_CLK_SEL_MASK			GENMASK(3, 2)
+#define INTPLL_REF_CLK_SEL_MASK			GENMASK(1, 0)
+
+#define INTPLL_MAIN_DIV_MASK		GENMASK(21, 12)
+#define INTPLL_MAIN_DIV_VAL(n)		((n << 12) & GENMASK(21, 12))
+#define INTPLL_MAIN_DIV_SHIFT		12
+#define INTPLL_PRE_DIV_MASK		GENMASK(9, 4)
+#define INTPLL_PRE_DIV_VAL(n)		((n << 4) & GENMASK(9, 4))
+#define INTPLL_PRE_DIV_SHIFT		4
+#define INTPLL_POST_DIV_MASK		GENMASK(2, 0)
+#define INTPLL_POST_DIV_VAL(n)		((n << 0) & GENMASK(2, 0))
+#define INTPLL_POST_DIV_SHIFT		0
+
+#define INTPLL_LOCK_CON_DLY_MASK	GENMASK(5, 4)
+#define INTPLL_LOCK_CON_DLY_SHIFT	4
+#define INTPLL_LOCK_CON_OUT_MASK	GENMASK(3, 2)
+#define INTPLL_LOCK_CON_OUT_SHIFT	2
+#define INTPLL_LOCK_CON_IN_MASK		GENMASK(1, 0)
+#define INTPLL_LOCK_CON_IN_SHIFT	0
+
+#define INTPLL_LRD_EN_MASK		BIT(21)
+#define INTPLL_FOUT_MASK		BIT(20)
+#define INTPLL_AFC_SEL_MASK		BIT(19)
+#define INTPLL_PBIAS_CTRL_MASK		BIT(18)
+#define INTPLL_PBIAS_CTRL_EN_MASK	BIT(17)
+#define INTPLL_AFCINIT_SEL_MASK		BIT(16)
+#define INTPLL_FSEL_MASK		BIT(14)
+#define INTPLL_FEED_EN_MASK		BIT(13)
+#define INTPLL_EXTAFC_MASK		GENMASK(7, 3)
+#define INTPLL_AFC_EN_MASK		BIT(2)
+#define INTPLL_ICP_MASK			GENMASK(1, 0)
+
+#endif
diff --git a/arch/arm/mach-imx/imx8m/Makefile b/arch/arm/mach-imx/imx8m/Makefile
index 42a1544c6b..92184f3135 100644
--- a/arch/arm/mach-imx/imx8m/Makefile
+++ b/arch/arm/mach-imx/imx8m/Makefile
@@ -5,3 +5,4 @@
 obj-y += lowlevel_init.o
 obj-y += clock_slice.o soc.o
 obj-$(CONFIG_IMX8MQ) += clock_imx8mq.o
+obj-$(CONFIG_IMX8MM) += clock_imx8mm.o
diff --git a/arch/arm/mach-imx/imx8m/clock_imx8mm.c b/arch/arm/mach-imx/imx8m/clock_imx8mm.c
new file mode 100644
index 0000000000..2f0903aefb
--- /dev/null
+++ b/arch/arm/mach-imx/imx8m/clock_imx8mm.c
@@ -0,0 +1,292 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2018-2019 NXP
+ *
+ * Peng Fan <peng.fan@nxp.com>
+ */
+
+#include <common.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/io.h>
+#include <clk.h>
+#include <clk-uclass.h>
+#include <dt-bindings/clock/imx8mm-clock.h>
+#include <div64.h>
+#include <errno.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static struct anamix_pll *ana_pll = (struct anamix_pll *)ANATOP_BASE_ADDR;
+
+void enable_ocotp_clk(unsigned char enable)
+{
+	struct clk *clkp;
+	int ret;
+
+	ret = clk_get_by_id(IMX8MM_CLK_OCOTP_ROOT, &clkp);
+	if (ret) {
+		printf("%s: err: %d\n", __func__, ret);
+		return;
+	}
+
+	enable ? clk_enable(clkp) : clk_disable(clkp);
+}
+
+#ifdef CONFIG_SPL_BUILD
+static struct imx_int_pll_rate_table imx8mm_fracpll_tbl[] = {
+	PLL_1443X_RATE(800000000U, 300, 9, 0, 0),
+	PLL_1443X_RATE(750000000U, 250, 8, 0, 0),
+	PLL_1443X_RATE(650000000U, 325, 3, 2, 0),
+	PLL_1443X_RATE(600000000U, 300, 3, 2, 0),
+	PLL_1443X_RATE(594000000U, 99, 1, 2, 0),
+	PLL_1443X_RATE(400000000U, 300, 9, 1, 0),
+	PLL_1443X_RATE(266666667U, 400, 9, 2, 0),
+	PLL_1443X_RATE(167000000U, 334, 3, 4, 0),
+	PLL_1443X_RATE(100000000U, 300, 9, 3, 0),
+};
+
+int fracpll_configure(enum pll_clocks pll, u32 freq)
+{
+	int i;
+	u32 tmp, div_val;
+	void *pll_base;
+	struct imx_int_pll_rate_table *rate;
+
+	for (i = 0; i < ARRAY_SIZE(imx8mm_fracpll_tbl); i++) {
+		if (freq == imx8mm_fracpll_tbl[i].rate)
+			break;
+	}
+
+	if (i == ARRAY_SIZE(imx8mm_fracpll_tbl)) {
+		printf("No matched freq table %u\n", freq);
+		return -EINVAL;
+	}
+
+	rate = &imx8mm_fracpll_tbl[i];
+
+	switch (pll) {
+	case ANATOP_DRAM_PLL:
+		setbits_le32(GPC_BASE_ADDR + 0xEC, 1 << 7);
+		setbits_le32(GPC_BASE_ADDR + 0xF8, 1 << 5);
+		writel(SRC_DDR1_ENABLE_MASK, SRC_BASE_ADDR + 0x1004);
+
+		pll_base = &ana_pll->dram_pll_gnrl_ctl;
+		break;
+	case ANATOP_VIDEO_PLL:
+		pll_base = &ana_pll->video_pll1_gnrl_ctl;
+		break;
+	default:
+		return 0;
+	}
+	/* Bypass clock and set lock to pll output lock */
+	tmp = readl(pll_base);
+	tmp |= BYPASS_MASK;
+	writel(tmp, pll_base);
+
+	/* Enable RST */
+	tmp &= ~RST_MASK;
+	writel(tmp, pll_base);
+
+	div_val = (rate->mdiv << MDIV_SHIFT) | (rate->pdiv << PDIV_SHIFT) |
+		(rate->sdiv << SDIV_SHIFT);
+	writel(div_val, pll_base + 4);
+	writel(rate->kdiv << KDIV_SHIFT, pll_base + 8);
+
+	__udelay(100);
+
+	/* Disable RST */
+	tmp |= RST_MASK;
+	writel(tmp, pll_base);
+
+	/* Wait Lock*/
+	while (!(readl(pll_base) & LOCK_STATUS))
+		;
+
+	/* Bypass */
+	tmp &= ~BYPASS_MASK;
+	writel(tmp, pll_base);
+
+	return 0;
+}
+
+void dram_pll_init(ulong pll_val)
+{
+	fracpll_configure(ANATOP_DRAM_PLL, pll_val);
+}
+
+static struct dram_bypass_clk_setting imx8mm_dram_bypass_tbl[] = {
+	DRAM_BYPASS_ROOT_CONFIG(MHZ(100), 2, CLK_ROOT_PRE_DIV1, 2,
+				CLK_ROOT_PRE_DIV2),
+	DRAM_BYPASS_ROOT_CONFIG(MHZ(250), 3, CLK_ROOT_PRE_DIV2, 2,
+				CLK_ROOT_PRE_DIV2),
+	DRAM_BYPASS_ROOT_CONFIG(MHZ(400), 1, CLK_ROOT_PRE_DIV2, 3,
+				CLK_ROOT_PRE_DIV2),
+};
+
+void dram_enable_bypass(ulong clk_val)
+{
+	int i;
+	struct dram_bypass_clk_setting *config;
+
+	for (i = 0; i < ARRAY_SIZE(imx8mm_dram_bypass_tbl); i++) {
+		if (clk_val == imx8mm_dram_bypass_tbl[i].clk)
+			break;
+	}
+
+	if (i == ARRAY_SIZE(imx8mm_dram_bypass_tbl)) {
+		printf("No matched freq table %lu\n", clk_val);
+		return;
+	}
+
+	config = &imx8mm_dram_bypass_tbl[i];
+
+	clock_set_target_val(DRAM_ALT_CLK_ROOT, CLK_ROOT_ON |
+			     CLK_ROOT_SOURCE_SEL(config->alt_root_sel) |
+			     CLK_ROOT_PRE_DIV(config->alt_pre_div));
+	clock_set_target_val(DRAM_APB_CLK_ROOT, CLK_ROOT_ON |
+			     CLK_ROOT_SOURCE_SEL(config->apb_root_sel) |
+			     CLK_ROOT_PRE_DIV(config->apb_pre_div));
+	clock_set_target_val(DRAM_SEL_CFG, CLK_ROOT_ON |
+			     CLK_ROOT_SOURCE_SEL(1));
+}
+
+void dram_disable_bypass(void)
+{
+	clock_set_target_val(DRAM_SEL_CFG, CLK_ROOT_ON |
+			     CLK_ROOT_SOURCE_SEL(0));
+	clock_set_target_val(DRAM_APB_CLK_ROOT, CLK_ROOT_ON |
+			     CLK_ROOT_SOURCE_SEL(4) |
+			     CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV5));
+}
+#endif
+
+void init_uart_clk(u32 index)
+{
+	/*
+	 * set uart clock root
+	 * 24M OSC
+	 */
+	switch (index) {
+	case 0:
+		clock_enable(CCGR_UART1, 0);
+		clock_set_target_val(UART1_CLK_ROOT, CLK_ROOT_ON |
+				     CLK_ROOT_SOURCE_SEL(0));
+		clock_enable(CCGR_UART1, 1);
+		return;
+	case 1:
+		clock_enable(CCGR_UART2, 0);
+		clock_set_target_val(UART2_CLK_ROOT, CLK_ROOT_ON |
+				     CLK_ROOT_SOURCE_SEL(0));
+		clock_enable(CCGR_UART2, 1);
+		return;
+	case 2:
+		clock_enable(CCGR_UART3, 0);
+		clock_set_target_val(UART3_CLK_ROOT, CLK_ROOT_ON |
+				     CLK_ROOT_SOURCE_SEL(0));
+		clock_enable(CCGR_UART3, 1);
+		return;
+	case 3:
+		clock_enable(CCGR_UART4, 0);
+		clock_set_target_val(UART4_CLK_ROOT, CLK_ROOT_ON |
+				     CLK_ROOT_SOURCE_SEL(0));
+		clock_enable(CCGR_UART4, 1);
+		return;
+	default:
+		printf("Invalid uart index\n");
+		return;
+	}
+}
+
+void init_wdog_clk(void)
+{
+	clock_enable(CCGR_WDOG1, 0);
+	clock_enable(CCGR_WDOG2, 0);
+	clock_enable(CCGR_WDOG3, 0);
+	clock_set_target_val(WDOG_CLK_ROOT, CLK_ROOT_ON |
+			     CLK_ROOT_SOURCE_SEL(0));
+	clock_enable(CCGR_WDOG1, 1);
+	clock_enable(CCGR_WDOG2, 1);
+	clock_enable(CCGR_WDOG3, 1);
+}
+
+int clock_init(void)
+{
+	u32 val_cfg0;
+
+	/*
+	 * The gate is not exported to clk tree, so configure them here.
+	 * According to ANAMIX SPEC
+	 * sys pll1 fixed at 800MHz
+	 * sys pll2 fixed at 1GHz
+	 * Here we only enable the outputs.
+	 */
+	val_cfg0 = readl(&ana_pll->sys_pll1_gnrl_ctl);
+	val_cfg0 |= INTPLL_CLKE_MASK | INTPLL_DIV2_CLKE_MASK |
+		INTPLL_DIV3_CLKE_MASK | INTPLL_DIV4_CLKE_MASK |
+		INTPLL_DIV5_CLKE_MASK | INTPLL_DIV6_CLKE_MASK |
+		INTPLL_DIV8_CLKE_MASK | INTPLL_DIV10_CLKE_MASK |
+		INTPLL_DIV20_CLKE_MASK;
+	writel(val_cfg0, &ana_pll->sys_pll1_gnrl_ctl);
+
+	val_cfg0 = readl(&ana_pll->sys_pll2_gnrl_ctl);
+	val_cfg0 |= INTPLL_CLKE_MASK | INTPLL_DIV2_CLKE_MASK |
+		INTPLL_DIV3_CLKE_MASK | INTPLL_DIV4_CLKE_MASK |
+		INTPLL_DIV5_CLKE_MASK | INTPLL_DIV6_CLKE_MASK |
+		INTPLL_DIV8_CLKE_MASK | INTPLL_DIV10_CLKE_MASK |
+		INTPLL_DIV20_CLKE_MASK;
+	writel(val_cfg0, &ana_pll->sys_pll2_gnrl_ctl);
+
+	/* config GIC to sys_pll2_100m */
+	clock_enable(CCGR_GIC, 0);
+	clock_set_target_val(GIC_CLK_ROOT, CLK_ROOT_ON |
+			     CLK_ROOT_SOURCE_SEL(3));
+	clock_enable(CCGR_GIC, 1);
+
+	clock_set_target_val(NAND_USDHC_BUS_CLK_ROOT, CLK_ROOT_ON |
+			     CLK_ROOT_SOURCE_SEL(1));
+
+	clock_enable(CCGR_DDR1, 0);
+	clock_set_target_val(DRAM_ALT_CLK_ROOT, CLK_ROOT_ON |
+			     CLK_ROOT_SOURCE_SEL(1));
+	clock_set_target_val(DRAM_APB_CLK_ROOT, CLK_ROOT_ON |
+			     CLK_ROOT_SOURCE_SEL(1));
+	clock_enable(CCGR_DDR1, 1);
+
+	init_wdog_clk();
+
+	clock_enable(CCGR_TEMP_SENSOR, 1);
+
+	clock_enable(CCGR_SEC_DEBUG, 1);
+
+	return 0;
+};
+
+u32 imx_get_uartclk(void)
+{
+	return 24000000U;
+}
+
+u32 mxc_get_clock(enum mxc_clock clk)
+{
+	struct clk *clkp;
+	int ret;
+
+	switch (clk) {
+	case MXC_IPG_CLK:
+		ret = clk_get_by_id(IMX8MM_CLK_IPG_ROOT, &clkp);
+		if (ret)
+			return 0;
+		return clk_get_rate(clkp);
+	case MXC_ARM_CLK:
+		ret = clk_get_by_id(IMX8MM_CLK_A53_DIV, &clkp);
+		if (ret)
+			return 0;
+		return clk_get_rate(clkp);
+	default:
+		printf("%s: %d not supported\n", __func__, clk);
+	}
+
+	return 0;
+}
diff --git a/arch/arm/mach-imx/imx8m/clock_slice.c b/arch/arm/mach-imx/imx8m/clock_slice.c
index 1a67c626f1..dc2a018e00 100644
--- a/arch/arm/mach-imx/imx8m/clock_slice.c
+++ b/arch/arm/mach-imx/imx8m/clock_slice.c
@@ -13,6 +13,7 @@
 
 static struct ccm_reg *ccm_reg = (struct ccm_reg *)CCM_BASE_ADDR;
 
+#ifdef CONFIG_IMX8MQ
 static struct clk_root_map root_array[] = {
 	{ARM_A53_CLK_ROOT, CORE_CLOCK_SLICE, 0,
 	 {OSC_25M_CLK, ARM_PLL_CLK, SYSTEM_PLL2_500M_CLK,
@@ -474,6 +475,466 @@ static struct clk_root_map root_array[] = {
 	 {DRAM_PLL1_CLK}
 	},
 };
+#elif defined(CONFIG_IMX8MM)
+static struct clk_root_map root_array[] = {
+	{ARM_A53_CLK_ROOT, CORE_CLOCK_SLICE, 0,
+	 {OSC_24M_CLK, ARM_PLL_CLK, SYSTEM_PLL2_500M_CLK,
+	  SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL1_800M_CLK,
+	  SYSTEM_PLL1_400M_CLK, AUDIO_PLL1_CLK, SYSTEM_PLL3_CLK}
+	},
+	{ARM_M4_CLK_ROOT, CORE_CLOCK_SLICE, 1,
+	 {OSC_24M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL2_250M_CLK,
+	  SYSTEM_PLL1_266M_CLK, SYSTEM_PLL1_800M_CLK,
+	  AUDIO_PLL1_CLK, VIDEO_PLL_CLK, SYSTEM_PLL3_CLK}
+	},
+	{VPU_A53_CLK_ROOT, CORE_CLOCK_SLICE, 2,
+	 {OSC_24M_CLK, ARM_PLL_CLK, SYSTEM_PLL2_500M_CLK,
+	  SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL1_800M_CLK,
+	  SYSTEM_PLL1_400M_CLK, AUDIO_PLL1_CLK, VPU_PLL_CLK}
+	},
+	{GPU3D_CLK_ROOT, CORE_CLOCK_SLICE, 3,
+	 {OSC_24M_CLK, GPU_PLL_CLK, SYSTEM_PLL1_800M_CLK,
+	  SYSTEM_PLL3_CLK, SYSTEM_PLL2_1000M_CLK,
+	  AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK}
+	},
+	{GPU2D_CLK_ROOT, CORE_CLOCK_SLICE, 4,
+	 {OSC_24M_CLK, GPU_PLL_CLK, SYSTEM_PLL1_800M_CLK,
+	  SYSTEM_PLL3_CLK, SYSTEM_PLL2_1000M_CLK,
+	  AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK}
+	},
+	{MAIN_AXI_CLK_ROOT, BUS_CLOCK_SLICE, 0,
+	 {OSC_24M_CLK, SYSTEM_PLL2_333M_CLK, SYSTEM_PLL1_800M_CLK,
+	  SYSTEM_PLL2_250M_CLK, SYSTEM_PLL2_1000M_CLK,
+	  AUDIO_PLL1_CLK, VIDEO_PLL_CLK, SYSTEM_PLL1_100M_CLK}
+	},
+	{ENET_AXI_CLK_ROOT, BUS_CLOCK_SLICE, 1,
+	 {OSC_24M_CLK, SYSTEM_PLL1_266M_CLK, SYSTEM_PLL1_800M_CLK,
+	  SYSTEM_PLL2_250M_CLK, SYSTEM_PLL2_200M_CLK,
+	  AUDIO_PLL1_CLK, VIDEO_PLL_CLK, SYSTEM_PLL3_CLK}
+	},
+	{NAND_USDHC_BUS_CLK_ROOT, BUS_CLOCK_SLICE, 2,
+	 {OSC_24M_CLK, SYSTEM_PLL1_266M_CLK, SYSTEM_PLL1_800M_CLK,
+	  SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_133M_CLK,
+	  SYSTEM_PLL3_CLK, SYSTEM_PLL2_250M_CLK, AUDIO_PLL1_CLK}
+	},
+	{VPU_BUS_CLK_ROOT, BUS_CLOCK_SLICE, 3,
+	 {OSC_24M_CLK, SYSTEM_PLL1_800M_CLK, VPU_PLL_CLK,
+	  AUDIO_PLL2_CLK, SYSTEM_PLL3_CLK, SYSTEM_PLL2_1000M_CLK,
+	  SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_100M_CLK}
+	},
+	{DISPLAY_AXI_CLK_ROOT, BUS_CLOCK_SLICE, 4,
+	 {OSC_24M_CLK, SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL1_800M_CLK,
+	  SYSTEM_PLL3_CLK, SYSTEM_PLL1_40M_CLK, AUDIO_PLL2_CLK,
+	  EXT_CLK_1, EXT_CLK_4}
+	},
+	{DISPLAY_APB_CLK_ROOT, BUS_CLOCK_SLICE, 5,
+	 {OSC_24M_CLK, SYSTEM_PLL2_125M_CLK, SYSTEM_PLL1_800M_CLK,
+	  SYSTEM_PLL3_CLK, SYSTEM_PLL1_40M_CLK, AUDIO_PLL2_CLK,
+	  EXT_CLK_1, EXT_CLK_3}
+	},
+	{DISPLAY_RTRM_CLK_ROOT, BUS_CLOCK_SLICE, 6,
+	 {OSC_24M_CLK, SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_200M_CLK,
+	  SYSTEM_PLL2_1000M_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK,
+	  EXT_CLK_2, EXT_CLK_3}
+	},
+	{USB_BUS_CLK_ROOT, BUS_CLOCK_SLICE, 7,
+	 {OSC_24M_CLK, SYSTEM_PLL2_500M_CLK, SYSTEM_PLL1_800M_CLK,
+	  SYSTEM_PLL2_100M_CLK, SYSTEM_PLL2_200M_CLK,
+	  EXT_CLK_2, EXT_CLK_4, AUDIO_PLL2_CLK}
+	},
+	{GPU_AXI_CLK_ROOT, BUS_CLOCK_SLICE, 8,
+	 {OSC_24M_CLK, SYSTEM_PLL1_800M_CLK, GPU_PLL_CLK,
+	  SYSTEM_PLL3_CLK, SYSTEM_PLL2_1000M_CLK,
+	  AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK}
+	},
+	{GPU_AHB_CLK_ROOT, BUS_CLOCK_SLICE, 9,
+	 {OSC_24M_CLK, SYSTEM_PLL1_800M_CLK, GPU_PLL_CLK,
+	  SYSTEM_PLL3_CLK, SYSTEM_PLL2_1000M_CLK,
+	  AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK}
+	},
+	{NOC_CLK_ROOT, BUS_CLOCK_SLICE, 10,
+	 {OSC_24M_CLK, SYSTEM_PLL1_800M_CLK, SYSTEM_PLL3_CLK,
+	  SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL2_500M_CLK,
+	  AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK}
+	},
+	{NOC_APB_CLK_ROOT, BUS_CLOCK_SLICE, 11,
+	 {OSC_24M_CLK, SYSTEM_PLL1_400M_CLK, SYSTEM_PLL3_CLK,
+	  SYSTEM_PLL2_333M_CLK, SYSTEM_PLL2_200M_CLK,
+	  SYSTEM_PLL1_800M_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK}
+	},
+	{AHB_CLK_ROOT, AHB_CLOCK_SLICE, 0,
+	 {OSC_24M_CLK, SYSTEM_PLL1_133M_CLK, SYSTEM_PLL1_800M_CLK,
+	  SYSTEM_PLL1_400M_CLK, SYSTEM_PLL2_125M_CLK,
+	  SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK}
+	},
+	{AUDIO_AHB_CLK_ROOT, AHB_CLOCK_SLICE, 1,
+	 {OSC_24M_CLK, SYSTEM_PLL2_500M_CLK, SYSTEM_PLL1_800M_CLK,
+	  SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL2_166M_CLK,
+	  SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK}
+	},
+	{MIPI_DSI_ESC_RX_CLK_ROOT, AHB_CLOCK_SLICE, 2,
+	 {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_80M_CLK,
+	  SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
+	  SYSTEM_PLL3_CLK, EXT_CLK_3, AUDIO_PLL2_CLK}
+	},
+	{DRAM_ALT_CLK_ROOT, IP_CLOCK_SLICE, 0,
+	 {OSC_24M_CLK, SYSTEM_PLL1_800M_CLK, SYSTEM_PLL1_100M_CLK,
+	  SYSTEM_PLL2_500M_CLK, SYSTEM_PLL2_1000M_CLK,
+	  SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, SYSTEM_PLL1_266M_CLK}
+	},
+	{DRAM_APB_CLK_ROOT, IP_CLOCK_SLICE, 1,
+	 {OSC_24M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_40M_CLK,
+	  SYSTEM_PLL1_160M_CLK, SYSTEM_PLL1_800M_CLK,
+	  SYSTEM_PLL3_CLK, SYSTEM_PLL2_250M_CLK, AUDIO_PLL2_CLK}
+	},
+	{VPU_G1_CLK_ROOT, IP_CLOCK_SLICE, 2,
+	 {OSC_24M_CLK, VPU_PLL_CLK, SYSTEM_PLL1_800M_CLK,
+	  SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL1_100M_CLK,
+	  SYSTEM_PLL2_125M_CLK, SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK}
+	},
+	{VPU_G2_CLK_ROOT, IP_CLOCK_SLICE, 3,
+	 {OSC_24M_CLK, VPU_PLL_CLK, SYSTEM_PLL1_800M_CLK,
+	  SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL1_100M_CLK,
+	  SYSTEM_PLL2_125M_CLK, SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK}
+	},
+	{DISPLAY_DTRC_CLK_ROOT, IP_CLOCK_SLICE, 4,
+	 {OSC_24M_CLK, VIDEO_PLL2_CLK, SYSTEM_PLL1_800M_CLK,
+	  SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL1_160M_CLK,
+	  VIDEO_PLL_CLK, SYSTEM_PLL3_CLK, AUDIO_PLL2_CLK}
+	},
+	{DISPLAY_DC8000_CLK_ROOT, IP_CLOCK_SLICE, 5,
+	 {OSC_24M_CLK, VIDEO_PLL2_CLK, SYSTEM_PLL1_800M_CLK,
+	  SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL1_160M_CLK,
+	  VIDEO_PLL_CLK, SYSTEM_PLL3_CLK, AUDIO_PLL2_CLK}
+	},
+	{PCIE_CTRL_CLK_ROOT, IP_CLOCK_SLICE, 6,
+	 {OSC_24M_CLK, SYSTEM_PLL2_250M_CLK, SYSTEM_PLL2_200M_CLK,
+	  SYSTEM_PLL1_266M_CLK, SYSTEM_PLL1_800M_CLK,
+	  SYSTEM_PLL2_500M_CLK, SYSTEM_PLL2_333M_CLK, SYSTEM_PLL3_CLK}
+	},
+	{PCIE_PHY_CLK_ROOT, IP_CLOCK_SLICE, 7,
+	 {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL2_500M_CLK,
+	  EXT_CLK_1, EXT_CLK_2, EXT_CLK_3, EXT_CLK_4,
+	  SYSTEM_PLL1_400M_CLK}
+	},
+	{PCIE_AUX_CLK_ROOT, IP_CLOCK_SLICE, 8,
+	 {OSC_24M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL2_50M_CLK,
+	  SYSTEM_PLL3_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_80M_CLK,
+	  SYSTEM_PLL1_160M_CLK, SYSTEM_PLL1_200M_CLK}
+	},
+	{DC_PIXEL_CLK_ROOT, IP_CLOCK_SLICE, 9,
+	 {OSC_24M_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK,
+	  AUDIO_PLL1_CLK, SYSTEM_PLL1_800M_CLK,
+	  SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_4}
+	},
+	{LCDIF_PIXEL_CLK_ROOT, IP_CLOCK_SLICE, 10,
+	 {OSC_24M_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK,
+	  AUDIO_PLL1_CLK, SYSTEM_PLL1_800M_CLK,
+	  SYSTEM_PLL2_1000M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_4}
+	},
+	{SAI1_CLK_ROOT, IP_CLOCK_SLICE, 11,
+	 {OSC_24M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK,
+	  VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK,
+	  OSC_HDMI_CLK, EXT_CLK_1, EXT_CLK_2}
+	},
+	{SAI2_CLK_ROOT, IP_CLOCK_SLICE, 12,
+	 {OSC_24M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK,
+	  VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK,
+	  OSC_HDMI_CLK, EXT_CLK_2, EXT_CLK_3}
+	},
+	{SAI3_CLK_ROOT, IP_CLOCK_SLICE, 13,
+	 {OSC_24M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK,
+	  VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK,
+	  OSC_HDMI_CLK, EXT_CLK_3, EXT_CLK_4}
+	},
+	{SAI4_CLK_ROOT, IP_CLOCK_SLICE, 14,
+	 {OSC_24M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK,
+	  VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK,
+	  OSC_HDMI_CLK, EXT_CLK_1, EXT_CLK_2}
+	},
+	{SAI5_CLK_ROOT, IP_CLOCK_SLICE, 15,
+	 {OSC_24M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK,
+	  VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK,
+	  OSC_HDMI_CLK, EXT_CLK_2, EXT_CLK_3}
+	},
+	{SAI6_CLK_ROOT, IP_CLOCK_SLICE, 16,
+	 {OSC_24M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK,
+	  VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK,
+	  OSC_HDMI_CLK, EXT_CLK_3, EXT_CLK_4}
+	},
+	{SPDIF1_CLK_ROOT, IP_CLOCK_SLICE, 17,
+	 {OSC_24M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK,
+	  VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK,
+	  OSC_HDMI_CLK, EXT_CLK_2, EXT_CLK_3}
+	},
+	{SPDIF2_CLK_ROOT, IP_CLOCK_SLICE, 18,
+	 {OSC_24M_CLK, AUDIO_PLL1_CLK, AUDIO_PLL2_CLK,
+	  VIDEO_PLL_CLK, SYSTEM_PLL1_133M_CLK,
+	  OSC_HDMI_CLK, EXT_CLK_3, EXT_CLK_4}
+	},
+	{ENET_REF_CLK_ROOT, IP_CLOCK_SLICE, 19,
+	 {OSC_24M_CLK, SYSTEM_PLL2_125M_CLK, SYSTEM_PLL2_50M_CLK,
+	  SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_160M_CLK,
+	  AUDIO_PLL1_CLK, VIDEO_PLL_CLK, EXT_CLK_4}
+	},
+	{ENET_TIMER_CLK_ROOT, IP_CLOCK_SLICE, 20,
+	 {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, AUDIO_PLL1_CLK,
+	  EXT_CLK_1, EXT_CLK_2, EXT_CLK_3, EXT_CLK_4,
+	  VIDEO_PLL_CLK}
+	},
+	{ENET_PHY_REF_CLK_ROOT, IP_CLOCK_SLICE, 21,
+	 {OSC_24M_CLK, SYSTEM_PLL2_50M_CLK, SYSTEM_PLL2_125M_CLK,
+	  SYSTEM_PLL2_200M_CLK, SYSTEM_PLL2_500M_CLK,
+	  AUDIO_PLL1_CLK, VIDEO_PLL_CLK, AUDIO_PLL2_CLK}
+	},
+	{NAND_CLK_ROOT, IP_CLOCK_SLICE, 22,
+	 {OSC_24M_CLK, SYSTEM_PLL2_500M_CLK, AUDIO_PLL1_CLK,
+	  SYSTEM_PLL1_400M_CLK, AUDIO_PLL2_CLK, SYSTEM_PLL3_CLK,
+	  SYSTEM_PLL2_250M_CLK, VIDEO_PLL_CLK}
+	},
+	{QSPI_CLK_ROOT, IP_CLOCK_SLICE, 23,
+	 {OSC_24M_CLK, SYSTEM_PLL1_400M_CLK, SYSTEM_PLL2_333M_CLK,
+	  SYSTEM_PLL2_500M_CLK, AUDIO_PLL2_CLK,
+	  SYSTEM_PLL1_266M_CLK, SYSTEM_PLL3_CLK, SYSTEM_PLL1_100M_CLK}
+	},
+	{USDHC1_CLK_ROOT, IP_CLOCK_SLICE, 24,
+	 {OSC_24M_CLK, SYSTEM_PLL1_400M_CLK, SYSTEM_PLL1_800M_CLK,
+	  SYSTEM_PLL2_500M_CLK, SYSTEM_PLL3_CLK,
+	  SYSTEM_PLL1_266M_CLK, AUDIO_PLL2_CLK, SYSTEM_PLL1_100M_CLK}
+	},
+	{USDHC2_CLK_ROOT, IP_CLOCK_SLICE, 25,
+	 {OSC_24M_CLK, SYSTEM_PLL1_400M_CLK, SYSTEM_PLL1_800M_CLK,
+	  SYSTEM_PLL2_500M_CLK, SYSTEM_PLL3_CLK,
+	  SYSTEM_PLL1_266M_CLK, AUDIO_PLL2_CLK, SYSTEM_PLL1_100M_CLK}
+	},
+	{I2C1_CLK_ROOT, IP_CLOCK_SLICE, 26,
+	 {OSC_24M_CLK, SYSTEM_PLL1_160M_CLK, SYSTEM_PLL2_50M_CLK,
+	  SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK,
+	  AUDIO_PLL2_CLK, SYSTEM_PLL1_133M_CLK}
+	},
+	{I2C2_CLK_ROOT, IP_CLOCK_SLICE, 27,
+	 {OSC_24M_CLK, SYSTEM_PLL1_160M_CLK, SYSTEM_PLL2_50M_CLK,
+	  SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK,
+	  AUDIO_PLL2_CLK, SYSTEM_PLL1_133M_CLK}
+	},
+	{I2C3_CLK_ROOT, IP_CLOCK_SLICE, 28,
+	 {OSC_24M_CLK, SYSTEM_PLL1_160M_CLK, SYSTEM_PLL2_50M_CLK,
+	  SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK,
+	  AUDIO_PLL2_CLK, SYSTEM_PLL1_133M_CLK}
+	},
+	{I2C4_CLK_ROOT, IP_CLOCK_SLICE, 29,
+	 {OSC_24M_CLK, SYSTEM_PLL1_160M_CLK, SYSTEM_PLL2_50M_CLK,
+	  SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK, VIDEO_PLL_CLK,
+	  AUDIO_PLL2_CLK, SYSTEM_PLL1_133M_CLK}
+	},
+	{UART1_CLK_ROOT, IP_CLOCK_SLICE, 30,
+	 {OSC_24M_CLK, SYSTEM_PLL1_80M_CLK, SYSTEM_PLL2_200M_CLK,
+	  SYSTEM_PLL2_100M_CLK, SYSTEM_PLL3_CLK,
+	  EXT_CLK_2, EXT_CLK_4, AUDIO_PLL2_CLK}
+	},
+	{UART2_CLK_ROOT, IP_CLOCK_SLICE, 31,
+	 {OSC_24M_CLK, SYSTEM_PLL1_80M_CLK, SYSTEM_PLL2_200M_CLK,
+	  SYSTEM_PLL2_100M_CLK, SYSTEM_PLL3_CLK,
+	  EXT_CLK_2, EXT_CLK_3, AUDIO_PLL2_CLK}
+	},
+	{UART3_CLK_ROOT, IP_CLOCK_SLICE, 32,
+	 {OSC_24M_CLK, SYSTEM_PLL1_80M_CLK, SYSTEM_PLL2_200M_CLK,
+	  SYSTEM_PLL2_100M_CLK, SYSTEM_PLL3_CLK,
+	  EXT_CLK_2, EXT_CLK_4, AUDIO_PLL2_CLK}
+	},
+	{UART4_CLK_ROOT, IP_CLOCK_SLICE, 33,
+	 {OSC_24M_CLK, SYSTEM_PLL1_80M_CLK, SYSTEM_PLL2_200M_CLK,
+	  SYSTEM_PLL2_100M_CLK, SYSTEM_PLL3_CLK,
+	  EXT_CLK_2, EXT_CLK_3, AUDIO_PLL2_CLK}
+	},
+	{USB_CORE_REF_CLK_ROOT, IP_CLOCK_SLICE, 34,
+	 {OSC_24M_CLK, SYSTEM_PLL1_100M_CLK, SYSTEM_PLL1_40M_CLK,
+	  SYSTEM_PLL2_100M_CLK, SYSTEM_PLL2_200M_CLK,
+	  EXT_CLK_2, EXT_CLK_3, AUDIO_PLL2_CLK}
+	},
+	{USB_PHY_REF_CLK_ROOT, IP_CLOCK_SLICE, 35,
+	 {OSC_24M_CLK, SYSTEM_PLL1_100M_CLK, SYSTEM_PLL1_40M_CLK,
+	  SYSTEM_PLL2_100M_CLK, SYSTEM_PLL2_200M_CLK,
+	  EXT_CLK_2, EXT_CLK_3, AUDIO_PLL2_CLK}
+	},
+	{GIC_CLK_ROOT, IP_CLOCK_SLICE, 36,
+	 {OSC_24M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_40M_CLK,
+	  SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_800M_CLK,
+	  EXT_CLK_2, EXT_CLK_4, AUDIO_PLL2_CLK}
+	},
+	{ECSPI1_CLK_ROOT, IP_CLOCK_SLICE, 37,
+	 {OSC_24M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_40M_CLK,
+	  SYSTEM_PLL1_160M_CLK, SYSTEM_PLL1_800M_CLK,
+	  SYSTEM_PLL3_CLK, SYSTEM_PLL2_250M_CLK, AUDIO_PLL2_CLK}
+	},
+	{ECSPI2_CLK_ROOT, IP_CLOCK_SLICE, 38,
+	 {OSC_24M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_40M_CLK,
+	  SYSTEM_PLL1_160M_CLK, SYSTEM_PLL1_800M_CLK,
+	  SYSTEM_PLL3_CLK, SYSTEM_PLL2_250M_CLK, AUDIO_PLL2_CLK}
+	},
+	{PWM1_CLK_ROOT, IP_CLOCK_SLICE, 39,
+	 {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_160M_CLK,
+	  SYSTEM_PLL1_40M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_1,
+	  SYSTEM_PLL1_80M_CLK, VIDEO_PLL_CLK}
+	},
+	{PWM2_CLK_ROOT, IP_CLOCK_SLICE, 40,
+	 {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_160M_CLK,
+	  SYSTEM_PLL1_40M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_1,
+	  SYSTEM_PLL1_80M_CLK, VIDEO_PLL_CLK}
+	},
+	{PWM3_CLK_ROOT, IP_CLOCK_SLICE, 41,
+	 {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_160M_CLK,
+	  SYSTEM_PLL1_40M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_2,
+	  SYSTEM_PLL1_80M_CLK, VIDEO_PLL_CLK}
+	},
+	{PWM4_CLK_ROOT, IP_CLOCK_SLICE, 42,
+	 {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_160M_CLK,
+	  SYSTEM_PLL1_40M_CLK, SYSTEM_PLL3_CLK, EXT_CLK_2,
+	  SYSTEM_PLL1_80M_CLK, VIDEO_PLL_CLK}
+	},
+	{GPT1_CLK_ROOT, IP_CLOCK_SLICE, 43,
+	 {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_400M_CLK,
+	  SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK,
+	  SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_1}
+	},
+	{GPT2_CLK_ROOT, IP_CLOCK_SLICE, 44,
+	 {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_400M_CLK,
+	  SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK,
+	  SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_2}
+	},
+	{GPT3_CLK_ROOT, IP_CLOCK_SLICE, 45,
+	 {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_400M_CLK,
+	  SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK,
+	  SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_3}
+	},
+	{GPT4_CLK_ROOT, IP_CLOCK_SLICE, 46,
+	 {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_400M_CLK,
+	  SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK,
+	  SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_1}
+	},
+	{GPT5_CLK_ROOT, IP_CLOCK_SLICE, 47,
+	 {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_400M_CLK,
+	  SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK,
+	  SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_2}
+	},
+	{GPT6_CLK_ROOT, IP_CLOCK_SLICE, 48,
+	 {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_400M_CLK,
+	  SYSTEM_PLL1_40M_CLK, VIDEO_PLL_CLK,
+	  SYSTEM_PLL1_80M_CLK, AUDIO_PLL1_CLK, EXT_CLK_3}
+	},
+	{TRACE_CLK_ROOT, IP_CLOCK_SLICE, 49,
+	 {OSC_24M_CLK, SYSTEM_PLL1_133M_CLK, SYSTEM_PLL1_160M_CLK,
+	  VPU_PLL_CLK, SYSTEM_PLL2_125M_CLK,
+	  SYSTEM_PLL3_CLK, EXT_CLK_1, EXT_CLK_3}
+	},
+	{WDOG_CLK_ROOT, IP_CLOCK_SLICE, 50,
+	 {OSC_24M_CLK, SYSTEM_PLL1_133M_CLK, SYSTEM_PLL1_160M_CLK,
+	  VPU_PLL_CLK, SYSTEM_PLL2_125M_CLK,
+	  SYSTEM_PLL3_CLK, SYSTEM_PLL1_80M_CLK, SYSTEM_PLL2_166M_CLK}
+	},
+	{WRCLK_CLK_ROOT, IP_CLOCK_SLICE, 51,
+	 {OSC_24M_CLK, SYSTEM_PLL1_40M_CLK, VPU_PLL_CLK,
+	  SYSTEM_PLL3_CLK, SYSTEM_PLL2_200M_CLK,
+	  SYSTEM_PLL1_266M_CLK, SYSTEM_PLL2_500M_CLK, SYSTEM_PLL1_100M_CLK}
+	},
+	{IPP_DO_CLKO1, IP_CLOCK_SLICE, 52,
+	 {OSC_24M_CLK, SYSTEM_PLL1_800M_CLK, OSC_HDMI_CLK,
+	  SYSTEM_PLL1_200M_CLK, AUDIO_PLL2_CLK,
+	  SYSTEM_PLL2_500M_CLK, VPU_PLL_CLK, SYSTEM_PLL1_80M_CLK}
+	},
+	{IPP_DO_CLKO2, IP_CLOCK_SLICE, 53,
+	 {OSC_24M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_400M_CLK,
+	  SYSTEM_PLL2_166M_CLK, SYSTEM_PLL3_CLK,
+	  AUDIO_PLL1_CLK, VIDEO_PLL_CLK, OSC_32K_CLK}
+	},
+	{MIPI_DSI_CORE_CLK_ROOT, IP_CLOCK_SLICE, 54,
+	 {OSC_24M_CLK, SYSTEM_PLL1_266M_CLK, SYSTEM_PLL2_250M_CLK,
+	  SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
+	  SYSTEM_PLL3_CLK, AUDIO_PLL2_CLK, VIDEO_PLL_CLK}
+	},
+	{MIPI_DSI_PHY_REF_CLK_ROOT, IP_CLOCK_SLICE, 55,
+	 {OSC_24M_CLK, SYSTEM_PLL2_125M_CLK, SYSTEM_PLL2_100M_CLK,
+	  SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
+	  EXT_CLK_2, AUDIO_PLL2_CLK, VIDEO_PLL_CLK}
+	},
+	{MIPI_DSI_DBI_CLK_ROOT, IP_CLOCK_SLICE, 56,
+	 {OSC_24M_CLK, SYSTEM_PLL1_266M_CLK, SYSTEM_PLL2_100M_CLK,
+	  SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
+	  SYSTEM_PLL3_CLK, AUDIO_PLL2_CLK, VIDEO_PLL_CLK}
+	},
+	{USDHC3_CLK_ROOT, IP_CLOCK_SLICE, 57,
+	 {OSC_24M_CLK, SYSTEM_PLL1_400M_CLK, SYSTEM_PLL1_800M_CLK,
+	  SYSTEM_PLL2_500M_CLK, SYSTEM_PLL3_CLK,
+	  SYSTEM_PLL1_266M_CLK, AUDIO_PLL2_CLK, SYSTEM_PLL1_100M_CLK}
+	},
+	{MIPI_CSI1_CORE_CLK_ROOT, IP_CLOCK_SLICE, 58,
+	 {OSC_24M_CLK, SYSTEM_PLL1_266M_CLK, SYSTEM_PLL2_250M_CLK,
+	  SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
+	  SYSTEM_PLL3_CLK, AUDIO_PLL2_CLK, VIDEO_PLL_CLK}
+	},
+	{MIPI_CSI1_PHY_REF_CLK_ROOT, IP_CLOCK_SLICE, 59,
+	 {OSC_24M_CLK, SYSTEM_PLL2_333M_CLK, SYSTEM_PLL2_100M_CLK,
+	  SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
+	  EXT_CLK_2, AUDIO_PLL2_CLK, VIDEO_PLL_CLK}
+	},
+	{MIPI_CSI1_ESC_CLK_ROOT, IP_CLOCK_SLICE, 60,
+	 {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_80M_CLK,
+	  SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
+	  SYSTEM_PLL3_CLK, EXT_CLK_3, AUDIO_PLL2_CLK}
+	},
+	{MIPI_CSI2_CORE_CLK_ROOT, IP_CLOCK_SLICE, 61,
+	 {OSC_24M_CLK, SYSTEM_PLL1_266M_CLK, SYSTEM_PLL2_250M_CLK,
+	  SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
+	  SYSTEM_PLL3_CLK, AUDIO_PLL2_CLK, VIDEO_PLL_CLK}
+	},
+	{MIPI_CSI2_PHY_REF_CLK_ROOT, IP_CLOCK_SLICE, 62,
+	 {OSC_24M_CLK, SYSTEM_PLL2_333M_CLK, SYSTEM_PLL2_100M_CLK,
+	  SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
+	  EXT_CLK_2, AUDIO_PLL2_CLK, VIDEO_PLL_CLK}
+	},
+	{MIPI_CSI2_ESC_CLK_ROOT, IP_CLOCK_SLICE, 63,
+	 {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL1_80M_CLK,
+	  SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
+	  SYSTEM_PLL3_CLK, EXT_CLK_3, AUDIO_PLL2_CLK}
+	},
+	{PCIE2_CTRL_CLK_ROOT, IP_CLOCK_SLICE, 64,
+	 {OSC_24M_CLK, SYSTEM_PLL2_250M_CLK, SYSTEM_PLL2_200M_CLK,
+	  SYSTEM_PLL1_266M_CLK, SYSTEM_PLL1_800M_CLK,
+	  SYSTEM_PLL2_500M_CLK, SYSTEM_PLL2_333M_CLK, SYSTEM_PLL3_CLK}
+	},
+	{PCIE2_PHY_CLK_ROOT, IP_CLOCK_SLICE, 65,
+	 {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, SYSTEM_PLL2_500M_CLK,
+	  EXT_CLK_1, EXT_CLK_2, EXT_CLK_3,
+	  EXT_CLK_4, SYSTEM_PLL1_400M_CLK}
+	},
+	{PCIE2_AUX_CLK_ROOT, IP_CLOCK_SLICE, 66,
+	 {OSC_24M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL2_50M_CLK,
+	  SYSTEM_PLL3_CLK, SYSTEM_PLL2_100M_CLK,
+	  SYSTEM_PLL1_80M_CLK, SYSTEM_PLL1_160M_CLK, SYSTEM_PLL1_200M_CLK}
+	},
+	{ECSPI3_CLK_ROOT, IP_CLOCK_SLICE, 67,
+	 {OSC_24M_CLK, SYSTEM_PLL2_200M_CLK, SYSTEM_PLL1_40M_CLK,
+	  SYSTEM_PLL1_160M_CLK, SYSTEM_PLL1_800M_CLK,
+	  SYSTEM_PLL3_CLK, SYSTEM_PLL2_250M_CLK, AUDIO_PLL2_CLK}
+	},
+	{PDM_CLK_ROOT, IP_CLOCK_SLICE, 68,
+	 {OSC_24M_CLK, SYSTEM_PLL2_100M_CLK, AUDIO_PLL1_CLK,
+	  SYSTEM_PLL1_800M_CLK, SYSTEM_PLL2_1000M_CLK,
+	  SYSTEM_PLL3_CLK, EXT_CLK_3, AUDIO_PLL2_CLK},
+	},
+	{VPU_H1_CLK_ROOT, IP_CLOCK_SLICE, 69,
+	 {OSC_24M_CLK, VPU_PLL_CLK, SYSTEM_PLL1_800M_CLK,
+	  SYSTEM_PLL2_1000M_CLK, AUDIO_PLL2_CLK,
+	  SYSTEM_PLL2_125M_CLK, SYSTEM_PLL3_CLK, AUDIO_PLL1_CLK}
+	},
+	{DRAM_SEL_CFG, DRAM_SEL_CLOCK_SLICE, 0,
+	 {DRAM_PLL1_CLK}
+	},
+	{CORE_SEL_CFG, CORE_SEL_CLOCK_SLICE, 0,
+	 {DRAM_PLL1_CLK}
+	},
+};
+#endif
 
 static int select(enum clk_root_index clock_id)
 {
-- 
2.16.4

[U-Boot] [i.MX8MM+CCF 28/41] imx8m: soc: probe clk before relocation

[Peng Fan]

probe clk device before relocation to get cpu clk.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 arch/arm/mach-imx/imx8m/soc.c | 21 +++++++++++++++++++++
 1 file changed, 21 insertions(+)

diff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/mach-imx/imx8m/soc.c
index 42b99945b4..07cda86bdd 100644
--- a/arch/arm/mach-imx/imx8m/soc.c
+++ b/arch/arm/mach-imx/imx8m/soc.c
@@ -14,6 +14,10 @@
 #include <asm/mach-imx/boot_mode.h>
 #include <asm/mach-imx/syscounter.h>
 #include <asm/armv8/mmu.h>
+#include <dm/uclass.h>
+#include <dm/device.h>
+#include <dm/uclass-internal.h>
+#include <dm/device-internal.h>
 #include <errno.h>
 #include <fdt_support.h>
 #include <fsl_wdog.h>
@@ -277,3 +281,20 @@ void reset_cpu(ulong addr)
 		 */
 	}
 }
+
+/* TODO: Add i.MX8MQ */
+#ifdef CONFIG_IMX8MM
+int arch_cpu_init_dm(void)
+{
+	struct udevice *dev;
+
+	uclass_find_first_device(UCLASS_CLK, &dev);
+
+	for (; dev; uclass_find_next_device(&dev)) {
+		if (device_probe(dev))
+			continue;
+	}
+
+	return 0;
+}
+#endif
-- 
2.16.4

[U-Boot] [i.MX8MM+CCF 29/41] imx8m: add pin header for i.MX8MM

[Peng Fan]

Add pin header file for i.MX8MM

To IMX8MM_PAD_NAND_WE_B_USDHC3_CLK, IOMUX_CONFIG_SION needs to be
selected.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 arch/arm/include/asm/arch-imx8m/imx8mm_pins.h | 691 ++++++++++++++++++++++++++
 1 file changed, 691 insertions(+)
 create mode 100644 arch/arm/include/asm/arch-imx8m/imx8mm_pins.h

diff --git a/arch/arm/include/asm/arch-imx8m/imx8mm_pins.h b/arch/arm/include/asm/arch-imx8m/imx8mm_pins.h
new file mode 100644
index 0000000000..210e96e1db
--- /dev/null
+++ b/arch/arm/include/asm/arch-imx8m/imx8mm_pins.h
@@ -0,0 +1,691 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2018-2019 NXP
+ */
+
+#ifndef __ASM_ARCH_IMX8MM_PINS_H__
+#define __ASM_ARCH_IMX8MM_PINS_H__
+
+#include <asm/mach-imx/iomux-v3.h>
+
+enum {
+	IMX8MM_PAD_GPIO1_IO00_GPIO1_IO0                               =  IOMUX_PAD(0x0290, 0x0028, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_GPIO1_IO00_CCM_ENET_PHY_REF_CLK_ROOT               =  IOMUX_PAD(0x0290, 0x0028, 1, 0x0000, 0, 0),
+	IMX8MM_PAD_GPIO1_IO00_XTALOSC_REF_CLK_32K                     =  IOMUX_PAD(0x0290, 0x0028, 5, 0x0000, 0, 0),
+	IMX8MM_PAD_GPIO1_IO00_CCM_EXT_CLK1                            =  IOMUX_PAD(0x0290, 0x0028, 6, 0x0000, 0, 0),
+
+	IMX8MM_PAD_GPIO1_IO01_GPIO1_IO1                               =  IOMUX_PAD(0x0294, 0x002C, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_GPIO1_IO01_PWM1_OUT                                =  IOMUX_PAD(0x0294, 0x002C, 1, 0x0000, 0, 0),
+	IMX8MM_PAD_GPIO1_IO01_XTALOSC_REF_CLK_24M                     =  IOMUX_PAD(0x0294, 0x002C, 5, 0x0000, 0, 0),
+	IMX8MM_PAD_GPIO1_IO01_CCM_EXT_CLK2                            =  IOMUX_PAD(0x0294, 0x002C, 6, 0x0000, 0, 0),
+
+	IMX8MM_PAD_GPIO1_IO02_GPIO1_IO2                               =  IOMUX_PAD(0x0298, 0x0030, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B                            =  IOMUX_PAD(0x0298, 0x0030, 1, 0x0000, 0, 0),
+	IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_ANY                          =  IOMUX_PAD(0x0298, 0x0030, 5, 0x0000, 0, 0),
+
+	IMX8MM_PAD_GPIO1_IO03_GPIO1_IO3                               =  IOMUX_PAD(0x029C, 0x0034, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_GPIO1_IO03_USDHC1_VSELECT                          =  IOMUX_PAD(0x029C, 0x0034, 1, 0x0000, 0, 0),
+	IMX8MM_PAD_GPIO1_IO03_SDMA1_EXT_EVENT0                        =  IOMUX_PAD(0x029C, 0x0034, 5, 0x0000, 0, 0),
+
+	IMX8MM_PAD_GPIO1_IO04_GPIO1_IO4                               =  IOMUX_PAD(0x02A0, 0x0038, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_GPIO1_IO04_USDHC2_VSELECT                          =  IOMUX_PAD(0x02A0, 0x0038, 1, 0x0000, 0, 0),
+	IMX8MM_PAD_GPIO1_IO04_SDMA1_EXT_EVENT1                        =  IOMUX_PAD(0x02A0, 0x0038, 5, 0x0000, 0, 0),
+
+	IMX8MM_PAD_GPIO1_IO05_GPIO1_IO5                               =  IOMUX_PAD(0x02A4, 0x003C, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_GPIO1_IO05_ARM_PLATFORM_M4_NMI                     =  IOMUX_PAD(0x02A4, 0x003C, 1, 0x0000, 0, 0),
+	IMX8MM_PAD_GPIO1_IO05_CCM_PMIC_READY                          =  IOMUX_PAD(0x02A4, 0x003C, 5, 0x04BC, 0, 0),
+	IMX8MM_PAD_GPIO1_IO05_SRC_INT_BOOT                            =  IOMUX_PAD(0x02A4, 0x003C, 6, 0x0000, 0, 0),
+
+	IMX8MM_PAD_GPIO1_IO06_GPIO1_IO6                               =  IOMUX_PAD(0x02A8, 0x0040, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_GPIO1_IO06_ENET1_MDC                               =  IOMUX_PAD(0x02A8, 0x0040, 1, 0x0000, 0, 0),
+	IMX8MM_PAD_GPIO1_IO06_USDHC1_CD_B                             =  IOMUX_PAD(0x02A8, 0x0040, 5, 0x0000, 0, 0),
+	IMX8MM_PAD_GPIO1_IO06_CCM_EXT_CLK3                            =  IOMUX_PAD(0x02A8, 0x0040, 6, 0x0000, 0, 0),
+
+	IMX8MM_PAD_GPIO1_IO07_GPIO1_IO7                               =  IOMUX_PAD(0x02AC, 0x0044, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_GPIO1_IO07_ENET1_MDIO                              =  IOMUX_PAD(0x02AC, 0x0044, 1, 0x04C0, 0, 0),
+	IMX8MM_PAD_GPIO1_IO07_USDHC1_WP                               =  IOMUX_PAD(0x02AC, 0x0044, 5, 0x0000, 0, 0),
+	IMX8MM_PAD_GPIO1_IO07_CCM_EXT_CLK4                            =  IOMUX_PAD(0x02AC, 0x0044, 6, 0x0000, 0, 0),
+
+	IMX8MM_PAD_GPIO1_IO08_GPIO1_IO8                               =  IOMUX_PAD(0x02B0, 0x0048, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_GPIO1_IO08_ENET1_1588_EVENT0_IN                    =  IOMUX_PAD(0x02B0, 0x0048, 1, 0x0000, 0, 0),
+	IMX8MM_PAD_GPIO1_IO08_USDHC2_RESET_B                          =  IOMUX_PAD(0x02B0, 0x0048, 5, 0x0000, 0, 0),
+	IMX8MM_PAD_GPIO1_IO08_CCM_WAIT                                =  IOMUX_PAD(0x02B0, 0x0048, 6, 0x0000, 0, 0),
+
+	IMX8MM_PAD_GPIO1_IO09_GPIO1_IO9                               =  IOMUX_PAD(0x02B4, 0x004C, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_GPIO1_IO09_ENET1_1588_EVENT0_OUT                   =  IOMUX_PAD(0x02B4, 0x004C, 1, 0x0000, 0, 0),
+	IMX8MM_PAD_GPIO1_IO09_USDHC3_RESET_B                          =  IOMUX_PAD(0x02B4, 0x004C, 4, 0x0000, 0, 0),
+	IMX8MM_PAD_GPIO1_IO09_SDMA2_EXT_EVENT0                        =  IOMUX_PAD(0x02B4, 0x004C, 5, 0x0000, 0, 0),
+	IMX8MM_PAD_GPIO1_IO09_CCM_STOP                                =  IOMUX_PAD(0x02B4, 0x004C, 6, 0x0000, 0, 0),
+
+	IMX8MM_PAD_GPIO1_IO10_GPIO1_IO10                              =  IOMUX_PAD(0x02B8, 0x0050, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_GPIO1_IO10_USB1_OTG_ID                             =  IOMUX_PAD(0x02B8, 0x0050, 1, 0x0000, 0, 0),
+
+	IMX8MM_PAD_GPIO1_IO11_GPIO1_IO11                              =  IOMUX_PAD(0x02BC, 0x0054, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_GPIO1_IO11_USB2_OTG_ID                             =  IOMUX_PAD(0x02BC, 0x0054, 1, 0x0000, 0, 0),
+	IMX8MM_PAD_GPIO1_IO11_USDHC3_VSELECT                          =  IOMUX_PAD(0x02BC, 0x0054, 4, 0x0000, 0, 0),
+	IMX8MM_PAD_GPIO1_IO11_CCM_PMIC_READY                          =  IOMUX_PAD(0x02BC, 0x0054, 5, 0x04BC, 1, 0),
+	IMX8MM_PAD_GPIO1_IO11_CCM_OUT0                                =  IOMUX_PAD(0x02BC, 0x0054, 6, 0x0000, 0, 0),
+
+	IMX8MM_PAD_GPIO1_IO12_GPIO1_IO12                              =  IOMUX_PAD(0x02C0, 0x0058, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_GPIO1_IO12_USB1_OTG_PWR                            =  IOMUX_PAD(0x02C0, 0x0058, 1, 0x0000, 0, 0),
+	IMX8MM_PAD_GPIO1_IO12_SDMA2_EXT_EVENT1                        =  IOMUX_PAD(0x02C0, 0x0058, 5, 0x0000, 0, 0),
+	IMX8MM_PAD_GPIO1_IO12_CCM_OUT1                                =  IOMUX_PAD(0x02C0, 0x0058, 6, 0x0000, 0, 0),
+
+	IMX8MM_PAD_GPIO1_IO13_GPIO1_IO13                              =  IOMUX_PAD(0x02C4, 0x005C, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_GPIO1_IO13_USB1_OTG_OC                             =  IOMUX_PAD(0x02C4, 0x005C, 1, 0x0000, 0, 0),
+	IMX8MM_PAD_GPIO1_IO13_PWM2_OUT                                =  IOMUX_PAD(0x02C4, 0x005C, 5, 0x0000, 0, 0),
+	IMX8MM_PAD_GPIO1_IO13_CCM_OUT2                                =  IOMUX_PAD(0x02C4, 0x005C, 6, 0x0000, 0, 0),
+
+	IMX8MM_PAD_GPIO1_IO14_GPIO1_IO14                              =  IOMUX_PAD(0x02C8, 0x0060, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_GPIO1_IO14_USB2_OTG_PWR                            =  IOMUX_PAD(0x02C8, 0x0060, 1, 0x0000, 0, 0),
+	IMX8MM_PAD_GPIO1_IO14_USDHC3_CD_B                             =  IOMUX_PAD(0x02C8, 0x0060, 4, 0x0544, 2, 0),
+	IMX8MM_PAD_GPIO1_IO14_PWM3_OUT                                =  IOMUX_PAD(0x02C8, 0x0060, 5, 0x0000, 0, 0),
+	IMX8MM_PAD_GPIO1_IO14_CCM_CLKO1                               =  IOMUX_PAD(0x02C8, 0x0060, 6, 0x0000, 0, 0),
+
+	IMX8MM_PAD_GPIO1_IO15_GPIO1_IO15                              =  IOMUX_PAD(0x02CC, 0x0064, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_GPIO1_IO15_USB2_OTG_OC                             =  IOMUX_PAD(0x02CC, 0x0064, 1, 0x0000, 0, 0),
+	IMX8MM_PAD_GPIO1_IO15_USDHC3_WP                               =  IOMUX_PAD(0x02CC, 0x0064, 4, 0x0548, 2, 0),
+	IMX8MM_PAD_GPIO1_IO15_PWM4_OUT                                =  IOMUX_PAD(0x02CC, 0x0064, 5, 0x0000, 0, 0),
+	IMX8MM_PAD_GPIO1_IO15_CCM_CLKO2                               =  IOMUX_PAD(0x02CC, 0x0064, 6, 0x0000, 0, 0),
+
+	IMX8MM_PAD_ENET_MDC_ENET1_MDC                                 =  IOMUX_PAD(0x02D0, 0x0068, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_ENET_MDC_GPIO1_IO16                                =  IOMUX_PAD(0x02D0, 0x0068, 5, 0x0000, 0, 0),
+
+	IMX8MM_PAD_ENET_MDIO_ENET1_MDIO                               =  IOMUX_PAD(0x02D4, 0x006C, 0, 0x04C0, 1, 0),
+	IMX8MM_PAD_ENET_MDIO_GPIO1_IO17                               =  IOMUX_PAD(0x02D4, 0x006C, 5, 0x0000, 0, 0),
+
+	IMX8MM_PAD_ENET_TD3_ENET1_RGMII_TD3                           =  IOMUX_PAD(0x02D8, 0x0070, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_ENET_TD3_GPIO1_IO18                                =  IOMUX_PAD(0x02D8, 0x0070, 5, 0x0000, 0, 0),
+
+	IMX8MM_PAD_ENET_TD2_ENET1_RGMII_TD2                           =  IOMUX_PAD(0x02DC, 0x0074, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_ENET_TD2_ENET1_TX_CLK                              =  IOMUX_PAD(0x02DC, 0x0074, 1, 0x0000, 0, 0),
+	IMX8MM_PAD_ENET_TD2_CCM_ENET_REF_CLK_ROOT                     =  IOMUX_PAD(0x02DC, 0x0074, 1, 0x0000, 0, 0),
+	IMX8MM_PAD_ENET_TD2_GPIO1_IO19                                =  IOMUX_PAD(0x02DC, 0x0074, 5, 0x0000, 0, 0),
+
+	IMX8MM_PAD_ENET_TD1_ENET1_RGMII_TD1                           =  IOMUX_PAD(0x02E0, 0x0078, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_ENET_TD1_GPIO1_IO20                                =  IOMUX_PAD(0x02E0, 0x0078, 5, 0x0000, 0, 0),
+
+	IMX8MM_PAD_ENET_TD0_ENET1_RGMII_TD0                           =  IOMUX_PAD(0x02E4, 0x007C, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_ENET_TD0_GPIO1_IO21                                =  IOMUX_PAD(0x02E4, 0x007C, 5, 0x0000, 0, 0),
+
+	IMX8MM_PAD_ENET_TX_CTL_ENET1_RGMII_TX_CTL                     =  IOMUX_PAD(0x02E8, 0x0080, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_ENET_TX_CTL_GPIO1_IO22                             =  IOMUX_PAD(0x02E8, 0x0080, 5, 0x0000, 0, 0),
+
+	IMX8MM_PAD_ENET_TXC_ENET1_RGMII_TXC                           =  IOMUX_PAD(0x02EC, 0x0084, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_ENET_TXC_ENET1_TX_ER                               =  IOMUX_PAD(0x02EC, 0x0084, 1, 0x0000, 0, 0),
+	IMX8MM_PAD_ENET_TXC_GPIO1_IO23                                =  IOMUX_PAD(0x02EC, 0x0084, 5, 0x0000, 0, 0),
+
+	IMX8MM_PAD_ENET_RX_CTL_ENET1_RGMII_RX_CTL                     =  IOMUX_PAD(0x02F0, 0x0088, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_ENET_RX_CTL_GPIO1_IO24                             =  IOMUX_PAD(0x02F0, 0x0088, 5, 0x0000, 0, 0),
+
+	IMX8MM_PAD_ENET_RXC_ENET1_RGMII_RXC                           =  IOMUX_PAD(0x02F4, 0x008C, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_ENET_RXC_ENET1_RX_ER                               =  IOMUX_PAD(0x02F4, 0x008C, 1, 0x0000, 0, 0),
+	IMX8MM_PAD_ENET_RXC_GPIO1_IO25                                =  IOMUX_PAD(0x02F4, 0x008C, 5, 0x0000, 0, 0),
+
+	IMX8MM_PAD_ENET_RD0_ENET1_RGMII_RD0                           =  IOMUX_PAD(0x02F8, 0x0090, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_ENET_RD0_GPIO1_IO26                                =  IOMUX_PAD(0x02F8, 0x0090, 5, 0x0000, 0, 0),
+
+	IMX8MM_PAD_ENET_RD1_ENET1_RGMII_RD1                           =  IOMUX_PAD(0x02FC, 0x0094, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_ENET_RD1_GPIO1_IO27                                =  IOMUX_PAD(0x02FC, 0x0094, 5, 0x0000, 0, 0),
+
+	IMX8MM_PAD_ENET_RD2_ENET1_RGMII_RD2                           =  IOMUX_PAD(0x0300, 0x0098, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_ENET_RD2_GPIO1_IO28                                =  IOMUX_PAD(0x0300, 0x0098, 5, 0x0000, 0, 0),
+
+	IMX8MM_PAD_ENET_RD3_ENET1_RGMII_RD3                           =  IOMUX_PAD(0x0304, 0x009C, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_ENET_RD3_GPIO1_IO29                                =  IOMUX_PAD(0x0304, 0x009C, 5, 0x0000, 0, 0),
+
+	IMX8MM_PAD_SD1_CLK_USDHC1_CLK                                 =  IOMUX_PAD(0x0308, 0x00A0, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_SD1_CLK_GPIO2_IO0                                  =  IOMUX_PAD(0x0308, 0x00A0, 5, 0x0000, 0, 0),
+
+	IMX8MM_PAD_SD1_CMD_USDHC1_CMD                                 =  IOMUX_PAD(0x030C, 0x00A4, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_SD1_CMD_GPIO2_IO1                                  =  IOMUX_PAD(0x030C, 0x00A4, 5, 0x0000, 0, 0),
+
+	IMX8MM_PAD_SD1_DATA0_USDHC1_DATA0                             =  IOMUX_PAD(0x0310, 0x00A8, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_SD1_DATA0_GPIO2_IO2                                =  IOMUX_PAD(0x0310, 0x00A8, 5, 0x0000, 0, 0),
+
+	IMX8MM_PAD_SD1_DATA1_USDHC1_DATA1                             =  IOMUX_PAD(0x0314, 0x00AC, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_SD1_DATA1_GPIO2_IO3                                =  IOMUX_PAD(0x0314, 0x00AC, 5, 0x0000, 0, 0),
+
+	IMX8MM_PAD_SD1_DATA2_USDHC1_DATA2                             =  IOMUX_PAD(0x0318, 0x00B0, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_SD1_DATA2_GPIO2_IO4                                =  IOMUX_PAD(0x0318, 0x00B0, 5, 0x0000, 0, 0),
+
+	IMX8MM_PAD_SD1_DATA3_USDHC1_DATA3                             =  IOMUX_PAD(0x031C, 0x00B4, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_SD1_DATA3_GPIO2_IO5                                =  IOMUX_PAD(0x031C, 0x00B4, 5, 0x0000, 0, 0),
+
+	IMX8MM_PAD_SD1_DATA4_USDHC1_DATA4                             =  IOMUX_PAD(0x0320, 0x00B8, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_SD1_DATA4_GPIO2_IO6                                =  IOMUX_PAD(0x0320, 0x00B8, 5, 0x0000, 0, 0),
+
+	IMX8MM_PAD_SD1_DATA5_USDHC1_DATA5                             =  IOMUX_PAD(0x0324, 0x00BC, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_SD1_DATA5_GPIO2_IO7                                =  IOMUX_PAD(0x0324, 0x00BC, 5, 0x0000, 0, 0),
+
+	IMX8MM_PAD_SD1_DATA6_USDHC1_DATA6                             =  IOMUX_PAD(0x0328, 0x00C0, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_SD1_DATA6_GPIO2_IO8                                =  IOMUX_PAD(0x0328, 0x00C0, 5, 0x0000, 0, 0),
+
+	IMX8MM_PAD_SD1_DATA7_USDHC1_DATA7                             =  IOMUX_PAD(0x032C, 0x00C4, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_SD1_DATA7_GPIO2_IO9                                =  IOMUX_PAD(0x032C, 0x00C4, 5, 0x0000, 0, 0),
+
+	IMX8MM_PAD_SD1_RESET_B_USDHC1_RESET_B                         =  IOMUX_PAD(0x0330, 0x00C8, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_SD1_RESET_B_GPIO2_IO10                             =  IOMUX_PAD(0x0330, 0x00C8, 5, 0x0000, 0, 0),
+
+	IMX8MM_PAD_SD1_STROBE_USDHC1_STROBE                           =  IOMUX_PAD(0x0334, 0x00CC, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_SD1_STROBE_GPIO2_IO11                              =  IOMUX_PAD(0x0334, 0x00CC, 5, 0x0000, 0, 0),
+
+	IMX8MM_PAD_SD2_CD_B_USDHC2_CD_B                               =  IOMUX_PAD(0x0338, 0x00D0, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_SD2_CD_B_GPIO2_IO12                                =  IOMUX_PAD(0x0338, 0x00D0, 5, 0x0000, 0, 0),
+
+	IMX8MM_PAD_SD2_CLK_USDHC2_CLK                                 =  IOMUX_PAD(0x033C, 0x00D4, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_SD2_CLK_GPIO2_IO13                                 =  IOMUX_PAD(0x033C, 0x00D4, 5, 0x0000, 0, 0),
+	IMX8MM_PAD_SD2_CLK_CCM_OBSERVE0                               =  IOMUX_PAD(0x033C, 0x00D4, 6, 0x0000, 0, 0),
+
+	IMX8MM_PAD_SD2_CMD_USDHC2_CMD                                 =  IOMUX_PAD(0x0340, 0x00D8, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_SD2_CMD_GPIO2_IO14                                 =  IOMUX_PAD(0x0340, 0x00D8, 5, 0x0000, 0, 0),
+	IMX8MM_PAD_SD2_CMD_CCM_OBSERVE1                               =  IOMUX_PAD(0x0340, 0x00D8, 6, 0x0000, 0, 0),
+
+	IMX8MM_PAD_SD2_DATA0_USDHC2_DATA0                             =  IOMUX_PAD(0x0344, 0x00DC, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_SD2_DATA0_GPIO2_IO15                               =  IOMUX_PAD(0x0344, 0x00DC, 5, 0x0000, 0, 0),
+	IMX8MM_PAD_SD2_DATA0_CCM_OBSERVE2                             =  IOMUX_PAD(0x0344, 0x00DC, 6, 0x0000, 0, 0),
+
+	IMX8MM_PAD_SD2_DATA1_USDHC2_DATA1                             =  IOMUX_PAD(0x0348, 0x00E0, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_SD2_DATA1_GPIO2_IO16                               =  IOMUX_PAD(0x0348, 0x00E0, 5, 0x0000, 0, 0),
+	IMX8MM_PAD_SD2_DATA1_CCM_WAIT                                 =  IOMUX_PAD(0x0348, 0x00E0, 6, 0x0000, 0, 0),
+
+	IMX8MM_PAD_SD2_DATA2_USDHC2_DATA2                             =  IOMUX_PAD(0x034C, 0x00E4, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_SD2_DATA2_GPIO2_IO17                               =  IOMUX_PAD(0x034C, 0x00E4, 5, 0x0000, 0, 0),
+	IMX8MM_PAD_SD2_DATA2_CCM_STOP                                 =  IOMUX_PAD(0x034C, 0x00E4, 6, 0x0000, 0, 0),
+
+	IMX8MM_PAD_SD2_DATA3_USDHC2_DATA3                             =  IOMUX_PAD(0x0350, 0x00E8, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_SD2_DATA3_GPIO2_IO18                               =  IOMUX_PAD(0x0350, 0x00E8, 5, 0x0000, 0, 0),
+	IMX8MM_PAD_SD2_DATA3_SRC_EARLY_RESET                          =  IOMUX_PAD(0x0350, 0x00E8, 6, 0x0000, 0, 0),
+
+	IMX8MM_PAD_SD2_RESET_B_USDHC2_RESET_B                         =  IOMUX_PAD(0x0354, 0x00EC, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_SD2_RESET_B_GPIO2_IO19                             =  IOMUX_PAD(0x0354, 0x00EC, 5, 0x0000, 0, 0),
+	IMX8MM_PAD_SD2_RESET_B_SRC_SYSTEM_RESET                       =  IOMUX_PAD(0x0354, 0x00EC, 6, 0x0000, 0, 0),
+
+	IMX8MM_PAD_SD2_WP_USDHC2_WP                                   =  IOMUX_PAD(0x0358, 0x00F0, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_SD2_WP_GPIO2_IO20                                  =  IOMUX_PAD(0x0358, 0x00F0, 5, 0x0000, 0, 0),
+
+	IMX8MM_PAD_NAND_ALE_RAWNAND_ALE                               =  IOMUX_PAD(0x035C, 0x00F4, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_NAND_ALE_QSPI_A_SCLK                               =  IOMUX_PAD(0x035C, 0x00F4, 1, 0x0000, 0, 0),
+	IMX8MM_PAD_NAND_ALE_GPIO3_IO0                                 =  IOMUX_PAD(0x035C, 0x00F4, 5, 0x0000, 0, 0),
+
+	IMX8MM_PAD_NAND_CE0_B_RAWNAND_CE0_B                           =  IOMUX_PAD(0x0360, 0x00F8, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_NAND_CE0_B_QSPI_A_SS0_B                            =  IOMUX_PAD(0x0360, 0x00F8, 1, 0x0000, 0, 0),
+	IMX8MM_PAD_NAND_CE0_B_GPIO3_IO1                               =  IOMUX_PAD(0x0360, 0x00F8, 5, 0x0000, 0, 0),
+
+	IMX8MM_PAD_NAND_CE1_B_RAWNAND_CE1_B                           =  IOMUX_PAD(0x0364, 0x00FC, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_NAND_CE1_B_QSPI_A_SS1_B                            =  IOMUX_PAD(0x0364, 0x00FC, 1, 0x0000, 0, 0),
+	IMX8MM_PAD_NAND_CE1_B_USDHC3_STROBE                           =  IOMUX_PAD(0x0364, 0x00FC, 2, 0x0000, 0, 0),
+	IMX8MM_PAD_NAND_CE1_B_GPIO3_IO2                               =  IOMUX_PAD(0x0364, 0x00FC, 5, 0x0000, 0, 0),
+
+	IMX8MM_PAD_NAND_CE2_B_RAWNAND_CE2_B                           =  IOMUX_PAD(0x0368, 0x0100, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_NAND_CE2_B_QSPI_B_SS0_B                            =  IOMUX_PAD(0x0368, 0x0100, 1, 0x0000, 0, 0),
+	IMX8MM_PAD_NAND_CE2_B_USDHC3_DATA5                            =  IOMUX_PAD(0x0368, 0x0100, 2, 0x0000, 0, 0),
+	IMX8MM_PAD_NAND_CE2_B_GPIO3_IO3                               =  IOMUX_PAD(0x0368, 0x0100, 5, 0x0000, 0, 0),
+
+	IMX8MM_PAD_NAND_CE3_B_RAWNAND_CE3_B                           =  IOMUX_PAD(0x036C, 0x0104, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_NAND_CE3_B_QSPI_B_SS1_B                            =  IOMUX_PAD(0x036C, 0x0104, 1, 0x0000, 0, 0),
+	IMX8MM_PAD_NAND_CE3_B_USDHC3_DATA6                            =  IOMUX_PAD(0x036C, 0x0104, 2, 0x0000, 0, 0),
+	IMX8MM_PAD_NAND_CE3_B_GPIO3_IO4                               =  IOMUX_PAD(0x036C, 0x0104, 5, 0x0000, 0, 0),
+
+	IMX8MM_PAD_NAND_CLE_RAWNAND_CLE                               =  IOMUX_PAD(0x0370, 0x0108, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_NAND_CLE_QSPI_B_SCLK                               =  IOMUX_PAD(0x0370, 0x0108, 1, 0x0000, 0, 0),
+	IMX8MM_PAD_NAND_CLE_USDHC3_DATA7                              =  IOMUX_PAD(0x0370, 0x0108, 2, 0x0000, 0, 0),
+	IMX8MM_PAD_NAND_CLE_GPIO3_IO5                                 =  IOMUX_PAD(0x0370, 0x0108, 5, 0x0000, 0, 0),
+
+	IMX8MM_PAD_NAND_DATA00_RAWNAND_DATA00                         =  IOMUX_PAD(0x0374, 0x010C, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_NAND_DATA00_QSPI_A_DATA0                           =  IOMUX_PAD(0x0374, 0x010C, 1, 0x0000, 0, 0),
+	IMX8MM_PAD_NAND_DATA00_GPIO3_IO6                              =  IOMUX_PAD(0x0374, 0x010C, 5, 0x0000, 0, 0),
+
+	IMX8MM_PAD_NAND_DATA01_RAWNAND_DATA01                         =  IOMUX_PAD(0x0378, 0x0110, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_NAND_DATA01_QSPI_A_DATA1                           =  IOMUX_PAD(0x0378, 0x0110, 1, 0x0000, 0, 0),
+	IMX8MM_PAD_NAND_DATA01_GPIO3_IO7                              =  IOMUX_PAD(0x0378, 0x0110, 5, 0x0000, 0, 0),
+
+	IMX8MM_PAD_NAND_DATA02_RAWNAND_DATA02                         =  IOMUX_PAD(0x037C, 0x0114, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_NAND_DATA02_QSPI_A_DATA2                           =  IOMUX_PAD(0x037C, 0x0114, 1, 0x0000, 0, 0),
+	IMX8MM_PAD_NAND_DATA02_USDHC3_CD_B                            =  IOMUX_PAD(0x037C, 0x0114, 2, 0x0544, 0, 0),
+	IMX8MM_PAD_NAND_DATA02_GPIO3_IO8                              =  IOMUX_PAD(0x037C, 0x0114, 5, 0x0000, 0, 0),
+
+	IMX8MM_PAD_NAND_DATA03_RAWNAND_DATA03                         =  IOMUX_PAD(0x0380, 0x0118, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_NAND_DATA03_QSPI_A_DATA3                           =  IOMUX_PAD(0x0380, 0x0118, 1, 0x0000, 0, 0),
+	IMX8MM_PAD_NAND_DATA03_USDHC3_WP                              =  IOMUX_PAD(0x0380, 0x0118, 2, 0x0548, 0, 0),
+	IMX8MM_PAD_NAND_DATA03_GPIO3_IO9                              =  IOMUX_PAD(0x0380, 0x0118, 5, 0x0000, 0, 0),
+
+	IMX8MM_PAD_NAND_DATA04_RAWNAND_DATA04                         =  IOMUX_PAD(0x0384, 0x011C, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_NAND_DATA04_QSPI_B_DATA0                           =  IOMUX_PAD(0x0384, 0x011C, 1, 0x0000, 0, 0),
+	IMX8MM_PAD_NAND_DATA04_USDHC3_DATA0                           =  IOMUX_PAD(0x0384, 0x011C, 2, 0x0000, 0, 0),
+	IMX8MM_PAD_NAND_DATA04_GPIO3_IO10                             =  IOMUX_PAD(0x0384, 0x011C, 5, 0x0000, 0, 0),
+
+	IMX8MM_PAD_NAND_DATA05_RAWNAND_DATA05                         =  IOMUX_PAD(0x0388, 0x0120, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_NAND_DATA05_QSPI_B_DATA1                           =  IOMUX_PAD(0x0388, 0x0120, 1, 0x0000, 0, 0),
+	IMX8MM_PAD_NAND_DATA05_USDHC3_DATA1                           =  IOMUX_PAD(0x0388, 0x0120, 2, 0x0000, 0, 0),
+	IMX8MM_PAD_NAND_DATA05_GPIO3_IO11                             =  IOMUX_PAD(0x0388, 0x0120, 5, 0x0000, 0, 0),
+
+	IMX8MM_PAD_NAND_DATA06_RAWNAND_DATA06                         =  IOMUX_PAD(0x038C, 0x0124, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_NAND_DATA06_QSPI_B_DATA2                           =  IOMUX_PAD(0x038C, 0x0124, 1, 0x0000, 0, 0),
+	IMX8MM_PAD_NAND_DATA06_USDHC3_DATA2                           =  IOMUX_PAD(0x038C, 0x0124, 2, 0x0000, 0, 0),
+	IMX8MM_PAD_NAND_DATA06_GPIO3_IO12                             =  IOMUX_PAD(0x038C, 0x0124, 5, 0x0000, 0, 0),
+
+	IMX8MM_PAD_NAND_DATA07_RAWNAND_DATA07                         =  IOMUX_PAD(0x0390, 0x0128, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_NAND_DATA07_QSPI_B_DATA3                           =  IOMUX_PAD(0x0390, 0x0128, 1, 0x0000, 0, 0),
+	IMX8MM_PAD_NAND_DATA07_USDHC3_DATA3                           =  IOMUX_PAD(0x0390, 0x0128, 2, 0x0000, 0, 0),
+	IMX8MM_PAD_NAND_DATA07_GPIO3_IO13                             =  IOMUX_PAD(0x0390, 0x0128, 5, 0x0000, 0, 0),
+
+	IMX8MM_PAD_NAND_DQS_RAWNAND_DQS                               =  IOMUX_PAD(0x0394, 0x012C, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_NAND_DQS_QSPI_A_DQS                                =  IOMUX_PAD(0x0394, 0x012C, 1, 0x0000, 0, 0),
+	IMX8MM_PAD_NAND_DQS_GPIO3_IO14                                =  IOMUX_PAD(0x0394, 0x012C, 5, 0x0000, 0, 0),
+
+	IMX8MM_PAD_NAND_RE_B_RAWNAND_RE_B                             =  IOMUX_PAD(0x0398, 0x0130, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_NAND_RE_B_QSPI_B_DQS                               =  IOMUX_PAD(0x0398, 0x0130, 1, 0x0000, 0, 0),
+	IMX8MM_PAD_NAND_RE_B_USDHC3_DATA4                             =  IOMUX_PAD(0x0398, 0x0130, 2, 0x0000, 0, 0),
+	IMX8MM_PAD_NAND_RE_B_GPIO3_IO15                               =  IOMUX_PAD(0x0398, 0x0130, 5, 0x0000, 0, 0),
+
+	IMX8MM_PAD_NAND_READY_B_RAWNAND_READY_B                       =  IOMUX_PAD(0x039C, 0x0134, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_NAND_READY_B_USDHC3_RESET_B                        =  IOMUX_PAD(0x039C, 0x0134, 2, 0x0000, 0, 0),
+	IMX8MM_PAD_NAND_READY_B_GPIO3_IO16                            =  IOMUX_PAD(0x039C, 0x0134, 5, 0x0000, 0, 0),
+
+	IMX8MM_PAD_NAND_WE_B_RAWNAND_WE_B                             =  IOMUX_PAD(0x03A0, 0x0138, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_NAND_WE_B_USDHC3_CLK                               =  IOMUX_PAD(0x03A0, 0x0138, 2 | IOMUX_CONFIG_SION, 0x0000, 0, 0),
+	IMX8MM_PAD_NAND_WE_B_GPIO3_IO17                               =  IOMUX_PAD(0x03A0, 0x0138, 5, 0x0000, 0, 0),
+
+	IMX8MM_PAD_NAND_WP_B_RAWNAND_WP_B                             =  IOMUX_PAD(0x03A4, 0x013C, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_NAND_WP_B_USDHC3_CMD                               =  IOMUX_PAD(0x03A4, 0x013C, 2, 0x0000, 0, 0),
+	IMX8MM_PAD_NAND_WP_B_GPIO3_IO18                               =  IOMUX_PAD(0x03A4, 0x013C, 5, 0x0000, 0, 0),
+
+	IMX8MM_PAD_SAI5_RXFS_SAI5_RX_SYNC                             =  IOMUX_PAD(0x03A8, 0x0140, 0, 0x04E4, 0, 0),
+	IMX8MM_PAD_SAI5_RXFS_SAI1_TX_DATA0                            =  IOMUX_PAD(0x03A8, 0x0140, 1, 0x0000, 0, 0),
+	IMX8MM_PAD_SAI5_RXFS_GPIO3_IO19                               =  IOMUX_PAD(0x03A8, 0x0140, 5, 0x0000, 0, 0),
+
+	IMX8MM_PAD_SAI5_RXC_SAI5_RX_BCLK                              =  IOMUX_PAD(0x03AC, 0x0144, 0, 0x04D0, 0, 0),
+	IMX8MM_PAD_SAI5_RXC_SAI1_TX_DATA1                             =  IOMUX_PAD(0x03AC, 0x0144, 1, 0x0000, 0, 0),
+	IMX8MM_PAD_SAI5_RXC_PDM_CLK                                   =  IOMUX_PAD(0x03AC, 0x0144, 4, 0x0000, 0, 0),
+	IMX8MM_PAD_SAI5_RXC_GPIO3_IO20                                =  IOMUX_PAD(0x03AC, 0x0144, 5, 0x0000, 0, 0),
+
+	IMX8MM_PAD_SAI5_RXD0_SAI5_RX_DATA0                            =  IOMUX_PAD(0x03B0, 0x0148, 0, 0x04D4, 0, 0),
+	IMX8MM_PAD_SAI5_RXD0_SAI1_TX_DATA2                            =  IOMUX_PAD(0x03B0, 0x0148, 1, 0x0000, 0, 0),
+	IMX8MM_PAD_SAI5_RXD0_PDM_BIT_STREAM0                          =  IOMUX_PAD(0x03B0, 0x0148, 4, 0x0534, 0, 0),
+	IMX8MM_PAD_SAI5_RXD0_GPIO3_IO21                               =  IOMUX_PAD(0x03B0, 0x0148, 5, 0x0000, 0, 0),
+
+	IMX8MM_PAD_SAI5_RXD1_SAI5_RX_DATA1                            =  IOMUX_PAD(0x03B4, 0x014C, 0, 0x04D8, 0, 0),
+	IMX8MM_PAD_SAI5_RXD1_SAI1_TX_DATA3                            =  IOMUX_PAD(0x03B4, 0x014C, 1, 0x0000, 0, 0),
+	IMX8MM_PAD_SAI5_RXD1_SAI1_TX_SYNC                             =  IOMUX_PAD(0x03B4, 0x014C, 2, 0x04CC, 0, 0),
+	IMX8MM_PAD_SAI5_RXD1_SAI5_TX_SYNC                             =  IOMUX_PAD(0x03B4, 0x014C, 3, 0x04EC, 0, 0),
+	IMX8MM_PAD_SAI5_RXD1_PDM_BIT_STREAM1                          =  IOMUX_PAD(0x03B4, 0x014C, 4, 0x0538, 0, 0),
+	IMX8MM_PAD_SAI5_RXD1_GPIO3_IO22                               =  IOMUX_PAD(0x03B4, 0x014C, 5, 0x0000, 0, 0),
+
+	IMX8MM_PAD_SAI5_RXD2_SAI5_RX_DATA2                            =  IOMUX_PAD(0x03B8, 0x0150, 0, 0x04DC, 0, 0),
+	IMX8MM_PAD_SAI5_RXD2_SAI1_TX_DATA4                            =  IOMUX_PAD(0x03B8, 0x0150, 1, 0x0000, 0, 0),
+	IMX8MM_PAD_SAI5_RXD2_SAI1_TX_SYNC                             =  IOMUX_PAD(0x03B8, 0x0150, 2, 0x04CC, 1, 0),
+	IMX8MM_PAD_SAI5_RXD2_SAI5_TX_BCLK                             =  IOMUX_PAD(0x03B8, 0x0150, 3, 0x04E8, 0, 0),
+	IMX8MM_PAD_SAI5_RXD2_PDM_BIT_STREAM2                          =  IOMUX_PAD(0x03B8, 0x0150, 4, 0x053C, 0, 0),
+	IMX8MM_PAD_SAI5_RXD2_GPIO3_IO23                               =  IOMUX_PAD(0x03B8, 0x0150, 5, 0x0000, 0, 0),
+
+	IMX8MM_PAD_SAI5_RXD3_SAI5_RX_DATA3                            =  IOMUX_PAD(0x03BC, 0x0154, 0, 0x04E0, 0, 0),
+	IMX8MM_PAD_SAI5_RXD3_SAI1_TX_DATA5                            =  IOMUX_PAD(0x03BC, 0x0154, 1, 0x0000, 0, 0),
+	IMX8MM_PAD_SAI5_RXD3_SAI1_TX_SYNC                             =  IOMUX_PAD(0x03BC, 0x0154, 2, 0x04CC, 2, 0),
+	IMX8MM_PAD_SAI5_RXD3_SAI5_TX_DATA0                            =  IOMUX_PAD(0x03BC, 0x0154, 3, 0x0000, 0, 0),
+	IMX8MM_PAD_SAI5_RXD3_PDM_BIT_STREAM3                          =  IOMUX_PAD(0x03BC, 0x0154, 4, 0x0540, 0, 0),
+	IMX8MM_PAD_SAI5_RXD3_GPIO3_IO24                               =  IOMUX_PAD(0x03BC, 0x0154, 5, 0x0000, 0, 0),
+
+	IMX8MM_PAD_SAI5_MCLK_SAI5_MCLK                                =  IOMUX_PAD(0x03C0, 0x0158, 0, 0x052C, 0, 0),
+	IMX8MM_PAD_SAI5_MCLK_SAI1_TX_BCLK                             =  IOMUX_PAD(0x03C0, 0x0158, 1, 0x04C8, 0, 0),
+	IMX8MM_PAD_SAI5_MCLK_GPIO3_IO25                               =  IOMUX_PAD(0x03C0, 0x0158, 5, 0x0000, 0, 0),
+	IMX8MM_PAD_SAI5_MCLK_SRC_TESTER_ACK                           =  IOMUX_PAD(0x03C0, 0x0158, 6, 0x0000, 0, 0),
+
+	IMX8MM_PAD_SAI1_RXFS_SAI1_RX_SYNC                             =  IOMUX_PAD(0x03C4, 0x015C, 0, 0x04C4, 0, 0),
+	IMX8MM_PAD_SAI1_RXFS_SAI5_RX_SYNC                             =  IOMUX_PAD(0x03C4, 0x015C, 1, 0x04E4, 1, 0),
+	IMX8MM_PAD_SAI1_RXFS_ARM_PLATFORM_TRACE_CLK                   =  IOMUX_PAD(0x03C4, 0x015C, 4, 0x0000, 0, 0),
+	IMX8MM_PAD_SAI1_RXFS_GPIO4_IO0                                =  IOMUX_PAD(0x03C4, 0x015C, 5, 0x0000, 0, 0),
+
+	IMX8MM_PAD_SAI1_RXC_SAI1_RX_BCLK                              =  IOMUX_PAD(0x03C8, 0x0160, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_SAI1_RXC_SAI5_RX_BCLK                              =  IOMUX_PAD(0x03C8, 0x0160, 1, 0x04D0, 1, 0),
+	IMX8MM_PAD_SAI1_RXC_ARM_PLATFORM_TRACE_CTL                    =  IOMUX_PAD(0x03C8, 0x0160, 4, 0x0000, 0, 0),
+	IMX8MM_PAD_SAI1_RXC_GPIO4_IO1                                 =  IOMUX_PAD(0x03C8, 0x0160, 5, 0x0000, 0, 0),
+
+	IMX8MM_PAD_SAI1_RXD0_SAI1_RX_DATA0                            =  IOMUX_PAD(0x03CC, 0x0164, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_SAI1_RXD0_SAI5_RX_DATA0                            =  IOMUX_PAD(0x03CC, 0x0164, 1, 0x04D4, 1, 0),
+	IMX8MM_PAD_SAI1_RXD0_SAI1_TX_DATA1                            =  IOMUX_PAD(0x03CC, 0x0164, 2, 0x0000, 0, 0),
+	IMX8MM_PAD_SAI1_RXD0_PDM_BIT_STREAM0                          =  IOMUX_PAD(0x03CC, 0x0164, 3, 0x0534, 1, 0),
+	IMX8MM_PAD_SAI1_RXD0_ARM_PLATFORM_TRACE0                      =  IOMUX_PAD(0x03CC, 0x0164, 4, 0x0000, 0, 0),
+	IMX8MM_PAD_SAI1_RXD0_GPIO4_IO2                                =  IOMUX_PAD(0x03CC, 0x0164, 5, 0x0000, 0, 0),
+	IMX8MM_PAD_SAI1_RXD0_SRC_BOOT_CFG0                            =  IOMUX_PAD(0x03CC, 0x0164, 6, 0x0000, 0, 0),
+
+	IMX8MM_PAD_SAI1_RXD1_SAI1_RX_DATA1                            =  IOMUX_PAD(0x03D0, 0x0168, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_SAI1_RXD1_SAI5_RX_DATA1                            =  IOMUX_PAD(0x03D0, 0x0168, 1, 0x04D8, 1, 0),
+	IMX8MM_PAD_SAI1_RXD1_PDM_BIT_STREAM1                          =  IOMUX_PAD(0x03D0, 0x0168, 3, 0x0538, 1, 0),
+	IMX8MM_PAD_SAI1_RXD1_ARM_PLATFORM_TRACE1                      =  IOMUX_PAD(0x03D0, 0x0168, 4, 0x0000, 0, 0),
+	IMX8MM_PAD_SAI1_RXD1_GPIO4_IO3                                =  IOMUX_PAD(0x03D0, 0x0168, 5, 0x0000, 0, 0),
+	IMX8MM_PAD_SAI1_RXD1_SRC_BOOT_CFG1                            =  IOMUX_PAD(0x03D0, 0x0168, 6, 0x0000, 0, 0),
+
+	IMX8MM_PAD_SAI1_RXD2_SAI1_RX_DATA2                            =  IOMUX_PAD(0x03D4, 0x016C, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_SAI1_RXD2_SAI5_RX_DATA2                            =  IOMUX_PAD(0x03D4, 0x016C, 1, 0x04DC, 1, 0),
+	IMX8MM_PAD_SAI1_RXD2_PDM_BIT_STREAM2                          =  IOMUX_PAD(0x03D4, 0x016C, 3, 0x053C, 1, 0),
+	IMX8MM_PAD_SAI1_RXD2_ARM_PLATFORM_TRACE2                      =  IOMUX_PAD(0x03D4, 0x016C, 4, 0x0000, 0, 0),
+	IMX8MM_PAD_SAI1_RXD2_GPIO4_IO4                                =  IOMUX_PAD(0x03D4, 0x016C, 5, 0x0000, 0, 0),
+	IMX8MM_PAD_SAI1_RXD2_SRC_BOOT_CFG2                            =  IOMUX_PAD(0x03D4, 0x016C, 6, 0x0000, 0, 0),
+
+	IMX8MM_PAD_SAI1_RXD3_SAI1_RX_DATA3                            =  IOMUX_PAD(0x03D8, 0x0170, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_SAI1_RXD3_SAI5_RX_DATA3                            =  IOMUX_PAD(0x03D8, 0x0170, 1, 0x04E0, 1, 0),
+	IMX8MM_PAD_SAI1_RXD3_PDM_BIT_STREAM3                          =  IOMUX_PAD(0x03D8, 0x0170, 3, 0x0540, 1, 0),
+	IMX8MM_PAD_SAI1_RXD3_ARM_PLATFORM_TRACE3                      =  IOMUX_PAD(0x03D8, 0x0170, 4, 0x0000, 0, 0),
+	IMX8MM_PAD_SAI1_RXD3_GPIO4_IO5                                =  IOMUX_PAD(0x03D8, 0x0170, 5, 0x0000, 0, 0),
+	IMX8MM_PAD_SAI1_RXD3_SRC_BOOT_CFG3                            =  IOMUX_PAD(0x03D8, 0x0170, 6, 0x0000, 0, 0),
+
+	IMX8MM_PAD_SAI1_RXD4_SAI1_RX_DATA4                            =  IOMUX_PAD(0x03DC, 0x0174, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_SAI1_RXD4_SAI6_TX_BCLK                             =  IOMUX_PAD(0x03DC, 0x0174, 1, 0x051C, 0, 0),
+	IMX8MM_PAD_SAI1_RXD4_SAI6_RX_BCLK                             =  IOMUX_PAD(0x03DC, 0x0174, 2, 0x0510, 0, 0),
+	IMX8MM_PAD_SAI1_RXD4_ARM_PLATFORM_TRACE4                      =  IOMUX_PAD(0x03DC, 0x0174, 4, 0x0000, 0, 0),
+	IMX8MM_PAD_SAI1_RXD4_GPIO4_IO6                                =  IOMUX_PAD(0x03DC, 0x0174, 5, 0x0000, 0, 0),
+	IMX8MM_PAD_SAI1_RXD4_SRC_BOOT_CFG4                            =  IOMUX_PAD(0x03DC, 0x0174, 6, 0x0000, 0, 0),
+
+	IMX8MM_PAD_SAI1_RXD5_SAI1_RX_DATA5                            =  IOMUX_PAD(0x03E0, 0x0178, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_SAI1_RXD5_SAI6_TX_DATA0                            =  IOMUX_PAD(0x03E0, 0x0178, 1, 0x0000, 0, 0),
+	IMX8MM_PAD_SAI1_RXD5_SAI6_RX_DATA0                            =  IOMUX_PAD(0x03E0, 0x0178, 2, 0x0514, 0, 0),
+	IMX8MM_PAD_SAI1_RXD5_SAI1_RX_SYNC                             =  IOMUX_PAD(0x03E0, 0x0178, 3, 0x04C4, 1, 0),
+	IMX8MM_PAD_SAI1_RXD5_ARM_PLATFORM_TRACE5                      =  IOMUX_PAD(0x03E0, 0x0178, 4, 0x0000, 0, 0),
+	IMX8MM_PAD_SAI1_RXD5_GPIO4_IO7                                =  IOMUX_PAD(0x03E0, 0x0178, 5, 0x0000, 0, 0),
+	IMX8MM_PAD_SAI1_RXD5_SRC_BOOT_CFG5                            =  IOMUX_PAD(0x03E0, 0x0178, 6, 0x0000, 0, 0),
+
+	IMX8MM_PAD_SAI1_RXD6_SAI1_RX_DATA6                            =  IOMUX_PAD(0x03E4, 0x017C, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_SAI1_RXD6_SAI6_TX_SYNC                             =  IOMUX_PAD(0x03E4, 0x017C, 1, 0x0520, 0, 0),
+	IMX8MM_PAD_SAI1_RXD6_SAI6_RX_SYNC                             =  IOMUX_PAD(0x03E4, 0x017C, 2, 0x0518, 0, 0),
+	IMX8MM_PAD_SAI1_RXD6_ARM_PLATFORM_TRACE6                      =  IOMUX_PAD(0x03E4, 0x017C, 4, 0x0000, 0, 0),
+	IMX8MM_PAD_SAI1_RXD6_GPIO4_IO8                                =  IOMUX_PAD(0x03E4, 0x017C, 5, 0x0000, 0, 0),
+	IMX8MM_PAD_SAI1_RXD6_SRC_BOOT_CFG6                            =  IOMUX_PAD(0x03E4, 0x017C, 6, 0x0000, 0, 0),
+
+	IMX8MM_PAD_SAI1_RXD7_SAI1_RX_DATA7                            =  IOMUX_PAD(0x03E8, 0x0180, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_SAI1_RXD7_SAI6_MCLK                                =  IOMUX_PAD(0x03E8, 0x0180, 1, 0x0530, 0, 0),
+	IMX8MM_PAD_SAI1_RXD7_SAI1_TX_SYNC                             =  IOMUX_PAD(0x03E8, 0x0180, 2, 0x04CC, 4, 0),
+	IMX8MM_PAD_SAI1_RXD7_SAI1_TX_DATA4                            =  IOMUX_PAD(0x03E8, 0x0180, 3, 0x0000, 0, 0),
+	IMX8MM_PAD_SAI1_RXD7_ARM_PLATFORM_TRACE7                      =  IOMUX_PAD(0x03E8, 0x0180, 4, 0x0000, 0, 0),
+	IMX8MM_PAD_SAI1_RXD7_GPIO4_IO9                                =  IOMUX_PAD(0x03E8, 0x0180, 5, 0x0000, 0, 0),
+	IMX8MM_PAD_SAI1_RXD7_SRC_BOOT_CFG7                            =  IOMUX_PAD(0x03E8, 0x0180, 6, 0x0000, 0, 0),
+
+	IMX8MM_PAD_SAI1_TXFS_SAI1_TX_SYNC                             =  IOMUX_PAD(0x03EC, 0x0184, 0, 0x04CC, 3, 0),
+	IMX8MM_PAD_SAI1_TXFS_SAI5_TX_SYNC                             =  IOMUX_PAD(0x03EC, 0x0184, 1, 0x04EC, 1, 0),
+	IMX8MM_PAD_SAI1_TXFS_ARM_PLATFORM_EVENTO                      =  IOMUX_PAD(0x03EC, 0x0184, 4, 0x0000, 0, 0),
+	IMX8MM_PAD_SAI1_TXFS_GPIO4_IO10                               =  IOMUX_PAD(0x03EC, 0x0184, 5, 0x0000, 0, 0),
+
+	IMX8MM_PAD_SAI1_TXC_SAI1_TX_BCLK                              =  IOMUX_PAD(0x03F0, 0x0188, 0, 0x04C8, 1, 0),
+	IMX8MM_PAD_SAI1_TXC_SAI5_TX_BCLK                              =  IOMUX_PAD(0x03F0, 0x0188, 1, 0x04E8, 1, 0),
+	IMX8MM_PAD_SAI1_TXC_ARM_PLATFORM_EVENTI                       =  IOMUX_PAD(0x03F0, 0x0188, 4, 0x0000, 0, 0),
+	IMX8MM_PAD_SAI1_TXC_GPIO4_IO11                                =  IOMUX_PAD(0x03F0, 0x0188, 5, 0x0000, 0, 0),
+
+	IMX8MM_PAD_SAI1_TXD0_SAI1_TX_DATA0                            =  IOMUX_PAD(0x03F4, 0x018C, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_SAI1_TXD0_SAI5_TX_DATA0                            =  IOMUX_PAD(0x03F4, 0x018C, 1, 0x0000, 0, 0),
+	IMX8MM_PAD_SAI1_TXD0_ARM_PLATFORM_TRACE8                      =  IOMUX_PAD(0x03F4, 0x018C, 4, 0x0000, 0, 0),
+	IMX8MM_PAD_SAI1_TXD0_GPIO4_IO12                               =  IOMUX_PAD(0x03F4, 0x018C, 5, 0x0000, 0, 0),
+	IMX8MM_PAD_SAI1_TXD0_SRC_BOOT_CFG8                            =  IOMUX_PAD(0x03F4, 0x018C, 6, 0x0000, 0, 0),
+
+	IMX8MM_PAD_SAI1_TXD1_SAI1_TX_DATA1                            =  IOMUX_PAD(0x03F8, 0x0190, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_SAI1_TXD1_SAI5_TX_DATA1                            =  IOMUX_PAD(0x03F8, 0x0190, 1, 0x0000, 0, 0),
+	IMX8MM_PAD_SAI1_TXD1_ARM_PLATFORM_TRACE9                      =  IOMUX_PAD(0x03F8, 0x0190, 4, 0x0000, 0, 0),
+	IMX8MM_PAD_SAI1_TXD1_GPIO4_IO13                               =  IOMUX_PAD(0x03F8, 0x0190, 5, 0x0000, 0, 0),
+	IMX8MM_PAD_SAI1_TXD1_SRC_BOOT_CFG9                            =  IOMUX_PAD(0x03F8, 0x0190, 6, 0x0000, 0, 0),
+
+	IMX8MM_PAD_SAI1_TXD2_SAI1_TX_DATA2                            =  IOMUX_PAD(0x03FC, 0x0194, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_SAI1_TXD2_SAI5_TX_DATA2                            =  IOMUX_PAD(0x03FC, 0x0194, 1, 0x0000, 0, 0),
+	IMX8MM_PAD_SAI1_TXD2_ARM_PLATFORM_TRACE10                     =  IOMUX_PAD(0x03FC, 0x0194, 4, 0x0000, 0, 0),
+	IMX8MM_PAD_SAI1_TXD2_GPIO4_IO14                               =  IOMUX_PAD(0x03FC, 0x0194, 5, 0x0000, 0, 0),
+	IMX8MM_PAD_SAI1_TXD2_SRC_BOOT_CFG10                           =  IOMUX_PAD(0x03FC, 0x0194, 6, 0x0000, 0, 0),
+
+	IMX8MM_PAD_SAI1_TXD3_SAI1_TX_DATA3                            =  IOMUX_PAD(0x0400, 0x0198, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_SAI1_TXD3_SAI5_TX_DATA3                            =  IOMUX_PAD(0x0400, 0x0198, 1, 0x0000, 0, 0),
+	IMX8MM_PAD_SAI1_TXD3_ARM_PLATFORM_TRACE11                     =  IOMUX_PAD(0x0400, 0x0198, 4, 0x0000, 0, 0),
+	IMX8MM_PAD_SAI1_TXD3_GPIO4_IO15                               =  IOMUX_PAD(0x0400, 0x0198, 5, 0x0000, 0, 0),
+	IMX8MM_PAD_SAI1_TXD3_SRC_BOOT_CFG11                           =  IOMUX_PAD(0x0400, 0x0198, 6, 0x0000, 0, 0),
+
+	IMX8MM_PAD_SAI1_TXD4_SAI1_TX_DATA4                            =  IOMUX_PAD(0x0404, 0x019C, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_SAI1_TXD4_SAI6_RX_BCLK                             =  IOMUX_PAD(0x0404, 0x019C, 1, 0x0510, 1, 0),
+	IMX8MM_PAD_SAI1_TXD4_SAI6_TX_BCLK                             =  IOMUX_PAD(0x0404, 0x019C, 2, 0x051C, 1, 0),
+	IMX8MM_PAD_SAI1_TXD4_ARM_PLATFORM_TRACE12                     =  IOMUX_PAD(0x0404, 0x019C, 4, 0x0000, 0, 0),
+	IMX8MM_PAD_SAI1_TXD4_GPIO4_IO16                               =  IOMUX_PAD(0x0404, 0x019C, 5, 0x0000, 0, 0),
+	IMX8MM_PAD_SAI1_TXD4_SRC_BOOT_CFG12                           =  IOMUX_PAD(0x0404, 0x019C, 6, 0x0000, 0, 0),
+
+	IMX8MM_PAD_SAI1_TXD5_SAI1_TX_DATA5                            =  IOMUX_PAD(0x0408, 0x01A0, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_SAI1_TXD5_SAI6_RX_DATA0                            =  IOMUX_PAD(0x0408, 0x01A0, 1, 0x0514, 1, 0),
+	IMX8MM_PAD_SAI1_TXD5_SAI6_TX_DATA0                            =  IOMUX_PAD(0x0408, 0x01A0, 2, 0x0000, 0, 0),
+	IMX8MM_PAD_SAI1_TXD5_ARM_PLATFORM_TRACE13                     =  IOMUX_PAD(0x0408, 0x01A0, 4, 0x0000, 0, 0),
+	IMX8MM_PAD_SAI1_TXD5_GPIO4_IO17                               =  IOMUX_PAD(0x0408, 0x01A0, 5, 0x0000, 0, 0),
+	IMX8MM_PAD_SAI1_TXD5_SRC_BOOT_CFG13                           =  IOMUX_PAD(0x0408, 0x01A0, 6, 0x0000, 0, 0),
+
+	IMX8MM_PAD_SAI1_TXD6_SAI1_TX_DATA6                            =  IOMUX_PAD(0x040C, 0x01A4, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_SAI1_TXD6_SAI6_RX_SYNC                             =  IOMUX_PAD(0x040C, 0x01A4, 1, 0x0518, 1, 0),
+	IMX8MM_PAD_SAI1_TXD6_SAI6_TX_SYNC                             =  IOMUX_PAD(0x040C, 0x01A4, 2, 0x0520, 1, 0),
+	IMX8MM_PAD_SAI1_TXD6_ARM_PLATFORM_TRACE14                     =  IOMUX_PAD(0x040C, 0x01A4, 4, 0x0000, 0, 0),
+	IMX8MM_PAD_SAI1_TXD6_GPIO4_IO18                               =  IOMUX_PAD(0x040C, 0x01A4, 5, 0x0000, 0, 0),
+	IMX8MM_PAD_SAI1_TXD6_SRC_BOOT_CFG14                           =  IOMUX_PAD(0x040C, 0x01A4, 6, 0x0000, 0, 0),
+
+	IMX8MM_PAD_SAI1_TXD7_SAI1_TX_DATA7                            =  IOMUX_PAD(0x0410, 0x01A8, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_SAI1_TXD7_SAI6_MCLK                                =  IOMUX_PAD(0x0410, 0x01A8, 1, 0x0530, 1, 0),
+	IMX8MM_PAD_SAI1_TXD7_PDM_CLK                                  =  IOMUX_PAD(0x0410, 0x01A8, 3, 0x0000, 0, 0),
+	IMX8MM_PAD_SAI1_TXD7_ARM_PLATFORM_TRACE15                     =  IOMUX_PAD(0x0410, 0x01A8, 4, 0x0000, 0, 0),
+	IMX8MM_PAD_SAI1_TXD7_GPIO4_IO19                               =  IOMUX_PAD(0x0410, 0x01A8, 5, 0x0000, 0, 0),
+	IMX8MM_PAD_SAI1_TXD7_SRC_BOOT_CFG15                           =  IOMUX_PAD(0x0410, 0x01A8, 6, 0x0000, 0, 0),
+
+	IMX8MM_PAD_SAI1_MCLK_SAI1_MCLK                                =  IOMUX_PAD(0x0414, 0x01AC, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_SAI1_MCLK_SAI5_MCLK                                =  IOMUX_PAD(0x0414, 0x01AC, 1, 0x052C, 1, 0),
+	IMX8MM_PAD_SAI1_MCLK_SAI1_TX_BCLK                             =  IOMUX_PAD(0x0414, 0x01AC, 2, 0x04C8, 2, 0),
+	IMX8MM_PAD_SAI1_MCLK_PDM_CLK                                  =  IOMUX_PAD(0x0414, 0x01AC, 3, 0x0000, 0, 0),
+	IMX8MM_PAD_SAI1_MCLK_GPIO4_IO20                               =  IOMUX_PAD(0x0414, 0x01AC, 5, 0x0000, 0, 0),
+
+	IMX8MM_PAD_SAI2_RXFS_SAI2_RX_SYNC                             =  IOMUX_PAD(0x0418, 0x01B0, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_SAI2_RXFS_SAI5_TX_SYNC                             =  IOMUX_PAD(0x0418, 0x01B0, 1, 0x04EC, 2, 0),
+	IMX8MM_PAD_SAI2_RXFS_SAI5_TX_DATA1                            =  IOMUX_PAD(0x0418, 0x01B0, 2, 0x0000, 0, 0),
+	IMX8MM_PAD_SAI2_RXFS_SAI2_RX_DATA1                            =  IOMUX_PAD(0x0418, 0x01B0, 3, 0x0000, 0, 0),
+	IMX8MM_PAD_SAI2_RXFS_UART1_TX                                 =  IOMUX_PAD(0x0418, 0x01B0, 4, 0x0000, 0, 0),
+	IMX8MM_PAD_SAI2_RXFS_UART1_RX                                 =  IOMUX_PAD(0x0418, 0x01B0, 4, 0x04F4, 2, 0),
+	IMX8MM_PAD_SAI2_RXFS_GPIO4_IO21                               =  IOMUX_PAD(0x0418, 0x01B0, 5, 0x0000, 0, 0),
+
+	IMX8MM_PAD_SAI2_RXC_SAI2_RX_BCLK                              =  IOMUX_PAD(0x041C, 0x01B4, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_SAI2_RXC_SAI5_TX_BCLK                              =  IOMUX_PAD(0x041C, 0x01B4, 1, 0x04E8, 2, 0),
+	IMX8MM_PAD_SAI2_RXC_UART1_RX                                  =  IOMUX_PAD(0x041C, 0x01B4, 4, 0x04F4, 3, 0),
+	IMX8MM_PAD_SAI2_RXC_UART1_TX                                  =  IOMUX_PAD(0x041C, 0x01B4, 4, 0x0000, 0, 0),
+	IMX8MM_PAD_SAI2_RXC_GPIO4_IO22                                =  IOMUX_PAD(0x041C, 0x01B4, 5, 0x0000, 0, 0),
+
+	IMX8MM_PAD_SAI2_RXD0_SAI2_RX_DATA0                            =  IOMUX_PAD(0x0420, 0x01B8, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_SAI2_RXD0_SAI5_TX_DATA0                            =  IOMUX_PAD(0x0420, 0x01B8, 1, 0x0000, 0, 0),
+	IMX8MM_PAD_SAI2_RXD0_UART1_RTS_B                              =  IOMUX_PAD(0x0420, 0x01B8, 4, 0x04F0, 2, 0),
+	IMX8MM_PAD_SAI2_RXD0_UART1_CTS_B                              =  IOMUX_PAD(0x0420, 0x01B8, 4, 0x0000, 0, 0),
+	IMX8MM_PAD_SAI2_RXD0_GPIO4_IO23                               =  IOMUX_PAD(0x0420, 0x01B8, 5, 0x0000, 0, 0),
+
+	IMX8MM_PAD_SAI2_TXFS_SAI2_TX_SYNC                             =  IOMUX_PAD(0x0424, 0x01BC, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_SAI2_TXFS_SAI5_TX_DATA1                            =  IOMUX_PAD(0x0424, 0x01BC, 1, 0x0000, 0, 0),
+	IMX8MM_PAD_SAI2_TXFS_SAI2_TX_DATA1                            =  IOMUX_PAD(0x0424, 0x01BC, 3, 0x0000, 0, 0),
+	IMX8MM_PAD_SAI2_TXFS_UART1_CTS_B                              =  IOMUX_PAD(0x0424, 0x01BC, 4, 0x0000, 0, 0),
+	IMX8MM_PAD_SAI2_TXFS_UART1_RTS_B                              =  IOMUX_PAD(0x0424, 0x01BC, 4, 0x04F0, 3, 0),
+	IMX8MM_PAD_SAI2_TXFS_GPIO4_IO24                               =  IOMUX_PAD(0x0424, 0x01BC, 5, 0x0000, 0, 0),
+
+	IMX8MM_PAD_SAI2_TXC_SAI2_TX_BCLK                              =  IOMUX_PAD(0x0428, 0x01C0, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_SAI2_TXC_SAI5_TX_DATA2                             =  IOMUX_PAD(0x0428, 0x01C0, 1, 0x0000, 0, 0),
+	IMX8MM_PAD_SAI2_TXC_GPIO4_IO25                                =  IOMUX_PAD(0x0428, 0x01C0, 5, 0x0000, 0, 0),
+
+	IMX8MM_PAD_SAI2_TXD0_SAI2_TX_DATA0                            =  IOMUX_PAD(0x042C, 0x01C4, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_SAI2_TXD0_SAI5_TX_DATA3                            =  IOMUX_PAD(0x042C, 0x01C4, 1, 0x0000, 0, 0),
+	IMX8MM_PAD_SAI2_TXD0_GPIO4_IO26                               =  IOMUX_PAD(0x042C, 0x01C4, 5, 0x0000, 0, 0),
+
+	IMX8MM_PAD_SAI2_MCLK_SAI2_MCLK                                =  IOMUX_PAD(0x0430, 0x01C8, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_SAI2_MCLK_SAI5_MCLK                                =  IOMUX_PAD(0x0430, 0x01C8, 1, 0x052C, 2, 0),
+	IMX8MM_PAD_SAI2_MCLK_GPIO4_IO27                               =  IOMUX_PAD(0x0430, 0x01C8, 5, 0x0000, 0, 0),
+
+	IMX8MM_PAD_SAI3_RXFS_SAI3_RX_SYNC                             =  IOMUX_PAD(0x0434, 0x01CC, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_SAI3_RXFS_GPT1_CAPTURE1                            =  IOMUX_PAD(0x0434, 0x01CC, 1, 0x0000, 0, 0),
+	IMX8MM_PAD_SAI3_RXFS_SAI5_RX_SYNC                             =  IOMUX_PAD(0x0434, 0x01CC, 2, 0x04E4, 2, 0),
+	IMX8MM_PAD_SAI3_RXFS_SAI3_RX_DATA1                            =  IOMUX_PAD(0x0434, 0x01CC, 3, 0x0000, 0, 0),
+	IMX8MM_PAD_SAI3_RXFS_GPIO4_IO28                               =  IOMUX_PAD(0x0434, 0x01CC, 5, 0x0000, 0, 0),
+
+	IMX8MM_PAD_SAI3_RXC_SAI3_RX_BCLK                              =  IOMUX_PAD(0x0438, 0x01D0, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_SAI3_RXC_GPT1_CLK                                  =  IOMUX_PAD(0x0438, 0x01D0, 1, 0x0000, 0, 0),
+	IMX8MM_PAD_SAI3_RXC_SAI5_RX_BCLK                              =  IOMUX_PAD(0x0438, 0x01D0, 2, 0x04D0, 2, 0),
+	IMX8MM_PAD_SAI3_RXC_UART2_CTS_B                               =  IOMUX_PAD(0x0438, 0x01D0, 4, 0x0000, 0, 0),
+	IMX8MM_PAD_SAI3_RXC_UART2_RTS_B                               =  IOMUX_PAD(0x0438, 0x01D0, 4, 0x04F8, 2, 0),
+	IMX8MM_PAD_SAI3_RXC_GPIO4_IO29                                =  IOMUX_PAD(0x0438, 0x01D0, 5, 0x0000, 0, 0),
+
+	IMX8MM_PAD_SAI3_RXD_SAI3_RX_DATA0                             =  IOMUX_PAD(0x043C, 0x01D4, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_SAI3_RXD_GPT1_COMPARE1                             =  IOMUX_PAD(0x043C, 0x01D4, 1, 0x0000, 0, 0),
+	IMX8MM_PAD_SAI3_RXD_SAI5_RX_DATA0                             =  IOMUX_PAD(0x043C, 0x01D4, 2, 0x04D4, 2, 0),
+	IMX8MM_PAD_SAI3_RXD_UART2_RTS_B                               =  IOMUX_PAD(0x043C, 0x01D4, 4, 0x04F8, 3, 0),
+	IMX8MM_PAD_SAI3_RXD_UART2_CTS_B                               =  IOMUX_PAD(0x043C, 0x01D4, 4, 0x0000, 0, 0),
+	IMX8MM_PAD_SAI3_RXD_GPIO4_IO30                                =  IOMUX_PAD(0x043C, 0x01D4, 5, 0x0000, 0, 0),
+
+	IMX8MM_PAD_SAI3_TXFS_SAI3_TX_SYNC                             =  IOMUX_PAD(0x0440, 0x01D8, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_SAI3_TXFS_GPT1_CAPTURE2                            =  IOMUX_PAD(0x0440, 0x01D8, 1, 0x0000, 0, 0),
+	IMX8MM_PAD_SAI3_TXFS_SAI5_RX_DATA1                            =  IOMUX_PAD(0x0440, 0x01D8, 2, 0x04D8, 2, 0),
+	IMX8MM_PAD_SAI3_TXFS_SAI3_TX_DATA1                            =  IOMUX_PAD(0x0440, 0x01D8, 3, 0x0000, 0, 0),
+	IMX8MM_PAD_SAI3_TXFS_UART2_RX                                 =  IOMUX_PAD(0x0440, 0x01D8, 4, 0x04FC, 2, 0),
+	IMX8MM_PAD_SAI3_TXFS_UART2_TX                                 =  IOMUX_PAD(0x0440, 0x01D8, 4, 0x0000, 0, 0),
+	IMX8MM_PAD_SAI3_TXFS_GPIO4_IO31                               =  IOMUX_PAD(0x0440, 0x01D8, 5, 0x0000, 0, 0),
+
+	IMX8MM_PAD_SAI3_TXC_SAI3_TX_BCLK                              =  IOMUX_PAD(0x0444, 0x01DC, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_SAI3_TXC_GPT1_COMPARE2                             =  IOMUX_PAD(0x0444, 0x01DC, 1, 0x0000, 0, 0),
+	IMX8MM_PAD_SAI3_TXC_SAI5_RX_DATA2                             =  IOMUX_PAD(0x0444, 0x01DC, 2, 0x04DC, 2, 0),
+	IMX8MM_PAD_SAI3_TXC_UART2_TX                                  =  IOMUX_PAD(0x0444, 0x01DC, 4, 0x0000, 0, 0),
+	IMX8MM_PAD_SAI3_TXC_UART2_RX                                  =  IOMUX_PAD(0x0444, 0x01DC, 4, 0x04FC, 3, 0),
+	IMX8MM_PAD_SAI3_TXC_GPIO5_IO0                                 =  IOMUX_PAD(0x0444, 0x01DC, 5, 0x0000, 0, 0),
+
+	IMX8MM_PAD_SAI3_TXD_SAI3_TX_DATA0                             =  IOMUX_PAD(0x0448, 0x01E0, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_SAI3_TXD_GPT1_COMPARE3                             =  IOMUX_PAD(0x0448, 0x01E0, 1, 0x0000, 0, 0),
+	IMX8MM_PAD_SAI3_TXD_SAI5_RX_DATA3                             =  IOMUX_PAD(0x0448, 0x01E0, 2, 0x04E0, 2, 0),
+	IMX8MM_PAD_SAI3_TXD_GPIO5_IO1                                 =  IOMUX_PAD(0x0448, 0x01E0, 5, 0x0000, 0, 0),
+
+	IMX8MM_PAD_SAI3_MCLK_SAI3_MCLK                                =  IOMUX_PAD(0x044C, 0x01E4, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_SAI3_MCLK_PWM4_OUT                                 =  IOMUX_PAD(0x044C, 0x01E4, 1, 0x0000, 0, 0),
+	IMX8MM_PAD_SAI3_MCLK_SAI5_MCLK                                =  IOMUX_PAD(0x044C, 0x01E4, 2, 0x052C, 3, 0),
+	IMX8MM_PAD_SAI3_MCLK_GPIO5_IO2                                =  IOMUX_PAD(0x044C, 0x01E4, 5, 0x0000, 0, 0),
+
+	IMX8MM_PAD_SPDIF_TX_SPDIF1_OUT                                =  IOMUX_PAD(0x0450, 0x01E8, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_SPDIF_TX_PWM3_OUT                                  =  IOMUX_PAD(0x0450, 0x01E8, 1, 0x0000, 0, 0),
+	IMX8MM_PAD_SPDIF_TX_GPIO5_IO3                                 =  IOMUX_PAD(0x0450, 0x01E8, 5, 0x0000, 0, 0),
+
+	IMX8MM_PAD_SPDIF_RX_SPDIF1_IN                                 =  IOMUX_PAD(0x0454, 0x01EC, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_SPDIF_RX_PWM2_OUT                                  =  IOMUX_PAD(0x0454, 0x01EC, 1, 0x0000, 0, 0),
+	IMX8MM_PAD_SPDIF_RX_GPIO5_IO4                                 =  IOMUX_PAD(0x0454, 0x01EC, 5, 0x0000, 0, 0),
+
+	IMX8MM_PAD_SPDIF_EXT_CLK_SPDIF1_EXT_CLK                       =  IOMUX_PAD(0x0458, 0x01F0, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_SPDIF_EXT_CLK_PWM1_OUT                             =  IOMUX_PAD(0x0458, 0x01F0, 1, 0x0000, 0, 0),
+	IMX8MM_PAD_SPDIF_EXT_CLK_GPIO5_IO5                            =  IOMUX_PAD(0x0458, 0x01F0, 5, 0x0000, 0, 0),
+
+	IMX8MM_PAD_ECSPI1_SCLK_ECSPI1_SCLK                            =  IOMUX_PAD(0x045C, 0x01F4, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_ECSPI1_SCLK_UART3_RX                               =  IOMUX_PAD(0x045C, 0x01F4, 1, 0x0504, 0, 0),
+	IMX8MM_PAD_ECSPI1_SCLK_UART3_TX                               =  IOMUX_PAD(0x045C, 0x01F4, 1, 0x0000, 0, 0),
+	IMX8MM_PAD_ECSPI1_SCLK_GPIO5_IO6                              =  IOMUX_PAD(0x045C, 0x01F4, 5, 0x0000, 0, 0),
+
+	IMX8MM_PAD_ECSPI1_MOSI_ECSPI1_MOSI                            =  IOMUX_PAD(0x0460, 0x01F8, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_ECSPI1_MOSI_UART3_TX                               =  IOMUX_PAD(0x0460, 0x01F8, 1, 0x0000, 0, 0),
+	IMX8MM_PAD_ECSPI1_MOSI_UART3_RX                               =  IOMUX_PAD(0x0460, 0x01F8, 1, 0x0504, 1, 0),
+	IMX8MM_PAD_ECSPI1_MOSI_GPIO5_IO7                              =  IOMUX_PAD(0x0460, 0x01F8, 5, 0x0000, 0, 0),
+
+	IMX8MM_PAD_ECSPI1_MISO_ECSPI1_MISO                            =  IOMUX_PAD(0x0464, 0x01FC, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_ECSPI1_MISO_UART3_CTS_B                            =  IOMUX_PAD(0x0464, 0x01FC, 1, 0x0000, 0, 0),
+	IMX8MM_PAD_ECSPI1_MISO_UART3_RTS_B                            =  IOMUX_PAD(0x0464, 0x01FC, 1, 0x0500, 0, 0),
+	IMX8MM_PAD_ECSPI1_MISO_GPIO5_IO8                              =  IOMUX_PAD(0x0464, 0x01FC, 5, 0x0000, 0, 0),
+
+	IMX8MM_PAD_ECSPI1_SS0_ECSPI1_SS0                              =  IOMUX_PAD(0x0468, 0x0200, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_ECSPI1_SS0_UART3_RTS_B                             =  IOMUX_PAD(0x0468, 0x0200, 1, 0x0500, 1, 0),
+	IMX8MM_PAD_ECSPI1_SS0_UART3_CTS_B                             =  IOMUX_PAD(0x0468, 0x0200, 1, 0x0000, 0, 0),
+	IMX8MM_PAD_ECSPI1_SS0_GPIO5_IO9                               =  IOMUX_PAD(0x0468, 0x0200, 5, 0x0000, 0, 0),
+
+	IMX8MM_PAD_ECSPI2_SCLK_ECSPI2_SCLK                            =  IOMUX_PAD(0x046C, 0x0204, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_ECSPI2_SCLK_UART4_RX                               =  IOMUX_PAD(0x046C, 0x0204, 1, 0x050C, 0, 0),
+	IMX8MM_PAD_ECSPI2_SCLK_UART4_TX                               =  IOMUX_PAD(0x046C, 0x0204, 1, 0x0000, 0, 0),
+	IMX8MM_PAD_ECSPI2_SCLK_GPIO5_IO10                             =  IOMUX_PAD(0x046C, 0x0204, 5, 0x0000, 0, 0),
+
+	IMX8MM_PAD_ECSPI2_MOSI_ECSPI2_MOSI                            =  IOMUX_PAD(0x0470, 0x0208, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_ECSPI2_MOSI_UART4_TX                               =  IOMUX_PAD(0x0470, 0x0208, 1, 0x0000, 0, 0),
+	IMX8MM_PAD_ECSPI2_MOSI_UART4_RX                               =  IOMUX_PAD(0x0470, 0x0208, 1, 0x050C, 1, 0),
+	IMX8MM_PAD_ECSPI2_MOSI_GPIO5_IO11                             =  IOMUX_PAD(0x0470, 0x0208, 5, 0x0000, 0, 0),
+
+	IMX8MM_PAD_ECSPI2_MISO_ECSPI2_MISO                            =  IOMUX_PAD(0x0474, 0x020C, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_ECSPI2_MISO_UART4_CTS_B                            =  IOMUX_PAD(0x0474, 0x020C, 1, 0x0000, 0, 0),
+	IMX8MM_PAD_ECSPI2_MISO_UART4_RTS_B                            =  IOMUX_PAD(0x0474, 0x020C, 1, 0x0508, 0, 0),
+	IMX8MM_PAD_ECSPI2_MISO_GPIO5_IO12                             =  IOMUX_PAD(0x0474, 0x020C, 5, 0x0000, 0, 0),
+
+	IMX8MM_PAD_ECSPI2_SS0_ECSPI2_SS0                              =  IOMUX_PAD(0x0478, 0x0210, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_ECSPI2_SS0_UART4_RTS_B                             =  IOMUX_PAD(0x0478, 0x0210, 1, 0x0508, 1, 0),
+	IMX8MM_PAD_ECSPI2_SS0_UART4_CTS_B                             =  IOMUX_PAD(0x0478, 0x0210, 1, 0x0000, 0, 0),
+	IMX8MM_PAD_ECSPI2_SS0_GPIO5_IO13                              =  IOMUX_PAD(0x0478, 0x0210, 5, 0x0000, 0, 0),
+
+	IMX8MM_PAD_I2C1_SCL_I2C1_SCL                                  =  IOMUX_PAD(0x047C, 0x0214, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0),
+	IMX8MM_PAD_I2C1_SCL_ENET1_MDC                                 =  IOMUX_PAD(0x047C, 0x0214, 1, 0x0000, 0, 0),
+	IMX8MM_PAD_I2C1_SCL_GPIO5_IO14                                =  IOMUX_PAD(0x047C, 0x0214, 5, 0x0000, 0, 0),
+
+	IMX8MM_PAD_I2C1_SDA_I2C1_SDA                                  =  IOMUX_PAD(0x0480, 0x0218, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0),
+	IMX8MM_PAD_I2C1_SDA_ENET1_MDIO                                =  IOMUX_PAD(0x0480, 0x0218, 1, 0x04C0, 2, 0),
+	IMX8MM_PAD_I2C1_SDA_GPIO5_IO15                                =  IOMUX_PAD(0x0480, 0x0218, 5, 0x0000, 0, 0),
+
+	IMX8MM_PAD_I2C2_SCL_I2C2_SCL                                  =  IOMUX_PAD(0x0484, 0x021C, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_I2C2_SCL_ENET1_1588_EVENT1_IN                      =  IOMUX_PAD(0x0484, 0x021C, 1, 0x0000, 0, 0),
+	IMX8MM_PAD_I2C2_SCL_USDHC3_CD_B                               =  IOMUX_PAD(0x0484, 0x021C, 2, 0x0544, 1, 0),
+	IMX8MM_PAD_I2C2_SCL_GPIO5_IO16                                =  IOMUX_PAD(0x0484, 0x021C, 5, 0x0000, 0, 0),
+
+	IMX8MM_PAD_I2C2_SDA_I2C2_SDA                                  =  IOMUX_PAD(0x0488, 0x0220, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_I2C2_SDA_ENET1_1588_EVENT1_OUT                     =  IOMUX_PAD(0x0488, 0x0220, 1, 0x0000, 0, 0),
+	IMX8MM_PAD_I2C2_SDA_USDHC3_WP                                 =  IOMUX_PAD(0x0488, 0x0220, 2, 0x0548, 1, 0),
+	IMX8MM_PAD_I2C2_SDA_GPIO5_IO17                                =  IOMUX_PAD(0x0488, 0x0220, 5, 0x0000, 0, 0),
+
+	IMX8MM_PAD_I2C3_SCL_I2C3_SCL                                  =  IOMUX_PAD(0x048C, 0x0224, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_I2C3_SCL_PWM4_OUT                                  =  IOMUX_PAD(0x048C, 0x0224, 1, 0x0000, 0, 0),
+	IMX8MM_PAD_I2C3_SCL_GPT2_CLK                                  =  IOMUX_PAD(0x048C, 0x0224, 2, 0x0000, 0, 0),
+	IMX8MM_PAD_I2C3_SCL_GPIO5_IO18                                =  IOMUX_PAD(0x048C, 0x0224, 5, 0x0000, 0, 0),
+
+	IMX8MM_PAD_I2C3_SDA_I2C3_SDA                                  =  IOMUX_PAD(0x0490, 0x0228, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_I2C3_SDA_PWM3_OUT                                  =  IOMUX_PAD(0x0490, 0x0228, 1, 0x0000, 0, 0),
+	IMX8MM_PAD_I2C3_SDA_GPT3_CLK                                  =  IOMUX_PAD(0x0490, 0x0228, 2, 0x0000, 0, 0),
+	IMX8MM_PAD_I2C3_SDA_GPIO5_IO19                                =  IOMUX_PAD(0x0490, 0x0228, 5, 0x0000, 0, 0),
+
+	IMX8MM_PAD_I2C4_SCL_I2C4_SCL                                  =  IOMUX_PAD(0x0494, 0x022C, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_I2C4_SCL_PWM2_OUT                                  =  IOMUX_PAD(0x0494, 0x022C, 1, 0x0000, 0, 0),
+	IMX8MM_PAD_I2C4_SCL_PCIE1_CLKREQ_B                            =  IOMUX_PAD(0x0494, 0x022C, 2, 0x0524, 0, 0),
+	IMX8MM_PAD_I2C4_SCL_GPIO5_IO20                                =  IOMUX_PAD(0x0494, 0x022C, 5, 0x0000, 0, 0),
+
+	IMX8MM_PAD_I2C4_SDA_I2C4_SDA                                  =  IOMUX_PAD(0x0498, 0x0230, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_I2C4_SDA_PWM1_OUT                                  =  IOMUX_PAD(0x0498, 0x0230, 1, 0x0000, 0, 0),
+	IMX8MM_PAD_I2C4_SDA_GPIO5_IO21                                =  IOMUX_PAD(0x0498, 0x0230, 5, 0x0000, 0, 0),
+
+	IMX8MM_PAD_UART1_RXD_UART1_RX                                 =  IOMUX_PAD(0x049C, 0x0234, 0, 0x04F4, 0, 0),
+	IMX8MM_PAD_UART1_RXD_UART1_TX                                 =  IOMUX_PAD(0x049C, 0x0234, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_UART1_RXD_ECSPI3_SCLK                              =  IOMUX_PAD(0x049C, 0x0234, 1, 0x0000, 0, 0),
+	IMX8MM_PAD_UART1_RXD_GPIO5_IO22                               =  IOMUX_PAD(0x049C, 0x0234, 5, 0x0000, 0, 0),
+
+	IMX8MM_PAD_UART1_TXD_UART1_TX                                 =  IOMUX_PAD(0x04A0, 0x0238, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_UART1_TXD_UART1_RX                                 =  IOMUX_PAD(0x04A0, 0x0238, 0, 0x04F4, 1, 0),
+	IMX8MM_PAD_UART1_TXD_ECSPI3_MOSI                              =  IOMUX_PAD(0x04A0, 0x0238, 1, 0x0000, 0, 0),
+	IMX8MM_PAD_UART1_TXD_GPIO5_IO23                               =  IOMUX_PAD(0x04A0, 0x0238, 5, 0x0000, 0, 0),
+
+	IMX8MM_PAD_UART2_RXD_UART2_RX                                 =  IOMUX_PAD(0x04A4, 0x023C, 0, 0x04FC, 0, 0),
+	IMX8MM_PAD_UART2_RXD_UART2_TX                                 =  IOMUX_PAD(0x04A4, 0x023C, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_UART2_RXD_ECSPI3_MISO                              =  IOMUX_PAD(0x04A4, 0x023C, 1, 0x0000, 0, 0),
+	IMX8MM_PAD_UART2_RXD_GPIO5_IO24                               =  IOMUX_PAD(0x04A4, 0x023C, 5, 0x0000, 0, 0),
+
+	IMX8MM_PAD_UART2_TXD_UART2_TX                                 =  IOMUX_PAD(0x04A8, 0x0240, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_UART2_TXD_UART2_RX                                 =  IOMUX_PAD(0x04A8, 0x0240, 0, 0x04FC, 1, 0),
+	IMX8MM_PAD_UART2_TXD_ECSPI3_SS0                               =  IOMUX_PAD(0x04A8, 0x0240, 1, 0x0000, 0, 0),
+	IMX8MM_PAD_UART2_TXD_GPIO5_IO25                               =  IOMUX_PAD(0x04A8, 0x0240, 5, 0x0000, 0, 0),
+
+	IMX8MM_PAD_UART3_RXD_UART3_RX                                 =  IOMUX_PAD(0x04AC, 0x0244, 0, 0x0504, 2, 0),
+	IMX8MM_PAD_UART3_RXD_UART3_TX                                 =  IOMUX_PAD(0x04AC, 0x0244, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_UART3_RXD_UART1_CTS_B                              =  IOMUX_PAD(0x04AC, 0x0244, 1, 0x0000, 0, 0),
+	IMX8MM_PAD_UART3_RXD_UART1_RTS_B                              =  IOMUX_PAD(0x04AC, 0x0244, 1, 0x04F0, 0, 0),
+	IMX8MM_PAD_UART3_RXD_USDHC3_RESET_B                           =  IOMUX_PAD(0x04AC, 0x0244, 2, 0x0000, 0, 0),
+	IMX8MM_PAD_UART3_RXD_GPIO5_IO26                               =  IOMUX_PAD(0x04AC, 0x0244, 5, 0x0000, 0, 0),
+
+	IMX8MM_PAD_UART3_TXD_UART3_TX                                 =  IOMUX_PAD(0x04B0, 0x0248, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_UART3_TXD_UART3_RX                                 =  IOMUX_PAD(0x04B0, 0x0248, 0, 0x0504, 3, 0),
+	IMX8MM_PAD_UART3_TXD_UART1_RTS_B                              =  IOMUX_PAD(0x04B0, 0x0248, 1, 0x04F0, 1, 0),
+	IMX8MM_PAD_UART3_TXD_UART1_CTS_B                              =  IOMUX_PAD(0x04B0, 0x0248, 1, 0x0000, 0, 0),
+	IMX8MM_PAD_UART3_TXD_USDHC3_VSELECT                           =  IOMUX_PAD(0x04B0, 0x0248, 2, 0x0000, 0, 0),
+	IMX8MM_PAD_UART3_TXD_GPIO5_IO27                               =  IOMUX_PAD(0x04B0, 0x0248, 5, 0x0000, 0, 0),
+
+	IMX8MM_PAD_UART4_RXD_UART4_RX                                 =  IOMUX_PAD(0x04B4, 0x024C, 0, 0x050C, 2, 0),
+	IMX8MM_PAD_UART4_RXD_UART4_TX                                 =  IOMUX_PAD(0x04B4, 0x024C, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_UART4_RXD_UART2_CTS_B                              =  IOMUX_PAD(0x04B4, 0x024C, 1, 0x0000, 0, 0),
+	IMX8MM_PAD_UART4_RXD_UART2_RTS_B                              =  IOMUX_PAD(0x04B4, 0x024C, 1, 0x04F8, 0, 0),
+	IMX8MM_PAD_UART4_RXD_PCIE1_CLKREQ_B                           =  IOMUX_PAD(0x04B4, 0x024C, 2, 0x0524, 1, 0),
+	IMX8MM_PAD_UART4_RXD_GPIO5_IO28                               =  IOMUX_PAD(0x04B4, 0x024C, 5, 0x0000, 0, 0),
+
+	IMX8MM_PAD_UART4_TXD_UART4_TX                                 =  IOMUX_PAD(0x04B8, 0x0250, 0, 0x0000, 0, 0),
+	IMX8MM_PAD_UART4_TXD_UART4_RX                                 =  IOMUX_PAD(0x04B8, 0x0250, 0, 0x050C, 3, 0),
+	IMX8MM_PAD_UART4_TXD_UART2_RTS_B                              =  IOMUX_PAD(0x04B8, 0x0250, 1, 0x04F8, 1, 0),
+	IMX8MM_PAD_UART4_TXD_UART2_CTS_B                              =  IOMUX_PAD(0x04B8, 0x0250, 1, 0x0000, 0, 0),
+	IMX8MM_PAD_UART4_TXD_GPIO5_IO29                               =  IOMUX_PAD(0x04B8, 0x0250, 5, 0x0000, 0, 0),
+};
+#endif
-- 
2.16.4

[U-Boot] [i.MX8MM+CCF 30/41] imx: add i.MX8MM PE property

[Peng Fan]

i.MX8MM does not have LVTTL, it has a PE property

Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 arch/arm/include/asm/mach-imx/iomux-v3.h | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/arm/include/asm/mach-imx/iomux-v3.h b/arch/arm/include/asm/mach-imx/iomux-v3.h
index b899a4ff6f..720e8f7043 100644
--- a/arch/arm/include/asm/mach-imx/iomux-v3.h
+++ b/arch/arm/include/asm/mach-imx/iomux-v3.h
@@ -104,7 +104,11 @@ typedef u64 iomux_v3_cfg_t;
 #define PAD_CTL_ODE		(0x1 << 5)
 #define PAD_CTL_PUE		(0x1 << 6)
 #define PAD_CTL_HYS		(0x1 << 7)
+#ifdef CONFIG_IMX8MM
+#define PAD_CTL_PE		(0x1 << 8)
+#else
 #define PAD_CTL_LVTTL		(0x1 << 8)
+#endif
 
 #elif defined CONFIG_MX7
 
-- 
2.16.4

[U-Boot] [i.MX8MM+CCF 31/41] imx8m: Fix MMU table issue for OPTEE memory

[Peng Fan]

When running with OPTEE, the MMU table in u-boot does not remove the OPTEE
memory from its settings. So ARM speculative prefetch in u-boot may access
that OPTEE memory. Due to trust zone is enabled by OPTEE and that memory
is set to secure access, then the speculative prefetch will fail and cause
various memory issue in u-boot.
The fail address register and int_status register in trustzone has logged
that speculative access from u-boot.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 arch/arm/mach-imx/imx8m/soc.c | 20 ++++++++++++++++++--
 1 file changed, 18 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/mach-imx/imx8m/soc.c
index 07cda86bdd..5e9481c565 100644
--- a/arch/arm/mach-imx/imx8m/soc.c
+++ b/arch/arm/mach-imx/imx8m/soc.c
@@ -116,16 +116,18 @@ static struct mm_region imx8m_mem_map[] = {
 		/* DRAM1 */
 		.virt = 0x40000000UL,
 		.phys = 0x40000000UL,
-		.size = 0xC0000000UL,
+		.size = PHYS_SDRAM_SIZE,
 		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
 			 PTE_BLOCK_OUTER_SHARE
+#ifdef PHYS_SDRAM_2_SIZE
 	}, {
 		/* DRAM2 */
 		.virt = 0x100000000UL,
 		.phys = 0x100000000UL,
-		.size = 0x040000000UL,
+		.size = PHYS_SDRAM_2_SIZE,
 		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
 			 PTE_BLOCK_OUTER_SHARE
+#endif
 	}, {
 		/* List terminator */
 		0,
@@ -134,6 +136,20 @@ static struct mm_region imx8m_mem_map[] = {
 
 struct mm_region *mem_map = imx8m_mem_map;
 
+void enable_caches(void)
+{
+	/*
+	 * If OPTEE runs, remove OPTEE memory from MMU table to
+	 * avoid speculative prefetch. OPTEE runs at the top of
+	 * the first memory bank
+	 */
+	if (rom_pointer[1])
+		imx8m_mem_map[5].size -= rom_pointer[1];
+
+	icache_enable();
+	dcache_enable();
+}
+
 static u32 get_cpu_variant_type(u32 type)
 {
 	struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
-- 
2.16.4

[U-Boot] [i.MX8MM+CCF 32/41] imx8m: set BYPASS ID SWAP to avoid AXI bus errors

[Peng Fan]

set the BYPASS ID SWAP bit (GPR10 bit 1) in order for GPU not to
generated AXI bus errors with TZC380 enabled.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 arch/arm/mach-imx/imx8m/soc.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/mach-imx/imx8m/soc.c
index 5e9481c565..3918578399 100644
--- a/arch/arm/mach-imx/imx8m/soc.c
+++ b/arch/arm/mach-imx/imx8m/soc.c
@@ -59,6 +59,8 @@ void enable_tzc380(void)
 	/* Enable TZASC and lock setting */
 	setbits_le32(&gpr->gpr[10], GPR_TZASC_EN);
 	setbits_le32(&gpr->gpr[10], GPR_TZASC_EN_LOCK);
+	if (IS_ENABLED(CONFIG_IMX8MM))
+		setbits_le32(&gpr->gpr[10], BIT(1));
 }
 
 void set_wdog_reset(struct wdog_regs *wdog)
-- 
2.16.4

[U-Boot] [i.MX8MM+CCF 33/41] imx8m: Configure trustzone region 0 for non-secure access

[Peng Fan]

From: Ye Li <ye.li@nxp.com>

Set trustzone region 0 to allow both non-secure and secure access
when trust zone is enabled. We found USB controller fails to access
DDR if the default region 0 is secure access only.

Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 arch/arm/mach-imx/imx8m/soc.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/mach-imx/imx8m/soc.c
index 3918578399..abf526bc68 100644
--- a/arch/arm/mach-imx/imx8m/soc.c
+++ b/arch/arm/mach-imx/imx8m/soc.c
@@ -61,6 +61,12 @@ void enable_tzc380(void)
 	setbits_le32(&gpr->gpr[10], GPR_TZASC_EN_LOCK);
 	if (IS_ENABLED(CONFIG_IMX8MM))
 		setbits_le32(&gpr->gpr[10], BIT(1));
+	/*
+	 * set Region 0 attribute to allow secure and non-secure
+	 * read/write permission. Found some masters like usb dwc3
+	 * controllers can't work with secure memory.
+	 */
+	writel(0xf0000000, TZASC_BASE_ADDR + 0x108);
 }
 
 void set_wdog_reset(struct wdog_regs *wdog)
-- 
2.16.4

[U-Boot] [i.MX8MM+CCF 34/41] imx8m: soc: enable SCTR clock before timer init

[Peng Fan]

To i.MX8MM SCTR clock is disabled by ROM, so before timer init
need to enable it.
To i.MX8MQ, it does not hurt the clock is enabled again.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 arch/arm/mach-imx/imx8m/soc.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/mach-imx/imx8m/soc.c
index abf526bc68..ea83a495c2 100644
--- a/arch/arm/mach-imx/imx8m/soc.c
+++ b/arch/arm/mach-imx/imx8m/soc.c
@@ -234,6 +234,12 @@ static void imx_set_wdog_powerdown(bool enable)
 
 int arch_cpu_init(void)
 {
+	/*
+	 * ROM might disable clock for SCTR,
+	 * enable the clock before timer_init.
+	 */
+	if (IS_ENABLED(CONFIG_SPL_BUILD))
+		clock_enable(CCGR_SCTR, 1);
 	/*
 	 * Init timer at very early state, because sscg pll setting
 	 * will use it
-- 
2.16.4

[U-Boot] [i.MX8MM+CCF 35/41] serial: Kconfig: make MXC_UART usable for MX7 and IMX8M

[Peng Fan]

i.MX7 and i.MX8M use mxc uart driver, so let's make the SoC could
use MXC_UART kconfig.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 drivers/serial/Kconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
index fcbb0a81ed..a37b2d60f2 100644
--- a/drivers/serial/Kconfig
+++ b/drivers/serial/Kconfig
@@ -561,7 +561,7 @@ config MVEBU_A3700_UART
 
 config MXC_UART
 	bool "IMX serial port support"
-	depends on MX5 || MX6
+	depends on MX5 || MX6 || MX7 || IMX8M
 	help
 	  If you have a machine based on a Motorola IMX CPU you
 	  can enable its onboard serial port by enabling this option.
-- 
2.16.4

[U-Boot] [i.MX8MM+CCF 36/41] clk: imx: add Kconfig entry for i.MX8MM

[Peng Fan]

Add Kconfig entry for i.MX8MM, select CLK_CCF and SPL_CLK_CCF

Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 drivers/clk/imx/Kconfig | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/drivers/clk/imx/Kconfig b/drivers/clk/imx/Kconfig
index 469768b5c3..0e4c68659c 100644
--- a/drivers/clk/imx/Kconfig
+++ b/drivers/clk/imx/Kconfig
@@ -13,3 +13,12 @@ config CLK_IMX8
 	select CLK
 	help
 	  This enables support clock driver for i.MX8 platforms.
+
+config CLK_IMX8MM
+	bool "Clock support for i.MX8MM"
+	depends on IMX8MM
+	select CLK
+	select CLK_CCF
+	select SPL_CLK_CCF
+	help
+	  This enables support clock driver for i.MX8 platforms.
-- 
2.16.4

[U-Boot] [i.MX8MM+CCF 37/41] clk: imx: add pll14xx driver

[Peng Fan]

Add pll14xx driver

Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 drivers/clk/imx/clk-pll14xx.c | 377 ++++++++++++++++++++++++++++++++++++++++++
 drivers/clk/imx/clk.h         |  25 +++
 2 files changed, 402 insertions(+)
 create mode 100644 drivers/clk/imx/clk-pll14xx.c

diff --git a/drivers/clk/imx/clk-pll14xx.c b/drivers/clk/imx/clk-pll14xx.c
new file mode 100644
index 0000000000..a398b0bbc4
--- /dev/null
+++ b/drivers/clk/imx/clk-pll14xx.c
@@ -0,0 +1,377 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2017-2019 NXP.
+ *
+ * Peng Fan <peng.fan@nxp.com>
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <malloc.h>
+#include <clk-uclass.h>
+#include <dm/device.h>
+#include <linux/clk-provider.h>
+#include <linux/iopoll.h>
+#include <clk.h>
+#include <div64.h>
+
+#include "clk.h"
+
+#define UBOOT_DM_CLK_IMX_PLL1443X "imx_clk_pll1443x"
+#define UBOOT_DM_CLK_IMX_PLL1416X "imx_clk_pll1416x"
+
+#define GNRL_CTL	0x0
+#define DIV_CTL		0x4
+#define LOCK_STATUS	BIT(31)
+#define LOCK_SEL_MASK	BIT(29)
+#define CLKE_MASK	BIT(11)
+#define RST_MASK	BIT(9)
+#define BYPASS_MASK	BIT(4)
+#define MDIV_SHIFT	12
+#define MDIV_MASK	GENMASK(21, 12)
+#define PDIV_SHIFT	4
+#define PDIV_MASK	GENMASK(9, 4)
+#define SDIV_SHIFT	0
+#define SDIV_MASK	GENMASK(2, 0)
+#define KDIV_SHIFT	0
+#define KDIV_MASK	GENMASK(15, 0)
+
+#define LOCK_TIMEOUT_US		10000
+
+struct clk_pll14xx {
+	struct clk			clk;
+	void __iomem			*base;
+	enum imx_pll14xx_type		type;
+	const struct imx_pll14xx_rate_table *rate_table;
+	int rate_count;
+};
+
+#define to_clk_pll14xx(_clk) container_of(_clk, struct clk_pll14xx, clk)
+
+static const struct imx_pll14xx_rate_table *imx_get_pll_settings(
+		struct clk_pll14xx *pll, unsigned long rate)
+{
+	const struct imx_pll14xx_rate_table *rate_table = pll->rate_table;
+	int i;
+
+	for (i = 0; i < pll->rate_count; i++)
+		if (rate == rate_table[i].rate)
+			return &rate_table[i];
+
+	return NULL;
+}
+
+static unsigned long clk_pll1416x_recalc_rate(struct clk *clk)
+{
+	struct clk_pll14xx *pll = to_clk_pll14xx(
+		(struct clk *)dev_get_driver_data(clk->dev));
+	u32 mdiv, pdiv, sdiv, pll_div;
+	u64 fvco = clk_get_parent_rate(clk);
+
+	pll_div = readl(pll->base + 4);
+	mdiv = (pll_div & MDIV_MASK) >> MDIV_SHIFT;
+	pdiv = (pll_div & PDIV_MASK) >> PDIV_SHIFT;
+	sdiv = (pll_div & SDIV_MASK) >> SDIV_SHIFT;
+
+	fvco *= mdiv;
+	do_div(fvco, pdiv << sdiv);
+
+	return fvco;
+}
+
+static unsigned long clk_pll1443x_recalc_rate(struct clk *clk)
+{
+	struct clk_pll14xx *pll = to_clk_pll14xx(
+		(struct clk *)dev_get_driver_data(clk->dev));
+	u32 mdiv, pdiv, sdiv, pll_div_ctl0, pll_div_ctl1;
+	short int kdiv;
+	u64 fvco = clk_get_parent_rate(clk);
+
+	pll_div_ctl0 = readl(pll->base + 4);
+	pll_div_ctl1 = readl(pll->base + 8);
+	mdiv = (pll_div_ctl0 & MDIV_MASK) >> MDIV_SHIFT;
+	pdiv = (pll_div_ctl0 & PDIV_MASK) >> PDIV_SHIFT;
+	sdiv = (pll_div_ctl0 & SDIV_MASK) >> SDIV_SHIFT;
+	kdiv = pll_div_ctl1 & KDIV_MASK;
+
+	/* fvco = (m * 65536 + k) * Fin / (p * 65536) */
+	fvco *= (mdiv * 65536 + kdiv);
+	pdiv *= 65536;
+
+	do_div(fvco, pdiv << sdiv);
+
+	return fvco;
+}
+
+static inline bool clk_pll1416x_mp_change(const struct imx_pll14xx_rate_table *rate,
+					  u32 pll_div)
+{
+	u32 old_mdiv, old_pdiv;
+
+	old_mdiv = (pll_div >> MDIV_SHIFT) & MDIV_MASK;
+	old_pdiv = (pll_div >> PDIV_SHIFT) & PDIV_MASK;
+
+	return rate->mdiv != old_mdiv || rate->pdiv != old_pdiv;
+}
+
+static inline bool clk_pll1443x_mpk_change(const struct imx_pll14xx_rate_table *rate,
+					  u32 pll_div_ctl0, u32 pll_div_ctl1)
+{
+	u32 old_mdiv, old_pdiv, old_kdiv;
+
+	old_mdiv = (pll_div_ctl0 >> MDIV_SHIFT) & MDIV_MASK;
+	old_pdiv = (pll_div_ctl0 >> PDIV_SHIFT) & PDIV_MASK;
+	old_kdiv = (pll_div_ctl1 >> KDIV_SHIFT) & KDIV_MASK;
+
+	return rate->mdiv != old_mdiv || rate->pdiv != old_pdiv ||
+		rate->kdiv != old_kdiv;
+}
+
+static inline bool clk_pll1443x_mp_change(const struct imx_pll14xx_rate_table *rate,
+					  u32 pll_div_ctl0, u32 pll_div_ctl1)
+{
+	u32 old_mdiv, old_pdiv, old_kdiv;
+
+	old_mdiv = (pll_div_ctl0 >> MDIV_SHIFT) & MDIV_MASK;
+	old_pdiv = (pll_div_ctl0 >> PDIV_SHIFT) & PDIV_MASK;
+	old_kdiv = (pll_div_ctl1 >> KDIV_SHIFT) & KDIV_MASK;
+
+	return rate->mdiv != old_mdiv || rate->pdiv != old_pdiv ||
+		rate->kdiv != old_kdiv;
+}
+
+static int clk_pll14xx_wait_lock(struct clk_pll14xx *pll)
+{
+	u32 val;
+
+	return readl_poll_timeout(pll->base, val, val & LOCK_TIMEOUT_US,
+			LOCK_TIMEOUT_US);
+}
+
+static ulong clk_pll1416x_set_rate(struct clk *clk, unsigned long drate)
+{
+	struct clk_pll14xx *pll = to_clk_pll14xx(
+		(struct clk *)dev_get_driver_data(clk->dev));
+	const struct imx_pll14xx_rate_table *rate;
+	u32 tmp, div_val;
+	int ret;
+
+	rate = imx_get_pll_settings(pll, drate);
+	if (!rate) {
+		pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__,
+		       drate, "xxxx");
+		return -EINVAL;
+	}
+
+	tmp = readl(pll->base + 4);
+
+	if (!clk_pll1416x_mp_change(rate, tmp)) {
+		tmp &= ~(SDIV_MASK) << SDIV_SHIFT;
+		tmp |= rate->sdiv << SDIV_SHIFT;
+		writel(tmp, pll->base + 4);
+
+		return clk_pll1416x_recalc_rate(clk);
+	}
+
+	/* Bypass clock and set lock to pll output lock */
+	tmp = readl(pll->base);
+	tmp |= LOCK_SEL_MASK;
+	writel(tmp, pll->base);
+
+	/* Enable RST */
+	tmp &= ~RST_MASK;
+	writel(tmp, pll->base);
+
+	div_val = (rate->mdiv << MDIV_SHIFT) | (rate->pdiv << PDIV_SHIFT) |
+		(rate->sdiv << SDIV_SHIFT);
+	writel(div_val, pll->base + 0x4);
+
+	/*
+	 * According to SPEC, t3 - t2 need to be greater than
+	 * 1us and 1/FREF, respectively.
+	 * FREF is FIN / Prediv, the prediv is [1, 63], so choose
+	 * 3us.
+	 */
+	udelay(3);
+
+	/* Disable RST */
+	tmp |= RST_MASK;
+	writel(tmp, pll->base);
+
+	/* Wait Lock */
+	ret = clk_pll14xx_wait_lock(pll);
+	if (ret)
+		return ret;
+
+	/* Bypass */
+	tmp &= ~BYPASS_MASK;
+	writel(tmp, pll->base);
+
+	return clk_pll1416x_recalc_rate(clk);
+}
+
+static ulong clk_pll1443x_set_rate(struct clk *clk, unsigned long drate)
+{
+	struct clk_pll14xx *pll = to_clk_pll14xx(
+		(struct clk *)dev_get_driver_data(clk->dev));
+	const struct imx_pll14xx_rate_table *rate;
+	u32 tmp, div_val;
+	int ret;
+
+	rate = imx_get_pll_settings(pll, drate);
+	if (!rate) {
+		pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__,
+		       drate, "===");
+		return -EINVAL;
+	}
+
+	tmp = readl(pll->base + 4);
+	div_val = readl(pll->base + 8);
+
+	if (!clk_pll1443x_mpk_change(rate, tmp, div_val)) {
+		tmp &= ~(SDIV_MASK) << SDIV_SHIFT;
+		tmp |= rate->sdiv << SDIV_SHIFT;
+		writel(tmp, pll->base + 4);
+
+		return clk_pll1443x_recalc_rate(clk);
+	}
+
+	/* Enable RST */
+	tmp = readl(pll->base);
+	tmp &= ~RST_MASK;
+	writel(tmp, pll->base);
+
+	div_val = (rate->mdiv << MDIV_SHIFT) | (rate->pdiv << PDIV_SHIFT) |
+		(rate->sdiv << SDIV_SHIFT);
+	writel(div_val, pll->base + 0x4);
+	writel(rate->kdiv << KDIV_SHIFT, pll->base + 0x8);
+
+	/*
+	 * According to SPEC, t3 - t2 need to be greater than
+	 * 1us and 1/FREF, respectively.
+	 * FREF is FIN / Prediv, the prediv is [1, 63], so choose
+	 * 3us.
+	 */
+	udelay(3);
+
+	/* Disable RST */
+	tmp |= RST_MASK;
+	writel(tmp, pll->base);
+
+	/* Wait Lock*/
+	ret = clk_pll14xx_wait_lock(pll);
+	if (ret)
+		return ret;
+
+	/* Bypass */
+	tmp &= ~BYPASS_MASK;
+	writel(tmp, pll->base);
+
+	return clk_pll1443x_recalc_rate(clk);
+}
+
+static int clk_pll14xx_prepare(struct clk *clk)
+{
+	struct clk_pll14xx *pll = to_clk_pll14xx(
+		(struct clk *)dev_get_driver_data(clk->dev));
+	u32 val;
+
+	/*
+	 * RESETB = 1 from 0, PLL starts its normal
+	 * operation after lock time
+	 */
+	val = readl(pll->base + GNRL_CTL);
+	val |= RST_MASK;
+	writel(val, pll->base + GNRL_CTL);
+
+	return clk_pll14xx_wait_lock(pll);
+}
+
+static int clk_pll14xx_unprepare(struct clk *clk)
+{
+	struct clk_pll14xx *pll = to_clk_pll14xx(
+		(struct clk *)dev_get_driver_data(clk->dev));
+	u32 val;
+
+	/*
+	 * Set RST to 0, power down mode is enabled and
+	 * every digital block is reset
+	 */
+	val = readl(pll->base + GNRL_CTL);
+	val &= ~RST_MASK;
+	writel(val, pll->base + GNRL_CTL);
+
+	return 0;
+}
+
+static const struct clk_ops clk_pll1416x_ops = {
+	.enable		= clk_pll14xx_prepare,
+	.disable	= clk_pll14xx_unprepare,
+	.set_rate	= clk_pll1416x_set_rate,
+	.get_rate	= clk_pll1416x_recalc_rate,
+};
+
+static const struct clk_ops clk_pll1443x_ops = {
+	.enable		= clk_pll14xx_prepare,
+	.disable	= clk_pll14xx_unprepare,
+	.set_rate	= clk_pll1443x_set_rate,
+	.get_rate	= clk_pll1443x_recalc_rate,
+};
+
+struct clk *imx_clk_pll14xx(const char *name, const char *parent_name,
+			    void __iomem *base,
+			    const struct imx_pll14xx_clk *pll_clk)
+{
+	struct clk_pll14xx *pll;
+	struct clk *clk;
+	char *type_name;
+	int ret;
+
+	pll = kzalloc(sizeof(*pll), GFP_KERNEL);
+	if (!pll)
+		return ERR_PTR(-ENOMEM);
+
+	switch (pll_clk->type) {
+	case PLL_1416X:
+		type_name = UBOOT_DM_CLK_IMX_PLL1416X;
+		break;
+	case PLL_1443X:
+		type_name = UBOOT_DM_CLK_IMX_PLL1443X;
+		break;
+	default:
+		pr_err("%s: Unknown pll type for pll clk %s\n",
+		       __func__, name);
+		return ERR_PTR(-EINVAL);
+	};
+
+	pll->base = base;
+	pll->type = pll_clk->type;
+	pll->rate_table = pll_clk->rate_table;
+	pll->rate_count = pll_clk->rate_count;
+
+	clk = &pll->clk;
+
+	ret = clk_register(clk, type_name, (ulong)clk, name, parent_name);
+	if (ret) {
+		pr_err("%s: failed to register pll %s %d\n",
+		       __func__, name, ret);
+		kfree(pll);
+		return ERR_PTR(ret);
+	}
+
+	return clk;
+}
+
+U_BOOT_DRIVER(clk_pll1443x) = {
+	.name	= UBOOT_DM_CLK_IMX_PLL1443X,
+	.id	= UCLASS_CLK,
+	.ops	= &clk_pll1443x_ops,
+	.flags = DM_FLAG_PRE_RELOC,
+};
+
+U_BOOT_DRIVER(clk_pll1416x) = {
+	.name	= UBOOT_DM_CLK_IMX_PLL1416X,
+	.id	= UCLASS_CLK,
+	.ops	= &clk_pll1416x_ops,
+	.flags = DM_FLAG_PRE_RELOC,
+};
diff --git a/drivers/clk/imx/clk.h b/drivers/clk/imx/clk.h
index aa6e81ff13..b5330cdf51 100644
--- a/drivers/clk/imx/clk.h
+++ b/drivers/clk/imx/clk.h
@@ -26,6 +26,31 @@ enum imx_pllv3_type {
 	IMX_PLLV3_DDR_IMX7,
 };
 
+enum imx_pll14xx_type {
+	PLL_1416X,
+	PLL_1443X,
+};
+
+/* NOTE: Rate table should be kept sorted in descending order. */
+struct imx_pll14xx_rate_table {
+	unsigned int rate;
+	unsigned int pdiv;
+	unsigned int mdiv;
+	unsigned int sdiv;
+	unsigned int kdiv;
+};
+
+struct imx_pll14xx_clk {
+	enum imx_pll14xx_type type;
+	const struct imx_pll14xx_rate_table *rate_table;
+	int rate_count;
+	int flags;
+};
+
+struct clk *imx_clk_pll14xx(const char *name, const char *parent_name,
+			    void __iomem *base,
+			    const struct imx_pll14xx_clk *pll_clk);
+
 struct clk *clk_register_gate2(struct device *dev, const char *name,
 		const char *parent_name, unsigned long flags,
 		void __iomem *reg, u8 bit_idx, u8 cgr_val,
-- 
2.16.4

[U-Boot] [i.MX8MM+CCF 38/41] clk: add composite clk support

[Peng Fan]

Import clk composite clk support from Linux Kernel 5.1-rc5

Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 drivers/clk/Kconfig          |  14 ++++
 drivers/clk/Makefile         |   1 +
 drivers/clk/clk-composite.c  | 165 +++++++++++++++++++++++++++++++++++++++++++
 include/linux/clk-provider.h |  22 ++++++
 4 files changed, 202 insertions(+)
 create mode 100644 drivers/clk/clk-composite.c

diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index 9df3bc731a..3735e235f5 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -53,6 +53,13 @@ config SPL_CLK_CCF
 	  Enable this option if you want to (re-)use the Linux kernel's Common
 	  Clock Framework [CCF] code in U-Boot's SPL.
 
+config SPL_CLK_COMPOSITE_CCF
+	bool "SPL Common Clock Framework [CCF] composite clk support "
+	depends on SPL_CLK_CCF
+	help
+	  Enable this option if you want to (re-)use the Linux kernel's Common
+	  Clock Framework [CCF] composite code in U-Boot's SPL.
+
 config CLK_CCF
 	bool "Common Clock Framework [CCF] support "
 	depends on CLK
@@ -60,6 +67,13 @@ config CLK_CCF
 	  Enable this option if you want to (re-)use the Linux kernel's Common
 	  Clock Framework [CCF] code in U-Boot's clock driver.
 
+config CLK_COMPOSITE_CCF
+	bool "Common Clock Framework [CCF] composite clk support "
+	depends on CLK_CCF
+	help
+	  Enable this option if you want to (re-)use the Linux kernel's Common
+	  Clock Framework [CCF] composite code in U-Boot's clock driver.
+
 config CLK_STM32F
 	bool "Enable clock driver support for STM32F family"
 	depends on CLK && (STM32F7 || STM32F4)
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 0bc8f7e5ce..6c71b0fc16 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -9,6 +9,7 @@ obj-$(CONFIG_$(SPL_TPL_)CLK) += clk_fixed_rate.o
 obj-$(CONFIG_$(SPL_TPL_)CLK) += clk_fixed_factor.o
 obj-$(CONFIG_$(SPL_TPL_)CLK_CCF) += clk.o clk-divider.o clk-mux.o clk-gate.o
 obj-$(CONFIG_$(SPL_TPL_)CLK_CCF) += clk-fixed-factor.o
+obj-$(CONFIG_$(SPL_TPL_)CLK_COMPOSITE_CCF) += clk-composite.o
 
 obj-y += imx/
 obj-y += tegra/
diff --git a/drivers/clk/clk-composite.c b/drivers/clk/clk-composite.c
new file mode 100644
index 0000000000..18adfd9850
--- /dev/null
+++ b/drivers/clk/clk-composite.c
@@ -0,0 +1,165 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2013 NVIDIA CORPORATION.  All rights reserved.
+ * Copyright 2019 NXP
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <malloc.h>
+#include <clk-uclass.h>
+#include <dm/device.h>
+#include <linux/clk-provider.h>
+#include <clk.h>
+
+#include "clk.h"
+
+#define UBOOT_DM_CLK_COMPOSITE "clk_composite"
+
+static u8 clk_composite_get_parent(struct clk *clk)
+{
+	struct clk_composite *composite = to_clk_composite(
+		clk_dev_binded(clk) ?
+		(struct clk *)dev_get_driver_data(clk->dev) : clk);
+	struct clk *mux = composite->mux;
+
+	return clk_mux_get_parent(mux);
+}
+
+static int clk_composite_set_parent(struct clk *clk, struct clk *parent)
+{
+	struct clk_composite *composite = to_clk_composite(
+		clk_dev_binded(clk) ?
+		(struct clk *)dev_get_driver_data(clk->dev) : clk);
+	const struct clk_ops *mux_ops = composite->mux_ops;
+	struct clk *mux = composite->mux;
+
+	return mux_ops->set_parent(mux, parent);
+}
+
+static unsigned long clk_composite_recalc_rate(struct clk *clk)
+{
+	struct clk_composite *composite = to_clk_composite(
+		clk_dev_binded(clk) ?
+		(struct clk *)dev_get_driver_data(clk->dev) : clk);
+	const struct clk_ops *rate_ops = composite->rate_ops;
+	struct clk *rate = composite->rate;
+
+	return rate_ops->get_rate(rate);
+}
+
+static ulong clk_composite_set_rate(struct clk *clk, unsigned long rate)
+{
+	struct clk_composite *composite = to_clk_composite(
+		clk_dev_binded(clk) ?
+		(struct clk *)dev_get_driver_data(clk->dev) : clk);
+	const struct clk_ops *rate_ops = composite->rate_ops;
+	struct clk *clk_rate = composite->rate;
+
+	return rate_ops->set_rate(clk_rate, rate);
+}
+
+static int clk_composite_enable(struct clk *clk)
+{
+	struct clk_composite *composite = to_clk_composite(
+		clk_dev_binded(clk) ?
+		(struct clk *)dev_get_driver_data(clk->dev) : clk);
+	const struct clk_ops *gate_ops = composite->gate_ops;
+	struct clk *gate = composite->gate;
+
+	return gate_ops->enable(gate);
+}
+
+static int clk_composite_disable(struct clk *clk)
+{
+	struct clk_composite *composite = to_clk_composite(
+		clk_dev_binded(clk) ?
+		(struct clk *)dev_get_driver_data(clk->dev) : clk);
+	const struct clk_ops *gate_ops = composite->gate_ops;
+	struct clk *gate = composite->gate;
+
+	gate_ops->disable(gate);
+
+	return 0;
+}
+
+struct clk_ops clk_composite_ops = {
+	/* This will be set according to clk_register_composite */
+};
+
+struct clk *clk_register_composite(struct device *dev, const char *name,
+			const char * const *parent_names, int num_parents,
+			struct clk *mux, const struct clk_ops *mux_ops,
+			struct clk *rate, const struct clk_ops *rate_ops,
+			struct clk *gate, const struct clk_ops *gate_ops,
+			unsigned long flags)
+{
+	struct clk *clk;
+	struct clk_composite *composite;
+	int ret;
+	struct clk_ops *composite_ops = &clk_composite_ops;
+
+	composite = kzalloc(sizeof(*composite), GFP_KERNEL);
+	if (!composite)
+		return ERR_PTR(-ENOMEM);
+
+	if (mux && mux_ops) {
+		composite->mux = mux;
+		composite->mux_ops = mux_ops;
+		if (mux_ops->set_parent)
+			composite_ops->set_parent = clk_composite_set_parent;
+		mux->data = (ulong)composite;
+	}
+
+	if (rate && rate_ops) {
+		if (!rate_ops->get_rate) {
+			clk = ERR_PTR(-EINVAL);
+			goto err;
+		}
+		composite_ops->get_rate = clk_composite_recalc_rate;
+
+		/* .set_rate requires either .round_rate or .determine_rate */
+		if (rate_ops->set_rate) {
+				composite_ops->set_rate =
+						clk_composite_set_rate;
+		}
+
+		composite->rate = rate;
+		composite->rate_ops = rate_ops;
+		rate->data = (ulong)composite;
+	}
+
+	if (gate && gate_ops) {
+		if (!gate_ops->enable || !gate_ops->disable) {
+			clk = ERR_PTR(-EINVAL);
+			goto err;
+		}
+
+		composite->gate = gate;
+		composite->gate_ops = gate_ops;
+		composite_ops->enable = clk_composite_enable;
+		composite_ops->disable = clk_composite_disable;
+		gate->data = (ulong)composite;
+	}
+
+	clk = &composite->clk;
+	ret = clk_register(clk, UBOOT_DM_CLK_COMPOSITE, (ulong)clk,
+			   name, parent_names[clk_composite_get_parent(clk)]);
+	if (ret) {
+		clk = ERR_PTR(ret);
+		goto err;
+	}
+
+	return clk;
+
+err:
+	kfree(composite);
+	return clk;
+}
+
+U_BOOT_DRIVER(clk_composite) = {
+	.name	= UBOOT_DM_CLK_COMPOSITE,
+	.id	= UCLASS_CLK,
+	.ops	= &clk_composite_ops,
+	.flags = DM_FLAG_PRE_RELOC,
+};
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index b2bed768b6..490713adb6 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -119,6 +119,28 @@ struct clk_fixed_rate {
 
 #define to_clk_fixed_rate(dev)	((struct clk_fixed_rate *)dev_get_platdata(dev))
 
+struct clk_composite {
+	struct clk	clk;
+	struct clk_ops	ops;
+
+	struct clk	*mux;
+	struct clk	*rate;
+	struct clk	*gate;
+
+	const struct clk_ops	*mux_ops;
+	const struct clk_ops	*rate_ops;
+	const struct clk_ops	*gate_ops;
+};
+
+#define to_clk_composite(_clk) container_of(_clk, struct clk_composite, clk)
+
+struct clk *clk_register_composite(struct device *dev, const char *name,
+		const char * const *parent_names, int num_parents,
+		struct clk *mux_clk, const struct clk_ops *mux_ops,
+		struct clk *rate_clk, const struct clk_ops *rate_ops,
+		struct clk *gate_clk, const struct clk_ops *gate_ops,
+		unsigned long flags);
+
 int clk_register(struct clk *clk, const char *drv_name,
 		 ulong drv_data, const char *name,
 		 const char *parent_name);
-- 
2.16.4

[U-Boot] [i.MX8MM+CCF 39/41] clk: imx: add i.MX8MM composite clk support

[Peng Fan]

Import i.MX8MM composite clk from Linux Kernel

Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 drivers/clk/imx/clk-composite-8m.c | 170 +++++++++++++++++++++++++++++++++++++
 include/linux/clk-provider.h       |   3 +
 2 files changed, 173 insertions(+)
 create mode 100644 drivers/clk/imx/clk-composite-8m.c

diff --git a/drivers/clk/imx/clk-composite-8m.c b/drivers/clk/imx/clk-composite-8m.c
new file mode 100644
index 0000000000..57ebbc3bb0
--- /dev/null
+++ b/drivers/clk/imx/clk-composite-8m.c
@@ -0,0 +1,170 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2019 NXP
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <malloc.h>
+#include <clk-uclass.h>
+#include <dm/device.h>
+#include <linux/clk-provider.h>
+#include <clk.h>
+#include "clk.h"
+
+#define UBOOT_DM_CLK_IMX_COMPOSITE "imx_clk_composite"
+
+#define PCG_PREDIV_SHIFT	16
+#define PCG_PREDIV_WIDTH	3
+#define PCG_PREDIV_MAX		8
+
+#define PCG_DIV_SHIFT		0
+#define PCG_DIV_WIDTH		6
+#define PCG_DIV_MAX		64
+
+#define PCG_PCS_SHIFT		24
+#define PCG_PCS_MASK		0x7
+
+#define PCG_CGC_SHIFT		28
+
+static unsigned long imx8m_clk_composite_divider_recalc_rate(struct clk *clk)
+{
+	struct clk_divider *divider = (struct clk_divider *)to_clk_divider(clk);
+	struct clk_composite *composite = (struct clk_composite *)clk->data;
+	ulong parent_rate = clk_get_parent_rate(&composite->clk);
+	unsigned long prediv_rate;
+	unsigned int prediv_value;
+	unsigned int div_value;
+
+	debug("%s: name %s prate: %lu reg: %p\n", __func__,
+	      (&composite->clk)->dev->name, parent_rate, divider->reg);
+	prediv_value = readl(divider->reg) >> divider->shift;
+	prediv_value &= clk_div_mask(divider->width);
+
+	prediv_rate = divider_recalc_rate(clk, parent_rate, prediv_value,
+					  NULL, divider->flags,
+					  divider->width);
+
+	div_value = readl(divider->reg) >> PCG_DIV_SHIFT;
+	div_value &= clk_div_mask(PCG_DIV_WIDTH);
+
+	return divider_recalc_rate(clk, prediv_rate, div_value, NULL,
+				   divider->flags, PCG_DIV_WIDTH);
+}
+
+static int imx8m_clk_composite_compute_dividers(unsigned long rate,
+						unsigned long parent_rate,
+						int *prediv, int *postdiv)
+{
+	int div1, div2;
+	int error = INT_MAX;
+	int ret = -EINVAL;
+
+	*prediv = 1;
+	*postdiv = 1;
+
+	for (div1 = 1; div1 <= PCG_PREDIV_MAX; div1++) {
+		for (div2 = 1; div2 <= PCG_DIV_MAX; div2++) {
+			int new_error = ((parent_rate / div1) / div2) - rate;
+
+			if (abs(new_error) < abs(error)) {
+				*prediv = div1;
+				*postdiv = div2;
+				error = new_error;
+				ret = 0;
+			}
+		}
+	}
+	return ret;
+}
+
+/*
+ * The clk are not binded to a dev, because it is part of composite clk
+ * use composite clk to get dev
+ */
+static ulong imx8m_clk_composite_divider_set_rate(struct clk *clk,
+						  unsigned long rate)
+{
+	struct clk_divider *divider = (struct clk_divider *)to_clk_divider(clk);
+	struct clk_composite *composite = (struct clk_composite *)clk->data;
+	ulong parent_rate = clk_get_parent_rate(&composite->clk);
+	int prediv_value;
+	int div_value;
+	int ret;
+	u32 val;
+
+	ret = imx8m_clk_composite_compute_dividers(rate, parent_rate,
+						   &prediv_value, &div_value);
+	if (ret)
+		return -EINVAL;
+
+	val = readl(divider->reg);
+	val &= ~((clk_div_mask(divider->width) << divider->shift) |
+			(clk_div_mask(PCG_DIV_WIDTH) << PCG_DIV_SHIFT));
+
+	val |= (u32)(prediv_value  - 1) << divider->shift;
+	val |= (u32)(div_value - 1) << PCG_DIV_SHIFT;
+	writel(val, divider->reg);
+
+	return clk_get_rate(&composite->clk);
+}
+
+static const struct clk_ops imx8m_clk_composite_divider_ops = {
+	.get_rate = imx8m_clk_composite_divider_recalc_rate,
+	.set_rate = imx8m_clk_composite_divider_set_rate,
+};
+
+struct clk *imx8m_clk_composite_flags(const char *name,
+				      const char * const *parent_names,
+				      int num_parents, void __iomem *reg,
+				      unsigned long flags)
+{
+	struct clk *clk = ERR_PTR(-ENOMEM);
+	struct clk_divider *div = NULL;
+	struct clk_gate *gate = NULL;
+	struct clk_mux *mux = NULL;
+
+	mux = kzalloc(sizeof(*mux), GFP_KERNEL);
+	if (!mux)
+		goto fail;
+
+	mux->reg = reg;
+	mux->shift = PCG_PCS_SHIFT;
+	mux->mask = PCG_PCS_MASK;
+	mux->num_parents = num_parents;
+	mux->flags = flags;
+	mux->parent_names = parent_names;
+
+	div = kzalloc(sizeof(*div), GFP_KERNEL);
+	if (!div)
+		goto fail;
+
+	div->reg = reg;
+	div->shift = PCG_PREDIV_SHIFT;
+	div->width = PCG_PREDIV_WIDTH;
+	div->flags = CLK_DIVIDER_ROUND_CLOSEST | flags;
+
+	gate = kzalloc(sizeof(*gate), GFP_KERNEL);
+	if (!gate)
+		goto fail;
+
+	gate->reg = reg;
+	gate->bit_idx = PCG_CGC_SHIFT;
+	gate->flags = flags;
+
+	clk = clk_register_composite(NULL, name,
+				     parent_names, num_parents,
+				     &mux->clk, &clk_mux_ops, &div->clk,
+				     &imx8m_clk_composite_divider_ops,
+				     &gate->clk, &clk_gate_ops, flags);
+	if (IS_ERR(clk))
+		goto fail;
+
+	return clk;
+
+fail:
+	kfree(gate);
+	kfree(div);
+	kfree(mux);
+	return ERR_CAST(clk);
+}
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index 490713adb6..568a0e87d6 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -102,6 +102,9 @@ struct clk_divider {
 #define CLK_DIVIDER_READ_ONLY		BIT(5)
 #define CLK_DIVIDER_MAX_AT_ZERO		BIT(6)
 extern const struct clk_ops clk_divider_ops;
+unsigned long divider_recalc_rate(struct clk *hw, unsigned long parent_rate,
+		unsigned int val, const struct clk_div_table *table,
+		unsigned long flags, unsigned long width);
 
 struct clk_fixed_factor {
 	struct clk	clk;
-- 
2.16.4

[U-Boot] [i.MX8MM+CCF 40/41] clk: imx: add i.MX8MM clk driver

[Peng Fan]

Add i.MX8MM clk driver support.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 drivers/clk/imx/Makefile     |   1 +
 drivers/clk/imx/clk-imx8mm.c | 415 +++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 416 insertions(+)
 create mode 100644 drivers/clk/imx/clk-imx8mm.c

diff --git a/drivers/clk/imx/Makefile b/drivers/clk/imx/Makefile
index beba3bff39..e8cac4127a 100644
--- a/drivers/clk/imx/Makefile
+++ b/drivers/clk/imx/Makefile
@@ -5,3 +5,4 @@
 obj-$(CONFIG_$(SPL_TPL_)CLK_CCF) += clk-gate2.o clk-pllv3.o clk-pfd.o
 obj-$(CONFIG_CLK_IMX6Q) += clk-imx6q.o
 obj-$(CONFIG_CLK_IMX8) += clk-imx8.o
+obj-$(CONFIG_CLK_IMX8MM) += clk-imx8mm.o clk-pll14xx.o clk-composite-8m.o
diff --git a/drivers/clk/imx/clk-imx8mm.c b/drivers/clk/imx/clk-imx8mm.c
new file mode 100644
index 0000000000..329fd8ed06
--- /dev/null
+++ b/drivers/clk/imx/clk-imx8mm.c
@@ -0,0 +1,415 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2019 NXP
+ * Peng Fan <peng.fan@nxp.com>
+ */
+
+#include <common.h>
+#include <clk.h>
+#include <clk-uclass.h>
+#include <dm.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/imx-regs.h>
+#include <dt-bindings/clock/imx8mm-clock.h>
+
+#include "clk.h"
+
+#define PLL_1416X_RATE(_rate, _m, _p, _s)		\
+	{						\
+		.rate	=	(_rate),		\
+		.mdiv	=	(_m),			\
+		.pdiv	=	(_p),			\
+		.sdiv	=	(_s),			\
+	}
+
+#define PLL_1443X_RATE(_rate, _m, _p, _s, _k)		\
+	{						\
+		.rate	=	(_rate),		\
+		.mdiv	=	(_m),			\
+		.pdiv	=	(_p),			\
+		.sdiv	=	(_s),			\
+		.kdiv	=	(_k),			\
+	}
+
+static const struct imx_pll14xx_rate_table imx8mm_pll1416x_tbl[] = {
+	PLL_1416X_RATE(1800000000U, 225, 3, 0),
+	PLL_1416X_RATE(1600000000U, 200, 3, 0),
+	PLL_1416X_RATE(1200000000U, 300, 3, 1),
+	PLL_1416X_RATE(1000000000U, 250, 3, 1),
+	PLL_1416X_RATE(800000000U,  200, 3, 1),
+	PLL_1416X_RATE(750000000U,  250, 2, 2),
+	PLL_1416X_RATE(700000000U,  350, 3, 2),
+	PLL_1416X_RATE(600000000U,  300, 3, 2),
+};
+
+static const struct imx_pll14xx_rate_table imx8mm_drampll_tbl[] = {
+	PLL_1443X_RATE(650000000U, 325, 3, 2, 0),
+};
+
+static struct imx_pll14xx_clk imx8mm_dram_pll __initdata = {
+		.type = PLL_1443X,
+		.rate_table = imx8mm_drampll_tbl,
+		.rate_count = ARRAY_SIZE(imx8mm_drampll_tbl),
+};
+
+static struct imx_pll14xx_clk imx8mm_arm_pll __initdata = {
+		.type = PLL_1416X,
+		.rate_table = imx8mm_pll1416x_tbl,
+		.rate_count = ARRAY_SIZE(imx8mm_pll1416x_tbl),
+};
+
+static struct imx_pll14xx_clk imx8mm_sys_pll __initdata = {
+		.type = PLL_1416X,
+		.rate_table = imx8mm_pll1416x_tbl,
+		.rate_count = ARRAY_SIZE(imx8mm_pll1416x_tbl),
+};
+
+static const char *pll_ref_sels[] = { "clock-osc-24m", "dummy", "dummy", "dummy", };
+static const char *dram_pll_bypass_sels[] = {"dram_pll", "dram_pll_ref_sel", };
+static const char *arm_pll_bypass_sels[] = {"arm_pll", "arm_pll_ref_sel", };
+static const char *sys_pll1_bypass_sels[] = {"sys_pll1", "sys_pll1_ref_sel", };
+static const char *sys_pll2_bypass_sels[] = {"sys_pll2", "sys_pll2_ref_sel", };
+static const char *sys_pll3_bypass_sels[] = {"sys_pll3", "sys_pll3_ref_sel", };
+
+static const char *imx8mm_a53_sels[] = {"clock-osc-24m", "arm_pll_out", "sys_pll2_500m", "sys_pll2_1000m",
+					"sys_pll1_800m", "sys_pll1_400m", "audio_pll1_out", "sys_pll3_out", };
+
+static const char *imx8mm_ahb_sels[] = {"osc_24m", "sys_pll1_133m", "sys_pll1_800m", "sys_pll1_400m",
+					"sys_pll2_125m", "sys_pll3_out", "audio_pll1_out", "video_pll1_out", };
+
+static const char *imx8mm_enet_axi_sels[] = {"clock-osc-24m", "sys_pll1_266m", "sys_pll1_800m", "sys_pll2_250m",
+					     "sys_pll2_200m", "audio_pll1_out", "video_pll1_out", "sys_pll3_out", };
+
+static const char *imx8mm_nand_usdhc_sels[] = {"clock-osc-24m", "sys_pll1_266m", "sys_pll1_800m", "sys_pll2_200m",
+					       "sys_pll1_133m", "sys_pll3_out", "sys_pll2_250m", "audio_pll1_out", };
+
+static const char *imx8mm_usdhc1_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sys_pll1_800m", "sys_pll2_500m",
+					   "sys_pll3_out", "sys_pll1_266m", "audio_pll2_out", "sys_pll1_100m", };
+
+static const char *imx8mm_usdhc2_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sys_pll1_800m", "sys_pll2_500m",
+					   "sys_pll3_out", "sys_pll1_266m", "audio_pll2_out", "sys_pll1_100m", };
+
+static const char *imx8mm_i2c1_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m", "sys_pll3_out", "audio_pll1_out",
+					 "video_pll1_out", "audio_pll2_out", "sys_pll1_133m", };
+
+static const char *imx8mm_i2c2_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m", "sys_pll3_out", "audio_pll1_out",
+					 "video_pll1_out", "audio_pll2_out", "sys_pll1_133m", };
+
+static const char *imx8mm_i2c3_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m", "sys_pll3_out", "audio_pll1_out",
+					 "video_pll1_out", "audio_pll2_out", "sys_pll1_133m", };
+
+static const char *imx8mm_i2c4_sels[] = {"clock-osc-24m", "sys_pll1_160m", "sys_pll2_50m", "sys_pll3_out", "audio_pll1_out",
+					 "video_pll1_out", "audio_pll2_out", "sys_pll1_133m", };
+
+static const char *imx8mm_wdog_sels[] = {"clock-osc-24m", "sys_pll1_133m", "sys_pll1_160m", "vpu_pll_out",
+					 "sys_pll2_125m", "sys_pll3_out", "sys_pll1_80m", "sys_pll2_166m", };
+
+static const char *imx8mm_usdhc3_sels[] = {"clock-osc-24m", "sys_pll1_400m", "sys_pll1_800m", "sys_pll2_500m",
+					   "sys_pll3_out", "sys_pll1_266m", "audio_pll2_clk", "sys_pll1_100m", };
+
+
+static ulong imx8mm_clk_get_rate(struct clk *clk)
+{
+	struct clk *c;
+	int ret;
+
+	debug("%s(#%lu)\n", __func__, clk->id);
+
+	ret = clk_get_by_id(clk->id, &c);
+	if (ret)
+		return ret;
+
+	return clk_get_rate(c);
+}
+
+static ulong imx8mm_clk_set_rate(struct clk *clk, unsigned long rate)
+{
+	struct clk *c;
+	int ret = 0;
+
+	debug("%s(#%lu), rate: %lu\n", __func__, clk->id, rate);
+
+	ret = clk_get_by_id(clk->id, &c);
+	if (ret)
+		return ret;
+
+	return clk_set_rate(c, rate);
+}
+
+static int __imx8mm_clk_enable(struct clk *clk, bool enable)
+{
+	struct clk *c;
+	int ret = 0;
+
+	debug("%s(#%lu) en: %d\n", __func__, clk->id, enable);
+
+	ret = clk_get_by_id(clk->id, &c);
+	if (ret)
+		return ret;
+
+	if (enable)
+		ret = clk_enable(c);
+	else
+		ret = clk_disable(c);
+
+	return ret;
+}
+
+static int imx8mm_clk_disable(struct clk *clk)
+{
+	return __imx8mm_clk_enable(clk, 0);
+}
+
+static int imx8mm_clk_enable(struct clk *clk)
+{
+	return __imx8mm_clk_enable(clk, 1);
+}
+
+static struct clk_ops imx8mm_clk_ops = {
+	.set_rate = imx8mm_clk_set_rate,
+	.get_rate = imx8mm_clk_get_rate,
+	.enable = imx8mm_clk_enable,
+	.disable = imx8mm_clk_disable,
+};
+
+static int imx8mm_clk_probe(struct udevice *dev)
+{
+	void __iomem *base;
+
+	base = (void *)ANATOP_BASE_ADDR;
+
+	clk_dm(IMX8MM_DRAM_PLL_REF_SEL,
+	       imx_clk_mux("dram_pll_ref_sel", base + 0x50, 0, 2,
+			   pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
+	clk_dm(IMX8MM_ARM_PLL_REF_SEL,
+	       imx_clk_mux("arm_pll_ref_sel", base + 0x84, 0, 2,
+			   pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
+	clk_dm(IMX8MM_SYS_PLL1_REF_SEL,
+	       imx_clk_mux("sys_pll1_ref_sel", base + 0x94, 0, 2,
+			   pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
+	clk_dm(IMX8MM_SYS_PLL2_REF_SEL,
+	       imx_clk_mux("sys_pll2_ref_sel", base + 0x104, 0, 2,
+			   pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
+	clk_dm(IMX8MM_SYS_PLL3_REF_SEL,
+	       imx_clk_mux("sys_pll3_ref_sel", base + 0x114, 0, 2,
+			   pll_ref_sels, ARRAY_SIZE(pll_ref_sels)));
+
+	clk_dm(IMX8MM_DRAM_PLL,
+	       imx_clk_pll14xx("dram_pll", "dram_pll_ref_sel",
+			       base + 0x50, &imx8mm_dram_pll));
+	clk_dm(IMX8MM_ARM_PLL,
+	       imx_clk_pll14xx("arm_pll", "arm_pll_ref_sel",
+			       base + 0x84, &imx8mm_arm_pll));
+	clk_dm(IMX8MM_SYS_PLL1,
+	       imx_clk_pll14xx("sys_pll1", "sys_pll1_ref_sel",
+			       base + 0x94, &imx8mm_sys_pll));
+	clk_dm(IMX8MM_SYS_PLL2,
+	       imx_clk_pll14xx("sys_pll2", "sys_pll2_ref_sel",
+			       base + 0x104, &imx8mm_sys_pll));
+	clk_dm(IMX8MM_SYS_PLL3,
+	       imx_clk_pll14xx("sys_pll3", "sys_pll3_ref_sel",
+			       base + 0x114, &imx8mm_sys_pll));
+
+	/* PLL bypass out */
+	clk_dm(IMX8MM_DRAM_PLL_BYPASS,
+	       imx_clk_mux_flags("dram_pll_bypass", base + 0x50, 4, 1,
+				 dram_pll_bypass_sels,
+				 ARRAY_SIZE(dram_pll_bypass_sels),
+				 CLK_SET_RATE_PARENT));
+	clk_dm(IMX8MM_ARM_PLL_BYPASS,
+	       imx_clk_mux_flags("arm_pll_bypass", base + 0x84, 4, 1,
+				 arm_pll_bypass_sels,
+				 ARRAY_SIZE(arm_pll_bypass_sels),
+				 CLK_SET_RATE_PARENT));
+	clk_dm(IMX8MM_SYS_PLL1_BYPASS,
+	       imx_clk_mux_flags("sys_pll1_bypass", base + 0x94, 4, 1,
+				 sys_pll1_bypass_sels,
+				 ARRAY_SIZE(sys_pll1_bypass_sels),
+				 CLK_SET_RATE_PARENT));
+	clk_dm(IMX8MM_SYS_PLL2_BYPASS,
+	       imx_clk_mux_flags("sys_pll2_bypass", base + 0x104, 4, 1,
+				 sys_pll2_bypass_sels,
+				 ARRAY_SIZE(sys_pll2_bypass_sels),
+				 CLK_SET_RATE_PARENT));
+	clk_dm(IMX8MM_SYS_PLL3_BYPASS,
+	       imx_clk_mux_flags("sys_pll3_bypass", base + 0x114, 4, 1,
+				 sys_pll3_bypass_sels,
+				 ARRAY_SIZE(sys_pll3_bypass_sels),
+				 CLK_SET_RATE_PARENT));
+
+	/* PLL out gate */
+	clk_dm(IMX8MM_DRAM_PLL_OUT,
+	       imx_clk_gate("dram_pll_out", "dram_pll_bypass",
+			    base + 0x50, 13));
+	clk_dm(IMX8MM_ARM_PLL_OUT,
+	       imx_clk_gate("arm_pll_out", "arm_pll_bypass",
+			    base + 0x84, 13));
+	clk_dm(IMX8MM_SYS_PLL1_OUT,
+	       imx_clk_gate("sys_pll1_out", "sys_pll1_bypass",
+			    base + 0x94, 13));
+	clk_dm(IMX8MM_SYS_PLL2_OUT,
+	       imx_clk_gate("sys_pll2_out", "sys_pll2_bypass",
+			    base + 0x104, 13));
+	clk_dm(IMX8MM_SYS_PLL3_OUT,
+	       imx_clk_gate("sys_pll3_out", "sys_pll3_bypass",
+			    base + 0x114, 13));
+
+	/* SYS PLL fixed output */
+	clk_dm(IMX8MM_SYS_PLL1_40M,
+	       imx_clk_fixed_factor("sys_pll1_40m", "sys_pll1_out", 1, 20));
+	clk_dm(IMX8MM_SYS_PLL1_80M,
+	       imx_clk_fixed_factor("sys_pll1_80m", "sys_pll1_out", 1, 10));
+	clk_dm(IMX8MM_SYS_PLL1_100M,
+	       imx_clk_fixed_factor("sys_pll1_100m", "sys_pll1_out", 1, 8));
+	clk_dm(IMX8MM_SYS_PLL1_133M,
+	       imx_clk_fixed_factor("sys_pll1_133m", "sys_pll1_out", 1, 6));
+	clk_dm(IMX8MM_SYS_PLL1_160M,
+	       imx_clk_fixed_factor("sys_pll1_160m", "sys_pll1_out", 1, 5));
+	clk_dm(IMX8MM_SYS_PLL1_200M,
+	       imx_clk_fixed_factor("sys_pll1_200m", "sys_pll1_out", 1, 4));
+	clk_dm(IMX8MM_SYS_PLL1_266M,
+	       imx_clk_fixed_factor("sys_pll1_266m", "sys_pll1_out", 1, 3));
+	clk_dm(IMX8MM_SYS_PLL1_400M,
+	       imx_clk_fixed_factor("sys_pll1_400m", "sys_pll1_out", 1, 2));
+	clk_dm(IMX8MM_SYS_PLL1_800M,
+	       imx_clk_fixed_factor("sys_pll1_800m", "sys_pll1_out", 1, 1));
+
+	clk_dm(IMX8MM_SYS_PLL2_50M,
+	       imx_clk_fixed_factor("sys_pll2_50m", "sys_pll2_out", 1, 20));
+	clk_dm(IMX8MM_SYS_PLL2_100M,
+	       imx_clk_fixed_factor("sys_pll2_100m", "sys_pll2_out", 1, 10));
+	clk_dm(IMX8MM_SYS_PLL2_125M,
+	       imx_clk_fixed_factor("sys_pll2_125m", "sys_pll2_out", 1, 8));
+	clk_dm(IMX8MM_SYS_PLL2_166M,
+	       imx_clk_fixed_factor("sys_pll2_166m", "sys_pll2_out", 1, 6));
+	clk_dm(IMX8MM_SYS_PLL2_200M,
+	       imx_clk_fixed_factor("sys_pll2_200m", "sys_pll2_out", 1, 5));
+	clk_dm(IMX8MM_SYS_PLL2_250M,
+	       imx_clk_fixed_factor("sys_pll2_250m", "sys_pll2_out", 1, 4));
+	clk_dm(IMX8MM_SYS_PLL2_333M,
+	       imx_clk_fixed_factor("sys_pll2_333m", "sys_pll2_out", 1, 3));
+	clk_dm(IMX8MM_SYS_PLL2_500M,
+	       imx_clk_fixed_factor("sys_pll2_500m", "sys_pll2_out", 1, 2));
+	clk_dm(IMX8MM_SYS_PLL2_1000M,
+	       imx_clk_fixed_factor("sys_pll2_1000m", "sys_pll2_out", 1, 1));
+
+	base = dev_read_addr_ptr(dev);
+	if (base == (void *)FDT_ADDR_T_NONE)
+		return -EINVAL;
+
+	clk_dm(IMX8MM_CLK_A53_SRC,
+	       imx_clk_mux2("arm_a53_src", base + 0x8000, 24, 3,
+			    imx8mm_a53_sels, ARRAY_SIZE(imx8mm_a53_sels)));
+	clk_dm(IMX8MM_CLK_A53_CG,
+	       imx_clk_gate3("arm_a53_cg", "arm_a53_src", base + 0x8000, 28));
+	clk_dm(IMX8MM_CLK_A53_DIV,
+	       imx_clk_divider2("arm_a53_div", "arm_a53_cg",
+				base + 0x8000, 0, 3));
+
+	clk_dm(IMX8MM_CLK_AHB,
+	       imx8m_clk_composite_critical("ahb", imx8mm_ahb_sels,
+					    base + 0x9000));
+	clk_dm(IMX8MM_CLK_IPG_ROOT,
+	       imx_clk_divider2("ipg_root", "ahb", base + 0x9080, 0, 1));
+
+	clk_dm(IMX8MM_CLK_ENET_AXI,
+	       imx8m_clk_composite("enet_axi", imx8mm_enet_axi_sels,
+				   base + 0x8880));
+	clk_dm(IMX8MM_CLK_NAND_USDHC_BUS,
+	       imx8m_clk_composite_critical("nand_usdhc_bus",
+					    imx8mm_nand_usdhc_sels,
+					    base + 0x8900));
+
+	/* IP */
+	clk_dm(IMX8MM_CLK_USDHC1,
+	       imx8m_clk_composite("usdhc1", imx8mm_usdhc1_sels,
+				   base + 0xac00));
+	clk_dm(IMX8MM_CLK_USDHC2,
+	       imx8m_clk_composite("usdhc2", imx8mm_usdhc2_sels,
+				   base + 0xac80));
+	clk_dm(IMX8MM_CLK_I2C1,
+	       imx8m_clk_composite("i2c1", imx8mm_i2c1_sels, base + 0xad00));
+	clk_dm(IMX8MM_CLK_I2C2,
+	       imx8m_clk_composite("i2c2", imx8mm_i2c2_sels, base + 0xad80));
+	clk_dm(IMX8MM_CLK_I2C3,
+	       imx8m_clk_composite("i2c3", imx8mm_i2c3_sels, base + 0xae00));
+	clk_dm(IMX8MM_CLK_I2C4,
+	       imx8m_clk_composite("i2c4", imx8mm_i2c4_sels, base + 0xae80));
+	clk_dm(IMX8MM_CLK_WDOG,
+	       imx8m_clk_composite("wdog", imx8mm_wdog_sels, base + 0xb900));
+	clk_dm(IMX8MM_CLK_USDHC3,
+	       imx8m_clk_composite("usdhc3", imx8mm_usdhc3_sels,
+				   base + 0xbc80));
+
+	clk_dm(IMX8MM_CLK_I2C1_ROOT,
+	       imx_clk_gate4("i2c1_root_clk", "i2c1", base + 0x4170, 0));
+	clk_dm(IMX8MM_CLK_I2C2_ROOT,
+	       imx_clk_gate4("i2c2_root_clk", "i2c2", base + 0x4180, 0));
+	clk_dm(IMX8MM_CLK_I2C3_ROOT,
+	       imx_clk_gate4("i2c3_root_clk", "i2c3", base + 0x4190, 0));
+	clk_dm(IMX8MM_CLK_I2C4_ROOT,
+	       imx_clk_gate4("i2c4_root_clk", "i2c4", base + 0x41a0, 0));
+	clk_dm(IMX8MM_CLK_OCOTP_ROOT,
+	       imx_clk_gate4("ocotp_root_clk", "ipg_root", base + 0x4220, 0));
+	clk_dm(IMX8MM_CLK_USDHC1_ROOT,
+	       imx_clk_gate4("usdhc1_root_clk", "usdhc1", base + 0x4510, 0));
+	clk_dm(IMX8MM_CLK_USDHC2_ROOT,
+	       imx_clk_gate4("usdhc2_root_clk", "usdhc2", base + 0x4520, 0));
+	clk_dm(IMX8MM_CLK_WDOG1_ROOT,
+	       imx_clk_gate4("wdog1_root_clk", "wdog", base + 0x4530, 0));
+	clk_dm(IMX8MM_CLK_WDOG2_ROOT,
+	       imx_clk_gate4("wdog2_root_clk", "wdog", base + 0x4540, 0));
+	clk_dm(IMX8MM_CLK_WDOG3_ROOT,
+	       imx_clk_gate4("wdog3_root_clk", "wdog", base + 0x4550, 0));
+	clk_dm(IMX8MM_CLK_USDHC3_ROOT,
+	       imx_clk_gate4("usdhc3_root_clk", "usdhc3", base + 0x45e0, 0));
+
+#ifdef CONFIG_SPL_BUILD
+	struct clk *clkp, *clkp1;
+	struct udevice *devp;
+
+	clk_get_by_id(IMX8MM_CLK_WDOG1_ROOT, &clkp);
+	clk_enable(clkp);
+	clk_get_by_id(IMX8MM_CLK_WDOG2_ROOT, &clkp);
+	clk_enable(clkp);
+	clk_get_by_id(IMX8MM_CLK_WDOG3_ROOT, &clkp);
+	clk_enable(clkp);
+
+	/* Configure SYS_PLL3 to 750MHz */
+	clk_get_by_id(IMX8MM_SYS_PLL3, &clkp);
+	clk_set_rate(clkp, 750000000UL);
+
+	/* Configure ARM to osc24M */
+	clk_get_by_id(IMX8MM_CLK_A53_SRC, &clkp);
+	uclass_get_device_by_name(UCLASS_CLK, "clock-osc-24m", &devp);
+	clkp1 = &to_clk_fixed_rate(devp)->clk;
+	clk_set_parent(clkp, clkp1);
+
+	/* Configure ARM PLL to 1.2GHz */
+	clk_get_by_id(IMX8MM_ARM_PLL, &clkp1);
+	clk_set_rate(clkp1, 1200000000UL);
+	clk_get_by_id(IMX8MM_ARM_PLL_OUT, &clkp1);
+	clk_enable(clkp1);
+	clk_set_parent(clkp, clkp1);
+
+	/* Configure DIV to 1.2GHz */
+	clk_get_by_id(IMX8MM_CLK_A53_DIV, &clkp1);
+	clk_set_rate(clkp1, 1200000000UL);
+#endif
+
+	return 0;
+}
+
+static const struct udevice_id imx8mm_clk_ids[] = {
+	{ .compatible = "fsl,imx8mm-ccm" },
+	{ },
+};
+
+U_BOOT_DRIVER(imx8mm_clk) = {
+	.name = "clk_imx8mm",
+	.id = UCLASS_CLK,
+	.of_match = imx8mm_clk_ids,
+	.ops = &imx8mm_clk_ops,
+	.probe = imx8mm_clk_probe,
+	.flags = DM_FLAG_PRE_RELOC,
+};
-- 
2.16.4

[U-Boot] [i.MX8MM+CCF 41/41] imx: add i.MX8MM EVK board support

[Peng Fan]

Add i.MX8MM EVK board support.

Add board and SoC dts
Add ddr training code
support SD/MMC/GPIO/PINCTRL/UART

Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 arch/arm/dts/Makefile                      |    3 +-
 arch/arm/dts/imx8mm-evk-u-boot.dtsi        |   92 ++
 arch/arm/dts/imx8mm-evk.dts                |  235 ++++
 arch/arm/dts/imx8mm-pinfunc.h              |  629 +++++++++
 arch/arm/dts/imx8mm.dtsi                   |  733 ++++++++++
 arch/arm/mach-imx/imx8m/Kconfig            |    7 +
 board/freescale/imx8mm_evk/Kconfig         |   12 +
 board/freescale/imx8mm_evk/MAINTAINERS     |    6 +
 board/freescale/imx8mm_evk/Makefile        |   12 +
 board/freescale/imx8mm_evk/imx8mm_evk.c    |   90 ++
 board/freescale/imx8mm_evk/lpddr4_timing.c | 1980 ++++++++++++++++++++++++++++
 board/freescale/imx8mm_evk/spl.c           |  216 +++
 configs/imx8mm_evk_defconfig               |   52 +
 include/configs/imx8mm_evk.h               |  199 +++
 14 files changed, 4265 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/dts/imx8mm-evk-u-boot.dtsi
 create mode 100644 arch/arm/dts/imx8mm-evk.dts
 create mode 100644 arch/arm/dts/imx8mm-pinfunc.h
 create mode 100644 arch/arm/dts/imx8mm.dtsi
 create mode 100644 board/freescale/imx8mm_evk/Kconfig
 create mode 100644 board/freescale/imx8mm_evk/MAINTAINERS
 create mode 100644 board/freescale/imx8mm_evk/Makefile
 create mode 100644 board/freescale/imx8mm_evk/imx8mm_evk.c
 create mode 100644 board/freescale/imx8mm_evk/lpddr4_timing.c
 create mode 100644 board/freescale/imx8mm_evk/spl.c
 create mode 100644 configs/imx8mm_evk_defconfig
 create mode 100644 include/configs/imx8mm_evk.h

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 0aee8dfde0..b556bc72d2 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -563,7 +563,8 @@ dtb-$(CONFIG_ARCH_MX7ULP) += imx7ulp-evk.dtb
 
 dtb-$(CONFIG_ARCH_IMX8) += fsl-imx8qxp-mek.dtb
 
-dtb-$(CONFIG_ARCH_IMX8M) += fsl-imx8mq-evk.dtb
+dtb-$(CONFIG_ARCH_IMX8M) += fsl-imx8mq-evk.dtb \
+	imx8mm-evk.dtb
 
 dtb-$(CONFIG_RCAR_GEN2) += \
 	r8a7790-lager-u-boot.dtb \
diff --git a/arch/arm/dts/imx8mm-evk-u-boot.dtsi b/arch/arm/dts/imx8mm-evk-u-boot.dtsi
new file mode 100644
index 0000000000..1095d36e31
--- /dev/null
+++ b/arch/arm/dts/imx8mm-evk-u-boot.dtsi
@@ -0,0 +1,92 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019 NXP
+ */
+
+&{/soc} {
+	u-boot,dm-pre-reloc;
+	u-boot,dm-spl;
+};
+
+&clk {
+	u-boot,dm-spl;
+	u-boot,dm-pre-reloc;
+};
+
+&osc_24m {
+	u-boot,dm-spl;
+	u-boot,dm-pre-reloc;
+};
+
+&aips1 {
+	u-boot,dm-spl;
+	u-boot,dm-pre-reloc;
+};
+
+&aips2 {
+	u-boot,dm-spl;
+};
+
+&aips3 {
+	u-boot,dm-spl;
+};
+
+&iomuxc {
+	u-boot,dm-spl;
+};
+
+&pinctrl_reg_usdhc2_vmmc {
+	u-boot,dm-spl;
+};
+
+&pinctrl_uart2 {
+	u-boot,dm-spl;
+};
+
+&pinctrl_usdhc2_gpio {
+	u-boot,dm-spl;
+};
+
+&pinctrl_usdhc2 {
+	u-boot,dm-spl;
+};
+
+&pinctrl_usdhc3 {
+	u-boot,dm-spl;
+};
+
+&gpio1 {
+	u-boot,dm-spl;
+};
+
+&gpio2 {
+	u-boot,dm-spl;
+};
+
+&gpio3 {
+	u-boot,dm-spl;
+};
+
+&gpio4 {
+	u-boot,dm-spl;
+};
+
+&gpio5 {
+	u-boot,dm-spl;
+};
+
+&uart2 {
+	u-boot,dm-spl;
+};
+
+&usdhc1 {
+	u-boot,dm-spl;
+};
+
+&usdhc2 {
+	u-boot,dm-spl;
+};
+
+&usdhc3 {
+	u-boot,dm-spl;
+};
diff --git a/arch/arm/dts/imx8mm-evk.dts b/arch/arm/dts/imx8mm-evk.dts
new file mode 100644
index 0000000000..2d5d89475b
--- /dev/null
+++ b/arch/arm/dts/imx8mm-evk.dts
@@ -0,0 +1,235 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2019 NXP
+ */
+
+/dts-v1/;
+
+#include "imx8mm.dtsi"
+
+/ {
+	model = "FSL i.MX8MM EVK board";
+	compatible = "fsl,imx8mm-evk", "fsl,imx8mm";
+
+	chosen {
+		stdout-path = &uart2;
+	};
+
+	leds {
+		compatible = "gpio-leds";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_gpio_led>;
+
+		status {
+			label = "status";
+			gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>;
+			default-state = "on";
+		};
+	};
+
+	reg_usdhc2_vmmc: regulator-usdhc2 {
+		compatible = "regulator-fixed";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
+		regulator-name = "VSD_3V3";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+	};
+};
+
+&fec1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_fec1>;
+	phy-mode = "rgmii-id";
+	phy-handle = <&ethphy0>;
+	fsl,magic-packet;
+	status = "okay";
+
+	mdio {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		ethphy0: ethernet-phy at 0 {
+			compatible = "ethernet-phy-ieee802.3-c22";
+			reg = <0>;
+			at803x,led-act-blind-workaround;
+			at803x,eee-okay;
+			at803x,vddio-1p8v;
+		};
+	};
+};
+
+&uart2 { /* console */
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart2>;
+	status = "okay";
+};
+
+&usdhc2 {
+	pinctrl-names = "default", "state_100mhz", "state_200mhz";
+	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
+	pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
+	pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
+	cd-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
+	bus-width = <4>;
+	vmmc-supply = <&reg_usdhc2_vmmc>;
+	status = "okay";
+};
+
+&usdhc3 {
+	pinctrl-names = "default", "state_100mhz", "state_200mhz";
+	pinctrl-0 = <&pinctrl_usdhc3>;
+	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
+	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
+	bus-width = <8>;
+	non-removable;
+	status = "okay";
+};
+
+&wdog1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_wdog>;
+	fsl,ext-reset-output;
+	status = "okay";
+};
+
+&iomuxc {
+	pinctrl-names = "default";
+
+	pinctrl_fec1: fec1grp {
+		fsl,pins = <
+			MX8MM_IOMUXC_ENET_MDC_ENET1_MDC			0x3
+			MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO		0x3
+			MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3		0x1f
+			MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2		0x1f
+			MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1		0x1f
+			MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0		0x1f
+			MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3		0x91
+			MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2		0x91
+			MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1		0x91
+			MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0		0x91
+			MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC		0x1f
+			MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC		0x91
+			MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL	0x91
+			MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL	0x1f
+			MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22		0x19
+		>;
+	};
+
+	pinctrl_gpio_led: gpioledgrp {
+		fsl,pins = <
+			MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16	0x19
+		>;
+	};
+
+	pinctrl_reg_usdhc2_vmmc: regusdhc2vmmc {
+		fsl,pins = <
+			MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19	0x41
+		>;
+	};
+
+	pinctrl_uart2: uart2grp {
+		fsl,pins = <
+			MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX	0x140
+			MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX	0x140
+		>;
+	};
+
+	pinctrl_usdhc2_gpio: usdhc2grpgpio {
+		fsl,pins = <
+			MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15	0x1c4
+		>;
+	};
+
+	pinctrl_usdhc2: usdhc2grp {
+		fsl,pins = <
+			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK		0x190
+			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d0
+			MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d0
+			MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d0
+			MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d0
+			MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d0
+			MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0x1d0
+		>;
+	};
+
+	pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
+		fsl,pins = <
+			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK		0x194
+			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d4
+			MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d4
+			MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d4
+			MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d4
+			MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d4
+			MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0x1d0
+		>;
+	};
+
+	pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
+		fsl,pins = <
+			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK		0x196
+			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d6
+			MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d6
+			MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d6
+			MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d6
+			MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d6
+			MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0x1d0
+		>;
+	};
+
+	pinctrl_usdhc3: usdhc3grp {
+		fsl,pins = <
+			MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK		0x190
+			MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD		0x1d0
+			MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0		0x1d0
+			MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1		0x1d0
+			MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2		0x1d0
+			MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3		0x1d0
+			MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4		0x1d0
+			MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5		0x1d0
+			MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6		0x1d0
+			MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7		0x1d0
+			MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 		0x190
+		>;
+	};
+
+	pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
+		fsl,pins = <
+			MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK		0x194
+			MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD		0x1d4
+			MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0		0x1d4
+			MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1		0x1d4
+			MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2		0x1d4
+			MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3		0x1d4
+			MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4		0x1d4
+			MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5		0x1d4
+			MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6		0x1d4
+			MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7		0x1d4
+			MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 		0x194
+		>;
+	};
+
+	pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
+		fsl,pins = <
+			MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK		0x196
+			MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD		0x1d6
+			MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0		0x1d6
+			MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1		0x1d6
+			MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2		0x1d6
+			MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3		0x1d6
+			MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4		0x1d6
+			MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5		0x1d6
+			MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6		0x1d6
+			MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7		0x1d6
+			MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 		0x196
+		>;
+	};
+
+	pinctrl_wdog: wdoggrp {
+		fsl,pins = <
+			MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B	0xc6
+		>;
+	};
+};
diff --git a/arch/arm/dts/imx8mm-pinfunc.h b/arch/arm/dts/imx8mm-pinfunc.h
new file mode 100644
index 0000000000..e25f7fcd79
--- /dev/null
+++ b/arch/arm/dts/imx8mm-pinfunc.h
@@ -0,0 +1,629 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2017-2018 NXP
+ */
+
+#ifndef __DTS_IMX8MM_PINFUNC_H
+#define __DTS_IMX8MM_PINFUNC_H
+
+/*
+ * The pin function ID is a tuple of
+ * <mux_reg conf_reg input_reg mux_mode input_val>
+ */
+
+#define MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0                                   0x028 0x290 0x000 0x0 0x0
+#define MX8MM_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT          0x028 0x290 0x4C0 0x1 0x0
+#define MX8MM_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K                          0x028 0x290 0x000 0x5 0x0
+#define MX8MM_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1                       0x028 0x290 0x000 0x6 0x0
+#define MX8MM_IOMUXC_GPIO1_IO00_SJC_FAIL                                    0x028 0x290 0x000 0x7 0x0
+#define MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1                                   0x02C 0x294 0x000 0x0 0x0
+#define MX8MM_IOMUXC_GPIO1_IO01_PWM1_OUT                                    0x02C 0x294 0x000 0x1 0x0
+#define MX8MM_IOMUXC_GPIO1_IO01_ANAMIX_REF_CLK_24M                          0x02C 0x294 0x4BC 0x5 0x0
+#define MX8MM_IOMUXC_GPIO1_IO01_CCMSRCGPCMIX_EXT_CLK2                       0x02C 0x294 0x000 0x6 0x0
+#define MX8MM_IOMUXC_GPIO1_IO01_SJC_ACTIVE                                  0x02C 0x294 0x000 0x7 0x0
+#define MX8MM_IOMUXC_GPIO1_IO02_GPIO1_IO2                                   0x030 0x298 0x000 0x0 0x0
+#define MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B                                0x030 0x298 0x000 0x1 0x0
+#define MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_ANY                              0x030 0x298 0x000 0x5 0x0
+#define MX8MM_IOMUXC_GPIO1_IO02_SJC_DE_B                                    0x030 0x298 0x000 0x7 0x0
+#define MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3                                   0x034 0x29C 0x000 0x0 0x0
+#define MX8MM_IOMUXC_GPIO1_IO03_USDHC1_VSELECT                              0x034 0x29C 0x000 0x1 0x0
+#define MX8MM_IOMUXC_GPIO1_IO03_SDMA1_EXT_EVENT0                            0x034 0x29C 0x000 0x5 0x0
+#define MX8MM_IOMUXC_GPIO1_IO03_ANAMIX_XTAL_OK                              0x034 0x29C 0x000 0x6 0x0
+#define MX8MM_IOMUXC_GPIO1_IO03_SJC_DONE                                    0x034 0x29C 0x000 0x7 0x0
+#define MX8MM_IOMUXC_GPIO1_IO04_GPIO1_IO4                                   0x038 0x2A0 0x000 0x0 0x0
+#define MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT                              0x038 0x2A0 0x000 0x1 0x0
+#define MX8MM_IOMUXC_GPIO1_IO04_SDMA1_EXT_EVENT1                            0x038 0x2A0 0x000 0x5 0x0
+#define MX8MM_IOMUXC_GPIO1_IO04_ANAMIX_XTAL_OK_LV                           0x038 0x2A0 0x000 0x6 0x0
+#define MX8MM_IOMUXC_GPIO1_IO04_USDHC1_TEST_TRIG                            0x038 0x2A0 0x000 0x7 0x0
+#define MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5                                   0x03C 0x2A4 0x000 0x0 0x0
+#define MX8MM_IOMUXC_GPIO1_IO05_M4_NMI                                      0x03C 0x2A4 0x000 0x1 0x0
+#define MX8MM_IOMUXC_GPIO1_IO05_CCMSRCGPCMIX_PMIC_READY                     0x03C 0x2A4 0x000 0x5 0x0
+#define MX8MM_IOMUXC_GPIO1_IO05_CCMSRCGPCMIX_INT_BOOT                       0x03C 0x2A4 0x000 0x6 0x0
+#define MX8MM_IOMUXC_GPIO1_IO05_USDHC2_TEST_TRIG                            0x03C 0x2A4 0x000 0x7 0x0
+#define MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6                                   0x040 0x2A8 0x000 0x0 0x0
+#define MX8MM_IOMUXC_GPIO1_IO06_ENET1_MDC                                   0x040 0x2A8 0x000 0x1 0x0
+#define MX8MM_IOMUXC_GPIO1_IO06_USDHC1_CD_B                                 0x040 0x2A8 0x000 0x5 0x0
+#define MX8MM_IOMUXC_GPIO1_IO06_CCMSRCGPCMIX_EXT_CLK3                       0x040 0x2A8 0x000 0x6 0x0
+#define MX8MM_IOMUXC_GPIO1_IO06_ECSPI1_TEST_TRIG                            0x040 0x2A8 0x000 0x7 0x0
+#define MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7                                   0x044 0x2AC 0x000 0x0 0x0
+#define MX8MM_IOMUXC_GPIO1_IO07_ENET1_MDIO                                  0x044 0x2AC 0x000 0x1 0x0
+#define MX8MM_IOMUXC_GPIO1_IO07_USDHC1_WP                                   0x044 0x2AC 0x000 0x5 0x0
+#define MX8MM_IOMUXC_GPIO1_IO07_CCMSRCGPCMIX_EXT_CLK4                       0x044 0x2AC 0x000 0x6 0x0
+#define MX8MM_IOMUXC_GPIO1_IO07_ECSPI2_TEST_TRIG                            0x044 0x2AC 0x000 0x7 0x0
+#define MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8                                   0x048 0x2B0 0x000 0x0 0x0
+#define MX8MM_IOMUXC_GPIO1_IO08_ENET1_1588_EVENT0_IN                        0x048 0x2B0 0x000 0x1 0x0
+#define MX8MM_IOMUXC_GPIO1_IO08_USDHC2_RESET_B                              0x048 0x2B0 0x000 0x5 0x0
+#define MX8MM_IOMUXC_GPIO1_IO08_CCMSRCGPCMIX_WAIT                           0x048 0x2B0 0x000 0x6 0x0
+#define MX8MM_IOMUXC_GPIO1_IO08_QSPI_TEST_TRIG                              0x048 0x2B0 0x000 0x7 0x0
+#define MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9                                   0x04C 0x2B4 0x000 0x0 0x0
+#define MX8MM_IOMUXC_GPIO1_IO09_ENET1_1588_EVENT0_OUT                       0x04C 0x2B4 0x000 0x1 0x0
+#define MX8MM_IOMUXC_GPIO1_IO09_SDMA2_EXT_EVENT0                            0x04C 0x2B4 0x000 0x5 0x0
+#define MX8MM_IOMUXC_GPIO1_IO09_CCMSRCGPCMIX_STOP                           0x04C 0x2B4 0x000 0x6 0x0
+#define MX8MM_IOMUXC_GPIO1_IO09_RAWNAND_TEST_TRIG                           0x04C 0x2B4 0x000 0x7 0x0
+#define MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10                                  0x050 0x2B8 0x000 0x0 0x0
+#define MX8MM_IOMUXC_GPIO1_IO10_USB1_OTG_ID                                 0x050 0x2B8 0x000 0x1 0x0
+#define MX8MM_IOMUXC_GPIO1_IO10_OCOTP_CTRL_WRAPPER_FUSE_LATCHED             0x050 0x2B8 0x000 0x7 0x0
+#define MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11                                  0x054 0x2BC 0x000 0x0 0x0
+#define MX8MM_IOMUXC_GPIO1_IO11_USB2_OTG_ID                                 0x054 0x2BC 0x000 0x1 0x0
+#define MX8MM_IOMUXC_GPIO1_IO11_CCMSRCGPCMIX_PMIC_READY                     0x054 0x2BC 0x4BC 0x5 0x1
+#define MX8MM_IOMUXC_GPIO1_IO11_CCMSRCGPCMIX_OUT0                           0x054 0x2BC 0x000 0x6 0x0
+#define MX8MM_IOMUXC_GPIO1_IO11_CAAM_WRAPPER_RNG_OSC_OBS                    0x054 0x2BC 0x000 0x7 0x0
+#define MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12                                  0x058 0x2C0 0x000 0x0 0x0
+#define MX8MM_IOMUXC_GPIO1_IO12_USB1_OTG_PWR                                0x058 0x2C0 0x000 0x1 0x0
+#define MX8MM_IOMUXC_GPIO1_IO12_SDMA2_EXT_EVENT1                            0x058 0x2C0 0x000 0x5 0x0
+#define MX8MM_IOMUXC_GPIO1_IO12_CCMSRCGPCMIX_OUT1                           0x058 0x2C0 0x000 0x6 0x0
+#define MX8MM_IOMUXC_GPIO1_IO12_CSU_CSU_ALARM_AUT0                          0x058 0x2C0 0x000 0x7 0x0
+#define MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13                                  0x05C 0x2C4 0x000 0x0 0x0
+#define MX8MM_IOMUXC_GPIO1_IO13_USB1_OTG_OC                                 0x05C 0x2C4 0x000 0x1 0x0
+#define MX8MM_IOMUXC_GPIO1_IO13_PWM2_OUT                                    0x05C 0x2C4 0x000 0x5 0x0
+#define MX8MM_IOMUXC_GPIO1_IO13_CCMSRCGPCMIX_OUT2                           0x05C 0x2C4 0x000 0x6 0x0
+#define MX8MM_IOMUXC_GPIO1_IO13_CSU_CSU_ALARM_AUT1                          0x05C 0x2C4 0x000 0x7 0x0
+#define MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14                                  0x060 0x2C8 0x000 0x0 0x0
+#define MX8MM_IOMUXC_GPIO1_IO14_USB2_OTG_PWR                                0x060 0x2C8 0x000 0x1 0x0
+#define MX8MM_IOMUXC_GPIO1_IO14_PWM3_OUT                                    0x060 0x2C8 0x000 0x5 0x0
+#define MX8MM_IOMUXC_GPIO1_IO14_CCMSRCGPCMIX_CLKO1                          0x060 0x2C8 0x000 0x6 0x0
+#define MX8MM_IOMUXC_GPIO1_IO14_CSU_CSU_ALARM_AUT2                          0x060 0x2C8 0x000 0x7 0x0
+#define MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15                                  0x064 0x2CC 0x000 0x0 0x0
+#define MX8MM_IOMUXC_GPIO1_IO15_USB2_OTG_OC                                 0x064 0x2CC 0x000 0x1 0x0
+#define MX8MM_IOMUXC_GPIO1_IO15_PWM4_OUT                                    0x064 0x2CC 0x000 0x5 0x0
+#define MX8MM_IOMUXC_GPIO1_IO15_CCMSRCGPCMIX_CLKO2                          0x064 0x2CC 0x000 0x6 0x0
+#define MX8MM_IOMUXC_GPIO1_IO15_CSU_CSU_INT_DEB                             0x064 0x2CC 0x000 0x7 0x0
+#define MX8MM_IOMUXC_ENET_MDC_ENET1_MDC                                     0x068 0x2D0 0x000 0x0 0x0
+#define MX8MM_IOMUXC_ENET_MDC_GPIO1_IO16                                    0x068 0x2D0 0x000 0x5 0x0
+#define MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO                                   0x06C 0x2D4 0x4C0 0x0 0x1
+#define MX8MM_IOMUXC_ENET_MDIO_GPIO1_IO17                                   0x06C 0x2D4 0x000 0x5 0x0
+#define MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3                               0x070 0x2D8 0x000 0x0 0x0
+#define MX8MM_IOMUXC_ENET_TD3_GPIO1_IO18                                    0x070 0x2D8 0x000 0x5 0x0
+#define MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2                               0x074 0x2DC 0x000 0x0 0x0
+#define MX8MM_IOMUXC_ENET_TD2_ENET1_TX_CLK                                  0x074 0x2DC 0x000 0x1 0x0
+#define MX8MM_IOMUXC_ENET_TD2_GPIO1_IO19                                    0x074 0x2DC 0x000 0x5 0x0
+#define MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1                               0x078 0x2E0 0x000 0x0 0x0
+#define MX8MM_IOMUXC_ENET_TD1_GPIO1_IO20                                    0x078 0x2E0 0x000 0x5 0x0
+#define MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0                               0x07C 0x2E4 0x000 0x0 0x0
+#define MX8MM_IOMUXC_ENET_TD0_GPIO1_IO21                                    0x07C 0x2E4 0x000 0x5 0x0
+#define MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL                         0x080 0x2E8 0x000 0x0 0x0
+#define MX8MM_IOMUXC_ENET_TX_CTL_GPIO1_IO22                                 0x080 0x2E8 0x000 0x5 0x0
+#define MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC                               0x084 0x2EC 0x000 0x0 0x0
+#define MX8MM_IOMUXC_ENET_TXC_ENET1_TX_ER                                   0x084 0x2EC 0x000 0x1 0x0
+#define MX8MM_IOMUXC_ENET_TXC_GPIO1_IO23                                    0x084 0x2EC 0x000 0x5 0x0
+#define MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL                         0x088 0x2F0 0x000 0x0 0x0
+#define MX8MM_IOMUXC_ENET_RX_CTL_GPIO1_IO24                                 0x088 0x2F0 0x000 0x5 0x0
+#define MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC                               0x08C 0x2F4 0x000 0x0 0x0
+#define MX8MM_IOMUXC_ENET_RXC_ENET1_RX_ER                                   0x08C 0x2F4 0x000 0x1 0x0
+#define MX8MM_IOMUXC_ENET_RXC_GPIO1_IO25                                    0x08C 0x2F4 0x000 0x5 0x0
+#define MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0                               0x090 0x2F8 0x000 0x0 0x0
+#define MX8MM_IOMUXC_ENET_RD0_GPIO1_IO26                                    0x090 0x2F8 0x000 0x5 0x0
+#define MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1                               0x094 0x2FC 0x000 0x0 0x0
+#define MX8MM_IOMUXC_ENET_RD1_GPIO1_IO27                                    0x094 0x2FC 0x000 0x5 0x0
+#define MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2                               0x098 0x300 0x000 0x0 0x0
+#define MX8MM_IOMUXC_ENET_RD2_GPIO1_IO28                                    0x098 0x300 0x000 0x5 0x0
+#define MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3                               0x09C 0x304 0x000 0x0 0x0
+#define MX8MM_IOMUXC_ENET_RD3_GPIO1_IO29                                    0x09C 0x304 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK                                     0x0A0 0x308 0x000 0x0 0x0
+#define MX8MM_IOMUXC_SD1_CLK_GPIO2_IO0                                      0x0A0 0x308 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD                                     0x0A4 0x30C 0x000 0x0 0x0
+#define MX8MM_IOMUXC_SD1_CMD_GPIO2_IO1                                      0x0A4 0x30C 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0                                 0x0A8 0x310 0x000 0x0 0x0
+#define MX8MM_IOMUXC_SD1_DATA0_GPIO2_IO2                                    0x0A8 0x31  0x000 0x5 0x0
+#define MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1                                 0x0AC 0x314 0x000 0x0 0x0
+#define MX8MM_IOMUXC_SD1_DATA1_GPIO2_IO3                                    0x0AC 0x314 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2                                 0x0B0 0x318 0x000 0x0 0x0
+#define MX8MM_IOMUXC_SD1_DATA2_GPIO2_IO4                                    0x0B0 0x318 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3                                 0x0B4 0x31C 0x000 0x0 0x0
+#define MX8MM_IOMUXC_SD1_DATA3_GPIO2_IO5                                    0x0B4 0x31C 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4                                 0x0B8 0x320 0x000 0x0 0x0
+#define MX8MM_IOMUXC_SD1_DATA4_GPIO2_IO6                                    0x0B8 0x320 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5                                 0x0BC 0x324 0x000 0x0 0x0
+#define MX8MM_IOMUXC_SD1_DATA5_GPIO2_IO7                                    0x0BC 0x324 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6                                 0x0C0 0x328 0x000 0x0 0x0
+#define MX8MM_IOMUXC_SD1_DATA6_GPIO2_IO8                                    0x0C0 0x328 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7                                 0x0C4 0x32C 0x000 0x0 0x0
+#define MX8MM_IOMUXC_SD1_DATA7_GPIO2_IO9                                    0x0C4 0x32C 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B                             0x0C8 0x330 0x000 0x0 0x0
+#define MX8MM_IOMUXC_SD1_RESET_B_GPIO2_IO10                                 0x0C8 0x330 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE                               0x0CC 0x334 0x000 0x0 0x0
+#define MX8MM_IOMUXC_SD1_STROBE_GPIO2_IO11                                  0x0CC 0x334 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SD2_CD_B_USDHC2_CD_B                                   0x0D0 0x338 0x000 0x0 0x0
+#define MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12                                    0x0D0 0x338 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK                                     0x0D4 0x33C 0x000 0x0 0x0
+#define MX8MM_IOMUXC_SD2_CLK_GPIO2_IO13                                     0x0D4 0x33C 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SD2_CLK_CCMSRCGPCMIX_OBSERVE0                          0x0D4 0x33C 0x000 0x6 0x0
+#define MX8MM_IOMUXC_SD2_CLK_OBSERVE_MUX_OUT0                               0x0D4 0x33C 0x000 0x7 0x0
+#define MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD                                     0x0D8 0x340 0x000 0x0 0x0
+#define MX8MM_IOMUXC_SD2_CMD_GPIO2_IO14                                     0x0D8 0x340 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SD2_CMD_CCMSRCGPCMIX_OBSERVE1                          0x0D8 0x340 0x000 0x6 0x0
+#define MX8MM_IOMUXC_SD2_CMD_OBSERVE_MUX_OUT1                               0x0D8 0x340 0x000 0x7 0x0
+#define MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0                                 0x0DC 0x344 0x000 0x0 0x0
+#define MX8MM_IOMUXC_SD2_DATA0_GPIO2_IO15                                   0x0DC 0x344 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SD2_DATA0_CCMSRCGPCMIX_OBSERVE2                        0x0DC 0x344 0x000 0x6 0x0
+#define MX8MM_IOMUXC_SD2_DATA0_OBSERVE_MUX_OUT2                             0x0DC 0x344 0x000 0x7 0x0
+#define MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1                                 0x0E0 0x348 0x000 0x0 0x0
+#define MX8MM_IOMUXC_SD2_DATA1_GPIO2_IO16                                   0x0E0 0x348 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SD2_DATA1_CCMSRCGPCMIX_WAIT                            0x0E0 0x348 0x000 0x6 0x0
+#define MX8MM_IOMUXC_SD2_DATA1_OBSERVE_MUX_OUT3                             0x0E0 0x348 0x000 0x7 0x0
+#define MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2                                 0x0E4 0x34C 0x000 0x0 0x0
+#define MX8MM_IOMUXC_SD2_DATA2_GPIO2_IO17                                   0x0E4 0x34C 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SD2_DATA2_CCMSRCGPCMIX_STOP                            0x0E4 0x34C 0x000 0x6 0x0
+#define MX8MM_IOMUXC_SD2_DATA2_OBSERVE_MUX_OUT4                             0x0E4 0x34C 0x000 0x7 0x0
+#define MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3                                 0x0E8 0x350 0x000 0x0 0x0
+#define MX8MM_IOMUXC_SD2_DATA3_GPIO2_IO18                                   0x0E8 0x350 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SD2_DATA3_CCMSRCGPCMIX_EARLY_RESET                     0x0E8 0x350 0x000 0x6 0x0
+#define MX8MM_IOMUXC_SD2_RESET_B_USDHC2_RESET_B                             0x0EC 0x354 0x000 0x0 0x0
+#define MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19                                 0x0EC 0x354 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SD2_RESET_B_CCMSRCGPCMIX_SYSTEM_RESET                  0x0EC 0x354 0x000 0x6 0x0
+#define MX8MM_IOMUXC_SD2_WP_USDHC2_WP                                       0x0F0 0x358 0x000 0x0 0x0
+#define MX8MM_IOMUXC_SD2_WP_GPIO2_IO20                                      0x0F0 0x358 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SD2_WP_SIM_M_HMASTLOCK                                 0x0F0 0x358 0x000 0x7 0x0
+#define MX8MM_IOMUXC_NAND_ALE_RAWNAND_ALE                                   0x0F4 0x35C 0x000 0x0 0x0
+#define MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK                                   0x0F4 0x35C 0x000 0x1 0x0
+#define MX8MM_IOMUXC_NAND_ALE_GPIO3_IO0                                     0x0F4 0x35C 0x000 0x5 0x0
+#define MX8MM_IOMUXC_NAND_ALE_SIM_M_HPROT0                                  0x0F4 0x35C 0x000 0x7 0x0
+#define MX8MM_IOMUXC_NAND_CE0_B_RAWNAND_CE0_B                               0x0F8 0x360 0x000 0x0 0x0
+#define MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B                                0x0F8 0x360 0x000 0x1 0x0
+#define MX8MM_IOMUXC_NAND_CE0_B_GPIO3_IO1                                   0x0F8 0x360 0x000 0x5 0x0
+#define MX8MM_IOMUXC_NAND_CE0_B_SIM_M_HPROT1                                0x0F8 0x360 0x000 0x7 0x0
+#define MX8MM_IOMUXC_NAND_CE1_B_RAWNAND_CE1_B                               0x0FC 0x364 0x000 0x0 0x0
+#define MX8MM_IOMUXC_NAND_CE1_B_QSPI_A_SS1_B                                0x0FC 0x364 0x000 0x1 0x0
+#define MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE                               0x0FC 0x364 0x000 0x2 0x0
+#define MX8MM_IOMUXC_NAND_CE1_B_GPIO3_IO2                                   0x0FC 0x364 0x000 0x5 0x0
+#define MX8MM_IOMUXC_NAND_CE1_B_SIM_M_HPROT2                                0x0FC 0x364 0x000 0x7 0x0
+#define MX8MM_IOMUXC_NAND_CE2_B_RAWNAND_CE2_B                               0x100 0x368 0x000 0x0 0x0
+#define MX8MM_IOMUXC_NAND_CE2_B_QSPI_B_SS0_B                                0x100 0x368 0x000 0x1 0x0
+#define MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5                                0x100 0x368 0x000 0x2 0x0
+#define MX8MM_IOMUXC_NAND_CE2_B_GPIO3_IO3                                   0x100 0x368 0x000 0x5 0x0
+#define MX8MM_IOMUXC_NAND_CE2_B_SIM_M_HPROT3                                0x100 0x368 0x000 0x7 0x0
+#define MX8MM_IOMUXC_NAND_CE3_B_RAWNAND_CE3_B                               0x104 0x36C 0x000 0x0 0x0
+#define MX8MM_IOMUXC_NAND_CE3_B_QSPI_B_SS1_B                                0x104 0x36C 0x000 0x1 0x0
+#define MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6                                0x104 0x36C 0x000 0x2 0x0
+#define MX8MM_IOMUXC_NAND_CE3_B_GPIO3_IO4                                   0x104 0x36C 0x000 0x5 0x0
+#define MX8MM_IOMUXC_NAND_CE3_B_SIM_M_HADDR0                                0x104 0x36C 0x000 0x7 0x0
+#define MX8MM_IOMUXC_NAND_CLE_RAWNAND_CLE                                   0x108 0x370 0x000 0x0 0x0
+#define MX8MM_IOMUXC_NAND_CLE_QSPI_B_SCLK                                   0x108 0x370 0x000 0x1 0x0
+#define MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7                                  0x108 0x370 0x000 0x2 0x0
+#define MX8MM_IOMUXC_NAND_CLE_GPIO3_IO5                                     0x108 0x370 0x000 0x5 0x0
+#define MX8MM_IOMUXC_NAND_CLE_SIM_M_HADDR1                                  0x108 0x370 0x000 0x7 0x0
+#define MX8MM_IOMUXC_NAND_DATA00_RAWNAND_DATA00                             0x10C 0x374 0x000 0x0 0x0
+#define MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0                               0x10C 0x374 0x000 0x1 0x0
+#define MX8MM_IOMUXC_NAND_DATA00_GPIO3_IO6                                  0x10C 0x374 0x000 0x5 0x0
+#define MX8MM_IOMUXC_NAND_DATA00_SIM_M_HADDR2                               0x10C 0x374 0x000 0x7 0x0
+#define MX8MM_IOMUXC_NAND_DATA01_RAWNAND_DATA01                             0x110 0x378 0x000 0x0 0x0
+#define MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1                               0x110 0x378 0x000 0x1 0x0
+#define MX8MM_IOMUXC_NAND_DATA01_GPIO3_IO7                                  0x110 0x378 0x000 0x5 0x0
+#define MX8MM_IOMUXC_NAND_DATA01_SIM_M_HADDR3                               0x110 0x378 0x000 0x7 0x0
+#define MX8MM_IOMUXC_NAND_DATA02_RAWNAND_DATA02                             0x114 0x37C 0x000 0x0 0x0
+#define MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2                               0x114 0x37C 0x000 0x1 0x0
+#define MX8MM_IOMUXC_NAND_DATA02_GPIO3_IO8                                  0x114 0x37C 0x000 0x5 0x0
+#define MX8MM_IOMUXC_NAND_DATA02_SIM_M_HADDR4                               0x114 0x37C 0x000 0x7 0x0
+#define MX8MM_IOMUXC_NAND_DATA03_RAWNAND_DATA03                             0x118 0x380 0x000 0x0 0x0
+#define MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3                               0x118 0x380 0x000 0x1 0x0
+#define MX8MM_IOMUXC_NAND_DATA03_GPIO3_IO9                                  0x118 0x380 0x000 0x5 0x0
+#define MX8MM_IOMUXC_NAND_DATA03_SIM_M_HADDR5                               0x118 0x380 0x000 0x7 0x0
+#define MX8MM_IOMUXC_NAND_DATA04_RAWNAND_DATA04                             0x11C 0x384 0x000 0x0 0x0
+#define MX8MM_IOMUXC_NAND_DATA04_QSPI_B_DATA0                               0x11C 0x384 0x000 0x1 0x0
+#define MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0                               0x11C 0x384 0x000 0x2 0x0
+#define MX8MM_IOMUXC_NAND_DATA04_GPIO3_IO10                                 0x11C 0x384 0x000 0x5 0x0
+#define MX8MM_IOMUXC_NAND_DATA04_SIM_M_HADDR6                               0x11C 0x384 0x000 0x7 0x0
+#define MX8MM_IOMUXC_NAND_DATA05_RAWNAND_DATA05                             0x120 0x388 0x000 0x0 0x0
+#define MX8MM_IOMUXC_NAND_DATA05_QSPI_B_DATA1                               0x120 0x388 0x000 0x1 0x0
+#define MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1                               0x120 0x388 0x000 0x2 0x0
+#define MX8MM_IOMUXC_NAND_DATA05_GPIO3_IO11                                 0x120 0x388 0x000 0x5 0x0
+#define MX8MM_IOMUXC_NAND_DATA05_SIM_M_HADDR7                               0x120 0x388 0x000 0x7 0x0
+#define MX8MM_IOMUXC_NAND_DATA06_RAWNAND_DATA06                             0x124 0x38C 0x000 0x0 0x0
+#define MX8MM_IOMUXC_NAND_DATA06_QSPI_B_DATA2                               0x124 0x38C 0x000 0x1 0x0
+#define MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2	                            0x124 0x38C 0x000 0x2 0x0
+#define MX8MM_IOMUXC_NAND_DATA06_GPIO3_IO12                                 0x124 0x38C 0x000 0x5 0x0
+#define MX8MM_IOMUXC_NAND_DATA06_SIM_M_HADDR8                               0x124 0x38C 0x000 0x7 0x0
+#define MX8MM_IOMUXC_NAND_DATA07_RAWNAND_DATA07                             0x128 0x390 0x000 0x0 0x0
+#define MX8MM_IOMUXC_NAND_DATA07_QSPI_B_DATA3                               0x128 0x390 0x000 0x1 0x0
+#define MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3                               0x128 0x390 0x000 0x2 0x0
+#define MX8MM_IOMUXC_NAND_DATA07_GPIO3_IO13                                 0x128 0x390 0x000 0x5 0x0
+#define MX8MM_IOMUXC_NAND_DATA07_SIM_M_HADDR9                               0x128 0x390 0x000 0x7 0x0
+#define MX8MM_IOMUXC_NAND_DQS_RAWNAND_DQS                                   0x12C 0x394 0x000 0x0 0x0
+#define MX8MM_IOMUXC_NAND_DQS_QSPI_A_DQS                                    0x12C 0x394 0x000 0x1 0x0
+#define MX8MM_IOMUXC_NAND_DQS_GPIO3_IO14                                    0x12C 0x394 0x000 0x5 0x0
+#define MX8MM_IOMUXC_NAND_DQS_SIM_M_HADDR10                                 0x12C 0x394 0x000 0x7 0x0
+#define MX8MM_IOMUXC_NAND_RE_B_RAWNAND_RE_B                                 0x130 0x398 0x000 0x0 0x0
+#define MX8MM_IOMUXC_NAND_RE_B_QSPI_B_DQS                                   0x130 0x398 0x000 0x1 0x0
+#define MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4                                 0x130 0x398 0x000 0x2 0x0
+#define MX8MM_IOMUXC_NAND_RE_B_GPIO3_IO15                                   0x130 0x398 0x000 0x5 0x0
+#define MX8MM_IOMUXC_NAND_RE_B_SIM_M_HADDR11                                0x130 0x398 0x000 0x7 0x0
+#define MX8MM_IOMUXC_NAND_READY_B_RAWNAND_READY_B                           0x134 0x39C 0x000 0x0 0x0
+#define MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16                                0x134 0x39C 0x000 0x5 0x0
+#define MX8MM_IOMUXC_NAND_READY_B_SIM_M_HADDR12                             0x134 0x39C 0x000 0x7 0x0
+#define MX8MM_IOMUXC_NAND_WE_B_RAWNAND_WE_B                                 0x138 0x3A0 0x000 0x0 0x0
+#define MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK                                   0x138 0x3A0 0x000 0x12 0x0
+#define MX8MM_IOMUXC_NAND_WE_B_GPIO3_IO17                                   0x138 0x3A0 0x000 0x5 0x0
+#define MX8MM_IOMUXC_NAND_WE_B_SIM_M_HADDR13                                0x138 0x3A0 0x000 0x7 0x0
+#define MX8MM_IOMUXC_NAND_WP_B_RAWNAND_WP_B                                 0x13C 0x3A4 0x000 0x0 0x0
+#define MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD                                   0x13C 0x3A4 0x000 0x2 0x0
+#define MX8MM_IOMUXC_NAND_WP_B_GPIO3_IO18                                   0x13C 0x3A4 0x000 0x5 0x0
+#define MX8MM_IOMUXC_NAND_WP_B_SIM_M_HADDR14                                0x13C 0x3A4 0x000 0x7 0x0
+#define MX8MM_IOMUXC_SAI5_RXFS_SAI5_RX_SYNC                                 0x140 0x3A8 0x4E4 0x0 0x0
+#define MX8MM_IOMUXC_SAI5_RXFS_SAI1_TX_DATA0                                0x140 0x3A8 0x000 0x1 0x0
+#define MX8MM_IOMUXC_SAI5_RXFS_GPIO3_IO19                                   0x140 0x3A8 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SAI5_RXC_SAI5_RX_BCLK                                  0x144 0x3AC 0x4D0 0x0 0x0
+#define MX8MM_IOMUXC_SAI5_RXC_SAI1_TX_DATA1                                 0x144 0x3AC 0x000 0x1 0x0
+#define MX8MM_IOMUXC_SAI5_RXC_PDM_CLK                                       0x144 0x3AC 0x000 0x4 0x0
+#define MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20                                    0x144 0x3AC 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SAI5_RXD0_SAI5_RX_DATA0                                0x148 0x3B0 0x4D4 0x0 0x0
+#define MX8MM_IOMUXC_SAI5_RXD0_SAI1_TX_DATA2                                0x148 0x3B0 0x000 0x1 0x0
+#define MX8MM_IOMUXC_SAI5_RXD0_PDM_DATA0                                    0x148 0x3B0 0x534 0x4 0x0
+#define MX8MM_IOMUXC_SAI5_RXD0_GPIO3_IO21                                   0x148 0x3B0 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SAI5_RXD1_SAI5_RX_DATA1                                0x14C 0x3B4 0x4D8 0x0 0x0
+#define MX8MM_IOMUXC_SAI5_RXD1_SAI1_TX_DATA3                                0x14C 0x3B4 0x000 0x1 0x0
+#define MX8MM_IOMUXC_SAI5_RXD1_SAI1_TX_SYNC                                 0x14C 0x3B4 0x4CC 0x2 0x0
+#define MX8MM_IOMUXC_SAI5_RXD1_SAI5_TX_SYNC                                 0x14C 0x3B4 0x4EC 0x3 0x0
+#define MX8MM_IOMUXC_SAI5_RXD1_PDM_DATA1                                    0x14C 0x3B4 0x538 0x4 0x0
+#define MX8MM_IOMUXC_SAI5_RXD1_GPIO3_IO22                                   0x14C 0x3B4 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SAI5_RXD2_SAI5_RX_DATA2                                0x150 0x3B8 0x4DC 0x0 0x0
+#define MX8MM_IOMUXC_SAI5_RXD2_SAI1_TX_DATA4                                0x150 0x3B8 0x000 0x1 0x0
+#define MX8MM_IOMUXC_SAI5_RXD2_SAI1_TX_SYNC                                 0x150 0x3B8 0x4CC 0x2 0x1
+#define MX8MM_IOMUXC_SAI5_RXD2_SAI5_TX_BCLK                                 0x150 0x3B8 0x4E8 0x3 0x0
+#define MX8MM_IOMUXC_SAI5_RXD2_PDM_DATA2                                    0x150 0x3B8 0x53c 0x4 0x0
+#define MX8MM_IOMUXC_SAI5_RXD2_GPIO3_IO23                                   0x150 0x3B8 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SAI5_RXD3_SAI5_RX_DATA3                                0x154 0x3BC 0x4E0 0x0 0x0
+#define MX8MM_IOMUXC_SAI5_RXD3_SAI1_TX_DATA5                                0x154 0x3BC 0x000 0x1 0x0
+#define MX8MM_IOMUXC_SAI5_RXD3_SAI1_TX_SYNC                                 0x154 0x3BC 0x4CC 0x2 0x2
+#define MX8MM_IOMUXC_SAI5_RXD3_SAI5_TX_DATA0                                0x154 0x3BC 0x000 0x3 0x0
+#define MX8MM_IOMUXC_SAI5_RXD3_PDM_DATA3                                    0x154 0x3BC 0x540 0x4 0x0
+#define MX8MM_IOMUXC_SAI5_RXD3_GPIO3_IO24                                   0x154 0x3BC 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SAI5_MCLK_SAI5_MCLK                                    0x158 0x3C0 0x52C 0x0 0x0
+#define MX8MM_IOMUXC_SAI5_MCLK_SAI1_TX_BCLK                                 0x158 0x3C0 0x4C8 0x1 0x0
+#define MX8MM_IOMUXC_SAI5_MCLK_SAI4_MCLK                                    0x158 0x3C0 0x000 0x2 0x0
+#define MX8MM_IOMUXC_SAI5_MCLK_GPIO3_IO25                                   0x158 0x3C0 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SAI5_MCLK_CCMSRCGPCMIX_TESTER_ACK                      0x158 0x3C0 0x000 0x6 0x0
+#define MX8MM_IOMUXC_SAI1_RXFS_SAI1_RX_SYNC                                 0x15C 0x3C4 0x4C4 0x0 0x0
+#define MX8MM_IOMUXC_SAI1_RXFS_SAI5_RX_SYNC                                 0x15C 0x3C4 0x4E4 0x1 0x1
+#define MX8MM_IOMUXC_SAI1_RXFS_CORESIGHT_TRACE_CLK                          0x15C 0x3C4 0x000 0x4 0x0
+#define MX8MM_IOMUXC_SAI1_RXFS_GPIO4_IO0                                    0x15C 0x3C4 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SAI1_RXFS_SIM_M_HADDR15                                0x15C 0x3C4 0x000 0x7 0x0
+#define MX8MM_IOMUXC_SAI1_RXC_SAI1_RX_BCLK                                  0x160 0x3C8 0x000 0x0 0x0
+#define MX8MM_IOMUXC_SAI1_RXC_SAI5_RX_BCLK                                  0x160 0x3C8 0x4D0 0x1 0x1
+#define MX8MM_IOMUXC_SAI1_RXC_CORESIGHT_TRACE_CTL                           0x160 0x3C8 0x000 0x4 0x0
+#define MX8MM_IOMUXC_SAI1_RXC_GPIO4_IO1                                     0x160 0x3C8 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SAI1_RXC_SIM_M_HADDR16                                 0x160 0x3C8 0x000 0x7 0x0
+#define MX8MM_IOMUXC_SAI1_RXD0_SAI1_RX_DATA0                                0x164 0x3CC 0x000 0x0 0x0
+#define MX8MM_IOMUXC_SAI1_RXD0_SAI5_RX_DATA0                                0x164 0x3CC 0x4D4 0x1 0x1
+#define MX8MM_IOMUXC_SAI1_RXD0_PDM_DATA0                                    0x164 0x3CC 0x534 0x3 0x1
+#define MX8MM_IOMUXC_SAI1_RXD0_CORESIGHT_TRACE0                             0x164 0x3CC 0x000 0x4 0x0
+#define MX8MM_IOMUXC_SAI1_RXD0_GPIO4_IO2                                    0x164 0x3CC 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SAI1_RXD0_CCMSRCGPCMIX_BOOT_CFG0                       0x164 0x3CC 0x000 0x6 0x0
+#define MX8MM_IOMUXC_SAI1_RXD0_SIM_M_HADDR17                                0x164 0x3CC 0x000 0x7 0x0
+#define MX8MM_IOMUXC_SAI1_RXD1_SAI1_RX_DATA1                                0x168 0x3D0 0x000 0x0 0x0
+#define MX8MM_IOMUXC_SAI1_RXD1_SAI5_RX_DATA1                                0x168 0x3D0 0x4D8 0x1 0x1
+#define MX8MM_IOMUXC_SAI1_RXD1_PDM_DATA1                                    0x168 0x3D0 0x538 0x3 0x1
+#define MX8MM_IOMUXC_SAI1_RXD1_CORESIGHT_TRACE1                             0x168 0x3D0 0x000 0x4 0x0
+#define MX8MM_IOMUXC_SAI1_RXD1_GPIO4_IO3                                    0x168 0x3D0 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SAI1_RXD1_CCMSRCGPCMIX_BOOT_CFG1                       0x168 0x3D0 0x000 0x6 0x0
+#define MX8MM_IOMUXC_SAI1_RXD1_SIM_M_HADDR18                                0x168 0x3D0 0x000 0x7 0x0
+#define MX8MM_IOMUXC_SAI1_RXD2_SAI1_RX_DATA2                                0x16C 0x3D4 0x000 0x0 0x0
+#define MX8MM_IOMUXC_SAI1_RXD2_SAI5_RX_DATA2                                0x16C 0x3D4 0x4DC 0x1 0x1
+#define MX8MM_IOMUXC_SAI1_RXD2_PDM_DATA2                                    0x16C 0x3D4 0x53C 0x3 0x1
+#define MX8MM_IOMUXC_SAI1_RXD2_CORESIGHT_TRACE2                             0x16C 0x3D4 0x000 0x4 0x0
+#define MX8MM_IOMUXC_SAI1_RXD2_GPIO4_IO4                                    0x16C 0x3D4 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SAI1_RXD2_CCMSRCGPCMIX_BOOT_CFG2                       0x16C 0x3D4 0x000 0x6 0x0
+#define MX8MM_IOMUXC_SAI1_RXD2_SIM_M_HADDR19                                0x16C 0x3D4 0x000 0x7 0x0
+#define MX8MM_IOMUXC_SAI1_RXD3_SAI1_RX_DATA3                                0x170 0x3D8 0x4E0 0x0 0x1
+#define MX8MM_IOMUXC_SAI1_RXD3_SAI5_RX_DATA3                                0x170 0x3D8 0x000 0x1 0x0
+#define MX8MM_IOMUXC_SAI1_RXD3_PDM_DATA3                                    0x170 0x3D8 0x540 0x3 0x1
+#define MX8MM_IOMUXC_SAI1_RXD3_CORESIGHT_TRACE3                             0x170 0x3D8 0x000 0x4 0x0
+#define MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5                                    0x170 0x3D8 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SAI1_RXD3_CCMSRCGPCMIX_BOOT_CFG3                       0x170 0x3D8 0x000 0x6 0x0
+#define MX8MM_IOMUXC_SAI1_RXD3_SIM_M_HADDR20                                0x170 0x3D8 0x000 0x7 0x0
+#define MX8MM_IOMUXC_SAI1_RXD4_SAI1_RX_DATA4                                0x174 0x3DC 0x000 0x0 0x0
+#define MX8MM_IOMUXC_SAI1_RXD4_SAI6_TX_BCLK                                 0x174 0x3DC 0x51C 0x1 0x0
+#define MX8MM_IOMUXC_SAI1_RXD4_SAI6_RX_BCLK                                 0x174 0x3DC 0x510 0x2 0x0
+#define MX8MM_IOMUXC_SAI1_RXD4_CORESIGHT_TRACE4                             0x174 0x3DC 0x000 0x4 0x0
+#define MX8MM_IOMUXC_SAI1_RXD4_GPIO4_IO6                                    0x174 0x3DC 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SAI1_RXD4_CCMSRCGPCMIX_BOOT_CFG4                       0x174 0x3DC 0x000 0x6 0x0
+#define MX8MM_IOMUXC_SAI1_RXD4_SIM_M_HADDR21                                0x174 0x3DC 0x000 0x7 0x0
+#define MX8MM_IOMUXC_SAI1_RXD5_SAI1_RX_DATA5                                0x178 0x3E0 0x000 0x0 0x0
+#define MX8MM_IOMUXC_SAI1_RXD5_SAI6_TX_DATA0                                0x178 0x3E0 0x000 0x1 0x0
+#define MX8MM_IOMUXC_SAI1_RXD5_SAI6_RX_DATA0                                0x178 0x3E0 0x514 0x2 0x0
+#define MX8MM_IOMUXC_SAI1_RXD5_SAI1_RX_SYNC                                 0x178 0x3E0 0x4C4 0x3 0x1
+#define MX8MM_IOMUXC_SAI1_RXD5_CORESIGHT_TRACE5                             0x178 0x3E0 0x000 0x4 0x0
+#define MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7                                    0x178 0x3E0 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SAI1_RXD5_CCMSRCGPCMIX_BOOT_CFG5                       0x178 0x3E0 0x000 0x6 0x0
+#define MX8MM_IOMUXC_SAI1_RXD5_SIM_M_HADDR22                                0x178 0x3E0 0x000 0x7 0x0
+#define MX8MM_IOMUXC_SAI1_RXD6_SAI1_RX_DATA6                                0x17C 0x3E4 0x520 0x0 0x0
+#define MX8MM_IOMUXC_SAI1_RXD6_SAI6_TX_SYNC                                 0x17C 0x3E4 0x000 0x1 0x0
+#define MX8MM_IOMUXC_SAI1_RXD6_SAI6_RX_SYNC                                 0x17C 0x3E4 0x518 0x2 0x0
+#define MX8MM_IOMUXC_SAI1_RXD6_CORESIGHT_TRACE6                             0x17C 0x3E4 0x000 0x4 0x0
+#define MX8MM_IOMUXC_SAI1_RXD6_GPIO4_IO8                                    0x17C 0x3E4 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SAI1_RXD6_CCMSRCGPCMIX_BOOT_CFG6                       0x17C 0x3E4 0x000 0x6 0x0
+#define MX8MM_IOMUXC_SAI1_RXD6_SIM_M_HADDR23                                0x17C 0x3E4 0x000 0x7 0x0
+#define MX8MM_IOMUXC_SAI1_RXD7_SAI1_RX_DATA7                                0x180 0x3E8 0x000 0x0 0x0
+#define MX8MM_IOMUXC_SAI1_RXD7_SAI6_MCLK                                    0x180 0x3E8 0x530 0x1 0x0
+#define MX8MM_IOMUXC_SAI1_RXD7_SAI1_TX_SYNC                                 0x180 0x3E8 0x4CC 0x2 0x4
+#define MX8MM_IOMUXC_SAI1_RXD7_SAI1_TX_DATA4                                0x180 0x3E8 0x000 0x3 0x0
+#define MX8MM_IOMUXC_SAI1_RXD7_CORESIGHT_TRACE7                             0x180 0x3E8 0x000 0x4 0x0
+#define MX8MM_IOMUXC_SAI1_RXD7_GPIO4_IO9                                    0x180 0x3E8 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SAI1_RXD7_CCMSRCGPCMIX_BOOT_CFG7                       0x180 0x3E8 0x000 0x6 0x0
+#define MX8MM_IOMUXC_SAI1_RXD7_SIM_M_HADDR24                                0x180 0x3E8 0x000 0x7 0x0
+#define MX8MM_IOMUXC_SAI1_TXFS_SAI1_TX_SYNC                                 0x184 0x3EC 0x4CC 0x0 0x3
+#define MX8MM_IOMUXC_SAI1_TXFS_SAI5_TX_SYNC                                 0x184 0x3EC 0x4EC 0x1 0x1
+#define MX8MM_IOMUXC_SAI1_TXFS_CORESIGHT_EVENTO                             0x184 0x3EC 0x000 0x4 0x0
+#define MX8MM_IOMUXC_SAI1_TXFS_GPIO4_IO10                                   0x184 0x3EC 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SAI1_TXFS_SIM_M_HADDR25                                0x184 0x3EC 0x000 0x7 0x0
+#define MX8MM_IOMUXC_SAI1_TXC_SAI1_TX_BCLK                                  0x188 0x3F0 0x4C8 0x0 0x1
+#define MX8MM_IOMUXC_SAI1_TXC_SAI5_TX_BCLK                                  0x188 0x3F0 0x4E8 0x1 0x1
+#define MX8MM_IOMUXC_SAI1_TXC_CORESIGHT_EVENTI                              0x188 0x3F0 0x000 0x4 0x0
+#define MX8MM_IOMUXC_SAI1_TXC_GPIO4_IO11                                    0x188 0x3F0 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SAI1_TXC_SIM_M_HADDR26                                 0x188 0x3F0 0x000 0x7 0x0
+#define MX8MM_IOMUXC_SAI1_TXD0_SAI1_TX_DATA0                                0x18C 0x3F4 0x000 0x0 0x0
+#define MX8MM_IOMUXC_SAI1_TXD0_SAI5_TX_DATA0                                0x18C 0x3F4 0x000 0x1 0x0
+#define MX8MM_IOMUXC_SAI1_TXD0_CORESIGHT_TRACE8                             0x18C 0x3F4 0x000 0x4 0x0
+#define MX8MM_IOMUXC_SAI1_TXD0_GPIO4_IO12                                   0x18C 0x3F4 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SAI1_TXD0_CCMSRCGPCMIX_BOOT_CFG8                       0x18C 0x3F4 0x000 0x6 0x0
+#define MX8MM_IOMUXC_SAI1_TXD0_SIM_M_HADDR27                                0x18C 0x3F4 0x000 0x7 0x0
+#define MX8MM_IOMUXC_SAI1_TXD1_SAI1_TX_DATA1                                0x190 0x3F8 0x000 0x0 0x0
+#define MX8MM_IOMUXC_SAI1_TXD1_SAI5_TX_DATA1                                0x190 0x3F8 0x000 0x1 0x0
+#define MX8MM_IOMUXC_SAI1_TXD1_CORESIGHT_TRACE9                             0x190 0x3F8 0x000 0x4 0x0
+#define MX8MM_IOMUXC_SAI1_TXD1_GPIO4_IO13                                   0x190 0x3F8 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SAI1_TXD1_CCMSRCGPCMIX_BOOT_CFG9                       0x190 0x3F8 0x000 0x6 0x0
+#define MX8MM_IOMUXC_SAI1_TXD1_SIM_M_HADDR28                                0x190 0x3F8 0x000 0x7 0x0
+#define MX8MM_IOMUXC_SAI1_TXD2_SAI1_TX_DATA2                                0x194 0x3FC 0x000 0x0 0x0
+#define MX8MM_IOMUXC_SAI1_TXD2_SAI5_TX_DATA2                                0x194 0x3FC 0x000 0x1 0x0
+#define MX8MM_IOMUXC_SAI1_TXD2_CORESIGHT_TRACE10                            0x194 0x3FC 0x000 0x4 0x0
+#define MX8MM_IOMUXC_SAI1_TXD2_GPIO4_IO14                                   0x194 0x3FC 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SAI1_TXD2_CCMSRCGPCMIX_BOOT_CFG10                      0x194 0x3FC 0x000 0x6 0x0
+#define MX8MM_IOMUXC_SAI1_TXD2_SIM_M_HADDR29                                0x194 0x3FC 0x000 0x7 0x0
+#define MX8MM_IOMUXC_SAI1_TXD3_SAI1_TX_DATA3                                0x198 0x400 0x000 0x0 0x0
+#define MX8MM_IOMUXC_SAI1_TXD3_SAI5_TX_DATA3                                0x198 0x400 0x000 0x1 0x0
+#define MX8MM_IOMUXC_SAI1_TXD3_CORESIGHT_TRACE11                            0x198 0x400 0x000 0x4 0x0
+#define MX8MM_IOMUXC_SAI1_TXD3_GPIO4_IO15                                   0x198 0x400 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SAI1_TXD3_CCMSRCGPCMIX_BOOT_CFG11                      0x198 0x400 0x000 0x6 0x0
+#define MX8MM_IOMUXC_SAI1_TXD3_SIM_M_HADDR30                                0x198 0x400 0x000 0x7 0x0
+#define MX8MM_IOMUXC_SAI1_TXD4_SAI1_TX_DATA4                                0x19C 0x404 0x000 0x0 0x0
+#define MX8MM_IOMUXC_SAI1_TXD4_SAI6_RX_BCLK                                 0x19C 0x404 0x510 0x1 0x1
+#define MX8MM_IOMUXC_SAI1_TXD4_SAI6_TX_BCLK                                 0x19C 0x404 0x51C 0x2 0x1
+#define MX8MM_IOMUXC_SAI1_TXD4_CORESIGHT_TRACE12                            0x19C 0x404 0x000 0x4 0x0
+#define MX8MM_IOMUXC_SAI1_TXD4_GPIO4_IO16                                   0x19C 0x404 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SAI1_TXD4_CCMSRCGPCMIX_BOOT_CFG12                      0x19C 0x404 0x000 0x6 0x0
+#define MX8MM_IOMUXC_SAI1_TXD4_SIM_M_HADDR31                                0x19C 0x404 0x000 0x7 0x0
+#define MX8MM_IOMUXC_SAI1_TXD5_SAI1_TX_DATA5                                0x1A0 0x408 0x000 0x0 0x0
+#define MX8MM_IOMUXC_SAI1_TXD5_SAI6_RX_DATA0                                0x1A0 0x408 0x514 0x1 0x1
+#define MX8MM_IOMUXC_SAI1_TXD5_SAI6_TX_DATA0                                0x1A0 0x408 0x000 0x2 0x0
+#define MX8MM_IOMUXC_SAI1_TXD5_CORESIGHT_TRACE13                            0x1A0 0x408 0x000 0x4 0x0
+#define MX8MM_IOMUXC_SAI1_TXD5_GPIO4_IO17                                   0x1A0 0x408 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SAI1_TXD5_CCMSRCGPCMIX_BOOT_CFG13                      0x1A0 0x408 0x000 0x6 0x0
+#define MX8MM_IOMUXC_SAI1_TXD5_SIM_M_HBURST0                                0x1A0 0x408 0x000 0x7 0x0
+#define MX8MM_IOMUXC_SAI1_TXD6_SAI1_TX_DATA6                                0x1A4 0x40C 0x000 0x0 0x0
+#define MX8MM_IOMUXC_SAI1_TXD6_SAI6_RX_SYNC                                 0x1A4 0x40C 0x518 0x1 0x1
+#define MX8MM_IOMUXC_SAI1_TXD6_SAI6_TX_SYNC                                 0x1A4 0x40C 0x520 0x2 0x1
+#define MX8MM_IOMUXC_SAI1_TXD6_CORESIGHT_TRACE14                            0x1A4 0x40C 0x000 0x4 0x0
+#define MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18                                   0x1A4 0x40C 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SAI1_TXD6_CCMSRCGPCMIX_BOOT_CFG14                      0x1A4 0x40C 0x000 0x6 0x0
+#define MX8MM_IOMUXC_SAI1_TXD6_SIM_M_HBURST1                                0x1A4 0x40C 0x000 0x7 0x0
+#define MX8MM_IOMUXC_SAI1_TXD7_SAI1_TX_DATA7                                0x1A8 0x410 0x000 0x0 0x0
+#define MX8MM_IOMUXC_SAI1_TXD7_SAI6_MCLK                                    0x1A8 0x410 0x530 0x1 0x1
+#define MX8MM_IOMUXC_SAI1_TXD7_PDM_CLK                                      0x1A8 0x410 0x000 0x3 0x0
+#define MX8MM_IOMUXC_SAI1_TXD7_CORESIGHT_TRACE15                            0x1A8 0x410 0x000 0x4 0x0
+#define MX8MM_IOMUXC_SAI1_TXD7_GPIO4_IO19                                   0x1A8 0x410 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SAI1_TXD7_CCMSRCGPCMIX_BOOT_CFG15                      0x1A8 0x410 0x000 0x6 0x0
+#define MX8MM_IOMUXC_SAI1_TXD7_SIM_M_HBURST2                                0x1A8 0x410 0x000 0x7 0x0
+#define MX8MM_IOMUXC_SAI1_MCLK_SAI1_MCLK                                    0x1AC 0x414 0x000 0x0 0x0
+#define MX8MM_IOMUXC_SAI1_MCLK_SAI5_MCLK                                    0x1AC 0x414 0x52C 0x1 0x1
+#define MX8MM_IOMUXC_SAI1_MCLK_SAI1_TX_BCLK                                 0x1AC 0x414 0x4C8 0x2 0x2
+#define MX8MM_IOMUXC_SAI1_MCLK_PDM_CLK                                      0x1AC 0x414 0x000 0x3 0x0
+#define MX8MM_IOMUXC_SAI1_MCLK_GPIO4_IO20                                   0x1AC 0x414 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SAI1_MCLK_SIM_M_HRESP                                  0x1AC 0x414 0x000 0x7 0x0
+#define MX8MM_IOMUXC_SAI2_RXFS_SAI2_RX_SYNC                                 0x1B0 0x418 0x000 0x0 0x0
+#define MX8MM_IOMUXC_SAI2_RXFS_SAI5_TX_SYNC                                 0x1B0 0x418 0x4EC 0x1 0x2
+#define MX8MM_IOMUXC_SAI2_RXFS_GPIO4_IO21                                   0x1B0 0x418 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SAI2_RXFS_SIM_M_HSIZE0                                 0x1B0 0x418 0x000 0x7 0x0
+#define MX8MM_IOMUXC_SAI2_RXC_SAI2_RX_BCLK                                  0x1B4 0x41C 0x000 0x0 0x0
+#define MX8MM_IOMUXC_SAI2_RXC_SAI5_TX_BCLK                                  0x1B4 0x41C 0x4E8 0x1 0x2
+#define MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22                                    0x1B4 0x41C 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SAI2_RXC_SIM_M_HSIZE1                                  0x1B4 0x41C 0x000 0x7 0x0
+#define MX8MM_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0                                0x1B8 0x420 0x000 0x0 0x0
+#define MX8MM_IOMUXC_SAI2_RXD0_SAI5_TX_DATA0                                0x1B8 0x420 0x000 0x1 0x0
+#define MX8MM_IOMUXC_SAI2_RXD0_GPIO4_IO23                                   0x1B8 0x420 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SAI2_RXD0_SIM_M_HSIZE2                                 0x1B8 0x420 0x000 0x7 0x0
+#define MX8MM_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC                                 0x1BC 0x424 0x000 0x0 0x0
+#define MX8MM_IOMUXC_SAI2_TXFS_SAI5_TX_DATA1                                0x1BC 0x424 0x000 0x1 0x0
+#define MX8MM_IOMUXC_SAI2_TXFS_GPIO4_IO24                                   0x1BC 0x424 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SAI2_TXFS_SIM_M_HWRITE                                 0x1BC 0x424 0x000 0x7 0x0
+#define MX8MM_IOMUXC_SAI2_TXC_SAI2_TX_BCLK                                  0x1C0 0x428 0x000 0x0 0x0
+#define MX8MM_IOMUXC_SAI2_TXC_SAI5_TX_DATA2                                 0x1C0 0x428 0x000 0x1 0x0
+#define MX8MM_IOMUXC_SAI2_TXC_GPIO4_IO25                                    0x1C0 0x428 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SAI2_TXC_SIM_M_HREADYOUT                               0x1C0 0x428 0x000 0x7 0x0
+#define MX8MM_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0                                0x1C4 0x42C 0x000 0x0 0x0
+#define MX8MM_IOMUXC_SAI2_TXD0_SAI5_TX_DATA3                                0x1C4 0x42C 0x000 0x1 0x0
+#define MX8MM_IOMUXC_SAI2_TXD0_GPIO4_IO26                                   0x1C4 0x42C 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SAI2_TXD0_TPSMP_CLK                                    0x1C4 0x42C 0x000 0x7 0x0
+#define MX8MM_IOMUXC_SAI2_MCLK_SAI2_MCLK                                    0x1C8 0x430 0x000 0x0 0x0
+#define MX8MM_IOMUXC_SAI2_MCLK_SAI5_MCLK                                    0x1C8 0x430 0x52C 0x1 0x2
+#define MX8MM_IOMUXC_SAI2_MCLK_GPIO4_IO27                                   0x1C8 0x430 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SAI2_MCLK_TPSMP_HDATA_DIR                              0x1C8 0x430 0x000 0x7 0x0
+#define MX8MM_IOMUXC_SAI3_RXFS_SAI3_RX_SYNC                                 0x1CC 0x434 0x000 0x0 0x0
+#define MX8MM_IOMUXC_SAI3_RXFS_GPT1_CAPTURE1                                0x1CC 0x434 0x000 0x1 0x0
+#define MX8MM_IOMUXC_SAI3_RXFS_SAI5_RX_SYNC                                 0x1CC 0x434 0x4E4 0x2 0x2
+#define MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28                                   0x1CC 0x434 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SAI3_RXFS_TPSMP_HTRANS0                                0x1CC 0x434 0x000 0x7 0x0
+#define MX8MM_IOMUXC_SAI3_RXC_SAI3_RX_BCLK                                  0x1D0 0x438 0x000 0x0 0x0
+#define MX8MM_IOMUXC_SAI3_RXC_GPT1_CAPTURE2                                 0x1D0 0x438 0x000 0x1 0x0
+#define MX8MM_IOMUXC_SAI3_RXC_SAI5_RX_BCLK                                  0x1D0 0x438 0x4D0 0x2 0x2
+#define MX8MM_IOMUXC_SAI3_RXC_GPIO4_IO29                                    0x1D0 0x438 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SAI3_RXC_TPSMP_HTRANS1                                 0x1D0 0x438 0x000 0x7 0x0
+#define MX8MM_IOMUXC_SAI3_RXD_SAI3_RX_DATA0                                 0x1D4 0x43C 0x000 0x0 0x0
+#define MX8MM_IOMUXC_SAI3_RXD_GPT1_COMPARE1                                 0x1D4 0x43C 0x000 0x1 0x0
+#define MX8MM_IOMUXC_SAI3_RXD_SAI5_RX_DATA0                                 0x1D4 0x43C 0x4D4 0x2 0x2
+#define MX8MM_IOMUXC_SAI3_RXD_GPIO4_IO30                                    0x1D4 0x43C 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SAI3_RXD_TPSMP_HDATA0                                  0x1D4 0x43C 0x000 0x7 0x0
+#define MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC                                 0x1D8 0x440 0x000 0x0 0x0
+#define MX8MM_IOMUXC_SAI3_TXFS_GPT1_CLK                                     0x1D8 0x440 0x000 0x1 0x0
+#define MX8MM_IOMUXC_SAI3_TXFS_SAI5_RX_DATA1                                0x1D8 0x440 0x4D8 0x2 0x2
+#define MX8MM_IOMUXC_SAI3_TXFS_GPIO4_IO31                                   0x1D8 0x440 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SAI3_TXFS_TPSMP_HDATA1                                 0x1D8 0x440 0x000 0x7 0x0
+#define MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK                                  0x1DC 0x444 0x000 0x0 0x0
+#define MX8MM_IOMUXC_SAI3_TXC_GPT1_COMPARE2                                 0x1DC 0x444 0x000 0x1 0x0
+#define MX8MM_IOMUXC_SAI3_TXC_SAI5_RX_DATA2                                 0x1DC 0x444 0x4DC 0x2 0x2
+#define MX8MM_IOMUXC_SAI3_TXC_GPIO5_IO0                                     0x1DC 0x444 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SAI3_TXC_TPSMP_HDATA2                                  0x1DC 0x444 0x000 0x7 0x0
+#define MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0                                 0x1E0 0x448 0x000 0x0 0x0
+#define MX8MM_IOMUXC_SAI3_TXD_GPT1_COMPARE3                                 0x1E0 0x448 0x000 0x1 0x0
+#define MX8MM_IOMUXC_SAI3_TXD_SAI5_RX_DATA3                                 0x1E0 0x448 0x4E0 0x2 0x2
+#define MX8MM_IOMUXC_SAI3_TXD_GPIO5_IO1                                     0x1E0 0x448 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SAI3_TXD_TPSMP_HDATA3                                  0x1E0 0x448 0x000 0x7 0x0
+#define MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK                                    0x1E4 0x44C 0x000 0x0 0x0
+#define MX8MM_IOMUXC_SAI3_MCLK_PWM4_OUT                                     0x1E4 0x44C 0x000 0x1 0x0
+#define MX8MM_IOMUXC_SAI3_MCLK_SAI5_MCLK                                    0x1E4 0x44C 0x52C 0x2 0x3
+#define MX8MM_IOMUXC_SAI3_MCLK_GPIO5_IO2                                    0x1E4 0x44C 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SAI3_MCLK_TPSMP_HDATA4                                 0x1E4 0x44C 0x000 0x7 0x0
+#define MX8MM_IOMUXC_SPDIF_TX_SPDIF1_OUT                                    0x1E8 0x450 0x000 0x0 0x0
+#define MX8MM_IOMUXC_SPDIF_TX_PWM3_OUT                                      0x1E8 0x450 0x000 0x1 0x0
+#define MX8MM_IOMUXC_SPDIF_TX_GPIO5_IO3                                     0x1E8 0x450 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SPDIF_TX_TPSMP_HDATA5                                  0x1E8 0x450 0x000 0x7 0x0
+#define MX8MM_IOMUXC_SPDIF_RX_SPDIF1_IN                                     0x1EC 0x454 0x000 0x0 0x0
+#define MX8MM_IOMUXC_SPDIF_RX_PWM2_OUT                                      0x1EC 0x454 0x000 0x1 0x0
+#define MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4                                     0x1EC 0x454 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SPDIF_RX_TPSMP_HDATA6                                  0x1EC 0x454 0x000 0x7 0x0
+#define MX8MM_IOMUXC_SPDIF_EXT_CLK_SPDIF1_EXT_CLK                           0x1F0 0x458 0x000 0x0 0x0
+#define MX8MM_IOMUXC_SPDIF_EXT_CLK_PWM1_OUT                                 0x1F0 0x458 0x000 0x1 0x0
+#define MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5                                0x1F0 0x458 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SPDIF_EXT_CLK_TPSMP_HDATA7                             0x1F0 0x458 0x000 0x7 0x0
+#define MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK                                0x1F4 0x45C 0x000 0x0 0x0
+#define MX8MM_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX                               0x1F4 0x45C 0x504 0x1 0x0
+#define MX8MM_IOMUXC_ECSPI1_SCLK_UART3_DTE_TX                               0x1F4 0x45C 0x000 0x1 0x0
+#define MX8MM_IOMUXC_ECSPI1_SCLK_GPIO5_IO6                                  0x1F4 0x45C 0x000 0x5 0x0
+#define MX8MM_IOMUXC_ECSPI1_SCLK_TPSMP_HDATA8                               0x1F4 0x45C 0x000 0x7 0x0
+#define MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI                                0x1F8 0x460 0x000 0x0 0x0
+#define MX8MM_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX                               0x1F8 0x460 0x000 0x1 0x0
+#define MX8MM_IOMUXC_ECSPI1_MOSI_UART3_DTE_RX                               0x1F8 0x460 0x504 0x1 0x1
+#define MX8MM_IOMUXC_ECSPI1_MOSI_GPIO5_IO7                                  0x1F8 0x460 0x000 0x5 0x0
+#define MX8MM_IOMUXC_ECSPI1_MOSI_TPSMP_HDATA9                               0x1F8 0x460 0x000 0x7 0x0
+#define MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO                                0x1FC 0x464 0x000 0x0 0x0
+#define MX8MM_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B                            0x1FC 0x464 0x000 0x1 0x0
+#define MX8MM_IOMUXC_ECSPI1_MISO_UART3_DTE_RTS_B                            0x1FC 0x464 0x500 0x1 0x0
+#define MX8MM_IOMUXC_ECSPI1_MISO_GPIO5_IO8                                  0x1FC 0x464 0x000 0x5 0x0
+#define MX8MM_IOMUXC_ECSPI1_MISO_TPSMP_HDATA10                              0x1FC 0x464 0x000 0x7 0x0
+#define MX8MM_IOMUXC_ECSPI1_SS0_ECSPI1_SS0                                  0x200 0x468 0x000 0x0 0x0
+#define MX8MM_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B                             0x200 0x468 0x500 0x1 0x1
+#define MX8MM_IOMUXC_ECSPI1_SS0_UART3_DTE_CTS_B                             0x200 0x468 0x000 0x1 0x0
+#define MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9                                   0x200 0x468 0x000 0x5 0x0
+#define MX8MM_IOMUXC_ECSPI1_SS0_TPSMP_HDATA11                               0x200 0x468 0x000 0x7 0x0
+#define MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK                                0x204 0x46C 0x000 0x0 0x0
+#define MX8MM_IOMUXC_ECSPI2_SCLK_UART4_DCE_RX                               0x204 0x46C 0x50C 0x1 0x0
+#define MX8MM_IOMUXC_ECSPI2_SCLK_UART4_DTE_TX                               0x204 0x46C 0x000 0x1 0x0
+#define MX8MM_IOMUXC_ECSPI2_SCLK_GPIO5_IO10                                 0x204 0x46C 0x000 0x5 0x0
+#define MX8MM_IOMUXC_ECSPI2_SCLK_TPSMP_HDATA12                              0x204 0x46C 0x000 0x7 0x0
+#define MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI                                0x208 0x470 0x000 0x0 0x0
+#define MX8MM_IOMUXC_ECSPI2_MOSI_UART4_DCE_TX                               0x208 0x470 0x000 0x1 0x0
+#define MX8MM_IOMUXC_ECSPI2_MOSI_UART4_DTE_RX                               0x208 0x470 0x50C 0x1 0x1
+#define MX8MM_IOMUXC_ECSPI2_MOSI_GPIO5_IO11                                 0x208 0x470 0x000 0x5 0x0
+#define MX8MM_IOMUXC_ECSPI2_MOSI_TPSMP_HDATA13                              0x208 0x470 0x000 0x7 0x0
+#define MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO                                0x20C 0x474 0x000 0x0 0x0
+#define MX8MM_IOMUXC_ECSPI2_MISO_UART4_DCE_CTS_B                            0x20C 0x474 0x000 0x1 0x0
+#define MX8MM_IOMUXC_ECSPI2_MISO_UART4_DTE_RTS_B                            0x20C 0x474 0x508 0x1 0x0
+#define MX8MM_IOMUXC_ECSPI2_MISO_GPIO5_IO12                                 0x20C 0x474 0x000 0x5 0x0
+#define MX8MM_IOMUXC_ECSPI2_MISO_TPSMP_HDATA14                              0x20C 0x474 0x000 0x7 0x0
+#define MX8MM_IOMUXC_ECSPI2_SS0_ECSPI2_SS0                                  0x210 0x478 0x000 0x0 0x0
+#define MX8MM_IOMUXC_ECSPI2_SS0_UART4_DCE_RTS_B                             0x210 0x478 0x508 0x1 0x1
+#define MX8MM_IOMUXC_ECSPI2_SS0_UART4_DTE_CTS_B                             0x210 0x478 0x000 0x1 0x0
+#define MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13                                  0x210 0x478 0x000 0x5 0x0
+#define MX8MM_IOMUXC_ECSPI2_SS0_TPSMP_HDATA15                               0x210 0x478 0x000 0x7 0x0
+#define MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL                                      0x214 0x47C 0x000 0x0 0x0
+#define MX8MM_IOMUXC_I2C1_SCL_ENET1_MDC                                     0x214 0x47C 0x000 0x1 0x0
+#define MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14                                    0x214 0x47C 0x000 0x5 0x0
+#define MX8MM_IOMUXC_I2C1_SCL_TPSMP_HDATA16                                 0x214 0x47C 0x000 0x7 0x0
+#define MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA                                      0x218 0x480 0x000 0x0 0x0
+#define MX8MM_IOMUXC_I2C1_SDA_ENET1_MDIO                                    0x218 0x480 0x4C0 0x1 0x2
+#define MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15                                    0x218 0x480 0x000 0x5 0x0
+#define MX8MM_IOMUXC_I2C1_SDA_TPSMP_HDATA17                                 0x218 0x480 0x000 0x7 0x0
+#define MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL                                      0x21C 0x484 0x000 0x0 0x0
+#define MX8MM_IOMUXC_I2C2_SCL_ENET1_1588_EVENT1_IN                          0x21C 0x484 0x000 0x1 0x0
+#define MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16                                    0x21C 0x484 0x000 0x5 0x0
+#define MX8MM_IOMUXC_I2C2_SCL_TPSMP_HDATA18                                 0x21C 0x484 0x000 0x7 0x0
+#define MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA                                      0x220 0x488 0x000 0x0 0x0
+#define MX8MM_IOMUXC_I2C2_SDA_ENET1_1588_EVENT1_OUT                         0x220 0x488 0x000 0x1 0x0
+#define MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17                                    0x220 0x488 0x000 0x5 0x0
+#define MX8MM_IOMUXC_I2C2_SDA_TPSMP_HDATA19                                 0x220 0x488 0x000 0x7 0x0
+#define MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL                                      0x224 0x48C 0x000 0x0 0x0
+#define MX8MM_IOMUXC_I2C3_SCL_PWM4_OUT                                      0x224 0x48C 0x000 0x1 0x0
+#define MX8MM_IOMUXC_I2C3_SCL_GPT2_CLK                                      0x224 0x48C 0x000 0x2 0x0
+#define MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18                                    0x224 0x48C 0x000 0x5 0x0
+#define MX8MM_IOMUXC_I2C3_SCL_TPSMP_HDATA20                                 0x224 0x48C 0x000 0x7 0x0
+#define MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA                                      0x228 0x490 0x000 0x0 0x0
+#define MX8MM_IOMUXC_I2C3_SDA_PWM3_OUT                                      0x228 0x490 0x000 0x1 0x0
+#define MX8MM_IOMUXC_I2C3_SDA_GPT3_CLK                                      0x228 0x490 0x000 0x2 0x0
+#define MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19                                    0x228 0x490 0x000 0x5 0x0
+#define MX8MM_IOMUXC_I2C3_SDA_TPSMP_HDATA21                                 0x228 0x490 0x000 0x7 0x0
+#define MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL                                      0x22C 0x494 0x000 0x0 0x0
+#define MX8MM_IOMUXC_I2C4_SCL_PWM2_OUT                                      0x22C 0x494 0x000 0x1 0x0
+#define MX8MM_IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B                                0x22C 0x494 0x524 0x12 0x0
+#define MX8MM_IOMUXC_I2C4_SCL_GPIO5_IO20                                    0x22C 0x494 0x000 0x5 0x0
+#define MX8MM_IOMUXC_I2C4_SCL_TPSMP_HDATA22                                 0x22C 0x494 0x000 0x7 0x0
+#define MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA                                      0x230 0x498 0x000 0x0 0x0
+#define MX8MM_IOMUXC_I2C4_SDA_PWM1_OUT                                      0x230 0x498 0x000 0x1 0x0
+#define MX8MM_IOMUXC_I2C4_SDA_PCIE2_CLKREQ_B                                0x230 0x498 0x528 0x2 0x0
+#define MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21                                    0x230 0x498 0x000 0x5 0x0
+#define MX8MM_IOMUXC_I2C4_SDA_TPSMP_HDATA23                                 0x230 0x498 0x000 0x7 0x0
+#define MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX                                 0x234 0x49C 0x4F4 0x0 0x0
+#define MX8MM_IOMUXC_UART1_RXD_UART1_DTE_TX                                 0x234 0x49C 0x000 0x0 0x0
+#define MX8MM_IOMUXC_UART1_RXD_ECSPI3_SCLK                                  0x234 0x49C 0x000 0x1 0x0
+#define MX8MM_IOMUXC_UART1_RXD_GPIO5_IO22                                   0x234 0x49C 0x000 0x5 0x0
+#define MX8MM_IOMUXC_UART1_RXD_TPSMP_HDATA24                                0x234 0x49C 0x000 0x7 0x0
+#define MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX                                 0x238 0x4A0 0x000 0x0 0x0
+#define MX8MM_IOMUXC_UART1_TXD_UART1_DTE_RX                                 0x238 0x4A0 0x4F4 0x0 0x0
+#define MX8MM_IOMUXC_UART1_TXD_ECSPI3_MOSI                                  0x238 0x4A0 0x000 0x1 0x0
+#define MX8MM_IOMUXC_UART1_TXD_GPIO5_IO23                                   0x238 0x4A0 0x000 0x5 0x0
+#define MX8MM_IOMUXC_UART1_TXD_TPSMP_HDATA25                                0x238 0x4A0 0x000 0x7 0x0
+#define MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX                                 0x23C 0x4A4 0x4FC 0x0 0x0
+#define MX8MM_IOMUXC_UART2_RXD_UART2_DTE_TX                                 0x23C 0x4A4 0x000 0x0 0x0
+#define MX8MM_IOMUXC_UART2_RXD_ECSPI3_MISO                                  0x23C 0x4A4 0x000 0x1 0x0
+#define MX8MM_IOMUXC_UART2_RXD_GPIO5_IO24                                   0x23C 0x4A4 0x000 0x5 0x0
+#define MX8MM_IOMUXC_UART2_RXD_TPSMP_HDATA26                                0x23C 0x4A4 0x000 0x7 0x0
+#define MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX                                 0x240 0x4A8 0x000 0x0 0x0
+#define MX8MM_IOMUXC_UART2_TXD_UART2_DTE_RX                                 0x240 0x4A8 0x4FC 0x0 0x1
+#define MX8MM_IOMUXC_UART2_TXD_ECSPI3_SS0                                   0x240 0x4A8 0x000 0x1 0x0
+#define MX8MM_IOMUXC_UART2_TXD_GPIO5_IO25                                   0x240 0x4A8 0x000 0x5 0x0
+#define MX8MM_IOMUXC_UART2_TXD_TPSMP_HDATA27                                0x240 0x4A8 0x000 0x7 0x0
+#define MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX                                 0x244 0x4AC 0x504 0x0 0x2
+#define MX8MM_IOMUXC_UART3_RXD_UART3_DTE_TX                                 0x244 0x4AC 0x000 0x0 0x0
+#define MX8MM_IOMUXC_UART3_RXD_UART1_DCE_CTS_B                              0x244 0x4AC 0x000 0x1 0x0
+#define MX8MM_IOMUXC_UART3_RXD_UART1_DTE_RTS_B                              0x244 0x4AC 0x4F0 0x1 0x0
+#define MX8MM_IOMUXC_UART3_RXD_GPIO5_IO26                                   0x244 0x4AC 0x000 0x5 0x0
+#define MX8MM_IOMUXC_UART3_RXD_TPSMP_HDATA28                                0x244 0x4AC 0x000 0x7 0x0
+#define MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX                                 0x248 0x4B0 0x000 0x0 0x0
+#define MX8MM_IOMUXC_UART3_TXD_UART3_DTE_RX                                 0x248 0x4B0 0x504 0x0 0x3
+#define MX8MM_IOMUXC_UART3_TXD_UART1_DCE_RTS_B                              0x248 0x4B0 0x4F0 0x1 0x1
+#define MX8MM_IOMUXC_UART3_TXD_UART1_DTE_CTS_B                              0x248 0x4B0 0x000 0x1 0x0
+#define MX8MM_IOMUXC_UART3_TXD_GPIO5_IO27                                   0x248 0x4B0 0x000 0x5 0x0
+#define MX8MM_IOMUXC_UART3_TXD_TPSMP_HDATA29                                0x248 0x4B0 0x000 0x7 0x0
+#define MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX                                 0x24C 0x4B4 0x50C 0x0 0x2
+#define MX8MM_IOMUXC_UART4_RXD_UART4_DTE_TX                                 0x24C 0x4B4 0x000 0x0 0x0
+#define MX8MM_IOMUXC_UART4_RXD_UART2_DCE_CTS_B                              0x24C 0x4B4 0x000 0x1 0x0
+#define MX8MM_IOMUXC_UART4_RXD_UART2_DTE_RTS_B                              0x24C 0x4B4 0x4F8 0x1 0x0
+#define MX8MM_IOMUXC_UART4_RXD_PCIE1_CLKREQ_B                               0x24C 0x4B4 0x524 0x2 0x1
+#define MX8MM_IOMUXC_UART4_RXD_GPIO5_IO28                                   0x24C 0x4B4 0x000 0x5 0x0
+#define MX8MM_IOMUXC_UART4_RXD_TPSMP_HDATA30                                0x24C 0x4B4 0x000 0x7 0x0
+#define MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX                                 0x250 0x4B8 0x000 0x0 0x0
+#define MX8MM_IOMUXC_UART4_TXD_UART4_DTE_RX                                 0x250 0x4B8 0x50C 0x0 0x3
+#define MX8MM_IOMUXC_UART4_TXD_UART2_DCE_RTS_B                              0x250 0x4B8 0x4F8 0x1 0x1
+#define MX8MM_IOMUXC_UART4_TXD_UART2_DTE_CTS_B                              0x250 0x4B8 0x000 0x1 0x0
+#define MX8MM_IOMUXC_UART4_TXD_PCIE2_CLKREQ_B                               0x250 0x4B8 0x528 0x2 0x1
+#define MX8MM_IOMUXC_UART4_TXD_GPIO5_IO29                                   0x250 0x4B8 0x000 0x5 0x0
+#define MX8MM_IOMUXC_UART4_TXD_TPSMP_HDATA31                                0x250 0x4B8 0x000 0x7 0x0
+
+#endif /* __DTS_IMX8MM_PINFUNC_H */
diff --git a/arch/arm/dts/imx8mm.dtsi b/arch/arm/dts/imx8mm.dtsi
new file mode 100644
index 0000000000..6b407a94c0
--- /dev/null
+++ b/arch/arm/dts/imx8mm.dtsi
@@ -0,0 +1,733 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2019 NXP
+ */
+
+#include <dt-bindings/clock/imx8mm-clock.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/thermal/thermal.h>
+
+#include "imx8mm-pinfunc.h"
+
+/ {
+	compatible = "fsl,imx8mm";
+	interrupt-parent = <&gic>;
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	aliases {
+		ethernet0 = &fec1;
+		i2c0 = &i2c1;
+		i2c1 = &i2c2;
+		i2c2 = &i2c3;
+		i2c3 = &i2c4;
+		serial0 = &uart1;
+		serial1 = &uart2;
+		serial2 = &uart3;
+		serial3 = &uart4;
+		spi0 = &ecspi1;
+		spi1 = &ecspi2;
+		spi2 = &ecspi3;
+		mmc0 = &usdhc1;
+		mmc1 = &usdhc2;
+		mmc2 = &usdhc3;
+		gpio0 = &gpio1;
+		gpio1 = &gpio2;
+		gpio2 = &gpio3;
+		gpio3 = &gpio4;
+		gpio4 = &gpio5;
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		A53_0: cpu at 0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a53";
+			reg = <0x0>;
+			clock-latency = <61036>; /* two CLK32 periods */
+			clocks = <&clk IMX8MM_CLK_ARM>;
+			enable-method = "psci";
+			next-level-cache = <&A53_L2>;
+			operating-points-v2 = <&a53_opp_table>;
+		};
+
+		A53_1: cpu at 1 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a53";
+			reg = <0x1>;
+			clock-latency = <61036>; /* two CLK32 periods */
+			clocks = <&clk IMX8MM_CLK_ARM>;
+			enable-method = "psci";
+			next-level-cache = <&A53_L2>;
+			operating-points-v2 = <&a53_opp_table>;
+		};
+
+		A53_2: cpu at 2 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a53";
+			reg = <0x2>;
+			clock-latency = <61036>; /* two CLK32 periods */
+			clocks = <&clk IMX8MM_CLK_ARM>;
+			enable-method = "psci";
+			next-level-cache = <&A53_L2>;
+			operating-points-v2 = <&a53_opp_table>;
+		};
+
+		A53_3: cpu at 3 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a53";
+			reg = <0x3>;
+			clock-latency = <61036>; /* two CLK32 periods */
+			clocks = <&clk IMX8MM_CLK_ARM>;
+			enable-method = "psci";
+			next-level-cache = <&A53_L2>;
+			operating-points-v2 = <&a53_opp_table>;
+		};
+
+		A53_L2: l2-cache0 {
+			compatible = "cache";
+		};
+	};
+
+	a53_opp_table: opp-table {
+		compatible = "operating-points-v2";
+		opp-shared;
+
+		opp-1200000000 {
+			opp-hz = /bits/ 64 <1200000000>;
+			opp-microvolt = <850000>;
+			clock-latency-ns = <150000>;
+		};
+
+		opp-1600000000 {
+			opp-hz = /bits/ 64 <1600000000>;
+			opp-microvolt = <900000>;
+			clock-latency-ns = <150000>;
+			opp-suspend;
+		};
+	};
+
+	memory at 40000000 {
+		device_type = "memory";
+		reg = <0x0 0x40000000 0 0x80000000>;
+	};
+
+	osc_32k: clock-osc-32k {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <32768>;
+		clock-output-names = "osc_32k";
+	};
+
+	osc_24m: clock-osc-24m {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <24000000>;
+		clock-output-names = "osc_24m";
+	};
+
+	clk_ext1: clock-ext1 {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <133000000>;
+		clock-output-names = "clk_ext1";
+	};
+
+	clk_ext2: clock-ext2 {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <133000000>;
+		clock-output-names = "clk_ext2";
+	};
+
+	clk_ext3: clock-ext3 {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <133000000>;
+		clock-output-names = "clk_ext3";
+	};
+
+	clk_ext4: clock-ext4 {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency= <133000000>;
+		clock-output-names = "clk_ext4";
+	};
+
+	gic: interrupt-controller at 38800000 {
+		compatible = "arm,gic-v3";
+		reg = <0x0 0x38800000 0 0x10000>, /* GIC Dist */
+		      <0x0 0x38880000 0 0xC0000>; /* GICR (RD_base + SGI_base) */
+		#interrupt-cells = <3>;
+		interrupt-controller;
+		interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+	};
+
+	psci {
+		compatible = "arm,psci-1.0";
+		method = "smc";
+	};
+
+	pmu {
+		compatible = "arm,armv8-pmuv3";
+		interrupts = <GIC_PPI 7
+			     (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>;
+		interrupt-affinity = <&A53_0>, <&A53_1>, <&A53_2>, <&A53_3>;
+	};
+
+	timer {
+		compatible = "arm,armv8-timer";
+		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Physical Secure */
+			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Physical Non-Secure */
+			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Virtual */
+			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>; /* Hypervisor */
+		clock-frequency = <8000000>;
+		arm,no-tick-in-suspend;
+	};
+
+	soc {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0x0 0x0 0x0 0x3e000000>;
+
+		aips1: bus at 30000000 {
+			compatible = "fsl,aips-bus", "simple-bus";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges;
+
+			gpio1: gpio at 30200000 {
+				compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio";
+				reg = <0x30200000 0x10000>;
+				interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+			};
+
+			gpio2: gpio at 30210000 {
+				compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio";
+				reg = <0x30210000 0x10000>;
+				interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+			};
+
+			gpio3: gpio at 30220000 {
+				compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio";
+				reg = <0x30220000 0x10000>;
+				interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+			};
+
+			gpio4: gpio at 30230000 {
+				compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio";
+				reg = <0x30230000 0x10000>;
+				interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+			};
+
+			gpio5: gpio at 30240000 {
+				compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio";
+				reg = <0x30240000 0x10000>;
+				interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+			};
+
+			wdog1: watchdog at 30280000 {
+				compatible = "fsl,imx8mm-wdt", "fsl,imx21-wdt";
+				reg = <0x30280000 0x10000>;
+				interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clk IMX8MM_CLK_WDOG1_ROOT>;
+				status = "disabled";
+			};
+
+			wdog2: watchdog at 30290000 {
+				compatible = "fsl,imx8mm-wdt", "fsl,imx21-wdt";
+				reg = <0x30290000 0x10000>;
+				interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clk IMX8MM_CLK_WDOG2_ROOT>;
+				status = "disabled";
+			};
+
+			wdog3: watchdog at 302a0000 {
+				compatible = "fsl,imx8mm-wdt", "fsl,imx21-wdt";
+				reg = <0x302a0000 0x10000>;
+				interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clk IMX8MM_CLK_WDOG3_ROOT>;
+				status = "disabled";
+			};
+
+			sdma2: dma-controller at 302c0000 {
+				compatible = "fsl,imx8mm-sdma", "fsl,imx7d-sdma";
+				reg = <0x302c0000 0x10000>;
+				interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clk IMX8MM_CLK_SDMA2_ROOT>,
+					 <&clk IMX8MM_CLK_SDMA2_ROOT>;
+				clock-names = "ipg", "ahb";
+				#dma-cells = <3>;
+				fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
+			};
+
+			sdma3: dma-controller at 302b0000 {
+				compatible = "fsl,imx8mm-sdma", "fsl,imx7d-sdma";
+				reg = <0x302b0000 0x10000>;
+				interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clk IMX8MM_CLK_SDMA3_ROOT>,
+				 <&clk IMX8MM_CLK_SDMA3_ROOT>;
+				clock-names = "ipg", "ahb";
+				#dma-cells = <3>;
+				fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
+			};
+
+			iomuxc: pinctrl at 30330000 {
+				compatible = "fsl,imx8mm-iomuxc";
+				reg = <0x30330000 0x10000>;
+			};
+
+			gpr: iomuxc-gpr at 30340000 {
+				compatible = "fsl,imx8mm-iomuxc-gpr", "syscon";
+				reg = <0x30340000 0x10000>;
+			};
+
+			ocotp: ocotp-ctrl at 30350000 {
+				compatible = "fsl,imx8mm-ocotp", "fsl,imx7d-ocotp", "syscon";
+				reg = <0x30350000 0x10000>;
+				clocks = <&clk IMX8MM_CLK_OCOTP_ROOT>;
+				/* For nvmem subnodes */
+				#address-cells = <1>;
+				#size-cells = <1>;
+			};
+
+			anatop: anatop at 30360000 {
+				compatible = "fsl,imx8mm-anatop", "syscon", "simple-bus";
+				reg = <0x30360000 0x10000>;
+			};
+
+			snvs: snvs at 30370000 {
+				compatible = "fsl,sec-v4.0-mon","syscon", "simple-mfd";
+				reg = <0x30370000 0x10000>;
+
+				snvs_rtc: snvs-rtc-lp {
+					compatible = "fsl,sec-v4.0-mon-rtc-lp";
+					regmap = <&snvs>;
+					offset = <0x34>;
+					interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
+						     <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
+				};
+
+				snvs_pwrkey: snvs-powerkey {
+					compatible = "fsl,sec-v4.0-pwrkey";
+					regmap = <&snvs>;
+					interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+					linux,keycode = <KEY_POWER>;
+					wakeup-source;
+				};
+			};
+
+			clk: clock-controller at 30380000 {
+				compatible = "fsl,imx8mm-ccm";
+				reg = <0x30380000 0x10000>;
+				#clock-cells = <1>;
+				clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>,
+					 <&clk_ext3>, <&clk_ext4>;
+				clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2",
+					      "clk_ext3", "clk_ext4";
+			};
+
+			src: reset-controller at 30390000 {
+				compatible = "fsl,imx8mm-src", "syscon";
+				reg = <0x30390000 0x10000>;
+				interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
+				#reset-cells = <1>;
+			};
+		};
+
+		aips2: bus at 30400000 {
+			compatible = "fsl,aips-bus", "simple-bus";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges;
+
+			pwm1: pwm at 30660000 {
+				compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm";
+				reg = <0x30660000 0x10000>;
+				interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clk IMX8MM_CLK_PWM1_ROOT>,
+					<&clk IMX8MM_CLK_PWM1_ROOT>;
+				clock-names = "ipg", "per";
+				#pwm-cells = <2>;
+				status = "disabled";
+			};
+
+			pwm2: pwm at 30670000 {
+				compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm";
+				reg = <0x30670000 0x10000>;
+				interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clk IMX8MM_CLK_PWM2_ROOT>,
+					 <&clk IMX8MM_CLK_PWM2_ROOT>;
+				clock-names = "ipg", "per";
+				#pwm-cells = <2>;
+				status = "disabled";
+			};
+
+			pwm3: pwm at 30680000 {
+				compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm";
+				reg = <0x30680000 0x10000>;
+				interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clk IMX8MM_CLK_PWM3_ROOT>,
+					 <&clk IMX8MM_CLK_PWM3_ROOT>;
+				clock-names = "ipg", "per";
+				#pwm-cells = <2>;
+				status = "disabled";
+			};
+
+			pwm4: pwm at 30690000 {
+				compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm";
+				reg = <0x30690000 0x10000>;
+				interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clk IMX8MM_CLK_PWM4_ROOT>,
+					 <&clk IMX8MM_CLK_PWM4_ROOT>;
+				clock-names = "ipg", "per";
+				#pwm-cells = <2>;
+				status = "disabled";
+			};
+		};
+
+		aips3: bus at 30800000 {
+			compatible = "fsl,aips-bus", "simple-bus";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges;
+
+			ecspi1: spi at 30820000 {
+				compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				reg = <0x30820000 0x10000>;
+				interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clk IMX8MM_CLK_ECSPI1_ROOT>,
+					 <&clk IMX8MM_CLK_ECSPI1_ROOT>;
+				clock-names = "ipg", "per";
+				dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>;
+				dma-names = "rx", "tx";
+				status = "disabled";
+			};
+
+			ecspi2: spi at 30830000 {
+				compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				reg = <0x30830000 0x10000>;
+				interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clk IMX8MM_CLK_ECSPI2_ROOT>,
+					 <&clk IMX8MM_CLK_ECSPI2_ROOT>;
+				clock-names = "ipg", "per";
+				dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>;
+				dma-names = "rx", "tx";
+				status = "disabled";
+			};
+
+			ecspi3: spi at 30840000 {
+				compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				reg = <0x30840000 0x10000>;
+				interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clk IMX8MM_CLK_ECSPI3_ROOT>,
+					 <&clk IMX8MM_CLK_ECSPI3_ROOT>;
+				clock-names = "ipg", "per";
+				dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>;
+				dma-names = "rx", "tx";
+				status = "disabled";
+			};
+
+			uart1: serial at 30860000 {
+				compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart";
+				reg = <0x30860000 0x10000>;
+				interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clk IMX8MM_CLK_UART1_ROOT>,
+					 <&clk IMX8MM_CLK_UART1_ROOT>;
+				clock-names = "ipg", "per";
+				dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>;
+				dma-names = "rx", "tx";
+				status = "disabled";
+			};
+
+			uart3: serial at 30880000 {
+				compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart";
+				reg = <0x30880000 0x10000>;
+				interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clk IMX8MM_CLK_UART3_ROOT>,
+					 <&clk IMX8MM_CLK_UART3_ROOT>;
+				clock-names = "ipg", "per";
+				dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>;
+				dma-names = "rx", "tx";
+				status = "disabled";
+			};
+
+			uart2: serial at 30890000 {
+				compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart";
+				reg = <0x30890000 0x10000>;
+				interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clk IMX8MM_CLK_UART2_ROOT>,
+					 <&clk IMX8MM_CLK_UART2_ROOT>;
+				clock-names = "ipg", "per";
+				status = "disabled";
+			};
+
+			i2c1: i2c at 30a20000 {
+				compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				reg = <0x30a20000 0x10000>;
+				interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clk IMX8MM_CLK_I2C1_ROOT>;
+				status = "disabled";
+			};
+
+			i2c2: i2c at 30a30000 {
+				compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				reg = <0x30a30000 0x10000>;
+				interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clk IMX8MM_CLK_I2C2_ROOT>;
+				status = "disabled";
+			};
+
+			i2c3: i2c at 30a40000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c";
+				reg = <0x30a40000 0x10000>;
+				interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clk IMX8MM_CLK_I2C3_ROOT>;
+				status = "disabled";
+			};
+
+			i2c4: i2c at 30a50000 {
+				compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				reg = <0x30a50000 0x10000>;
+				interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clk IMX8MM_CLK_I2C4_ROOT>;
+				status = "disabled";
+			};
+
+			uart4: serial at 30a60000 {
+				compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart";
+				reg = <0x30a60000 0x10000>;
+				interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clk IMX8MM_CLK_UART4_ROOT>,
+					 <&clk IMX8MM_CLK_UART4_ROOT>;
+				clock-names = "ipg", "per";
+				dmas = <&sdma1 28 4 0>, <&sdma1 29 4 0>;
+				dma-names = "rx", "tx";
+				status = "disabled";
+			};
+
+			usdhc1: mmc at 30b40000 {
+				compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
+				reg = <0x30b40000 0x10000>;
+				interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clk IMX8MM_CLK_DUMMY>,
+					 <&clk IMX8MM_CLK_NAND_USDHC_BUS>,
+					 <&clk IMX8MM_CLK_USDHC1_ROOT>;
+				clock-names = "ipg", "ahb", "per";
+				assigned-clocks = <&clk IMX8MM_CLK_USDHC1>;
+				assigned-clock-rates = <400000000>;
+				fsl,tuning-start-tap = <20>;
+				fsl,tuning-step= <2>;
+				bus-width = <4>;
+				status = "disabled";
+			};
+
+			usdhc2: mmc at 30b50000 {
+				compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
+				reg = <0x30b50000 0x10000>;
+				interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clk IMX8MM_CLK_DUMMY>,
+					 <&clk IMX8MM_CLK_NAND_USDHC_BUS>,
+					 <&clk IMX8MM_CLK_USDHC2_ROOT>;
+				clock-names = "ipg", "ahb", "per";
+				fsl,tuning-start-tap = <20>;
+				fsl,tuning-step= <2>;
+				bus-width = <4>;
+				status = "disabled";
+			};
+
+			usdhc3: mmc at 30b60000 {
+				compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
+				reg = <0x30b60000 0x10000>;
+				interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clk IMX8MM_CLK_DUMMY>,
+					 <&clk IMX8MM_CLK_NAND_USDHC_BUS>,
+					 <&clk IMX8MM_CLK_USDHC3_ROOT>;
+				clock-names = "ipg", "ahb", "per";
+				assigned-clocks = <&clk IMX8MM_CLK_USDHC3_ROOT>;
+				assigned-clock-rates = <400000000>;
+				fsl,tuning-start-tap = <20>;
+				fsl,tuning-step= <2>;
+				bus-width = <4>;
+				status = "disabled";
+			};
+
+			sdma1: dma-controller at 30bd0000 {
+				compatible = "fsl,imx8mm-sdma", "fsl,imx7d-sdma";
+				reg = <0x30bd0000 0x10000>;
+				interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clk IMX8MM_CLK_SDMA1_ROOT>,
+					 <&clk IMX8MM_CLK_SDMA1_ROOT>;
+				clock-names = "ipg", "ahb";
+				#dma-cells = <3>;
+				fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
+			};
+
+			fec1: ethernet at 30be0000 {
+				compatible = "fsl,imx8mm-fec", "fsl,imx6sx-fec";
+				reg = <0x30be0000 0x10000>;
+				interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clk IMX8MM_CLK_ENET1_ROOT>,
+					 <&clk IMX8MM_CLK_ENET1_ROOT>,
+					 <&clk IMX8MM_CLK_ENET_TIMER>,
+					 <&clk IMX8MM_CLK_ENET_REF>,
+					 <&clk IMX8MM_CLK_ENET_PHY_REF>;
+				clock-names = "ipg", "ahb", "ptp",
+					      "enet_clk_ref", "enet_out";
+				assigned-clocks = <&clk IMX8MM_CLK_ENET_AXI>,
+						  <&clk IMX8MM_CLK_ENET_TIMER>,
+						  <&clk IMX8MM_CLK_ENET_REF>,
+						  <&clk IMX8MM_CLK_ENET_TIMER>;
+				assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_266M>,
+							 <&clk IMX8MM_SYS_PLL2_100M>,
+							 <&clk IMX8MM_SYS_PLL2_125M>;
+				assigned-clock-rates = <0>, <0>, <125000000>, <100000000>;
+				fsl,num-tx-queues = <3>;
+				fsl,num-rx-queues = <3>;
+				status = "disabled";
+			};
+
+		};
+
+		aips4: bus at 32c00000 {
+			compatible = "fsl,aips-bus", "simple-bus";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges;
+
+			usbotg1: usb at 32e40000 {
+				compatible = "fsl,imx8mm-usb", "fsl,imx7d-usb";
+				reg = <0x32e40000 0x200>;
+				interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clk IMX8MM_CLK_USB1_CTRL_ROOT>;
+				clock-names = "usb1_ctrl_root_clk";
+				assigned-clocks = <&clk IMX8MM_CLK_USB_BUS>,
+						  <&clk IMX8MM_CLK_USB_CORE_REF>;
+				assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>,
+							 <&clk IMX8MM_SYS_PLL1_100M>;
+				fsl,usbphy = <&usbphynop1>;
+				fsl,usbmisc = <&usbmisc1 0>;
+				status = "disabled";
+			};
+
+			usbphynop1: usbphynop1 {
+				compatible = "usb-nop-xceiv";
+				clocks = <&clk IMX8MM_CLK_USB_PHY_REF>;
+				assigned-clocks = <&clk IMX8MM_CLK_USB_PHY_REF>;
+				assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_100M>;
+				clock-names = "main_clk";
+			};
+
+			usbmisc1: usbmisc at 32e40200 {
+				compatible = "fsl,imx8mm-usbmisc", "fsl,imx7d-usbmisc";
+				#index-cells = <1>;
+				reg = <0x32e40200 0x200>;
+			};
+
+			usbotg2: usb at 32e50000 {
+				compatible = "fsl,imx8mm-usb", "fsl,imx7d-usb";
+				reg = <0x32e50000 0x200>;
+				interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clk IMX8MM_CLK_USB1_CTRL_ROOT>;
+				clock-names = "usb1_ctrl_root_clk";
+				assigned-clocks = <&clk IMX8MM_CLK_USB_BUS>,
+						  <&clk IMX8MM_CLK_USB_CORE_REF>;
+				assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>,
+							 <&clk IMX8MM_SYS_PLL1_100M>;
+				fsl,usbphy = <&usbphynop2>;
+				fsl,usbmisc = <&usbmisc2 0>;
+				status = "disabled";
+			};
+
+			usbphynop2: usbphynop2 {
+				compatible = "usb-nop-xceiv";
+				clocks = <&clk IMX8MM_CLK_USB_PHY_REF>;
+				assigned-clocks = <&clk IMX8MM_CLK_USB_PHY_REF>;
+				assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_100M>;
+				clock-names = "main_clk";
+			};
+
+			usbmisc2: usbmisc at 32e50200 {
+				compatible = "fsl,imx8mm-usbmisc", "fsl,imx7d-usbmisc";
+				#index-cells = <1>;
+				reg = <0x32e50200 0x200>;
+			};
+
+		};
+
+		dma_apbh: dma-controller at 33000000 {
+			compatible = "fsl,imx7d-dma-apbh", "fsl,imx28-dma-apbh";
+			reg = <0x33000000 0x2000>;
+			interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
+			#dma-cells = <1>;
+			dma-channels = <4>;
+			clocks = <&clk IMX8MM_CLK_NAND_USDHC_BUS_RAWNAND_CLK>;
+		};
+
+		gpmi: nand-controller at 33002000{
+			compatible = "fsl,imx8mm-gpmi-nand", "fsl,imx7d-gpmi-nand";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			reg = <0x33002000 0x2000>, <0x33004000 0x4000>;
+			reg-names = "gpmi-nand", "bch";
+			interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "bch";
+			clocks = <&clk IMX8MM_CLK_NAND_ROOT>,
+				 <&clk IMX8MM_CLK_NAND_USDHC_BUS_RAWNAND_CLK>;
+			clock-names = "gpmi_io", "gpmi_bch_apb";
+			dmas = <&dma_apbh 0>;
+			dma-names = "rx-tx";
+			status = "disabled";
+		};
+	};
+};
diff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach-imx/imx8m/Kconfig
index 35c978e863..f520075875 100644
--- a/arch/arm/mach-imx/imx8m/Kconfig
+++ b/arch/arm/mach-imx/imx8m/Kconfig
@@ -24,8 +24,15 @@ config TARGET_IMX8MQ_EVK
 	select IMX8MQ
 	select IMX8M_LPDDR4
 
+config TARGET_IMX8MM_EVK
+	bool "imx8mm LPDDR4 EVK board"
+	select IMX8MM
+	select SUPPORT_SPL
+	select IMX8M_LPDDR4
+
 endchoice
 
 source "board/freescale/imx8mq_evk/Kconfig"
+source "board/freescale/imx8mm_evk/Kconfig"
 
 endif
diff --git a/board/freescale/imx8mm_evk/Kconfig b/board/freescale/imx8mm_evk/Kconfig
new file mode 100644
index 0000000000..299691a619
--- /dev/null
+++ b/board/freescale/imx8mm_evk/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_IMX8MM_EVK
+
+config SYS_BOARD
+	default "imx8mm_evk"
+
+config SYS_VENDOR
+	default "freescale"
+
+config SYS_CONFIG_NAME
+	default "imx8mm_evk"
+
+endif
diff --git a/board/freescale/imx8mm_evk/MAINTAINERS b/board/freescale/imx8mm_evk/MAINTAINERS
new file mode 100644
index 0000000000..b031bb0674
--- /dev/null
+++ b/board/freescale/imx8mm_evk/MAINTAINERS
@@ -0,0 +1,6 @@
+i.MX8MM EVK BOARD
+M:	Peng Fan <peng.fan@nxp.com>
+S:	Maintained
+F:	board/freescale/imx8mm_evk/
+F:	include/configs/imx8mm_evk.h
+F:	configs/imx8mm_evk_defconfig
diff --git a/board/freescale/imx8mm_evk/Makefile b/board/freescale/imx8mm_evk/Makefile
new file mode 100644
index 0000000000..1db7b62caf
--- /dev/null
+++ b/board/freescale/imx8mm_evk/Makefile
@@ -0,0 +1,12 @@
+#
+# Copyright 2018 NXP
+#
+# SPDX-License-Identifier:      GPL-2.0+
+#
+
+obj-y += imx8mm_evk.o
+
+ifdef CONFIG_SPL_BUILD
+obj-y += spl.o
+obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_timing.o
+endif
diff --git a/board/freescale/imx8mm_evk/imx8mm_evk.c b/board/freescale/imx8mm_evk/imx8mm_evk.c
new file mode 100644
index 0000000000..1ea7b7f1e9
--- /dev/null
+++ b/board/freescale/imx8mm_evk/imx8mm_evk.c
@@ -0,0 +1,90 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2018 NXP
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <errno.h>
+#include <asm/io.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm-generic/gpio.h>
+#include <fsl_esdhc.h>
+#include <mmc.h>
+#include <asm/arch/imx8mm_pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/mach-imx/gpio.h>
+#include <asm/arch/clock.h>
+#include <spl.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define UART_PAD_CTRL	(PAD_CTL_DSE6 | PAD_CTL_FSEL1)
+#define WDOG_PAD_CTRL	(PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
+
+static iomux_v3_cfg_t const uart_pads[] = {
+	IMX8MM_PAD_UART2_RXD_UART2_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+	IMX8MM_PAD_UART2_TXD_UART2_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const wdog_pads[] = {
+	IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B  | MUX_PAD_CTRL(WDOG_PAD_CTRL),
+};
+
+int board_early_init_f(void)
+{
+	struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
+
+	imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
+
+	set_wdog_reset(wdog);
+
+	imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
+
+	return 0;
+}
+
+#ifdef CONFIG_BOARD_POSTCLK_INIT
+int board_postclk_init(void)
+{
+	/* TODO */
+	return 0;
+}
+#endif
+
+int dram_init(void)
+{
+	/* rom_pointer[1] contains the size of TEE occupies */
+	if (rom_pointer[1])
+		gd->ram_size = PHYS_SDRAM_SIZE - rom_pointer[1];
+	else
+		gd->ram_size = PHYS_SDRAM_SIZE;
+
+	return 0;
+}
+
+#ifdef CONFIG_OF_BOARD_SETUP
+int ft_board_setup(void *blob, bd_t *bd)
+{
+	return 0;
+}
+#endif
+
+int board_init(void)
+{
+	return 0;
+}
+
+int board_mmc_get_env_dev(int devno)
+{
+	return devno - 1;
+}
+
+int board_late_init(void)
+{
+#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+	env_set("board_name", "EVK");
+	env_set("board_rev", "iMX8MM");
+#endif
+	return 0;
+}
diff --git a/board/freescale/imx8mm_evk/lpddr4_timing.c b/board/freescale/imx8mm_evk/lpddr4_timing.c
new file mode 100644
index 0000000000..4bade5bf74
--- /dev/null
+++ b/board/freescale/imx8mm_evk/lpddr4_timing.c
@@ -0,0 +1,1980 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2018 NXP
+ */
+
+#include <linux/kernel.h>
+#include <common.h>
+#include <asm/arch/ddr.h>
+#include <asm/arch/lpddr4_define.h>
+
+struct dram_cfg_param lpddr4_ddrc_cfg[] = {
+	/* Start to config, default 3200mbps */
+	{ DDRC_DBG1(0),	0x00000001 },
+	{ DDRC_PWRCTL(0), 0x00000001 },
+	{ DDRC_MSTR(0),	0xa1080020 },
+	{ DDRC_RFSHTMG(0), 0x005b00d2 },
+	{ DDRC_INIT0(0), 0xC003061B },
+	{ DDRC_INIT1(0), 0x009D0000 },
+	{ DDRC_INIT3(0), 0x00D4002D },
+	{ DDRC_INIT4(0), (LPDDR4_MR3 << 16) | 0x0000 },
+	{ DDRC_INIT6(0), 0x0066004a },
+	{ DDRC_INIT7(0), 0x0006004a },
+
+	{ DDRC_DRAMTMG0(0), 0x1A201B22 },
+	{ DDRC_DRAMTMG1(0), 0x00060633 },
+	{ DDRC_DRAMTMG3(0), 0x00C0C000 },
+	{ DDRC_DRAMTMG4(0), 0x0F04080F },
+	{ DDRC_DRAMTMG5(0), 0x02040C0C },
+	{ DDRC_DRAMTMG6(0), 0x01010007 },
+	{ DDRC_DRAMTMG7(0), 0x00000401 },
+	{ DDRC_DRAMTMG12(0), 0x00020600 },
+	{ DDRC_DRAMTMG13(0), 0x0C100002 },
+	{ DDRC_DRAMTMG14(0), 0x000000E6 },
+	{ DDRC_DRAMTMG17(0), 0x00A00050 },
+
+	{ DDRC_ZQCTL0(0), 0x03200018 },
+	{ DDRC_ZQCTL1(0), 0x028061A8 },
+	{ DDRC_ZQCTL2(0), 0x00000000 },
+
+	{ DDRC_DFITMG0(0), 0x0497820A },
+	{ DDRC_DFITMG2(0), 0x0000170A },
+	{ DDRC_DRAMTMG2(0), 0x070E171a },
+	{ DDRC_DBICTL(0), 0x00000001 },
+
+	{ DDRC_DFITMG1(0), 0x00080303 },
+	{ DDRC_DFIUPD0(0), 0xE0400018 },
+	{ DDRC_DFIUPD1(0), 0x00DF00E4 },
+	{ DDRC_DFIUPD2(0), 0x80000000 },
+	{ DDRC_DFIMISC(0), 0x00000011 },
+
+	{ DDRC_DFIPHYMSTR(0), 0x00000000 },
+	{ DDRC_RANKCTL(0), 0x00000c99 },
+
+	/* address mapping */
+	{ DDRC_ADDRMAP0(0), 0x0000001f },
+	{ DDRC_ADDRMAP1(0), 0x00080808 },
+	{ DDRC_ADDRMAP2(0), 0x00000000 },
+	{ DDRC_ADDRMAP3(0), 0x00000000 },
+	{ DDRC_ADDRMAP4(0), 0x00001f1f },
+	{ DDRC_ADDRMAP5(0), 0x07070707 },
+	{ DDRC_ADDRMAP6(0), 0x07070707 },
+	{ DDRC_ADDRMAP7(0), 0x00000f0f },
+
+	/* performance setting */
+	{ DDRC_SCHED(0), 0x29001701 },
+	{ DDRC_SCHED1(0), 0x0000002c },
+	{ DDRC_PERFHPR1(0), 0x04000030 },
+	{ DDRC_PERFLPR1(0), 0x900093e7 },
+	{ DDRC_PERFWR1(0), 0x20005574 },
+	{ DDRC_PCCFG(0), 0x00000111 },
+	{ DDRC_PCFGW_0(0), 0x000072ff },
+	{ DDRC_PCFGQOS0_0(0), 0x02100e07 },
+	{ DDRC_PCFGQOS1_0(0), 0x00620096 },
+	{ DDRC_PCFGWQOS0_0(0), 0x01100e07 },
+	{ DDRC_PCFGWQOS1_0(0), 0x00c8012c },
+
+	/* frequency P1&P2 */
+	/* Frequency 1: 400mbps */
+	{ DDRC_FREQ1_DRAMTMG0(0), 0x0d0b010c },
+	{ DDRC_FREQ1_DRAMTMG1(0), 0x00030410 },
+	{ DDRC_FREQ1_DRAMTMG2(0), 0x0203090c },
+	{ DDRC_FREQ1_DRAMTMG3(0), 0x00505006 },
+	{ DDRC_FREQ1_DRAMTMG4(0), 0x05040305 },
+	{ DDRC_FREQ1_DRAMTMG5(0), 0x0d0e0504 },
+	{ DDRC_FREQ1_DRAMTMG6(0), 0x0a060004 },
+	{ DDRC_FREQ1_DRAMTMG7(0), 0x0000090e },
+	{ DDRC_FREQ1_DRAMTMG14(0), 0x00000032 },
+	{ DDRC_FREQ1_DRAMTMG15(0), 0x00000000 },
+	{ DDRC_FREQ1_DRAMTMG17(0), 0x0036001b },
+	{ DDRC_FREQ1_DERATEINT(0), 0x7e9fbeb1 },
+	{ DDRC_FREQ1_DFITMG0(0), 0x03818200 },
+	{ DDRC_FREQ1_DFITMG2(0), 0x00000000 },
+	{ DDRC_FREQ1_RFSHTMG(0), 0x000C001c },
+	{ DDRC_FREQ1_INIT3(0), 0x00840000 },
+	{ DDRC_FREQ1_INIT4(0), 0x00310000 },
+	{ DDRC_FREQ1_INIT6(0), 0x0066004a },
+	{ DDRC_FREQ1_INIT7(0), 0x0006004a },
+
+	/* Frequency 2: 100mbps */
+	{ DDRC_FREQ2_DRAMTMG0(0), 0x0d0b010c },
+	{ DDRC_FREQ2_DRAMTMG1(0), 0x00030410 },
+	{ DDRC_FREQ2_DRAMTMG2(0), 0x0203090c },
+	{ DDRC_FREQ2_DRAMTMG3(0), 0x00505006 },
+	{ DDRC_FREQ2_DRAMTMG4(0), 0x05040305 },
+	{ DDRC_FREQ2_DRAMTMG5(0), 0x0d0e0504 },
+	{ DDRC_FREQ2_DRAMTMG6(0), 0x0a060004 },
+	{ DDRC_FREQ2_DRAMTMG7(0), 0x0000090e },
+	{ DDRC_FREQ2_DRAMTMG14(0), 0x00000032 },
+	{ DDRC_FREQ2_DRAMTMG17(0), 0x0036001b },
+	{ DDRC_FREQ2_DERATEINT(0), 0x7e9fbeb1 },
+	{ DDRC_FREQ2_DFITMG0(0), 0x03818200 },
+	{ DDRC_FREQ2_DFITMG2(0), 0x00000000 },
+	{ DDRC_FREQ2_RFSHTMG(0), 0x0003800c },
+	{ DDRC_FREQ2_RFSHTMG(0), 0x00030007 },
+	{ DDRC_FREQ2_INIT3(0), 0x00840000 },
+	{ DDRC_FREQ2_INIT4(0), 0x00310008 },
+	{ DDRC_FREQ2_INIT4(0), (LPDDR4_MR3 << 16) | 0x0000 },
+	{ DDRC_FREQ2_INIT6(0), 0x0066004a },
+	{ DDRC_FREQ2_INIT7(0), 0x0006004a },
+
+	/* boot start point */
+	{ DDRC_MSTR2(0), 0x2 }, //DDRC_MSTR2
+};
+
+/* PHY Initialize Configuration */
+struct dram_cfg_param lpddr4_ddrphy_cfg[] = {
+	{ 0x1005f, 0x1ff },
+	{ 0x1015f, 0x1ff },
+	{ 0x1105f, 0x1ff },
+	{ 0x1115f, 0x1ff },
+	{ 0x1205f, 0x1ff },
+	{ 0x1215f, 0x1ff },
+	{ 0x1305f, 0x1ff },
+	{ 0x1315f, 0x1ff },
+
+	{ 0x11005f, 0x1ff },
+	{ 0x11015f, 0x1ff },
+	{ 0x11105f, 0x1ff },
+	{ 0x11115f, 0x1ff },
+	{ 0x11205f, 0x1ff },
+	{ 0x11215f, 0x1ff },
+	{ 0x11305f, 0x1ff },
+	{ 0x11315f, 0x1ff },
+
+	{ 0x21005f, 0x1ff },
+	{ 0x21015f, 0x1ff },
+	{ 0x21105f, 0x1ff },
+	{ 0x21115f, 0x1ff },
+	{ 0x21205f, 0x1ff },
+	{ 0x21215f, 0x1ff },
+	{ 0x21305f, 0x1ff },
+	{ 0x21315f, 0x1ff },
+
+	{ 0x55, 0x1ff },
+	{ 0x1055, 0x1ff },
+	{ 0x2055, 0x1ff },
+	{ 0x3055, 0x1ff },
+	{ 0x4055, 0x1ff },
+	{ 0x5055, 0x1ff },
+	{ 0x6055, 0x1ff },
+	{ 0x7055, 0x1ff },
+	{ 0x8055, 0x1ff },
+	{ 0x9055, 0x1ff },
+
+	{ 0x200c5, 0x19 },
+	{ 0x1200c5, 0x7 },
+	{ 0x2200c5, 0x7 },
+
+	{ 0x2002e, 0x2 },
+	{ 0x12002e, 0x2 },
+	{ 0x22002e, 0x2 },
+
+	{ 0x90204, 0x0 },
+	{ 0x190204, 0x0 },
+	{ 0x290204, 0x0 },
+
+	{ 0x20024, 0xab },
+	{ 0x2003a, 0x0 },
+
+	{ 0x120024, 0xab },
+	{ 0x2003a, 0x0 },
+
+	{ 0x220024, 0xab },
+	{ 0x2003a, 0x0 },
+
+	{ 0x20056, 0x3 },
+	{ 0x120056, 0xa },
+	{ 0x220056, 0xa },
+
+	{ 0x1004d, 0xe00 },
+	{ 0x1014d, 0xe00 },
+	{ 0x1104d, 0xe00 },
+	{ 0x1114d, 0xe00 },
+	{ 0x1204d, 0xe00 },
+	{ 0x1214d, 0xe00 },
+	{ 0x1304d, 0xe00 },
+	{ 0x1314d, 0xe00 },
+
+	{ 0x11004d, 0xe00 },
+	{ 0x11014d, 0xe00 },
+	{ 0x11104d, 0xe00 },
+	{ 0x11114d, 0xe00 },
+	{ 0x11204d, 0xe00 },
+	{ 0x11214d, 0xe00 },
+	{ 0x11304d, 0xe00 },
+	{ 0x11314d, 0xe00 },
+
+	{ 0x21004d, 0xe00 },
+	{ 0x21014d, 0xe00 },
+	{ 0x21104d, 0xe00 },
+	{ 0x21114d, 0xe00 },
+	{ 0x21204d, 0xe00 },
+	{ 0x21214d, 0xe00 },
+	{ 0x21304d, 0xe00 },
+	{ 0x21314d, 0xe00 },
+
+	{ 0x10049, 0xfbe },
+	{ 0x10149, 0xfbe },
+	{ 0x11049, 0xfbe },
+	{ 0x11149, 0xfbe },
+	{ 0x12049, 0xfbe },
+	{ 0x12149, 0xfbe },
+	{ 0x13049, 0xfbe },
+	{ 0x13149, 0xfbe },
+
+	{ 0x110049, 0xfbe },
+	{ 0x110149, 0xfbe },
+	{ 0x111049, 0xfbe },
+	{ 0x111149, 0xfbe },
+	{ 0x112049, 0xfbe },
+	{ 0x112149, 0xfbe },
+	{ 0x113049, 0xfbe },
+	{ 0x113149, 0xfbe },
+
+	{ 0x210049, 0xfbe },
+	{ 0x210149, 0xfbe },
+	{ 0x211049, 0xfbe },
+	{ 0x211149, 0xfbe },
+	{ 0x212049, 0xfbe },
+	{ 0x212149, 0xfbe },
+	{ 0x213049, 0xfbe },
+	{ 0x213149, 0xfbe },
+
+	{ 0x43, 0x63 },
+	{ 0x1043, 0x63 },
+	{ 0x2043, 0x63 },
+	{ 0x3043, 0x63 },
+	{ 0x4043, 0x63 },
+	{ 0x5043, 0x63 },
+	{ 0x6043, 0x63 },
+	{ 0x7043, 0x63 },
+	{ 0x8043, 0x63 },
+	{ 0x9043, 0x63 },
+
+	{ 0x20018, 0x3 },
+	{ 0x20075, 0x4 },
+	{ 0x20050, 0x0 },
+	{ 0x20008, 0x2ee },
+	{ 0x120008, 0x64 },
+	{ 0x220008, 0x19 },
+	{ 0x20088, 0x9 },
+
+	{ 0x200b2, 0x1d4 },
+	{ 0x10043, 0x5a1 },
+	{ 0x10143, 0x5a1 },
+	{ 0x11043, 0x5a1 },
+	{ 0x11143, 0x5a1 },
+	{ 0x12043, 0x5a1 },
+	{ 0x12143, 0x5a1 },
+	{ 0x13043, 0x5a1 },
+	{ 0x13143, 0x5a1 },
+
+	{ 0x1200b2, 0xdc },
+	{ 0x110043, 0x5a1 },
+	{ 0x110143, 0x5a1 },
+	{ 0x111043, 0x5a1 },
+	{ 0x111143, 0x5a1 },
+	{ 0x112043, 0x5a1 },
+	{ 0x112143, 0x5a1 },
+	{ 0x113043, 0x5a1 },
+	{ 0x113143, 0x5a1 },
+
+	{ 0x2200b2, 0xdc },
+	{ 0x210043, 0x5a1 },
+	{ 0x210143, 0x5a1 },
+	{ 0x211043, 0x5a1 },
+	{ 0x211143, 0x5a1 },
+	{ 0x212043, 0x5a1 },
+	{ 0x212143, 0x5a1 },
+	{ 0x213043, 0x5a1 },
+	{ 0x213143, 0x5a1 },
+
+	{ 0x200fa, 0x1 },
+	{ 0x1200fa, 0x1 },
+	{ 0x2200fa, 0x1 },
+
+	{ 0x20019, 0x1 },
+	{ 0x120019, 0x1 },
+	{ 0x220019, 0x1 },
+
+	{ 0x200f0, 0x660 },
+	{ 0x200f1, 0x0 },
+	{ 0x200f2, 0x4444 },
+	{ 0x200f3, 0x8888 },
+	{ 0x200f4, 0x5665 },
+	{ 0x200f5, 0x0 },
+	{ 0x200f6, 0x0 },
+	{ 0x200f7, 0xf000 },
+
+	{ 0x20025, 0x0 },
+	{ 0x2002d, LPDDR4_PHY_DMIPinPresent },
+	{ 0x12002d, LPDDR4_PHY_DMIPinPresent },
+	{ 0x22002d, LPDDR4_PHY_DMIPinPresent },
+	{ 0x200c7, 0x21 },
+	{ 0x200ca, 0x24 },
+	{ 0x1200c7, 0x21 },
+	{ 0x1200ca, 0x24 },
+	{ 0x2200c7, 0x21 },
+	{ 0x2200ca, 0x24 },
+};
+
+/* ddr phy trained csr */
+struct dram_cfg_param lpddr4_ddrphy_trained_csr[] = {
+	{ 0x200b2, 0x0 },
+	{ 0x1200b2, 0x0 },
+	{ 0x2200b2, 0x0 },
+	{ 0x200cb, 0x0 },
+	{ 0x10043, 0x0 },
+	{ 0x110043, 0x0 },
+	{ 0x210043, 0x0 },
+	{ 0x10143, 0x0 },
+	{ 0x110143, 0x0 },
+	{ 0x210143, 0x0 },
+	{ 0x11043, 0x0 },
+	{ 0x111043, 0x0 },
+	{ 0x211043, 0x0 },
+	{ 0x11143, 0x0 },
+	{ 0x111143, 0x0 },
+	{ 0x211143, 0x0 },
+	{ 0x12043, 0x0 },
+	{ 0x112043, 0x0 },
+	{ 0x212043, 0x0 },
+	{ 0x12143, 0x0 },
+	{ 0x112143, 0x0 },
+	{ 0x212143, 0x0 },
+	{ 0x13043, 0x0 },
+	{ 0x113043, 0x0 },
+	{ 0x213043, 0x0 },
+	{ 0x13143, 0x0 },
+	{ 0x113143, 0x0 },
+	{ 0x213143, 0x0 },
+	{ 0x80, 0x0 },
+	{ 0x100080, 0x0 },
+	{ 0x200080, 0x0 },
+	{ 0x1080, 0x0 },
+	{ 0x101080, 0x0 },
+	{ 0x201080, 0x0 },
+	{ 0x2080, 0x0 },
+	{ 0x102080, 0x0 },
+	{ 0x202080, 0x0 },
+	{ 0x3080, 0x0 },
+	{ 0x103080, 0x0 },
+	{ 0x203080, 0x0 },
+	{ 0x4080, 0x0 },
+	{ 0x104080, 0x0 },
+	{ 0x204080, 0x0 },
+	{ 0x5080, 0x0 },
+	{ 0x105080, 0x0 },
+	{ 0x205080, 0x0 },
+	{ 0x6080, 0x0 },
+	{ 0x106080, 0x0 },
+	{ 0x206080, 0x0 },
+	{ 0x7080, 0x0 },
+	{ 0x107080, 0x0 },
+	{ 0x207080, 0x0 },
+	{ 0x8080, 0x0 },
+	{ 0x108080, 0x0 },
+	{ 0x208080, 0x0 },
+	{ 0x9080, 0x0 },
+	{ 0x109080, 0x0 },
+	{ 0x209080, 0x0 },
+	{ 0x10080, 0x0 },
+	{ 0x110080, 0x0 },
+	{ 0x210080, 0x0 },
+	{ 0x10180, 0x0 },
+	{ 0x110180, 0x0 },
+	{ 0x210180, 0x0 },
+	{ 0x11080, 0x0 },
+	{ 0x111080, 0x0 },
+	{ 0x211080, 0x0 },
+	{ 0x11180, 0x0 },
+	{ 0x111180, 0x0 },
+	{ 0x211180, 0x0 },
+	{ 0x12080, 0x0 },
+	{ 0x112080, 0x0 },
+	{ 0x212080, 0x0 },
+	{ 0x12180, 0x0 },
+	{ 0x112180, 0x0 },
+	{ 0x212180, 0x0 },
+	{ 0x13080, 0x0 },
+	{ 0x113080, 0x0 },
+	{ 0x213080, 0x0 },
+	{ 0x13180, 0x0 },
+	{ 0x113180, 0x0 },
+	{ 0x213180, 0x0 },
+	{ 0x10081, 0x0 },
+	{ 0x110081, 0x0 },
+	{ 0x210081, 0x0 },
+	{ 0x10181, 0x0 },
+	{ 0x110181, 0x0 },
+	{ 0x210181, 0x0 },
+	{ 0x11081, 0x0 },
+	{ 0x111081, 0x0 },
+	{ 0x211081, 0x0 },
+	{ 0x11181, 0x0 },
+	{ 0x111181, 0x0 },
+	{ 0x211181, 0x0 },
+	{ 0x12081, 0x0 },
+	{ 0x112081, 0x0 },
+	{ 0x212081, 0x0 },
+	{ 0x12181, 0x0 },
+	{ 0x112181, 0x0 },
+	{ 0x212181, 0x0 },
+	{ 0x13081, 0x0 },
+	{ 0x113081, 0x0 },
+	{ 0x213081, 0x0 },
+	{ 0x13181, 0x0 },
+	{ 0x113181, 0x0 },
+	{ 0x213181, 0x0 },
+	{ 0x100d0, 0x0 },
+	{ 0x1100d0, 0x0 },
+	{ 0x2100d0, 0x0 },
+	{ 0x101d0, 0x0 },
+	{ 0x1101d0, 0x0 },
+	{ 0x2101d0, 0x0 },
+	{ 0x110d0, 0x0 },
+	{ 0x1110d0, 0x0 },
+	{ 0x2110d0, 0x0 },
+	{ 0x111d0, 0x0 },
+	{ 0x1111d0, 0x0 },
+	{ 0x2111d0, 0x0 },
+	{ 0x120d0, 0x0 },
+	{ 0x1120d0, 0x0 },
+	{ 0x2120d0, 0x0 },
+	{ 0x121d0, 0x0 },
+	{ 0x1121d0, 0x0 },
+	{ 0x2121d0, 0x0 },
+	{ 0x130d0, 0x0 },
+	{ 0x1130d0, 0x0 },
+	{ 0x2130d0, 0x0 },
+	{ 0x131d0, 0x0 },
+	{ 0x1131d0, 0x0 },
+	{ 0x2131d0, 0x0 },
+	{ 0x100d1, 0x0 },
+	{ 0x1100d1, 0x0 },
+	{ 0x2100d1, 0x0 },
+	{ 0x101d1, 0x0 },
+	{ 0x1101d1, 0x0 },
+	{ 0x2101d1, 0x0 },
+	{ 0x110d1, 0x0 },
+	{ 0x1110d1, 0x0 },
+	{ 0x2110d1, 0x0 },
+	{ 0x111d1, 0x0 },
+	{ 0x1111d1, 0x0 },
+	{ 0x2111d1, 0x0 },
+	{ 0x120d1, 0x0 },
+	{ 0x1120d1, 0x0 },
+	{ 0x2120d1, 0x0 },
+	{ 0x121d1, 0x0 },
+	{ 0x1121d1, 0x0 },
+	{ 0x2121d1, 0x0 },
+	{ 0x130d1, 0x0 },
+	{ 0x1130d1, 0x0 },
+	{ 0x2130d1, 0x0 },
+	{ 0x131d1, 0x0 },
+	{ 0x1131d1, 0x0 },
+	{ 0x2131d1, 0x0 },
+	{ 0x10068, 0x0 },
+	{ 0x10168, 0x0 },
+	{ 0x10268, 0x0 },
+	{ 0x10368, 0x0 },
+	{ 0x10468, 0x0 },
+	{ 0x10568, 0x0 },
+	{ 0x10668, 0x0 },
+	{ 0x10768, 0x0 },
+	{ 0x10868, 0x0 },
+	{ 0x11068, 0x0 },
+	{ 0x11168, 0x0 },
+	{ 0x11268, 0x0 },
+	{ 0x11368, 0x0 },
+	{ 0x11468, 0x0 },
+	{ 0x11568, 0x0 },
+	{ 0x11668, 0x0 },
+	{ 0x11768, 0x0 },
+	{ 0x11868, 0x0 },
+	{ 0x12068, 0x0 },
+	{ 0x12168, 0x0 },
+	{ 0x12268, 0x0 },
+	{ 0x12368, 0x0 },
+	{ 0x12468, 0x0 },
+	{ 0x12568, 0x0 },
+	{ 0x12668, 0x0 },
+	{ 0x12768, 0x0 },
+	{ 0x12868, 0x0 },
+	{ 0x13068, 0x0 },
+	{ 0x13168, 0x0 },
+	{ 0x13268, 0x0 },
+	{ 0x13368, 0x0 },
+	{ 0x13468, 0x0 },
+	{ 0x13568, 0x0 },
+	{ 0x13668, 0x0 },
+	{ 0x13768, 0x0 },
+	{ 0x13868, 0x0 },
+	{ 0x10069, 0x0 },
+	{ 0x10169, 0x0 },
+	{ 0x10269, 0x0 },
+	{ 0x10369, 0x0 },
+	{ 0x10469, 0x0 },
+	{ 0x10569, 0x0 },
+	{ 0x10669, 0x0 },
+	{ 0x10769, 0x0 },
+	{ 0x10869, 0x0 },
+	{ 0x11069, 0x0 },
+	{ 0x11169, 0x0 },
+	{ 0x11269, 0x0 },
+	{ 0x11369, 0x0 },
+	{ 0x11469, 0x0 },
+	{ 0x11569, 0x0 },
+	{ 0x11669, 0x0 },
+	{ 0x11769, 0x0 },
+	{ 0x11869, 0x0 },
+	{ 0x12069, 0x0 },
+	{ 0x12169, 0x0 },
+	{ 0x12269, 0x0 },
+	{ 0x12369, 0x0 },
+	{ 0x12469, 0x0 },
+	{ 0x12569, 0x0 },
+	{ 0x12669, 0x0 },
+	{ 0x12769, 0x0 },
+	{ 0x12869, 0x0 },
+	{ 0x13069, 0x0 },
+	{ 0x13169, 0x0 },
+	{ 0x13269, 0x0 },
+	{ 0x13369, 0x0 },
+	{ 0x13469, 0x0 },
+	{ 0x13569, 0x0 },
+	{ 0x13669, 0x0 },
+	{ 0x13769, 0x0 },
+	{ 0x13869, 0x0 },
+	{ 0x1008c, 0x0 },
+	{ 0x11008c, 0x0 },
+	{ 0x21008c, 0x0 },
+	{ 0x1018c, 0x0 },
+	{ 0x11018c, 0x0 },
+	{ 0x21018c, 0x0 },
+	{ 0x1108c, 0x0 },
+	{ 0x11108c, 0x0 },
+	{ 0x21108c, 0x0 },
+	{ 0x1118c, 0x0 },
+	{ 0x11118c, 0x0 },
+	{ 0x21118c, 0x0 },
+	{ 0x1208c, 0x0 },
+	{ 0x11208c, 0x0 },
+	{ 0x21208c, 0x0 },
+	{ 0x1218c, 0x0 },
+	{ 0x11218c, 0x0 },
+	{ 0x21218c, 0x0 },
+	{ 0x1308c, 0x0 },
+	{ 0x11308c, 0x0 },
+	{ 0x21308c, 0x0 },
+	{ 0x1318c, 0x0 },
+	{ 0x11318c, 0x0 },
+	{ 0x21318c, 0x0 },
+	{ 0x1008d, 0x0 },
+	{ 0x11008d, 0x0 },
+	{ 0x21008d, 0x0 },
+	{ 0x1018d, 0x0 },
+	{ 0x11018d, 0x0 },
+	{ 0x21018d, 0x0 },
+	{ 0x1108d, 0x0 },
+	{ 0x11108d, 0x0 },
+	{ 0x21108d, 0x0 },
+	{ 0x1118d, 0x0 },
+	{ 0x11118d, 0x0 },
+	{ 0x21118d, 0x0 },
+	{ 0x1208d, 0x0 },
+	{ 0x11208d, 0x0 },
+	{ 0x21208d, 0x0 },
+	{ 0x1218d, 0x0 },
+	{ 0x11218d, 0x0 },
+	{ 0x21218d, 0x0 },
+	{ 0x1308d, 0x0 },
+	{ 0x11308d, 0x0 },
+	{ 0x21308d, 0x0 },
+	{ 0x1318d, 0x0 },
+	{ 0x11318d, 0x0 },
+	{ 0x21318d, 0x0 },
+	{ 0x100c0, 0x0 },
+	{ 0x1100c0, 0x0 },
+	{ 0x2100c0, 0x0 },
+	{ 0x101c0, 0x0 },
+	{ 0x1101c0, 0x0 },
+	{ 0x2101c0, 0x0 },
+	{ 0x102c0, 0x0 },
+	{ 0x1102c0, 0x0 },
+	{ 0x2102c0, 0x0 },
+	{ 0x103c0, 0x0 },
+	{ 0x1103c0, 0x0 },
+	{ 0x2103c0, 0x0 },
+	{ 0x104c0, 0x0 },
+	{ 0x1104c0, 0x0 },
+	{ 0x2104c0, 0x0 },
+	{ 0x105c0, 0x0 },
+	{ 0x1105c0, 0x0 },
+	{ 0x2105c0, 0x0 },
+	{ 0x106c0, 0x0 },
+	{ 0x1106c0, 0x0 },
+	{ 0x2106c0, 0x0 },
+	{ 0x107c0, 0x0 },
+	{ 0x1107c0, 0x0 },
+	{ 0x2107c0, 0x0 },
+	{ 0x108c0, 0x0 },
+	{ 0x1108c0, 0x0 },
+	{ 0x2108c0, 0x0 },
+	{ 0x110c0, 0x0 },
+	{ 0x1110c0, 0x0 },
+	{ 0x2110c0, 0x0 },
+	{ 0x111c0, 0x0 },
+	{ 0x1111c0, 0x0 },
+	{ 0x2111c0, 0x0 },
+	{ 0x112c0, 0x0 },
+	{ 0x1112c0, 0x0 },
+	{ 0x2112c0, 0x0 },
+	{ 0x113c0, 0x0 },
+	{ 0x1113c0, 0x0 },
+	{ 0x2113c0, 0x0 },
+	{ 0x114c0, 0x0 },
+	{ 0x1114c0, 0x0 },
+	{ 0x2114c0, 0x0 },
+	{ 0x115c0, 0x0 },
+	{ 0x1115c0, 0x0 },
+	{ 0x2115c0, 0x0 },
+	{ 0x116c0, 0x0 },
+	{ 0x1116c0, 0x0 },
+	{ 0x2116c0, 0x0 },
+	{ 0x117c0, 0x0 },
+	{ 0x1117c0, 0x0 },
+	{ 0x2117c0, 0x0 },
+	{ 0x118c0, 0x0 },
+	{ 0x1118c0, 0x0 },
+	{ 0x2118c0, 0x0 },
+	{ 0x120c0, 0x0 },
+	{ 0x1120c0, 0x0 },
+	{ 0x2120c0, 0x0 },
+	{ 0x121c0, 0x0 },
+	{ 0x1121c0, 0x0 },
+	{ 0x2121c0, 0x0 },
+	{ 0x122c0, 0x0 },
+	{ 0x1122c0, 0x0 },
+	{ 0x2122c0, 0x0 },
+	{ 0x123c0, 0x0 },
+	{ 0x1123c0, 0x0 },
+	{ 0x2123c0, 0x0 },
+	{ 0x124c0, 0x0 },
+	{ 0x1124c0, 0x0 },
+	{ 0x2124c0, 0x0 },
+	{ 0x125c0, 0x0 },
+	{ 0x1125c0, 0x0 },
+	{ 0x2125c0, 0x0 },
+	{ 0x126c0, 0x0 },
+	{ 0x1126c0, 0x0 },
+	{ 0x2126c0, 0x0 },
+	{ 0x127c0, 0x0 },
+	{ 0x1127c0, 0x0 },
+	{ 0x2127c0, 0x0 },
+	{ 0x128c0, 0x0 },
+	{ 0x1128c0, 0x0 },
+	{ 0x2128c0, 0x0 },
+	{ 0x130c0, 0x0 },
+	{ 0x1130c0, 0x0 },
+	{ 0x2130c0, 0x0 },
+	{ 0x131c0, 0x0 },
+	{ 0x1131c0, 0x0 },
+	{ 0x2131c0, 0x0 },
+	{ 0x132c0, 0x0 },
+	{ 0x1132c0, 0x0 },
+	{ 0x2132c0, 0x0 },
+	{ 0x133c0, 0x0 },
+	{ 0x1133c0, 0x0 },
+	{ 0x2133c0, 0x0 },
+	{ 0x134c0, 0x0 },
+	{ 0x1134c0, 0x0 },
+	{ 0x2134c0, 0x0 },
+	{ 0x135c0, 0x0 },
+	{ 0x1135c0, 0x0 },
+	{ 0x2135c0, 0x0 },
+	{ 0x136c0, 0x0 },
+	{ 0x1136c0, 0x0 },
+	{ 0x2136c0, 0x0 },
+	{ 0x137c0, 0x0 },
+	{ 0x1137c0, 0x0 },
+	{ 0x2137c0, 0x0 },
+	{ 0x138c0, 0x0 },
+	{ 0x1138c0, 0x0 },
+	{ 0x2138c0, 0x0 },
+	{ 0x100c1, 0x0 },
+	{ 0x1100c1, 0x0 },
+	{ 0x2100c1, 0x0 },
+	{ 0x101c1, 0x0 },
+	{ 0x1101c1, 0x0 },
+	{ 0x2101c1, 0x0 },
+	{ 0x102c1, 0x0 },
+	{ 0x1102c1, 0x0 },
+	{ 0x2102c1, 0x0 },
+	{ 0x103c1, 0x0 },
+	{ 0x1103c1, 0x0 },
+	{ 0x2103c1, 0x0 },
+	{ 0x104c1, 0x0 },
+	{ 0x1104c1, 0x0 },
+	{ 0x2104c1, 0x0 },
+	{ 0x105c1, 0x0 },
+	{ 0x1105c1, 0x0 },
+	{ 0x2105c1, 0x0 },
+	{ 0x106c1, 0x0 },
+	{ 0x1106c1, 0x0 },
+	{ 0x2106c1, 0x0 },
+	{ 0x107c1, 0x0 },
+	{ 0x1107c1, 0x0 },
+	{ 0x2107c1, 0x0 },
+	{ 0x108c1, 0x0 },
+	{ 0x1108c1, 0x0 },
+	{ 0x2108c1, 0x0 },
+	{ 0x110c1, 0x0 },
+	{ 0x1110c1, 0x0 },
+	{ 0x2110c1, 0x0 },
+	{ 0x111c1, 0x0 },
+	{ 0x1111c1, 0x0 },
+	{ 0x2111c1, 0x0 },
+	{ 0x112c1, 0x0 },
+	{ 0x1112c1, 0x0 },
+	{ 0x2112c1, 0x0 },
+	{ 0x113c1, 0x0 },
+	{ 0x1113c1, 0x0 },
+	{ 0x2113c1, 0x0 },
+	{ 0x114c1, 0x0 },
+	{ 0x1114c1, 0x0 },
+	{ 0x2114c1, 0x0 },
+	{ 0x115c1, 0x0 },
+	{ 0x1115c1, 0x0 },
+	{ 0x2115c1, 0x0 },
+	{ 0x116c1, 0x0 },
+	{ 0x1116c1, 0x0 },
+	{ 0x2116c1, 0x0 },
+	{ 0x117c1, 0x0 },
+	{ 0x1117c1, 0x0 },
+	{ 0x2117c1, 0x0 },
+	{ 0x118c1, 0x0 },
+	{ 0x1118c1, 0x0 },
+	{ 0x2118c1, 0x0 },
+	{ 0x120c1, 0x0 },
+	{ 0x1120c1, 0x0 },
+	{ 0x2120c1, 0x0 },
+	{ 0x121c1, 0x0 },
+	{ 0x1121c1, 0x0 },
+	{ 0x2121c1, 0x0 },
+	{ 0x122c1, 0x0 },
+	{ 0x1122c1, 0x0 },
+	{ 0x2122c1, 0x0 },
+	{ 0x123c1, 0x0 },
+	{ 0x1123c1, 0x0 },
+	{ 0x2123c1, 0x0 },
+	{ 0x124c1, 0x0 },
+	{ 0x1124c1, 0x0 },
+	{ 0x2124c1, 0x0 },
+	{ 0x125c1, 0x0 },
+	{ 0x1125c1, 0x0 },
+	{ 0x2125c1, 0x0 },
+	{ 0x126c1, 0x0 },
+	{ 0x1126c1, 0x0 },
+	{ 0x2126c1, 0x0 },
+	{ 0x127c1, 0x0 },
+	{ 0x1127c1, 0x0 },
+	{ 0x2127c1, 0x0 },
+	{ 0x128c1, 0x0 },
+	{ 0x1128c1, 0x0 },
+	{ 0x2128c1, 0x0 },
+	{ 0x130c1, 0x0 },
+	{ 0x1130c1, 0x0 },
+	{ 0x2130c1, 0x0 },
+	{ 0x131c1, 0x0 },
+	{ 0x1131c1, 0x0 },
+	{ 0x2131c1, 0x0 },
+	{ 0x132c1, 0x0 },
+	{ 0x1132c1, 0x0 },
+	{ 0x2132c1, 0x0 },
+	{ 0x133c1, 0x0 },
+	{ 0x1133c1, 0x0 },
+	{ 0x2133c1, 0x0 },
+	{ 0x134c1, 0x0 },
+	{ 0x1134c1, 0x0 },
+	{ 0x2134c1, 0x0 },
+	{ 0x135c1, 0x0 },
+	{ 0x1135c1, 0x0 },
+	{ 0x2135c1, 0x0 },
+	{ 0x136c1, 0x0 },
+	{ 0x1136c1, 0x0 },
+	{ 0x2136c1, 0x0 },
+	{ 0x137c1, 0x0 },
+	{ 0x1137c1, 0x0 },
+	{ 0x2137c1, 0x0 },
+	{ 0x138c1, 0x0 },
+	{ 0x1138c1, 0x0 },
+	{ 0x2138c1, 0x0 },
+	{ 0x10020, 0x0 },
+	{ 0x110020, 0x0 },
+	{ 0x210020, 0x0 },
+	{ 0x11020, 0x0 },
+	{ 0x111020, 0x0 },
+	{ 0x211020, 0x0 },
+	{ 0x12020, 0x0 },
+	{ 0x112020, 0x0 },
+	{ 0x212020, 0x0 },
+	{ 0x13020, 0x0 },
+	{ 0x113020, 0x0 },
+	{ 0x213020, 0x0 },
+	{ 0x20072, 0x0 },
+	{ 0x20073, 0x0 },
+	{ 0x20074, 0x0 },
+	{ 0x100aa, 0x0 },
+	{ 0x110aa, 0x0 },
+	{ 0x120aa, 0x0 },
+	{ 0x130aa, 0x0 },
+	{ 0x20010, 0x0 },
+	{ 0x120010, 0x0 },
+	{ 0x220010, 0x0 },
+	{ 0x20011, 0x0 },
+	{ 0x120011, 0x0 },
+	{ 0x220011, 0x0 },
+	{ 0x100ae, 0x0 },
+	{ 0x1100ae, 0x0 },
+	{ 0x2100ae, 0x0 },
+	{ 0x100af, 0x0 },
+	{ 0x1100af, 0x0 },
+	{ 0x2100af, 0x0 },
+	{ 0x110ae, 0x0 },
+	{ 0x1110ae, 0x0 },
+	{ 0x2110ae, 0x0 },
+	{ 0x110af, 0x0 },
+	{ 0x1110af, 0x0 },
+	{ 0x2110af, 0x0 },
+	{ 0x120ae, 0x0 },
+	{ 0x1120ae, 0x0 },
+	{ 0x2120ae, 0x0 },
+	{ 0x120af, 0x0 },
+	{ 0x1120af, 0x0 },
+	{ 0x2120af, 0x0 },
+	{ 0x130ae, 0x0 },
+	{ 0x1130ae, 0x0 },
+	{ 0x2130ae, 0x0 },
+	{ 0x130af, 0x0 },
+	{ 0x1130af, 0x0 },
+	{ 0x2130af, 0x0 },
+	{ 0x20020, 0x0 },
+	{ 0x120020, 0x0 },
+	{ 0x220020, 0x0 },
+	{ 0x100a0, 0x0 },
+	{ 0x100a1, 0x0 },
+	{ 0x100a2, 0x0 },
+	{ 0x100a3, 0x0 },
+	{ 0x100a4, 0x0 },
+	{ 0x100a5, 0x0 },
+	{ 0x100a6, 0x0 },
+	{ 0x100a7, 0x0 },
+	{ 0x110a0, 0x0 },
+	{ 0x110a1, 0x0 },
+	{ 0x110a2, 0x0 },
+	{ 0x110a3, 0x0 },
+	{ 0x110a4, 0x0 },
+	{ 0x110a5, 0x0 },
+	{ 0x110a6, 0x0 },
+	{ 0x110a7, 0x0 },
+	{ 0x120a0, 0x0 },
+	{ 0x120a1, 0x0 },
+	{ 0x120a2, 0x0 },
+	{ 0x120a3, 0x0 },
+	{ 0x120a4, 0x0 },
+	{ 0x120a5, 0x0 },
+	{ 0x120a6, 0x0 },
+	{ 0x120a7, 0x0 },
+	{ 0x130a0, 0x0 },
+	{ 0x130a1, 0x0 },
+	{ 0x130a2, 0x0 },
+	{ 0x130a3, 0x0 },
+	{ 0x130a4, 0x0 },
+	{ 0x130a5, 0x0 },
+	{ 0x130a6, 0x0 },
+	{ 0x130a7, 0x0 },
+	{ 0x2007c, 0x0 },
+	{ 0x12007c, 0x0 },
+	{ 0x22007c, 0x0 },
+	{ 0x2007d, 0x0 },
+	{ 0x12007d, 0x0 },
+	{ 0x22007d, 0x0 },
+	{ 0x400fd, 0x0 },
+	{ 0x400c0, 0x0 },
+	{ 0x90201, 0x0 },
+	{ 0x190201, 0x0 },
+	{ 0x290201, 0x0 },
+	{ 0x90202, 0x0 },
+	{ 0x190202, 0x0 },
+	{ 0x290202, 0x0 },
+	{ 0x90203, 0x0 },
+	{ 0x190203, 0x0 },
+	{ 0x290203, 0x0 },
+	{ 0x90204, 0x0 },
+	{ 0x190204, 0x0 },
+	{ 0x290204, 0x0 },
+	{ 0x90205, 0x0 },
+	{ 0x190205, 0x0 },
+	{ 0x290205, 0x0 },
+	{ 0x90206, 0x0 },
+	{ 0x190206, 0x0 },
+	{ 0x290206, 0x0 },
+	{ 0x90207, 0x0 },
+	{ 0x190207, 0x0 },
+	{ 0x290207, 0x0 },
+	{ 0x90208, 0x0 },
+	{ 0x190208, 0x0 },
+	{ 0x290208, 0x0 },
+	{ 0x10062, 0x0 },
+	{ 0x10162, 0x0 },
+	{ 0x10262, 0x0 },
+	{ 0x10362, 0x0 },
+	{ 0x10462, 0x0 },
+	{ 0x10562, 0x0 },
+	{ 0x10662, 0x0 },
+	{ 0x10762, 0x0 },
+	{ 0x10862, 0x0 },
+	{ 0x11062, 0x0 },
+	{ 0x11162, 0x0 },
+	{ 0x11262, 0x0 },
+	{ 0x11362, 0x0 },
+	{ 0x11462, 0x0 },
+	{ 0x11562, 0x0 },
+	{ 0x11662, 0x0 },
+	{ 0x11762, 0x0 },
+	{ 0x11862, 0x0 },
+	{ 0x12062, 0x0 },
+	{ 0x12162, 0x0 },
+	{ 0x12262, 0x0 },
+	{ 0x12362, 0x0 },
+	{ 0x12462, 0x0 },
+	{ 0x12562, 0x0 },
+	{ 0x12662, 0x0 },
+	{ 0x12762, 0x0 },
+	{ 0x12862, 0x0 },
+	{ 0x13062, 0x0 },
+	{ 0x13162, 0x0 },
+	{ 0x13262, 0x0 },
+	{ 0x13362, 0x0 },
+	{ 0x13462, 0x0 },
+	{ 0x13562, 0x0 },
+	{ 0x13662, 0x0 },
+	{ 0x13762, 0x0 },
+	{ 0x13862, 0x0 },
+	{ 0x20077, 0x0 },
+	{ 0x10001, 0x0 },
+	{ 0x11001, 0x0 },
+	{ 0x12001, 0x0 },
+	{ 0x13001, 0x0 },
+	{ 0x10040, 0x0 },
+	{ 0x10140, 0x0 },
+	{ 0x10240, 0x0 },
+	{ 0x10340, 0x0 },
+	{ 0x10440, 0x0 },
+	{ 0x10540, 0x0 },
+	{ 0x10640, 0x0 },
+	{ 0x10740, 0x0 },
+	{ 0x10840, 0x0 },
+	{ 0x10030, 0x0 },
+	{ 0x10130, 0x0 },
+	{ 0x10230, 0x0 },
+	{ 0x10330, 0x0 },
+	{ 0x10430, 0x0 },
+	{ 0x10530, 0x0 },
+	{ 0x10630, 0x0 },
+	{ 0x10730, 0x0 },
+	{ 0x10830, 0x0 },
+	{ 0x11040, 0x0 },
+	{ 0x11140, 0x0 },
+	{ 0x11240, 0x0 },
+	{ 0x11340, 0x0 },
+	{ 0x11440, 0x0 },
+	{ 0x11540, 0x0 },
+	{ 0x11640, 0x0 },
+	{ 0x11740, 0x0 },
+	{ 0x11840, 0x0 },
+	{ 0x11030, 0x0 },
+	{ 0x11130, 0x0 },
+	{ 0x11230, 0x0 },
+	{ 0x11330, 0x0 },
+	{ 0x11430, 0x0 },
+	{ 0x11530, 0x0 },
+	{ 0x11630, 0x0 },
+	{ 0x11730, 0x0 },
+	{ 0x11830, 0x0 },
+	{ 0x12040, 0x0 },
+	{ 0x12140, 0x0 },
+	{ 0x12240, 0x0 },
+	{ 0x12340, 0x0 },
+	{ 0x12440, 0x0 },
+	{ 0x12540, 0x0 },
+	{ 0x12640, 0x0 },
+	{ 0x12740, 0x0 },
+	{ 0x12840, 0x0 },
+	{ 0x12030, 0x0 },
+	{ 0x12130, 0x0 },
+	{ 0x12230, 0x0 },
+	{ 0x12330, 0x0 },
+	{ 0x12430, 0x0 },
+	{ 0x12530, 0x0 },
+	{ 0x12630, 0x0 },
+	{ 0x12730, 0x0 },
+	{ 0x12830, 0x0 },
+	{ 0x13040, 0x0 },
+	{ 0x13140, 0x0 },
+	{ 0x13240, 0x0 },
+	{ 0x13340, 0x0 },
+	{ 0x13440, 0x0 },
+	{ 0x13540, 0x0 },
+	{ 0x13640, 0x0 },
+	{ 0x13740, 0x0 },
+	{ 0x13840, 0x0 },
+	{ 0x13030, 0x0 },
+	{ 0x13130, 0x0 },
+	{ 0x13230, 0x0 },
+	{ 0x13330, 0x0 },
+	{ 0x13430, 0x0 },
+	{ 0x13530, 0x0 },
+	{ 0x13630, 0x0 },
+	{ 0x13730, 0x0 },
+	{ 0x13830, 0x0 },
+};
+
+/* P0 message block paremeter for training firmware */
+struct dram_cfg_param lpddr4_fsp0_cfg[] = {
+	{ 0xd0000, 0x0 },
+	{ 0x54000, 0x0 },
+	{ 0x54001, 0x0 },
+	{ 0x54002, 0x0 },
+	{ 0x54003, 0xbb8 },
+	{ 0x54004, 0x2 },
+	{ 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT) },//PHY Ron/Rtt
+	{ 0x54006, LPDDR4_PHY_VREF_VALUE },
+	{ 0x54007, 0x0 },
+	{ 0x54008, 0x131f },
+	{ 0x54009, 0xc8 },
+	{ 0x5400a, 0x0 },
+	{ 0x5400b, 0x2 },
+	{ 0x5400c, 0x0 },
+	{ 0x5400d, 0x0 },
+	{ 0x5400e, 0x0 },
+	{ 0x5400f, 0x0 },
+	{ 0x54010, 0x0 },
+	{ 0x54011, 0x0 },
+	{ 0x54012, (LPDDR4_CS << 8) | (0x110 & 0xff) },
+	{ 0x54013, 0x0 },
+	{ 0x54014, 0x0 },
+	{ 0x54015, 0x0 },
+	{ 0x54016, 0x0 },
+	{ 0x54017, 0x0 },
+	{ 0x54018, 0x0 },
+	{ 0x54019, 0x2dd4 },
+	{ 0x5401a, (0x31 & 0xff00) | LPDDR4_MR3 },
+	{ 0x5401b, 0x4d66 },
+	{ 0x5401c, 0x4d08 },
+	{ 0x5401d, 0x0 },
+	{ 0x5401e, LPDDR4_MR22_RANK0/*0x16*/ },
+	{ 0x5401f, 0x2dd4 },
+	{ 0x54020, (0x31 & 0xff00) | LPDDR4_MR3 },
+	{ 0x54021, 0x4d66 },
+	{ 0x54022, 0x4d08 },
+	{ 0x54023, 0x0 },
+	{ 0x54024, LPDDR4_MR22_RANK1/*0x16*/ },
+	{ 0x54025, 0x0 },
+	{ 0x54026, 0x0 },
+	{ 0x54027, 0x0 },
+	{ 0x54028, 0x0 },
+	{ 0x54029, 0x0 },
+	{ 0x5402a, 0x0 },
+	{ 0x5402b, 0x1000 },
+	{ 0x5402c, LPDDR4_CS },
+	{ 0x5402d, 0x0 },
+	{ 0x5402e, 0x0 },
+	{ 0x5402f, 0x0 },
+	{ 0x54030, 0x0 },
+	{ 0x54031, 0x0 },
+	{ 0x54032, 0xd400 },
+	{ 0x54033, (LPDDR4_MR3 << 8) | (0x312d & 0xff) },
+	{ 0x54034, 0x6600 },
+	{ 0x54035, 0x84d },
+	{ 0x54036, 0x4d },
+	{ 0x54037, (LPDDR4_MR22_RANK0 << 8)/*0x1600*/ },
+	{ 0x54038, 0xd400 },
+	{ 0x54039, (LPDDR4_MR3 << 8) | (0x312d & 0xff) },
+	{ 0x5403a, 0x6600 },
+	{ 0x5403b, 0x84d },
+	{ 0x5403c, 0x4d },
+	{ 0x5403d, (LPDDR4_MR22_RANK1 << 8)/*0x1600*/ },
+	{ 0x5403e, 0x0 },
+	{ 0x5403f, 0x0 },
+	{ 0x54040, 0x0 },
+	{ 0x54041, 0x0 },
+	{ 0x54042, 0x0 },
+	{ 0x54043, 0x0 },
+	{ 0x54044, 0x0 },
+	{ 0xd0000, 0x1 },
+};
+
+/* P1 message block paremeter for training firmware */
+struct dram_cfg_param lpddr4_fsp1_cfg[] = {
+	{ 0xd0000, 0x0 },
+	{ 0x54000, 0x0 },
+	{ 0x54001, 0x0 },
+	{ 0x54002, 0x101 },
+	{ 0x54003, 0x190 },
+	{ 0x54004, 0x2 },
+	{ 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT) },//PHY Ron/Rtt
+	{ 0x54006, LPDDR4_PHY_VREF_VALUE },
+	{ 0x54007, 0x0 },
+	{ 0x54008, 0x121f },
+	{ 0x54009, 0xc8 },
+	{ 0x5400a, 0x0 },
+	{ 0x5400b, 0x2 },
+	{ 0x5400c, 0x0 },
+	{ 0x5400d, 0x0 },
+	{ 0x5400e, 0x0 },
+	{ 0x5400f, 0x0 },
+	{ 0x54010, 0x0 },
+	{ 0x54011, 0x0 },
+	{ 0x54012, (LPDDR4_CS << 8) | (0x110 & 0xff) },
+	{ 0x54013, 0x0 },
+	{ 0x54014, 0x0 },
+	{ 0x54015, 0x0 },
+	{ 0x54016, 0x0 },
+	{ 0x54017, 0x0 },
+	{ 0x54018, 0x0 },
+	{ 0x54019, 0x84 },
+	{ 0x5401a, (0x31 & 0xff00) | LPDDR4_MR3 },
+	{ 0x5401b, 0x4d66 },
+	{ 0x5401c, 0x4d08 },
+	{ 0x5401d, 0x0 },
+	{ 0x5401e, LPDDR4_MR22_RANK0/*0x16*/ },
+	{ 0x5401f, 0x84 },
+	{ 0x54020, (0x31 & 0xff00) | LPDDR4_MR3 },
+	{ 0x54021, 0x4d66 },
+	{ 0x54022, 0x4d08 },
+	{ 0x54023, 0x0 },
+	{ 0x54024, LPDDR4_MR22_RANK1/*0x16*/ },
+	{ 0x54025, 0x0 },
+	{ 0x54026, 0x0 },
+	{ 0x54027, 0x0 },
+	{ 0x54028, 0x0 },
+	{ 0x54029, 0x0 },
+	{ 0x5402a, 0x0 },
+	{ 0x5402b, 0x1000 },
+	{ 0x5402c, LPDDR4_CS },
+	{ 0x5402d, 0x0 },
+	{ 0x5402e, 0x0 },
+	{ 0x5402f, 0x0 },
+	{ 0x54030, 0x0 },
+	{ 0x54031, 0x0 },
+	{ 0x54032, 0x8400 },
+	{ 0x54033, (LPDDR4_MR3 << 8) | (0x3100 & 0xff) },
+	{ 0x54034, 0x6600 },
+	{ 0x54035, 0x84d },
+	{ 0x54036, 0x4d },
+	{ 0x54037, (LPDDR4_MR22_RANK0 << 8)/*0x1600*/ },
+	{ 0x54038, 0x8400 },
+	{ 0x54039, (LPDDR4_MR3 << 8) | (0x3100 & 0xff) },
+	{ 0x5403a, 0x6600 },
+	{ 0x5403b, 0x84d },
+	{ 0x5403c, 0x4d },
+	{ 0x5403d, (LPDDR4_MR22_RANK1 << 8)/*0x1600*/ },
+	{ 0x5403e, 0x0 },
+	{ 0x5403f, 0x0 },
+	{ 0x54040, 0x0 },
+	{ 0x54041, 0x0 },
+	{ 0x54042, 0x0 },
+	{ 0x54043, 0x0 },
+	{ 0x54044, 0x0 },
+	{ 0xd0000, 0x1 },
+};
+
+/* P1 message block paremeter for training firmware */
+struct dram_cfg_param lpddr4_fsp2_cfg[] = {
+	{ 0xd0000, 0x0 },
+	{ 0x54000, 0x0 },
+	{ 0x54001, 0x0 },
+	{ 0x54002, 0x102 },
+	{ 0x54003, 0x64 },
+	{ 0x54004, 0x2 },
+	{ 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT) },//PHY Ron/Rtt
+	{ 0x54006, LPDDR4_PHY_VREF_VALUE },
+	{ 0x54007, 0x0 },
+	{ 0x54008, 0x121f },
+	{ 0x54009, 0xc8 },
+	{ 0x5400a, 0x0 },
+	{ 0x5400b, 0x2 },
+	{ 0x5400c, 0x0 },
+	{ 0x5400d, 0x0 },
+	{ 0x5400e, 0x0 },
+	{ 0x5400f, 0x0 },
+	{ 0x54010, 0x0 },
+	{ 0x54011, 0x0 },
+	{ 0x54012, (LPDDR4_CS << 8) | (0x110 & 0xff) },
+	{ 0x54013, 0x0 },
+	{ 0x54014, 0x0 },
+	{ 0x54015, 0x0 },
+	{ 0x54016, 0x0 },
+	{ 0x54017, 0x0 },
+	{ 0x54018, 0x0 },
+	{ 0x54019, 0x84 },
+	{ 0x5401a, (0x31 & 0xff00) | LPDDR4_MR3 },
+	{ 0x5401b, 0x4d66 },
+	{ 0x5401c, 0x4d08 },
+	{ 0x5401d, 0x0 },
+	{ 0x5401e, LPDDR4_MR22_RANK0/*0x16*/ },
+	{ 0x5401f, 0x84 },
+	{ 0x54020, (0x31 & 0xff00) | LPDDR4_MR3 },
+	{ 0x54021, 0x4d66 },
+	{ 0x54022, 0x4d08 },
+	{ 0x54023, 0x0 },
+	{ 0x54024, LPDDR4_MR22_RANK1/*0x16*/ },
+	{ 0x54025, 0x0 },
+	{ 0x54026, 0x0 },
+	{ 0x54027, 0x0 },
+	{ 0x54028, 0x0 },
+	{ 0x54029, 0x0 },
+	{ 0x5402a, 0x0 },
+	{ 0x5402b, 0x1000 },
+	{ 0x5402c, LPDDR4_CS },
+	{ 0x5402d, 0x0 },
+	{ 0x5402e, 0x0 },
+	{ 0x5402f, 0x0 },
+	{ 0x54030, 0x0 },
+	{ 0x54031, 0x0 },
+	{ 0x54032, 0x8400 },
+	{ 0x54033, (LPDDR4_MR3 << 8) | (0x3100 & 0xff) },
+	{ 0x54034, 0x6600 },
+	{ 0x54035, 0x84d },
+	{ 0x54036, 0x4d },
+	{ 0x54037, (LPDDR4_MR22_RANK0 << 8)/*0x1600*/ },
+	{ 0x54038, 0x8400 },
+	{ 0x54039, (LPDDR4_MR3 << 8) | (0x3100 & 0xff) },
+	{ 0x5403a, 0x6600 },
+	{ 0x5403b, 0x84d },
+	{ 0x5403c, 0x4d },
+	{ 0x5403d, (LPDDR4_MR22_RANK1 << 8)/*0x1600*/ },
+	{ 0x5403e, 0x0 },
+	{ 0x5403f, 0x0 },
+	{ 0x54040, 0x0 },
+	{ 0x54041, 0x0 },
+	{ 0x54042, 0x0 },
+	{ 0x54043, 0x0 },
+	{ 0x54044, 0x0 },
+	{ 0xd0000, 0x1 },
+};
+
+/* P0 2D message block paremeter for training firmware */
+struct dram_cfg_param lpddr4_fsp0_2d_cfg[] = {
+	{ 0xd0000, 0x0 },
+	{ 0x54000, 0x0 },
+	{ 0x54001, 0x0 },
+	{ 0x54002, 0x0 },
+	{ 0x54003, 0xbb8 },
+	{ 0x54004, 0x2 },
+	{ 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT) },//PHY Ron/Rtt
+	{ 0x54006, LPDDR4_PHY_VREF_VALUE },
+	{ 0x54007, 0x0 },
+	{ 0x54008, 0x61 },
+	{ 0x54009, 0xc8 },
+	{ 0x5400a, 0x0 },
+	{ 0x5400b, 0x2 },
+	{ 0x5400c, 0x0 },
+	{ 0x5400d, 0x0 },
+	{ 0x5400e, 0x0 },
+	{ 0x5400f, 0x100 },
+	{ 0x54010, 0x1f7f },
+	{ 0x54011, 0x0 },
+	{ 0x54012, (LPDDR4_CS << 8) | (0x110 & 0xff) },
+	{ 0x54013, 0x0 },
+	{ 0x54014, 0x0 },
+	{ 0x54015, 0x0 },
+	{ 0x54016, 0x0 },
+	{ 0x54017, 0x0 },
+	{ 0x54018, 0x0 },
+	{ 0x54019, 0x2dd4 },
+	{ 0x5401a, (0x31 & 0xff00) | LPDDR4_MR3 },
+	{ 0x5401b, 0x4d66 },
+	{ 0x5401c, 0x4d08 },
+	{ 0x5401d, 0x0 },
+	{ 0x5401e, LPDDR4_MR22_RANK0/*0x16*/ },
+	{ 0x5401f, 0x2dd4 },
+	{ 0x54020, (0x31 & 0xff00) | LPDDR4_MR3 },
+	{ 0x54021, 0x4d66 },
+	{ 0x54022, 0x4d08 },
+	{ 0x54023, 0x0 },
+	{ 0x54024, LPDDR4_MR22_RANK1/*0x16*/ },
+	{ 0x54025, 0x0 },
+	{ 0x54026, 0x0 },
+	{ 0x54027, 0x0 },
+	{ 0x54028, 0x0 },
+	{ 0x54029, 0x0 },
+	{ 0x5402a, 0x0 },
+	{ 0x5402b, 0x1000 },
+	{ 0x5402c, LPDDR4_CS },
+	{ 0x5402d, 0x0 },
+	{ 0x5402e, 0x0 },
+	{ 0x5402f, 0x0 },
+	{ 0x54030, 0x0 },
+	{ 0x54031, 0x0 },
+	{ 0x54032, 0xd400 },
+	{ 0x54033, (LPDDR4_MR3 << 8) | (0x312d & 0xff) },
+	{ 0x54034, 0x6600 },
+	{ 0x54035, 0x84d },
+	{ 0x54036, 0x4d },
+	{ 0x54037, (LPDDR4_MR22_RANK0 << 8)/*0x1600*/ },
+	{ 0x54038, 0xd400 },
+	{ 0x54039, (LPDDR4_MR3 << 8) | (0x312d & 0xff) },
+	{ 0x5403a, 0x6600 },
+	{ 0x5403b, 0x84d },
+	{ 0x5403c, 0x4d },
+	{ 0x5403d, (LPDDR4_MR22_RANK1 << 8)/*0x1600*/ },
+	{ 0x5403e, 0x0 },
+	{ 0x5403f, 0x0 },
+	{ 0x54040, 0x0 },
+	{ 0x54041, 0x0 },
+	{ 0x54042, 0x0 },
+	{ 0x54043, 0x0 },
+	{ 0x54044, 0x0 },
+	{ 0xd0000, 0x1 },
+};
+
+/* DRAM PHY init engine image */
+struct dram_cfg_param lpddr4_phy_pie[] = {
+	{ 0xd0000, 0x0 },
+	{ 0x90000, 0x10 },
+	{ 0x90001, 0x400 },
+	{ 0x90002, 0x10e },
+	{ 0x90003, 0x0 },
+	{ 0x90004, 0x0 },
+	{ 0x90005, 0x8 },
+	{ 0x90029, 0xb },
+	{ 0x9002a, 0x480 },
+	{ 0x9002b, 0x109 },
+	{ 0x9002c, 0x8 },
+	{ 0x9002d, 0x448 },
+	{ 0x9002e, 0x139 },
+	{ 0x9002f, 0x8 },
+	{ 0x90030, 0x478 },
+	{ 0x90031, 0x109 },
+	{ 0x90032, 0x0 },
+	{ 0x90033, 0xe8 },
+	{ 0x90034, 0x109 },
+	{ 0x90035, 0x2 },
+	{ 0x90036, 0x10 },
+	{ 0x90037, 0x139 },
+	{ 0x90038, 0xf },
+	{ 0x90039, 0x7c0 },
+	{ 0x9003a, 0x139 },
+	{ 0x9003b, 0x44 },
+	{ 0x9003c, 0x630 },
+	{ 0x9003d, 0x159 },
+	{ 0x9003e, 0x14f },
+	{ 0x9003f, 0x630 },
+	{ 0x90040, 0x159 },
+	{ 0x90041, 0x47 },
+	{ 0x90042, 0x630 },
+	{ 0x90043, 0x149 },
+	{ 0x90044, 0x4f },
+	{ 0x90045, 0x630 },
+	{ 0x90046, 0x179 },
+	{ 0x90047, 0x8 },
+	{ 0x90048, 0xe0 },
+	{ 0x90049, 0x109 },
+	{ 0x9004a, 0x0 },
+	{ 0x9004b, 0x7c8 },
+	{ 0x9004c, 0x109 },
+	{ 0x9004d, 0x0 },
+	{ 0x9004e, 0x1 },
+	{ 0x9004f, 0x8 },
+	{ 0x90050, 0x0 },
+	{ 0x90051, 0x45a },
+	{ 0x90052, 0x9 },
+	{ 0x90053, 0x0 },
+	{ 0x90054, 0x448 },
+	{ 0x90055, 0x109 },
+	{ 0x90056, 0x40 },
+	{ 0x90057, 0x630 },
+	{ 0x90058, 0x179 },
+	{ 0x90059, 0x1 },
+	{ 0x9005a, 0x618 },
+	{ 0x9005b, 0x109 },
+	{ 0x9005c, 0x40c0 },
+	{ 0x9005d, 0x630 },
+	{ 0x9005e, 0x149 },
+	{ 0x9005f, 0x8 },
+	{ 0x90060, 0x4 },
+	{ 0x90061, 0x48 },
+	{ 0x90062, 0x4040 },
+	{ 0x90063, 0x630 },
+	{ 0x90064, 0x149 },
+	{ 0x90065, 0x0 },
+	{ 0x90066, 0x4 },
+	{ 0x90067, 0x48 },
+	{ 0x90068, 0x40 },
+	{ 0x90069, 0x630 },
+	{ 0x9006a, 0x149 },
+	{ 0x9006b, 0x10 },
+	{ 0x9006c, 0x4 },
+	{ 0x9006d, 0x18 },
+	{ 0x9006e, 0x0 },
+	{ 0x9006f, 0x4 },
+	{ 0x90070, 0x78 },
+	{ 0x90071, 0x549 },
+	{ 0x90072, 0x630 },
+	{ 0x90073, 0x159 },
+	{ 0x90074, 0xd49 },
+	{ 0x90075, 0x630 },
+	{ 0x90076, 0x159 },
+	{ 0x90077, 0x94a },
+	{ 0x90078, 0x630 },
+	{ 0x90079, 0x159 },
+	{ 0x9007a, 0x441 },
+	{ 0x9007b, 0x630 },
+	{ 0x9007c, 0x149 },
+	{ 0x9007d, 0x42 },
+	{ 0x9007e, 0x630 },
+	{ 0x9007f, 0x149 },
+	{ 0x90080, 0x1 },
+	{ 0x90081, 0x630 },
+	{ 0x90082, 0x149 },
+	{ 0x90083, 0x0 },
+	{ 0x90084, 0xe0 },
+	{ 0x90085, 0x109 },
+	{ 0x90086, 0xa },
+	{ 0x90087, 0x10 },
+	{ 0x90088, 0x109 },
+	{ 0x90089, 0x9 },
+	{ 0x9008a, 0x3c0 },
+	{ 0x9008b, 0x149 },
+	{ 0x9008c, 0x9 },
+	{ 0x9008d, 0x3c0 },
+	{ 0x9008e, 0x159 },
+	{ 0x9008f, 0x18 },
+	{ 0x90090, 0x10 },
+	{ 0x90091, 0x109 },
+	{ 0x90092, 0x0 },
+	{ 0x90093, 0x3c0 },
+	{ 0x90094, 0x109 },
+	{ 0x90095, 0x18 },
+	{ 0x90096, 0x4 },
+	{ 0x90097, 0x48 },
+	{ 0x90098, 0x18 },
+	{ 0x90099, 0x4 },
+	{ 0x9009a, 0x58 },
+	{ 0x9009b, 0xa },
+	{ 0x9009c, 0x10 },
+	{ 0x9009d, 0x109 },
+	{ 0x9009e, 0x2 },
+	{ 0x9009f, 0x10 },
+	{ 0x900a0, 0x109 },
+	{ 0x900a1, 0x5 },
+	{ 0x900a2, 0x7c0 },
+	{ 0x900a3, 0x109 },
+	{ 0x900a4, 0x10 },
+	{ 0x900a5, 0x10 },
+	{ 0x900a6, 0x109 },
+	{ 0x40000, 0x811 },
+	{ 0x40020, 0x880 },
+	{ 0x40040, 0x0 },
+	{ 0x40060, 0x0 },
+	{ 0x40001, 0x4008 },
+	{ 0x40021, 0x83 },
+	{ 0x40041, 0x4f },
+	{ 0x40061, 0x0 },
+	{ 0x40002, 0x4040 },
+	{ 0x40022, 0x83 },
+	{ 0x40042, 0x51 },
+	{ 0x40062, 0x0 },
+	{ 0x40003, 0x811 },
+	{ 0x40023, 0x880 },
+	{ 0x40043, 0x0 },
+	{ 0x40063, 0x0 },
+	{ 0x40004, 0x720 },
+	{ 0x40024, 0xf },
+	{ 0x40044, 0x1740 },
+	{ 0x40064, 0x0 },
+	{ 0x40005, 0x16 },
+	{ 0x40025, 0x83 },
+	{ 0x40045, 0x4b },
+	{ 0x40065, 0x0 },
+	{ 0x40006, 0x716 },
+	{ 0x40026, 0xf },
+	{ 0x40046, 0x2001 },
+	{ 0x40066, 0x0 },
+	{ 0x40007, 0x716 },
+	{ 0x40027, 0xf },
+	{ 0x40047, 0x2800 },
+	{ 0x40067, 0x0 },
+	{ 0x40008, 0x716 },
+	{ 0x40028, 0xf },
+	{ 0x40048, 0xf00 },
+	{ 0x40068, 0x0 },
+	{ 0x40009, 0x720 },
+	{ 0x40029, 0xf },
+	{ 0x40049, 0x1400 },
+	{ 0x40069, 0x0 },
+	{ 0x4000a, 0xe08 },
+	{ 0x4002a, 0xc15 },
+	{ 0x4004a, 0x0 },
+	{ 0x4006a, 0x0 },
+	{ 0x4000b, 0x623 },
+	{ 0x4002b, 0x15 },
+	{ 0x4004b, 0x0 },
+	{ 0x4006b, 0x0 },
+	{ 0x4000c, 0x4028 },
+	{ 0x4002c, 0x80 },
+	{ 0x4004c, 0x0 },
+	{ 0x4006c, 0x0 },
+	{ 0x4000d, 0xe08 },
+	{ 0x4002d, 0xc1a },
+	{ 0x4004d, 0x0 },
+	{ 0x4006d, 0x0 },
+	{ 0x4000e, 0x623 },
+	{ 0x4002e, 0x1a },
+	{ 0x4004e, 0x0 },
+	{ 0x4006e, 0x0 },
+	{ 0x4000f, 0x4040 },
+	{ 0x4002f, 0x80 },
+	{ 0x4004f, 0x0 },
+	{ 0x4006f, 0x0 },
+	{ 0x40010, 0x2604 },
+	{ 0x40030, 0x15 },
+	{ 0x40050, 0x0 },
+	{ 0x40070, 0x0 },
+	{ 0x40011, 0x708 },
+	{ 0x40031, 0x5 },
+	{ 0x40051, 0x0 },
+	{ 0x40071, 0x2002 },
+	{ 0x40012, 0x8 },
+	{ 0x40032, 0x80 },
+	{ 0x40052, 0x0 },
+	{ 0x40072, 0x0 },
+	{ 0x40013, 0x2604 },
+	{ 0x40033, 0x1a },
+	{ 0x40053, 0x0 },
+	{ 0x40073, 0x0 },
+	{ 0x40014, 0x708 },
+	{ 0x40034, 0xa },
+	{ 0x40054, 0x0 },
+	{ 0x40074, 0x2002 },
+	{ 0x40015, 0x4040 },
+	{ 0x40035, 0x80 },
+	{ 0x40055, 0x0 },
+	{ 0x40075, 0x0 },
+	{ 0x40016, 0x60a },
+	{ 0x40036, 0x15 },
+	{ 0x40056, 0x1200 },
+	{ 0x40076, 0x0 },
+	{ 0x40017, 0x61a },
+	{ 0x40037, 0x15 },
+	{ 0x40057, 0x1300 },
+	{ 0x40077, 0x0 },
+	{ 0x40018, 0x60a },
+	{ 0x40038, 0x1a },
+	{ 0x40058, 0x1200 },
+	{ 0x40078, 0x0 },
+	{ 0x40019, 0x642 },
+	{ 0x40039, 0x1a },
+	{ 0x40059, 0x1300 },
+	{ 0x40079, 0x0 },
+	{ 0x4001a, 0x4808 },
+	{ 0x4003a, 0x880 },
+	{ 0x4005a, 0x0 },
+	{ 0x4007a, 0x0 },
+	{ 0x900a7, 0x0 },
+	{ 0x900a8, 0x790 },
+	{ 0x900a9, 0x11a },
+	{ 0x900aa, 0x8 },
+	{ 0x900ab, 0x7aa },
+	{ 0x900ac, 0x2a },
+	{ 0x900ad, 0x10 },
+	{ 0x900ae, 0x7b2 },
+	{ 0x900af, 0x2a },
+	{ 0x900b0, 0x0 },
+	{ 0x900b1, 0x7c8 },
+	{ 0x900b2, 0x109 },
+	{ 0x900b3, 0x10 },
+	{ 0x900b4, 0x2a8 },
+	{ 0x900b5, 0x129 },
+	{ 0x900b6, 0x8 },
+	{ 0x900b7, 0x370 },
+	{ 0x900b8, 0x129 },
+	{ 0x900b9, 0xa },
+	{ 0x900ba, 0x3c8 },
+	{ 0x900bb, 0x1a9 },
+	{ 0x900bc, 0xc },
+	{ 0x900bd, 0x408 },
+	{ 0x900be, 0x199 },
+	{ 0x900bf, 0x14 },
+	{ 0x900c0, 0x790 },
+	{ 0x900c1, 0x11a },
+	{ 0x900c2, 0x8 },
+	{ 0x900c3, 0x4 },
+	{ 0x900c4, 0x18 },
+	{ 0x900c5, 0xe },
+	{ 0x900c6, 0x408 },
+	{ 0x900c7, 0x199 },
+	{ 0x900c8, 0x8 },
+	{ 0x900c9, 0x8568 },
+	{ 0x900ca, 0x108 },
+	{ 0x900cb, 0x18 },
+	{ 0x900cc, 0x790 },
+	{ 0x900cd, 0x16a },
+	{ 0x900ce, 0x8 },
+	{ 0x900cf, 0x1d8 },
+	{ 0x900d0, 0x169 },
+	{ 0x900d1, 0x10 },
+	{ 0x900d2, 0x8558 },
+	{ 0x900d3, 0x168 },
+	{ 0x900d4, 0x70 },
+	{ 0x900d5, 0x788 },
+	{ 0x900d6, 0x16a },
+	{ 0x900d7, 0x1ff8 },
+	{ 0x900d8, 0x85a8 },
+	{ 0x900d9, 0x1e8 },
+	{ 0x900da, 0x50 },
+	{ 0x900db, 0x798 },
+	{ 0x900dc, 0x16a },
+	{ 0x900dd, 0x60 },
+	{ 0x900de, 0x7a0 },
+	{ 0x900df, 0x16a },
+	{ 0x900e0, 0x8 },
+	{ 0x900e1, 0x8310 },
+	{ 0x900e2, 0x168 },
+	{ 0x900e3, 0x8 },
+	{ 0x900e4, 0xa310 },
+	{ 0x900e5, 0x168 },
+	{ 0x900e6, 0xa },
+	{ 0x900e7, 0x408 },
+	{ 0x900e8, 0x169 },
+	{ 0x900e9, 0x6e },
+	{ 0x900ea, 0x0 },
+	{ 0x900eb, 0x68 },
+	{ 0x900ec, 0x0 },
+	{ 0x900ed, 0x408 },
+	{ 0x900ee, 0x169 },
+	{ 0x900ef, 0x0 },
+	{ 0x900f0, 0x8310 },
+	{ 0x900f1, 0x168 },
+	{ 0x900f2, 0x0 },
+	{ 0x900f3, 0xa310 },
+	{ 0x900f4, 0x168 },
+	{ 0x900f5, 0x1ff8 },
+	{ 0x900f6, 0x85a8 },
+	{ 0x900f7, 0x1e8 },
+	{ 0x900f8, 0x68 },
+	{ 0x900f9, 0x798 },
+	{ 0x900fa, 0x16a },
+	{ 0x900fb, 0x78 },
+	{ 0x900fc, 0x7a0 },
+	{ 0x900fd, 0x16a },
+	{ 0x900fe, 0x68 },
+	{ 0x900ff, 0x790 },
+	{ 0x90100, 0x16a },
+	{ 0x90101, 0x8 },
+	{ 0x90102, 0x8b10 },
+	{ 0x90103, 0x168 },
+	{ 0x90104, 0x8 },
+	{ 0x90105, 0xab10 },
+	{ 0x90106, 0x168 },
+	{ 0x90107, 0xa },
+	{ 0x90108, 0x408 },
+	{ 0x90109, 0x169 },
+	{ 0x9010a, 0x58 },
+	{ 0x9010b, 0x0 },
+	{ 0x9010c, 0x68 },
+	{ 0x9010d, 0x0 },
+	{ 0x9010e, 0x408 },
+	{ 0x9010f, 0x169 },
+	{ 0x90110, 0x0 },
+	{ 0x90111, 0x8b10 },
+	{ 0x90112, 0x168 },
+	{ 0x90113, 0x0 },
+	{ 0x90114, 0xab10 },
+	{ 0x90115, 0x168 },
+	{ 0x90116, 0x0 },
+	{ 0x90117, 0x1d8 },
+	{ 0x90118, 0x169 },
+	{ 0x90119, 0x80 },
+	{ 0x9011a, 0x790 },
+	{ 0x9011b, 0x16a },
+	{ 0x9011c, 0x18 },
+	{ 0x9011d, 0x7aa },
+	{ 0x9011e, 0x6a },
+	{ 0x9011f, 0xa },
+	{ 0x90120, 0x0 },
+	{ 0x90121, 0x1e9 },
+	{ 0x90122, 0x8 },
+	{ 0x90123, 0x8080 },
+	{ 0x90124, 0x108 },
+	{ 0x90125, 0xf },
+	{ 0x90126, 0x408 },
+	{ 0x90127, 0x169 },
+	{ 0x90128, 0xc },
+	{ 0x90129, 0x0 },
+	{ 0x9012a, 0x68 },
+	{ 0x9012b, 0x9 },
+	{ 0x9012c, 0x0 },
+	{ 0x9012d, 0x1a9 },
+	{ 0x9012e, 0x0 },
+	{ 0x9012f, 0x408 },
+	{ 0x90130, 0x169 },
+	{ 0x90131, 0x0 },
+	{ 0x90132, 0x8080 },
+	{ 0x90133, 0x108 },
+	{ 0x90134, 0x8 },
+	{ 0x90135, 0x7aa },
+	{ 0x90136, 0x6a },
+	{ 0x90137, 0x0 },
+	{ 0x90138, 0x8568 },
+	{ 0x90139, 0x108 },
+	{ 0x9013a, 0xb7 },
+	{ 0x9013b, 0x790 },
+	{ 0x9013c, 0x16a },
+	{ 0x9013d, 0x1f },
+	{ 0x9013e, 0x0 },
+	{ 0x9013f, 0x68 },
+	{ 0x90140, 0x8 },
+	{ 0x90141, 0x8558 },
+	{ 0x90142, 0x168 },
+	{ 0x90143, 0xf },
+	{ 0x90144, 0x408 },
+	{ 0x90145, 0x169 },
+	{ 0x90146, 0xc },
+	{ 0x90147, 0x0 },
+	{ 0x90148, 0x68 },
+	{ 0x90149, 0x0 },
+	{ 0x9014a, 0x408 },
+	{ 0x9014b, 0x169 },
+	{ 0x9014c, 0x0 },
+	{ 0x9014d, 0x8558 },
+	{ 0x9014e, 0x168 },
+	{ 0x9014f, 0x8 },
+	{ 0x90150, 0x3c8 },
+	{ 0x90151, 0x1a9 },
+	{ 0x90152, 0x3 },
+	{ 0x90153, 0x370 },
+	{ 0x90154, 0x129 },
+	{ 0x90155, 0x20 },
+	{ 0x90156, 0x2aa },
+	{ 0x90157, 0x9 },
+	{ 0x90158, 0x0 },
+	{ 0x90159, 0x400 },
+	{ 0x9015a, 0x10e },
+	{ 0x9015b, 0x8 },
+	{ 0x9015c, 0xe8 },
+	{ 0x9015d, 0x109 },
+	{ 0x9015e, 0x0 },
+	{ 0x9015f, 0x8140 },
+	{ 0x90160, 0x10c },
+	{ 0x90161, 0x10 },
+	{ 0x90162, 0x8138 },
+	{ 0x90163, 0x10c },
+	{ 0x90164, 0x8 },
+	{ 0x90165, 0x7c8 },
+	{ 0x90166, 0x101 },
+	{ 0x90167, 0x8 },
+	{ 0x90168, 0x0 },
+	{ 0x90169, 0x8 },
+	{ 0x9016a, 0x8 },
+	{ 0x9016b, 0x448 },
+	{ 0x9016c, 0x109 },
+	{ 0x9016d, 0xf },
+	{ 0x9016e, 0x7c0 },
+	{ 0x9016f, 0x109 },
+	{ 0x90170, 0x0 },
+	{ 0x90171, 0xe8 },
+	{ 0x90172, 0x109 },
+	{ 0x90173, 0x47 },
+	{ 0x90174, 0x630 },
+	{ 0x90175, 0x109 },
+	{ 0x90176, 0x8 },
+	{ 0x90177, 0x618 },
+	{ 0x90178, 0x109 },
+	{ 0x90179, 0x8 },
+	{ 0x9017a, 0xe0 },
+	{ 0x9017b, 0x109 },
+	{ 0x9017c, 0x0 },
+	{ 0x9017d, 0x7c8 },
+	{ 0x9017e, 0x109 },
+	{ 0x9017f, 0x8 },
+	{ 0x90180, 0x8140 },
+	{ 0x90181, 0x10c },
+	{ 0x90182, 0x0 },
+	{ 0x90183, 0x1 },
+	{ 0x90184, 0x8 },
+	{ 0x90185, 0x8 },
+	{ 0x90186, 0x4 },
+	{ 0x90187, 0x8 },
+	{ 0x90188, 0x8 },
+	{ 0x90189, 0x7c8 },
+	{ 0x9018a, 0x101 },
+	{ 0x90006, 0x0 },
+	{ 0x90007, 0x0 },
+	{ 0x90008, 0x8 },
+	{ 0x90009, 0x0 },
+	{ 0x9000a, 0x0 },
+	{ 0x9000b, 0x0 },
+	{ 0xd00e7, 0x400 },
+	{ 0x90017, 0x0 },
+	{ 0x9001f, 0x2a },
+	{ 0x90026, 0x6a },
+	{ 0x400d0, 0x0 },
+	{ 0x400d1, 0x101 },
+	{ 0x400d2, 0x105 },
+	{ 0x400d3, 0x107 },
+	{ 0x400d4, 0x10f },
+	{ 0x400d5, 0x202 },
+	{ 0x400d6, 0x20a },
+	{ 0x400d7, 0x20b },
+	{ 0x2003a, 0x2 },
+	{ 0x2000b, 0x5d },
+	{ 0x2000c, 0xbb },
+	{ 0x2000d, 0x753 },
+	{ 0x2000e, 0x2c },
+	{ 0x12000b, 0xc },
+	{ 0x12000c, 0x19 },
+	{ 0x12000d, 0xfa },
+	{ 0x12000e, 0x10 },
+	{ 0x22000b, 0x3 },
+	{ 0x22000c, 0x6 },
+	{ 0x22000d, 0x3e },
+	{ 0x22000e, 0x10 },
+	{ 0x9000c, 0x0 },
+	{ 0x9000d, 0x173 },
+	{ 0x9000e, 0x60 },
+	{ 0x9000f, 0x6110 },
+	{ 0x90010, 0x2152 },
+	{ 0x90011, 0xdfbd },
+	{ 0x90012, 0x60 },
+	{ 0x90013, 0x6152 },
+	{ 0x20010, 0x5a },
+	{ 0x20011, 0x3 },
+	{ 0x40080, 0xe0 },
+	{ 0x40081, 0x12 },
+	{ 0x40082, 0xe0 },
+	{ 0x40083, 0x12 },
+	{ 0x40084, 0xe0 },
+	{ 0x40085, 0x12 },
+	{ 0x140080, 0xe0 },
+	{ 0x140081, 0x12 },
+	{ 0x140082, 0xe0 },
+	{ 0x140083, 0x12 },
+	{ 0x140084, 0xe0 },
+	{ 0x140085, 0x12 },
+	{ 0x240080, 0xe0 },
+	{ 0x240081, 0x12 },
+	{ 0x240082, 0xe0 },
+	{ 0x240083, 0x12 },
+	{ 0x240084, 0xe0 },
+	{ 0x240085, 0x12 },
+	{ 0x400fd, 0xf },
+	{ 0x10011, 0x1 },
+	{ 0x10012, 0x1 },
+	{ 0x10013, 0x180 },
+	{ 0x10018, 0x1 },
+	{ 0x10002, 0x6209 },
+	{ 0x100b2, 0x1 },
+	{ 0x101b4, 0x1 },
+	{ 0x102b4, 0x1 },
+	{ 0x103b4, 0x1 },
+	{ 0x104b4, 0x1 },
+	{ 0x105b4, 0x1 },
+	{ 0x106b4, 0x1 },
+	{ 0x107b4, 0x1 },
+	{ 0x108b4, 0x1 },
+	{ 0x11011, 0x1 },
+	{ 0x11012, 0x1 },
+	{ 0x11013, 0x180 },
+	{ 0x11018, 0x1 },
+	{ 0x11002, 0x6209 },
+	{ 0x110b2, 0x1 },
+	{ 0x111b4, 0x1 },
+	{ 0x112b4, 0x1 },
+	{ 0x113b4, 0x1 },
+	{ 0x114b4, 0x1 },
+	{ 0x115b4, 0x1 },
+	{ 0x116b4, 0x1 },
+	{ 0x117b4, 0x1 },
+	{ 0x118b4, 0x1 },
+	{ 0x12011, 0x1 },
+	{ 0x12012, 0x1 },
+	{ 0x12013, 0x180 },
+	{ 0x12018, 0x1 },
+	{ 0x12002, 0x6209 },
+	{ 0x120b2, 0x1 },
+	{ 0x121b4, 0x1 },
+	{ 0x122b4, 0x1 },
+	{ 0x123b4, 0x1 },
+	{ 0x124b4, 0x1 },
+	{ 0x125b4, 0x1 },
+	{ 0x126b4, 0x1 },
+	{ 0x127b4, 0x1 },
+	{ 0x128b4, 0x1 },
+	{ 0x13011, 0x1 },
+	{ 0x13012, 0x1 },
+	{ 0x13013, 0x180 },
+	{ 0x13018, 0x1 },
+	{ 0x13002, 0x6209 },
+	{ 0x130b2, 0x1 },
+	{ 0x131b4, 0x1 },
+	{ 0x132b4, 0x1 },
+	{ 0x133b4, 0x1 },
+	{ 0x134b4, 0x1 },
+	{ 0x135b4, 0x1 },
+	{ 0x136b4, 0x1 },
+	{ 0x137b4, 0x1 },
+	{ 0x138b4, 0x1 },
+	{ 0x2003a, 0x2 },
+	{ 0xc0080, 0x2 },
+	{ 0xd0000, 0x1 },
+};
+
+struct dram_fsp_msg lpddr4_dram_fsp_msg[] = {
+	{
+		/* P0 3000mts 1D */
+		.drate = 3000,
+		.fw_type = FW_1D_IMAGE,
+		.fsp_cfg = lpddr4_fsp0_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp0_cfg),
+	},
+	{
+		/* P0 3000mts 2D */
+		.drate = 3000,
+		.fw_type = FW_2D_IMAGE,
+		.fsp_cfg = lpddr4_fsp0_2d_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp0_2d_cfg),
+	},
+	{
+		/* P1 400mts 1D */
+		.drate = 400,
+		.fw_type = FW_1D_IMAGE,
+		.fsp_cfg = lpddr4_fsp1_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp1_cfg),
+	},
+	{
+		/* P1 100mts 1D */
+		.drate = 100,
+		.fw_type = FW_1D_IMAGE,
+		.fsp_cfg = lpddr4_fsp2_cfg,
+		.fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp2_cfg),
+	},
+};
+
+/* lpddr4 timing config params on EVK board */
+struct dram_timing_info dram_timing = {
+	.ddrc_cfg = lpddr4_ddrc_cfg,
+	.ddrc_cfg_num = ARRAY_SIZE(lpddr4_ddrc_cfg),
+	.ddrphy_cfg = lpddr4_ddrphy_cfg,
+	.ddrphy_cfg_num = ARRAY_SIZE(lpddr4_ddrphy_cfg),
+	.fsp_msg = lpddr4_dram_fsp_msg,
+	.fsp_msg_num = ARRAY_SIZE(lpddr4_dram_fsp_msg),
+	.ddrphy_trained_csr = lpddr4_ddrphy_trained_csr,
+	.ddrphy_trained_csr_num = ARRAY_SIZE(lpddr4_ddrphy_trained_csr),
+	.ddrphy_pie = lpddr4_phy_pie,
+	.ddrphy_pie_num = ARRAY_SIZE(lpddr4_phy_pie),
+};
diff --git a/board/freescale/imx8mm_evk/spl.c b/board/freescale/imx8mm_evk/spl.c
new file mode 100644
index 0000000000..9e140ecf19
--- /dev/null
+++ b/board/freescale/imx8mm_evk/spl.c
@@ -0,0 +1,216 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019 NXP
+ */
+
+#include <common.h>
+#include <spl.h>
+#include <asm/io.h>
+#include <errno.h>
+#include <asm/io.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/arch/imx8mm_pins.h>
+#include <asm/arch/sys_proto.h>
+#include <power/pmic.h>
+#include <asm/arch/clock.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/mach-imx/gpio.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <fsl_esdhc.h>
+#include <mmc.h>
+#include <asm/arch/ddr.h>
+
+#include <dm/uclass.h>
+#include <dm/device.h>
+#include <dm/uclass-internal.h>
+#include <dm/device-internal.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int spl_board_boot_device(enum boot_device boot_dev_spl)
+{
+	switch (boot_dev_spl) {
+	case SD2_BOOT:
+	case MMC2_BOOT:
+		return BOOT_DEVICE_MMC1;
+	case SD3_BOOT:
+	case MMC3_BOOT:
+		return BOOT_DEVICE_MMC2;
+	default:
+		return BOOT_DEVICE_NONE;
+	}
+}
+
+void spl_dram_init(void)
+{
+	ddr_init(&dram_timing);
+}
+
+#define USDHC2_CD_GPIO	IMX_GPIO_NR(2, 18)
+#define USDHC2_PWR_GPIO IMX_GPIO_NR(2, 19)
+
+#define USDHC_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | \
+			PAD_CTL_PE | PAD_CTL_FSEL2)
+#define USDHC_GPIO_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE1)
+
+static iomux_v3_cfg_t const usdhc3_pads[] = {
+	IMX8MM_PAD_NAND_WE_B_USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MM_PAD_NAND_WP_B_USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MM_PAD_NAND_DATA04_USDHC3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MM_PAD_NAND_DATA05_USDHC3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MM_PAD_NAND_DATA06_USDHC3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MM_PAD_NAND_DATA07_USDHC3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MM_PAD_NAND_RE_B_USDHC3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MM_PAD_NAND_CE2_B_USDHC3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MM_PAD_NAND_CE3_B_USDHC3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MM_PAD_NAND_CLE_USDHC3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const usdhc2_pads[] = {
+	IMX8MM_PAD_SD2_CLK_USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MM_PAD_SD2_CMD_USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MM_PAD_SD2_DATA0_USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MM_PAD_SD2_DATA1_USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MM_PAD_SD2_DATA2_USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MM_PAD_SD2_DATA3_USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	IMX8MM_PAD_SD2_RESET_B_GPIO2_IO19 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL),
+};
+
+/*
+ * The evk board uses DAT3 to detect CD card plugin,
+ * in u-boot we mux the pin to GPIO when doing board_mmc_getcd.
+ */
+static iomux_v3_cfg_t const usdhc2_cd_pad =
+	IMX8MM_PAD_SD2_DATA3_GPIO2_IO18 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL);
+
+static iomux_v3_cfg_t const usdhc2_dat3_pad =
+	IMX8MM_PAD_SD2_DATA3_USDHC2_DATA3 |
+	MUX_PAD_CTRL(USDHC_PAD_CTRL);
+
+static struct fsl_esdhc_cfg usdhc_cfg[2] = {
+	{USDHC2_BASE_ADDR, 0, 1},
+	{USDHC3_BASE_ADDR, 0, 1},
+};
+
+int board_mmc_init(bd_t *bis)
+{
+	int i, ret;
+	/*
+	 * According to the board_mmc_init() the following map is done:
+	 * (U-Boot device node)    (Physical Port)
+	 * mmc0                    USDHC1
+	 * mmc1                    USDHC2
+	 */
+	for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
+		switch (i) {
+		case 0:
+			usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
+			imx_iomux_v3_setup_multiple_pads(usdhc2_pads,
+							 ARRAY_SIZE(usdhc2_pads));
+			gpio_request(USDHC2_PWR_GPIO, "usdhc2_reset");
+			gpio_direction_output(USDHC2_PWR_GPIO, 0);
+			udelay(500);
+			gpio_direction_output(USDHC2_PWR_GPIO, 1);
+			break;
+		case 1:
+			usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+			imx_iomux_v3_setup_multiple_pads(usdhc3_pads,
+							 ARRAY_SIZE(usdhc3_pads));
+			break;
+		default:
+			printf("USDHC controllers %d not supported \n", i + 1);
+			return -EINVAL;
+		}
+
+		ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
+		if (ret)
+			return ret;
+	}
+
+	return 0;
+}
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+	int ret = 0;
+
+	switch (cfg->esdhc_base) {
+	case USDHC3_BASE_ADDR:
+		ret = 1;
+		break;
+	case USDHC2_BASE_ADDR:
+		imx_iomux_v3_setup_pad(usdhc2_cd_pad);
+		gpio_request(USDHC2_CD_GPIO, "usdhc2 cd");
+		gpio_direction_input(USDHC2_CD_GPIO);
+
+		/*
+		 * Since it is the DAT3 pin, this pin is pulled to
+		 * low voltage if no card
+		 */
+		ret = gpio_get_value(USDHC2_CD_GPIO);
+
+		imx_iomux_v3_setup_pad(usdhc2_dat3_pad);
+		return ret;
+	}
+
+	return 1;
+}
+
+void spl_board_init(void)
+{
+	struct udevice *dev;
+
+	puts("Normal Boot\n");
+
+	uclass_find_first_device(UCLASS_CLK, &dev);
+
+	for (; dev; uclass_find_next_device(&dev)) {
+		if (device_probe(dev))
+			continue;
+	}
+}
+
+#ifdef CONFIG_SPL_LOAD_FIT
+int board_fit_config_name_match(const char *name)
+{
+	/* Just empty function now - can't decide what to choose */
+	debug("%s: %s\n", __func__, name);
+
+	return 0;
+}
+#endif
+
+void board_init_f(ulong dummy)
+{
+	int ret;
+
+	/* Clear global data */
+	memset((void *)gd, 0, sizeof(gd_t));
+
+	arch_cpu_init();
+
+	init_uart_clk(1);
+
+	board_early_init_f();
+
+	timer_init();
+
+	preloader_console_init();
+
+	/* Clear the BSS. */
+	memset(__bss_start, 0, __bss_end - __bss_start);
+
+	ret = spl_init();
+	if (ret) {
+		debug("spl_init() failed: %d\n", ret);
+		hang();
+	}
+
+	enable_tzc380();
+
+	/* DDR initialization */
+	spl_dram_init();
+
+	board_init_r(NULL, 0);
+}
diff --git a/configs/imx8mm_evk_defconfig b/configs/imx8mm_evk_defconfig
new file mode 100644
index 0000000000..49a242222b
--- /dev/null
+++ b/configs/imx8mm_evk_defconfig
@@ -0,0 +1,52 @@
+CONFIG_ARM=y
+CONFIG_ARCH_IMX8M=y
+CONFIG_SYS_TEXT_BASE=0x40200000
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SYS_MALLOC_F_LEN=0x6000
+CONFIG_TARGET_IMX8MM_EVK=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL=y
+CONFIG_FIT=y
+CONFIG_FIT_EXTERNAL_OFFSET=0x3000
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh"
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/imx8m/imximage.cfg,SPL_TEXT_BASE=0x7E1000"
+CONFIG_DEFAULT_FDT_FILE="fsl-imx8mm-evk.dtb"
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_CLK=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="imx8mm-evk"
+CONFIG_SPL_DM=y
+CONFIG_SPL_CLK=y
+CONFIG_SPL_CLK_COMPOSITE_CCF=y
+CONFIG_CLK_COMPOSITE_CCF=y
+CONFIG_CLK_IMX8MM=y
+CONFIG_DM_GPIO=y
+CONFIG_MXC_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_DM_MMC=y
+CONFIG_DM_ETH=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_PINCTRL_IMX8M=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_MXC_UART=y
+CONFIG_DM_THERMAL=y
diff --git a/include/configs/imx8mm_evk.h b/include/configs/imx8mm_evk.h
new file mode 100644
index 0000000000..f7f9592ecc
--- /dev/null
+++ b/include/configs/imx8mm_evk.h
@@ -0,0 +1,199 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2018 NXP
+ */
+
+#ifndef __IMX8MM_EVK_H
+#define __IMX8MM_EVK_H
+
+#include <linux/sizes.h>
+#include <asm/arch/imx-regs.h>
+
+#ifdef CONFIG_SECURE_BOOT
+#define CONFIG_CSF_SIZE			0x2000 /* 8K region */
+#endif
+
+#define CONFIG_SPL_MAX_SIZE		(148 * 1024)
+#define CONFIG_SYS_MONITOR_LEN		(512 * 1024)
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR	0x300
+#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION	1
+#define CONFIG_SYS_UBOOT_BASE	\
+	(QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
+
+#ifdef CONFIG_SPL_BUILD
+/*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/
+#define CONFIG_SPL_WATCHDOG_SUPPORT
+#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
+#define CONFIG_SPL_POWER_SUPPORT
+#define CONFIG_SPL_LDSCRIPT		"arch/arm/cpu/armv8/u-boot-spl.lds"
+#define CONFIG_SPL_STACK		0x91fff0
+#define CONFIG_SPL_BSS_START_ADDR      0x00910000
+#define CONFIG_SPL_BSS_MAX_SIZE        0x2000	/* 8 KB */
+#define CONFIG_SYS_SPL_MALLOC_START    0x42200000
+#define CONFIG_SYS_SPL_MALLOC_SIZE     0x80000	/* 512 KB */
+#define CONFIG_SYS_ICACHE_OFF
+#define CONFIG_SYS_DCACHE_OFF
+
+#define CONFIG_MALLOC_F_ADDR		0x912000 /* malloc f used before GD_FLG_FULL_MALLOC_INIT set */
+
+#define CONFIG_SPL_ABORT_ON_RAW_IMAGE /* For RAW image gives a error info not panic */
+
+#undef CONFIG_DM_MMC
+#undef CONFIG_DM_PMIC
+#undef CONFIG_DM_PMIC_PFUZE100
+
+#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+
+#endif
+
+#define CONFIG_REMAKE_ELF
+
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_BOARD_POSTCLK_INIT
+#define CONFIG_BOARD_LATE_INIT
+
+/* Flat Device Tree Definitions */
+#define CONFIG_OF_BOARD_SETUP
+
+#undef CONFIG_CMD_EXPORTENV
+#undef CONFIG_CMD_IMPORTENV
+#undef CONFIG_CMD_IMLS
+
+#undef CONFIG_CMD_CRC32
+#undef CONFIG_BOOTM_NETBSD
+
+/* Initial environment variables */
+#define CONFIG_EXTRA_ENV_SETTINGS		\
+	"script=boot.scr\0" \
+	"image=Image\0" \
+	"console=ttymxc1,115200 earlycon=ec_imx6q,0x30890000,115200\0" \
+	"fdt_addr=0x43000000\0"			\
+	"fdt_high=0xffffffffffffffff\0"		\
+	"boot_fdt=try\0" \
+	"fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
+	"initrd_addr=0x43800000\0"		\
+	"initrd_high=0xffffffffffffffff\0" \
+	"mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
+	"mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
+	"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
+	"mmcautodetect=yes\0" \
+	"mmcargs=setenv bootargs ${jh_clk} console=${console} root=${mmcroot}\0 " \
+	"loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
+	"bootscript=echo Running bootscript from mmc ...; " \
+		"source\0" \
+	"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
+	"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
+	"mmcboot=echo Booting from mmc ...; " \
+		"run mmcargs; " \
+		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+			"if run loadfdt; then " \
+				"booti ${loadaddr} - ${fdt_addr}; " \
+			"else " \
+				"echo WARN: Cannot load the DT; " \
+			"fi; " \
+		"else " \
+			"echo wait for boot; " \
+		"fi;\0" \
+	"netargs=setenv bootargs ${jh_clk} console=${console} " \
+		"root=/dev/nfs " \
+		"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
+	"netboot=echo Booting from net ...; " \
+		"run netargs;  " \
+		"if test ${ip_dyn} = yes; then " \
+			"setenv get_cmd dhcp; " \
+		"else " \
+			"setenv get_cmd tftp; " \
+		"fi; " \
+		"${get_cmd} ${loadaddr} ${image}; " \
+		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+			"if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
+				"booti ${loadaddr} - ${fdt_addr}; " \
+			"else " \
+				"echo WARN: Cannot load the DT; " \
+			"fi; " \
+		"else " \
+			"booti; " \
+		"fi;\0"
+
+#define CONFIG_BOOTCOMMAND \
+	   "mmc dev ${mmcdev}; if mmc rescan; then " \
+		   "if run loadbootscript; then " \
+			   "run bootscript; " \
+		   "else " \
+			   "if run loadimage; then " \
+				   "run mmcboot; " \
+			   "else run netboot; " \
+			   "fi; " \
+		   "fi; " \
+	   "else booti ${loadaddr} - ${fdt_addr}; fi"
+
+/* Link Definitions */
+#define CONFIG_LOADADDR			0x40480000
+
+#define CONFIG_SYS_LOAD_ADDR           CONFIG_LOADADDR
+
+#define CONFIG_SYS_INIT_RAM_ADDR        0x40000000
+#define CONFIG_SYS_INIT_RAM_SIZE        0x80000
+#define CONFIG_SYS_INIT_SP_OFFSET \
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+#define CONFIG_ENV_OVERWRITE
+#if defined(CONFIG_ENV_IS_IN_MMC)
+#define CONFIG_ENV_OFFSET               (64 * SZ_64K)
+#endif
+#define CONFIG_ENV_SIZE			0x1000
+#define CONFIG_SYS_MMC_ENV_DEV		0   /* USDHC2 */
+#define CONFIG_MMCROOT			"/dev/mmcblk1p2"  /* USDHC2 */
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN		SZ_32M
+
+#define CONFIG_SYS_SDRAM_BASE           0x40000000
+#define PHYS_SDRAM                      0x40000000
+#define PHYS_SDRAM_SIZE			0x80000000 /* 2GB DDR */
+
+#define CONFIG_SYS_MEMTEST_START    PHYS_SDRAM
+#define CONFIG_SYS_MEMTEST_END      (CONFIG_SYS_MEMTEST_START + (PHYS_SDRAM_SIZE >> 1))
+
+#define CONFIG_BAUDRATE			115200
+
+#define CONFIG_MXC_UART_BASE		UART2_BASE_ADDR
+
+/* Monitor Command Prompt */
+#undef CONFIG_SYS_PROMPT
+#define CONFIG_SYS_PROMPT		"u-boot=> "
+#define CONFIG_SYS_PROMPT_HUSH_PS2     "> "
+#define CONFIG_SYS_CBSIZE              2048
+#define CONFIG_SYS_MAXARGS             64
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
+					sizeof(CONFIG_SYS_PROMPT) + 16)
+
+#define CONFIG_IMX_BOOTAUX
+
+/* USDHC */
+#define CONFIG_CMD_MMC
+#define CONFIG_FSL_ESDHC
+#define CONFIG_FSL_USDHC
+
+#define CONFIG_SYS_FSL_USDHC_NUM	2
+#define CONFIG_SYS_FSL_ESDHC_ADDR       0
+
+#define CONFIG_SUPPORT_EMMC_BOOT	/* eMMC specific */
+#define CONFIG_SYS_MMC_IMG_LOAD_PART	1
+
+#define CONFIG_CMD_FUSE
+
+#define CONFIG_SYS_I2C_MXC_I2C1		/* enable I2C bus 1 */
+#define CONFIG_SYS_I2C_MXC_I2C2		/* enable I2C bus 2 */
+#define CONFIG_SYS_I2C_MXC_I2C3		/* enable I2C bus 3 */
+#define CONFIG_SYS_I2C_SPEED		100000
+
+#define CONFIG_OF_SYSTEM_SETUP
+
+#define CONFIG_PHYLIB
+
+#endif
-- 
2.16.4

[U-Boot] [i.MX8MM+CCF 00/41] i.MX8MM + CCF

[Schrempf Frieder]

Hi Peng,

I'm trying to add support for a board with i.MX8MM. First I applied 
Lukasz's CCF patches and your patches to U-Boot 2019.04 and tried to 
build imx8mm_evk config. But I'm getting build errors (see below).

Are there any other patches needed?
What things are still missing to get i.MX8MM running in U-Boot?

Thanks,
Frieder

| aarch64-ktn-linux-ld.bfd: cmd/built-in.o: in function `do_fuse':
| /home/frieder/repos/u-boot/cmd/fuse.c:68: undefined reference to 
`fuse_read'
| aarch64-ktn-linux-ld.bfd: /home/frieder/repos/u-boot/cmd/fuse.c:86: 
undefined reference to `fuse_sense'
| aarch64-ktn-linux-ld.bfd: /home/frieder/repos/u-boot/cmd/fuse.c:105: 
undefined reference to `fuse_prog'
| aarch64-ktn-linux-ld.bfd: /home/frieder/repos/u-boot/cmd/fuse.c:119: 
undefined reference to `fuse_override'
| aarch64-ktn-linux-ld.bfd: drivers/i2c/built-in.o: in function 
`mxc_i2c_probe':
| /home/frieder/repos/u-boot/drivers/i2c/mxc_i2c.c:824: undefined 
reference to `enable_i2c_clk'
| aarch64-ktn-linux-ld.bfd: 
/home/frieder/repos/u-boot/drivers/i2c/mxc_i2c.c:853: undefined 
reference to `enable_i2c_clk'


On 30.04.19 12:17, Peng Fan wrote:
> This patch set is based Lukasz V3 CCF patchset,
> [PATCH v3 00/11] clk: Port Linux common clock framework [CCF] to U-boot (tag: 5.0-rc3)
> https://github.com/lmajewski/u-boot-dfu/commits/CCF-v3
> 
> Added a few fixes to Lukasz's v3 patchset.
> Introduced clk-gate/composite
> Added set rate support
> Per my understanding, U-Boot CCF will not support mux reparent, and
> support rate prograte setting to parent automatically. So new clk
> feature added follow this rule.
> 
> There are many warnings when importing linux ccf code, I did not
> modify them all.
> 
> The rest patches are for i.MX8MM, part of legacy clk code are still
> kept, because we are hard to enable CCF at very early stage, we set
> malloc space to DRAM when dram initialized in spl stage, so we have
> limited SRAM for uclass dm and dm clk, so keep the DRAM PLL related
> setting with legacy clk code which use small ram.
> 
> The u-boot-spl.bin now is about 100KB without ddr firmware,usb stack and hab,
> so really large......
> I am thinking what we could do to shrink the size, welcome any suggestions.
> 
> Not expect this patchset could be merged, because of the CCF/clock code
> change, but since the clock part blocks i.MX8MM upstream, just would like
> to speed up the development with community and move on.
> 
> Peng Fan (40):
>    clk: correct get clk_x pointer
>    clk: fixed-factor: fix get clk_fixed_factor
>    clk: introduce clk_dev_binded
>    clk: use clk_dev_binded
>    clk-provider: sync more clk flags from Linux Kernel
>    cmd: clk: print err value when clk_get_rate failed
>    clk: mux: add set parent support
>    clk: export mux/divider ops
>    clk: add clk-gate support
>    divider set rate supporrt
>    clk: fixed_rate: export clk_fixed_rate
>    clk: fixed_rate: add pre reloc flag
>    clk: imx: import clk heplers
>    clk: imx: gate2 add set rate
>    linux: compat: guard PAGE_SIZE
>    drivers: core: use strcmp when find device by name
>    ddr: imx8m: fix ddr firmware location when enable SPL OF
>    imx: add IMX8MQ kconfig entry
>    imx: add IMX8MM kconfig entry
>    imx: imx8mm: add clock bindings header
>    imx: add i.MX8MM cpu type
>    imx: spl: add spl_board_boot_device for i.MX8MM
>    imx8m: update imx-regs for i.MX8MM
>    imx: add get_cpu_rev support for i.MX8MM
>    imx8m: rename clock to clock_imx8mq
>    imx8m: restructure clock.h
>    imx8m: add clk support for i.MX8MM
>    imx8m: soc: probe clk before relocation
>    imx8m: add pin header for i.MX8MM
>    imx: add i.MX8MM PE property
>    imx8m: Fix MMU table issue for OPTEE memory
>    imx8m: set BYPASS ID SWAP to avoid AXI bus errors
>    imx8m: soc: enable SCTR clock before timer init
>    serial: Kconfig: make MXC_UART usable for MX7 and IMX8M
>    clk: imx: add Kconfig entry for i.MX8MM
>    clk: imx: add pll14xx driver
>    clk: add composite clk support
>    clk: imx: add i.MX8MM composite clk support
>    clk: imx: add i.MX8MM clk driver
>    imx: add i.MX8MM EVK board support
> 
> Ye Li (1):
>    imx8m: Configure trustzone region 0 for non-secure access
> 
>   arch/arm/dts/Makefile                              |    3 +-
>   arch/arm/dts/imx8mm-evk-u-boot.dtsi                |   92 +
>   arch/arm/dts/imx8mm-evk.dts                        |  235 +++
>   arch/arm/dts/imx8mm-pinfunc.h                      |  629 +++++++
>   arch/arm/dts/imx8mm.dtsi                           |  733 ++++++++
>   arch/arm/include/asm/arch-imx/cpu.h                |    6 +
>   arch/arm/include/asm/arch-imx8m/clock.h            |  493 +----
>   arch/arm/include/asm/arch-imx8m/clock_imx8mm.h     |  387 ++++
>   arch/arm/include/asm/arch-imx8m/clock_imx8mq.h     |  424 +++++
>   arch/arm/include/asm/arch-imx8m/imx-regs.h         |   75 +-
>   arch/arm/include/asm/arch-imx8m/imx8mm_pins.h      |  691 +++++++
>   arch/arm/include/asm/mach-imx/iomux-v3.h           |    4 +
>   arch/arm/include/asm/mach-imx/sys_proto.h          |    8 +
>   arch/arm/mach-imx/cpu.c                            |   12 +
>   arch/arm/mach-imx/imx8m/Kconfig                    |   17 +-
>   arch/arm/mach-imx/imx8m/Makefile                   |    4 +-
>   arch/arm/mach-imx/imx8m/clock_imx8mm.c             |  292 +++
>   .../arm/mach-imx/imx8m/{clock.c => clock_imx8mq.c} |    5 +-
>   arch/arm/mach-imx/imx8m/clock_slice.c              |  461 +++++
>   arch/arm/mach-imx/imx8m/soc.c                      |  112 +-
>   arch/arm/mach-imx/spl.c                            |    8 +
>   board/freescale/imx8mm_evk/Kconfig                 |   12 +
>   board/freescale/imx8mm_evk/MAINTAINERS             |    6 +
>   board/freescale/imx8mm_evk/Makefile                |   12 +
>   board/freescale/imx8mm_evk/imx8mm_evk.c            |   90 +
>   board/freescale/imx8mm_evk/lpddr4_timing.c         | 1980 ++++++++++++++++++++
>   board/freescale/imx8mm_evk/spl.c                   |  216 +++
>   cmd/clk.c                                          |    2 +
>   configs/imx8mm_evk_defconfig                       |   52 +
>   drivers/clk/Kconfig                                |   14 +
>   drivers/clk/Makefile                               |    3 +-
>   drivers/clk/clk-composite.c                        |  165 ++
>   drivers/clk/clk-divider.c                          |   92 +-
>   drivers/clk/clk-fixed-factor.c                     |    2 +-
>   drivers/clk/clk-gate.c                             |  151 ++
>   drivers/clk/clk-mux.c                              |   76 +-
>   drivers/clk/clk.c                                  |    8 +
>   drivers/clk/clk_fixed_rate.c                       |    9 +-
>   drivers/clk/imx/Kconfig                            |    9 +
>   drivers/clk/imx/Makefile                           |    1 +
>   drivers/clk/imx/clk-composite-8m.c                 |  170 ++
>   drivers/clk/imx/clk-gate2.c                        |   15 +-
>   drivers/clk/imx/clk-imx8mm.c                       |  415 ++++
>   drivers/clk/imx/clk-pfd.c                          |    2 +-
>   drivers/clk/imx/clk-pll14xx.c                      |  377 ++++
>   drivers/clk/imx/clk-pllv3.c                        |    2 +-
>   drivers/clk/imx/clk.h                              |  106 ++
>   drivers/core/uclass.c                              |    2 +-
>   drivers/ddr/imx/imx8m/helper.c                     |   12 +-
>   drivers/serial/Kconfig                             |    2 +-
>   include/clk.h                                      |    9 +
>   include/configs/imx8mm_evk.h                       |  199 ++
>   include/dt-bindings/clock/imx8mm-clock.h           |  244 +++
>   include/linux/clk-provider.h                       |   74 +
>   include/linux/compat.h                             |    2 +
>   55 files changed, 8728 insertions(+), 494 deletions(-)
>   create mode 100644 arch/arm/dts/imx8mm-evk-u-boot.dtsi
>   create mode 100644 arch/arm/dts/imx8mm-evk.dts
>   create mode 100644 arch/arm/dts/imx8mm-pinfunc.h
>   create mode 100644 arch/arm/dts/imx8mm.dtsi
>   create mode 100644 arch/arm/include/asm/arch-imx8m/clock_imx8mm.h
>   create mode 100644 arch/arm/include/asm/arch-imx8m/clock_imx8mq.h
>   create mode 100644 arch/arm/include/asm/arch-imx8m/imx8mm_pins.h
>   create mode 100644 arch/arm/mach-imx/imx8m/clock_imx8mm.c
>   rename arch/arm/mach-imx/imx8m/{clock.c => clock_imx8mq.c} (99%)
>   create mode 100644 board/freescale/imx8mm_evk/Kconfig
>   create mode 100644 board/freescale/imx8mm_evk/MAINTAINERS
>   create mode 100644 board/freescale/imx8mm_evk/Makefile
>   create mode 100644 board/freescale/imx8mm_evk/imx8mm_evk.c
>   create mode 100644 board/freescale/imx8mm_evk/lpddr4_timing.c
>   create mode 100644 board/freescale/imx8mm_evk/spl.c
>   create mode 100644 configs/imx8mm_evk_defconfig
>   create mode 100644 drivers/clk/clk-composite.c
>   create mode 100644 drivers/clk/clk-gate.c
>   create mode 100644 drivers/clk/imx/clk-composite-8m.c
>   create mode 100644 drivers/clk/imx/clk-imx8mm.c
>   create mode 100644 drivers/clk/imx/clk-pll14xx.c
>   create mode 100644 include/configs/imx8mm_evk.h
>   create mode 100644 include/dt-bindings/clock/imx8mm-clock.h
> 

[U-Boot] [i.MX8MM+CCF 00/41] i.MX8MM + CCF

[Schrempf Frieder]

On 06.05.19 09:57, Frieder Schrempf wrote:
> Hi Peng,
> 
> I'm trying to add support for a board with i.MX8MM. First I applied 
> Lukasz's CCF patches and your patches to U-Boot 2019.04 and tried to 
> build imx8mm_evk config. But I'm getting build errors (see below).

The build works if I enable the OTP fuse driver and disable I2C support. 
In clock_imx8mm.c enable_i2c_clk() seems to be missing, or maybe the i2c 
driver needs to use the new clock framework now?

> 
> Are there any other patches needed?
> What things are still missing to get i.MX8MM running in U-Boot?

It seems like this still needs a bit of work. I also see some CONFIG 
options defined in the headers, that should be moved to defconfig.

> 
> Thanks,
> Frieder
> 
> | aarch64-ktn-linux-ld.bfd: cmd/built-in.o: in function `do_fuse':
> | /home/frieder/repos/u-boot/cmd/fuse.c:68: undefined reference to 
> `fuse_read'
> | aarch64-ktn-linux-ld.bfd: /home/frieder/repos/u-boot/cmd/fuse.c:86: 
> undefined reference to `fuse_sense'
> | aarch64-ktn-linux-ld.bfd: /home/frieder/repos/u-boot/cmd/fuse.c:105: 
> undefined reference to `fuse_prog'
> | aarch64-ktn-linux-ld.bfd: /home/frieder/repos/u-boot/cmd/fuse.c:119: 
> undefined reference to `fuse_override'
> | aarch64-ktn-linux-ld.bfd: drivers/i2c/built-in.o: in function 
> `mxc_i2c_probe':
> | /home/frieder/repos/u-boot/drivers/i2c/mxc_i2c.c:824: undefined 
> reference to `enable_i2c_clk'
> | aarch64-ktn-linux-ld.bfd: 
> /home/frieder/repos/u-boot/drivers/i2c/mxc_i2c.c:853: undefined 
> reference to `enable_i2c_clk'
> 
> 
> On 30.04.19 12:17, Peng Fan wrote:
>> This patch set is based Lukasz V3 CCF patchset,
>> [PATCH v3 00/11] clk: Port Linux common clock framework [CCF] to 
>> U-boot (tag: 5.0-rc3)
>> https://github.com/lmajewski/u-boot-dfu/commits/CCF-v3
>>
>> Added a few fixes to Lukasz's v3 patchset.
>> Introduced clk-gate/composite
>> Added set rate support
>> Per my understanding, U-Boot CCF will not support mux reparent, and
>> support rate prograte setting to parent automatically. So new clk
>> feature added follow this rule.
>>
>> There are many warnings when importing linux ccf code, I did not
>> modify them all.
>>
>> The rest patches are for i.MX8MM, part of legacy clk code are still
>> kept, because we are hard to enable CCF at very early stage, we set
>> malloc space to DRAM when dram initialized in spl stage, so we have
>> limited SRAM for uclass dm and dm clk, so keep the DRAM PLL related
>> setting with legacy clk code which use small ram.
>>
>> The u-boot-spl.bin now is about 100KB without ddr firmware,usb stack 
>> and hab,
>> so really large......
>> I am thinking what we could do to shrink the size, welcome any 
>> suggestions.
>>
>> Not expect this patchset could be merged, because of the CCF/clock code
>> change, but since the clock part blocks i.MX8MM upstream, just would like
>> to speed up the development with community and move on.
>>
>> Peng Fan (40):
>>    clk: correct get clk_x pointer
>>    clk: fixed-factor: fix get clk_fixed_factor
>>    clk: introduce clk_dev_binded
>>    clk: use clk_dev_binded
>>    clk-provider: sync more clk flags from Linux Kernel
>>    cmd: clk: print err value when clk_get_rate failed
>>    clk: mux: add set parent support
>>    clk: export mux/divider ops
>>    clk: add clk-gate support
>>    divider set rate supporrt
>>    clk: fixed_rate: export clk_fixed_rate
>>    clk: fixed_rate: add pre reloc flag
>>    clk: imx: import clk heplers
>>    clk: imx: gate2 add set rate
>>    linux: compat: guard PAGE_SIZE
>>    drivers: core: use strcmp when find device by name
>>    ddr: imx8m: fix ddr firmware location when enable SPL OF
>>    imx: add IMX8MQ kconfig entry
>>    imx: add IMX8MM kconfig entry
>>    imx: imx8mm: add clock bindings header
>>    imx: add i.MX8MM cpu type
>>    imx: spl: add spl_board_boot_device for i.MX8MM
>>    imx8m: update imx-regs for i.MX8MM
>>    imx: add get_cpu_rev support for i.MX8MM
>>    imx8m: rename clock to clock_imx8mq
>>    imx8m: restructure clock.h
>>    imx8m: add clk support for i.MX8MM
>>    imx8m: soc: probe clk before relocation
>>    imx8m: add pin header for i.MX8MM
>>    imx: add i.MX8MM PE property
>>    imx8m: Fix MMU table issue for OPTEE memory
>>    imx8m: set BYPASS ID SWAP to avoid AXI bus errors
>>    imx8m: soc: enable SCTR clock before timer init
>>    serial: Kconfig: make MXC_UART usable for MX7 and IMX8M
>>    clk: imx: add Kconfig entry for i.MX8MM
>>    clk: imx: add pll14xx driver
>>    clk: add composite clk support
>>    clk: imx: add i.MX8MM composite clk support
>>    clk: imx: add i.MX8MM clk driver
>>    imx: add i.MX8MM EVK board support
>>
>> Ye Li (1):
>>    imx8m: Configure trustzone region 0 for non-secure access
>>
>>   arch/arm/dts/Makefile                              |    3 +-
>>   arch/arm/dts/imx8mm-evk-u-boot.dtsi                |   92 +
>>   arch/arm/dts/imx8mm-evk.dts                        |  235 +++
>>   arch/arm/dts/imx8mm-pinfunc.h                      |  629 +++++++
>>   arch/arm/dts/imx8mm.dtsi                           |  733 ++++++++
>>   arch/arm/include/asm/arch-imx/cpu.h                |    6 +
>>   arch/arm/include/asm/arch-imx8m/clock.h            |  493 +----
>>   arch/arm/include/asm/arch-imx8m/clock_imx8mm.h     |  387 ++++
>>   arch/arm/include/asm/arch-imx8m/clock_imx8mq.h     |  424 +++++
>>   arch/arm/include/asm/arch-imx8m/imx-regs.h         |   75 +-
>>   arch/arm/include/asm/arch-imx8m/imx8mm_pins.h      |  691 +++++++
>>   arch/arm/include/asm/mach-imx/iomux-v3.h           |    4 +
>>   arch/arm/include/asm/mach-imx/sys_proto.h          |    8 +
>>   arch/arm/mach-imx/cpu.c                            |   12 +
>>   arch/arm/mach-imx/imx8m/Kconfig                    |   17 +-
>>   arch/arm/mach-imx/imx8m/Makefile                   |    4 +-
>>   arch/arm/mach-imx/imx8m/clock_imx8mm.c             |  292 +++
>>   .../arm/mach-imx/imx8m/{clock.c => clock_imx8mq.c} |    5 +-
>>   arch/arm/mach-imx/imx8m/clock_slice.c              |  461 +++++
>>   arch/arm/mach-imx/imx8m/soc.c                      |  112 +-
>>   arch/arm/mach-imx/spl.c                            |    8 +
>>   board/freescale/imx8mm_evk/Kconfig                 |   12 +
>>   board/freescale/imx8mm_evk/MAINTAINERS             |    6 +
>>   board/freescale/imx8mm_evk/Makefile                |   12 +
>>   board/freescale/imx8mm_evk/imx8mm_evk.c            |   90 +
>>   board/freescale/imx8mm_evk/lpddr4_timing.c         | 1980 
>> ++++++++++++++++++++
>>   board/freescale/imx8mm_evk/spl.c                   |  216 +++
>>   cmd/clk.c                                          |    2 +
>>   configs/imx8mm_evk_defconfig                       |   52 +
>>   drivers/clk/Kconfig                                |   14 +
>>   drivers/clk/Makefile                               |    3 +-
>>   drivers/clk/clk-composite.c                        |  165 ++
>>   drivers/clk/clk-divider.c                          |   92 +-
>>   drivers/clk/clk-fixed-factor.c                     |    2 +-
>>   drivers/clk/clk-gate.c                             |  151 ++
>>   drivers/clk/clk-mux.c                              |   76 +-
>>   drivers/clk/clk.c                                  |    8 +
>>   drivers/clk/clk_fixed_rate.c                       |    9 +-
>>   drivers/clk/imx/Kconfig                            |    9 +
>>   drivers/clk/imx/Makefile                           |    1 +
>>   drivers/clk/imx/clk-composite-8m.c                 |  170 ++
>>   drivers/clk/imx/clk-gate2.c                        |   15 +-
>>   drivers/clk/imx/clk-imx8mm.c                       |  415 ++++
>>   drivers/clk/imx/clk-pfd.c                          |    2 +-
>>   drivers/clk/imx/clk-pll14xx.c                      |  377 ++++
>>   drivers/clk/imx/clk-pllv3.c                        |    2 +-
>>   drivers/clk/imx/clk.h                              |  106 ++
>>   drivers/core/uclass.c                              |    2 +-
>>   drivers/ddr/imx/imx8m/helper.c                     |   12 +-
>>   drivers/serial/Kconfig                             |    2 +-
>>   include/clk.h                                      |    9 +
>>   include/configs/imx8mm_evk.h                       |  199 ++
>>   include/dt-bindings/clock/imx8mm-clock.h           |  244 +++
>>   include/linux/clk-provider.h                       |   74 +
>>   include/linux/compat.h                             |    2 +
>>   55 files changed, 8728 insertions(+), 494 deletions(-)
>>   create mode 100644 arch/arm/dts/imx8mm-evk-u-boot.dtsi
>>   create mode 100644 arch/arm/dts/imx8mm-evk.dts
>>   create mode 100644 arch/arm/dts/imx8mm-pinfunc.h
>>   create mode 100644 arch/arm/dts/imx8mm.dtsi
>>   create mode 100644 arch/arm/include/asm/arch-imx8m/clock_imx8mm.h
>>   create mode 100644 arch/arm/include/asm/arch-imx8m/clock_imx8mq.h
>>   create mode 100644 arch/arm/include/asm/arch-imx8m/imx8mm_pins.h
>>   create mode 100644 arch/arm/mach-imx/imx8m/clock_imx8mm.c
>>   rename arch/arm/mach-imx/imx8m/{clock.c => clock_imx8mq.c} (99%)
>>   create mode 100644 board/freescale/imx8mm_evk/Kconfig
>>   create mode 100644 board/freescale/imx8mm_evk/MAINTAINERS
>>   create mode 100644 board/freescale/imx8mm_evk/Makefile
>>   create mode 100644 board/freescale/imx8mm_evk/imx8mm_evk.c
>>   create mode 100644 board/freescale/imx8mm_evk/lpddr4_timing.c
>>   create mode 100644 board/freescale/imx8mm_evk/spl.c
>>   create mode 100644 configs/imx8mm_evk_defconfig
>>   create mode 100644 drivers/clk/clk-composite.c
>>   create mode 100644 drivers/clk/clk-gate.c
>>   create mode 100644 drivers/clk/imx/clk-composite-8m.c
>>   create mode 100644 drivers/clk/imx/clk-imx8mm.c
>>   create mode 100644 drivers/clk/imx/clk-pll14xx.c
>>   create mode 100644 include/configs/imx8mm_evk.h
>>   create mode 100644 include/dt-bindings/clock/imx8mm-clock.h
>>

[U-Boot] [i.MX8MM+CCF 00/41] i.MX8MM + CCF

[Peng Fan]

Hi Frieder,

> Subject: Re: [U-Boot] [i.MX8MM+CCF 00/41] i.MX8MM + CCF
> 
> On 06.05.19 09:57, Frieder Schrempf wrote:
> > Hi Peng,
> >
> > I'm trying to add support for a board with i.MX8MM. First I applied
> > Lukasz's CCF patches and your patches to U-Boot 2019.04 and tried to
> > build imx8mm_evk config. But I'm getting build errors (see below).

Thanks for trying. There was no build error, might be some new change,
I'll fix that in new version patchset.

> 
> The build works if I enable the OTP fuse driver and disable I2C support.
> In clock_imx8mm.c enable_i2c_clk() seems to be missing, or maybe the i2c
> driver needs to use the new clock framework now?

I have the i2c mxc driver adapted to this new framework, clock is ok, but i2c probe
not work as expected, I am still trying to find out what's wrong.

> 
> >
> > Are there any other patches needed?
> > What things are still missing to get i.MX8MM running in U-Boot?
> 
> It seems like this still needs a bit of work. I also see some CONFIG options
> defined in the headers, that should be moved to defconfig.

I'll clean up those in new version. Since this patchset depends on Lukasz's CCF,
so I expect Lukasz's new version patchset, then I'll post new version.

Lukasz,

There are a few CCF fixes that need you to check, or you could take those into
your patches.

Thanks,
Peng.

> 
> >
> > Thanks,
> > Frieder
> >
> > | aarch64-ktn-linux-ld.bfd: cmd/built-in.o: in function `do_fuse':
> > | /home/frieder/repos/u-boot/cmd/fuse.c:68: undefined reference to
> > `fuse_read'
> > | aarch64-ktn-linux-ld.bfd: /home/frieder/repos/u-boot/cmd/fuse.c:86:
> > undefined reference to `fuse_sense'
> > | aarch64-ktn-linux-ld.bfd: /home/frieder/repos/u-boot/cmd/fuse.c:105:
> > undefined reference to `fuse_prog'
> > | aarch64-ktn-linux-ld.bfd: /home/frieder/repos/u-boot/cmd/fuse.c:119:
> > undefined reference to `fuse_override'
> > | aarch64-ktn-linux-ld.bfd: drivers/i2c/built-in.o: in function
> > `mxc_i2c_probe':
> > | /home/frieder/repos/u-boot/drivers/i2c/mxc_i2c.c:824: undefined
> > reference to `enable_i2c_clk'
> > | aarch64-ktn-linux-ld.bfd:
> > /home/frieder/repos/u-boot/drivers/i2c/mxc_i2c.c:853: undefined
> > reference to `enable_i2c_clk'
> >
> >
> > On 30.04.19 12:17, Peng Fan wrote:
> >> This patch set is based Lukasz V3 CCF patchset, [PATCH v3 00/11] clk:
> >> Port Linux common clock framework [CCF] to U-boot (tag: 5.0-rc3)
> >> https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgit
> >>
> hub.com%2Flmajewski%2Fu-boot-dfu%2Fcommits%2FCCF-v3&data=02
> %7C01%
> >>
> 7Cpeng.fan%40nxp.com%7C92e3d4126a6a485ca3e808d6d1fc8fcb%7C686ea
> 1d3bc2
> >>
> b4c6fa92cd99c5c301635%7C0%7C0%7C636927280011703542&sdata=
> 5hIVJtM6
> >> PZOy2o3NywWIrI7Ogmgjjz%2B92S1tdFTmTso%3D&reserved=0
> >>
> >> Added a few fixes to Lukasz's v3 patchset.
> >> Introduced clk-gate/composite
> >> Added set rate support
> >> Per my understanding, U-Boot CCF will not support mux reparent, and
> >> support rate prograte setting to parent automatically. So new clk
> >> feature added follow this rule.
> >>
> >> There are many warnings when importing linux ccf code, I did not
> >> modify them all.
> >>
> >> The rest patches are for i.MX8MM, part of legacy clk code are still
> >> kept, because we are hard to enable CCF at very early stage, we set
> >> malloc space to DRAM when dram initialized in spl stage, so we have
> >> limited SRAM for uclass dm and dm clk, so keep the DRAM PLL related
> >> setting with legacy clk code which use small ram.
> >>
> >> The u-boot-spl.bin now is about 100KB without ddr firmware,usb stack
> >> and hab, so really large......
> >> I am thinking what we could do to shrink the size, welcome any
> >> suggestions.
> >>
> >> Not expect this patchset could be merged, because of the CCF/clock
> >> code change, but since the clock part blocks i.MX8MM upstream, just
> >> would like to speed up the development with community and move on.
> >>
> >> Peng Fan (40):
> >>    clk: correct get clk_x pointer
> >>    clk: fixed-factor: fix get clk_fixed_factor
> >>    clk: introduce clk_dev_binded
> >>    clk: use clk_dev_binded
> >>    clk-provider: sync more clk flags from Linux Kernel
> >>    cmd: clk: print err value when clk_get_rate failed
> >>    clk: mux: add set parent support
> >>    clk: export mux/divider ops
> >>    clk: add clk-gate support
> >>    divider set rate supporrt
> >>    clk: fixed_rate: export clk_fixed_rate
> >>    clk: fixed_rate: add pre reloc flag
> >>    clk: imx: import clk heplers
> >>    clk: imx: gate2 add set rate
> >>    linux: compat: guard PAGE_SIZE
> >>    drivers: core: use strcmp when find device by name
> >>    ddr: imx8m: fix ddr firmware location when enable SPL OF
> >>    imx: add IMX8MQ kconfig entry
> >>    imx: add IMX8MM kconfig entry
> >>    imx: imx8mm: add clock bindings header
> >>    imx: add i.MX8MM cpu type
> >>    imx: spl: add spl_board_boot_device for i.MX8MM
> >>    imx8m: update imx-regs for i.MX8MM
> >>    imx: add get_cpu_rev support for i.MX8MM
> >>    imx8m: rename clock to clock_imx8mq
> >>    imx8m: restructure clock.h
> >>    imx8m: add clk support for i.MX8MM
> >>    imx8m: soc: probe clk before relocation
> >>    imx8m: add pin header for i.MX8MM
> >>    imx: add i.MX8MM PE property
> >>    imx8m: Fix MMU table issue for OPTEE memory
> >>    imx8m: set BYPASS ID SWAP to avoid AXI bus errors
> >>    imx8m: soc: enable SCTR clock before timer init
> >>    serial: Kconfig: make MXC_UART usable for MX7 and IMX8M
> >>    clk: imx: add Kconfig entry for i.MX8MM
> >>    clk: imx: add pll14xx driver
> >>    clk: add composite clk support
> >>    clk: imx: add i.MX8MM composite clk support
> >>    clk: imx: add i.MX8MM clk driver
> >>    imx: add i.MX8MM EVK board support
> >>
> >> Ye Li (1):
> >>    imx8m: Configure trustzone region 0 for non-secure access
> >>
> >>   arch/arm/dts/Makefile                              |
>    3 +-
> >>   arch/arm/dts/imx8mm-evk-u-boot.dtsi                |   92
> +
> >>   arch/arm/dts/imx8mm-evk.dts                        |
>  235 +++
> >>   arch/arm/dts/imx8mm-pinfunc.h                      |
> 629 +++++++
> >>   arch/arm/dts/imx8mm.dtsi                           |
>  733 ++++++++
> >>   arch/arm/include/asm/arch-imx/cpu.h                |
> 6 +
> >>   arch/arm/include/asm/arch-imx8m/clock.h            |  493
> +----
> >>   arch/arm/include/asm/arch-imx8m/clock_imx8mm.h     |  387
> ++++
> >>   arch/arm/include/asm/arch-imx8m/clock_imx8mq.h     |  424
> +++++
> >>   arch/arm/include/asm/arch-imx8m/imx-regs.h         |   75 +-
> >>   arch/arm/include/asm/arch-imx8m/imx8mm_pins.h      |  691
> +++++++
> >>   arch/arm/include/asm/mach-imx/iomux-v3.h           |    4
> +
> >>   arch/arm/include/asm/mach-imx/sys_proto.h          |    8 +
> >>   arch/arm/mach-imx/cpu.c                            |
>    12 +
> >>   arch/arm/mach-imx/imx8m/Kconfig                    |
>  17 +-
> >>   arch/arm/mach-imx/imx8m/Makefile                   |
>   4 +-
> >>   arch/arm/mach-imx/imx8m/clock_imx8mm.c             |  2
> 92 +++
> >>   .../arm/mach-imx/imx8m/{clock.c => clock_imx8mq.c} |    5 +-
> >>   arch/arm/mach-imx/imx8m/clock_slice.c              |  461
> +++++
> >>   arch/arm/mach-imx/imx8m/soc.c                      |
>  112 +-
> >>   arch/arm/mach-imx/spl.c                            |
>    8 +
> >>   board/freescale/imx8mm_evk/Kconfig                 |   1
> 2 +
> >>   board/freescale/imx8mm_evk/MAINTAINERS             |
>  6 +
> >>   board/freescale/imx8mm_evk/Makefile                |   1
> 2 +
> >>   board/freescale/imx8mm_evk/imx8mm_evk.c            |   9
> 0 +
> >>   board/freescale/imx8mm_evk/lpddr4_timing.c         | 1980
> >> ++++++++++++++++++++
> >>   board/freescale/imx8mm_evk/spl.c                   |  21
> 6 +++
> >>   cmd/clk.c
>   |    2 +
> >>   configs/imx8mm_evk_defconfig                       |
>  52 +
> >>   drivers/clk/Kconfig                                |
>  14 +
> >>   drivers/clk/Makefile                               |
>    3 +-
> >>   drivers/clk/clk-composite.c                        |  165
> ++
> >>   drivers/clk/clk-divider.c                          |   92
> +-
> >>   drivers/clk/clk-fixed-factor.c                     |    2 +-
> >>   drivers/clk/clk-gate.c                             |  1
> 51 ++
> >>   drivers/clk/clk-mux.c                              |
>  76 +-
> >>   drivers/clk/clk.c                                  |
>    8 +
> >>   drivers/clk/clk_fixed_rate.c                       |    9
> +-
> >>   drivers/clk/imx/Kconfig                            |
>  9 +
> >>   drivers/clk/imx/Makefile                           |
>   1 +
> >>   drivers/clk/imx/clk-composite-8m.c                 |  170
> ++
> >>   drivers/clk/imx/clk-gate2.c                        |   15
> +-
> >>   drivers/clk/imx/clk-imx8mm.c                       |  4
> 15 ++++
> >>   drivers/clk/imx/clk-pfd.c                          |
> 2 +-
> >>   drivers/clk/imx/clk-pll14xx.c                      |  377
> ++++
> >>   drivers/clk/imx/clk-pllv3.c                        |    2
> +-
> >>   drivers/clk/imx/clk.h                              |
> 106 ++
> >>   drivers/core/uclass.c                              |
>   2 +-
> >>   drivers/ddr/imx/imx8m/helper.c                     |   1
> 2 +-
> >>   drivers/serial/Kconfig                             |
>  2 +-
> >>   include/clk.h
> |    9 +
> >>   include/configs/imx8mm_evk.h                       |  1
> 99 ++
> >>   include/dt-bindings/clock/imx8mm-clock.h           |  244
> +++
> >>   include/linux/clk-provider.h                       |   74
> +
> >>   include/linux/compat.h                             |
>   2 +
> >>   55 files changed, 8728 insertions(+), 494 deletions(-)
> >>   create mode 100644 arch/arm/dts/imx8mm-evk-u-boot.dtsi
> >>   create mode 100644 arch/arm/dts/imx8mm-evk.dts
> >>   create mode 100644 arch/arm/dts/imx8mm-pinfunc.h
> >>   create mode 100644 arch/arm/dts/imx8mm.dtsi
> >>   create mode 100644
> arch/arm/include/asm/arch-imx8m/clock_imx8mm.h
> >>   create mode 100644
> arch/arm/include/asm/arch-imx8m/clock_imx8mq.h
> >>   create mode 100644
> arch/arm/include/asm/arch-imx8m/imx8mm_pins.h
> >>   create mode 100644 arch/arm/mach-imx/imx8m/clock_imx8mm.c
> >>   rename arch/arm/mach-imx/imx8m/{clock.c => clock_imx8mq.c}
> (99%)
> >>   create mode 100644 board/freescale/imx8mm_evk/Kconfig
> >>   create mode 100644 board/freescale/imx8mm_evk/MAINTAINERS
> >>   create mode 100644 board/freescale/imx8mm_evk/Makefile
> >>   create mode 100644 board/freescale/imx8mm_evk/imx8mm_evk.c
> >>   create mode 100644 board/freescale/imx8mm_evk/lpddr4_timing.c
> >>   create mode 100644 board/freescale/imx8mm_evk/spl.c
> >>   create mode 100644 configs/imx8mm_evk_defconfig
> >>   create mode 100644 drivers/clk/clk-composite.c
> >>   create mode 100644 drivers/clk/clk-gate.c
> >>   create mode 100644 drivers/clk/imx/clk-composite-8m.c
> >>   create mode 100644 drivers/clk/imx/clk-imx8mm.c
> >>   create mode 100644 drivers/clk/imx/clk-pll14xx.c
> >>   create mode 100644 include/configs/imx8mm_evk.h
> >>   create mode 100644 include/dt-bindings/clock/imx8mm-clock.h
> >>

[U-Boot] [i.MX8MM+CCF 00/41] i.MX8MM + CCF

[Lukasz Majewski]

On Mon, 6 May 2019 09:08:46 +0000
Peng Fan <peng.fan@nxp.com> wrote:

> Hi Frieder,
> 
> > Subject: Re: [U-Boot] [i.MX8MM+CCF 00/41] i.MX8MM + CCF
> > 
> > On 06.05.19 09:57, Frieder Schrempf wrote:  
> > > Hi Peng,
> > >
> > > I'm trying to add support for a board with i.MX8MM. First I
> > > applied Lukasz's CCF patches and your patches to U-Boot 2019.04
> > > and tried to build imx8mm_evk config. But I'm getting build
> > > errors (see below).  
> 
> Thanks for trying. There was no build error, might be some new change,
> I'll fix that in new version patchset.
> 
> > 
> > The build works if I enable the OTP fuse driver and disable I2C
> > support. In clock_imx8mm.c enable_i2c_clk() seems to be missing, or
> > maybe the i2c driver needs to use the new clock framework now?  
> 
> I have the i2c mxc driver adapted to this new framework, clock is ok,
> but i2c probe not work as expected, I am still trying to find out
> what's wrong.
> 
> >   
> > >
> > > Are there any other patches needed?
> > > What things are still missing to get i.MX8MM running in U-Boot?  
> > 
> > It seems like this still needs a bit of work. I also see some
> > CONFIG options defined in the headers, that should be moved to
> > defconfig.  
> 
> I'll clean up those in new version. Since this patchset depends on
> Lukasz's CCF, so I expect Lukasz's new version patchset, then I'll
> post new version.
> 
> Lukasz,
> 
> There are a few CCF fixes that need you to check, or you could take
> those into your patches.

Till the end of today I will review your patches. As I did not received
any more feedback regarding last posted patches - I will add the cached
clock stuff and repost them.

(I'm out of office from 09.05 - 14.05, so I want to repost my patches
by then to not block the development).

> 
> Thanks,
> Peng.
> 
> >   
> > >
> > > Thanks,
> > > Frieder
> > >
> > > | aarch64-ktn-linux-ld.bfd: cmd/built-in.o: in function `do_fuse':
> > > | /home/frieder/repos/u-boot/cmd/fuse.c:68: undefined reference to
> > > `fuse_read'
> > > |
> > > aarch64-ktn-linux-ld.bfd: /home/frieder/repos/u-boot/cmd/fuse.c:86:
> > > undefined reference to `fuse_sense' |
> > > aarch64-ktn-linux-ld.bfd: /home/frieder/repos/u-boot/cmd/fuse.c:105:
> > > undefined reference to `fuse_prog' |
> > > aarch64-ktn-linux-ld.bfd: /home/frieder/repos/u-boot/cmd/fuse.c:119:
> > > undefined reference to `fuse_override' |
> > > aarch64-ktn-linux-ld.bfd: drivers/i2c/built-in.o: in function
> > > `mxc_i2c_probe':
> > > | /home/frieder/repos/u-boot/drivers/i2c/mxc_i2c.c:824: undefined
> > > reference to `enable_i2c_clk' | aarch64-ktn-linux-ld.bfd:
> > > /home/frieder/repos/u-boot/drivers/i2c/mxc_i2c.c:853: undefined
> > > reference to `enable_i2c_clk'
> > >
> > >
> > > On 30.04.19 12:17, Peng Fan wrote:  
> > >> This patch set is based Lukasz V3 CCF patchset, [PATCH v3 00/11]
> > >> clk: Port Linux common clock framework [CCF] to U-boot (tag:
> > >> 5.0-rc3)
> > >> https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgit 
> > hub.com%2Flmajewski%2Fu-boot-dfu%2Fcommits%2FCCF-v3&amp;data=02
> > %7C01%  
> > >>  
> > 7Cpeng.fan%40nxp.com%7C92e3d4126a6a485ca3e808d6d1fc8fcb%7C686ea
> > 1d3bc2  
> > >>  
> > b4c6fa92cd99c5c301635%7C0%7C0%7C636927280011703542&amp;sdata=
> > 5hIVJtM6  
> > >> PZOy2o3NywWIrI7Ogmgjjz%2B92S1tdFTmTso%3D&amp;reserved=0
> > >>
> > >> Added a few fixes to Lukasz's v3 patchset.
> > >> Introduced clk-gate/composite
> > >> Added set rate support
> > >> Per my understanding, U-Boot CCF will not support mux reparent,
> > >> and support rate prograte setting to parent automatically. So
> > >> new clk feature added follow this rule.
> > >>
> > >> There are many warnings when importing linux ccf code, I did not
> > >> modify them all.
> > >>
> > >> The rest patches are for i.MX8MM, part of legacy clk code are
> > >> still kept, because we are hard to enable CCF at very early
> > >> stage, we set malloc space to DRAM when dram initialized in spl
> > >> stage, so we have limited SRAM for uclass dm and dm clk, so keep
> > >> the DRAM PLL related setting with legacy clk code which use
> > >> small ram.
> > >>
> > >> The u-boot-spl.bin now is about 100KB without ddr firmware,usb
> > >> stack and hab, so really large......
> > >> I am thinking what we could do to shrink the size, welcome any
> > >> suggestions.
> > >>
> > >> Not expect this patchset could be merged, because of the
> > >> CCF/clock code change, but since the clock part blocks i.MX8MM
> > >> upstream, just would like to speed up the development with
> > >> community and move on.
> > >>
> > >> Peng Fan (40):
> > >>    clk: correct get clk_x pointer
> > >>    clk: fixed-factor: fix get clk_fixed_factor
> > >>    clk: introduce clk_dev_binded
> > >>    clk: use clk_dev_binded
> > >>    clk-provider: sync more clk flags from Linux Kernel
> > >>    cmd: clk: print err value when clk_get_rate failed
> > >>    clk: mux: add set parent support
> > >>    clk: export mux/divider ops
> > >>    clk: add clk-gate support
> > >>    divider set rate supporrt
> > >>    clk: fixed_rate: export clk_fixed_rate
> > >>    clk: fixed_rate: add pre reloc flag
> > >>    clk: imx: import clk heplers
> > >>    clk: imx: gate2 add set rate
> > >>    linux: compat: guard PAGE_SIZE
> > >>    drivers: core: use strcmp when find device by name
> > >>    ddr: imx8m: fix ddr firmware location when enable SPL OF
> > >>    imx: add IMX8MQ kconfig entry
> > >>    imx: add IMX8MM kconfig entry
> > >>    imx: imx8mm: add clock bindings header
> > >>    imx: add i.MX8MM cpu type
> > >>    imx: spl: add spl_board_boot_device for i.MX8MM
> > >>    imx8m: update imx-regs for i.MX8MM
> > >>    imx: add get_cpu_rev support for i.MX8MM
> > >>    imx8m: rename clock to clock_imx8mq
> > >>    imx8m: restructure clock.h
> > >>    imx8m: add clk support for i.MX8MM
> > >>    imx8m: soc: probe clk before relocation
> > >>    imx8m: add pin header for i.MX8MM
> > >>    imx: add i.MX8MM PE property
> > >>    imx8m: Fix MMU table issue for OPTEE memory
> > >>    imx8m: set BYPASS ID SWAP to avoid AXI bus errors
> > >>    imx8m: soc: enable SCTR clock before timer init
> > >>    serial: Kconfig: make MXC_UART usable for MX7 and IMX8M
> > >>    clk: imx: add Kconfig entry for i.MX8MM
> > >>    clk: imx: add pll14xx driver
> > >>    clk: add composite clk support
> > >>    clk: imx: add i.MX8MM composite clk support
> > >>    clk: imx: add i.MX8MM clk driver
> > >>    imx: add i.MX8MM EVK board support
> > >>
> > >> Ye Li (1):
> > >>    imx8m: Configure trustzone region 0 for non-secure access
> > >>
> > >>   arch/arm/dts/Makefile                              |  
> >    3 +-  
> > >>   arch/arm/dts/imx8mm-evk-u-boot.dtsi                |   92  
> > +  
> > >>   arch/arm/dts/imx8mm-evk.dts                        |  
> >  235 +++  
> > >>   arch/arm/dts/imx8mm-pinfunc.h                      |  
> > 629 +++++++  
> > >>   arch/arm/dts/imx8mm.dtsi                           |  
> >  733 ++++++++  
> > >>   arch/arm/include/asm/arch-imx/cpu.h                |  
> > 6 +  
> > >>   arch/arm/include/asm/arch-imx8m/clock.h            |  493  
> > +----  
> > >>   arch/arm/include/asm/arch-imx8m/clock_imx8mm.h     |  387  
> > ++++  
> > >>   arch/arm/include/asm/arch-imx8m/clock_imx8mq.h     |  424  
> > +++++  
> > >>   arch/arm/include/asm/arch-imx8m/imx-regs.h         |   75 +-
> > >>   arch/arm/include/asm/arch-imx8m/imx8mm_pins.h      |  691  
> > +++++++  
> > >>   arch/arm/include/asm/mach-imx/iomux-v3.h           |    4  
> > +  
> > >>   arch/arm/include/asm/mach-imx/sys_proto.h          |    8 +
> > >>   arch/arm/mach-imx/cpu.c                            |  
> >    12 +  
> > >>   arch/arm/mach-imx/imx8m/Kconfig                    |  
> >  17 +-  
> > >>   arch/arm/mach-imx/imx8m/Makefile                   |  
> >   4 +-  
> > >>   arch/arm/mach-imx/imx8m/clock_imx8mm.c             |  2  
> > 92 +++  
> > >>   .../arm/mach-imx/imx8m/{clock.c => clock_imx8mq.c} |    5 +-
> > >>   arch/arm/mach-imx/imx8m/clock_slice.c              |  461  
> > +++++  
> > >>   arch/arm/mach-imx/imx8m/soc.c                      |  
> >  112 +-  
> > >>   arch/arm/mach-imx/spl.c                            |  
> >    8 +  
> > >>   board/freescale/imx8mm_evk/Kconfig                 |   1  
> > 2 +  
> > >>   board/freescale/imx8mm_evk/MAINTAINERS             |  
> >  6 +  
> > >>   board/freescale/imx8mm_evk/Makefile                |   1  
> > 2 +  
> > >>   board/freescale/imx8mm_evk/imx8mm_evk.c            |   9  
> > 0 +  
> > >>   board/freescale/imx8mm_evk/lpddr4_timing.c         | 1980
> > >> ++++++++++++++++++++
> > >>   board/freescale/imx8mm_evk/spl.c                   |  21  
> > 6 +++  
> > >>   cmd/clk.c  
> >   |    2 +  
> > >>   configs/imx8mm_evk_defconfig                       |  
> >  52 +  
> > >>   drivers/clk/Kconfig                                |  
> >  14 +  
> > >>   drivers/clk/Makefile                               |  
> >    3 +-  
> > >>   drivers/clk/clk-composite.c                        |  165  
> > ++  
> > >>   drivers/clk/clk-divider.c                          |   92  
> > +-  
> > >>   drivers/clk/clk-fixed-factor.c                     |    2 +-
> > >>   drivers/clk/clk-gate.c                             |  1  
> > 51 ++  
> > >>   drivers/clk/clk-mux.c                              |  
> >  76 +-  
> > >>   drivers/clk/clk.c                                  |  
> >    8 +  
> > >>   drivers/clk/clk_fixed_rate.c                       |    9  
> > +-  
> > >>   drivers/clk/imx/Kconfig                            |  
> >  9 +  
> > >>   drivers/clk/imx/Makefile                           |  
> >   1 +  
> > >>   drivers/clk/imx/clk-composite-8m.c                 |  170  
> > ++  
> > >>   drivers/clk/imx/clk-gate2.c                        |   15  
> > +-  
> > >>   drivers/clk/imx/clk-imx8mm.c                       |  4  
> > 15 ++++  
> > >>   drivers/clk/imx/clk-pfd.c                          |  
> > 2 +-  
> > >>   drivers/clk/imx/clk-pll14xx.c                      |  377  
> > ++++  
> > >>   drivers/clk/imx/clk-pllv3.c                        |    2  
> > +-  
> > >>   drivers/clk/imx/clk.h                              |  
> > 106 ++  
> > >>   drivers/core/uclass.c                              |  
> >   2 +-  
> > >>   drivers/ddr/imx/imx8m/helper.c                     |   1  
> > 2 +-  
> > >>   drivers/serial/Kconfig                             |  
> >  2 +-  
> > >>   include/clk.h  
> > |    9 +  
> > >>   include/configs/imx8mm_evk.h                       |  1  
> > 99 ++  
> > >>   include/dt-bindings/clock/imx8mm-clock.h           |  244  
> > +++  
> > >>   include/linux/clk-provider.h                       |   74  
> > +  
> > >>   include/linux/compat.h                             |  
> >   2 +  
> > >>   55 files changed, 8728 insertions(+), 494 deletions(-)
> > >>   create mode 100644 arch/arm/dts/imx8mm-evk-u-boot.dtsi
> > >>   create mode 100644 arch/arm/dts/imx8mm-evk.dts
> > >>   create mode 100644 arch/arm/dts/imx8mm-pinfunc.h
> > >>   create mode 100644 arch/arm/dts/imx8mm.dtsi
> > >>   create mode 100644  
> > arch/arm/include/asm/arch-imx8m/clock_imx8mm.h  
> > >>   create mode 100644  
> > arch/arm/include/asm/arch-imx8m/clock_imx8mq.h  
> > >>   create mode 100644  
> > arch/arm/include/asm/arch-imx8m/imx8mm_pins.h  
> > >>   create mode 100644 arch/arm/mach-imx/imx8m/clock_imx8mm.c
> > >>   rename arch/arm/mach-imx/imx8m/{clock.c => clock_imx8mq.c}  
> > (99%)  
> > >>   create mode 100644 board/freescale/imx8mm_evk/Kconfig
> > >>   create mode 100644 board/freescale/imx8mm_evk/MAINTAINERS
> > >>   create mode 100644 board/freescale/imx8mm_evk/Makefile
> > >>   create mode 100644 board/freescale/imx8mm_evk/imx8mm_evk.c
> > >>   create mode 100644 board/freescale/imx8mm_evk/lpddr4_timing.c
> > >>   create mode 100644 board/freescale/imx8mm_evk/spl.c
> > >>   create mode 100644 configs/imx8mm_evk_defconfig
> > >>   create mode 100644 drivers/clk/clk-composite.c
> > >>   create mode 100644 drivers/clk/clk-gate.c
> > >>   create mode 100644 drivers/clk/imx/clk-composite-8m.c
> > >>   create mode 100644 drivers/clk/imx/clk-imx8mm.c
> > >>   create mode 100644 drivers/clk/imx/clk-pll14xx.c
> > >>   create mode 100644 include/configs/imx8mm_evk.h
> > >>   create mode 100644 include/dt-bindings/clock/imx8mm-clock.h
> > >>  




Best regards,

Lukasz Majewski

--

DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email: lukma at denx.de
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[U-Boot] [i.MX8MM+CCF 00/41] i.MX8MM + CCF

[Lukasz Majewski]

Hi Peng,

> This patch set is based Lukasz V3 CCF patchset,
> [PATCH v3 00/11] clk: Port Linux common clock framework [CCF] to
> U-boot (tag: 5.0-rc3)
> https://github.com/lmajewski/u-boot-dfu/commits/CCF-v3
> 
> Added a few fixes to Lukasz's v3 patchset.
> Introduced clk-gate/composite
> Added set rate support
> Per my understanding, U-Boot CCF will not support mux reparent, and
> support rate prograte setting to parent automatically. 

I think that we shall keep the code as small as possible and hence add
only necessary features (that is why my code only supports gating and
muxing for 'downstream' settings).

> So new clk
> feature added follow this rule.
> 
> There are many warnings when importing linux ccf code, I did not
> modify them all.

I've removed some not needed arguments (like spinlocks) when porting
the code.

> 
> The rest patches are for i.MX8MM, part of legacy clk code are still
> kept, because we are hard to enable CCF at very early stage,

Yes, CCF in SPL is a challenging task.

> we set
> malloc space to DRAM when dram initialized in spl stage, so we have
> limited SRAM for uclass dm and dm clk,

I'm puzzled about this sentence. The malloc is set to be in DRAM, but
also SRAM is used for uclass dm and CCF.

As fair as I remember on iMX6Q it is possible to setup early malloc to
be in SRAM (OCRAM). Having it in DRAM is a bit late, IMHO as clocks
are already setup in this moment.

> so keep the DRAM PLL related
> setting with legacy clk code which use small ram.

What is the 'ram' ? I suppose that the legacy clk code uses OCRAM to
allocate variables ? 

> 
> The u-boot-spl.bin now is about 100KB without ddr firmware,usb stack
> and hab, so really large......

I think that 100KiB is too much (without DDR, USB stack and HAB). For
one IMX6Q setup (before DM/DTS conversion) I had SPL size ~30 KiB.

After the conversion it is 55 KiB ...

> I am thinking what we could do to shrink the size, welcome any
> suggestions.

Please consider using:

- TINY_PRINTF
- TINY_FIT support (just support for single image in FIT)
- OF_PLATDATA (the in-device-tree code is compiled in as C
  structures) - no need to include DTS parsing / handling code in SPL.
  Also the *.dts file is not needed.

  Drawback is that you need to extend drivers to support OF_PLATDATA
  (RK3399 have some examples of such approach).

- Check if thumb2 is uses for SPL compilation 
- I simply do find *.o files and sort them regarding the size. Then I
  do know where to start with optimisations.

> 
> Not expect this patchset could be merged, because of the CCF/clock
> code change, but since the clock part blocks i.MX8MM upstream, just
> would like to speed up the development with community and move on.
> 
> Peng Fan (40):
>   clk: correct get clk_x pointer
>   clk: fixed-factor: fix get clk_fixed_factor
>   clk: introduce clk_dev_binded
>   clk: use clk_dev_binded
>   clk-provider: sync more clk flags from Linux Kernel
>   cmd: clk: print err value when clk_get_rate failed
>   clk: mux: add set parent support
>   clk: export mux/divider ops
>   clk: add clk-gate support
>   divider set rate supporrt
>   clk: fixed_rate: export clk_fixed_rate
>   clk: fixed_rate: add pre reloc flag
>   clk: imx: import clk heplers
>   clk: imx: gate2 add set rate
>   linux: compat: guard PAGE_SIZE
>   drivers: core: use strcmp when find device by name
>   ddr: imx8m: fix ddr firmware location when enable SPL OF
>   imx: add IMX8MQ kconfig entry
>   imx: add IMX8MM kconfig entry
>   imx: imx8mm: add clock bindings header
>   imx: add i.MX8MM cpu type
>   imx: spl: add spl_board_boot_device for i.MX8MM
>   imx8m: update imx-regs for i.MX8MM
>   imx: add get_cpu_rev support for i.MX8MM
>   imx8m: rename clock to clock_imx8mq
>   imx8m: restructure clock.h
>   imx8m: add clk support for i.MX8MM
>   imx8m: soc: probe clk before relocation
>   imx8m: add pin header for i.MX8MM
>   imx: add i.MX8MM PE property
>   imx8m: Fix MMU table issue for OPTEE memory
>   imx8m: set BYPASS ID SWAP to avoid AXI bus errors
>   imx8m: soc: enable SCTR clock before timer init
>   serial: Kconfig: make MXC_UART usable for MX7 and IMX8M
>   clk: imx: add Kconfig entry for i.MX8MM
>   clk: imx: add pll14xx driver
>   clk: add composite clk support
>   clk: imx: add i.MX8MM composite clk support
>   clk: imx: add i.MX8MM clk driver
>   imx: add i.MX8MM EVK board support
> 
> Ye Li (1):
>   imx8m: Configure trustzone region 0 for non-secure access
> 
>  arch/arm/dts/Makefile                              |    3 +-
>  arch/arm/dts/imx8mm-evk-u-boot.dtsi                |   92 +
>  arch/arm/dts/imx8mm-evk.dts                        |  235 +++
>  arch/arm/dts/imx8mm-pinfunc.h                      |  629 +++++++
>  arch/arm/dts/imx8mm.dtsi                           |  733 ++++++++
>  arch/arm/include/asm/arch-imx/cpu.h                |    6 +
>  arch/arm/include/asm/arch-imx8m/clock.h            |  493 +----
>  arch/arm/include/asm/arch-imx8m/clock_imx8mm.h     |  387 ++++
>  arch/arm/include/asm/arch-imx8m/clock_imx8mq.h     |  424 +++++
>  arch/arm/include/asm/arch-imx8m/imx-regs.h         |   75 +-
>  arch/arm/include/asm/arch-imx8m/imx8mm_pins.h      |  691 +++++++
>  arch/arm/include/asm/mach-imx/iomux-v3.h           |    4 +
>  arch/arm/include/asm/mach-imx/sys_proto.h          |    8 +
>  arch/arm/mach-imx/cpu.c                            |   12 +
>  arch/arm/mach-imx/imx8m/Kconfig                    |   17 +-
>  arch/arm/mach-imx/imx8m/Makefile                   |    4 +-
>  arch/arm/mach-imx/imx8m/clock_imx8mm.c             |  292 +++
>  .../arm/mach-imx/imx8m/{clock.c => clock_imx8mq.c} |    5 +-
>  arch/arm/mach-imx/imx8m/clock_slice.c              |  461 +++++
>  arch/arm/mach-imx/imx8m/soc.c                      |  112 +-
>  arch/arm/mach-imx/spl.c                            |    8 +
>  board/freescale/imx8mm_evk/Kconfig                 |   12 +
>  board/freescale/imx8mm_evk/MAINTAINERS             |    6 +
>  board/freescale/imx8mm_evk/Makefile                |   12 +
>  board/freescale/imx8mm_evk/imx8mm_evk.c            |   90 +
>  board/freescale/imx8mm_evk/lpddr4_timing.c         | 1980
> ++++++++++++++++++++
> board/freescale/imx8mm_evk/spl.c                   |  216 +++
> cmd/clk.c                                          |    2 +
> configs/imx8mm_evk_defconfig                       |   52 +
> drivers/clk/Kconfig                                |   14 +
> drivers/clk/Makefile                               |    3 +-
> drivers/clk/clk-composite.c                        |  165 ++
> drivers/clk/clk-divider.c                          |   92 +-
> drivers/clk/clk-fixed-factor.c                     |    2 +-
> drivers/clk/clk-gate.c                             |  151 ++
> drivers/clk/clk-mux.c                              |   76 +-
> drivers/clk/clk.c                                  |    8 +
> drivers/clk/clk_fixed_rate.c                       |    9 +-
> drivers/clk/imx/Kconfig                            |    9 +
> drivers/clk/imx/Makefile                           |    1 +
> drivers/clk/imx/clk-composite-8m.c                 |  170 ++
> drivers/clk/imx/clk-gate2.c                        |   15 +-
> drivers/clk/imx/clk-imx8mm.c                       |  415 ++++
> drivers/clk/imx/clk-pfd.c                          |    2 +-
> drivers/clk/imx/clk-pll14xx.c                      |  377 ++++
> drivers/clk/imx/clk-pllv3.c                        |    2 +-
> drivers/clk/imx/clk.h                              |  106 ++
> drivers/core/uclass.c                              |    2 +-
> drivers/ddr/imx/imx8m/helper.c                     |   12 +-
> drivers/serial/Kconfig                             |    2 +-
> include/clk.h                                      |    9 +
> include/configs/imx8mm_evk.h                       |  199 ++
> include/dt-bindings/clock/imx8mm-clock.h           |  244 +++
> include/linux/clk-provider.h                       |   74 +
> include/linux/compat.h                             |    2 + 55 files
> changed, 8728 insertions(+), 494 deletions(-) create mode 100644
> arch/arm/dts/imx8mm-evk-u-boot.dtsi create mode 100644
> arch/arm/dts/imx8mm-evk.dts create mode 100644
> arch/arm/dts/imx8mm-pinfunc.h create mode 100644
> arch/arm/dts/imx8mm.dtsi create mode 100644
> arch/arm/include/asm/arch-imx8m/clock_imx8mm.h create mode 100644
> arch/arm/include/asm/arch-imx8m/clock_imx8mq.h create mode 100644
> arch/arm/include/asm/arch-imx8m/imx8mm_pins.h create mode 100644
> arch/arm/mach-imx/imx8m/clock_imx8mm.c rename
> arch/arm/mach-imx/imx8m/{clock.c => clock_imx8mq.c} (99%) create mode
> 100644 board/freescale/imx8mm_evk/Kconfig create mode 100644
> board/freescale/imx8mm_evk/MAINTAINERS create mode 100644
> board/freescale/imx8mm_evk/Makefile create mode 100644
> board/freescale/imx8mm_evk/imx8mm_evk.c create mode 100644
> board/freescale/imx8mm_evk/lpddr4_timing.c create mode 100644
> board/freescale/imx8mm_evk/spl.c create mode 100644
> configs/imx8mm_evk_defconfig create mode 100644
> drivers/clk/clk-composite.c create mode 100644 drivers/clk/clk-gate.c
>  create mode 100644 drivers/clk/imx/clk-composite-8m.c
>  create mode 100644 drivers/clk/imx/clk-imx8mm.c
>  create mode 100644 drivers/clk/imx/clk-pll14xx.c
>  create mode 100644 include/configs/imx8mm_evk.h
>  create mode 100644 include/dt-bindings/clock/imx8mm-clock.h
> 




Best regards,

Lukasz Majewski

--

DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email: lukma at denx.de
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[U-Boot] [i.MX8MM+CCF 01/41] clk: correct get clk_x pointer

[Lukasz Majewski]

Hi Peng,

> Directly use driver data is wrong, need to the helper to get
> the correct clk_divider and etc

I just followed the kernel approach.

This works as the address of first element of struct clk_XXX is always
struct clk clk address;

But yes, this may be the preferred (more readable) approach.

> 
> Signed-off-by: Peng Fan <peng.fan@nxp.com>
> ---
>  drivers/clk/clk-divider.c   | 2 +-
>  drivers/clk/imx/clk-gate2.c | 4 ++--
>  drivers/clk/imx/clk-pfd.c   | 2 +-
>  drivers/clk/imx/clk-pllv3.c | 2 +-
>  4 files changed, 5 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c
> index 3841d8bfbb..1d2c1b1ec4 100644
> --- a/drivers/clk/clk-divider.c
> +++ b/drivers/clk/clk-divider.c
> @@ -70,7 +70,7 @@ unsigned long divider_recalc_rate(struct clk *hw,
> unsigned long parent_rate, static ulong
> clk_divider_recalc_rate(struct clk *clk) {
>  	struct clk_divider *divider =
> -		(struct clk_divider *)dev_get_driver_data(clk->dev);
> +		to_clk_divider((struct clk
> *)dev_get_driver_data(clk->dev)); unsigned long parent_rate =
> clk_get_parent_rate(clk); unsigned int val;
>  
> diff --git a/drivers/clk/imx/clk-gate2.c b/drivers/clk/imx/clk-gate2.c
> index 1e53e4f9db..83589b9206 100644
> --- a/drivers/clk/imx/clk-gate2.c
> +++ b/drivers/clk/imx/clk-gate2.c
> @@ -38,7 +38,7 @@ struct clk_gate2 {
>  static int clk_gate2_enable(struct clk *clk)
>  {
>  	struct clk_gate2 *gate =
> -		(struct clk_gate2 *)dev_get_driver_data(clk->dev);
> +		to_clk_gate2((struct clk
> *)dev_get_driver_data(clk->dev)); u32 reg;
>  
>  	reg = readl(gate->reg);
> @@ -52,7 +52,7 @@ static int clk_gate2_enable(struct clk *clk)
>  static int clk_gate2_disable(struct clk *clk)
>  {
>  	struct clk_gate2 *gate =
> -		(struct clk_gate2 *)dev_get_driver_data(clk->dev);
> +		to_clk_gate2((struct clk
> *)dev_get_driver_data(clk->dev)); u32 reg;
>  
>  	reg = readl(gate->reg);
> diff --git a/drivers/clk/imx/clk-pfd.c b/drivers/clk/imx/clk-pfd.c
> index 2293d481d4..51521ccee6 100644
> --- a/drivers/clk/imx/clk-pfd.c
> +++ b/drivers/clk/imx/clk-pfd.c
> @@ -41,7 +41,7 @@ struct clk_pfd {
>  static unsigned long clk_pfd_recalc_rate(struct clk *clk)
>  {
>  	struct clk_pfd *pfd =
> -		(struct clk_pfd *)dev_get_driver_data(clk->dev);
> +		to_clk_pfd((struct clk
> *)dev_get_driver_data(clk->dev)); unsigned long parent_rate =
> clk_get_parent_rate(clk); u64 tmp = parent_rate;
>  	u8 frac = (readl(pfd->reg) >> (pfd->idx * 8)) & 0x3f;
> diff --git a/drivers/clk/imx/clk-pllv3.c b/drivers/clk/imx/clk-pllv3.c
> index 3fe9b7c03d..28c0439878 100644
> --- a/drivers/clk/imx/clk-pllv3.c
> +++ b/drivers/clk/imx/clk-pllv3.c
> @@ -27,7 +27,7 @@ struct clk_pllv3 {
>  static ulong clk_pllv3_get_rate(struct clk *clk)
>  {
>  	struct clk_pllv3 *pll =
> -		(struct clk_pllv3 *)dev_get_driver_data(clk->dev);
> +		to_clk_pllv3((struct clk
> *)dev_get_driver_data(clk->dev)); unsigned long parent_rate =
> clk_get_parent_rate(clk); 
>  	u32 div = (readl(pll->base) >> pll->div_shift) &
> pll->div_mask;


Best regards,

Lukasz Majewski

--

DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email: lukma at denx.de
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[U-Boot] [i.MX8MM+CCF 02/41] clk: fixed-factor: fix get clk_fixed_factor

[Lukasz Majewski]

On Tue, 30 Apr 2019 10:17:36 +0000
Peng Fan <peng.fan@nxp.com> wrote:

> driver data is not clk, not clk_fixed_factor, fix it.

This description is a bit misleading, IMHO.

The dev->driver_data holds pointer to corresponding struct clk clk
element (as described [1]).
 
This patch resembles changes from PATCH [1/42].

> 
> Signed-off-by: Peng Fan <peng.fan@nxp.com>
> ---
>  drivers/clk/clk-fixed-factor.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/clk/clk-fixed-factor.c
> b/drivers/clk/clk-fixed-factor.c index acbc0909b4..c535aadc48 100644
> --- a/drivers/clk/clk-fixed-factor.c
> +++ b/drivers/clk/clk-fixed-factor.c
> @@ -19,7 +19,7 @@
>  static ulong clk_factor_recalc_rate(struct clk *clk)
>  {
>  	struct clk_fixed_factor *fix =
> -		(struct clk_fixed_factor
> *)dev_get_driver_data(clk->dev);
> +		to_clk_fixed_factor((struct clk
> *)dev_get_driver_data(clk->dev)); unsigned long parent_rate =
> clk_get_parent_rate(clk); unsigned long long int rate;
>  




Best regards,

Lukasz Majewski

--

DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email: lukma at denx.de
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[U-Boot] [i.MX8MM+CCF 03/41] clk: introduce clk_dev_binded

[Lukasz Majewski]

On Tue, 30 Apr 2019 10:17:40 +0000
Peng Fan <peng.fan@nxp.com> wrote:

> When support Clock Common Framework, U-Boot use dev for
> clk tree information, there is no clk->parent.

There is a function in clk uclass named:
clk_get_parent() to provide parent of the clock.

> When
> support composite clk, it contains mux/gate/divider,
> but the mux/gate/divider is not binded with device.

There is a binding:
struct clk_pllv3 {
	struct clk	clk;
	...
};

The clk.dev points to corresponding device.

In the opposite direction we do have dev->driver_data, which points to
struct clk embedded in for example struct clk_pllv3.
(as struct clk_pllv3 and struct clk share the same address it is up to
us to cast it properly).

I've written my thoughts and considerations about using dev->private
and dev->driver_data in the patch cover letter [1]


> So we could not use dev_get_driver_data to get the correct
> clk_mux/gate/divider. 

Maybe I've overlooked something, but dev_get_driver_data() shall
provide correct reference to udevice.

> So add clk_dev_binded to let
> choose the correct method.
> 

[1] - http://patchwork.ozlabs.org/cover/1090669/

> Signed-off-by: Peng Fan <peng.fan@nxp.com>
> ---
>  drivers/clk/clk.c | 8 ++++++++
>  include/clk.h     | 9 +++++++++
>  2 files changed, 17 insertions(+)
> 
> diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
> index 0a0fffb50b..025bb99ecc 100644
> --- a/drivers/clk/clk.c
> +++ b/drivers/clk/clk.c
> @@ -54,3 +54,11 @@ const char *clk_hw_get_name(const struct clk *hw)
>  {
>  	return hw->dev->name;
>  }
> +
> +bool clk_dev_binded(struct clk *clk)
> +{
> +	if (clk->dev && (clk->dev->flags & DM_FLAG_BOUND))
> +		return true;
> +
> +	return false;
> +}
> diff --git a/include/clk.h b/include/clk.h
> index a4ecca9fbc..8199119d01 100644
> --- a/include/clk.h
> +++ b/include/clk.h
> @@ -337,4 +337,13 @@ static inline bool clk_valid(struct clk *clk)
>   * @return zero on success, or -ENOENT on error
>   */
>  int clk_get_by_id(ulong id, struct clk **clkp);
> +
> +/**
> + * clk_dev_binded() - Check whether the clk has a device binded
> + *
> + * @clk		A pointer to the clk
> + *
> + * @return true on binded, or false on no
> + */
> +bool clk_dev_binded(struct clk *clk);
>  #endif




Best regards,

Lukasz Majewski

--

DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email: lukma at denx.de
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[U-Boot] [i.MX8MM+CCF 04/41] clk: use clk_dev_binded

[Lukasz Majewski]

On Tue, 30 Apr 2019 10:17:43 +0000
Peng Fan <peng.fan@nxp.com> wrote:

> Preparing to support composite clk.
> 
> Signed-off-by: Peng Fan <peng.fan@nxp.com>
> ---
>  drivers/clk/clk-divider.c | 4 ++--
>  drivers/clk/clk-mux.c     | 6 ++++--
>  2 files changed, 6 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c
> index 1d2c1b1ec4..2f09e0bb58 100644
> --- a/drivers/clk/clk-divider.c
> +++ b/drivers/clk/clk-divider.c
> @@ -69,8 +69,8 @@ unsigned long divider_recalc_rate(struct clk *hw,
> unsigned long parent_rate, 
>  static ulong clk_divider_recalc_rate(struct clk *clk)
>  {
> -	struct clk_divider *divider =
> -		to_clk_divider((struct clk
> *)dev_get_driver_data(clk->dev));
> +	struct clk_divider *divider =
> to_clk_divider(clk_dev_binded(clk) ?
> +			(struct clk

As I've wrote in the previous mail - in iMX6Q there was no issues.
Could you provide an explanation in what respect the iMX8MM is
different ?

What exactly is missing?

> *)dev_get_driver_data(clk->dev) : clk); unsigned long parent_rate =
> clk_get_parent_rate(clk); unsigned int val;
>  
> diff --git a/drivers/clk/clk-mux.c b/drivers/clk/clk-mux.c
> index 2c85f2052c..55fc97367a 100644
> --- a/drivers/clk/clk-mux.c
> +++ b/drivers/clk/clk-mux.c
> @@ -35,7 +35,8 @@
>  int clk_mux_val_to_index(struct clk *clk, u32 *table, unsigned int
> flags, unsigned int val)
>  {
> -	struct clk_mux *mux = to_clk_mux(clk);
> +	struct clk_mux *mux = to_clk_mux(clk_dev_binded(clk) ?
> +			(struct clk
> *)dev_get_driver_data(clk->dev) : clk); int num_parents =
> mux->num_parents; 
>  	if (table) {
> @@ -61,7 +62,8 @@ int clk_mux_val_to_index(struct clk *clk, u32
> *table, unsigned int flags, 
>  static u8 clk_mux_get_parent(struct clk *clk)
>  {
> -	struct clk_mux *mux = to_clk_mux(clk);
> +	struct clk_mux *mux = to_clk_mux(clk_dev_binded(clk) ?
> +			(struct clk
> *)dev_get_driver_data(clk->dev) : clk); u32 val;
>  
>  	val = readl(mux->reg) >> mux->shift;




Best regards,

Lukasz Majewski

--

DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email: lukma at denx.de
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[U-Boot] [i.MX8MM+CCF 05/41] clk-provider: sync more clk flags from Linux Kernel

[Lukasz Majewski]

On Tue, 30 Apr 2019 10:17:47 +0000
Peng Fan <peng.fan@nxp.com> wrote:

> Sync more clk flags that might be used in U-Boot CCF.
> 
> Signed-off-by: Peng Fan <peng.fan@nxp.com>
> ---
>  include/linux/clk-provider.h | 21 +++++++++++++++++++++
>  1 file changed, 21 insertions(+)
> 
> diff --git a/include/linux/clk-provider.h
> b/include/linux/clk-provider.h index eac045c5f8..3458746a60 100644
> --- a/include/linux/clk-provider.h
> +++ b/include/linux/clk-provider.h
> @@ -9,8 +9,29 @@
>  #ifndef __LINUX_CLK_PROVIDER_H
>  #define __LINUX_CLK_PROVIDER_H
>  
> +/*
> + * flags used across common struct clk.  these flags should only
> affect the
> + * top-level framework.  custom flags for dealing with hardware
> specifics
> + * belong in struct clk_foo
> + *
> + * Please update clk_flags[] in drivers/clk/clk.c when making
> changes here!
> + */
> +#define CLK_SET_RATE_GATE	BIT(0) /* must be gated across rate
> change */ +#define CLK_SET_PARENT_GATE	BIT(1) /* must be gated
> across re-parent */ #define CLK_SET_RATE_PARENT	BIT(2) /*
> propagate rate change up one level */ +#define
> CLK_IGNORE_UNUSED	BIT(3) /* do not gate even if unused */
> +				/* unused */
> +#define CLK_IS_BASIC		BIT(5) /* Basic clk, can't do a
> to_clk_foo() */ 

> +#define CLK_GET_RATE_NOCACHE	BIT(6) /* do not
> use the cached clk rate */ 

I guess that this is what your requested for the NOCACHE (to always
recalculate the rate).

> #define CLK_SET_RATE_NO_REPARENT BIT(7) /*
> don't re-parent on rate change */ +#define CLK_GET_ACCURACY_NOCACHE
> BIT(8) /* do not use the cached clk accuracy */ +#define
> CLK_RECALC_NEW_RATES	BIT(9) /* recalc rates after
> notifications */ +#define CLK_SET_RATE_UNGATE	BIT(10) /* clock
> needs to run to set rate */ +#define CLK_IS_CRITICAL
> BIT(11) /* do not gate, ever */ +/* parents need enable during
> gate/ungate, set rate and re-parent */ +#define
> CLK_OPS_PARENT_ENABLE	BIT(12) +/* duty cycle call may be
> forwarded to the parent clock */ +#define
> CLK_DUTY_CYCLE_PARENT	BIT(13) #define
> CLK_MUX_INDEX_ONE		BIT(0) #define
> CLK_MUX_INDEX_BIT		BIT(1)

Reviewed-by: Lukasz Majewski <lukma@denx.de>


Best regards,

Lukasz Majewski

--

DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email: lukma at denx.de
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[U-Boot] [i.MX8MM+CCF 06/41] cmd: clk: print err value when clk_get_rate failed

[Lukasz Majewski]

On Tue, 30 Apr 2019 10:17:50 +0000
Peng Fan <peng.fan@nxp.com> wrote:

> Print err value when clk_get_rate failed
> 
> Signed-off-by: Peng Fan <peng.fan@nxp.com>
> ---
>  cmd/clk.c | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/cmd/clk.c b/cmd/clk.c
> index 2ea82176aa..73d963184d 100644
> --- a/cmd/clk.c
> +++ b/cmd/clk.c
> @@ -41,6 +41,8 @@ int __weak soc_clk_dump(void)
>  		rate = clk_get_rate(&clk);
>  		if (!IS_ERR_VALUE(rate))
>  			printf("%-30.30s : %lu Hz\n", dev->name,
> rate);
> +		else
> +			printf("%-30.30s : err=%ld\n", dev->name,
> rate); 
>  		clk_free(&clk);
>  	}

Reviewed-by: Lukasz Majewski <lukma@denx.de>


Best regards,

Lukasz Majewski

--

DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email: lukma at denx.de
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[U-Boot] [i.MX8MM+CCF 07/41] clk: mux: add set parent support

[Lukasz Majewski]

On Tue, 30 Apr 2019 10:17:54 +0000
Peng Fan <peng.fan@nxp.com> wrote:

> Add set parent support for clk mux
> 

I suppose that it was ported from Linux kernel directly?

If yes, please state the SHA1 of Linux master (or exact tag).

> Signed-off-by: Peng Fan <peng.fan@nxp.com>
> ---
>  drivers/clk/clk-mux.c        | 70
> ++++++++++++++++++++++++++++++++++++++++++--
> include/linux/clk-provider.h |  2 ++ 2 files changed, 70
> insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/clk/clk-mux.c b/drivers/clk/clk-mux.c
> index 55fc97367a..1a937bf923 100644
> --- a/drivers/clk/clk-mux.c
> +++ b/drivers/clk/clk-mux.c
> @@ -60,7 +60,24 @@ int clk_mux_val_to_index(struct clk *clk, u32
> *table, unsigned int flags, return val;
>  }
>  
> -static u8 clk_mux_get_parent(struct clk *clk)
> +unsigned int clk_mux_index_to_val(u32 *table, unsigned int flags, u8
> index) +{
> +	unsigned int val = index;
> +
> +	if (table) {
> +		val = table[index];
> +	} else {
> +		if (flags & CLK_MUX_INDEX_BIT)
> +			val = 1 << index;
> +
> +		if (flags & CLK_MUX_INDEX_ONE)
> +			val++;
> +	}
> +
> +	return val;
> +}
> +
> +u8 clk_mux_get_parent(struct clk *clk)
>  {
>  	struct clk_mux *mux = to_clk_mux(clk_dev_binded(clk) ?
>  			(struct clk
> *)dev_get_driver_data(clk->dev) : clk); @@ -72,8 +89,57 @@ static u8
> clk_mux_get_parent(struct clk *clk) return clk_mux_val_to_index(clk,
> mux->table, mux->flags, val); }
>  
> +static int clk_fetch_parent_index(struct clk *clk,
> +				  struct clk *parent)
> +{
> +	struct clk_mux *mux = to_clk_mux(clk_dev_binded(clk) ?
> +			(struct clk
> *)dev_get_driver_data(clk->dev) : clk); +
> +	int i;
> +
> +	if (!parent)
> +		return -EINVAL;
> +
> +	for (i = 0; i < mux->num_parents; i++) {
> +		if (!strcmp(parent->dev->name, mux->parent_names[i]))
> +			return i;
> +	}
> +
> +	return -EINVAL;
> +}
> +
> +static int clk_mux_set_parent(struct clk *clk, struct clk *parent)
> +{
> +	struct clk_mux *mux = to_clk_mux(clk_dev_binded(clk) ?
> +			(struct clk
> *)dev_get_driver_data(clk->dev) : clk);
> +	int index;
> +	u32 val;
> +	u32 reg;
> +
> +	index = clk_fetch_parent_index(clk, parent);
> +	if (index < 0) {
> +		printf("Could not fetch index\n");
> +		return index;
> +	}
> +
> +	val = clk_mux_index_to_val(mux->table, mux->flags, index);
> +
> +	if (mux->flags & CLK_MUX_HIWORD_MASK) {
> +		reg = mux->mask << (mux->shift + 16);
> +	} else {
> +		reg = readl(mux->reg);
> +		reg &= ~(mux->mask << mux->shift);
> +	}
> +	val = val << mux->shift;
> +	reg |= val;
> +	writel(reg, mux->reg);
> +
> +	return 0;
> +}
> +
>  const struct clk_ops clk_mux_ops = {
> -		.get_rate = clk_generic_get_rate,
> +	.get_rate = clk_generic_get_rate,
> +	.set_parent = clk_mux_set_parent,
>  };
>  
>  struct clk *clk_hw_register_mux_table(struct device *dev, const char
> *name, diff --git a/include/linux/clk-provider.h
> b/include/linux/clk-provider.h index 3458746a60..216095d28c 100644
> --- a/include/linux/clk-provider.h
> +++ b/include/linux/clk-provider.h
> @@ -56,6 +56,8 @@ struct clk_mux {
>  };
>  
>  #define to_clk_mux(_clk) container_of(_clk, struct clk_mux, clk)
> +extern const struct clk_ops clk_mux_ops;
> +u8 clk_mux_get_parent(struct clk *clk);
>  
>  struct clk_div_table {
>  	unsigned int	val;




Best regards,

Lukasz Majewski

--

DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email: lukma at denx.de
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[U-Boot] [i.MX8MM+CCF 08/41] clk: export mux/divider ops

[Lukasz Majewski]

On Tue, 30 Apr 2019 10:17:58 +0000
Peng Fan <peng.fan@nxp.com> wrote:

> Export mux/divider ops for composite usage
> 
> Signed-off-by: Peng Fan <peng.fan@nxp.com>
> ---
>  include/linux/clk-provider.h | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/include/linux/clk-provider.h
> b/include/linux/clk-provider.h index 216095d28c..a60cf6e833 100644
> --- a/include/linux/clk-provider.h
> +++ b/include/linux/clk-provider.h
> @@ -83,6 +83,7 @@ struct clk_divider {
>  #define CLK_DIVIDER_ROUND_CLOSEST	BIT(4)
>  #define CLK_DIVIDER_READ_ONLY		BIT(5)
>  #define CLK_DIVIDER_MAX_AT_ZERO		BIT(6)
> +extern const struct clk_ops clk_divider_ops;
>  

Why do we need to export clk_divider_ops? Why iMX8MM requires it?

>  struct clk_fixed_factor {
>  	struct clk	clk;




Best regards,

Lukasz Majewski

--

DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email: lukma at denx.de
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[U-Boot] [i.MX8MM+CCF 10/41] divider set rate supporrt

[Lukasz Majewski]

On Tue, 30 Apr 2019 10:18:05 +0000
Peng Fan <peng.fan@nxp.com> wrote:

Please state the exact SHA1 or tag when porting the code from Linux
kernel.

> Signed-off-by: Peng Fan <peng.fan@nxp.com>
> ---
>  drivers/clk/clk-divider.c | 88
> +++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 88
> insertions(+)
> 
> diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c
> index 2f09e0bb58..8615f9815d 100644
> --- a/drivers/clk/clk-divider.c
> +++ b/drivers/clk/clk-divider.c
> @@ -18,6 +18,7 @@
>  #include <dm/lists.h>
>  #include <dm/device-internal.h>
>  #include <linux/clk-provider.h>
> +#include <linux/log2.h>
>  #include <div64.h>
>  #include <clk.h>
>  #include "clk.h"
> @@ -81,8 +82,95 @@ static ulong clk_divider_recalc_rate(struct clk
> *clk) divider->flags, divider->width);
>  }
>  
> +static bool _is_valid_table_div(const struct clk_div_table *table,
> +				unsigned int div)
> +{
> +	const struct clk_div_table *clkt;
> +
> +	for (clkt = table; clkt->div; clkt++)
> +		if (clkt->div == div)
> +			return true;
> +	return false;
> +}
> +
> +static bool _is_valid_div(const struct clk_div_table *table,
> unsigned int div,
> +			  unsigned long flags)
> +{
> +	if (flags & CLK_DIVIDER_POWER_OF_TWO)
> +		return is_power_of_2(div);
> +	if (table)
> +		return _is_valid_table_div(table, div);
> +	return true;
> +}
> +
> +static unsigned int _get_table_val(const struct clk_div_table *table,
> +				   unsigned int div)
> +{
> +	const struct clk_div_table *clkt;
> +
> +	for (clkt = table; clkt->div; clkt++)
> +		if (clkt->div == div)
> +			return clkt->val;
> +	return 0;
> +}
> +
> +static unsigned int _get_val(const struct clk_div_table *table,
> +			     unsigned int div, unsigned long flags,
> u8 width) +{
> +	if (flags & CLK_DIVIDER_ONE_BASED)
> +		return div;
> +	if (flags & CLK_DIVIDER_POWER_OF_TWO)
> +		return __ffs(div);
> +	if (flags & CLK_DIVIDER_MAX_AT_ZERO)
> +		return (div == clk_div_mask(width) + 1) ? 0 : div;
> +	if (table)
> +		return  _get_table_val(table, div);
> +	return div - 1;
> +}
> +int divider_get_val(unsigned long rate, unsigned long parent_rate,
> +		    const struct clk_div_table *table, u8 width,
> +		    unsigned long flags)
> +{
> +	unsigned int div, value;
> +
> +	div = DIV_ROUND_UP_ULL((u64)parent_rate, rate);
> +
> +	if (!_is_valid_div(table, div, flags))
> +		return -EINVAL;
> +
> +	value = _get_val(table, div, flags, width);
> +
> +	return min_t(unsigned int, value, clk_div_mask(width));
> +}
> +
> +static ulong clk_divider_set_rate(struct clk *clk, unsigned long
> rate) +{
> +	struct clk_divider *divider =
> to_clk_divider(clk_dev_binded(clk) ?
> +			(struct clk
> *)dev_get_driver_data(clk->dev) : clk);
> +	unsigned long parent_rate = clk_get_parent_rate(clk);
> +	int value;
> +	u32 val;
> +
> +	value = divider_get_val(rate, parent_rate, divider->table,
> +				divider->width, divider->flags);
> +	if (value < 0)
> +		return value;
> +
> +	if (divider->flags & CLK_DIVIDER_HIWORD_MASK) {
> +		val = clk_div_mask(divider->width) <<
> (divider->shift + 16);
> +	} else {
> +		val = readl(divider->reg);
> +		val &= ~(clk_div_mask(divider->width) <<
> divider->shift);
> +	}
> +	val |= (u32)value << divider->shift;
> +	writel(val, divider->reg);
> +
> +	return clk_get_rate(clk);
> +}
> +
>  const struct clk_ops clk_divider_ops = {
>  	.get_rate = clk_divider_recalc_rate,
> +	.set_rate = clk_divider_set_rate,
>  };
>  
>  static struct clk *_register_divider(struct device *dev, const char
> *name,




Best regards,

Lukasz Majewski

--

DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
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[U-Boot] [i.MX8MM+CCF 11/41] clk: fixed_rate: export clk_fixed_rate

[Lukasz Majewski]

Hi Peng,

> Export the structure for others to use.
> 
> Signed-off-by: Peng Fan <peng.fan@nxp.com>
> ---
>  drivers/clk/clk_fixed_rate.c | 8 +-------
>  include/linux/clk-provider.h | 7 +++++++
>  2 files changed, 8 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/clk/clk_fixed_rate.c
> b/drivers/clk/clk_fixed_rate.c index 089f060a23..069e643fbc 100644
> --- a/drivers/clk/clk_fixed_rate.c
> +++ b/drivers/clk/clk_fixed_rate.c
> @@ -6,13 +6,7 @@
>  #include <common.h>
>  #include <clk-uclass.h>
>  #include <dm.h>
> -
> -struct clk_fixed_rate {
> -	struct clk clk;
> -	unsigned long fixed_rate;
> -};
> -
> -#define to_clk_fixed_rate(dev)	((struct clk_fixed_rate
> *)dev_get_platdata(dev)) +#include <linux/clk-provider.h>
>  
>  static ulong clk_fixed_rate_get_rate(struct clk *clk)
>  {
> diff --git a/include/linux/clk-provider.h
> b/include/linux/clk-provider.h index 3ed0db86d2..b2bed768b6 100644
> --- a/include/linux/clk-provider.h
> +++ b/include/linux/clk-provider.h
> @@ -112,6 +112,13 @@ struct clk_fixed_factor {
>  #define to_clk_fixed_factor(_clk) container_of(_clk, struct
> clk_fixed_factor,\ clk)
>  
> +struct clk_fixed_rate {
> +	struct clk clk;
> +	unsigned long fixed_rate;
> +};

I think that this struct shall stay where it was. Moreover, the
clk-provider.h is not the API to be used by other parts of the clock
API.

The clk_fixed_rate shall be accessed via get_rate() only and in IMX6Q
it is available in early SPL (parsed from dts /clocks property - the
24MHz OSC)

> +
> +#define to_clk_fixed_rate(dev)	((struct clk_fixed_rate
> *)dev_get_platdata(dev)) +
>  int clk_register(struct clk *clk, const char *drv_name,
>  		 ulong drv_data, const char *name,
>  		 const char *parent_name);

Please explain why iMX8MM needs such global export?


Best regards,

Lukasz Majewski

--

DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email: lukma at denx.de
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[U-Boot] [i.MX8MM+CCF 12/41] clk: fixed_rate: add pre reloc flag

[Lukasz Majewski]

On Tue, 30 Apr 2019 10:18:12 +0000
Peng Fan <peng.fan@nxp.com> wrote:

> Add pre reloc flag to use this driver before relocation
> 
> Signed-off-by: Peng Fan <peng.fan@nxp.com>
> ---
>  drivers/clk/clk_fixed_rate.c | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/drivers/clk/clk_fixed_rate.c
> b/drivers/clk/clk_fixed_rate.c index 069e643fbc..debada1463 100644
> --- a/drivers/clk/clk_fixed_rate.c
> +++ b/drivers/clk/clk_fixed_rate.c
> @@ -45,4 +45,5 @@ U_BOOT_DRIVER(clk_fixed_rate) = {
>  	.ofdata_to_platdata = clk_fixed_rate_ofdata_to_platdata,
>  	.platdata_auto_alloc_size = sizeof(struct clk_fixed_rate),
>  	.ops = &clk_fixed_rate_ops,
> +	.flags = DM_FLAG_PRE_RELOC,
>  };

This probably shall be done with proper dts file (from TPC70 - imx6q
conversion code):

+#include "imx6qdl-u-boot.dtsi"
+
+/ {
+	clocks {
+		u-boot,dm-spl;
+		osc {
+			u-boot,dm-spl;
+		};
+	};
+};
+
+&clks {
+	u-boot,dm-pre-reloc;
+};



Best regards,

Lukasz Majewski

--

DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
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[U-Boot] [i.MX8MM+CCF 13/41] clk: imx: import clk heplers

[Lukasz Majewski]

On Tue, 30 Apr 2019 10:18:15 +0000
Peng Fan <peng.fan@nxp.com> wrote:

> Import some clk helpers from Linux Kernel for i.MX8MM usage
> 

Please globally provide SHA1 and tag of ported code from Linux kernel.

> Signed-off-by: Peng Fan <peng.fan@nxp.com>
> ---
>  drivers/clk/imx/clk.h | 81
> +++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed,
> 81 insertions(+)
> 
> diff --git a/drivers/clk/imx/clk.h b/drivers/clk/imx/clk.h
> index 864a215a22..aa6e81ff13 100644
> --- a/drivers/clk/imx/clk.h
> +++ b/drivers/clk/imx/clk.h
> @@ -42,6 +42,23 @@ static inline struct clk *imx_clk_gate2(const char
> *name, const char *parent, shift, 0x3, 0);
>  }
>  
> +static inline struct clk *imx_clk_gate4(const char *name, const char
> *parent,
> +		void __iomem *reg, u8 shift)
> +{
> +	return clk_register_gate2(NULL, name, parent,
> +			CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
> +			reg, shift, 0x3, 0);
> +}
> +
> +static inline struct clk *imx_clk_gate4_flags(const char *name,
> +		const char *parent, void __iomem *reg, u8 shift,
> +		unsigned long flags)
> +{
> +	return clk_register_gate2(NULL, name, parent,
> +			flags | CLK_SET_RATE_PARENT |
> CLK_OPS_PARENT_ENABLE,
> +			reg, shift, 0x3, 0);
> +}
> +
>  static inline struct clk *imx_clk_fixed_factor(const char *name,
>  		const char *parent, unsigned int mult, unsigned int
> div) {
> @@ -56,6 +73,14 @@ static inline struct clk *imx_clk_divider(const
> char *name, const char *parent, reg, shift, width, 0);
>  }
>  
> +static inline struct clk *imx_clk_divider2(const char *name, const
> char *parent,
> +		void __iomem *reg, u8 shift, u8 width)
> +{
> +	return clk_register_divider(NULL, name, parent,
> +			CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
> +			reg, shift, width, 0);
> +}
> +
>  struct clk *imx_clk_pfd(const char *name, const char *parent_name,
>  			void __iomem *reg, u8 idx);
>  
> @@ -63,6 +88,16 @@ struct clk *imx_clk_fixup_mux(const char *name,
> void __iomem *reg, u8 shift, u8 width, const char * const *parents,
>  			      int num_parents, void (*fixup)(u32
> *val)); 
> +static inline struct clk *imx_clk_mux_flags(const char *name,
> +			void __iomem *reg, u8 shift, u8 width,
> +			const char * const *parents, int num_parents,
> +			unsigned long flags)
> +{
> +	return clk_register_mux(NULL, name, parents, num_parents,
> +				flags | CLK_SET_RATE_NO_REPARENT,
> reg, shift,
> +				width, 0);
> +}
> +
>  static inline struct clk *imx_clk_mux(const char *name, void __iomem
> *reg, u8 shift, u8 width, const char * const *parents,
>  			int num_parents)
> @@ -72,4 +107,50 @@ static inline struct clk *imx_clk_mux(const char
> *name, void __iomem *reg, width, 0);
>  }
>  
> +static inline struct clk *imx_clk_mux2(const char *name, void
> __iomem *reg,
> +			u8 shift, u8 width, const char * const
> *parents,
> +			int num_parents)
> +{
> +	return clk_register_mux(NULL, name, parents, num_parents,
> +			CLK_SET_RATE_NO_REPARENT |
> CLK_OPS_PARENT_ENABLE,
> +			reg, shift, width, 0);
> +}
> +
> +static inline struct clk *imx_clk_gate(const char *name, const char
> *parent,
> +		void __iomem *reg, u8 shift)
> +{
> +	return clk_register_gate(NULL, name, parent,
> CLK_SET_RATE_PARENT, reg,
> +			shift, 0, NULL);
> +}
> +
> +static inline struct clk *imx_clk_gate_flags(const char *name, const
> char *parent,
> +		void __iomem *reg, u8 shift, unsigned long flags)
> +{
> +	return clk_register_gate(NULL, name, parent, flags |
> CLK_SET_RATE_PARENT, reg,
> +			shift, 0, NULL);
> +}
> +
> +static inline struct clk *imx_clk_gate3(const char *name, const char
> *parent,
> +		void __iomem *reg, u8 shift)
> +{
> +	return clk_register_gate(NULL, name, parent,
> +			CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
> +			reg, shift, 0, NULL);
> +}
> +
> +struct clk *imx8m_clk_composite_flags(const char *name,
> +		const char * const *parent_names,
> +		int num_parents, void __iomem *reg, unsigned long
> flags); +
> +#define __imx8m_clk_composite(name, parent_names, reg, flags) \
> +	imx8m_clk_composite_flags(name, parent_names, \
> +		ARRAY_SIZE(parent_names), reg, \
> +		flags | CLK_SET_RATE_NO_REPARENT |
> CLK_OPS_PARENT_ENABLE) +
> +#define imx8m_clk_composite(name, parent_names, reg) \
> +	__imx8m_clk_composite(name, parent_names, reg, 0)
> +
> +#define imx8m_clk_composite_critical(name, parent_names, reg) \
> +	__imx8m_clk_composite(name, parent_names, reg,
> CLK_IS_CRITICAL) +
>  #endif /* __MACH_IMX_CLK_H */




Best regards,

Lukasz Majewski

--

DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email: lukma at denx.de
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[U-Boot] [i.MX8MM+CCF 00/41] i.MX8MM + CCF

[Peng Fan]

> Subject: Re: [i.MX8MM+CCF 00/41] i.MX8MM + CCF
> 
> Hi Peng,
> 
> > This patch set is based Lukasz V3 CCF patchset, [PATCH v3 00/11] clk:
> > Port Linux common clock framework [CCF] to U-boot (tag: 5.0-rc3)
> > https://github.com/lmajewski/u-boot-dfu/commits/CCF-v3
> >
> > Added a few fixes to Lukasz's v3 patchset.
> > Introduced clk-gate/composite
> > Added set rate support
> > Per my understanding, U-Boot CCF will not support mux reparent, and
> > support rate prograte setting to parent automatically.
> 
> I think that we shall keep the code as small as possible and hence add only
> necessary features (that is why my code only supports gating and muxing for
> 'downstream' settings).

I understand. But when we want to set freq, we need set mux, set divider.
I suggest add kconfig entry for each clk-xx.c and ro/rw ops.

> 
> > So new clk
> > feature added follow this rule.
> >
> > There are many warnings when importing linux ccf code, I did not
> > modify them all.
> 
> I've removed some not needed arguments (like spinlocks) when porting the
> code.

I just set to NULL.

> 
> >
> > The rest patches are for i.MX8MM, part of legacy clk code are still
> > kept, because we are hard to enable CCF at very early stage,
> 
> Yes, CCF in SPL is a challenging task.
> 
> > we set
> > malloc space to DRAM when dram initialized in spl stage, so we have
> > limited SRAM for uclass dm and dm clk,
> 
> I'm puzzled about this sentence. The malloc is set to be in DRAM, but also
> SRAM is used for uclass dm and CCF.

CONFIG_SYS_SPL_MALLOC_START is set to DRAM space.

> 
> As fair as I remember on iMX6Q it is possible to setup early malloc to be in
> SRAM (OCRAM). Having it in DRAM is a bit late, IMHO as clocks are already
> setup in this moment.

We do dram initialization in spl board_init_f. Using CCF to configure dram clock
is complicated and kernel clock driver not have that, I need add it
to uboot if choose use CCF to configure the dram clock.
However use original clock code to set dram clock is simpler and cleaner.

> 
> > so keep the DRAM PLL related
> > setting with legacy clk code which use small ram.
> 
> What is the 'ram' ? I suppose that the legacy clk code uses OCRAM to allocate
> variables ?


Yes.

> 
> >
> > The u-boot-spl.bin now is about 100KB without ddr firmware,usb stack
> > and hab, so really large......
> 
> I think that 100KiB is too much (without DDR, USB stack and HAB). For one
> IMX6Q setup (before DM/DTS conversion) I had SPL size ~30 KiB.
> 
> After the conversion it is 55 KiB ...

I'll check more, but mostly DM related code. The DM CCF related code
cost about 15KB space.

> 
> > I am thinking what we could do to shrink the size, welcome any
> > suggestions.
> 
> Please consider using:
> 
> - TINY_PRINTF
> - TINY_FIT support (just support for single image in FIT)
> - OF_PLATDATA (the in-device-tree code is compiled in as C
>   structures) - no need to include DTS parsing / handling code in SPL.
>   Also the *.dts file is not needed.
> 
>   Drawback is that you need to extend drivers to support OF_PLATDATA
>   (RK3399 have some examples of such approach).
> 
> - Check if thumb2 is uses for SPL compilation
> - I simply do find *.o files and sort them regarding the size. Then I
>   do know where to start with optimisations.

Thanks for suggestions.

Thanks,
Peng.

> 
> >
> > Not expect this patchset could be merged, because of the CCF/clock
> > code change, but since the clock part blocks i.MX8MM upstream, just
> > would like to speed up the development with community and move on.
> >
> > Peng Fan (40):
> >   clk: correct get clk_x pointer
> >   clk: fixed-factor: fix get clk_fixed_factor
> >   clk: introduce clk_dev_binded
> >   clk: use clk_dev_binded
> >   clk-provider: sync more clk flags from Linux Kernel
> >   cmd: clk: print err value when clk_get_rate failed
> >   clk: mux: add set parent support
> >   clk: export mux/divider ops
> >   clk: add clk-gate support
> >   divider set rate supporrt
> >   clk: fixed_rate: export clk_fixed_rate
> >   clk: fixed_rate: add pre reloc flag
> >   clk: imx: import clk heplers
> >   clk: imx: gate2 add set rate
> >   linux: compat: guard PAGE_SIZE
> >   drivers: core: use strcmp when find device by name
> >   ddr: imx8m: fix ddr firmware location when enable SPL OF
> >   imx: add IMX8MQ kconfig entry
> >   imx: add IMX8MM kconfig entry
> >   imx: imx8mm: add clock bindings header
> >   imx: add i.MX8MM cpu type
> >   imx: spl: add spl_board_boot_device for i.MX8MM
> >   imx8m: update imx-regs for i.MX8MM
> >   imx: add get_cpu_rev support for i.MX8MM
> >   imx8m: rename clock to clock_imx8mq
> >   imx8m: restructure clock.h
> >   imx8m: add clk support for i.MX8MM
> >   imx8m: soc: probe clk before relocation
> >   imx8m: add pin header for i.MX8MM
> >   imx: add i.MX8MM PE property
> >   imx8m: Fix MMU table issue for OPTEE memory
> >   imx8m: set BYPASS ID SWAP to avoid AXI bus errors
> >   imx8m: soc: enable SCTR clock before timer init
> >   serial: Kconfig: make MXC_UART usable for MX7 and IMX8M
> >   clk: imx: add Kconfig entry for i.MX8MM
> >   clk: imx: add pll14xx driver
> >   clk: add composite clk support
> >   clk: imx: add i.MX8MM composite clk support
> >   clk: imx: add i.MX8MM clk driver
> >   imx: add i.MX8MM EVK board support
> >
> > Ye Li (1):
> >   imx8m: Configure trustzone region 0 for non-secure access
> >
> >  arch/arm/dts/Makefile                              |    3 +-
> >  arch/arm/dts/imx8mm-evk-u-boot.dtsi                |   92 +
> >  arch/arm/dts/imx8mm-evk.dts                        |  235 +++
> >  arch/arm/dts/imx8mm-pinfunc.h                      |  629
> +++++++
> >  arch/arm/dts/imx8mm.dtsi                           |  733
> ++++++++
> >  arch/arm/include/asm/arch-imx/cpu.h                |    6 +
> >  arch/arm/include/asm/arch-imx8m/clock.h            |  493 +----
> >  arch/arm/include/asm/arch-imx8m/clock_imx8mm.h     |  387 ++++
> >  arch/arm/include/asm/arch-imx8m/clock_imx8mq.h     |  424 +++++
> >  arch/arm/include/asm/arch-imx8m/imx-regs.h         |   75 +-
> >  arch/arm/include/asm/arch-imx8m/imx8mm_pins.h      |  691
> +++++++
> >  arch/arm/include/asm/mach-imx/iomux-v3.h           |    4 +
> >  arch/arm/include/asm/mach-imx/sys_proto.h          |    8 +
> >  arch/arm/mach-imx/cpu.c                            |   12 +
> >  arch/arm/mach-imx/imx8m/Kconfig                    |   17 +-
> >  arch/arm/mach-imx/imx8m/Makefile                   |    4 +-
> >  arch/arm/mach-imx/imx8m/clock_imx8mm.c             |  292 +++
> >  .../arm/mach-imx/imx8m/{clock.c => clock_imx8mq.c} |    5 +-
> >  arch/arm/mach-imx/imx8m/clock_slice.c              |  461 +++++
> >  arch/arm/mach-imx/imx8m/soc.c                      |  112 +-
> >  arch/arm/mach-imx/spl.c                            |    8 +
> >  board/freescale/imx8mm_evk/Kconfig                 |   12 +
> >  board/freescale/imx8mm_evk/MAINTAINERS             |    6 +
> >  board/freescale/imx8mm_evk/Makefile                |   12 +
> >  board/freescale/imx8mm_evk/imx8mm_evk.c            |   90 +
> >  board/freescale/imx8mm_evk/lpddr4_timing.c         | 1980
> > ++++++++++++++++++++
> > board/freescale/imx8mm_evk/spl.c                   |  216 +++
> > cmd/clk.c                                          |    2 +
> > configs/imx8mm_evk_defconfig                       |   52 +
> > drivers/clk/Kconfig                                |   14 +
> > drivers/clk/Makefile                               |    3 +-
> > drivers/clk/clk-composite.c                        |  165 ++
> > drivers/clk/clk-divider.c                          |   92 +-
> > drivers/clk/clk-fixed-factor.c                     |    2 +-
> > drivers/clk/clk-gate.c                             |  151 ++
> > drivers/clk/clk-mux.c                              |   76 +-
> > drivers/clk/clk.c                                  |    8 +
> > drivers/clk/clk_fixed_rate.c                       |    9 +-
> > drivers/clk/imx/Kconfig                            |    9 +
> > drivers/clk/imx/Makefile                           |    1 +
> > drivers/clk/imx/clk-composite-8m.c                 |  170 ++
> > drivers/clk/imx/clk-gate2.c                        |   15 +-
> > drivers/clk/imx/clk-imx8mm.c                       |  415 ++++
> > drivers/clk/imx/clk-pfd.c                          |    2 +-
> > drivers/clk/imx/clk-pll14xx.c                      |  377 ++++
> > drivers/clk/imx/clk-pllv3.c                        |    2 +-
> > drivers/clk/imx/clk.h                              |  106 ++
> > drivers/core/uclass.c                              |    2 +-
> > drivers/ddr/imx/imx8m/helper.c                     |   12 +-
> > drivers/serial/Kconfig                             |    2 +-
> > include/clk.h                                      |    9 +
> > include/configs/imx8mm_evk.h                       |  199 ++
> > include/dt-bindings/clock/imx8mm-clock.h           |  244 +++
> > include/linux/clk-provider.h                       |   74 +
> > include/linux/compat.h                             |    2 + 55
> files
> > changed, 8728 insertions(+), 494 deletions(-) create mode 100644
> > arch/arm/dts/imx8mm-evk-u-boot.dtsi create mode 100644
> > arch/arm/dts/imx8mm-evk.dts create mode 100644
> > arch/arm/dts/imx8mm-pinfunc.h create mode 100644
> > arch/arm/dts/imx8mm.dtsi create mode 100644
> > arch/arm/include/asm/arch-imx8m/clock_imx8mm.h create mode 100644
> > arch/arm/include/asm/arch-imx8m/clock_imx8mq.h create mode 100644
> > arch/arm/include/asm/arch-imx8m/imx8mm_pins.h create mode 100644
> > arch/arm/mach-imx/imx8m/clock_imx8mm.c rename
> > arch/arm/mach-imx/imx8m/{clock.c => clock_imx8mq.c} (99%) create
> mode
> > 100644 board/freescale/imx8mm_evk/Kconfig create mode 100644
> > board/freescale/imx8mm_evk/MAINTAINERS create mode 100644
> > board/freescale/imx8mm_evk/Makefile create mode 100644
> > board/freescale/imx8mm_evk/imx8mm_evk.c create mode 100644
> > board/freescale/imx8mm_evk/lpddr4_timing.c create mode 100644
> > board/freescale/imx8mm_evk/spl.c create mode 100644
> > configs/imx8mm_evk_defconfig create mode 100644
> > drivers/clk/clk-composite.c create mode 100644 drivers/clk/clk-gate.c
> > create mode 100644 drivers/clk/imx/clk-composite-8m.c
> >  create mode 100644 drivers/clk/imx/clk-imx8mm.c  create mode
> 100644
> > drivers/clk/imx/clk-pll14xx.c  create mode 100644
> > include/configs/imx8mm_evk.h  create mode 100644
> > include/dt-bindings/clock/imx8mm-clock.h
> >
> 
> 
> 
> 
> Best regards,
> 
> Lukasz Majewski
> 
> --
> 
> DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
> HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
> Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email:
> lukma at denx.de

[U-Boot] [i.MX8MM+CCF 03/41] clk: introduce clk_dev_binded

[Peng Fan]

> Subject: Re: [i.MX8MM+CCF 03/41] clk: introduce clk_dev_binded
> 
> On Tue, 30 Apr 2019 10:17:40 +0000
> Peng Fan <peng.fan@nxp.com> wrote:
> 
> > When support Clock Common Framework, U-Boot use dev for clk tree
> > information, there is no clk->parent.
> 
> There is a function in clk uclass named:
> clk_get_parent() to provide parent of the clock.
> 
> > When
> > support composite clk, it contains mux/gate/divider, but the
> > mux/gate/divider is not binded with device.
> 
> There is a binding:
> struct clk_pllv3 {
> 	struct clk	clk;
> 	...
> };
> 
> The clk.dev points to corresponding device.
> 
> In the opposite direction we do have dev->driver_data, which points to struct
> clk embedded in for example struct clk_pllv3.
> (as struct clk_pllv3 and struct clk share the same address it is up to us to cast
> it properly).
> 
> I've written my thoughts and considerations about using dev->private and
> dev->driver_data in the patch cover letter [1]
> 
> 
> > So we could not use dev_get_driver_data to get the correct
> > clk_mux/gate/divider.
> 
> Maybe I've overlooked something, but dev_get_driver_data() shall provide
> correct reference to udevice.

A composite clk contains a mux/gate/divider clk. Only the composite clk needs to
binded with a udevice. The mux/gate/divider inside a composite clk should not
bind a device, because they needs to be hidden from dm tree or clk dumps.

If bind the mux/gate/divider insides a composite clk, that will be mess. The reason
to introduce composite clk is to make clk tree cleaner/simplier.

Regards,
Peng.

> 
> > So add clk_dev_binded to let
> > choose the correct method.
> >
> 
> [1] - http://patchwork.ozlabs.org/cover/1090669/
> 
> > Signed-off-by: Peng Fan <peng.fan@nxp.com>
> > ---
> >  drivers/clk/clk.c | 8 ++++++++
> >  include/clk.h     | 9 +++++++++
> >  2 files changed, 17 insertions(+)
> >
> > diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c index
> > 0a0fffb50b..025bb99ecc 100644
> > --- a/drivers/clk/clk.c
> > +++ b/drivers/clk/clk.c
> > @@ -54,3 +54,11 @@ const char *clk_hw_get_name(const struct clk *hw)
> > {
> >  	return hw->dev->name;
> >  }
> > +
> > +bool clk_dev_binded(struct clk *clk)
> > +{
> > +	if (clk->dev && (clk->dev->flags & DM_FLAG_BOUND))
> > +		return true;
> > +
> > +	return false;
> > +}
> > diff --git a/include/clk.h b/include/clk.h index
> > a4ecca9fbc..8199119d01 100644
> > --- a/include/clk.h
> > +++ b/include/clk.h
> > @@ -337,4 +337,13 @@ static inline bool clk_valid(struct clk *clk)
> >   * @return zero on success, or -ENOENT on error
> >   */
> >  int clk_get_by_id(ulong id, struct clk **clkp);
> > +
> > +/**
> > + * clk_dev_binded() - Check whether the clk has a device binded
> > + *
> > + * @clk		A pointer to the clk
> > + *
> > + * @return true on binded, or false on no  */ bool
> > +clk_dev_binded(struct clk *clk);
> >  #endif
> 
> 
> 
> 
> Best regards,
> 
> Lukasz Majewski
> 
> --
> 
> DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
> HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
> Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email:
> lukma at denx.de

[U-Boot] [i.MX8MM+CCF 07/41] clk: mux: add set parent support

[Peng Fan]

> Subject: Re: [i.MX8MM+CCF 07/41] clk: mux: add set parent support
> 
> On Tue, 30 Apr 2019 10:17:54 +0000
> Peng Fan <peng.fan@nxp.com> wrote:
> 
> > Add set parent support for clk mux
> >
> 
> I suppose that it was ported from Linux kernel directly?
> 
> If yes, please state the SHA1 of Linux master (or exact tag).

Modified from 5.1-rc5. Will add it in next version.

Thanks,
Peng.

> 
> > Signed-off-by: Peng Fan <peng.fan@nxp.com>
> > ---
> >  drivers/clk/clk-mux.c        | 70
> > ++++++++++++++++++++++++++++++++++++++++++--
> > include/linux/clk-provider.h |  2 ++ 2 files changed, 70
> > insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/clk/clk-mux.c b/drivers/clk/clk-mux.c index
> > 55fc97367a..1a937bf923 100644
> > --- a/drivers/clk/clk-mux.c
> > +++ b/drivers/clk/clk-mux.c
> > @@ -60,7 +60,24 @@ int clk_mux_val_to_index(struct clk *clk, u32
> > *table, unsigned int flags, return val;  }
> >
> > -static u8 clk_mux_get_parent(struct clk *clk)
> > +unsigned int clk_mux_index_to_val(u32 *table, unsigned int flags, u8
> > index) +{
> > +	unsigned int val = index;
> > +
> > +	if (table) {
> > +		val = table[index];
> > +	} else {
> > +		if (flags & CLK_MUX_INDEX_BIT)
> > +			val = 1 << index;
> > +
> > +		if (flags & CLK_MUX_INDEX_ONE)
> > +			val++;
> > +	}
> > +
> > +	return val;
> > +}
> > +
> > +u8 clk_mux_get_parent(struct clk *clk)
> >  {
> >  	struct clk_mux *mux = to_clk_mux(clk_dev_binded(clk) ?
> >  			(struct clk
> > *)dev_get_driver_data(clk->dev) : clk); @@ -72,8 +89,57 @@ static u8
> > clk_mux_get_parent(struct clk *clk) return clk_mux_val_to_index(clk,
> > mux->table, mux->flags, val); }
> >
> > +static int clk_fetch_parent_index(struct clk *clk,
> > +				  struct clk *parent)
> > +{
> > +	struct clk_mux *mux = to_clk_mux(clk_dev_binded(clk) ?
> > +			(struct clk
> > *)dev_get_driver_data(clk->dev) : clk); +
> > +	int i;
> > +
> > +	if (!parent)
> > +		return -EINVAL;
> > +
> > +	for (i = 0; i < mux->num_parents; i++) {
> > +		if (!strcmp(parent->dev->name, mux->parent_names[i]))
> > +			return i;
> > +	}
> > +
> > +	return -EINVAL;
> > +}
> > +
> > +static int clk_mux_set_parent(struct clk *clk, struct clk *parent) {
> > +	struct clk_mux *mux = to_clk_mux(clk_dev_binded(clk) ?
> > +			(struct clk
> > *)dev_get_driver_data(clk->dev) : clk);
> > +	int index;
> > +	u32 val;
> > +	u32 reg;
> > +
> > +	index = clk_fetch_parent_index(clk, parent);
> > +	if (index < 0) {
> > +		printf("Could not fetch index\n");
> > +		return index;
> > +	}
> > +
> > +	val = clk_mux_index_to_val(mux->table, mux->flags, index);
> > +
> > +	if (mux->flags & CLK_MUX_HIWORD_MASK) {
> > +		reg = mux->mask << (mux->shift + 16);
> > +	} else {
> > +		reg = readl(mux->reg);
> > +		reg &= ~(mux->mask << mux->shift);
> > +	}
> > +	val = val << mux->shift;
> > +	reg |= val;
> > +	writel(reg, mux->reg);
> > +
> > +	return 0;
> > +}
> > +
> >  const struct clk_ops clk_mux_ops = {
> > -		.get_rate = clk_generic_get_rate,
> > +	.get_rate = clk_generic_get_rate,
> > +	.set_parent = clk_mux_set_parent,
> >  };
> >
> >  struct clk *clk_hw_register_mux_table(struct device *dev, const char
> > *name, diff --git a/include/linux/clk-provider.h
> > b/include/linux/clk-provider.h index 3458746a60..216095d28c 100644
> > --- a/include/linux/clk-provider.h
> > +++ b/include/linux/clk-provider.h
> > @@ -56,6 +56,8 @@ struct clk_mux {
> >  };
> >
> >  #define to_clk_mux(_clk) container_of(_clk, struct clk_mux, clk)
> > +extern const struct clk_ops clk_mux_ops;
> > +u8 clk_mux_get_parent(struct clk *clk);
> >
> >  struct clk_div_table {
> >  	unsigned int	val;
> 
> 
> 
> 
> Best regards,
> 
> Lukasz Majewski
> 
> --
> 
> DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
> HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
> Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email:
> lukma at denx.de

[U-Boot] [i.MX8MM+CCF 08/41] clk: export mux/divider ops

[Peng Fan]

> Subject: Re: [i.MX8MM+CCF 08/41] clk: export mux/divider ops
> 
> On Tue, 30 Apr 2019 10:17:58 +0000
> Peng Fan <peng.fan@nxp.com> wrote:
> 
> > Export mux/divider ops for composite usage
> >
> > Signed-off-by: Peng Fan <peng.fan@nxp.com>
> > ---
> >  include/linux/clk-provider.h | 1 +
> >  1 file changed, 1 insertion(+)
> >
> > diff --git a/include/linux/clk-provider.h
> > b/include/linux/clk-provider.h index 216095d28c..a60cf6e833 100644
> > --- a/include/linux/clk-provider.h
> > +++ b/include/linux/clk-provider.h
> > @@ -83,6 +83,7 @@ struct clk_divider {
> >  #define CLK_DIVIDER_ROUND_CLOSEST	BIT(4)
> >  #define CLK_DIVIDER_READ_ONLY		BIT(5)
> >  #define CLK_DIVIDER_MAX_AT_ZERO		BIT(6)
> > +extern const struct clk_ops clk_divider_ops;
> >
> 
> Why do we need to export clk_divider_ops? Why iMX8MM requires it?


The composite driver will use that to set ops for divider clk inside composite clk.
The Linux CCF also exports it.

You could check the clk-composite-imx8m and clk-composite driver in this patchset.

Regards,
Peng.

> 
> >  struct clk_fixed_factor {
> >  	struct clk	clk;
> 
> 
> 
> 
> Best regards,
> 
> Lukasz Majewski
> 
> --
> 
> DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
> HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
> Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email:
> lukma at denx.de

[U-Boot] [i.MX8MM+CCF 11/41] clk: fixed_rate: export clk_fixed_rate

[Peng Fan]

> Subject: Re: [i.MX8MM+CCF 11/41] clk: fixed_rate: export clk_fixed_rate
> 
> Hi Peng,
> 
> > Export the structure for others to use.
> >
> > Signed-off-by: Peng Fan <peng.fan@nxp.com>
> > ---
> >  drivers/clk/clk_fixed_rate.c | 8 +-------
> > include/linux/clk-provider.h | 7 +++++++
> >  2 files changed, 8 insertions(+), 7 deletions(-)
> >
> > diff --git a/drivers/clk/clk_fixed_rate.c
> > b/drivers/clk/clk_fixed_rate.c index 089f060a23..069e643fbc 100644
> > --- a/drivers/clk/clk_fixed_rate.c
> > +++ b/drivers/clk/clk_fixed_rate.c
> > @@ -6,13 +6,7 @@
> >  #include <common.h>
> >  #include <clk-uclass.h>
> >  #include <dm.h>
> > -
> > -struct clk_fixed_rate {
> > -	struct clk clk;
> > -	unsigned long fixed_rate;
> > -};
> > -
> > -#define to_clk_fixed_rate(dev)	((struct clk_fixed_rate
> > *)dev_get_platdata(dev)) +#include <linux/clk-provider.h>
> >
> >  static ulong clk_fixed_rate_get_rate(struct clk *clk)  { diff --git
> > a/include/linux/clk-provider.h b/include/linux/clk-provider.h index
> > 3ed0db86d2..b2bed768b6 100644
> > --- a/include/linux/clk-provider.h
> > +++ b/include/linux/clk-provider.h
> > @@ -112,6 +112,13 @@ struct clk_fixed_factor {  #define
> > to_clk_fixed_factor(_clk) container_of(_clk, struct clk_fixed_factor,\
> > clk)
> >
> > +struct clk_fixed_rate {
> > +	struct clk clk;
> > +	unsigned long fixed_rate;
> > +};
> 
> I think that this struct shall stay where it was. Moreover, the clk-provider.h is
> not the API to be used by other parts of the clock API.
> 
> The clk_fixed_rate shall be accessed via get_rate() only and in IMX6Q it is
> available in early SPL (parsed from dts /clocks property - the 24MHz OSC)
> 
> > +
> > +#define to_clk_fixed_rate(dev)	((struct clk_fixed_rate
> > *)dev_get_platdata(dev)) +
> >  int clk_register(struct clk *clk, const char *drv_name,
> >  		 ulong drv_data, const char *name,
> >  		 const char *parent_name);
> 
> Please explain why iMX8MM needs such global export?

In clk-imx8mm.c, first configure ARM clk to osc24M fixed clk to change pll clock.
+       /* Configure ARM to osc24M */
+       clk_get_by_id(IMX8MM_CLK_A53_SRC, &clkp);
+       uclass_get_device_by_name(UCLASS_CLK, "clock-osc-24m", &devp);
+       clkp1 = &to_clk_fixed_rate(devp)->clk;
+       clk_set_parent(clkp, clkp1);
+
+       /* Configure ARM PLL to 1.2GHz */
+       clk_get_by_id(IMX8MM_ARM_PLL, &clkp1);
+       clk_set_rate(clkp1, 1200000000UL);
+       clk_get_by_id(IMX8MM_ARM_PLL_OUT, &clkp1);
+       clk_enable(clkp1);
+       clk_set_parent(clkp, clkp1);
+
+       /* Configure DIV to 1.2GHz */
+       clk_get_by_id(IMX8MM_CLK_A53_DIV, &clkp1);
+       clk_set_rate(clkp1, 1200000000UL);

Regards,
Peng.

> 
> 
> Best regards,
> 
> Lukasz Majewski
> 
> --
> 
> DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
> HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
> Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email:
> lukma at denx.de

[U-Boot] [i.MX8MM+CCF 12/41] clk: fixed_rate: add pre reloc flag

[Peng Fan]

> Subject: Re: [i.MX8MM+CCF 12/41] clk: fixed_rate: add pre reloc flag
> 
> On Tue, 30 Apr 2019 10:18:12 +0000
> Peng Fan <peng.fan@nxp.com> wrote:
> 
> > Add pre reloc flag to use this driver before relocation
> >
> > Signed-off-by: Peng Fan <peng.fan@nxp.com>
> > ---
> >  drivers/clk/clk_fixed_rate.c | 1 +
> >  1 file changed, 1 insertion(+)
> >
> > diff --git a/drivers/clk/clk_fixed_rate.c
> > b/drivers/clk/clk_fixed_rate.c index 069e643fbc..debada1463 100644
> > --- a/drivers/clk/clk_fixed_rate.c
> > +++ b/drivers/clk/clk_fixed_rate.c
> > @@ -45,4 +45,5 @@ U_BOOT_DRIVER(clk_fixed_rate) = {
> >  	.ofdata_to_platdata = clk_fixed_rate_ofdata_to_platdata,
> >  	.platdata_auto_alloc_size = sizeof(struct clk_fixed_rate),
> >  	.ops = &clk_fixed_rate_ops,
> > +	.flags = DM_FLAG_PRE_RELOC,
> >  };
> 
> This probably shall be done with proper dts file (from TPC70 - imx6q
> conversion code):

My understanding is DM_FLAG_PRE_RELOC will let the driver could be used
before relocation. The dts u-boot,dm-spl or u-boot,dm-pre-reloc
is just to mark the device could be used at the corresponding stage.
Only modify dts will not make it work without the DM_FLAG_PRE_RELOC,
Right?

Thanks,
Peng.

> 
> +#include "imx6qdl-u-boot.dtsi"
> +
> +/ {
> +	clocks {
> +		u-boot,dm-spl;
> +		osc {
> +			u-boot,dm-spl;
> +		};
> +	};
> +};
> +
> +&clks {
> +	u-boot,dm-pre-reloc;
> +};
> 
> 
> 
> Best regards,
> 
> Lukasz Majewski
> 
> --
> 
> DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
> HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
> Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email:
> lukma at denx.de

[U-Boot] [i.MX8MM+CCF 12/41] clk: fixed_rate: add pre reloc flag

[Bin Meng]

Hi Peng,

On Tue, May 7, 2019 at 9:30 PM Peng Fan <peng.fan@nxp.com> wrote:
>
> > Subject: Re: [i.MX8MM+CCF 12/41] clk: fixed_rate: add pre reloc flag
> >
> > On Tue, 30 Apr 2019 10:18:12 +0000
> > Peng Fan <peng.fan@nxp.com> wrote:
> >
> > > Add pre reloc flag to use this driver before relocation
> > >
> > > Signed-off-by: Peng Fan <peng.fan@nxp.com>
> > > ---
> > >  drivers/clk/clk_fixed_rate.c | 1 +
> > >  1 file changed, 1 insertion(+)
> > >
> > > diff --git a/drivers/clk/clk_fixed_rate.c
> > > b/drivers/clk/clk_fixed_rate.c index 069e643fbc..debada1463 100644
> > > --- a/drivers/clk/clk_fixed_rate.c
> > > +++ b/drivers/clk/clk_fixed_rate.c
> > > @@ -45,4 +45,5 @@ U_BOOT_DRIVER(clk_fixed_rate) = {
> > >     .ofdata_to_platdata = clk_fixed_rate_ofdata_to_platdata,
> > >     .platdata_auto_alloc_size = sizeof(struct clk_fixed_rate),
> > >     .ops = &clk_fixed_rate_ops,
> > > +   .flags = DM_FLAG_PRE_RELOC,
> > >  };
> >
> > This probably shall be done with proper dts file (from TPC70 - imx6q
> > conversion code):
>
> My understanding is DM_FLAG_PRE_RELOC will let the driver could be used
> before relocation. The dts u-boot,dm-spl or u-boot,dm-pre-reloc
> is just to mark the device could be used at the corresponding stage.
> Only modify dts will not make it work without the DM_FLAG_PRE_RELOC,
> Right?
>

I think your understanding is correct. For device tree that cannot be
modified by U-Boot, eg: DT passed from previous bootloader, the only
way to support pre-relocation binding is to add DM_FLAG_PRE_RELOC in
the U-Boot driver.

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

Regards,
Bin

[U-Boot] [i.MX8MM+CCF 08/41] clk: export mux/divider ops

[Lukasz Majewski]

On Tue, 7 May 2019 13:25:00 +0000
Peng Fan <peng.fan@nxp.com> wrote:

> > Subject: Re: [i.MX8MM+CCF 08/41] clk: export mux/divider ops
> > 
> > On Tue, 30 Apr 2019 10:17:58 +0000
> > Peng Fan <peng.fan@nxp.com> wrote:
> >   
> > > Export mux/divider ops for composite usage
> > >
> > > Signed-off-by: Peng Fan <peng.fan@nxp.com>
> > > ---
> > >  include/linux/clk-provider.h | 1 +
> > >  1 file changed, 1 insertion(+)
> > >
> > > diff --git a/include/linux/clk-provider.h
> > > b/include/linux/clk-provider.h index 216095d28c..a60cf6e833 100644
> > > --- a/include/linux/clk-provider.h
> > > +++ b/include/linux/clk-provider.h
> > > @@ -83,6 +83,7 @@ struct clk_divider {
> > >  #define CLK_DIVIDER_ROUND_CLOSEST	BIT(4)
> > >  #define CLK_DIVIDER_READ_ONLY		BIT(5)
> > >  #define CLK_DIVIDER_MAX_AT_ZERO		BIT(6)
> > > +extern const struct clk_ops clk_divider_ops;
> > >  
> > 
> > Why do we need to export clk_divider_ops? Why iMX8MM requires it?  
> 
> 
> The composite driver will use that to set ops for divider clk inside
> composite clk.

Please then write a detailed rationale for this change in commit
message or a comment in the header file.

The one from the original message seems to be not enough.
 

> The Linux CCF also exports it.
> 
> You could check the clk-composite-imx8m and clk-composite driver in
> this patchset.
> 
> Regards,
> Peng.
> 
> >   
> > >  struct clk_fixed_factor {
> > >  	struct clk	clk;  
> > 
> > 
> > 
> > 
> > Best regards,
> > 
> > Lukasz Majewski
> > 
> > --
> > 
> > DENX Software Engineering GmbH,      Managing Director: Wolfgang
> > Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell,
> > Germany Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email:
> > lukma at denx.de  




Best regards,

Lukasz Majewski

--

DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email: lukma at denx.de
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[U-Boot] [i.MX8MM+CCF 08/41] clk: export mux/divider ops

[Peng Fan]

> Subject: Re: [i.MX8MM+CCF 08/41] clk: export mux/divider ops
> 
> On Tue, 7 May 2019 13:25:00 +0000
> Peng Fan <peng.fan@nxp.com> wrote:
> 
> > > Subject: Re: [i.MX8MM+CCF 08/41] clk: export mux/divider ops
> > >
> > > On Tue, 30 Apr 2019 10:17:58 +0000
> > > Peng Fan <peng.fan@nxp.com> wrote:
> > >
> > > > Export mux/divider ops for composite usage
> > > >
> > > > Signed-off-by: Peng Fan <peng.fan@nxp.com>
> > > > ---
> > > >  include/linux/clk-provider.h | 1 +
> > > >  1 file changed, 1 insertion(+)
> > > >
> > > > diff --git a/include/linux/clk-provider.h
> > > > b/include/linux/clk-provider.h index 216095d28c..a60cf6e833 100644
> > > > --- a/include/linux/clk-provider.h
> > > > +++ b/include/linux/clk-provider.h
> > > > @@ -83,6 +83,7 @@ struct clk_divider {
> > > >  #define CLK_DIVIDER_ROUND_CLOSEST	BIT(4)
> > > >  #define CLK_DIVIDER_READ_ONLY		BIT(5)
> > > >  #define CLK_DIVIDER_MAX_AT_ZERO		BIT(6)
> > > > +extern const struct clk_ops clk_divider_ops;
> > > >
> > >
> > > Why do we need to export clk_divider_ops? Why iMX8MM requires it?
> >
> >
> > The composite driver will use that to set ops for divider clk inside
> > composite clk.
> 
> Please then write a detailed rationale for this change in commit message or a
> comment in the header file.
> 
> The one from the original message seems to be not enough.

Will fix in new version.

Thanks,
Peng.

> 
> 
> > The Linux CCF also exports it.
> >
> > You could check the clk-composite-imx8m and clk-composite driver in
> > this patchset.
> >
> > Regards,
> > Peng.
> >
> > >
> > > >  struct clk_fixed_factor {
> > > >  	struct clk	clk;
> > >
> > >
> > >
> > >
> > > Best regards,
> > >
> > > Lukasz Majewski
> > >
> > > --
> > >
> > > DENX Software Engineering GmbH,      Managing Director: Wolfgang
> > > Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell,
> > > Germany Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email:
> > > lukma at denx.de
> 
> 
> 
> 
> Best regards,
> 
> Lukasz Majewski
> 
> --
> 
> DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
> HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
> Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email:
> lukma at denx.de

[U-Boot] [i.MX8MM+CCF 11/41] clk: fixed_rate: export clk_fixed_rate

[Lukasz Majewski]

On Tue, 7 May 2019 13:27:45 +0000
Peng Fan <peng.fan@nxp.com> wrote:

> > Subject: Re: [i.MX8MM+CCF 11/41] clk: fixed_rate: export
> > clk_fixed_rate
> > 
> > Hi Peng,
> >   
> > > Export the structure for others to use.
> > >
> > > Signed-off-by: Peng Fan <peng.fan@nxp.com>
> > > ---
> > >  drivers/clk/clk_fixed_rate.c | 8 +-------
> > > include/linux/clk-provider.h | 7 +++++++
> > >  2 files changed, 8 insertions(+), 7 deletions(-)
> > >
> > > diff --git a/drivers/clk/clk_fixed_rate.c
> > > b/drivers/clk/clk_fixed_rate.c index 089f060a23..069e643fbc 100644
> > > --- a/drivers/clk/clk_fixed_rate.c
> > > +++ b/drivers/clk/clk_fixed_rate.c
> > > @@ -6,13 +6,7 @@
> > >  #include <common.h>
> > >  #include <clk-uclass.h>
> > >  #include <dm.h>
> > > -
> > > -struct clk_fixed_rate {
> > > -	struct clk clk;
> > > -	unsigned long fixed_rate;
> > > -};
> > > -
> > > -#define to_clk_fixed_rate(dev)	((struct clk_fixed_rate
> > > *)dev_get_platdata(dev)) +#include <linux/clk-provider.h>
> > >
> > >  static ulong clk_fixed_rate_get_rate(struct clk *clk)  { diff
> > > --git a/include/linux/clk-provider.h
> > > b/include/linux/clk-provider.h index 3ed0db86d2..b2bed768b6 100644
> > > --- a/include/linux/clk-provider.h
> > > +++ b/include/linux/clk-provider.h
> > > @@ -112,6 +112,13 @@ struct clk_fixed_factor {  #define
> > > to_clk_fixed_factor(_clk) container_of(_clk, struct
> > > clk_fixed_factor,\ clk)
> > >
> > > +struct clk_fixed_rate {
> > > +	struct clk clk;
> > > +	unsigned long fixed_rate;
> > > +};  
> > 
> > I think that this struct shall stay where it was. Moreover, the
> > clk-provider.h is not the API to be used by other parts of the
> > clock API.
> > 
> > The clk_fixed_rate shall be accessed via get_rate() only and in
> > IMX6Q it is available in early SPL (parsed from dts /clocks
> > property - the 24MHz OSC) 
> > > +
> > > +#define to_clk_fixed_rate(dev)	((struct clk_fixed_rate
> > > *)dev_get_platdata(dev)) +
> > >  int clk_register(struct clk *clk, const char *drv_name,
> > >  		 ulong drv_data, const char *name,
> > >  		 const char *parent_name);  
> > 
> > Please explain why iMX8MM needs such global export?  
> 
> In clk-imx8mm.c, first configure ARM clk to osc24M fixed clk to
> change pll clock.
> +       /* Configure ARM to osc24M */
> +       clk_get_by_id(IMX8MM_CLK_A53_SRC, &clkp);
> +       uclass_get_device_by_name(UCLASS_CLK, "clock-osc-24m", &devp);
> +       clkp1 = &to_clk_fixed_rate(devp)->clk;
> +       clk_set_parent(clkp, clkp1);

This code looks a bit strange to me. Why imx8mm sets parent here?

In the imx6q I write "osc" as a part of the clock tree:

        clk_dm(IMX6QDL_CLK_PLL2,
               imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll2_bus", "osc",
                             base + 0x30, 0x1));

And here the parent is set as "osc".

Moreover, the "osc" or in your case "clock-osc-24m" shall be available
in "clocks" DTS node and hence parsed / setup from there (and be
available in the clk uclass list).

> +
> +       /* Configure ARM PLL to 1.2GHz */
> +       clk_get_by_id(IMX8MM_ARM_PLL, &clkp1);
> +       clk_set_rate(clkp1, 1200000000UL);

Shouldn't this be set in DTS ? As it is now - it seems like a hardcoded
value for early SPL clock setup. Am I right?

> +       clk_get_by_id(IMX8MM_ARM_PLL_OUT, &clkp1);
> +       clk_enable(clkp1);
> +       clk_set_parent(clkp, clkp1);
> +
> +       /* Configure DIV to 1.2GHz */
> +       clk_get_by_id(IMX8MM_CLK_A53_DIV, &clkp1);
> +       clk_set_rate(clkp1, 1200000000UL);
> 
> Regards,
> Peng.
> 
> > 
> > 
> > Best regards,
> > 
> > Lukasz Majewski
> > 
> > --
> > 
> > DENX Software Engineering GmbH,      Managing Director: Wolfgang
> > Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell,
> > Germany Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email:
> > lukma at denx.de  




Best regards,

Lukasz Majewski

--

DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email: lukma at denx.de
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[U-Boot] [i.MX8MM+CCF 11/41] clk: fixed_rate: export clk_fixed_rate

[Peng Fan]

> -----Original Message-----
> From: Lukasz Majewski [mailto:lukma at denx.de]
> Sent: 2019年5月8日 14:46
> To: Peng Fan <peng.fan@nxp.com>
> Cc: sbabic at denx.de; festevam at gmail.com; dl-uboot-imx
> <uboot-imx@nxp.com>; sjg at chromium.org; jagan at amarulasolutions.com;
> sr at denx.de; u-boot at lists.denx.de; trini at konsulko.com
> Subject: Re: [i.MX8MM+CCF 11/41] clk: fixed_rate: export clk_fixed_rate
> 
> On Tue, 7 May 2019 13:27:45 +0000
> Peng Fan <peng.fan@nxp.com> wrote:
> 
> > > Subject: Re: [i.MX8MM+CCF 11/41] clk: fixed_rate: export
> > > clk_fixed_rate
> > >
> > > Hi Peng,
> > >
> > > > Export the structure for others to use.
> > > >
> > > > Signed-off-by: Peng Fan <peng.fan@nxp.com>
> > > > ---
> > > >  drivers/clk/clk_fixed_rate.c | 8 +-------
> > > > include/linux/clk-provider.h | 7 +++++++
> > > >  2 files changed, 8 insertions(+), 7 deletions(-)
> > > >
> > > > diff --git a/drivers/clk/clk_fixed_rate.c
> > > > b/drivers/clk/clk_fixed_rate.c index 089f060a23..069e643fbc 100644
> > > > --- a/drivers/clk/clk_fixed_rate.c
> > > > +++ b/drivers/clk/clk_fixed_rate.c
> > > > @@ -6,13 +6,7 @@
> > > >  #include <common.h>
> > > >  #include <clk-uclass.h>
> > > >  #include <dm.h>
> > > > -
> > > > -struct clk_fixed_rate {
> > > > -	struct clk clk;
> > > > -	unsigned long fixed_rate;
> > > > -};
> > > > -
> > > > -#define to_clk_fixed_rate(dev)	((struct clk_fixed_rate
> > > > *)dev_get_platdata(dev)) +#include <linux/clk-provider.h>
> > > >
> > > >  static ulong clk_fixed_rate_get_rate(struct clk *clk)  { diff
> > > > --git a/include/linux/clk-provider.h
> > > > b/include/linux/clk-provider.h index 3ed0db86d2..b2bed768b6 100644
> > > > --- a/include/linux/clk-provider.h
> > > > +++ b/include/linux/clk-provider.h
> > > > @@ -112,6 +112,13 @@ struct clk_fixed_factor {  #define
> > > > to_clk_fixed_factor(_clk) container_of(_clk, struct
> > > > clk_fixed_factor,\ clk)
> > > >
> > > > +struct clk_fixed_rate {
> > > > +	struct clk clk;
> > > > +	unsigned long fixed_rate;
> > > > +};
> > >
> > > I think that this struct shall stay where it was. Moreover, the
> > > clk-provider.h is not the API to be used by other parts of the clock
> > > API.
> > >
> > > The clk_fixed_rate shall be accessed via get_rate() only and in
> > > IMX6Q it is available in early SPL (parsed from dts /clocks property
> > > - the 24MHz OSC)
> > > > +
> > > > +#define to_clk_fixed_rate(dev)	((struct clk_fixed_rate
> > > > *)dev_get_platdata(dev)) +
> > > >  int clk_register(struct clk *clk, const char *drv_name,
> > > >  		 ulong drv_data, const char *name,
> > > >  		 const char *parent_name);
> > >
> > > Please explain why iMX8MM needs such global export?
> >
> > In clk-imx8mm.c, first configure ARM clk to osc24M fixed clk to change
> > pll clock.
> > +       /* Configure ARM to osc24M */
> > +       clk_get_by_id(IMX8MM_CLK_A53_SRC, &clkp);
> > +       uclass_get_device_by_name(UCLASS_CLK, "clock-osc-24m",
> &devp);
> > +       clkp1 = &to_clk_fixed_rate(devp)->clk;
> > +       clk_set_parent(clkp, clkp1);
> 
> This code looks a bit strange to me. Why imx8mm sets parent here?

The A53 clk could not change on the fly. There is a mux here, one is PLL, one is OSC,
And there are others. If we want to change the pll clock which is currently
being used by A53, we need first switch the A53 clk to source from OSC,
then change pll clock, then switch A53 clk back to PLL.

> 
> In the imx6q I write "osc" as a part of the clock tree:
> 
>         clk_dm(IMX6QDL_CLK_PLL2,
>                imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll2_bus", "osc",
>                              base + 0x30, 0x1));
> 
> And here the parent is set as "osc".
> 
> Moreover, the "osc" or in your case "clock-osc-24m" shall be available in
> "clocks" DTS node and hence parsed / setup from there (and be available in
> the clk uclass list).
> 
> > +
> > +       /* Configure ARM PLL to 1.2GHz */
> > +       clk_get_by_id(IMX8MM_ARM_PLL, &clkp1);
> > +       clk_set_rate(clkp1, 1200000000UL);
> 
> Shouldn't this be set in DTS ? As it is now - it seems like a hardcoded value for
> early SPL clock setup. Am I right?

You mean get freq from cpu opp and set cpu freq? I do not have good idea
how to set in DTS.

Thanks,
Peng.

> 
> > +       clk_get_by_id(IMX8MM_ARM_PLL_OUT, &clkp1);
> > +       clk_enable(clkp1);
> > +       clk_set_parent(clkp, clkp1);
> > +
> > +       /* Configure DIV to 1.2GHz */
> > +       clk_get_by_id(IMX8MM_CLK_A53_DIV, &clkp1);
> > +       clk_set_rate(clkp1, 1200000000UL);
> >
> > Regards,
> > Peng.
> >
> > >
> > >
> > > Best regards,
> > >
> > > Lukasz Majewski
> > >
> > > --
> > >
> > > DENX Software Engineering GmbH,      Managing Director: Wolfgang
> > > Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell,
> > > Germany Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email:
> > > lukma at denx.de
> 
> 
> 
> 
> Best regards,
> 
> Lukasz Majewski
> 
> --
> 
> DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
> HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
> Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email:
> lukma at denx.de

[U-Boot] [i.MX8MM+CCF 12/41] clk: fixed_rate: add pre reloc flag

[Lukasz Majewski]

On Tue, 7 May 2019 13:29:41 +0000
Peng Fan <peng.fan@nxp.com> wrote:

> > Subject: Re: [i.MX8MM+CCF 12/41] clk: fixed_rate: add pre reloc flag
> > 
> > On Tue, 30 Apr 2019 10:18:12 +0000
> > Peng Fan <peng.fan@nxp.com> wrote:
> >   
> > > Add pre reloc flag to use this driver before relocation
> > >
> > > Signed-off-by: Peng Fan <peng.fan@nxp.com>
> > > ---
> > >  drivers/clk/clk_fixed_rate.c | 1 +
> > >  1 file changed, 1 insertion(+)
> > >
> > > diff --git a/drivers/clk/clk_fixed_rate.c
> > > b/drivers/clk/clk_fixed_rate.c index 069e643fbc..debada1463 100644
> > > --- a/drivers/clk/clk_fixed_rate.c
> > > +++ b/drivers/clk/clk_fixed_rate.c
> > > @@ -45,4 +45,5 @@ U_BOOT_DRIVER(clk_fixed_rate) = {
> > >  	.ofdata_to_platdata = clk_fixed_rate_ofdata_to_platdata,
> > >  	.platdata_auto_alloc_size = sizeof(struct
> > > clk_fixed_rate), .ops = &clk_fixed_rate_ops,
> > > +	.flags = DM_FLAG_PRE_RELOC,
> > >  };  
> > 
> > This probably shall be done with proper dts file (from TPC70 - imx6q
> > conversion code):  
> 
> My understanding is DM_FLAG_PRE_RELOC will let the driver could be
> used before relocation. 

I think that there is OR -> DM_FLAG_PRE_RELOC OR DTS
attribute (u-boot,dm-spl {pre-reloc}) to use device in early SPL.

Please look into drivers/core/lists.c Line 175:

if (pre_reloc_only) {
if (!dm_ofnode_pre_reloc(node)·&&
	!(entry->flags & DM_FLAG_PRE_RELOC))
	return 0;
}                                                                                                                                                                                                                             

We do not bind device only if there is NO DM_FLAG_PRE_RELOC set AND the
u-boot,dm-* property is not set in corresponding DTS node.

> The dts u-boot,dm-spl or u-boot,dm-pre-reloc
> is just to mark the device could be used at the corresponding stage.
> Only modify dts will not make it work without the DM_FLAG_PRE_RELOC,
> Right?
> 
> Thanks,
> Peng.
> 
> > 
> > +#include "imx6qdl-u-boot.dtsi"
> > +
> > +/ {
> > +	clocks {
> > +		u-boot,dm-spl;
> > +		osc {
> > +			u-boot,dm-spl;
> > +		};
> > +	};
> > +};
> > +
> > +&clks {
> > +	u-boot,dm-pre-reloc;
> > +};
> > 
> > 
> > 
> > Best regards,
> > 
> > Lukasz Majewski
> > 
> > --
> > 
> > DENX Software Engineering GmbH,      Managing Director: Wolfgang
> > Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell,
> > Germany Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email:
> > lukma at denx.de  




Best regards,

Lukasz Majewski

--

DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email: lukma at denx.de
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[U-Boot] [i.MX8MM+CCF 12/41] clk: fixed_rate: add pre reloc flag

[Lukasz Majewski]

On Tue, 7 May 2019 22:00:14 +0800
Bin Meng <bmeng.cn@gmail.com> wrote:

> Hi Peng,
> 
> On Tue, May 7, 2019 at 9:30 PM Peng Fan <peng.fan@nxp.com> wrote:
> >  
> > > Subject: Re: [i.MX8MM+CCF 12/41] clk: fixed_rate: add pre reloc
> > > flag
> > >
> > > On Tue, 30 Apr 2019 10:18:12 +0000
> > > Peng Fan <peng.fan@nxp.com> wrote:
> > >  
> > > > Add pre reloc flag to use this driver before relocation
> > > >
> > > > Signed-off-by: Peng Fan <peng.fan@nxp.com>
> > > > ---
> > > >  drivers/clk/clk_fixed_rate.c | 1 +
> > > >  1 file changed, 1 insertion(+)
> > > >
> > > > diff --git a/drivers/clk/clk_fixed_rate.c
> > > > b/drivers/clk/clk_fixed_rate.c index 069e643fbc..debada1463
> > > > 100644 --- a/drivers/clk/clk_fixed_rate.c
> > > > +++ b/drivers/clk/clk_fixed_rate.c
> > > > @@ -45,4 +45,5 @@ U_BOOT_DRIVER(clk_fixed_rate) = {
> > > >     .ofdata_to_platdata = clk_fixed_rate_ofdata_to_platdata,
> > > >     .platdata_auto_alloc_size = sizeof(struct clk_fixed_rate),
> > > >     .ops = &clk_fixed_rate_ops,
> > > > +   .flags = DM_FLAG_PRE_RELOC,
> > > >  };  
> > >
> > > This probably shall be done with proper dts file (from TPC70 -
> > > imx6q conversion code):  
> >
> > My understanding is DM_FLAG_PRE_RELOC will let the driver could be
> > used before relocation. The dts u-boot,dm-spl or u-boot,dm-pre-reloc
> > is just to mark the device could be used at the corresponding stage.
> > Only modify dts will not make it work without the DM_FLAG_PRE_RELOC,
> > Right?
> >  
> 
> I think your understanding is correct. For device tree that cannot be
> modified by U-Boot, eg: DT passed from previous bootloader, the only
> way to support pre-relocation binding is to add DM_FLAG_PRE_RELOC in
> the U-Boot driver.

But as fair as I understand - the discussion is about SPL, not u-boot's
proper pre-location stage.

Please correct me if I'm wrong, but the recent code removes from
u-boot's proper DTS u-boot,dm-* properties.

> 
> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
> 
> Regards,
> Bin




Best regards,

Lukasz Majewski

--

DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email: lukma at denx.de
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[U-Boot] [i.MX8MM+CCF 12/41] clk: fixed_rate: add pre reloc flag

[Peng Fan]

> Subject: Re: [i.MX8MM+CCF 12/41] clk: fixed_rate: add pre reloc flag
> 
> On Tue, 7 May 2019 13:29:41 +0000
> Peng Fan <peng.fan@nxp.com> wrote:
> 
> > > Subject: Re: [i.MX8MM+CCF 12/41] clk: fixed_rate: add pre reloc flag
> > >
> > > On Tue, 30 Apr 2019 10:18:12 +0000
> > > Peng Fan <peng.fan@nxp.com> wrote:
> > >
> > > > Add pre reloc flag to use this driver before relocation
> > > >
> > > > Signed-off-by: Peng Fan <peng.fan@nxp.com>
> > > > ---
> > > >  drivers/clk/clk_fixed_rate.c | 1 +
> > > >  1 file changed, 1 insertion(+)
> > > >
> > > > diff --git a/drivers/clk/clk_fixed_rate.c
> > > > b/drivers/clk/clk_fixed_rate.c index 069e643fbc..debada1463 100644
> > > > --- a/drivers/clk/clk_fixed_rate.c
> > > > +++ b/drivers/clk/clk_fixed_rate.c
> > > > @@ -45,4 +45,5 @@ U_BOOT_DRIVER(clk_fixed_rate) = {
> > > >  	.ofdata_to_platdata = clk_fixed_rate_ofdata_to_platdata,
> > > >  	.platdata_auto_alloc_size = sizeof(struct clk_fixed_rate), .ops
> > > > = &clk_fixed_rate_ops,
> > > > +	.flags = DM_FLAG_PRE_RELOC,
> > > >  };
> > >
> > > This probably shall be done with proper dts file (from TPC70 - imx6q
> > > conversion code):
> >
> > My understanding is DM_FLAG_PRE_RELOC will let the driver could be
> > used before relocation.
> 
> I think that there is OR -> DM_FLAG_PRE_RELOC OR DTS attribute
> (u-boot,dm-spl {pre-reloc}) to use device in early SPL.
> 
> Please look into drivers/core/lists.c Line 175:
> 
> if (pre_reloc_only) {
> if (!dm_ofnode_pre_reloc(node)·&&
> 	!(entry->flags & DM_FLAG_PRE_RELOC))
> 	return 0;
> }

ok, this is new code from Bin.
According this code, only need dts change is enough, no need this driver flag.
I'll drop this patch.

Thanks,
Peng.


> 
> We do not bind device only if there is NO DM_FLAG_PRE_RELOC set AND the
> u-boot,dm-* property is not set in corresponding DTS node.
> 
> > The dts u-boot,dm-spl or u-boot,dm-pre-reloc is just to mark the
> > device could be used at the corresponding stage.
> > Only modify dts will not make it work without the DM_FLAG_PRE_RELOC,
> > Right?
> >
> > Thanks,
> > Peng.
> >
> > >
> > > +#include "imx6qdl-u-boot.dtsi"
> > > +
> > > +/ {
> > > +	clocks {
> > > +		u-boot,dm-spl;
> > > +		osc {
> > > +			u-boot,dm-spl;
> > > +		};
> > > +	};
> > > +};
> > > +
> > > +&clks {
> > > +	u-boot,dm-pre-reloc;
> > > +};
> > >
> > >
> > >
> > > Best regards,
> > >
> > > Lukasz Majewski
> > >
> > > --
> > >
> > > DENX Software Engineering GmbH,      Managing Director: Wolfgang
> > > Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell,
> > > Germany Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email:
> > > lukma at denx.de
> 
> 
> 
> 
> Best regards,
> 
> Lukasz Majewski
> 
> --
> 
> DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
> HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
> Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email:
> lukma at denx.de

[U-Boot] [i.MX8MM+CCF 04/41] clk: use clk_dev_binded

[Lukasz Majewski]

On Tue, 30 Apr 2019 10:17:43 +0000
Peng Fan <peng.fan@nxp.com> wrote:

> Preparing to support composite clk.
> 
> Signed-off-by: Peng Fan <peng.fan@nxp.com>
> ---
>  drivers/clk/clk-divider.c | 4 ++--
>  drivers/clk/clk-mux.c     | 6 ++++--
>  2 files changed, 6 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c
> index 1d2c1b1ec4..2f09e0bb58 100644
> --- a/drivers/clk/clk-divider.c
> +++ b/drivers/clk/clk-divider.c
> @@ -69,8 +69,8 @@ unsigned long divider_recalc_rate(struct clk *hw,
> unsigned long parent_rate, 
>  static ulong clk_divider_recalc_rate(struct clk *clk)
>  {
> -	struct clk_divider *divider =
> -		to_clk_divider((struct clk
> *)dev_get_driver_data(clk->dev));
> +	struct clk_divider *divider =
> to_clk_divider(clk_dev_binded(clk) ?
> +			(struct clk
> *)dev_get_driver_data(clk->dev) : clk); unsigned long parent_rate =
> clk_get_parent_rate(clk); unsigned int val;
>  
> diff --git a/drivers/clk/clk-mux.c b/drivers/clk/clk-mux.c
> index 2c85f2052c..55fc97367a 100644
> --- a/drivers/clk/clk-mux.c
> +++ b/drivers/clk/clk-mux.c
> @@ -35,7 +35,8 @@
>  int clk_mux_val_to_index(struct clk *clk, u32 *table, unsigned int
> flags, unsigned int val)
>  {
> -	struct clk_mux *mux = to_clk_mux(clk);
> +	struct clk_mux *mux = to_clk_mux(clk_dev_binded(clk) ?
> +			(struct clk
> *)dev_get_driver_data(clk->dev) : clk); int num_parents =
> mux->num_parents; 
>  	if (table) {
> @@ -61,7 +62,8 @@ int clk_mux_val_to_index(struct clk *clk, u32
> *table, unsigned int flags, 
>  static u8 clk_mux_get_parent(struct clk *clk)
>  {
> -	struct clk_mux *mux = to_clk_mux(clk);
> +	struct clk_mux *mux = to_clk_mux(clk_dev_binded(clk) ?
> +			(struct clk
> *)dev_get_driver_data(clk->dev) : clk); u32 val;

Maybe the 

(clk_dev_binded(clk) ? (struct clk *)dev_get_driver_data(clk->dev) :
clk)

Could be an inline function or macro?

>  
>  	val = readl(mux->reg) >> mux->shift;




Best regards,

Lukasz Majewski

--

DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email: lukma at denx.de
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[U-Boot] [i.MX8MM+CCF 03/41] clk: introduce clk_dev_binded

[Lukasz Majewski]

On Tue, 7 May 2019 13:22:24 +0000
Peng Fan <peng.fan@nxp.com> wrote:

> > Subject: Re: [i.MX8MM+CCF 03/41] clk: introduce clk_dev_binded
> > 
> > On Tue, 30 Apr 2019 10:17:40 +0000
> > Peng Fan <peng.fan@nxp.com> wrote:
> >   
> > > When support Clock Common Framework, U-Boot use dev for clk tree
> > > information, there is no clk->parent.  
> > 
> > There is a function in clk uclass named:
> > clk_get_parent() to provide parent of the clock.
> >   
> > > When
> > > support composite clk, it contains mux/gate/divider, but the
> > > mux/gate/divider is not binded with device.  
> > 
> > There is a binding:
> > struct clk_pllv3 {
> > 	struct clk	clk;
> > 	...
> > };
> > 
> > The clk.dev points to corresponding device.
> > 
> > In the opposite direction we do have dev->driver_data, which points
> > to struct clk embedded in for example struct clk_pllv3.
> > (as struct clk_pllv3 and struct clk share the same address it is up
> > to us to cast it properly).
> > 
> > I've written my thoughts and considerations about using
> > dev->private and dev->driver_data in the patch cover letter [1]
> > 
> >   
> > > So we could not use dev_get_driver_data to get the correct
> > > clk_mux/gate/divider.  
> > 
> > Maybe I've overlooked something, but dev_get_driver_data() shall
> > provide correct reference to udevice.  
> 
> A composite clk contains a mux/gate/divider clk. Only the composite
> clk needs to binded with a udevice.

So, if I understood correctly we do need to have another reference to
udevice (or clock)?

Please correct my understanding:

- Composite clock would use clk->dev (to have pointer to struct udevice)
  and dev->driver_data to have pointer to clk.

- Then we use udevice flag DM_FLAG_BOUND to indicate if this device has
  other udevices (i.e. clk) bound.

- If it has bounded device then we use dev->driver_data to get it's
  struct clk (or clock IP - like mux). If not, then we just use this
  clk.

Considering the above - the commit message needs detailed explanation
of the "binding" concept.

> The mux/gate/divider inside a
> composite clk should not bind a device, because they needs to be
> hidden from dm tree or clk dumps.
> 
> If bind the mux/gate/divider insides a composite clk, that will be
> mess.

But the composite clock itself would be printed in 'dm tree' ?

If yes, maybe we can add some kind of indication that it is a
"container" and that it has some clocks "binded" ?

> The reason to introduce composite clk is to make clk tree
> cleaner/simplier.

Ok. No problem with this.

> 
> Regards,
> Peng.
> 
> >   
> > > So add clk_dev_binded to let
> > > choose the correct method.
> > >  
> > 
> > [1] - http://patchwork.ozlabs.org/cover/1090669/
> >   
> > > Signed-off-by: Peng Fan <peng.fan@nxp.com>
> > > ---
> > >  drivers/clk/clk.c | 8 ++++++++
> > >  include/clk.h     | 9 +++++++++
> > >  2 files changed, 17 insertions(+)
> > >
> > > diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c index
> > > 0a0fffb50b..025bb99ecc 100644
> > > --- a/drivers/clk/clk.c
> > > +++ b/drivers/clk/clk.c
> > > @@ -54,3 +54,11 @@ const char *clk_hw_get_name(const struct clk
> > > *hw) {
> > >  	return hw->dev->name;
> > >  }
> > > +
> > > +bool clk_dev_binded(struct clk *clk)
> > > +{
> > > +	if (clk->dev && (clk->dev->flags & DM_FLAG_BOUND))
> > > +		return true;
> > > +
> > > +	return false;
> > > +}
> > > diff --git a/include/clk.h b/include/clk.h index
> > > a4ecca9fbc..8199119d01 100644
> > > --- a/include/clk.h
> > > +++ b/include/clk.h
> > > @@ -337,4 +337,13 @@ static inline bool clk_valid(struct clk *clk)
> > >   * @return zero on success, or -ENOENT on error
> > >   */
> > >  int clk_get_by_id(ulong id, struct clk **clkp);
> > > +
> > > +/**
> > > + * clk_dev_binded() - Check whether the clk has a device binded
> > > + *
> > > + * @clk		A pointer to the clk
> > > + *
> > > + * @return true on binded, or false on no  */ bool
> > > +clk_dev_binded(struct clk *clk);
> > >  #endif  
> > 
> > 
> > 
> > 
> > Best regards,
> > 
> > Lukasz Majewski
> > 
> > --
> > 
> > DENX Software Engineering GmbH,      Managing Director: Wolfgang
> > Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell,
> > Germany Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email:
> > lukma at denx.de  




Best regards,

Lukasz Majewski

--

DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email: lukma at denx.de
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[U-Boot] [i.MX8MM+CCF 11/41] clk: fixed_rate: export clk_fixed_rate

[Lukasz Majewski]

On Wed, 8 May 2019 06:51:46 +0000
Peng Fan <peng.fan@nxp.com> wrote:

> > -----Original Message-----
> > From: Lukasz Majewski [mailto:lukma at denx.de]
> > Sent: 2019年5月8日 14:46
> > To: Peng Fan <peng.fan@nxp.com>
> > Cc: sbabic at denx.de; festevam at gmail.com; dl-uboot-imx
> > <uboot-imx@nxp.com>; sjg at chromium.org; jagan at amarulasolutions.com;
> > sr at denx.de; u-boot at lists.denx.de; trini at konsulko.com
> > Subject: Re: [i.MX8MM+CCF 11/41] clk: fixed_rate: export
> > clk_fixed_rate
> > 
> > On Tue, 7 May 2019 13:27:45 +0000
> > Peng Fan <peng.fan@nxp.com> wrote:
> >   
> > > > Subject: Re: [i.MX8MM+CCF 11/41] clk: fixed_rate: export
> > > > clk_fixed_rate
> > > >
> > > > Hi Peng,
> > > >  
> > > > > Export the structure for others to use.
> > > > >
> > > > > Signed-off-by: Peng Fan <peng.fan@nxp.com>
> > > > > ---
> > > > >  drivers/clk/clk_fixed_rate.c | 8 +-------
> > > > > include/linux/clk-provider.h | 7 +++++++
> > > > >  2 files changed, 8 insertions(+), 7 deletions(-)
> > > > >
> > > > > diff --git a/drivers/clk/clk_fixed_rate.c
> > > > > b/drivers/clk/clk_fixed_rate.c index 089f060a23..069e643fbc
> > > > > 100644 --- a/drivers/clk/clk_fixed_rate.c
> > > > > +++ b/drivers/clk/clk_fixed_rate.c
> > > > > @@ -6,13 +6,7 @@
> > > > >  #include <common.h>
> > > > >  #include <clk-uclass.h>
> > > > >  #include <dm.h>
> > > > > -
> > > > > -struct clk_fixed_rate {
> > > > > -	struct clk clk;
> > > > > -	unsigned long fixed_rate;
> > > > > -};
> > > > > -
> > > > > -#define to_clk_fixed_rate(dev)	((struct clk_fixed_rate
> > > > > *)dev_get_platdata(dev)) +#include <linux/clk-provider.h>
> > > > >
> > > > >  static ulong clk_fixed_rate_get_rate(struct clk *clk)  { diff
> > > > > --git a/include/linux/clk-provider.h
> > > > > b/include/linux/clk-provider.h index 3ed0db86d2..b2bed768b6
> > > > > 100644 --- a/include/linux/clk-provider.h
> > > > > +++ b/include/linux/clk-provider.h
> > > > > @@ -112,6 +112,13 @@ struct clk_fixed_factor {  #define
> > > > > to_clk_fixed_factor(_clk) container_of(_clk, struct
> > > > > clk_fixed_factor,\ clk)
> > > > >
> > > > > +struct clk_fixed_rate {
> > > > > +	struct clk clk;
> > > > > +	unsigned long fixed_rate;
> > > > > +};  
> > > >
> > > > I think that this struct shall stay where it was. Moreover, the
> > > > clk-provider.h is not the API to be used by other parts of the
> > > > clock API.
> > > >
> > > > The clk_fixed_rate shall be accessed via get_rate() only and in
> > > > IMX6Q it is available in early SPL (parsed from dts /clocks
> > > > property
> > > > - the 24MHz OSC)  
> > > > > +
> > > > > +#define to_clk_fixed_rate(dev)	((struct clk_fixed_rate
> > > > > *)dev_get_platdata(dev)) +
> > > > >  int clk_register(struct clk *clk, const char *drv_name,
> > > > >  		 ulong drv_data, const char *name,
> > > > >  		 const char *parent_name);  
> > > >
> > > > Please explain why iMX8MM needs such global export?  
> > >
> > > In clk-imx8mm.c, first configure ARM clk to osc24M fixed clk to
> > > change pll clock.
> > > +       /* Configure ARM to osc24M */
> > > +       clk_get_by_id(IMX8MM_CLK_A53_SRC, &clkp);
> > > +       uclass_get_device_by_name(UCLASS_CLK, "clock-osc-24m",  
> > &devp);  
> > > +       clkp1 = &to_clk_fixed_rate(devp)->clk;
> > > +       clk_set_parent(clkp, clkp1);  
> > 
> > This code looks a bit strange to me. Why imx8mm sets parent here?  
> 
> The A53 clk could not change on the fly. There is a mux here, one is
> PLL, one is OSC, And there are others. If we want to change the pll
> clock which is currently being used by A53, we need first switch the
> A53 clk to source from OSC, then change pll clock, then switch A53
> clk back to PLL.

The above description looks like a "standard" procedure for bypassing
PLL when it is going to be locked.

The same is also performed on IMX6Q:

https://elixir.bootlin.com/linux/v5.1/source/drivers/clk/imx/clk-imx6q.c#L88

But I've not ported that part from the original Linux source code.

> 
> > 
> > In the imx6q I write "osc" as a part of the clock tree:
> > 
> >         clk_dm(IMX6QDL_CLK_PLL2,
> >                imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll2_bus", "osc",
> >                              base + 0x30, 0x1));
> > 
> > And here the parent is set as "osc".
> > 
> > Moreover, the "osc" or in your case "clock-osc-24m" shall be
> > available in "clocks" DTS node and hence parsed / setup from there
> > (and be available in the clk uclass list).
> >   
> > > +
> > > +       /* Configure ARM PLL to 1.2GHz */
> > > +       clk_get_by_id(IMX8MM_ARM_PLL, &clkp1);
> > > +       clk_set_rate(clkp1, 1200000000UL);  
> > 
> > Shouldn't this be set in DTS ? As it is now - it seems like a
> > hardcoded value for early SPL clock setup. Am I right?  
> 
> You mean get freq from cpu opp and set cpu freq? I do not have good
> idea how to set in DTS.

I'm thinking about following description of the "osc" fixed clock:
https://elixir.bootlin.com/linux/v5.1/source/arch/arm/boot/dts/imx6qdl.dtsi#L64

and

http://git.denx.de/?p=u-boot/u-boot-imx.git;a=blob;f=arch/arm/dts/imx6qdl.dtsi;h=c0a94780087382a6e2805b7d6572f3e5e294e302;hb=HEAD#l53

The "fixed-clock" code has been adjusted to comply with the above DTS
(which is provided in pre-reloc SPL - even before console and ddr
setup).

(I had to use debug uart for debugging).

> 
> Thanks,
> Peng.
> 
> >   
> > > +       clk_get_by_id(IMX8MM_ARM_PLL_OUT, &clkp1);
> > > +       clk_enable(clkp1);
> > > +       clk_set_parent(clkp, clkp1);
> > > +
> > > +       /* Configure DIV to 1.2GHz */
> > > +       clk_get_by_id(IMX8MM_CLK_A53_DIV, &clkp1);
> > > +       clk_set_rate(clkp1, 1200000000UL);
> > >
> > > Regards,
> > > Peng.
> > >  
> > > >
> > > >
> > > > Best regards,
> > > >
> > > > Lukasz Majewski
> > > >
> > > > --
> > > >
> > > > DENX Software Engineering GmbH,      Managing Director: Wolfgang
> > > > Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194
> > > > Groebenzell, Germany Phone: (+49)-8142-66989-59 Fax:
> > > > (+49)-8142-66989-80 Email: lukma at denx.de  
> > 
> > 
> > 
> > 
> > Best regards,
> > 
> > Lukasz Majewski
> > 
> > --
> > 
> > DENX Software Engineering GmbH,      Managing Director: Wolfgang
> > Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell,
> > Germany Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email:
> > lukma at denx.de  




Best regards,

Lukasz Majewski

--

DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email: lukma at denx.de
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[U-Boot] [i.MX8MM+CCF 03/41] clk: introduce clk_dev_binded

[Peng Fan]

> -----Original Message-----
> From: Lukasz Majewski [mailto:lukma at denx.de]
> Sent: 2019年5月8日 15:31
> To: Peng Fan <peng.fan@nxp.com>
> Cc: sbabic at denx.de; festevam at gmail.com; dl-uboot-imx
> <uboot-imx@nxp.com>; sjg at chromium.org; jagan at amarulasolutions.com;
> sr at denx.de; u-boot at lists.denx.de; trini at konsulko.com
> Subject: Re: [i.MX8MM+CCF 03/41] clk: introduce clk_dev_binded
> 
> On Tue, 7 May 2019 13:22:24 +0000
> Peng Fan <peng.fan@nxp.com> wrote:
> 
> > > Subject: Re: [i.MX8MM+CCF 03/41] clk: introduce clk_dev_binded
> > >
> > > On Tue, 30 Apr 2019 10:17:40 +0000
> > > Peng Fan <peng.fan@nxp.com> wrote:
> > >
> > > > When support Clock Common Framework, U-Boot use dev for clk tree
> > > > information, there is no clk->parent.
> > >
> > > There is a function in clk uclass named:
> > > clk_get_parent() to provide parent of the clock.
> > >
> > > > When
> > > > support composite clk, it contains mux/gate/divider, but the
> > > > mux/gate/divider is not binded with device.
> > >
> > > There is a binding:
> > > struct clk_pllv3 {
> > > 	struct clk	clk;
> > > 	...
> > > };
> > >
> > > The clk.dev points to corresponding device.
> > >
> > > In the opposite direction we do have dev->driver_data, which points
> > > to struct clk embedded in for example struct clk_pllv3.
> > > (as struct clk_pllv3 and struct clk share the same address it is up
> > > to us to cast it properly).
> > >
> > > I've written my thoughts and considerations about using
> > > dev->private and dev->driver_data in the patch cover letter [1]
> > >
> > >
> > > > So we could not use dev_get_driver_data to get the correct
> > > > clk_mux/gate/divider.
> > >
> > > Maybe I've overlooked something, but dev_get_driver_data() shall
> > > provide correct reference to udevice.
> >
> > A composite clk contains a mux/gate/divider clk. Only the composite
> > clk needs to binded with a udevice.
> 
> So, if I understood correctly we do need to have another reference to udevice
> (or clock)?

The composite clk structure
struct clk_composite {
        struct clk      clk;
        struct clk_ops  ops;

        struct clk      *mux;
        struct clk      *rate;
        struct clk      *gate;

        const struct clk_ops    *mux_ops;
        const struct clk_ops    *rate_ops;
        const struct clk_ops    *gate_ops;
};

Only the first clk needs to be binded with a udevice.
The mux/rate/gate pointer is only used for composite clk
internal usage and no udevice will be binded with them.

> 
> Please correct my understanding:
> 
> - Composite clock would use clk->dev (to have pointer to struct udevice)
>   and dev->driver_data to have pointer to clk.

Yes, for the composite clk.

> 
> - Then we use udevice flag DM_FLAG_BOUND to indicate if this device has
>   other udevices (i.e. clk) bound.

Yes, DM_FLAG_BOUND means the clk has a udevice binded.

> 
> - If it has bounded device then we use dev->driver_data to get it's
>   struct clk (or clock IP - like mux). If not, then we just use this
>   clk.

Yes.

> 
> Considering the above - the commit message needs detailed explanation of
> the "binding" concept.
> 
> > The mux/gate/divider inside a
> > composite clk should not bind a device, because they needs to be
> > hidden from dm tree or clk dumps.
> >
> > If bind the mux/gate/divider insides a composite clk, that will be
> > mess.
> 
> But the composite clock itself would be printed in 'dm tree' ?

Yes.

> 
> If yes, maybe we can add some kind of indication that it is a "container" and
> that it has some clocks "binded" ?

Looking at clk summary from Linux /sys/kernel/debug/clk/clk_summary,
There is no flag shows that it is a composite clk or not.

I think only add a flag to show the clk is a container does not make much sense.

Thanks,
Peng.

> 
> > The reason to introduce composite clk is to make clk tree
> > cleaner/simplier.
> 
> Ok. No problem with this.
> 
> >
> > Regards,
> > Peng.
> >
> > >
> > > > So add clk_dev_binded to let
> > > > choose the correct method.
> > > >
> > >
> > > [1] - http://patchwork.ozlabs.org/cover/1090669/
> > >
> > > > Signed-off-by: Peng Fan <peng.fan@nxp.com>
> > > > ---
> > > >  drivers/clk/clk.c | 8 ++++++++
> > > >  include/clk.h     | 9 +++++++++
> > > >  2 files changed, 17 insertions(+)
> > > >
> > > > diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c index
> > > > 0a0fffb50b..025bb99ecc 100644
> > > > --- a/drivers/clk/clk.c
> > > > +++ b/drivers/clk/clk.c
> > > > @@ -54,3 +54,11 @@ const char *clk_hw_get_name(const struct clk
> > > > *hw) {
> > > >  	return hw->dev->name;
> > > >  }
> > > > +
> > > > +bool clk_dev_binded(struct clk *clk) {
> > > > +	if (clk->dev && (clk->dev->flags & DM_FLAG_BOUND))
> > > > +		return true;
> > > > +
> > > > +	return false;
> > > > +}
> > > > diff --git a/include/clk.h b/include/clk.h index
> > > > a4ecca9fbc..8199119d01 100644
> > > > --- a/include/clk.h
> > > > +++ b/include/clk.h
> > > > @@ -337,4 +337,13 @@ static inline bool clk_valid(struct clk *clk)
> > > >   * @return zero on success, or -ENOENT on error
> > > >   */
> > > >  int clk_get_by_id(ulong id, struct clk **clkp);
> > > > +
> > > > +/**
> > > > + * clk_dev_binded() - Check whether the clk has a device binded
> > > > + *
> > > > + * @clk		A pointer to the clk
> > > > + *
> > > > + * @return true on binded, or false on no  */ bool
> > > > +clk_dev_binded(struct clk *clk);
> > > >  #endif
> > >
> > >
> > >
> > >
> > > Best regards,
> > >
> > > Lukasz Majewski
> > >
> > > --
> > >
> > > DENX Software Engineering GmbH,      Managing Director: Wolfgang
> > > Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell,
> > > Germany Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email:
> > > lukma at denx.de
> 
> 
> 
> 
> Best regards,
> 
> Lukasz Majewski
> 
> --
> 
> DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
> HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
> Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email:
> lukma at denx.de

[U-Boot] [i.MX8MM+CCF 11/41] clk: fixed_rate: export clk_fixed_rate

[Peng Fan]

> -----Original Message-----
> From: Lukasz Majewski [mailto:lukma at denx.de]
> Sent: 2019年5月8日 15:40
> To: Peng Fan <peng.fan@nxp.com>
> Cc: sbabic at denx.de; festevam at gmail.com; dl-uboot-imx
> <uboot-imx@nxp.com>; sjg at chromium.org; jagan at amarulasolutions.com;
> sr at denx.de; u-boot at lists.denx.de; trini at konsulko.com
> Subject: Re: [i.MX8MM+CCF 11/41] clk: fixed_rate: export clk_fixed_rate
> 
> On Wed, 8 May 2019 06:51:46 +0000
> Peng Fan <peng.fan@nxp.com> wrote:
> 
> > > -----Original Message-----
> > > From: Lukasz Majewski [mailto:lukma at denx.de]
> > > Sent: 2019年5月8日 14:46
> > > To: Peng Fan <peng.fan@nxp.com>
> > > Cc: sbabic at denx.de; festevam at gmail.com; dl-uboot-imx
> > > <uboot-imx@nxp.com>; sjg at chromium.org;
> jagan at amarulasolutions.com;
> > > sr at denx.de; u-boot at lists.denx.de; trini at konsulko.com
> > > Subject: Re: [i.MX8MM+CCF 11/41] clk: fixed_rate: export
> > > clk_fixed_rate
> > >
> > > On Tue, 7 May 2019 13:27:45 +0000
> > > Peng Fan <peng.fan@nxp.com> wrote:
> > >
> > > > > Subject: Re: [i.MX8MM+CCF 11/41] clk: fixed_rate: export
> > > > > clk_fixed_rate
> > > > >
> > > > > Hi Peng,
> > > > >
> > > > > > Export the structure for others to use.
> > > > > >
> > > > > > Signed-off-by: Peng Fan <peng.fan@nxp.com>
> > > > > > ---
> > > > > >  drivers/clk/clk_fixed_rate.c | 8 +-------
> > > > > > include/linux/clk-provider.h | 7 +++++++
> > > > > >  2 files changed, 8 insertions(+), 7 deletions(-)
> > > > > >
> > > > > > diff --git a/drivers/clk/clk_fixed_rate.c
> > > > > > b/drivers/clk/clk_fixed_rate.c index 089f060a23..069e643fbc
> > > > > > 100644 --- a/drivers/clk/clk_fixed_rate.c
> > > > > > +++ b/drivers/clk/clk_fixed_rate.c
> > > > > > @@ -6,13 +6,7 @@
> > > > > >  #include <common.h>
> > > > > >  #include <clk-uclass.h>
> > > > > >  #include <dm.h>
> > > > > > -
> > > > > > -struct clk_fixed_rate {
> > > > > > -	struct clk clk;
> > > > > > -	unsigned long fixed_rate;
> > > > > > -};
> > > > > > -
> > > > > > -#define to_clk_fixed_rate(dev)	((struct clk_fixed_rate
> > > > > > *)dev_get_platdata(dev)) +#include <linux/clk-provider.h>
> > > > > >
> > > > > >  static ulong clk_fixed_rate_get_rate(struct clk *clk)  { diff
> > > > > > --git a/include/linux/clk-provider.h
> > > > > > b/include/linux/clk-provider.h index 3ed0db86d2..b2bed768b6
> > > > > > 100644 --- a/include/linux/clk-provider.h
> > > > > > +++ b/include/linux/clk-provider.h
> > > > > > @@ -112,6 +112,13 @@ struct clk_fixed_factor {  #define
> > > > > > to_clk_fixed_factor(_clk) container_of(_clk, struct
> > > > > > clk_fixed_factor,\ clk)
> > > > > >
> > > > > > +struct clk_fixed_rate {
> > > > > > +	struct clk clk;
> > > > > > +	unsigned long fixed_rate;
> > > > > > +};
> > > > >
> > > > > I think that this struct shall stay where it was. Moreover, the
> > > > > clk-provider.h is not the API to be used by other parts of the
> > > > > clock API.
> > > > >
> > > > > The clk_fixed_rate shall be accessed via get_rate() only and in
> > > > > IMX6Q it is available in early SPL (parsed from dts /clocks
> > > > > property
> > > > > - the 24MHz OSC)
> > > > > > +
> > > > > > +#define to_clk_fixed_rate(dev)	((struct clk_fixed_rate
> > > > > > *)dev_get_platdata(dev)) +
> > > > > >  int clk_register(struct clk *clk, const char *drv_name,
> > > > > >  		 ulong drv_data, const char *name,
> > > > > >  		 const char *parent_name);
> > > > >
> > > > > Please explain why iMX8MM needs such global export?
> > > >
> > > > In clk-imx8mm.c, first configure ARM clk to osc24M fixed clk to
> > > > change pll clock.
> > > > +       /* Configure ARM to osc24M */
> > > > +       clk_get_by_id(IMX8MM_CLK_A53_SRC, &clkp);
> > > > +       uclass_get_device_by_name(UCLASS_CLK, "clock-osc-24m",
> > > &devp);
> > > > +       clkp1 = &to_clk_fixed_rate(devp)->clk;
> > > > +       clk_set_parent(clkp, clkp1);
> > >
> > > This code looks a bit strange to me. Why imx8mm sets parent here?
> >
> > The A53 clk could not change on the fly. There is a mux here, one is
> > PLL, one is OSC, And there are others. If we want to change the pll
> > clock which is currently being used by A53, we need first switch the
> > A53 clk to source from OSC, then change pll clock, then switch A53 clk
> > back to PLL.
> 
> The above description looks like a "standard" procedure for bypassing PLL
> when it is going to be locked.
> 
> The same is also performed on IMX6Q:
> 
> https://elixir.bootlin.com/linux/v5.1/source/drivers/clk/imx/clk-imx6q.c#L88
> 
> But I've not ported that part from the original Linux source code.

i.MX8MM is different.

This is how Linux change cpu's clock.
https://elixir.bootlin.com/linux/v5.1/source/drivers/clk/imx/clk-imx8mm.c#L655

It has a new cpu clk driver, I do not want to introduce that complexity in U-Boot.

This patch is just a simplified step of the upper Linux code.

The reason to configure the clk here is that ROM not configure the clock following
datasheet even it not hurt, but better to configure it right in SPL.

Thanks,
Peng.

> 
> >
> > >
> > > In the imx6q I write "osc" as a part of the clock tree:
> > >
> > >         clk_dm(IMX6QDL_CLK_PLL2,
> > >                imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll2_bus", "osc",
> > >                              base + 0x30, 0x1));
> > >
> > > And here the parent is set as "osc".
> > >
> > > Moreover, the "osc" or in your case "clock-osc-24m" shall be
> > > available in "clocks" DTS node and hence parsed / setup from there
> > > (and be available in the clk uclass list).
> > >
> > > > +
> > > > +       /* Configure ARM PLL to 1.2GHz */
> > > > +       clk_get_by_id(IMX8MM_ARM_PLL, &clkp1);
> > > > +       clk_set_rate(clkp1, 1200000000UL);
> > >
> > > Shouldn't this be set in DTS ? As it is now - it seems like a
> > > hardcoded value for early SPL clock setup. Am I right?
> >
> > You mean get freq from cpu opp and set cpu freq? I do not have good
> > idea how to set in DTS.
> 
> I'm thinking about following description of the "osc" fixed clock:
> https://elixir.bootlin.com/linux/v5.1/source/arch/arm/boot/dts/imx6qdl.dtsi#
> L64
> 
> and
> 
> http://git.denx.de/?p=u-boot/u-boot-imx.git;a=blob;f=arch/arm/dts/imx6qdl.
> dtsi;h=c0a94780087382a6e2805b7d6572f3e5e294e302;hb=HEAD#l53
> 
> The "fixed-clock" code has been adjusted to comply with the above DTS
> (which is provided in pre-reloc SPL - even before console and ddr setup).
> 
> (I had to use debug uart for debugging).
> 
> >
> > Thanks,
> > Peng.
> >
> > >
> > > > +       clk_get_by_id(IMX8MM_ARM_PLL_OUT, &clkp1);
> > > > +       clk_enable(clkp1);
> > > > +       clk_set_parent(clkp, clkp1);
> > > > +
> > > > +       /* Configure DIV to 1.2GHz */
> > > > +       clk_get_by_id(IMX8MM_CLK_A53_DIV, &clkp1);
> > > > +       clk_set_rate(clkp1, 1200000000UL);
> > > >
> > > > Regards,
> > > > Peng.
> > > >
> > > > >
> > > > >
> > > > > Best regards,
> > > > >
> > > > > Lukasz Majewski
> > > > >
> > > > > --
> > > > >
> > > > > DENX Software Engineering GmbH,      Managing Director:
> Wolfgang
> > > > > Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194
> > > > > Groebenzell, Germany Phone: (+49)-8142-66989-59 Fax:
> > > > > (+49)-8142-66989-80 Email: lukma at denx.de
> > >
> > >
> > >
> > >
> > > Best regards,
> > >
> > > Lukasz Majewski
> > >
> > > --
> > >
> > > DENX Software Engineering GmbH,      Managing Director: Wolfgang
> > > Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell,
> > > Germany Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email:
> > > lukma at denx.de
> 
> 
> 
> 
> Best regards,
> 
> Lukasz Majewski
> 
> --
> 
> DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
> HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
> Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email:
> lukma at denx.de

[U-Boot] [i.MX8MM+CCF 03/41] clk: introduce clk_dev_binded

[Lukasz Majewski]

On Wed, 8 May 2019 07:41:18 +0000
Peng Fan <peng.fan@nxp.com> wrote:

> > -----Original Message-----
> > From: Lukasz Majewski [mailto:lukma at denx.de]
> > Sent: 2019年5月8日 15:31
> > To: Peng Fan <peng.fan@nxp.com>
> > Cc: sbabic at denx.de; festevam at gmail.com; dl-uboot-imx
> > <uboot-imx@nxp.com>; sjg at chromium.org; jagan at amarulasolutions.com;
> > sr at denx.de; u-boot at lists.denx.de; trini at konsulko.com
> > Subject: Re: [i.MX8MM+CCF 03/41] clk: introduce clk_dev_binded
> > 
> > On Tue, 7 May 2019 13:22:24 +0000
> > Peng Fan <peng.fan@nxp.com> wrote:
> >   
> > > > Subject: Re: [i.MX8MM+CCF 03/41] clk: introduce clk_dev_binded
> > > >
> > > > On Tue, 30 Apr 2019 10:17:40 +0000
> > > > Peng Fan <peng.fan@nxp.com> wrote:
> > > >  
> > > > > When support Clock Common Framework, U-Boot use dev for clk
> > > > > tree information, there is no clk->parent.  
> > > >
> > > > There is a function in clk uclass named:
> > > > clk_get_parent() to provide parent of the clock.
> > > >  
> > > > > When
> > > > > support composite clk, it contains mux/gate/divider, but the
> > > > > mux/gate/divider is not binded with device.  
> > > >
> > > > There is a binding:
> > > > struct clk_pllv3 {
> > > > 	struct clk	clk;
> > > > 	...
> > > > };
> > > >
> > > > The clk.dev points to corresponding device.
> > > >
> > > > In the opposite direction we do have dev->driver_data, which
> > > > points to struct clk embedded in for example struct clk_pllv3.
> > > > (as struct clk_pllv3 and struct clk share the same address it
> > > > is up to us to cast it properly).
> > > >
> > > > I've written my thoughts and considerations about using
> > > > dev->private and dev->driver_data in the patch cover letter [1]
> > > >
> > > >  
> > > > > So we could not use dev_get_driver_data to get the correct
> > > > > clk_mux/gate/divider.  
> > > >
> > > > Maybe I've overlooked something, but dev_get_driver_data() shall
> > > > provide correct reference to udevice.  
> > >
> > > A composite clk contains a mux/gate/divider clk. Only the
> > > composite clk needs to binded with a udevice.  
> > 
> > So, if I understood correctly we do need to have another reference
> > to udevice (or clock)?  
> 
> The composite clk structure
> struct clk_composite {
>         struct clk      clk;
>         struct clk_ops  ops;
> 
>         struct clk      *mux;
>         struct clk      *rate;
>         struct clk      *gate;
> 
>         const struct clk_ops    *mux_ops;
>         const struct clk_ops    *rate_ops;
>         const struct clk_ops    *gate_ops;
> };
> 
> Only the first clk needs to be binded with a udevice.
> The mux/rate/gate pointer is only used for composite clk
> internal usage and no udevice will be binded with them.
> 
> > 
> > Please correct my understanding:
> > 
> > - Composite clock would use clk->dev (to have pointer to struct
> > udevice) and dev->driver_data to have pointer to clk.  
> 
> Yes, for the composite clk.
> 
> > 
> > - Then we use udevice flag DM_FLAG_BOUND to indicate if this device
> > has other udevices (i.e. clk) bound.  
> 
> Yes, DM_FLAG_BOUND means the clk has a udevice binded.
> 
> > 
> > - If it has bounded device then we use dev->driver_data to get it's
> >   struct clk (or clock IP - like mux). If not, then we just use this
> >   clk.  
> 
> Yes.
> 
> > 
> > Considering the above - the commit message needs detailed
> > explanation of the "binding" concept.
> >   
> > > The mux/gate/divider inside a
> > > composite clk should not bind a device, because they needs to be
> > > hidden from dm tree or clk dumps.
> > >
> > > If bind the mux/gate/divider insides a composite clk, that will be
> > > mess.  
> > 
> > But the composite clock itself would be printed in 'dm tree' ?  
> 
> Yes.
> 
> > 
> > If yes, maybe we can add some kind of indication that it is a
> > "container" and that it has some clocks "binded" ?  
> 
> Looking at clk summary from Linux /sys/kernel/debug/clk/clk_summary,
> There is no flag shows that it is a composite clk or not.
> 
> I think only add a flag to show the clk is a container does not make
> much sense.

Ok. I see.

> 
> Thanks,
> Peng.
> 
> >   
> > > The reason to introduce composite clk is to make clk tree
> > > cleaner/simplier.  
> > 
> > Ok. No problem with this.
> >   
> > >
> > > Regards,
> > > Peng.
> > >  
> > > >  
> > > > > So add clk_dev_binded to let
> > > > > choose the correct method.
> > > > >  
> > > >
> > > > [1] - http://patchwork.ozlabs.org/cover/1090669/
> > > >  
> > > > > Signed-off-by: Peng Fan <peng.fan@nxp.com>
> > > > > ---
> > > > >  drivers/clk/clk.c | 8 ++++++++
> > > > >  include/clk.h     | 9 +++++++++
> > > > >  2 files changed, 17 insertions(+)
> > > > >
> > > > > diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c index
> > > > > 0a0fffb50b..025bb99ecc 100644
> > > > > --- a/drivers/clk/clk.c
> > > > > +++ b/drivers/clk/clk.c
> > > > > @@ -54,3 +54,11 @@ const char *clk_hw_get_name(const struct
> > > > > clk *hw) {
> > > > >  	return hw->dev->name;
> > > > >  }
> > > > > +
> > > > > +bool clk_dev_binded(struct clk *clk) {
> > > > > +	if (clk->dev && (clk->dev->flags & DM_FLAG_BOUND))
> > > > > +		return true;
> > > > > +
> > > > > +	return false;
> > > > > +}
> > > > > diff --git a/include/clk.h b/include/clk.h index
> > > > > a4ecca9fbc..8199119d01 100644
> > > > > --- a/include/clk.h
> > > > > +++ b/include/clk.h
> > > > > @@ -337,4 +337,13 @@ static inline bool clk_valid(struct clk
> > > > > *clk)
> > > > >   * @return zero on success, or -ENOENT on error
> > > > >   */
> > > > >  int clk_get_by_id(ulong id, struct clk **clkp);
> > > > > +
> > > > > +/**
> > > > > + * clk_dev_binded() - Check whether the clk has a device
> > > > > binded
> > > > > + *
> > > > > + * @clk		A pointer to the clk
> > > > > + *
> > > > > + * @return true on binded, or false on no  */ bool
> > > > > +clk_dev_binded(struct clk *clk);
> > > > >  #endif  
> > > >
> > > >
> > > >
> > > >
> > > > Best regards,
> > > >
> > > > Lukasz Majewski
> > > >
> > > > --
> > > >
> > > > DENX Software Engineering GmbH,      Managing Director: Wolfgang
> > > > Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194
> > > > Groebenzell, Germany Phone: (+49)-8142-66989-59 Fax:
> > > > (+49)-8142-66989-80 Email: lukma at denx.de  
> > 
> > 
> > 
> > 
> > Best regards,
> > 
> > Lukasz Majewski
> > 
> > --
> > 
> > DENX Software Engineering GmbH,      Managing Director: Wolfgang
> > Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell,
> > Germany Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email:
> > lukma at denx.de  




Best regards,

Lukasz Majewski

--

DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email: lukma at denx.de
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[U-Boot] [i.MX8MM+CCF 11/41] clk: fixed_rate: export clk_fixed_rate

[Lukasz Majewski]

On Wed, 8 May 2019 07:45:39 +0000
Peng Fan <peng.fan@nxp.com> wrote:

> > -----Original Message-----
> > From: Lukasz Majewski [mailto:lukma at denx.de]
> > Sent: 2019年5月8日 15:40
> > To: Peng Fan <peng.fan@nxp.com>
> > Cc: sbabic at denx.de; festevam at gmail.com; dl-uboot-imx
> > <uboot-imx@nxp.com>; sjg at chromium.org; jagan at amarulasolutions.com;
> > sr at denx.de; u-boot at lists.denx.de; trini at konsulko.com
> > Subject: Re: [i.MX8MM+CCF 11/41] clk: fixed_rate: export
> > clk_fixed_rate
> > 
> > On Wed, 8 May 2019 06:51:46 +0000
> > Peng Fan <peng.fan@nxp.com> wrote:
> >   
> > > > -----Original Message-----
> > > > From: Lukasz Majewski [mailto:lukma at denx.de]
> > > > Sent: 2019年5月8日 14:46
> > > > To: Peng Fan <peng.fan@nxp.com>
> > > > Cc: sbabic at denx.de; festevam at gmail.com; dl-uboot-imx
> > > > <uboot-imx@nxp.com>; sjg at chromium.org;  
> > jagan at amarulasolutions.com;  
> > > > sr at denx.de; u-boot at lists.denx.de; trini at konsulko.com
> > > > Subject: Re: [i.MX8MM+CCF 11/41] clk: fixed_rate: export
> > > > clk_fixed_rate
> > > >
> > > > On Tue, 7 May 2019 13:27:45 +0000
> > > > Peng Fan <peng.fan@nxp.com> wrote:
> > > >  
> > > > > > Subject: Re: [i.MX8MM+CCF 11/41] clk: fixed_rate: export
> > > > > > clk_fixed_rate
> > > > > >
> > > > > > Hi Peng,
> > > > > >  
> > > > > > > Export the structure for others to use.
> > > > > > >
> > > > > > > Signed-off-by: Peng Fan <peng.fan@nxp.com>
> > > > > > > ---
> > > > > > >  drivers/clk/clk_fixed_rate.c | 8 +-------
> > > > > > > include/linux/clk-provider.h | 7 +++++++
> > > > > > >  2 files changed, 8 insertions(+), 7 deletions(-)
> > > > > > >
> > > > > > > diff --git a/drivers/clk/clk_fixed_rate.c
> > > > > > > b/drivers/clk/clk_fixed_rate.c index
> > > > > > > 089f060a23..069e643fbc 100644 ---
> > > > > > > a/drivers/clk/clk_fixed_rate.c +++
> > > > > > > b/drivers/clk/clk_fixed_rate.c @@ -6,13 +6,7 @@
> > > > > > >  #include <common.h>
> > > > > > >  #include <clk-uclass.h>
> > > > > > >  #include <dm.h>
> > > > > > > -
> > > > > > > -struct clk_fixed_rate {
> > > > > > > -	struct clk clk;
> > > > > > > -	unsigned long fixed_rate;
> > > > > > > -};
> > > > > > > -
> > > > > > > -#define to_clk_fixed_rate(dev)	((struct
> > > > > > > clk_fixed_rate *)dev_get_platdata(dev)) +#include
> > > > > > > <linux/clk-provider.h>
> > > > > > >
> > > > > > >  static ulong clk_fixed_rate_get_rate(struct clk *clk)
> > > > > > > { diff --git a/include/linux/clk-provider.h
> > > > > > > b/include/linux/clk-provider.h index
> > > > > > > 3ed0db86d2..b2bed768b6 100644 ---
> > > > > > > a/include/linux/clk-provider.h +++
> > > > > > > b/include/linux/clk-provider.h @@ -112,6 +112,13 @@
> > > > > > > struct clk_fixed_factor {  #define
> > > > > > > to_clk_fixed_factor(_clk) container_of(_clk, struct
> > > > > > > clk_fixed_factor,\ clk)
> > > > > > >
> > > > > > > +struct clk_fixed_rate {
> > > > > > > +	struct clk clk;
> > > > > > > +	unsigned long fixed_rate;
> > > > > > > +};  
> > > > > >
> > > > > > I think that this struct shall stay where it was. Moreover,
> > > > > > the clk-provider.h is not the API to be used by other parts
> > > > > > of the clock API.
> > > > > >
> > > > > > The clk_fixed_rate shall be accessed via get_rate() only
> > > > > > and in IMX6Q it is available in early SPL (parsed from
> > > > > > dts /clocks property
> > > > > > - the 24MHz OSC)  
> > > > > > > +
> > > > > > > +#define to_clk_fixed_rate(dev)	((struct
> > > > > > > clk_fixed_rate *)dev_get_platdata(dev)) +
> > > > > > >  int clk_register(struct clk *clk, const char *drv_name,
> > > > > > >  		 ulong drv_data, const char *name,
> > > > > > >  		 const char *parent_name);  
> > > > > >
> > > > > > Please explain why iMX8MM needs such global export?  
> > > > >
> > > > > In clk-imx8mm.c, first configure ARM clk to osc24M fixed clk
> > > > > to change pll clock.
> > > > > +       /* Configure ARM to osc24M */
> > > > > +       clk_get_by_id(IMX8MM_CLK_A53_SRC, &clkp);
> > > > > +       uclass_get_device_by_name(UCLASS_CLK,
> > > > > "clock-osc-24m",  
> > > > &devp);  
> > > > > +       clkp1 = &to_clk_fixed_rate(devp)->clk;
> > > > > +       clk_set_parent(clkp, clkp1);  
> > > >
> > > > This code looks a bit strange to me. Why imx8mm sets parent
> > > > here?  
> > >
> > > The A53 clk could not change on the fly. There is a mux here, one
> > > is PLL, one is OSC, And there are others. If we want to change
> > > the pll clock which is currently being used by A53, we need first
> > > switch the A53 clk to source from OSC, then change pll clock,
> > > then switch A53 clk back to PLL.  
> > 
> > The above description looks like a "standard" procedure for
> > bypassing PLL when it is going to be locked.
> > 
> > The same is also performed on IMX6Q:
> > 
> > https://elixir.bootlin.com/linux/v5.1/source/drivers/clk/imx/clk-imx6q.c#L88
> > 
> > But I've not ported that part from the original Linux source code.  
> 
> i.MX8MM is different.
> 
> This is how Linux change cpu's clock.
> https://elixir.bootlin.com/linux/v5.1/source/drivers/clk/imx/clk-imx8mm.c#L655
> 
> It has a new cpu clk driver, I do not want to introduce that
> complexity in U-Boot.

Ok.

> 
> This patch is just a simplified step of the upper Linux code.

My point is that this driver pollutes the fixed-clock code and makes it
imx8 specific.

> 
> The reason to configure the clk here is that ROM not configure the
> clock following datasheet even it not hurt, but better to configure
> it right in SPL.

So this code is for fixing bugs (incomplete initialisation) in SoC's
ROM?

> 
> Thanks,
> Peng.
> 
> >   
> > >  
> > > >
> > > > In the imx6q I write "osc" as a part of the clock tree:
> > > >
> > > >         clk_dm(IMX6QDL_CLK_PLL2,
> > > >                imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll2_bus",
> > > > "osc", base + 0x30, 0x1));
> > > >
> > > > And here the parent is set as "osc".
> > > >
> > > > Moreover, the "osc" or in your case "clock-osc-24m" shall be
> > > > available in "clocks" DTS node and hence parsed / setup from
> > > > there (and be available in the clk uclass list).
> > > >  
> > > > > +
> > > > > +       /* Configure ARM PLL to 1.2GHz */
> > > > > +       clk_get_by_id(IMX8MM_ARM_PLL, &clkp1);
> > > > > +       clk_set_rate(clkp1, 1200000000UL);  
> > > >
> > > > Shouldn't this be set in DTS ? As it is now - it seems like a
> > > > hardcoded value for early SPL clock setup. Am I right?  
> > >
> > > You mean get freq from cpu opp and set cpu freq? I do not have
> > > good idea how to set in DTS.  
> > 
> > I'm thinking about following description of the "osc" fixed clock:
> > https://elixir.bootlin.com/linux/v5.1/source/arch/arm/boot/dts/imx6qdl.dtsi#
> > L64
> > 
> > and
> > 
> > http://git.denx.de/?p=u-boot/u-boot-imx.git;a=blob;f=arch/arm/dts/imx6qdl.
> > dtsi;h=c0a94780087382a6e2805b7d6572f3e5e294e302;hb=HEAD#l53
> > 
> > The "fixed-clock" code has been adjusted to comply with the above
> > DTS (which is provided in pre-reloc SPL - even before console and
> > ddr setup).
> > 
> > (I had to use debug uart for debugging).
> >   
> > >
> > > Thanks,
> > > Peng.
> > >  
> > > >  
> > > > > +       clk_get_by_id(IMX8MM_ARM_PLL_OUT, &clkp1);
> > > > > +       clk_enable(clkp1);
> > > > > +       clk_set_parent(clkp, clkp1);
> > > > > +
> > > > > +       /* Configure DIV to 1.2GHz */
> > > > > +       clk_get_by_id(IMX8MM_CLK_A53_DIV, &clkp1);
> > > > > +       clk_set_rate(clkp1, 1200000000UL);
> > > > >
> > > > > Regards,
> > > > > Peng.
> > > > >  
> > > > > >
> > > > > >
> > > > > > Best regards,
> > > > > >
> > > > > > Lukasz Majewski
> > > > > >
> > > > > > --
> > > > > >
> > > > > > DENX Software Engineering GmbH,      Managing Director:  
> > Wolfgang  
> > > > > > Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194
> > > > > > Groebenzell, Germany Phone: (+49)-8142-66989-59 Fax:
> > > > > > (+49)-8142-66989-80 Email: lukma at denx.de  
> > > >
> > > >
> > > >
> > > >
> > > > Best regards,
> > > >
> > > > Lukasz Majewski
> > > >
> > > > --
> > > >
> > > > DENX Software Engineering GmbH,      Managing Director: Wolfgang
> > > > Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194
> > > > Groebenzell, Germany Phone: (+49)-8142-66989-59 Fax:
> > > > (+49)-8142-66989-80 Email: lukma at denx.de  
> > 
> > 
> > 
> > 
> > Best regards,
> > 
> > Lukasz Majewski
> > 
> > --
> > 
> > DENX Software Engineering GmbH,      Managing Director: Wolfgang
> > Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell,
> > Germany Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email:
> > lukma at denx.de  




Best regards,

Lukasz Majewski

--

DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email: lukma at denx.de
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[U-Boot] [i.MX8MM+CCF 11/41] clk: fixed_rate: export clk_fixed_rate

[Peng Fan]

> Subject: Re: [i.MX8MM+CCF 11/41] clk: fixed_rate: export clk_fixed_rate
> 
> On Wed, 8 May 2019 07:45:39 +0000
> Peng Fan <peng.fan@nxp.com> wrote:
> 
> > > -----Original Message-----
> > > From: Lukasz Majewski [mailto:lukma at denx.de]
> > > Sent: 2019年5月8日 15:40
> > > To: Peng Fan <peng.fan@nxp.com>
> > > Cc: sbabic at denx.de; festevam at gmail.com; dl-uboot-imx
> > > <uboot-imx@nxp.com>; sjg at chromium.org;
> jagan at amarulasolutions.com;
> > > sr at denx.de; u-boot at lists.denx.de; trini at konsulko.com
> > > Subject: Re: [i.MX8MM+CCF 11/41] clk: fixed_rate: export
> > > clk_fixed_rate
> > >
> > > On Wed, 8 May 2019 06:51:46 +0000
> > > Peng Fan <peng.fan@nxp.com> wrote:
> > >
> > > > > -----Original Message-----
> > > > > From: Lukasz Majewski [mailto:lukma at denx.de]
> > > > > Sent: 2019年5月8日 14:46
> > > > > To: Peng Fan <peng.fan@nxp.com>
> > > > > Cc: sbabic at denx.de; festevam at gmail.com; dl-uboot-imx
> > > > > <uboot-imx@nxp.com>; sjg at chromium.org;
> > > jagan at amarulasolutions.com;
> > > > > sr at denx.de; u-boot at lists.denx.de; trini at konsulko.com
> > > > > Subject: Re: [i.MX8MM+CCF 11/41] clk: fixed_rate: export
> > > > > clk_fixed_rate
> > > > >
> > > > > On Tue, 7 May 2019 13:27:45 +0000 Peng Fan <peng.fan@nxp.com>
> > > > > wrote:
> > > > >
> > > > > > > Subject: Re: [i.MX8MM+CCF 11/41] clk: fixed_rate: export
> > > > > > > clk_fixed_rate
> > > > > > >
> > > > > > > Hi Peng,
> > > > > > >
> > > > > > > > Export the structure for others to use.
> > > > > > > >
> > > > > > > > Signed-off-by: Peng Fan <peng.fan@nxp.com>
> > > > > > > > ---
> > > > > > > >  drivers/clk/clk_fixed_rate.c | 8 +-------
> > > > > > > > include/linux/clk-provider.h | 7 +++++++
> > > > > > > >  2 files changed, 8 insertions(+), 7 deletions(-)
> > > > > > > >
> > > > > > > > diff --git a/drivers/clk/clk_fixed_rate.c
> > > > > > > > b/drivers/clk/clk_fixed_rate.c index
> > > > > > > > 089f060a23..069e643fbc 100644 ---
> > > > > > > > a/drivers/clk/clk_fixed_rate.c +++
> > > > > > > > b/drivers/clk/clk_fixed_rate.c @@ -6,13 +6,7 @@  #include
> > > > > > > > <common.h>  #include <clk-uclass.h>  #include <dm.h>
> > > > > > > > -
> > > > > > > > -struct clk_fixed_rate {
> > > > > > > > -	struct clk clk;
> > > > > > > > -	unsigned long fixed_rate;
> > > > > > > > -};
> > > > > > > > -
> > > > > > > > -#define to_clk_fixed_rate(dev)	((struct
> > > > > > > > clk_fixed_rate *)dev_get_platdata(dev)) +#include
> > > > > > > > <linux/clk-provider.h>
> > > > > > > >
> > > > > > > >  static ulong clk_fixed_rate_get_rate(struct clk *clk) {
> > > > > > > > diff --git a/include/linux/clk-provider.h
> > > > > > > > b/include/linux/clk-provider.h index
> > > > > > > > 3ed0db86d2..b2bed768b6 100644 ---
> > > > > > > > a/include/linux/clk-provider.h +++
> > > > > > > > b/include/linux/clk-provider.h @@ -112,6 +112,13 @@ struct
> > > > > > > > clk_fixed_factor {  #define
> > > > > > > > to_clk_fixed_factor(_clk) container_of(_clk, struct
> > > > > > > > clk_fixed_factor,\ clk)
> > > > > > > >
> > > > > > > > +struct clk_fixed_rate {
> > > > > > > > +	struct clk clk;
> > > > > > > > +	unsigned long fixed_rate; };
> > > > > > >
> > > > > > > I think that this struct shall stay where it was. Moreover,
> > > > > > > the clk-provider.h is not the API to be used by other parts
> > > > > > > of the clock API.
> > > > > > >
> > > > > > > The clk_fixed_rate shall be accessed via get_rate() only and
> > > > > > > in IMX6Q it is available in early SPL (parsed from dts
> > > > > > > /clocks property
> > > > > > > - the 24MHz OSC)
> > > > > > > > +
> > > > > > > > +#define to_clk_fixed_rate(dev)	((struct
> > > > > > > > clk_fixed_rate *)dev_get_platdata(dev)) +  int
> > > > > > > > clk_register(struct clk *clk, const char *drv_name,
> > > > > > > >  		 ulong drv_data, const char *name,
> > > > > > > >  		 const char *parent_name);
> > > > > > >
> > > > > > > Please explain why iMX8MM needs such global export?
> > > > > >
> > > > > > In clk-imx8mm.c, first configure ARM clk to osc24M fixed clk
> > > > > > to change pll clock.
> > > > > > +       /* Configure ARM to osc24M */
> > > > > > +       clk_get_by_id(IMX8MM_CLK_A53_SRC, &clkp);
> > > > > > +       uclass_get_device_by_name(UCLASS_CLK,
> > > > > > "clock-osc-24m",
> > > > > &devp);
> > > > > > +       clkp1 = &to_clk_fixed_rate(devp)->clk;
> > > > > > +       clk_set_parent(clkp, clkp1);
> > > > >
> > > > > This code looks a bit strange to me. Why imx8mm sets parent
> > > > > here?
> > > >
> > > > The A53 clk could not change on the fly. There is a mux here, one
> > > > is PLL, one is OSC, And there are others. If we want to change the
> > > > pll clock which is currently being used by A53, we need first
> > > > switch the A53 clk to source from OSC, then change pll clock, then
> > > > switch A53 clk back to PLL.
> > >
> > > The above description looks like a "standard" procedure for
> > > bypassing PLL when it is going to be locked.
> > >
> > > The same is also performed on IMX6Q:
> > >
> > > https://elixir.bootlin.com/linux/v5.1/source/drivers/clk/imx/clk-imx
> > > 6q.c#L88
> > >
> > > But I've not ported that part from the original Linux source code.
> >
> > i.MX8MM is different.
> >
> > This is how Linux change cpu's clock.
> > https://elixir.bootlin.com/linux/v5.1/source/drivers/clk/imx/clk-imx8m
> > m.c#L655
> >
> > It has a new cpu clk driver, I do not want to introduce that
> > complexity in U-Boot.
> 
> Ok.
> 
> >
> > This patch is just a simplified step of the upper Linux code.
> 
> My point is that this driver pollutes the fixed-clock code and makes it
> imx8 specific.

If i.MX7 switch to CCF, it also has such requirement.

I am not sure others, Linux exports
grep "to_clk_fix" ./include/linux/clk-provider.h -rn
313:#define to_clk_fixed_rate(_hw) container_of(_hw, struct clk_fixed_rate, hw)
575:#define to_clk_fixed_factor(_hw) container_of(_hw, struct clk_fixed_factor, hw)

I think it does not hurt for uboot also export it.

> 
> >
> > The reason to configure the clk here is that ROM not configure the
> > clock following datasheet even it not hurt, but better to configure it
> > right in SPL.
> 
> So this code is for fixing bugs (incomplete initialisation) in SoC's ROM?

Strictly speaking it is not a bug. The datasheet opp has 1.2GHz, but not 1GHz configured
by ROM. But actually when power up, the initial freq is 24MHz. Just
configure in uboot to follow datasheet and might make Linux kernel happy.

Thanks,
Peng.

> 
> >
> > Thanks,
> > Peng.
> >
> > >
> > > >
> > > > >
> > > > > In the imx6q I write "osc" as a part of the clock tree:
> > > > >
> > > > >         clk_dm(IMX6QDL_CLK_PLL2,
> > > > >                imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll2_bus",
> > > > > "osc", base + 0x30, 0x1));
> > > > >
> > > > > And here the parent is set as "osc".
> > > > >
> > > > > Moreover, the "osc" or in your case "clock-osc-24m" shall be
> > > > > available in "clocks" DTS node and hence parsed / setup from
> > > > > there (and be available in the clk uclass list).
> > > > >
> > > > > > +
> > > > > > +       /* Configure ARM PLL to 1.2GHz */
> > > > > > +       clk_get_by_id(IMX8MM_ARM_PLL, &clkp1);
> > > > > > +       clk_set_rate(clkp1, 1200000000UL);
> > > > >
> > > > > Shouldn't this be set in DTS ? As it is now - it seems like a
> > > > > hardcoded value for early SPL clock setup. Am I right?
> > > >
> > > > You mean get freq from cpu opp and set cpu freq? I do not have
> > > > good idea how to set in DTS.
> > >
> > > I'm thinking about following description of the "osc" fixed clock:
> > > https://elixir.bootlin.com/linux/v5.1/source/arch/arm/boot/dts/imx6q
> > > dl.dtsi#
> > > L64
> > >
> > > and
> > >
> > >
> http://git.denx.de/?p=u-boot/u-boot-imx.git;a=blob;f=arch/arm/dts/imx6qdl.
> > > dtsi;h=c0a94780087382a6e2805b7d6572f3e5e294e302;hb=HEAD#l53
> > >
> > > The "fixed-clock" code has been adjusted to comply with the above
> > > DTS (which is provided in pre-reloc SPL - even before console and
> > > ddr setup).
> > >
> > > (I had to use debug uart for debugging).
> > >
> > > >
> > > > Thanks,
> > > > Peng.
> > > >
> > > > >
> > > > > > +       clk_get_by_id(IMX8MM_ARM_PLL_OUT, &clkp1);
> > > > > > +       clk_enable(clkp1);
> > > > > > +       clk_set_parent(clkp, clkp1);
> > > > > > +
> > > > > > +       /* Configure DIV to 1.2GHz */
> > > > > > +       clk_get_by_id(IMX8MM_CLK_A53_DIV, &clkp1);
> > > > > > +       clk_set_rate(clkp1, 1200000000UL);
> > > > > >
> > > > > > Regards,
> > > > > > Peng.
> > > > > >
> > > > > > >
> > > > > > >
> > > > > > > Best regards,
> > > > > > >
> > > > > > > Lukasz Majewski
> > > > > > >
> > > > > > > --
> > > > > > >
> > > > > > > DENX Software Engineering GmbH,      Managing Director:
> > > Wolfgang
> > > > > > > Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194
> > > > > > > Groebenzell, Germany Phone: (+49)-8142-66989-59 Fax:
> > > > > > > (+49)-8142-66989-80 Email: lukma at denx.de
> > > > >
> > > > >
> > > > >
> > > > >
> > > > > Best regards,
> > > > >
> > > > > Lukasz Majewski
> > > > >
> > > > > --
> > > > >
> > > > > DENX Software Engineering GmbH,      Managing Director:
> Wolfgang
> > > > > Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194
> > > > > Groebenzell, Germany Phone: (+49)-8142-66989-59 Fax:
> > > > > (+49)-8142-66989-80 Email: lukma at denx.de
> > >
> > >
> > >
> > >
> > > Best regards,
> > >
> > > Lukasz Majewski
> > >
> > > --
> > >
> > > DENX Software Engineering GmbH,      Managing Director: Wolfgang
> > > Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell,
> > > Germany Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email:
> > > lukma at denx.de
> 
> 
> 
> 
> Best regards,
> 
> Lukasz Majewski
> 
> --
> 
> DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
> HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
> Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email:
> lukma at denx.de

[U-Boot] [i.MX8MM+CCF 11/41] clk: fixed_rate: export clk_fixed_rate

[Lukasz Majewski]

On Thu, 9 May 2019 01:13:15 +0000
Peng Fan <peng.fan@nxp.com> wrote:

> > Subject: Re: [i.MX8MM+CCF 11/41] clk: fixed_rate: export
> > clk_fixed_rate
> > 
> > On Wed, 8 May 2019 07:45:39 +0000
> > Peng Fan <peng.fan@nxp.com> wrote:
> >   
> > > > -----Original Message-----
> > > > From: Lukasz Majewski [mailto:lukma at denx.de]
> > > > Sent: 2019年5月8日 15:40
> > > > To: Peng Fan <peng.fan@nxp.com>
> > > > Cc: sbabic at denx.de; festevam at gmail.com; dl-uboot-imx
> > > > <uboot-imx@nxp.com>; sjg at chromium.org;  
> > jagan at amarulasolutions.com;  
> > > > sr at denx.de; u-boot at lists.denx.de; trini at konsulko.com
> > > > Subject: Re: [i.MX8MM+CCF 11/41] clk: fixed_rate: export
> > > > clk_fixed_rate
> > > >
> > > > On Wed, 8 May 2019 06:51:46 +0000
> > > > Peng Fan <peng.fan@nxp.com> wrote:
> > > >  
> > > > > > -----Original Message-----
> > > > > > From: Lukasz Majewski [mailto:lukma at denx.de]
> > > > > > Sent: 2019年5月8日 14:46
> > > > > > To: Peng Fan <peng.fan@nxp.com>
> > > > > > Cc: sbabic at denx.de; festevam at gmail.com; dl-uboot-imx
> > > > > > <uboot-imx@nxp.com>; sjg at chromium.org;  
> > > > jagan at amarulasolutions.com;  
> > > > > > sr at denx.de; u-boot at lists.denx.de; trini at konsulko.com
> > > > > > Subject: Re: [i.MX8MM+CCF 11/41] clk: fixed_rate: export
> > > > > > clk_fixed_rate
> > > > > >
> > > > > > On Tue, 7 May 2019 13:27:45 +0000 Peng Fan
> > > > > > <peng.fan@nxp.com> wrote:
> > > > > >  
> > > > > > > > Subject: Re: [i.MX8MM+CCF 11/41] clk: fixed_rate: export
> > > > > > > > clk_fixed_rate
> > > > > > > >
> > > > > > > > Hi Peng,
> > > > > > > >  
> > > > > > > > > Export the structure for others to use.
> > > > > > > > >
> > > > > > > > > Signed-off-by: Peng Fan <peng.fan@nxp.com>
> > > > > > > > > ---
> > > > > > > > >  drivers/clk/clk_fixed_rate.c | 8 +-------
> > > > > > > > > include/linux/clk-provider.h | 7 +++++++
> > > > > > > > >  2 files changed, 8 insertions(+), 7 deletions(-)
> > > > > > > > >
> > > > > > > > > diff --git a/drivers/clk/clk_fixed_rate.c
> > > > > > > > > b/drivers/clk/clk_fixed_rate.c index
> > > > > > > > > 089f060a23..069e643fbc 100644 ---
> > > > > > > > > a/drivers/clk/clk_fixed_rate.c +++
> > > > > > > > > b/drivers/clk/clk_fixed_rate.c @@ -6,13 +6,7 @@
> > > > > > > > > #include <common.h>  #include <clk-uclass.h>
> > > > > > > > > #include <dm.h> -
> > > > > > > > > -struct clk_fixed_rate {
> > > > > > > > > -	struct clk clk;
> > > > > > > > > -	unsigned long fixed_rate;
> > > > > > > > > -};
> > > > > > > > > -
> > > > > > > > > -#define to_clk_fixed_rate(dev)	((struct
> > > > > > > > > clk_fixed_rate *)dev_get_platdata(dev)) +#include
> > > > > > > > > <linux/clk-provider.h>
> > > > > > > > >
> > > > > > > > >  static ulong clk_fixed_rate_get_rate(struct clk
> > > > > > > > > *clk) { diff --git a/include/linux/clk-provider.h
> > > > > > > > > b/include/linux/clk-provider.h index
> > > > > > > > > 3ed0db86d2..b2bed768b6 100644 ---
> > > > > > > > > a/include/linux/clk-provider.h +++
> > > > > > > > > b/include/linux/clk-provider.h @@ -112,6 +112,13 @@
> > > > > > > > > struct clk_fixed_factor {  #define
> > > > > > > > > to_clk_fixed_factor(_clk) container_of(_clk, struct
> > > > > > > > > clk_fixed_factor,\ clk)
> > > > > > > > >
> > > > > > > > > +struct clk_fixed_rate {
> > > > > > > > > +	struct clk clk;
> > > > > > > > > +	unsigned long fixed_rate; };  
> > > > > > > >
> > > > > > > > I think that this struct shall stay where it was.
> > > > > > > > Moreover, the clk-provider.h is not the API to be used
> > > > > > > > by other parts of the clock API.
> > > > > > > >
> > > > > > > > The clk_fixed_rate shall be accessed via get_rate()
> > > > > > > > only and in IMX6Q it is available in early SPL (parsed
> > > > > > > > from dts /clocks property
> > > > > > > > - the 24MHz OSC)  
> > > > > > > > > +
> > > > > > > > > +#define to_clk_fixed_rate(dev)	((struct
> > > > > > > > > clk_fixed_rate *)dev_get_platdata(dev)) +  int
> > > > > > > > > clk_register(struct clk *clk, const char *drv_name,
> > > > > > > > >  		 ulong drv_data, const char *name,
> > > > > > > > >  		 const char *parent_name);  
> > > > > > > >
> > > > > > > > Please explain why iMX8MM needs such global export?  
> > > > > > >
> > > > > > > In clk-imx8mm.c, first configure ARM clk to osc24M fixed
> > > > > > > clk to change pll clock.
> > > > > > > +       /* Configure ARM to osc24M */
> > > > > > > +       clk_get_by_id(IMX8MM_CLK_A53_SRC, &clkp);
> > > > > > > +       uclass_get_device_by_name(UCLASS_CLK,
> > > > > > > "clock-osc-24m",  
> > > > > > &devp);  
> > > > > > > +       clkp1 = &to_clk_fixed_rate(devp)->clk;
> > > > > > > +       clk_set_parent(clkp, clkp1);  
> > > > > >
> > > > > > This code looks a bit strange to me. Why imx8mm sets parent
> > > > > > here?  
> > > > >
> > > > > The A53 clk could not change on the fly. There is a mux here,
> > > > > one is PLL, one is OSC, And there are others. If we want to
> > > > > change the pll clock which is currently being used by A53, we
> > > > > need first switch the A53 clk to source from OSC, then change
> > > > > pll clock, then switch A53 clk back to PLL.  
> > > >
> > > > The above description looks like a "standard" procedure for
> > > > bypassing PLL when it is going to be locked.
> > > >
> > > > The same is also performed on IMX6Q:
> > > >
> > > > https://elixir.bootlin.com/linux/v5.1/source/drivers/clk/imx/clk-imx
> > > > 6q.c#L88
> > > >
> > > > But I've not ported that part from the original Linux source
> > > > code.  
> > >
> > > i.MX8MM is different.
> > >
> > > This is how Linux change cpu's clock.
> > > https://elixir.bootlin.com/linux/v5.1/source/drivers/clk/imx/clk-imx8m
> > > m.c#L655
> > >
> > > It has a new cpu clk driver, I do not want to introduce that
> > > complexity in U-Boot.  
> > 
> > Ok.
> >   
> > >
> > > This patch is just a simplified step of the upper Linux code.  
> > 
> > My point is that this driver pollutes the fixed-clock code and
> > makes it imx8 specific.  
> 
> If i.MX7 switch to CCF, it also has such requirement.
> 
> I am not sure others, Linux exports
> grep "to_clk_fix" ./include/linux/clk-provider.h -rn
> 313:#define to_clk_fixed_rate(_hw) container_of(_hw, struct
> clk_fixed_rate, hw) 575:#define to_clk_fixed_factor(_hw)
> container_of(_hw, struct clk_fixed_factor, hw)
> 
> I think it does not hurt for uboot also export it.
> 
> >   
> > >
> > > The reason to configure the clk here is that ROM not configure the
> > > clock following datasheet even it not hurt, but better to
> > > configure it right in SPL.  
> > 
> > So this code is for fixing bugs (incomplete initialisation) in
> > SoC's ROM?  
> 
> Strictly speaking it is not a bug. The datasheet opp has 1.2GHz, but
> not 1GHz configured by ROM. But actually when power up, the initial
> freq is 24MHz. Just configure in uboot to follow datasheet and might
> make Linux kernel happy.

For IMX6Q there is a table in the User Manual, which describes the
state (i.e. the clock frequencies of the IP blocks) in which is the
board when ROM handles the execution to SPL.

I also assume that 24 MHz Core frequency is too low and will be fixed
in next ROM (SoC) revisions ?

> 
> Thanks,
> Peng.
> 
> >   
> > >
> > > Thanks,
> > > Peng.
> > >  
> > > >  
> > > > >  
> > > > > >
> > > > > > In the imx6q I write "osc" as a part of the clock tree:
> > > > > >
> > > > > >         clk_dm(IMX6QDL_CLK_PLL2,
> > > > > >                imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll2_bus",
> > > > > > "osc", base + 0x30, 0x1));
> > > > > >
> > > > > > And here the parent is set as "osc".
> > > > > >
> > > > > > Moreover, the "osc" or in your case "clock-osc-24m" shall be
> > > > > > available in "clocks" DTS node and hence parsed / setup from
> > > > > > there (and be available in the clk uclass list).
> > > > > >  
> > > > > > > +
> > > > > > > +       /* Configure ARM PLL to 1.2GHz */
> > > > > > > +       clk_get_by_id(IMX8MM_ARM_PLL, &clkp1);
> > > > > > > +       clk_set_rate(clkp1, 1200000000UL);  
> > > > > >
> > > > > > Shouldn't this be set in DTS ? As it is now - it seems like
> > > > > > a hardcoded value for early SPL clock setup. Am I right?  
> > > > >
> > > > > You mean get freq from cpu opp and set cpu freq? I do not have
> > > > > good idea how to set in DTS.  
> > > >
> > > > I'm thinking about following description of the "osc" fixed
> > > > clock:
> > > > https://elixir.bootlin.com/linux/v5.1/source/arch/arm/boot/dts/imx6q
> > > > dl.dtsi# L64
> > > >
> > > > and
> > > >
> > > >  
> > http://git.denx.de/?p=u-boot/u-boot-imx.git;a=blob;f=arch/arm/dts/imx6qdl.  
> > > > dtsi;h=c0a94780087382a6e2805b7d6572f3e5e294e302;hb=HEAD#l53
> > > >
> > > > The "fixed-clock" code has been adjusted to comply with the
> > > > above DTS (which is provided in pre-reloc SPL - even before
> > > > console and ddr setup).
> > > >
> > > > (I had to use debug uart for debugging).
> > > >  
> > > > >
> > > > > Thanks,
> > > > > Peng.
> > > > >  
> > > > > >  
> > > > > > > +       clk_get_by_id(IMX8MM_ARM_PLL_OUT, &clkp1);
> > > > > > > +       clk_enable(clkp1);
> > > > > > > +       clk_set_parent(clkp, clkp1);
> > > > > > > +
> > > > > > > +       /* Configure DIV to 1.2GHz */
> > > > > > > +       clk_get_by_id(IMX8MM_CLK_A53_DIV, &clkp1);
> > > > > > > +       clk_set_rate(clkp1, 1200000000UL);
> > > > > > >
> > > > > > > Regards,
> > > > > > > Peng.
> > > > > > >  
> > > > > > > >
> > > > > > > >
> > > > > > > > Best regards,
> > > > > > > >
> > > > > > > > Lukasz Majewski
> > > > > > > >
> > > > > > > > --
> > > > > > > >
> > > > > > > > DENX Software Engineering GmbH,      Managing
> > > > > > > > Director:  
> > > > Wolfgang  
> > > > > > > > Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194
> > > > > > > > Groebenzell, Germany Phone: (+49)-8142-66989-59 Fax:
> > > > > > > > (+49)-8142-66989-80 Email: lukma at denx.de  
> > > > > >
> > > > > >
> > > > > >
> > > > > >
> > > > > > Best regards,
> > > > > >
> > > > > > Lukasz Majewski
> > > > > >
> > > > > > --
> > > > > >
> > > > > > DENX Software Engineering GmbH,      Managing Director:  
> > Wolfgang  
> > > > > > Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194
> > > > > > Groebenzell, Germany Phone: (+49)-8142-66989-59 Fax:
> > > > > > (+49)-8142-66989-80 Email: lukma at denx.de  
> > > >
> > > >
> > > >
> > > >
> > > > Best regards,
> > > >
> > > > Lukasz Majewski
> > > >
> > > > --
> > > >
> > > > DENX Software Engineering GmbH,      Managing Director: Wolfgang
> > > > Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194
> > > > Groebenzell, Germany Phone: (+49)-8142-66989-59 Fax:
> > > > (+49)-8142-66989-80 Email: lukma at denx.de  
> > 
> > 
> > 
> > 
> > Best regards,
> > 
> > Lukasz Majewski
> > 
> > --
> > 
> > DENX Software Engineering GmbH,      Managing Director: Wolfgang
> > Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell,
> > Germany Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email:
> > lukma at denx.de  




Best regards,

Lukasz Majewski

--

DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email: lukma at denx.de
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[U-Boot] [i.MX8MM+CCF 11/41] clk: fixed_rate: export clk_fixed_rate

[Peng Fan]

> Subject: Re: [i.MX8MM+CCF 11/41] clk: fixed_rate: export clk_fixed_rate
> 
> On Thu, 9 May 2019 01:13:15 +0000
> Peng Fan <peng.fan@nxp.com> wrote:
> 
> > > Subject: Re: [i.MX8MM+CCF 11/41] clk: fixed_rate: export
> > > clk_fixed_rate
> > >
> > > On Wed, 8 May 2019 07:45:39 +0000
> > > Peng Fan <peng.fan@nxp.com> wrote:
> > >
> > > > > -----Original Message-----
> > > > > From: Lukasz Majewski [mailto:lukma at denx.de]
> > > > > Sent: 2019年5月8日 15:40
> > > > > To: Peng Fan <peng.fan@nxp.com>
> > > > > Cc: sbabic at denx.de; festevam at gmail.com; dl-uboot-imx
> > > > > <uboot-imx@nxp.com>; sjg at chromium.org;
> > > jagan at amarulasolutions.com;
> > > > > sr at denx.de; u-boot at lists.denx.de; trini at konsulko.com
> > > > > Subject: Re: [i.MX8MM+CCF 11/41] clk: fixed_rate: export
> > > > > clk_fixed_rate
> > > > >
> > > > > On Wed, 8 May 2019 06:51:46 +0000 Peng Fan <peng.fan@nxp.com>
> > > > > wrote:
> > > > >
> > > > > > > -----Original Message-----
> > > > > > > From: Lukasz Majewski [mailto:lukma at denx.de]
> > > > > > > Sent: 2019年5月8日 14:46
> > > > > > > To: Peng Fan <peng.fan@nxp.com>
> > > > > > > Cc: sbabic at denx.de; festevam at gmail.com; dl-uboot-imx
> > > > > > > <uboot-imx@nxp.com>; sjg at chromium.org;
> > > > > jagan at amarulasolutions.com;
> > > > > > > sr at denx.de; u-boot at lists.denx.de; trini at konsulko.com
> > > > > > > Subject: Re: [i.MX8MM+CCF 11/41] clk: fixed_rate: export
> > > > > > > clk_fixed_rate
> > > > > > >
> > > > > > > On Tue, 7 May 2019 13:27:45 +0000 Peng Fan
> > > > > > > <peng.fan@nxp.com> wrote:
> > > > > > >
> > > > > > > > > Subject: Re: [i.MX8MM+CCF 11/41] clk: fixed_rate: export
> > > > > > > > > clk_fixed_rate
> > > > > > > > >
> > > > > > > > > Hi Peng,
> > > > > > > > >
> > > > > > > > > > Export the structure for others to use.
> > > > > > > > > >
> > > > > > > > > > Signed-off-by: Peng Fan <peng.fan@nxp.com>
> > > > > > > > > > ---
> > > > > > > > > >  drivers/clk/clk_fixed_rate.c | 8 +-------
> > > > > > > > > > include/linux/clk-provider.h | 7 +++++++
> > > > > > > > > >  2 files changed, 8 insertions(+), 7 deletions(-)
> > > > > > > > > >
> > > > > > > > > > diff --git a/drivers/clk/clk_fixed_rate.c
> > > > > > > > > > b/drivers/clk/clk_fixed_rate.c index
> > > > > > > > > > 089f060a23..069e643fbc 100644 ---
> > > > > > > > > > a/drivers/clk/clk_fixed_rate.c +++
> > > > > > > > > > b/drivers/clk/clk_fixed_rate.c @@ -6,13 +6,7 @@
> > > > > > > > > > #include <common.h>  #include <clk-uclass.h> #include
> > > > > > > > > > <dm.h> - -struct clk_fixed_rate {
> > > > > > > > > > -	struct clk clk;
> > > > > > > > > > -	unsigned long fixed_rate;
> > > > > > > > > > -};
> > > > > > > > > > -
> > > > > > > > > > -#define to_clk_fixed_rate(dev)	((struct
> > > > > > > > > > clk_fixed_rate *)dev_get_platdata(dev)) +#include
> > > > > > > > > > <linux/clk-provider.h>
> > > > > > > > > >
> > > > > > > > > >  static ulong clk_fixed_rate_get_rate(struct clk
> > > > > > > > > > *clk) { diff --git a/include/linux/clk-provider.h
> > > > > > > > > > b/include/linux/clk-provider.h index
> > > > > > > > > > 3ed0db86d2..b2bed768b6 100644 ---
> > > > > > > > > > a/include/linux/clk-provider.h +++
> > > > > > > > > > b/include/linux/clk-provider.h @@ -112,6 +112,13 @@
> > > > > > > > > > struct clk_fixed_factor {  #define
> > > > > > > > > > to_clk_fixed_factor(_clk) container_of(_clk, struct
> > > > > > > > > > clk_fixed_factor,\ clk)
> > > > > > > > > >
> > > > > > > > > > +struct clk_fixed_rate {
> > > > > > > > > > +	struct clk clk;
> > > > > > > > > > +	unsigned long fixed_rate; };
> > > > > > > > >
> > > > > > > > > I think that this struct shall stay where it was.
> > > > > > > > > Moreover, the clk-provider.h is not the API to be used
> > > > > > > > > by other parts of the clock API.
> > > > > > > > >
> > > > > > > > > The clk_fixed_rate shall be accessed via get_rate() only
> > > > > > > > > and in IMX6Q it is available in early SPL (parsed from
> > > > > > > > > dts /clocks property
> > > > > > > > > - the 24MHz OSC)
> > > > > > > > > > +
> > > > > > > > > > +#define to_clk_fixed_rate(dev)	((struct
> > > > > > > > > > clk_fixed_rate *)dev_get_platdata(dev)) +  int
> > > > > > > > > > clk_register(struct clk *clk, const char *drv_name,
> > > > > > > > > >  		 ulong drv_data, const char *name,
> > > > > > > > > >  		 const char *parent_name);
> > > > > > > > >
> > > > > > > > > Please explain why iMX8MM needs such global export?
> > > > > > > >
> > > > > > > > In clk-imx8mm.c, first configure ARM clk to osc24M fixed
> > > > > > > > clk to change pll clock.
> > > > > > > > +       /* Configure ARM to osc24M */
> > > > > > > > +       clk_get_by_id(IMX8MM_CLK_A53_SRC, &clkp);
> > > > > > > > +       uclass_get_device_by_name(UCLASS_CLK,
> > > > > > > > "clock-osc-24m",
> > > > > > > &devp);
> > > > > > > > +       clkp1 = &to_clk_fixed_rate(devp)->clk;
> > > > > > > > +       clk_set_parent(clkp, clkp1);
> > > > > > >
> > > > > > > This code looks a bit strange to me. Why imx8mm sets parent
> > > > > > > here?
> > > > > >
> > > > > > The A53 clk could not change on the fly. There is a mux here,
> > > > > > one is PLL, one is OSC, And there are others. If we want to
> > > > > > change the pll clock which is currently being used by A53, we
> > > > > > need first switch the A53 clk to source from OSC, then change
> > > > > > pll clock, then switch A53 clk back to PLL.
> > > > >
> > > > > The above description looks like a "standard" procedure for
> > > > > bypassing PLL when it is going to be locked.
> > > > >
> > > > > The same is also performed on IMX6Q:
> > > > >
> > > > > https://elixir.bootlin.com/linux/v5.1/source/drivers/clk/imx/clk
> > > > > -imx
> > > > > 6q.c#L88
> > > > >
> > > > > But I've not ported that part from the original Linux source
> > > > > code.
> > > >
> > > > i.MX8MM is different.
> > > >
> > > > This is how Linux change cpu's clock.
> > > > https://elixir.bootlin.com/linux/v5.1/source/drivers/clk/imx/clk-i
> > > > mx8m
> > > > m.c#L655
> > > >
> > > > It has a new cpu clk driver, I do not want to introduce that
> > > > complexity in U-Boot.
> > >
> > > Ok.
> > >
> > > >
> > > > This patch is just a simplified step of the upper Linux code.
> > >
> > > My point is that this driver pollutes the fixed-clock code and makes
> > > it imx8 specific.
> >
> > If i.MX7 switch to CCF, it also has such requirement.
> >
> > I am not sure others, Linux exports
> > grep "to_clk_fix" ./include/linux/clk-provider.h -rn 313:#define
> > to_clk_fixed_rate(_hw) container_of(_hw, struct clk_fixed_rate, hw)
> > 575:#define to_clk_fixed_factor(_hw) container_of(_hw, struct
> > clk_fixed_factor, hw)
> >
> > I think it does not hurt for uboot also export it.
> >
> > >
> > > >
> > > > The reason to configure the clk here is that ROM not configure the
> > > > clock following datasheet even it not hurt, but better to
> > > > configure it right in SPL.
> > >
> > > So this code is for fixing bugs (incomplete initialisation) in SoC's
> > > ROM?
> >
> > Strictly speaking it is not a bug. The datasheet opp has 1.2GHz, but
> > not 1GHz configured by ROM. But actually when power up, the initial
> > freq is 24MHz. Just configure in uboot to follow datasheet and might
> > make Linux kernel happy.
> 
> For IMX6Q there is a table in the User Manual, which describes the state (i.e.
> the clock frequencies of the IP blocks) in which is the board when ROM
> handles the execution to SPL.
> 
> I also assume that 24 MHz Core frequency is too low and will be fixed in next
> ROM (SoC) revisions ?

When power up, before ROM configure PLL, the core will runs at osc clock,
After ROM configures ARM PLL, the core will runs at higher frequency.

It is just ROM not configure ARM PLL following datasheet, but it is not actually
an issue here. U-Boot just following spec to reconfigure the ARM PLL.

Regards,
Peng.

> 
> >
> > Thanks,
> > Peng.
> >
> > >
> > > >
> > > > Thanks,
> > > > Peng.
> > > >
> > > > >
> > > > > >
> > > > > > >
> > > > > > > In the imx6q I write "osc" as a part of the clock tree:
> > > > > > >
> > > > > > >         clk_dm(IMX6QDL_CLK_PLL2,
> > > > > > >                imx_clk_pllv3(IMX_PLLV3_GENERIC,
> "pll2_bus",
> > > > > > > "osc", base + 0x30, 0x1));
> > > > > > >
> > > > > > > And here the parent is set as "osc".
> > > > > > >
> > > > > > > Moreover, the "osc" or in your case "clock-osc-24m" shall be
> > > > > > > available in "clocks" DTS node and hence parsed / setup from
> > > > > > > there (and be available in the clk uclass list).
> > > > > > >
> > > > > > > > +
> > > > > > > > +       /* Configure ARM PLL to 1.2GHz */
> > > > > > > > +       clk_get_by_id(IMX8MM_ARM_PLL, &clkp1);
> > > > > > > > +       clk_set_rate(clkp1, 1200000000UL);
> > > > > > >
> > > > > > > Shouldn't this be set in DTS ? As it is now - it seems like
> > > > > > > a hardcoded value for early SPL clock setup. Am I right?
> > > > > >
> > > > > > You mean get freq from cpu opp and set cpu freq? I do not have
> > > > > > good idea how to set in DTS.
> > > > >
> > > > > I'm thinking about following description of the "osc" fixed
> > > > > clock:
> > > > > https://elixir.bootlin.com/linux/v5.1/source/arch/arm/boot/dts/i
> > > > > mx6q
> > > > > dl.dtsi# L64
> > > > >
> > > > > and
> > > > >
> > > > >
> > >
> http://git.denx.de/?p=u-boot/u-boot-imx.git;a=blob;f=arch/arm/dts/imx6qdl.
> > > > > dtsi;h=c0a94780087382a6e2805b7d6572f3e5e294e302;hb=HEAD#l53
> > > > >
> > > > > The "fixed-clock" code has been adjusted to comply with the
> > > > > above DTS (which is provided in pre-reloc SPL - even before
> > > > > console and ddr setup).
> > > > >
> > > > > (I had to use debug uart for debugging).
> > > > >
> > > > > >
> > > > > > Thanks,
> > > > > > Peng.
> > > > > >
> > > > > > >
> > > > > > > > +       clk_get_by_id(IMX8MM_ARM_PLL_OUT, &clkp1);
> > > > > > > > +       clk_enable(clkp1);
> > > > > > > > +       clk_set_parent(clkp, clkp1);
> > > > > > > > +
> > > > > > > > +       /* Configure DIV to 1.2GHz */
> > > > > > > > +       clk_get_by_id(IMX8MM_CLK_A53_DIV, &clkp1);
> > > > > > > > +       clk_set_rate(clkp1, 1200000000UL);
> > > > > > > >
> > > > > > > > Regards,
> > > > > > > > Peng.
> > > > > > > >
> > > > > > > > >
> > > > > > > > >
> > > > > > > > > Best regards,
> > > > > > > > >
> > > > > > > > > Lukasz Majewski
> > > > > > > > >
> > > > > > > > > --
> > > > > > > > >
> > > > > > > > > DENX Software Engineering GmbH,      Managing
> > > > > > > > > Director:
> > > > > Wolfgang
> > > > > > > > > Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194
> > > > > > > > > Groebenzell, Germany Phone: (+49)-8142-66989-59 Fax:
> > > > > > > > > (+49)-8142-66989-80 Email: lukma at denx.de
> > > > > > >
> > > > > > >
> > > > > > >
> > > > > > >
> > > > > > > Best regards,
> > > > > > >
> > > > > > > Lukasz Majewski
> > > > > > >
> > > > > > > --
> > > > > > >
> > > > > > > DENX Software Engineering GmbH,      Managing Director:
> > > Wolfgang
> > > > > > > Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194
> > > > > > > Groebenzell, Germany Phone: (+49)-8142-66989-59 Fax:
> > > > > > > (+49)-8142-66989-80 Email: lukma at denx.de
> > > > >
> > > > >
> > > > >
> > > > >
> > > > > Best regards,
> > > > >
> > > > > Lukasz Majewski
> > > > >
> > > > > --
> > > > >
> > > > > DENX Software Engineering GmbH,      Managing Director:
> Wolfgang
> > > > > Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194
> > > > > Groebenzell, Germany Phone: (+49)-8142-66989-59 Fax:
> > > > > (+49)-8142-66989-80 Email: lukma at denx.de
> > >
> > >
> > >
> > >
> > > Best regards,
> > >
> > > Lukasz Majewski
> > >
> > > --
> > >
> > > DENX Software Engineering GmbH,      Managing Director: Wolfgang
> > > Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell,
> > > Germany Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email:
> > > lukma at denx.de
> 
> 
> 
> 
> Best regards,
> 
> Lukasz Majewski
> 
> --
> 
> DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
> HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
> Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email:
> lukma at denx.de

[U-Boot] [i.MX8MM+CCF 11/41] clk: fixed_rate: export clk_fixed_rate

[Lukasz Majewski]

On Thu, 16 May 2019 09:58:17 +0000
Peng Fan <peng.fan@nxp.com> wrote:

> > Subject: Re: [i.MX8MM+CCF 11/41] clk: fixed_rate: export
> > clk_fixed_rate
> > 
> > On Thu, 9 May 2019 01:13:15 +0000
> > Peng Fan <peng.fan@nxp.com> wrote:
> >   
> > > > Subject: Re: [i.MX8MM+CCF 11/41] clk: fixed_rate: export
> > > > clk_fixed_rate
> > > >
> > > > On Wed, 8 May 2019 07:45:39 +0000
> > > > Peng Fan <peng.fan@nxp.com> wrote:
> > > >  
> > > > > > -----Original Message-----
> > > > > > From: Lukasz Majewski [mailto:lukma at denx.de]
> > > > > > Sent: 2019年5月8日 15:40
> > > > > > To: Peng Fan <peng.fan@nxp.com>
> > > > > > Cc: sbabic at denx.de; festevam at gmail.com; dl-uboot-imx
> > > > > > <uboot-imx@nxp.com>; sjg at chromium.org;  
> > > > jagan at amarulasolutions.com;  
> > > > > > sr at denx.de; u-boot at lists.denx.de; trini at konsulko.com
> > > > > > Subject: Re: [i.MX8MM+CCF 11/41] clk: fixed_rate: export
> > > > > > clk_fixed_rate
> > > > > >
> > > > > > On Wed, 8 May 2019 06:51:46 +0000 Peng Fan
> > > > > > <peng.fan@nxp.com> wrote:
> > > > > >  
> > > > > > > > -----Original Message-----
> > > > > > > > From: Lukasz Majewski [mailto:lukma at denx.de]
> > > > > > > > Sent: 2019年5月8日 14:46
> > > > > > > > To: Peng Fan <peng.fan@nxp.com>
> > > > > > > > Cc: sbabic at denx.de; festevam at gmail.com; dl-uboot-imx
> > > > > > > > <uboot-imx@nxp.com>; sjg at chromium.org;  
> > > > > > jagan at amarulasolutions.com;  
> > > > > > > > sr at denx.de; u-boot at lists.denx.de; trini at konsulko.com
> > > > > > > > Subject: Re: [i.MX8MM+CCF 11/41] clk: fixed_rate: export
> > > > > > > > clk_fixed_rate
> > > > > > > >
> > > > > > > > On Tue, 7 May 2019 13:27:45 +0000 Peng Fan
> > > > > > > > <peng.fan@nxp.com> wrote:
> > > > > > > >  
> > > > > > > > > > Subject: Re: [i.MX8MM+CCF 11/41] clk: fixed_rate:
> > > > > > > > > > export clk_fixed_rate
> > > > > > > > > >
> > > > > > > > > > Hi Peng,
> > > > > > > > > >  
> > > > > > > > > > > Export the structure for others to use.
> > > > > > > > > > >
> > > > > > > > > > > Signed-off-by: Peng Fan <peng.fan@nxp.com>
> > > > > > > > > > > ---
> > > > > > > > > > >  drivers/clk/clk_fixed_rate.c | 8 +-------
> > > > > > > > > > > include/linux/clk-provider.h | 7 +++++++
> > > > > > > > > > >  2 files changed, 8 insertions(+), 7 deletions(-)
> > > > > > > > > > >
> > > > > > > > > > > diff --git a/drivers/clk/clk_fixed_rate.c
> > > > > > > > > > > b/drivers/clk/clk_fixed_rate.c index
> > > > > > > > > > > 089f060a23..069e643fbc 100644 ---
> > > > > > > > > > > a/drivers/clk/clk_fixed_rate.c +++
> > > > > > > > > > > b/drivers/clk/clk_fixed_rate.c @@ -6,13 +6,7 @@
> > > > > > > > > > > #include <common.h>  #include <clk-uclass.h>
> > > > > > > > > > > #include <dm.h> - -struct clk_fixed_rate {
> > > > > > > > > > > -	struct clk clk;
> > > > > > > > > > > -	unsigned long fixed_rate;
> > > > > > > > > > > -};
> > > > > > > > > > > -
> > > > > > > > > > > -#define to_clk_fixed_rate(dev)	((struct
> > > > > > > > > > > clk_fixed_rate *)dev_get_platdata(dev)) +#include
> > > > > > > > > > > <linux/clk-provider.h>
> > > > > > > > > > >
> > > > > > > > > > >  static ulong clk_fixed_rate_get_rate(struct clk
> > > > > > > > > > > *clk) { diff --git a/include/linux/clk-provider.h
> > > > > > > > > > > b/include/linux/clk-provider.h index
> > > > > > > > > > > 3ed0db86d2..b2bed768b6 100644 ---
> > > > > > > > > > > a/include/linux/clk-provider.h +++
> > > > > > > > > > > b/include/linux/clk-provider.h @@ -112,6 +112,13
> > > > > > > > > > > @@ struct clk_fixed_factor {  #define
> > > > > > > > > > > to_clk_fixed_factor(_clk) container_of(_clk,
> > > > > > > > > > > struct clk_fixed_factor,\ clk)
> > > > > > > > > > >
> > > > > > > > > > > +struct clk_fixed_rate {
> > > > > > > > > > > +	struct clk clk;
> > > > > > > > > > > +	unsigned long fixed_rate; };  
> > > > > > > > > >
> > > > > > > > > > I think that this struct shall stay where it was.
> > > > > > > > > > Moreover, the clk-provider.h is not the API to be
> > > > > > > > > > used by other parts of the clock API.
> > > > > > > > > >
> > > > > > > > > > The clk_fixed_rate shall be accessed via get_rate()
> > > > > > > > > > only and in IMX6Q it is available in early SPL
> > > > > > > > > > (parsed from dts /clocks property
> > > > > > > > > > - the 24MHz OSC)  
> > > > > > > > > > > +
> > > > > > > > > > > +#define to_clk_fixed_rate(dev)	((struct
> > > > > > > > > > > clk_fixed_rate *)dev_get_platdata(dev)) +  int
> > > > > > > > > > > clk_register(struct clk *clk, const char
> > > > > > > > > > > *drv_name, ulong drv_data, const char *name,
> > > > > > > > > > >  		 const char *parent_name);  
> > > > > > > > > >
> > > > > > > > > > Please explain why iMX8MM needs such global
> > > > > > > > > > export?  
> > > > > > > > >
> > > > > > > > > In clk-imx8mm.c, first configure ARM clk to osc24M
> > > > > > > > > fixed clk to change pll clock.
> > > > > > > > > +       /* Configure ARM to osc24M */
> > > > > > > > > +       clk_get_by_id(IMX8MM_CLK_A53_SRC, &clkp);
> > > > > > > > > +       uclass_get_device_by_name(UCLASS_CLK,
> > > > > > > > > "clock-osc-24m",  
> > > > > > > > &devp);  
> > > > > > > > > +       clkp1 = &to_clk_fixed_rate(devp)->clk;
> > > > > > > > > +       clk_set_parent(clkp, clkp1);  
> > > > > > > >
> > > > > > > > This code looks a bit strange to me. Why imx8mm sets
> > > > > > > > parent here?  
> > > > > > >
> > > > > > > The A53 clk could not change on the fly. There is a mux
> > > > > > > here, one is PLL, one is OSC, And there are others. If we
> > > > > > > want to change the pll clock which is currently being
> > > > > > > used by A53, we need first switch the A53 clk to source
> > > > > > > from OSC, then change pll clock, then switch A53 clk back
> > > > > > > to PLL.  
> > > > > >
> > > > > > The above description looks like a "standard" procedure for
> > > > > > bypassing PLL when it is going to be locked.
> > > > > >
> > > > > > The same is also performed on IMX6Q:
> > > > > >
> > > > > > https://elixir.bootlin.com/linux/v5.1/source/drivers/clk/imx/clk
> > > > > > -imx
> > > > > > 6q.c#L88
> > > > > >
> > > > > > But I've not ported that part from the original Linux source
> > > > > > code.  
> > > > >
> > > > > i.MX8MM is different.
> > > > >
> > > > > This is how Linux change cpu's clock.
> > > > > https://elixir.bootlin.com/linux/v5.1/source/drivers/clk/imx/clk-i
> > > > > mx8m
> > > > > m.c#L655
> > > > >
> > > > > It has a new cpu clk driver, I do not want to introduce that
> > > > > complexity in U-Boot.  
> > > >
> > > > Ok.
> > > >  
> > > > >
> > > > > This patch is just a simplified step of the upper Linux
> > > > > code.  
> > > >
> > > > My point is that this driver pollutes the fixed-clock code and
> > > > makes it imx8 specific.  
> > >
> > > If i.MX7 switch to CCF, it also has such requirement.
> > >
> > > I am not sure others, Linux exports
> > > grep "to_clk_fix" ./include/linux/clk-provider.h -rn 313:#define
> > > to_clk_fixed_rate(_hw) container_of(_hw, struct clk_fixed_rate,
> > > hw) 575:#define to_clk_fixed_factor(_hw) container_of(_hw, struct
> > > clk_fixed_factor, hw)
> > >
> > > I think it does not hurt for uboot also export it.
> > >  
> > > >  
> > > > >
> > > > > The reason to configure the clk here is that ROM not
> > > > > configure the clock following datasheet even it not hurt, but
> > > > > better to configure it right in SPL.  
> > > >
> > > > So this code is for fixing bugs (incomplete initialisation) in
> > > > SoC's ROM?  
> > >
> > > Strictly speaking it is not a bug. The datasheet opp has 1.2GHz,
> > > but not 1GHz configured by ROM. But actually when power up, the
> > > initial freq is 24MHz. Just configure in uboot to follow
> > > datasheet and might make Linux kernel happy.  
> > 
> > For IMX6Q there is a table in the User Manual, which describes the
> > state (i.e. the clock frequencies of the IP blocks) in which is the
> > board when ROM handles the execution to SPL.
> > 
> > I also assume that 24 MHz Core frequency is too low and will be
> > fixed in next ROM (SoC) revisions ?  
> 
> When power up, before ROM configure PLL, the core will runs at osc
> clock, After ROM configures ARM PLL, the core will runs at higher
> frequency.
> 
> It is just ROM not configure ARM PLL following datasheet, but it is
> not actually an issue here. U-Boot just following spec to reconfigure
> the ARM PLL.

Ach... OK. I must have misunderstood the last e-mail. The issue is with
difference between 1.2 GHz and 1.0 GHz PLL configuration.

> 
> Regards,
> Peng.
> 
> >   
> > >
> > > Thanks,
> > > Peng.
> > >  
> > > >  
> > > > >
> > > > > Thanks,
> > > > > Peng.
> > > > >  
> > > > > >  
> > > > > > >  
> > > > > > > >
> > > > > > > > In the imx6q I write "osc" as a part of the clock tree:
> > > > > > > >
> > > > > > > >         clk_dm(IMX6QDL_CLK_PLL2,
> > > > > > > >                imx_clk_pllv3(IMX_PLLV3_GENERIC,  
> > "pll2_bus",  
> > > > > > > > "osc", base + 0x30, 0x1));
> > > > > > > >
> > > > > > > > And here the parent is set as "osc".
> > > > > > > >
> > > > > > > > Moreover, the "osc" or in your case "clock-osc-24m"
> > > > > > > > shall be available in "clocks" DTS node and hence
> > > > > > > > parsed / setup from there (and be available in the clk
> > > > > > > > uclass list). 
> > > > > > > > > +
> > > > > > > > > +       /* Configure ARM PLL to 1.2GHz */
> > > > > > > > > +       clk_get_by_id(IMX8MM_ARM_PLL, &clkp1);
> > > > > > > > > +       clk_set_rate(clkp1, 1200000000UL);  
> > > > > > > >
> > > > > > > > Shouldn't this be set in DTS ? As it is now - it seems
> > > > > > > > like a hardcoded value for early SPL clock setup. Am I
> > > > > > > > right?  
> > > > > > >
> > > > > > > You mean get freq from cpu opp and set cpu freq? I do not
> > > > > > > have good idea how to set in DTS.  
> > > > > >
> > > > > > I'm thinking about following description of the "osc" fixed
> > > > > > clock:
> > > > > > https://elixir.bootlin.com/linux/v5.1/source/arch/arm/boot/dts/i
> > > > > > mx6q
> > > > > > dl.dtsi# L64
> > > > > >
> > > > > > and
> > > > > >
> > > > > >  
> > > >  
> > http://git.denx.de/?p=u-boot/u-boot-imx.git;a=blob;f=arch/arm/dts/imx6qdl.  
> > > > > > dtsi;h=c0a94780087382a6e2805b7d6572f3e5e294e302;hb=HEAD#l53
> > > > > >
> > > > > > The "fixed-clock" code has been adjusted to comply with the
> > > > > > above DTS (which is provided in pre-reloc SPL - even before
> > > > > > console and ddr setup).
> > > > > >
> > > > > > (I had to use debug uart for debugging).
> > > > > >  
> > > > > > >
> > > > > > > Thanks,
> > > > > > > Peng.
> > > > > > >  
> > > > > > > >  
> > > > > > > > > +       clk_get_by_id(IMX8MM_ARM_PLL_OUT, &clkp1);
> > > > > > > > > +       clk_enable(clkp1);
> > > > > > > > > +       clk_set_parent(clkp, clkp1);
> > > > > > > > > +
> > > > > > > > > +       /* Configure DIV to 1.2GHz */
> > > > > > > > > +       clk_get_by_id(IMX8MM_CLK_A53_DIV, &clkp1);
> > > > > > > > > +       clk_set_rate(clkp1, 1200000000UL);
> > > > > > > > >
> > > > > > > > > Regards,
> > > > > > > > > Peng.
> > > > > > > > >  
> > > > > > > > > >
> > > > > > > > > >
> > > > > > > > > > Best regards,
> > > > > > > > > >
> > > > > > > > > > Lukasz Majewski
> > > > > > > > > >
> > > > > > > > > > --
> > > > > > > > > >
> > > > > > > > > > DENX Software Engineering GmbH,      Managing
> > > > > > > > > > Director:  
> > > > > > Wolfgang  
> > > > > > > > > > Denk HRB 165235 Munich, Office: Kirchenstr.5,
> > > > > > > > > > D-82194 Groebenzell, Germany Phone:
> > > > > > > > > > (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email:
> > > > > > > > > > lukma at denx.de  
> > > > > > > >
> > > > > > > >
> > > > > > > >
> > > > > > > >
> > > > > > > > Best regards,
> > > > > > > >
> > > > > > > > Lukasz Majewski
> > > > > > > >
> > > > > > > > --
> > > > > > > >
> > > > > > > > DENX Software Engineering GmbH,      Managing
> > > > > > > > Director:  
> > > > Wolfgang  
> > > > > > > > Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194
> > > > > > > > Groebenzell, Germany Phone: (+49)-8142-66989-59 Fax:
> > > > > > > > (+49)-8142-66989-80 Email: lukma at denx.de  
> > > > > >
> > > > > >
> > > > > >
> > > > > >
> > > > > > Best regards,
> > > > > >
> > > > > > Lukasz Majewski
> > > > > >
> > > > > > --
> > > > > >
> > > > > > DENX Software Engineering GmbH,      Managing Director:  
> > Wolfgang  
> > > > > > Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194
> > > > > > Groebenzell, Germany Phone: (+49)-8142-66989-59 Fax:
> > > > > > (+49)-8142-66989-80 Email: lukma at denx.de  
> > > >
> > > >
> > > >
> > > >
> > > > Best regards,
> > > >
> > > > Lukasz Majewski
> > > >
> > > > --
> > > >
> > > > DENX Software Engineering GmbH,      Managing Director: Wolfgang
> > > > Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194
> > > > Groebenzell, Germany Phone: (+49)-8142-66989-59 Fax:
> > > > (+49)-8142-66989-80 Email: lukma at denx.de  
> > 
> > 
> > 
> > 
> > Best regards,
> > 
> > Lukasz Majewski
> > 
> > --
> > 
> > DENX Software Engineering GmbH,      Managing Director: Wolfgang
> > Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell,
> > Germany Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email:
> > lukma at denx.de  




Best regards,

Lukasz Majewski

--

DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email: lukma at denx.de
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